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Commit | Line | Data |
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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx Ethernet switch single-chip support |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
b8fee957 VD |
6 | * Copyright (c) 2015 CMC Electronics, Inc. |
7 | * Added support for VLAN Table Unit operations | |
8 | * | |
14c7b3c3 AL |
9 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
10 | * | |
91da11f8 LB |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
19b2f97e | 17 | #include <linux/delay.h> |
defb05b9 | 18 | #include <linux/etherdevice.h> |
dea87024 | 19 | #include <linux/ethtool.h> |
facd95b2 | 20 | #include <linux/if_bridge.h> |
19b2f97e | 21 | #include <linux/jiffies.h> |
91da11f8 | 22 | #include <linux/list.h> |
14c7b3c3 | 23 | #include <linux/mdio.h> |
2bbba277 | 24 | #include <linux/module.h> |
caac8545 | 25 | #include <linux/of_device.h> |
b516d453 | 26 | #include <linux/of_mdio.h> |
91da11f8 | 27 | #include <linux/netdevice.h> |
c8c1b39a | 28 | #include <linux/gpio/consumer.h> |
91da11f8 | 29 | #include <linux/phy.h> |
c8f0b869 | 30 | #include <net/dsa.h> |
1f36faf2 | 31 | #include <net/switchdev.h> |
91da11f8 LB |
32 | #include "mv88e6xxx.h" |
33 | ||
9f8b3ee1 | 34 | static void assert_reg_lock(struct mv88e6xxx_priv_state *ps) |
3996a4ff | 35 | { |
9f8b3ee1 VD |
36 | if (unlikely(!mutex_is_locked(&ps->reg_lock))) { |
37 | dev_err(ps->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
38 | dump_stack(); |
39 | } | |
40 | } | |
41 | ||
914b32f6 VD |
42 | /* The switch ADDR[4:1] configuration pins define the chip SMI device address |
43 | * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). | |
44 | * | |
45 | * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it | |
46 | * is the only device connected to the SMI master. In this mode it responds to | |
47 | * all 32 possible SMI addresses, and thus maps directly the internal devices. | |
48 | * | |
49 | * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing | |
50 | * multiple devices to share the SMI interface. In this mode it responds to only | |
51 | * 2 registers, used to indirectly access the internal SMI devices. | |
91da11f8 | 52 | */ |
914b32f6 VD |
53 | |
54 | static int mv88e6xxx_smi_read(struct mv88e6xxx_priv_state *ps, | |
55 | int addr, int reg, u16 *val) | |
56 | { | |
57 | if (!ps->smi_ops) | |
58 | return -EOPNOTSUPP; | |
59 | ||
60 | return ps->smi_ops->read(ps, addr, reg, val); | |
61 | } | |
62 | ||
63 | static int mv88e6xxx_smi_write(struct mv88e6xxx_priv_state *ps, | |
64 | int addr, int reg, u16 val) | |
65 | { | |
66 | if (!ps->smi_ops) | |
67 | return -EOPNOTSUPP; | |
68 | ||
69 | return ps->smi_ops->write(ps, addr, reg, val); | |
70 | } | |
71 | ||
72 | static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_priv_state *ps, | |
73 | int addr, int reg, u16 *val) | |
74 | { | |
75 | int ret; | |
76 | ||
77 | ret = mdiobus_read_nested(ps->bus, addr, reg); | |
78 | if (ret < 0) | |
79 | return ret; | |
80 | ||
81 | *val = ret & 0xffff; | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
86 | static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_priv_state *ps, | |
87 | int addr, int reg, u16 val) | |
88 | { | |
89 | int ret; | |
90 | ||
91 | ret = mdiobus_write_nested(ps->bus, addr, reg, val); | |
92 | if (ret < 0) | |
93 | return ret; | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = { | |
99 | .read = mv88e6xxx_smi_single_chip_read, | |
100 | .write = mv88e6xxx_smi_single_chip_write, | |
101 | }; | |
102 | ||
103 | static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_priv_state *ps) | |
91da11f8 LB |
104 | { |
105 | int ret; | |
106 | int i; | |
107 | ||
108 | for (i = 0; i < 16; i++) { | |
914b32f6 | 109 | ret = mdiobus_read_nested(ps->bus, ps->sw_addr, SMI_CMD); |
91da11f8 LB |
110 | if (ret < 0) |
111 | return ret; | |
112 | ||
cca8b133 | 113 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
114 | return 0; |
115 | } | |
116 | ||
117 | return -ETIMEDOUT; | |
118 | } | |
119 | ||
914b32f6 VD |
120 | static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_priv_state *ps, |
121 | int addr, int reg, u16 *val) | |
91da11f8 LB |
122 | { |
123 | int ret; | |
124 | ||
3675c8d7 | 125 | /* Wait for the bus to become free. */ |
914b32f6 | 126 | ret = mv88e6xxx_smi_multi_chip_wait(ps); |
91da11f8 LB |
127 | if (ret < 0) |
128 | return ret; | |
129 | ||
3675c8d7 | 130 | /* Transmit the read command. */ |
914b32f6 | 131 | ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_CMD, |
6e899e6c | 132 | SMI_CMD_OP_22_READ | (addr << 5) | reg); |
91da11f8 LB |
133 | if (ret < 0) |
134 | return ret; | |
135 | ||
3675c8d7 | 136 | /* Wait for the read command to complete. */ |
914b32f6 | 137 | ret = mv88e6xxx_smi_multi_chip_wait(ps); |
91da11f8 LB |
138 | if (ret < 0) |
139 | return ret; | |
140 | ||
3675c8d7 | 141 | /* Read the data. */ |
914b32f6 | 142 | ret = mdiobus_read_nested(ps->bus, ps->sw_addr, SMI_DATA); |
bb92ea5e VD |
143 | if (ret < 0) |
144 | return ret; | |
145 | ||
914b32f6 | 146 | *val = ret & 0xffff; |
91da11f8 | 147 | |
914b32f6 | 148 | return 0; |
8d6d09e7 GR |
149 | } |
150 | ||
914b32f6 VD |
151 | static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_priv_state *ps, |
152 | int addr, int reg, u16 val) | |
91da11f8 LB |
153 | { |
154 | int ret; | |
155 | ||
3675c8d7 | 156 | /* Wait for the bus to become free. */ |
914b32f6 | 157 | ret = mv88e6xxx_smi_multi_chip_wait(ps); |
91da11f8 LB |
158 | if (ret < 0) |
159 | return ret; | |
160 | ||
3675c8d7 | 161 | /* Transmit the data to write. */ |
914b32f6 | 162 | ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_DATA, val); |
91da11f8 LB |
163 | if (ret < 0) |
164 | return ret; | |
165 | ||
3675c8d7 | 166 | /* Transmit the write command. */ |
914b32f6 | 167 | ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_CMD, |
6e899e6c | 168 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); |
91da11f8 LB |
169 | if (ret < 0) |
170 | return ret; | |
171 | ||
3675c8d7 | 172 | /* Wait for the write command to complete. */ |
914b32f6 | 173 | ret = mv88e6xxx_smi_multi_chip_wait(ps); |
91da11f8 LB |
174 | if (ret < 0) |
175 | return ret; | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
914b32f6 VD |
180 | static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = { |
181 | .read = mv88e6xxx_smi_multi_chip_read, | |
182 | .write = mv88e6xxx_smi_multi_chip_write, | |
183 | }; | |
184 | ||
185 | static int mv88e6xxx_read(struct mv88e6xxx_priv_state *ps, | |
186 | int addr, int reg, u16 *val) | |
187 | { | |
188 | int err; | |
189 | ||
190 | assert_reg_lock(ps); | |
191 | ||
192 | err = mv88e6xxx_smi_read(ps, addr, reg, val); | |
193 | if (err) | |
194 | return err; | |
195 | ||
196 | dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
197 | addr, reg, *val); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | static int mv88e6xxx_write(struct mv88e6xxx_priv_state *ps, | |
203 | int addr, int reg, u16 val) | |
91da11f8 | 204 | { |
914b32f6 VD |
205 | int err; |
206 | ||
9f8b3ee1 | 207 | assert_reg_lock(ps); |
91da11f8 | 208 | |
914b32f6 VD |
209 | err = mv88e6xxx_smi_write(ps, addr, reg, val); |
210 | if (err) | |
211 | return err; | |
212 | ||
158bc065 | 213 | dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
214 | addr, reg, val); |
215 | ||
914b32f6 VD |
216 | return 0; |
217 | } | |
218 | ||
219 | static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, | |
220 | int addr, int reg) | |
221 | { | |
222 | u16 val; | |
223 | int err; | |
224 | ||
225 | err = mv88e6xxx_read(ps, addr, reg, &val); | |
226 | if (err) | |
227 | return err; | |
228 | ||
229 | return val; | |
230 | } | |
231 | ||
232 | static int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, | |
233 | int reg) | |
234 | { | |
235 | int ret; | |
236 | ||
237 | mutex_lock(&ps->reg_lock); | |
238 | ret = _mv88e6xxx_reg_read(ps, addr, reg); | |
239 | mutex_unlock(&ps->reg_lock); | |
240 | ||
241 | return ret; | |
242 | } | |
243 | ||
244 | static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, | |
245 | int reg, u16 val) | |
246 | { | |
247 | return mv88e6xxx_write(ps, addr, reg, val); | |
8d6d09e7 GR |
248 | } |
249 | ||
57d32310 VD |
250 | static int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, |
251 | int reg, u16 val) | |
8d6d09e7 | 252 | { |
8d6d09e7 GR |
253 | int ret; |
254 | ||
9f8b3ee1 | 255 | mutex_lock(&ps->reg_lock); |
158bc065 | 256 | ret = _mv88e6xxx_reg_write(ps, addr, reg, val); |
9f8b3ee1 | 257 | mutex_unlock(&ps->reg_lock); |
91da11f8 LB |
258 | |
259 | return ret; | |
260 | } | |
261 | ||
1d13a06e | 262 | static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
2e5f0320 | 263 | { |
158bc065 | 264 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
48ace4ef | 265 | int err; |
2e5f0320 | 266 | |
158bc065 | 267 | err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01, |
48ace4ef AL |
268 | (addr[0] << 8) | addr[1]); |
269 | if (err) | |
270 | return err; | |
271 | ||
158bc065 | 272 | err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23, |
48ace4ef AL |
273 | (addr[2] << 8) | addr[3]); |
274 | if (err) | |
275 | return err; | |
276 | ||
158bc065 | 277 | return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45, |
48ace4ef | 278 | (addr[4] << 8) | addr[5]); |
2e5f0320 LB |
279 | } |
280 | ||
1d13a06e | 281 | static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
91da11f8 | 282 | { |
158bc065 | 283 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 | 284 | int ret; |
48ace4ef | 285 | int i; |
91da11f8 LB |
286 | |
287 | for (i = 0; i < 6; i++) { | |
288 | int j; | |
289 | ||
3675c8d7 | 290 | /* Write the MAC address byte. */ |
158bc065 | 291 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
48ace4ef AL |
292 | GLOBAL2_SWITCH_MAC_BUSY | |
293 | (i << 8) | addr[i]); | |
294 | if (ret) | |
295 | return ret; | |
91da11f8 | 296 | |
3675c8d7 | 297 | /* Wait for the write to complete. */ |
91da11f8 | 298 | for (j = 0; j < 16; j++) { |
158bc065 | 299 | ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, |
48ace4ef AL |
300 | GLOBAL2_SWITCH_MAC); |
301 | if (ret < 0) | |
302 | return ret; | |
303 | ||
cca8b133 | 304 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) |
91da11f8 LB |
305 | break; |
306 | } | |
307 | if (j == 16) | |
308 | return -ETIMEDOUT; | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
57d32310 | 314 | static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) |
1d13a06e VD |
315 | { |
316 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
317 | ||
318 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC)) | |
319 | return mv88e6xxx_set_addr_indirect(ds, addr); | |
320 | else | |
321 | return mv88e6xxx_set_addr_direct(ds, addr); | |
322 | } | |
323 | ||
03a4a540 AL |
324 | static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_priv_state *ps, |
325 | int addr, int regnum) | |
91da11f8 LB |
326 | { |
327 | if (addr >= 0) | |
158bc065 | 328 | return _mv88e6xxx_reg_read(ps, addr, regnum); |
91da11f8 LB |
329 | return 0xffff; |
330 | } | |
331 | ||
03a4a540 AL |
332 | static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_priv_state *ps, |
333 | int addr, int regnum, u16 val) | |
91da11f8 LB |
334 | { |
335 | if (addr >= 0) | |
158bc065 | 336 | return _mv88e6xxx_reg_write(ps, addr, regnum, val); |
91da11f8 LB |
337 | return 0; |
338 | } | |
339 | ||
158bc065 | 340 | static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps) |
2e5f0320 LB |
341 | { |
342 | int ret; | |
19b2f97e | 343 | unsigned long timeout; |
2e5f0320 | 344 | |
8c9983a2 | 345 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); |
48ace4ef AL |
346 | if (ret < 0) |
347 | return ret; | |
348 | ||
8c9983a2 VD |
349 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, |
350 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
48ace4ef AL |
351 | if (ret) |
352 | return ret; | |
2e5f0320 | 353 | |
19b2f97e BG |
354 | timeout = jiffies + 1 * HZ; |
355 | while (time_before(jiffies, timeout)) { | |
8c9983a2 | 356 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); |
48ace4ef AL |
357 | if (ret < 0) |
358 | return ret; | |
359 | ||
19b2f97e | 360 | usleep_range(1000, 2000); |
cca8b133 AL |
361 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
362 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 363 | return 0; |
2e5f0320 LB |
364 | } |
365 | ||
366 | return -ETIMEDOUT; | |
367 | } | |
368 | ||
158bc065 | 369 | static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps) |
2e5f0320 | 370 | { |
48ace4ef | 371 | int ret, err; |
19b2f97e | 372 | unsigned long timeout; |
2e5f0320 | 373 | |
762eb67b | 374 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); |
48ace4ef AL |
375 | if (ret < 0) |
376 | return ret; | |
377 | ||
762eb67b VD |
378 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, |
379 | ret | GLOBAL_CONTROL_PPU_ENABLE); | |
48ace4ef AL |
380 | if (err) |
381 | return err; | |
2e5f0320 | 382 | |
19b2f97e BG |
383 | timeout = jiffies + 1 * HZ; |
384 | while (time_before(jiffies, timeout)) { | |
762eb67b | 385 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); |
48ace4ef AL |
386 | if (ret < 0) |
387 | return ret; | |
388 | ||
19b2f97e | 389 | usleep_range(1000, 2000); |
cca8b133 AL |
390 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
391 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 392 | return 0; |
2e5f0320 LB |
393 | } |
394 | ||
395 | return -ETIMEDOUT; | |
396 | } | |
397 | ||
398 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
399 | { | |
400 | struct mv88e6xxx_priv_state *ps; | |
401 | ||
402 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
762eb67b | 403 | |
9f8b3ee1 | 404 | mutex_lock(&ps->reg_lock); |
762eb67b | 405 | |
2e5f0320 | 406 | if (mutex_trylock(&ps->ppu_mutex)) { |
158bc065 | 407 | if (mv88e6xxx_ppu_enable(ps) == 0) |
85686581 BG |
408 | ps->ppu_disabled = 0; |
409 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 | 410 | } |
762eb67b | 411 | |
9f8b3ee1 | 412 | mutex_unlock(&ps->reg_lock); |
2e5f0320 LB |
413 | } |
414 | ||
415 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
416 | { | |
417 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
418 | ||
419 | schedule_work(&ps->ppu_work); | |
420 | } | |
421 | ||
158bc065 | 422 | static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps) |
2e5f0320 | 423 | { |
2e5f0320 LB |
424 | int ret; |
425 | ||
426 | mutex_lock(&ps->ppu_mutex); | |
427 | ||
3675c8d7 | 428 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
429 | * we can access the PHY registers. If it was already |
430 | * disabled, cancel the timer that is going to re-enable | |
431 | * it. | |
432 | */ | |
433 | if (!ps->ppu_disabled) { | |
158bc065 | 434 | ret = mv88e6xxx_ppu_disable(ps); |
85686581 BG |
435 | if (ret < 0) { |
436 | mutex_unlock(&ps->ppu_mutex); | |
437 | return ret; | |
438 | } | |
439 | ps->ppu_disabled = 1; | |
2e5f0320 | 440 | } else { |
85686581 BG |
441 | del_timer(&ps->ppu_timer); |
442 | ret = 0; | |
2e5f0320 LB |
443 | } |
444 | ||
445 | return ret; | |
446 | } | |
447 | ||
158bc065 | 448 | static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps) |
2e5f0320 | 449 | { |
3675c8d7 | 450 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
451 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
452 | mutex_unlock(&ps->ppu_mutex); | |
453 | } | |
454 | ||
57d32310 | 455 | static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps) |
2e5f0320 | 456 | { |
2e5f0320 LB |
457 | mutex_init(&ps->ppu_mutex); |
458 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
459 | init_timer(&ps->ppu_timer); | |
460 | ps->ppu_timer.data = (unsigned long)ps; | |
461 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
462 | } | |
463 | ||
03a4a540 AL |
464 | static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_priv_state *ps, int addr, |
465 | int regnum) | |
2e5f0320 LB |
466 | { |
467 | int ret; | |
468 | ||
158bc065 | 469 | ret = mv88e6xxx_ppu_access_get(ps); |
2e5f0320 | 470 | if (ret >= 0) { |
8c9983a2 | 471 | ret = _mv88e6xxx_reg_read(ps, addr, regnum); |
158bc065 | 472 | mv88e6xxx_ppu_access_put(ps); |
2e5f0320 LB |
473 | } |
474 | ||
475 | return ret; | |
476 | } | |
477 | ||
03a4a540 AL |
478 | static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_priv_state *ps, int addr, |
479 | int regnum, u16 val) | |
2e5f0320 LB |
480 | { |
481 | int ret; | |
482 | ||
158bc065 | 483 | ret = mv88e6xxx_ppu_access_get(ps); |
2e5f0320 | 484 | if (ret >= 0) { |
8c9983a2 | 485 | ret = _mv88e6xxx_reg_write(ps, addr, regnum, val); |
158bc065 | 486 | mv88e6xxx_ppu_access_put(ps); |
2e5f0320 LB |
487 | } |
488 | ||
489 | return ret; | |
490 | } | |
2e5f0320 | 491 | |
158bc065 | 492 | static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 493 | { |
22356476 | 494 | return ps->info->family == MV88E6XXX_FAMILY_6065; |
54d792f2 AL |
495 | } |
496 | ||
158bc065 | 497 | static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 498 | { |
22356476 | 499 | return ps->info->family == MV88E6XXX_FAMILY_6095; |
54d792f2 AL |
500 | } |
501 | ||
158bc065 | 502 | static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 503 | { |
22356476 | 504 | return ps->info->family == MV88E6XXX_FAMILY_6097; |
54d792f2 AL |
505 | } |
506 | ||
158bc065 | 507 | static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 508 | { |
22356476 | 509 | return ps->info->family == MV88E6XXX_FAMILY_6165; |
54d792f2 AL |
510 | } |
511 | ||
158bc065 | 512 | static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 513 | { |
22356476 | 514 | return ps->info->family == MV88E6XXX_FAMILY_6185; |
54d792f2 AL |
515 | } |
516 | ||
158bc065 | 517 | static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps) |
7c3d0d67 | 518 | { |
22356476 | 519 | return ps->info->family == MV88E6XXX_FAMILY_6320; |
7c3d0d67 AK |
520 | } |
521 | ||
158bc065 | 522 | static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps) |
54d792f2 | 523 | { |
22356476 | 524 | return ps->info->family == MV88E6XXX_FAMILY_6351; |
54d792f2 AL |
525 | } |
526 | ||
158bc065 | 527 | static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps) |
f3a8b6b6 | 528 | { |
22356476 | 529 | return ps->info->family == MV88E6XXX_FAMILY_6352; |
f3a8b6b6 AL |
530 | } |
531 | ||
158bc065 | 532 | static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps) |
f74df0be | 533 | { |
cd5a2c82 | 534 | return ps->info->num_databases; |
f74df0be VD |
535 | } |
536 | ||
158bc065 | 537 | static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps) |
b426e5f7 VD |
538 | { |
539 | /* Does the device have dedicated FID registers for ATU and VTU ops? */ | |
158bc065 AL |
540 | if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || |
541 | mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) | |
b426e5f7 VD |
542 | return true; |
543 | ||
544 | return false; | |
545 | } | |
546 | ||
dea87024 AL |
547 | /* We expect the switch to perform auto negotiation if there is a real |
548 | * phy. However, in the case of a fixed link phy, we force the port | |
549 | * settings from the fixed link settings. | |
550 | */ | |
f81ec90f VD |
551 | static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
552 | struct phy_device *phydev) | |
dea87024 AL |
553 | { |
554 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
49052871 AL |
555 | u32 reg; |
556 | int ret; | |
dea87024 AL |
557 | |
558 | if (!phy_is_pseudo_fixed_link(phydev)) | |
559 | return; | |
560 | ||
9f8b3ee1 | 561 | mutex_lock(&ps->reg_lock); |
dea87024 | 562 | |
158bc065 | 563 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); |
dea87024 AL |
564 | if (ret < 0) |
565 | goto out; | |
566 | ||
567 | reg = ret & ~(PORT_PCS_CTRL_LINK_UP | | |
568 | PORT_PCS_CTRL_FORCE_LINK | | |
569 | PORT_PCS_CTRL_DUPLEX_FULL | | |
570 | PORT_PCS_CTRL_FORCE_DUPLEX | | |
571 | PORT_PCS_CTRL_UNFORCED); | |
572 | ||
573 | reg |= PORT_PCS_CTRL_FORCE_LINK; | |
574 | if (phydev->link) | |
57d32310 | 575 | reg |= PORT_PCS_CTRL_LINK_UP; |
dea87024 | 576 | |
158bc065 | 577 | if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100) |
dea87024 AL |
578 | goto out; |
579 | ||
580 | switch (phydev->speed) { | |
581 | case SPEED_1000: | |
582 | reg |= PORT_PCS_CTRL_1000; | |
583 | break; | |
584 | case SPEED_100: | |
585 | reg |= PORT_PCS_CTRL_100; | |
586 | break; | |
587 | case SPEED_10: | |
588 | reg |= PORT_PCS_CTRL_10; | |
589 | break; | |
590 | default: | |
591 | pr_info("Unknown speed"); | |
592 | goto out; | |
593 | } | |
594 | ||
595 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; | |
596 | if (phydev->duplex == DUPLEX_FULL) | |
597 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; | |
598 | ||
158bc065 | 599 | if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) && |
009a2b98 | 600 | (port >= ps->info->num_ports - 2)) { |
e7e72ac0 AL |
601 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
602 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; | |
603 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
604 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; | |
605 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
606 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | | |
607 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); | |
608 | } | |
158bc065 | 609 | _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg); |
dea87024 AL |
610 | |
611 | out: | |
9f8b3ee1 | 612 | mutex_unlock(&ps->reg_lock); |
dea87024 AL |
613 | } |
614 | ||
158bc065 | 615 | static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps) |
91da11f8 LB |
616 | { |
617 | int ret; | |
618 | int i; | |
619 | ||
620 | for (i = 0; i < 10; i++) { | |
158bc065 | 621 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 622 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
623 | return 0; |
624 | } | |
625 | ||
626 | return -ETIMEDOUT; | |
627 | } | |
628 | ||
158bc065 AL |
629 | static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps, |
630 | int port) | |
91da11f8 LB |
631 | { |
632 | int ret; | |
633 | ||
158bc065 | 634 | if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) |
f3a8b6b6 AL |
635 | port = (port + 1) << 5; |
636 | ||
3675c8d7 | 637 | /* Snapshot the hardware statistics counters for this port. */ |
158bc065 | 638 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, |
31888234 AL |
639 | GLOBAL_STATS_OP_CAPTURE_PORT | |
640 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
641 | if (ret < 0) | |
642 | return ret; | |
91da11f8 | 643 | |
3675c8d7 | 644 | /* Wait for the snapshotting to complete. */ |
158bc065 | 645 | ret = _mv88e6xxx_stats_wait(ps); |
91da11f8 LB |
646 | if (ret < 0) |
647 | return ret; | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
158bc065 AL |
652 | static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps, |
653 | int stat, u32 *val) | |
91da11f8 LB |
654 | { |
655 | u32 _val; | |
656 | int ret; | |
657 | ||
658 | *val = 0; | |
659 | ||
158bc065 | 660 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, |
31888234 AL |
661 | GLOBAL_STATS_OP_READ_CAPTURED | |
662 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
663 | if (ret < 0) |
664 | return; | |
665 | ||
158bc065 | 666 | ret = _mv88e6xxx_stats_wait(ps); |
91da11f8 LB |
667 | if (ret < 0) |
668 | return; | |
669 | ||
158bc065 | 670 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
671 | if (ret < 0) |
672 | return; | |
673 | ||
674 | _val = ret << 16; | |
675 | ||
158bc065 | 676 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
677 | if (ret < 0) |
678 | return; | |
679 | ||
680 | *val = _val | ret; | |
681 | } | |
682 | ||
e413e7e1 | 683 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
f5e2ed02 AL |
684 | { "in_good_octets", 8, 0x00, BANK0, }, |
685 | { "in_bad_octets", 4, 0x02, BANK0, }, | |
686 | { "in_unicast", 4, 0x04, BANK0, }, | |
687 | { "in_broadcasts", 4, 0x06, BANK0, }, | |
688 | { "in_multicasts", 4, 0x07, BANK0, }, | |
689 | { "in_pause", 4, 0x16, BANK0, }, | |
690 | { "in_undersize", 4, 0x18, BANK0, }, | |
691 | { "in_fragments", 4, 0x19, BANK0, }, | |
692 | { "in_oversize", 4, 0x1a, BANK0, }, | |
693 | { "in_jabber", 4, 0x1b, BANK0, }, | |
694 | { "in_rx_error", 4, 0x1c, BANK0, }, | |
695 | { "in_fcs_error", 4, 0x1d, BANK0, }, | |
696 | { "out_octets", 8, 0x0e, BANK0, }, | |
697 | { "out_unicast", 4, 0x10, BANK0, }, | |
698 | { "out_broadcasts", 4, 0x13, BANK0, }, | |
699 | { "out_multicasts", 4, 0x12, BANK0, }, | |
700 | { "out_pause", 4, 0x15, BANK0, }, | |
701 | { "excessive", 4, 0x11, BANK0, }, | |
702 | { "collisions", 4, 0x1e, BANK0, }, | |
703 | { "deferred", 4, 0x05, BANK0, }, | |
704 | { "single", 4, 0x14, BANK0, }, | |
705 | { "multiple", 4, 0x17, BANK0, }, | |
706 | { "out_fcs_error", 4, 0x03, BANK0, }, | |
707 | { "late", 4, 0x1f, BANK0, }, | |
708 | { "hist_64bytes", 4, 0x08, BANK0, }, | |
709 | { "hist_65_127bytes", 4, 0x09, BANK0, }, | |
710 | { "hist_128_255bytes", 4, 0x0a, BANK0, }, | |
711 | { "hist_256_511bytes", 4, 0x0b, BANK0, }, | |
712 | { "hist_512_1023bytes", 4, 0x0c, BANK0, }, | |
713 | { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, | |
714 | { "sw_in_discards", 4, 0x10, PORT, }, | |
715 | { "sw_in_filtered", 2, 0x12, PORT, }, | |
716 | { "sw_out_filtered", 2, 0x13, PORT, }, | |
717 | { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
718 | { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
719 | { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
720 | { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
721 | { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
722 | { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
723 | { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
724 | { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
725 | { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
726 | { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
727 | { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
728 | { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
729 | { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
730 | { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
731 | { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
732 | { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
733 | { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
734 | { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
735 | { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
736 | { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
737 | { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
738 | { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
739 | { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
740 | { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
741 | { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
742 | { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, | |
e413e7e1 AL |
743 | }; |
744 | ||
158bc065 | 745 | static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps, |
f5e2ed02 | 746 | struct mv88e6xxx_hw_stat *stat) |
e413e7e1 | 747 | { |
f5e2ed02 AL |
748 | switch (stat->type) { |
749 | case BANK0: | |
e413e7e1 | 750 | return true; |
f5e2ed02 | 751 | case BANK1: |
158bc065 | 752 | return mv88e6xxx_6320_family(ps); |
f5e2ed02 | 753 | case PORT: |
158bc065 AL |
754 | return mv88e6xxx_6095_family(ps) || |
755 | mv88e6xxx_6185_family(ps) || | |
756 | mv88e6xxx_6097_family(ps) || | |
757 | mv88e6xxx_6165_family(ps) || | |
758 | mv88e6xxx_6351_family(ps) || | |
759 | mv88e6xxx_6352_family(ps); | |
91da11f8 | 760 | } |
f5e2ed02 | 761 | return false; |
91da11f8 LB |
762 | } |
763 | ||
158bc065 | 764 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps, |
f5e2ed02 | 765 | struct mv88e6xxx_hw_stat *s, |
80c4627b AL |
766 | int port) |
767 | { | |
80c4627b AL |
768 | u32 low; |
769 | u32 high = 0; | |
770 | int ret; | |
771 | u64 value; | |
772 | ||
f5e2ed02 AL |
773 | switch (s->type) { |
774 | case PORT: | |
158bc065 | 775 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg); |
80c4627b AL |
776 | if (ret < 0) |
777 | return UINT64_MAX; | |
778 | ||
779 | low = ret; | |
780 | if (s->sizeof_stat == 4) { | |
158bc065 | 781 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), |
f5e2ed02 | 782 | s->reg + 1); |
80c4627b AL |
783 | if (ret < 0) |
784 | return UINT64_MAX; | |
785 | high = ret; | |
786 | } | |
f5e2ed02 AL |
787 | break; |
788 | case BANK0: | |
789 | case BANK1: | |
158bc065 | 790 | _mv88e6xxx_stats_read(ps, s->reg, &low); |
80c4627b | 791 | if (s->sizeof_stat == 8) |
158bc065 | 792 | _mv88e6xxx_stats_read(ps, s->reg + 1, &high); |
80c4627b AL |
793 | } |
794 | value = (((u64)high) << 16) | low; | |
795 | return value; | |
796 | } | |
797 | ||
f81ec90f VD |
798 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
799 | uint8_t *data) | |
91da11f8 | 800 | { |
158bc065 | 801 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
f5e2ed02 AL |
802 | struct mv88e6xxx_hw_stat *stat; |
803 | int i, j; | |
91da11f8 | 804 | |
f5e2ed02 AL |
805 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
806 | stat = &mv88e6xxx_hw_stats[i]; | |
158bc065 | 807 | if (mv88e6xxx_has_stat(ps, stat)) { |
f5e2ed02 AL |
808 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
809 | ETH_GSTRING_LEN); | |
810 | j++; | |
811 | } | |
91da11f8 | 812 | } |
e413e7e1 AL |
813 | } |
814 | ||
f81ec90f | 815 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) |
e413e7e1 | 816 | { |
158bc065 | 817 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
f5e2ed02 AL |
818 | struct mv88e6xxx_hw_stat *stat; |
819 | int i, j; | |
820 | ||
821 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
822 | stat = &mv88e6xxx_hw_stats[i]; | |
158bc065 | 823 | if (mv88e6xxx_has_stat(ps, stat)) |
f5e2ed02 AL |
824 | j++; |
825 | } | |
826 | return j; | |
e413e7e1 AL |
827 | } |
828 | ||
f81ec90f VD |
829 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
830 | uint64_t *data) | |
e413e7e1 | 831 | { |
f5e2ed02 AL |
832 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
833 | struct mv88e6xxx_hw_stat *stat; | |
834 | int ret; | |
835 | int i, j; | |
836 | ||
9f8b3ee1 | 837 | mutex_lock(&ps->reg_lock); |
f5e2ed02 | 838 | |
158bc065 | 839 | ret = _mv88e6xxx_stats_snapshot(ps, port); |
f5e2ed02 | 840 | if (ret < 0) { |
9f8b3ee1 | 841 | mutex_unlock(&ps->reg_lock); |
f5e2ed02 AL |
842 | return; |
843 | } | |
844 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
845 | stat = &mv88e6xxx_hw_stats[i]; | |
158bc065 AL |
846 | if (mv88e6xxx_has_stat(ps, stat)) { |
847 | data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port); | |
f5e2ed02 AL |
848 | j++; |
849 | } | |
850 | } | |
851 | ||
9f8b3ee1 | 852 | mutex_unlock(&ps->reg_lock); |
e413e7e1 AL |
853 | } |
854 | ||
f81ec90f | 855 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 GR |
856 | { |
857 | return 32 * sizeof(u16); | |
858 | } | |
859 | ||
f81ec90f VD |
860 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
861 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 862 | { |
158bc065 | 863 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
a1ab91f3 GR |
864 | u16 *p = _p; |
865 | int i; | |
866 | ||
867 | regs->version = 0; | |
868 | ||
869 | memset(p, 0xff, 32 * sizeof(u16)); | |
870 | ||
9f8b3ee1 | 871 | mutex_lock(&ps->reg_lock); |
23062513 | 872 | |
a1ab91f3 GR |
873 | for (i = 0; i < 32; i++) { |
874 | int ret; | |
875 | ||
23062513 | 876 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i); |
a1ab91f3 GR |
877 | if (ret >= 0) |
878 | p[i] = ret; | |
879 | } | |
23062513 | 880 | |
9f8b3ee1 | 881 | mutex_unlock(&ps->reg_lock); |
a1ab91f3 GR |
882 | } |
883 | ||
158bc065 | 884 | static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset, |
3898c148 | 885 | u16 mask) |
f3044683 AL |
886 | { |
887 | unsigned long timeout = jiffies + HZ / 10; | |
888 | ||
889 | while (time_before(jiffies, timeout)) { | |
890 | int ret; | |
891 | ||
158bc065 | 892 | ret = _mv88e6xxx_reg_read(ps, reg, offset); |
3898c148 AL |
893 | if (ret < 0) |
894 | return ret; | |
f3044683 AL |
895 | if (!(ret & mask)) |
896 | return 0; | |
897 | ||
898 | usleep_range(1000, 2000); | |
899 | } | |
900 | return -ETIMEDOUT; | |
901 | } | |
902 | ||
158bc065 AL |
903 | static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, |
904 | int offset, u16 mask) | |
3898c148 | 905 | { |
3898c148 AL |
906 | int ret; |
907 | ||
9f8b3ee1 | 908 | mutex_lock(&ps->reg_lock); |
158bc065 | 909 | ret = _mv88e6xxx_wait(ps, reg, offset, mask); |
9f8b3ee1 | 910 | mutex_unlock(&ps->reg_lock); |
3898c148 AL |
911 | |
912 | return ret; | |
913 | } | |
914 | ||
03a4a540 | 915 | static int mv88e6xxx_mdio_wait(struct mv88e6xxx_priv_state *ps) |
f3044683 | 916 | { |
158bc065 | 917 | return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, |
3898c148 | 918 | GLOBAL2_SMI_OP_BUSY); |
f3044683 AL |
919 | } |
920 | ||
d24645be | 921 | static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) |
f3044683 | 922 | { |
158bc065 AL |
923 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
924 | ||
925 | return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, | |
cca8b133 | 926 | GLOBAL2_EEPROM_OP_LOAD); |
f3044683 AL |
927 | } |
928 | ||
d24645be | 929 | static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) |
f3044683 | 930 | { |
158bc065 AL |
931 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
932 | ||
933 | return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, | |
cca8b133 | 934 | GLOBAL2_EEPROM_OP_BUSY); |
f3044683 AL |
935 | } |
936 | ||
d24645be VD |
937 | static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr) |
938 | { | |
939 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
940 | int ret; | |
941 | ||
942 | mutex_lock(&ps->eeprom_mutex); | |
943 | ||
944 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, | |
945 | GLOBAL2_EEPROM_OP_READ | | |
946 | (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); | |
947 | if (ret < 0) | |
948 | goto error; | |
949 | ||
950 | ret = mv88e6xxx_eeprom_busy_wait(ds); | |
951 | if (ret < 0) | |
952 | goto error; | |
953 | ||
954 | ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA); | |
955 | error: | |
956 | mutex_unlock(&ps->eeprom_mutex); | |
957 | return ret; | |
958 | } | |
959 | ||
f8cd8753 AL |
960 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
961 | { | |
962 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
963 | ||
964 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) | |
965 | return ps->eeprom_len; | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
f81ec90f VD |
970 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
971 | struct ethtool_eeprom *eeprom, u8 *data) | |
d24645be VD |
972 | { |
973 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
974 | int offset; | |
975 | int len; | |
976 | int ret; | |
977 | ||
978 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) | |
979 | return -EOPNOTSUPP; | |
980 | ||
981 | offset = eeprom->offset; | |
982 | len = eeprom->len; | |
983 | eeprom->len = 0; | |
984 | ||
985 | eeprom->magic = 0xc3ec4951; | |
986 | ||
987 | ret = mv88e6xxx_eeprom_load_wait(ds); | |
988 | if (ret < 0) | |
989 | return ret; | |
990 | ||
991 | if (offset & 1) { | |
992 | int word; | |
993 | ||
994 | word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); | |
995 | if (word < 0) | |
996 | return word; | |
997 | ||
998 | *data++ = (word >> 8) & 0xff; | |
999 | ||
1000 | offset++; | |
1001 | len--; | |
1002 | eeprom->len++; | |
1003 | } | |
1004 | ||
1005 | while (len >= 2) { | |
1006 | int word; | |
1007 | ||
1008 | word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); | |
1009 | if (word < 0) | |
1010 | return word; | |
1011 | ||
1012 | *data++ = word & 0xff; | |
1013 | *data++ = (word >> 8) & 0xff; | |
1014 | ||
1015 | offset += 2; | |
1016 | len -= 2; | |
1017 | eeprom->len += 2; | |
1018 | } | |
1019 | ||
1020 | if (len) { | |
1021 | int word; | |
1022 | ||
1023 | word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); | |
1024 | if (word < 0) | |
1025 | return word; | |
1026 | ||
1027 | *data++ = word & 0xff; | |
1028 | ||
1029 | offset++; | |
1030 | len--; | |
1031 | eeprom->len++; | |
1032 | } | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds) | |
1038 | { | |
1039 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1040 | int ret; | |
1041 | ||
1042 | ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP); | |
1043 | if (ret < 0) | |
1044 | return ret; | |
1045 | ||
1046 | if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN)) | |
1047 | return -EROFS; | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr, | |
1053 | u16 data) | |
1054 | { | |
1055 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1056 | int ret; | |
1057 | ||
1058 | mutex_lock(&ps->eeprom_mutex); | |
1059 | ||
1060 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); | |
1061 | if (ret < 0) | |
1062 | goto error; | |
1063 | ||
1064 | ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, | |
1065 | GLOBAL2_EEPROM_OP_WRITE | | |
1066 | (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); | |
1067 | if (ret < 0) | |
1068 | goto error; | |
1069 | ||
1070 | ret = mv88e6xxx_eeprom_busy_wait(ds); | |
1071 | error: | |
1072 | mutex_unlock(&ps->eeprom_mutex); | |
1073 | return ret; | |
1074 | } | |
1075 | ||
f81ec90f VD |
1076 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
1077 | struct ethtool_eeprom *eeprom, u8 *data) | |
d24645be VD |
1078 | { |
1079 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1080 | int offset; | |
1081 | int ret; | |
1082 | int len; | |
1083 | ||
1084 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) | |
1085 | return -EOPNOTSUPP; | |
1086 | ||
1087 | if (eeprom->magic != 0xc3ec4951) | |
1088 | return -EINVAL; | |
1089 | ||
1090 | ret = mv88e6xxx_eeprom_is_readonly(ds); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | ||
1094 | offset = eeprom->offset; | |
1095 | len = eeprom->len; | |
1096 | eeprom->len = 0; | |
1097 | ||
1098 | ret = mv88e6xxx_eeprom_load_wait(ds); | |
1099 | if (ret < 0) | |
1100 | return ret; | |
1101 | ||
1102 | if (offset & 1) { | |
1103 | int word; | |
1104 | ||
1105 | word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); | |
1106 | if (word < 0) | |
1107 | return word; | |
1108 | ||
1109 | word = (*data++ << 8) | (word & 0xff); | |
1110 | ||
1111 | ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); | |
1112 | if (ret < 0) | |
1113 | return ret; | |
1114 | ||
1115 | offset++; | |
1116 | len--; | |
1117 | eeprom->len++; | |
1118 | } | |
1119 | ||
1120 | while (len >= 2) { | |
1121 | int word; | |
1122 | ||
1123 | word = *data++; | |
1124 | word |= *data++ << 8; | |
1125 | ||
1126 | ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); | |
1127 | if (ret < 0) | |
1128 | return ret; | |
1129 | ||
1130 | offset += 2; | |
1131 | len -= 2; | |
1132 | eeprom->len += 2; | |
1133 | } | |
1134 | ||
1135 | if (len) { | |
1136 | int word; | |
1137 | ||
1138 | word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); | |
1139 | if (word < 0) | |
1140 | return word; | |
1141 | ||
1142 | word = (word & 0xff00) | *data++; | |
1143 | ||
1144 | ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); | |
1145 | if (ret < 0) | |
1146 | return ret; | |
1147 | ||
1148 | offset++; | |
1149 | len--; | |
1150 | eeprom->len++; | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
158bc065 | 1156 | static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps) |
facd95b2 | 1157 | { |
158bc065 | 1158 | return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP, |
cca8b133 | 1159 | GLOBAL_ATU_OP_BUSY); |
facd95b2 GR |
1160 | } |
1161 | ||
03a4a540 | 1162 | static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_priv_state *ps, |
158bc065 | 1163 | int addr, int regnum) |
f3044683 AL |
1164 | { |
1165 | int ret; | |
1166 | ||
158bc065 | 1167 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, |
3898c148 AL |
1168 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | |
1169 | regnum); | |
1170 | if (ret < 0) | |
1171 | return ret; | |
f3044683 | 1172 | |
03a4a540 | 1173 | ret = mv88e6xxx_mdio_wait(ps); |
f3044683 AL |
1174 | if (ret < 0) |
1175 | return ret; | |
1176 | ||
158bc065 AL |
1177 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
1178 | ||
1179 | return ret; | |
f3044683 AL |
1180 | } |
1181 | ||
03a4a540 | 1182 | static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_priv_state *ps, |
158bc065 | 1183 | int addr, int regnum, u16 val) |
f3044683 | 1184 | { |
3898c148 AL |
1185 | int ret; |
1186 | ||
158bc065 | 1187 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); |
3898c148 AL |
1188 | if (ret < 0) |
1189 | return ret; | |
f3044683 | 1190 | |
158bc065 | 1191 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, |
3898c148 AL |
1192 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | |
1193 | regnum); | |
1194 | ||
03a4a540 | 1195 | return mv88e6xxx_mdio_wait(ps); |
f3044683 AL |
1196 | } |
1197 | ||
f81ec90f VD |
1198 | static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, |
1199 | struct ethtool_eee *e) | |
11b3b45d | 1200 | { |
2f40c698 | 1201 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
1202 | int reg; |
1203 | ||
aadbdb8a VD |
1204 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) |
1205 | return -EOPNOTSUPP; | |
1206 | ||
9f8b3ee1 | 1207 | mutex_lock(&ps->reg_lock); |
2f40c698 | 1208 | |
03a4a540 | 1209 | reg = mv88e6xxx_mdio_read_indirect(ps, port, 16); |
11b3b45d | 1210 | if (reg < 0) |
2f40c698 | 1211 | goto out; |
11b3b45d GR |
1212 | |
1213 | e->eee_enabled = !!(reg & 0x0200); | |
1214 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
1215 | ||
158bc065 | 1216 | reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); |
11b3b45d | 1217 | if (reg < 0) |
2f40c698 | 1218 | goto out; |
11b3b45d | 1219 | |
cca8b133 | 1220 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 1221 | reg = 0; |
11b3b45d | 1222 | |
2f40c698 | 1223 | out: |
9f8b3ee1 | 1224 | mutex_unlock(&ps->reg_lock); |
2f40c698 | 1225 | return reg; |
11b3b45d GR |
1226 | } |
1227 | ||
f81ec90f VD |
1228 | static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, |
1229 | struct phy_device *phydev, struct ethtool_eee *e) | |
11b3b45d | 1230 | { |
2f40c698 AL |
1231 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1232 | int reg; | |
11b3b45d GR |
1233 | int ret; |
1234 | ||
aadbdb8a VD |
1235 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) |
1236 | return -EOPNOTSUPP; | |
1237 | ||
9f8b3ee1 | 1238 | mutex_lock(&ps->reg_lock); |
11b3b45d | 1239 | |
03a4a540 | 1240 | ret = mv88e6xxx_mdio_read_indirect(ps, port, 16); |
2f40c698 AL |
1241 | if (ret < 0) |
1242 | goto out; | |
1243 | ||
1244 | reg = ret & ~0x0300; | |
1245 | if (e->eee_enabled) | |
1246 | reg |= 0x0200; | |
1247 | if (e->tx_lpi_enabled) | |
1248 | reg |= 0x0100; | |
1249 | ||
03a4a540 | 1250 | ret = mv88e6xxx_mdio_write_indirect(ps, port, 16, reg); |
2f40c698 | 1251 | out: |
9f8b3ee1 | 1252 | mutex_unlock(&ps->reg_lock); |
2f40c698 AL |
1253 | |
1254 | return ret; | |
11b3b45d GR |
1255 | } |
1256 | ||
158bc065 | 1257 | static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd) |
facd95b2 GR |
1258 | { |
1259 | int ret; | |
1260 | ||
158bc065 AL |
1261 | if (mv88e6xxx_has_fid_reg(ps)) { |
1262 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid); | |
b426e5f7 VD |
1263 | if (ret < 0) |
1264 | return ret; | |
158bc065 | 1265 | } else if (mv88e6xxx_num_databases(ps) == 256) { |
11ea809f | 1266 | /* ATU DBNum[7:4] are located in ATU Control 15:12 */ |
158bc065 | 1267 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL); |
11ea809f VD |
1268 | if (ret < 0) |
1269 | return ret; | |
1270 | ||
158bc065 | 1271 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
11ea809f VD |
1272 | (ret & 0xfff) | |
1273 | ((fid << 8) & 0xf000)); | |
1274 | if (ret < 0) | |
1275 | return ret; | |
1276 | ||
1277 | /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ | |
1278 | cmd |= fid & 0xf; | |
b426e5f7 VD |
1279 | } |
1280 | ||
158bc065 | 1281 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
1282 | if (ret < 0) |
1283 | return ret; | |
1284 | ||
158bc065 | 1285 | return _mv88e6xxx_atu_wait(ps); |
facd95b2 GR |
1286 | } |
1287 | ||
158bc065 | 1288 | static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps, |
37705b73 VD |
1289 | struct mv88e6xxx_atu_entry *entry) |
1290 | { | |
1291 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
1292 | ||
1293 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1294 | unsigned int mask, shift; | |
1295 | ||
1296 | if (entry->trunk) { | |
1297 | data |= GLOBAL_ATU_DATA_TRUNK; | |
1298 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1299 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1300 | } else { | |
1301 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1302 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1303 | } | |
1304 | ||
1305 | data |= (entry->portv_trunkid << shift) & mask; | |
1306 | } | |
1307 | ||
158bc065 | 1308 | return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data); |
37705b73 VD |
1309 | } |
1310 | ||
158bc065 | 1311 | static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps, |
7fb5e755 VD |
1312 | struct mv88e6xxx_atu_entry *entry, |
1313 | bool static_too) | |
facd95b2 | 1314 | { |
7fb5e755 VD |
1315 | int op; |
1316 | int err; | |
facd95b2 | 1317 | |
158bc065 | 1318 | err = _mv88e6xxx_atu_wait(ps); |
7fb5e755 VD |
1319 | if (err) |
1320 | return err; | |
facd95b2 | 1321 | |
158bc065 | 1322 | err = _mv88e6xxx_atu_data_write(ps, entry); |
7fb5e755 VD |
1323 | if (err) |
1324 | return err; | |
1325 | ||
1326 | if (entry->fid) { | |
7fb5e755 VD |
1327 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : |
1328 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
1329 | } else { | |
1330 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
1331 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
1332 | } | |
1333 | ||
158bc065 | 1334 | return _mv88e6xxx_atu_cmd(ps, entry->fid, op); |
7fb5e755 VD |
1335 | } |
1336 | ||
158bc065 AL |
1337 | static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps, |
1338 | u16 fid, bool static_too) | |
7fb5e755 VD |
1339 | { |
1340 | struct mv88e6xxx_atu_entry entry = { | |
1341 | .fid = fid, | |
1342 | .state = 0, /* EntryState bits must be 0 */ | |
1343 | }; | |
70cc99d1 | 1344 | |
158bc065 | 1345 | return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); |
7fb5e755 VD |
1346 | } |
1347 | ||
158bc065 AL |
1348 | static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid, |
1349 | int from_port, int to_port, bool static_too) | |
9f4d55d2 VD |
1350 | { |
1351 | struct mv88e6xxx_atu_entry entry = { | |
1352 | .trunk = false, | |
1353 | .fid = fid, | |
1354 | }; | |
1355 | ||
1356 | /* EntryState bits must be 0xF */ | |
1357 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1358 | ||
1359 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1360 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1361 | entry.portv_trunkid |= from_port & 0x0f; | |
1362 | ||
158bc065 | 1363 | return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); |
9f4d55d2 VD |
1364 | } |
1365 | ||
158bc065 AL |
1366 | static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid, |
1367 | int port, bool static_too) | |
9f4d55d2 VD |
1368 | { |
1369 | /* Destination port 0xF means remove the entries */ | |
158bc065 | 1370 | return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too); |
9f4d55d2 VD |
1371 | } |
1372 | ||
2d9deae4 VD |
1373 | static const char * const mv88e6xxx_port_state_names[] = { |
1374 | [PORT_CONTROL_STATE_DISABLED] = "Disabled", | |
1375 | [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", | |
1376 | [PORT_CONTROL_STATE_LEARNING] = "Learning", | |
1377 | [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", | |
1378 | }; | |
1379 | ||
158bc065 AL |
1380 | static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port, |
1381 | u8 state) | |
facd95b2 | 1382 | { |
158bc065 | 1383 | struct dsa_switch *ds = ps->ds; |
c3ffe6d2 | 1384 | int reg, ret = 0; |
facd95b2 GR |
1385 | u8 oldstate; |
1386 | ||
158bc065 | 1387 | reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL); |
2d9deae4 VD |
1388 | if (reg < 0) |
1389 | return reg; | |
facd95b2 | 1390 | |
cca8b133 | 1391 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
2d9deae4 | 1392 | |
facd95b2 GR |
1393 | if (oldstate != state) { |
1394 | /* Flush forwarding database if we're moving a port | |
1395 | * from Learning or Forwarding state to Disabled or | |
1396 | * Blocking or Listening state. | |
1397 | */ | |
2d9deae4 | 1398 | if ((oldstate == PORT_CONTROL_STATE_LEARNING || |
57d32310 VD |
1399 | oldstate == PORT_CONTROL_STATE_FORWARDING) && |
1400 | (state == PORT_CONTROL_STATE_DISABLED || | |
1401 | state == PORT_CONTROL_STATE_BLOCKING)) { | |
158bc065 | 1402 | ret = _mv88e6xxx_atu_remove(ps, 0, port, false); |
facd95b2 | 1403 | if (ret) |
2d9deae4 | 1404 | return ret; |
facd95b2 | 1405 | } |
2d9deae4 | 1406 | |
cca8b133 | 1407 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
158bc065 | 1408 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL, |
cca8b133 | 1409 | reg); |
2d9deae4 VD |
1410 | if (ret) |
1411 | return ret; | |
1412 | ||
c8b09808 | 1413 | netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n", |
2d9deae4 VD |
1414 | mv88e6xxx_port_state_names[state], |
1415 | mv88e6xxx_port_state_names[oldstate]); | |
facd95b2 GR |
1416 | } |
1417 | ||
facd95b2 GR |
1418 | return ret; |
1419 | } | |
1420 | ||
158bc065 AL |
1421 | static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps, |
1422 | int port) | |
facd95b2 | 1423 | { |
b7666efe | 1424 | struct net_device *bridge = ps->ports[port].bridge_dev; |
009a2b98 | 1425 | const u16 mask = (1 << ps->info->num_ports) - 1; |
158bc065 | 1426 | struct dsa_switch *ds = ps->ds; |
b7666efe | 1427 | u16 output_ports = 0; |
ede8098d | 1428 | int reg; |
b7666efe VD |
1429 | int i; |
1430 | ||
1431 | /* allow CPU port or DSA link(s) to send frames to every port */ | |
1432 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { | |
1433 | output_ports = mask; | |
1434 | } else { | |
009a2b98 | 1435 | for (i = 0; i < ps->info->num_ports; ++i) { |
b7666efe VD |
1436 | /* allow sending frames to every group member */ |
1437 | if (bridge && ps->ports[i].bridge_dev == bridge) | |
1438 | output_ports |= BIT(i); | |
1439 | ||
1440 | /* allow sending frames to CPU port and DSA link(s) */ | |
1441 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) | |
1442 | output_ports |= BIT(i); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | /* prevent frames from going back out of the port they came in on */ | |
1447 | output_ports &= ~BIT(port); | |
facd95b2 | 1448 | |
158bc065 | 1449 | reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); |
ede8098d VD |
1450 | if (reg < 0) |
1451 | return reg; | |
facd95b2 | 1452 | |
ede8098d VD |
1453 | reg &= ~mask; |
1454 | reg |= output_ports & mask; | |
facd95b2 | 1455 | |
158bc065 | 1456 | return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1457 | } |
1458 | ||
f81ec90f VD |
1459 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1460 | u8 state) | |
facd95b2 GR |
1461 | { |
1462 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1463 | int stp_state; | |
553eb544 | 1464 | int err; |
facd95b2 | 1465 | |
936f234a VD |
1466 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE)) |
1467 | return; | |
1468 | ||
facd95b2 GR |
1469 | switch (state) { |
1470 | case BR_STATE_DISABLED: | |
cca8b133 | 1471 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1472 | break; |
1473 | case BR_STATE_BLOCKING: | |
1474 | case BR_STATE_LISTENING: | |
cca8b133 | 1475 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1476 | break; |
1477 | case BR_STATE_LEARNING: | |
cca8b133 | 1478 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1479 | break; |
1480 | case BR_STATE_FORWARDING: | |
1481 | default: | |
cca8b133 | 1482 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1483 | break; |
1484 | } | |
1485 | ||
9f8b3ee1 | 1486 | mutex_lock(&ps->reg_lock); |
553eb544 | 1487 | err = _mv88e6xxx_port_state(ps, port, stp_state); |
9f8b3ee1 | 1488 | mutex_unlock(&ps->reg_lock); |
553eb544 VD |
1489 | |
1490 | if (err) | |
c8b09808 AL |
1491 | netdev_err(ds->ports[port].netdev, |
1492 | "failed to update state to %s\n", | |
553eb544 | 1493 | mv88e6xxx_port_state_names[stp_state]); |
facd95b2 GR |
1494 | } |
1495 | ||
158bc065 AL |
1496 | static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port, |
1497 | u16 *new, u16 *old) | |
76e398a6 | 1498 | { |
158bc065 | 1499 | struct dsa_switch *ds = ps->ds; |
5da96031 | 1500 | u16 pvid; |
76e398a6 VD |
1501 | int ret; |
1502 | ||
158bc065 | 1503 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN); |
76e398a6 VD |
1504 | if (ret < 0) |
1505 | return ret; | |
1506 | ||
5da96031 VD |
1507 | pvid = ret & PORT_DEFAULT_VLAN_MASK; |
1508 | ||
1509 | if (new) { | |
1510 | ret &= ~PORT_DEFAULT_VLAN_MASK; | |
1511 | ret |= *new & PORT_DEFAULT_VLAN_MASK; | |
1512 | ||
158bc065 | 1513 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
5da96031 VD |
1514 | PORT_DEFAULT_VLAN, ret); |
1515 | if (ret < 0) | |
1516 | return ret; | |
1517 | ||
c8b09808 AL |
1518 | netdev_dbg(ds->ports[port].netdev, |
1519 | "DefaultVID %d (was %d)\n", *new, pvid); | |
5da96031 VD |
1520 | } |
1521 | ||
1522 | if (old) | |
1523 | *old = pvid; | |
76e398a6 VD |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
158bc065 AL |
1528 | static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps, |
1529 | int port, u16 *pvid) | |
5da96031 | 1530 | { |
158bc065 | 1531 | return _mv88e6xxx_port_pvid(ps, port, NULL, pvid); |
5da96031 VD |
1532 | } |
1533 | ||
158bc065 AL |
1534 | static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps, |
1535 | int port, u16 pvid) | |
0d3b33e6 | 1536 | { |
158bc065 | 1537 | return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL); |
0d3b33e6 VD |
1538 | } |
1539 | ||
158bc065 | 1540 | static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps) |
6b17e864 | 1541 | { |
158bc065 | 1542 | return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP, |
6b17e864 VD |
1543 | GLOBAL_VTU_OP_BUSY); |
1544 | } | |
1545 | ||
158bc065 | 1546 | static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op) |
6b17e864 VD |
1547 | { |
1548 | int ret; | |
1549 | ||
158bc065 | 1550 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op); |
6b17e864 VD |
1551 | if (ret < 0) |
1552 | return ret; | |
1553 | ||
158bc065 | 1554 | return _mv88e6xxx_vtu_wait(ps); |
6b17e864 VD |
1555 | } |
1556 | ||
158bc065 | 1557 | static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps) |
6b17e864 VD |
1558 | { |
1559 | int ret; | |
1560 | ||
158bc065 | 1561 | ret = _mv88e6xxx_vtu_wait(ps); |
6b17e864 VD |
1562 | if (ret < 0) |
1563 | return ret; | |
1564 | ||
158bc065 | 1565 | return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL); |
6b17e864 VD |
1566 | } |
1567 | ||
158bc065 | 1568 | static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps, |
b8fee957 VD |
1569 | struct mv88e6xxx_vtu_stu_entry *entry, |
1570 | unsigned int nibble_offset) | |
1571 | { | |
b8fee957 VD |
1572 | u16 regs[3]; |
1573 | int i; | |
1574 | int ret; | |
1575 | ||
1576 | for (i = 0; i < 3; ++i) { | |
158bc065 | 1577 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, |
b8fee957 VD |
1578 | GLOBAL_VTU_DATA_0_3 + i); |
1579 | if (ret < 0) | |
1580 | return ret; | |
1581 | ||
1582 | regs[i] = ret; | |
1583 | } | |
1584 | ||
009a2b98 | 1585 | for (i = 0; i < ps->info->num_ports; ++i) { |
b8fee957 VD |
1586 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1587 | u16 reg = regs[i / 4]; | |
1588 | ||
1589 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1590 | } | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
15d7d7d4 VD |
1595 | static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps, |
1596 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1597 | { | |
1598 | return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0); | |
1599 | } | |
1600 | ||
1601 | static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps, | |
1602 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1603 | { | |
1604 | return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2); | |
1605 | } | |
1606 | ||
158bc065 | 1607 | static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps, |
7dad08d7 VD |
1608 | struct mv88e6xxx_vtu_stu_entry *entry, |
1609 | unsigned int nibble_offset) | |
1610 | { | |
7dad08d7 VD |
1611 | u16 regs[3] = { 0 }; |
1612 | int i; | |
1613 | int ret; | |
1614 | ||
009a2b98 | 1615 | for (i = 0; i < ps->info->num_ports; ++i) { |
7dad08d7 VD |
1616 | unsigned int shift = (i % 4) * 4 + nibble_offset; |
1617 | u8 data = entry->data[i]; | |
1618 | ||
1619 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1620 | } | |
1621 | ||
1622 | for (i = 0; i < 3; ++i) { | |
158bc065 | 1623 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, |
7dad08d7 VD |
1624 | GLOBAL_VTU_DATA_0_3 + i, regs[i]); |
1625 | if (ret < 0) | |
1626 | return ret; | |
1627 | } | |
1628 | ||
1629 | return 0; | |
1630 | } | |
1631 | ||
15d7d7d4 VD |
1632 | static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps, |
1633 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1634 | { | |
1635 | return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0); | |
1636 | } | |
1637 | ||
1638 | static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps, | |
1639 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1640 | { | |
1641 | return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2); | |
1642 | } | |
1643 | ||
158bc065 | 1644 | static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid) |
36d04ba1 | 1645 | { |
158bc065 | 1646 | return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, |
36d04ba1 VD |
1647 | vid & GLOBAL_VTU_VID_MASK); |
1648 | } | |
1649 | ||
158bc065 | 1650 | static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps, |
b8fee957 VD |
1651 | struct mv88e6xxx_vtu_stu_entry *entry) |
1652 | { | |
1653 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1654 | int ret; | |
1655 | ||
158bc065 | 1656 | ret = _mv88e6xxx_vtu_wait(ps); |
b8fee957 VD |
1657 | if (ret < 0) |
1658 | return ret; | |
1659 | ||
158bc065 | 1660 | ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT); |
b8fee957 VD |
1661 | if (ret < 0) |
1662 | return ret; | |
1663 | ||
158bc065 | 1664 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); |
b8fee957 VD |
1665 | if (ret < 0) |
1666 | return ret; | |
1667 | ||
1668 | next.vid = ret & GLOBAL_VTU_VID_MASK; | |
1669 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1670 | ||
1671 | if (next.valid) { | |
15d7d7d4 | 1672 | ret = mv88e6xxx_vtu_data_read(ps, &next); |
b8fee957 VD |
1673 | if (ret < 0) |
1674 | return ret; | |
1675 | ||
158bc065 AL |
1676 | if (mv88e6xxx_has_fid_reg(ps)) { |
1677 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, | |
b8fee957 VD |
1678 | GLOBAL_VTU_FID); |
1679 | if (ret < 0) | |
1680 | return ret; | |
1681 | ||
1682 | next.fid = ret & GLOBAL_VTU_FID_MASK; | |
158bc065 | 1683 | } else if (mv88e6xxx_num_databases(ps) == 256) { |
11ea809f VD |
1684 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1685 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1686 | */ | |
158bc065 | 1687 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, |
11ea809f VD |
1688 | GLOBAL_VTU_OP); |
1689 | if (ret < 0) | |
1690 | return ret; | |
1691 | ||
1692 | next.fid = (ret & 0xf00) >> 4; | |
1693 | next.fid |= ret & 0xf; | |
2e7bd5ef | 1694 | } |
b8fee957 | 1695 | |
cb9b9020 | 1696 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { |
158bc065 | 1697 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, |
b8fee957 VD |
1698 | GLOBAL_VTU_SID); |
1699 | if (ret < 0) | |
1700 | return ret; | |
1701 | ||
1702 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1703 | } | |
1704 | } | |
1705 | ||
1706 | *entry = next; | |
1707 | return 0; | |
1708 | } | |
1709 | ||
f81ec90f VD |
1710 | static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
1711 | struct switchdev_obj_port_vlan *vlan, | |
1712 | int (*cb)(struct switchdev_obj *obj)) | |
ceff5eff VD |
1713 | { |
1714 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1715 | struct mv88e6xxx_vtu_stu_entry next; | |
1716 | u16 pvid; | |
1717 | int err; | |
1718 | ||
54d77b5b VD |
1719 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) |
1720 | return -EOPNOTSUPP; | |
1721 | ||
9f8b3ee1 | 1722 | mutex_lock(&ps->reg_lock); |
ceff5eff | 1723 | |
158bc065 | 1724 | err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); |
ceff5eff VD |
1725 | if (err) |
1726 | goto unlock; | |
1727 | ||
158bc065 | 1728 | err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); |
ceff5eff VD |
1729 | if (err) |
1730 | goto unlock; | |
1731 | ||
1732 | do { | |
158bc065 | 1733 | err = _mv88e6xxx_vtu_getnext(ps, &next); |
ceff5eff VD |
1734 | if (err) |
1735 | break; | |
1736 | ||
1737 | if (!next.valid) | |
1738 | break; | |
1739 | ||
1740 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1741 | continue; | |
1742 | ||
1743 | /* reinit and dump this VLAN obj */ | |
57d32310 VD |
1744 | vlan->vid_begin = next.vid; |
1745 | vlan->vid_end = next.vid; | |
ceff5eff VD |
1746 | vlan->flags = 0; |
1747 | ||
1748 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1749 | vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; | |
1750 | ||
1751 | if (next.vid == pvid) | |
1752 | vlan->flags |= BRIDGE_VLAN_INFO_PVID; | |
1753 | ||
1754 | err = cb(&vlan->obj); | |
1755 | if (err) | |
1756 | break; | |
1757 | } while (next.vid < GLOBAL_VTU_VID_MASK); | |
1758 | ||
1759 | unlock: | |
9f8b3ee1 | 1760 | mutex_unlock(&ps->reg_lock); |
ceff5eff VD |
1761 | |
1762 | return err; | |
1763 | } | |
1764 | ||
158bc065 | 1765 | static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps, |
7dad08d7 VD |
1766 | struct mv88e6xxx_vtu_stu_entry *entry) |
1767 | { | |
11ea809f | 1768 | u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; |
7dad08d7 VD |
1769 | u16 reg = 0; |
1770 | int ret; | |
1771 | ||
158bc065 | 1772 | ret = _mv88e6xxx_vtu_wait(ps); |
7dad08d7 VD |
1773 | if (ret < 0) |
1774 | return ret; | |
1775 | ||
1776 | if (!entry->valid) | |
1777 | goto loadpurge; | |
1778 | ||
1779 | /* Write port member tags */ | |
15d7d7d4 | 1780 | ret = mv88e6xxx_vtu_data_write(ps, entry); |
7dad08d7 VD |
1781 | if (ret < 0) |
1782 | return ret; | |
1783 | ||
cb9b9020 | 1784 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { |
7dad08d7 | 1785 | reg = entry->sid & GLOBAL_VTU_SID_MASK; |
158bc065 | 1786 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); |
7dad08d7 VD |
1787 | if (ret < 0) |
1788 | return ret; | |
b426e5f7 | 1789 | } |
7dad08d7 | 1790 | |
158bc065 | 1791 | if (mv88e6xxx_has_fid_reg(ps)) { |
7dad08d7 | 1792 | reg = entry->fid & GLOBAL_VTU_FID_MASK; |
158bc065 | 1793 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg); |
7dad08d7 VD |
1794 | if (ret < 0) |
1795 | return ret; | |
158bc065 | 1796 | } else if (mv88e6xxx_num_databases(ps) == 256) { |
11ea809f VD |
1797 | /* VTU DBNum[7:4] are located in VTU Operation 11:8, and |
1798 | * VTU DBNum[3:0] are located in VTU Operation 3:0 | |
1799 | */ | |
1800 | op |= (entry->fid & 0xf0) << 8; | |
1801 | op |= entry->fid & 0xf; | |
7dad08d7 VD |
1802 | } |
1803 | ||
1804 | reg = GLOBAL_VTU_VID_VALID; | |
1805 | loadpurge: | |
1806 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
158bc065 | 1807 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
7dad08d7 VD |
1808 | if (ret < 0) |
1809 | return ret; | |
1810 | ||
158bc065 | 1811 | return _mv88e6xxx_vtu_cmd(ps, op); |
7dad08d7 VD |
1812 | } |
1813 | ||
158bc065 | 1814 | static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid, |
0d3b33e6 VD |
1815 | struct mv88e6xxx_vtu_stu_entry *entry) |
1816 | { | |
1817 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1818 | int ret; | |
1819 | ||
158bc065 | 1820 | ret = _mv88e6xxx_vtu_wait(ps); |
0d3b33e6 VD |
1821 | if (ret < 0) |
1822 | return ret; | |
1823 | ||
158bc065 | 1824 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, |
0d3b33e6 VD |
1825 | sid & GLOBAL_VTU_SID_MASK); |
1826 | if (ret < 0) | |
1827 | return ret; | |
1828 | ||
158bc065 | 1829 | ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT); |
0d3b33e6 VD |
1830 | if (ret < 0) |
1831 | return ret; | |
1832 | ||
158bc065 | 1833 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID); |
0d3b33e6 VD |
1834 | if (ret < 0) |
1835 | return ret; | |
1836 | ||
1837 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1838 | ||
158bc065 | 1839 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); |
0d3b33e6 VD |
1840 | if (ret < 0) |
1841 | return ret; | |
1842 | ||
1843 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1844 | ||
1845 | if (next.valid) { | |
15d7d7d4 | 1846 | ret = mv88e6xxx_stu_data_read(ps, &next); |
0d3b33e6 VD |
1847 | if (ret < 0) |
1848 | return ret; | |
1849 | } | |
1850 | ||
1851 | *entry = next; | |
1852 | return 0; | |
1853 | } | |
1854 | ||
158bc065 | 1855 | static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps, |
0d3b33e6 VD |
1856 | struct mv88e6xxx_vtu_stu_entry *entry) |
1857 | { | |
1858 | u16 reg = 0; | |
1859 | int ret; | |
1860 | ||
158bc065 | 1861 | ret = _mv88e6xxx_vtu_wait(ps); |
0d3b33e6 VD |
1862 | if (ret < 0) |
1863 | return ret; | |
1864 | ||
1865 | if (!entry->valid) | |
1866 | goto loadpurge; | |
1867 | ||
1868 | /* Write port states */ | |
15d7d7d4 | 1869 | ret = mv88e6xxx_stu_data_write(ps, entry); |
0d3b33e6 VD |
1870 | if (ret < 0) |
1871 | return ret; | |
1872 | ||
1873 | reg = GLOBAL_VTU_VID_VALID; | |
1874 | loadpurge: | |
158bc065 | 1875 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); |
0d3b33e6 VD |
1876 | if (ret < 0) |
1877 | return ret; | |
1878 | ||
1879 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
158bc065 | 1880 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); |
0d3b33e6 VD |
1881 | if (ret < 0) |
1882 | return ret; | |
1883 | ||
158bc065 | 1884 | return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE); |
0d3b33e6 VD |
1885 | } |
1886 | ||
158bc065 AL |
1887 | static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port, |
1888 | u16 *new, u16 *old) | |
2db9ce1f | 1889 | { |
158bc065 | 1890 | struct dsa_switch *ds = ps->ds; |
f74df0be | 1891 | u16 upper_mask; |
2db9ce1f VD |
1892 | u16 fid; |
1893 | int ret; | |
1894 | ||
158bc065 | 1895 | if (mv88e6xxx_num_databases(ps) == 4096) |
f74df0be | 1896 | upper_mask = 0xff; |
158bc065 | 1897 | else if (mv88e6xxx_num_databases(ps) == 256) |
11ea809f | 1898 | upper_mask = 0xf; |
f74df0be VD |
1899 | else |
1900 | return -EOPNOTSUPP; | |
1901 | ||
2db9ce1f | 1902 | /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ |
158bc065 | 1903 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); |
2db9ce1f VD |
1904 | if (ret < 0) |
1905 | return ret; | |
1906 | ||
1907 | fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; | |
1908 | ||
1909 | if (new) { | |
1910 | ret &= ~PORT_BASE_VLAN_FID_3_0_MASK; | |
1911 | ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; | |
1912 | ||
158bc065 | 1913 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, |
2db9ce1f VD |
1914 | ret); |
1915 | if (ret < 0) | |
1916 | return ret; | |
1917 | } | |
1918 | ||
1919 | /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ | |
158bc065 | 1920 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1); |
2db9ce1f VD |
1921 | if (ret < 0) |
1922 | return ret; | |
1923 | ||
f74df0be | 1924 | fid |= (ret & upper_mask) << 4; |
2db9ce1f VD |
1925 | |
1926 | if (new) { | |
f74df0be VD |
1927 | ret &= ~upper_mask; |
1928 | ret |= (*new >> 4) & upper_mask; | |
2db9ce1f | 1929 | |
158bc065 | 1930 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, |
2db9ce1f VD |
1931 | ret); |
1932 | if (ret < 0) | |
1933 | return ret; | |
1934 | ||
c8b09808 AL |
1935 | netdev_dbg(ds->ports[port].netdev, |
1936 | "FID %d (was %d)\n", *new, fid); | |
2db9ce1f VD |
1937 | } |
1938 | ||
1939 | if (old) | |
1940 | *old = fid; | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
158bc065 AL |
1945 | static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps, |
1946 | int port, u16 *fid) | |
2db9ce1f | 1947 | { |
158bc065 | 1948 | return _mv88e6xxx_port_fid(ps, port, NULL, fid); |
2db9ce1f VD |
1949 | } |
1950 | ||
158bc065 AL |
1951 | static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps, |
1952 | int port, u16 fid) | |
2db9ce1f | 1953 | { |
158bc065 | 1954 | return _mv88e6xxx_port_fid(ps, port, &fid, NULL); |
2db9ce1f VD |
1955 | } |
1956 | ||
158bc065 | 1957 | static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid) |
3285f9e8 VD |
1958 | { |
1959 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
1960 | struct mv88e6xxx_vtu_stu_entry vlan; | |
2db9ce1f | 1961 | int i, err; |
3285f9e8 VD |
1962 | |
1963 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1964 | ||
2db9ce1f | 1965 | /* Set every FID bit used by the (un)bridged ports */ |
009a2b98 | 1966 | for (i = 0; i < ps->info->num_ports; ++i) { |
158bc065 | 1967 | err = _mv88e6xxx_port_fid_get(ps, i, fid); |
2db9ce1f VD |
1968 | if (err) |
1969 | return err; | |
1970 | ||
1971 | set_bit(*fid, fid_bitmap); | |
1972 | } | |
1973 | ||
3285f9e8 | 1974 | /* Set every FID bit used by the VLAN entries */ |
158bc065 | 1975 | err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); |
3285f9e8 VD |
1976 | if (err) |
1977 | return err; | |
1978 | ||
1979 | do { | |
158bc065 | 1980 | err = _mv88e6xxx_vtu_getnext(ps, &vlan); |
3285f9e8 VD |
1981 | if (err) |
1982 | return err; | |
1983 | ||
1984 | if (!vlan.valid) | |
1985 | break; | |
1986 | ||
1987 | set_bit(vlan.fid, fid_bitmap); | |
1988 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1989 | ||
1990 | /* The reset value 0x000 is used to indicate that multiple address | |
1991 | * databases are not needed. Return the next positive available. | |
1992 | */ | |
1993 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
158bc065 | 1994 | if (unlikely(*fid >= mv88e6xxx_num_databases(ps))) |
3285f9e8 VD |
1995 | return -ENOSPC; |
1996 | ||
1997 | /* Clear the database */ | |
158bc065 | 1998 | return _mv88e6xxx_atu_flush(ps, *fid, true); |
3285f9e8 VD |
1999 | } |
2000 | ||
158bc065 | 2001 | static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid, |
2fb5ef09 | 2002 | struct mv88e6xxx_vtu_stu_entry *entry) |
0d3b33e6 | 2003 | { |
158bc065 | 2004 | struct dsa_switch *ds = ps->ds; |
0d3b33e6 VD |
2005 | struct mv88e6xxx_vtu_stu_entry vlan = { |
2006 | .valid = true, | |
2007 | .vid = vid, | |
2008 | }; | |
3285f9e8 VD |
2009 | int i, err; |
2010 | ||
158bc065 | 2011 | err = _mv88e6xxx_fid_new(ps, &vlan.fid); |
3285f9e8 VD |
2012 | if (err) |
2013 | return err; | |
0d3b33e6 | 2014 | |
3d131f07 | 2015 | /* exclude all ports except the CPU and DSA ports */ |
009a2b98 | 2016 | for (i = 0; i < ps->info->num_ports; ++i) |
3d131f07 VD |
2017 | vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) |
2018 | ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED | |
2019 | : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
0d3b33e6 | 2020 | |
158bc065 AL |
2021 | if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || |
2022 | mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) { | |
0d3b33e6 | 2023 | struct mv88e6xxx_vtu_stu_entry vstp; |
0d3b33e6 VD |
2024 | |
2025 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
2026 | * implemented, only one STU entry is needed to cover all VTU | |
2027 | * entries. Thus, validate the SID 0. | |
2028 | */ | |
2029 | vlan.sid = 0; | |
158bc065 | 2030 | err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp); |
0d3b33e6 VD |
2031 | if (err) |
2032 | return err; | |
2033 | ||
2034 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
2035 | memset(&vstp, 0, sizeof(vstp)); | |
2036 | vstp.valid = true; | |
2037 | vstp.sid = vlan.sid; | |
2038 | ||
158bc065 | 2039 | err = _mv88e6xxx_stu_loadpurge(ps, &vstp); |
0d3b33e6 VD |
2040 | if (err) |
2041 | return err; | |
2042 | } | |
0d3b33e6 VD |
2043 | } |
2044 | ||
2045 | *entry = vlan; | |
2046 | return 0; | |
2047 | } | |
2048 | ||
158bc065 | 2049 | static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid, |
2fb5ef09 VD |
2050 | struct mv88e6xxx_vtu_stu_entry *entry, bool creat) |
2051 | { | |
2052 | int err; | |
2053 | ||
2054 | if (!vid) | |
2055 | return -EINVAL; | |
2056 | ||
158bc065 | 2057 | err = _mv88e6xxx_vtu_vid_write(ps, vid - 1); |
2fb5ef09 VD |
2058 | if (err) |
2059 | return err; | |
2060 | ||
158bc065 | 2061 | err = _mv88e6xxx_vtu_getnext(ps, entry); |
2fb5ef09 VD |
2062 | if (err) |
2063 | return err; | |
2064 | ||
2065 | if (entry->vid != vid || !entry->valid) { | |
2066 | if (!creat) | |
2067 | return -EOPNOTSUPP; | |
2068 | /* -ENOENT would've been more appropriate, but switchdev expects | |
2069 | * -EOPNOTSUPP to inform bridge about an eventual software VLAN. | |
2070 | */ | |
2071 | ||
158bc065 | 2072 | err = _mv88e6xxx_vtu_new(ps, vid, entry); |
2fb5ef09 VD |
2073 | } |
2074 | ||
2075 | return err; | |
2076 | } | |
2077 | ||
da9c359e VD |
2078 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
2079 | u16 vid_begin, u16 vid_end) | |
2080 | { | |
2081 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2082 | struct mv88e6xxx_vtu_stu_entry vlan; | |
2083 | int i, err; | |
2084 | ||
2085 | if (!vid_begin) | |
2086 | return -EOPNOTSUPP; | |
2087 | ||
9f8b3ee1 | 2088 | mutex_lock(&ps->reg_lock); |
da9c359e | 2089 | |
158bc065 | 2090 | err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1); |
da9c359e VD |
2091 | if (err) |
2092 | goto unlock; | |
2093 | ||
2094 | do { | |
158bc065 | 2095 | err = _mv88e6xxx_vtu_getnext(ps, &vlan); |
da9c359e VD |
2096 | if (err) |
2097 | goto unlock; | |
2098 | ||
2099 | if (!vlan.valid) | |
2100 | break; | |
2101 | ||
2102 | if (vlan.vid > vid_end) | |
2103 | break; | |
2104 | ||
009a2b98 | 2105 | for (i = 0; i < ps->info->num_ports; ++i) { |
da9c359e VD |
2106 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) |
2107 | continue; | |
2108 | ||
2109 | if (vlan.data[i] == | |
2110 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
2111 | continue; | |
2112 | ||
2113 | if (ps->ports[i].bridge_dev == | |
2114 | ps->ports[port].bridge_dev) | |
2115 | break; /* same bridge, check next VLAN */ | |
2116 | ||
c8b09808 | 2117 | netdev_warn(ds->ports[port].netdev, |
da9c359e VD |
2118 | "hardware VLAN %d already used by %s\n", |
2119 | vlan.vid, | |
2120 | netdev_name(ps->ports[i].bridge_dev)); | |
2121 | err = -EOPNOTSUPP; | |
2122 | goto unlock; | |
2123 | } | |
2124 | } while (vlan.vid < vid_end); | |
2125 | ||
2126 | unlock: | |
9f8b3ee1 | 2127 | mutex_unlock(&ps->reg_lock); |
da9c359e VD |
2128 | |
2129 | return err; | |
2130 | } | |
2131 | ||
214cdb99 VD |
2132 | static const char * const mv88e6xxx_port_8021q_mode_names[] = { |
2133 | [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", | |
2134 | [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", | |
2135 | [PORT_CONTROL_2_8021Q_CHECK] = "Check", | |
2136 | [PORT_CONTROL_2_8021Q_SECURE] = "Secure", | |
2137 | }; | |
2138 | ||
f81ec90f VD |
2139 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
2140 | bool vlan_filtering) | |
214cdb99 VD |
2141 | { |
2142 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2143 | u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : | |
2144 | PORT_CONTROL_2_8021Q_DISABLED; | |
2145 | int ret; | |
2146 | ||
54d77b5b VD |
2147 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) |
2148 | return -EOPNOTSUPP; | |
2149 | ||
9f8b3ee1 | 2150 | mutex_lock(&ps->reg_lock); |
214cdb99 | 2151 | |
158bc065 | 2152 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2); |
214cdb99 VD |
2153 | if (ret < 0) |
2154 | goto unlock; | |
2155 | ||
2156 | old = ret & PORT_CONTROL_2_8021Q_MASK; | |
2157 | ||
5220ef1e VD |
2158 | if (new != old) { |
2159 | ret &= ~PORT_CONTROL_2_8021Q_MASK; | |
2160 | ret |= new & PORT_CONTROL_2_8021Q_MASK; | |
214cdb99 | 2161 | |
158bc065 | 2162 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2, |
5220ef1e VD |
2163 | ret); |
2164 | if (ret < 0) | |
2165 | goto unlock; | |
2166 | ||
c8b09808 | 2167 | netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n", |
5220ef1e VD |
2168 | mv88e6xxx_port_8021q_mode_names[new], |
2169 | mv88e6xxx_port_8021q_mode_names[old]); | |
2170 | } | |
214cdb99 | 2171 | |
5220ef1e | 2172 | ret = 0; |
214cdb99 | 2173 | unlock: |
9f8b3ee1 | 2174 | mutex_unlock(&ps->reg_lock); |
214cdb99 VD |
2175 | |
2176 | return ret; | |
2177 | } | |
2178 | ||
57d32310 VD |
2179 | static int |
2180 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
2181 | const struct switchdev_obj_port_vlan *vlan, | |
2182 | struct switchdev_trans *trans) | |
76e398a6 | 2183 | { |
54d77b5b | 2184 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
da9c359e VD |
2185 | int err; |
2186 | ||
54d77b5b VD |
2187 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) |
2188 | return -EOPNOTSUPP; | |
2189 | ||
da9c359e VD |
2190 | /* If the requested port doesn't belong to the same bridge as the VLAN |
2191 | * members, do not support it (yet) and fallback to software VLAN. | |
2192 | */ | |
2193 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, | |
2194 | vlan->vid_end); | |
2195 | if (err) | |
2196 | return err; | |
2197 | ||
76e398a6 VD |
2198 | /* We don't need any dynamic resource from the kernel (yet), |
2199 | * so skip the prepare phase. | |
2200 | */ | |
2201 | return 0; | |
2202 | } | |
2203 | ||
158bc065 AL |
2204 | static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port, |
2205 | u16 vid, bool untagged) | |
0d3b33e6 | 2206 | { |
0d3b33e6 VD |
2207 | struct mv88e6xxx_vtu_stu_entry vlan; |
2208 | int err; | |
2209 | ||
158bc065 | 2210 | err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true); |
0d3b33e6 | 2211 | if (err) |
76e398a6 | 2212 | return err; |
0d3b33e6 | 2213 | |
0d3b33e6 VD |
2214 | vlan.data[port] = untagged ? |
2215 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
2216 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
2217 | ||
158bc065 | 2218 | return _mv88e6xxx_vtu_loadpurge(ps, &vlan); |
76e398a6 VD |
2219 | } |
2220 | ||
f81ec90f VD |
2221 | static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
2222 | const struct switchdev_obj_port_vlan *vlan, | |
2223 | struct switchdev_trans *trans) | |
76e398a6 VD |
2224 | { |
2225 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2226 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
2227 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
2228 | u16 vid; | |
76e398a6 | 2229 | |
54d77b5b VD |
2230 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) |
2231 | return; | |
2232 | ||
9f8b3ee1 | 2233 | mutex_lock(&ps->reg_lock); |
76e398a6 | 2234 | |
4d5770b3 | 2235 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) |
158bc065 | 2236 | if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged)) |
c8b09808 AL |
2237 | netdev_err(ds->ports[port].netdev, |
2238 | "failed to add VLAN %d%c\n", | |
4d5770b3 | 2239 | vid, untagged ? 'u' : 't'); |
76e398a6 | 2240 | |
158bc065 | 2241 | if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end)) |
c8b09808 | 2242 | netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", |
4d5770b3 | 2243 | vlan->vid_end); |
0d3b33e6 | 2244 | |
9f8b3ee1 | 2245 | mutex_unlock(&ps->reg_lock); |
0d3b33e6 VD |
2246 | } |
2247 | ||
158bc065 AL |
2248 | static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps, |
2249 | int port, u16 vid) | |
7dad08d7 | 2250 | { |
158bc065 | 2251 | struct dsa_switch *ds = ps->ds; |
7dad08d7 | 2252 | struct mv88e6xxx_vtu_stu_entry vlan; |
7dad08d7 VD |
2253 | int i, err; |
2254 | ||
158bc065 | 2255 | err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); |
7dad08d7 | 2256 | if (err) |
76e398a6 | 2257 | return err; |
7dad08d7 | 2258 | |
2fb5ef09 VD |
2259 | /* Tell switchdev if this VLAN is handled in software */ |
2260 | if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
3c06f08b | 2261 | return -EOPNOTSUPP; |
7dad08d7 VD |
2262 | |
2263 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
2264 | ||
2265 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 2266 | vlan.valid = false; |
009a2b98 | 2267 | for (i = 0; i < ps->info->num_ports; ++i) { |
3d131f07 | 2268 | if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) |
7dad08d7 VD |
2269 | continue; |
2270 | ||
2271 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 2272 | vlan.valid = true; |
7dad08d7 VD |
2273 | break; |
2274 | } | |
2275 | } | |
2276 | ||
158bc065 | 2277 | err = _mv88e6xxx_vtu_loadpurge(ps, &vlan); |
76e398a6 VD |
2278 | if (err) |
2279 | return err; | |
2280 | ||
158bc065 | 2281 | return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false); |
76e398a6 VD |
2282 | } |
2283 | ||
f81ec90f VD |
2284 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
2285 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 VD |
2286 | { |
2287 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2288 | u16 pvid, vid; | |
2289 | int err = 0; | |
2290 | ||
54d77b5b VD |
2291 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) |
2292 | return -EOPNOTSUPP; | |
2293 | ||
9f8b3ee1 | 2294 | mutex_lock(&ps->reg_lock); |
76e398a6 | 2295 | |
158bc065 | 2296 | err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); |
7dad08d7 VD |
2297 | if (err) |
2298 | goto unlock; | |
2299 | ||
76e398a6 | 2300 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
158bc065 | 2301 | err = _mv88e6xxx_port_vlan_del(ps, port, vid); |
76e398a6 VD |
2302 | if (err) |
2303 | goto unlock; | |
2304 | ||
2305 | if (vid == pvid) { | |
158bc065 | 2306 | err = _mv88e6xxx_port_pvid_set(ps, port, 0); |
76e398a6 VD |
2307 | if (err) |
2308 | goto unlock; | |
2309 | } | |
2310 | } | |
2311 | ||
7dad08d7 | 2312 | unlock: |
9f8b3ee1 | 2313 | mutex_unlock(&ps->reg_lock); |
7dad08d7 VD |
2314 | |
2315 | return err; | |
2316 | } | |
2317 | ||
158bc065 | 2318 | static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps, |
c5723ac5 | 2319 | const unsigned char *addr) |
defb05b9 GR |
2320 | { |
2321 | int i, ret; | |
2322 | ||
2323 | for (i = 0; i < 3; i++) { | |
cca8b133 | 2324 | ret = _mv88e6xxx_reg_write( |
158bc065 | 2325 | ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, |
cca8b133 | 2326 | (addr[i * 2] << 8) | addr[i * 2 + 1]); |
defb05b9 GR |
2327 | if (ret < 0) |
2328 | return ret; | |
2329 | } | |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
158bc065 AL |
2334 | static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps, |
2335 | unsigned char *addr) | |
defb05b9 GR |
2336 | { |
2337 | int i, ret; | |
2338 | ||
2339 | for (i = 0; i < 3; i++) { | |
158bc065 | 2340 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, |
cca8b133 | 2341 | GLOBAL_ATU_MAC_01 + i); |
defb05b9 GR |
2342 | if (ret < 0) |
2343 | return ret; | |
2344 | addr[i * 2] = ret >> 8; | |
2345 | addr[i * 2 + 1] = ret & 0xff; | |
2346 | } | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
158bc065 | 2351 | static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps, |
fd231c82 | 2352 | struct mv88e6xxx_atu_entry *entry) |
defb05b9 | 2353 | { |
6630e236 VD |
2354 | int ret; |
2355 | ||
158bc065 | 2356 | ret = _mv88e6xxx_atu_wait(ps); |
defb05b9 GR |
2357 | if (ret < 0) |
2358 | return ret; | |
2359 | ||
158bc065 | 2360 | ret = _mv88e6xxx_atu_mac_write(ps, entry->mac); |
defb05b9 GR |
2361 | if (ret < 0) |
2362 | return ret; | |
2363 | ||
158bc065 | 2364 | ret = _mv88e6xxx_atu_data_write(ps, entry); |
fd231c82 | 2365 | if (ret < 0) |
87820510 VD |
2366 | return ret; |
2367 | ||
158bc065 | 2368 | return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB); |
fd231c82 | 2369 | } |
87820510 | 2370 | |
158bc065 | 2371 | static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port, |
fd231c82 VD |
2372 | const unsigned char *addr, u16 vid, |
2373 | u8 state) | |
2374 | { | |
2375 | struct mv88e6xxx_atu_entry entry = { 0 }; | |
3285f9e8 VD |
2376 | struct mv88e6xxx_vtu_stu_entry vlan; |
2377 | int err; | |
2378 | ||
2db9ce1f VD |
2379 | /* Null VLAN ID corresponds to the port private database */ |
2380 | if (vid == 0) | |
158bc065 | 2381 | err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid); |
2db9ce1f | 2382 | else |
158bc065 | 2383 | err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); |
3285f9e8 VD |
2384 | if (err) |
2385 | return err; | |
fd231c82 | 2386 | |
3285f9e8 | 2387 | entry.fid = vlan.fid; |
fd231c82 VD |
2388 | entry.state = state; |
2389 | ether_addr_copy(entry.mac, addr); | |
2390 | if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
2391 | entry.trunk = false; | |
2392 | entry.portv_trunkid = BIT(port); | |
2393 | } | |
2394 | ||
158bc065 | 2395 | return _mv88e6xxx_atu_load(ps, &entry); |
87820510 VD |
2396 | } |
2397 | ||
f81ec90f VD |
2398 | static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
2399 | const struct switchdev_obj_port_fdb *fdb, | |
2400 | struct switchdev_trans *trans) | |
146a3206 | 2401 | { |
2672f825 VD |
2402 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2403 | ||
2404 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) | |
2405 | return -EOPNOTSUPP; | |
2406 | ||
146a3206 VD |
2407 | /* We don't need any dynamic resource from the kernel (yet), |
2408 | * so skip the prepare phase. | |
2409 | */ | |
2410 | return 0; | |
2411 | } | |
2412 | ||
f81ec90f VD |
2413 | static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2414 | const struct switchdev_obj_port_fdb *fdb, | |
2415 | struct switchdev_trans *trans) | |
87820510 | 2416 | { |
1f36faf2 | 2417 | int state = is_multicast_ether_addr(fdb->addr) ? |
87820510 VD |
2418 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
2419 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
cdf09697 | 2420 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
87820510 | 2421 | |
2672f825 VD |
2422 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) |
2423 | return; | |
2424 | ||
9f8b3ee1 | 2425 | mutex_lock(&ps->reg_lock); |
158bc065 | 2426 | if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state)) |
c8b09808 AL |
2427 | netdev_err(ds->ports[port].netdev, |
2428 | "failed to load MAC address\n"); | |
9f8b3ee1 | 2429 | mutex_unlock(&ps->reg_lock); |
87820510 VD |
2430 | } |
2431 | ||
f81ec90f VD |
2432 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
2433 | const struct switchdev_obj_port_fdb *fdb) | |
87820510 VD |
2434 | { |
2435 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87820510 VD |
2436 | int ret; |
2437 | ||
2672f825 VD |
2438 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) |
2439 | return -EOPNOTSUPP; | |
2440 | ||
9f8b3ee1 | 2441 | mutex_lock(&ps->reg_lock); |
158bc065 | 2442 | ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, |
cdf09697 | 2443 | GLOBAL_ATU_DATA_STATE_UNUSED); |
9f8b3ee1 | 2444 | mutex_unlock(&ps->reg_lock); |
87820510 VD |
2445 | |
2446 | return ret; | |
2447 | } | |
2448 | ||
158bc065 | 2449 | static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid, |
1d194046 | 2450 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 2451 | { |
1d194046 VD |
2452 | struct mv88e6xxx_atu_entry next = { 0 }; |
2453 | int ret; | |
2454 | ||
2455 | next.fid = fid; | |
defb05b9 | 2456 | |
158bc065 | 2457 | ret = _mv88e6xxx_atu_wait(ps); |
cdf09697 DM |
2458 | if (ret < 0) |
2459 | return ret; | |
6630e236 | 2460 | |
158bc065 | 2461 | ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
1d194046 VD |
2462 | if (ret < 0) |
2463 | return ret; | |
6630e236 | 2464 | |
158bc065 | 2465 | ret = _mv88e6xxx_atu_mac_read(ps, next.mac); |
1d194046 VD |
2466 | if (ret < 0) |
2467 | return ret; | |
6630e236 | 2468 | |
158bc065 | 2469 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA); |
cdf09697 DM |
2470 | if (ret < 0) |
2471 | return ret; | |
6630e236 | 2472 | |
1d194046 VD |
2473 | next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
2474 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
2475 | unsigned int mask, shift; | |
2476 | ||
2477 | if (ret & GLOBAL_ATU_DATA_TRUNK) { | |
2478 | next.trunk = true; | |
2479 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
2480 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
2481 | } else { | |
2482 | next.trunk = false; | |
2483 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
2484 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
2485 | } | |
2486 | ||
2487 | next.portv_trunkid = (ret & mask) >> shift; | |
2488 | } | |
cdf09697 | 2489 | |
1d194046 | 2490 | *entry = next; |
cdf09697 DM |
2491 | return 0; |
2492 | } | |
2493 | ||
158bc065 AL |
2494 | static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps, |
2495 | u16 fid, u16 vid, int port, | |
74b6ba0d VD |
2496 | struct switchdev_obj_port_fdb *fdb, |
2497 | int (*cb)(struct switchdev_obj *obj)) | |
2498 | { | |
2499 | struct mv88e6xxx_atu_entry addr = { | |
2500 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
2501 | }; | |
2502 | int err; | |
2503 | ||
158bc065 | 2504 | err = _mv88e6xxx_atu_mac_write(ps, addr.mac); |
74b6ba0d VD |
2505 | if (err) |
2506 | return err; | |
2507 | ||
2508 | do { | |
158bc065 | 2509 | err = _mv88e6xxx_atu_getnext(ps, fid, &addr); |
74b6ba0d VD |
2510 | if (err) |
2511 | break; | |
2512 | ||
2513 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
2514 | break; | |
2515 | ||
2516 | if (!addr.trunk && addr.portv_trunkid & BIT(port)) { | |
2517 | bool is_static = addr.state == | |
2518 | (is_multicast_ether_addr(addr.mac) ? | |
2519 | GLOBAL_ATU_DATA_STATE_MC_STATIC : | |
2520 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
2521 | ||
2522 | fdb->vid = vid; | |
2523 | ether_addr_copy(fdb->addr, addr.mac); | |
2524 | fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; | |
2525 | ||
2526 | err = cb(&fdb->obj); | |
2527 | if (err) | |
2528 | break; | |
2529 | } | |
2530 | } while (!is_broadcast_ether_addr(addr.mac)); | |
2531 | ||
2532 | return err; | |
2533 | } | |
2534 | ||
f81ec90f VD |
2535 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
2536 | struct switchdev_obj_port_fdb *fdb, | |
2537 | int (*cb)(struct switchdev_obj *obj)) | |
f33475bd VD |
2538 | { |
2539 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2540 | struct mv88e6xxx_vtu_stu_entry vlan = { | |
2541 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ | |
2542 | }; | |
2db9ce1f | 2543 | u16 fid; |
f33475bd VD |
2544 | int err; |
2545 | ||
2672f825 VD |
2546 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) |
2547 | return -EOPNOTSUPP; | |
2548 | ||
9f8b3ee1 | 2549 | mutex_lock(&ps->reg_lock); |
f33475bd | 2550 | |
2db9ce1f | 2551 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
158bc065 | 2552 | err = _mv88e6xxx_port_fid_get(ps, port, &fid); |
2db9ce1f VD |
2553 | if (err) |
2554 | goto unlock; | |
2555 | ||
158bc065 | 2556 | err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb); |
2db9ce1f VD |
2557 | if (err) |
2558 | goto unlock; | |
2559 | ||
74b6ba0d | 2560 | /* Dump VLANs' Filtering Information Databases */ |
158bc065 | 2561 | err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid); |
f33475bd VD |
2562 | if (err) |
2563 | goto unlock; | |
2564 | ||
2565 | do { | |
158bc065 | 2566 | err = _mv88e6xxx_vtu_getnext(ps, &vlan); |
f33475bd | 2567 | if (err) |
74b6ba0d | 2568 | break; |
f33475bd VD |
2569 | |
2570 | if (!vlan.valid) | |
2571 | break; | |
2572 | ||
158bc065 | 2573 | err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port, |
74b6ba0d | 2574 | fdb, cb); |
f33475bd | 2575 | if (err) |
74b6ba0d | 2576 | break; |
f33475bd VD |
2577 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); |
2578 | ||
2579 | unlock: | |
9f8b3ee1 | 2580 | mutex_unlock(&ps->reg_lock); |
f33475bd VD |
2581 | |
2582 | return err; | |
2583 | } | |
2584 | ||
f81ec90f VD |
2585 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
2586 | struct net_device *bridge) | |
e79a8bcb | 2587 | { |
a6692754 | 2588 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1d9619d5 | 2589 | int i, err = 0; |
466dfa07 | 2590 | |
936f234a VD |
2591 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) |
2592 | return -EOPNOTSUPP; | |
2593 | ||
9f8b3ee1 | 2594 | mutex_lock(&ps->reg_lock); |
466dfa07 | 2595 | |
b7666efe | 2596 | /* Assign the bridge and remap each port's VLANTable */ |
a6692754 | 2597 | ps->ports[port].bridge_dev = bridge; |
b7666efe | 2598 | |
009a2b98 | 2599 | for (i = 0; i < ps->info->num_ports; ++i) { |
b7666efe | 2600 | if (ps->ports[i].bridge_dev == bridge) { |
158bc065 | 2601 | err = _mv88e6xxx_port_based_vlan_map(ps, i); |
b7666efe VD |
2602 | if (err) |
2603 | break; | |
2604 | } | |
2605 | } | |
2606 | ||
9f8b3ee1 | 2607 | mutex_unlock(&ps->reg_lock); |
a6692754 | 2608 | |
466dfa07 | 2609 | return err; |
e79a8bcb VD |
2610 | } |
2611 | ||
f81ec90f | 2612 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) |
66d9cd0f | 2613 | { |
a6692754 | 2614 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
b7666efe | 2615 | struct net_device *bridge = ps->ports[port].bridge_dev; |
16bfa702 | 2616 | int i; |
466dfa07 | 2617 | |
936f234a VD |
2618 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) |
2619 | return; | |
2620 | ||
9f8b3ee1 | 2621 | mutex_lock(&ps->reg_lock); |
466dfa07 | 2622 | |
b7666efe | 2623 | /* Unassign the bridge and remap each port's VLANTable */ |
a6692754 | 2624 | ps->ports[port].bridge_dev = NULL; |
b7666efe | 2625 | |
009a2b98 | 2626 | for (i = 0; i < ps->info->num_ports; ++i) |
16bfa702 | 2627 | if (i == port || ps->ports[i].bridge_dev == bridge) |
158bc065 | 2628 | if (_mv88e6xxx_port_based_vlan_map(ps, i)) |
c8b09808 AL |
2629 | netdev_warn(ds->ports[i].netdev, |
2630 | "failed to remap\n"); | |
b7666efe | 2631 | |
9f8b3ee1 | 2632 | mutex_unlock(&ps->reg_lock); |
66d9cd0f VD |
2633 | } |
2634 | ||
03a4a540 AL |
2635 | static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_priv_state *ps, |
2636 | int port, int page, int reg, int val) | |
75baacf0 PU |
2637 | { |
2638 | int ret; | |
2639 | ||
03a4a540 | 2640 | ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page); |
75baacf0 PU |
2641 | if (ret < 0) |
2642 | goto restore_page_0; | |
2643 | ||
03a4a540 | 2644 | ret = mv88e6xxx_mdio_write_indirect(ps, port, reg, val); |
75baacf0 | 2645 | restore_page_0: |
03a4a540 | 2646 | mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0); |
75baacf0 PU |
2647 | |
2648 | return ret; | |
2649 | } | |
2650 | ||
03a4a540 AL |
2651 | static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_priv_state *ps, |
2652 | int port, int page, int reg) | |
75baacf0 PU |
2653 | { |
2654 | int ret; | |
2655 | ||
03a4a540 | 2656 | ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page); |
75baacf0 PU |
2657 | if (ret < 0) |
2658 | goto restore_page_0; | |
2659 | ||
03a4a540 | 2660 | ret = mv88e6xxx_mdio_read_indirect(ps, port, reg); |
75baacf0 | 2661 | restore_page_0: |
03a4a540 | 2662 | mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0); |
75baacf0 PU |
2663 | |
2664 | return ret; | |
2665 | } | |
2666 | ||
552238b5 VD |
2667 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps) |
2668 | { | |
2669 | bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE); | |
2670 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
52638f71 | 2671 | struct gpio_desc *gpiod = ps->reset; |
552238b5 VD |
2672 | unsigned long timeout; |
2673 | int ret; | |
2674 | int i; | |
2675 | ||
2676 | /* Set all ports to the disabled state. */ | |
2677 | for (i = 0; i < ps->info->num_ports; i++) { | |
2678 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL); | |
2679 | if (ret < 0) | |
2680 | return ret; | |
2681 | ||
2682 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL, | |
2683 | ret & 0xfffc); | |
2684 | if (ret) | |
2685 | return ret; | |
2686 | } | |
2687 | ||
2688 | /* Wait for transmit queues to drain. */ | |
2689 | usleep_range(2000, 4000); | |
2690 | ||
2691 | /* If there is a gpio connected to the reset pin, toggle it */ | |
2692 | if (gpiod) { | |
2693 | gpiod_set_value_cansleep(gpiod, 1); | |
2694 | usleep_range(10000, 20000); | |
2695 | gpiod_set_value_cansleep(gpiod, 0); | |
2696 | usleep_range(10000, 20000); | |
2697 | } | |
2698 | ||
2699 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2700 | * needs to be active to support indirect phy register access | |
2701 | * through global registers 0x18 and 0x19. | |
2702 | */ | |
2703 | if (ppu_active) | |
2704 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000); | |
2705 | else | |
2706 | ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400); | |
2707 | if (ret) | |
2708 | return ret; | |
2709 | ||
2710 | /* Wait up to one second for reset to complete. */ | |
2711 | timeout = jiffies + 1 * HZ; | |
2712 | while (time_before(jiffies, timeout)) { | |
2713 | ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00); | |
2714 | if (ret < 0) | |
2715 | return ret; | |
2716 | ||
2717 | if ((ret & is_reset) == is_reset) | |
2718 | break; | |
2719 | usleep_range(1000, 2000); | |
2720 | } | |
2721 | if (time_after(jiffies, timeout)) | |
2722 | ret = -ETIMEDOUT; | |
2723 | else | |
2724 | ret = 0; | |
2725 | ||
2726 | return ret; | |
2727 | } | |
2728 | ||
158bc065 | 2729 | static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps) |
13a7ebb3 PU |
2730 | { |
2731 | int ret; | |
2732 | ||
03a4a540 AL |
2733 | ret = _mv88e6xxx_mdio_page_read(ps, REG_FIBER_SERDES, |
2734 | PAGE_FIBER_SERDES, MII_BMCR); | |
13a7ebb3 PU |
2735 | if (ret < 0) |
2736 | return ret; | |
2737 | ||
2738 | if (ret & BMCR_PDOWN) { | |
2739 | ret &= ~BMCR_PDOWN; | |
03a4a540 AL |
2740 | ret = _mv88e6xxx_mdio_page_write(ps, REG_FIBER_SERDES, |
2741 | PAGE_FIBER_SERDES, MII_BMCR, | |
2742 | ret); | |
13a7ebb3 PU |
2743 | } |
2744 | ||
2745 | return ret; | |
2746 | } | |
2747 | ||
a1a6a4d1 | 2748 | static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port) |
d827e88a | 2749 | { |
a1a6a4d1 | 2750 | struct dsa_switch *ds = ps->ds; |
f02bdffc | 2751 | int ret; |
54d792f2 | 2752 | u16 reg; |
d827e88a | 2753 | |
158bc065 AL |
2754 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2755 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2756 | mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || | |
2757 | mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) { | |
54d792f2 AL |
2758 | /* MAC Forcing register: don't force link, speed, |
2759 | * duplex or flow control state to any particular | |
2760 | * values on physical ports, but force the CPU port | |
2761 | * and all DSA ports to their maximum bandwidth and | |
2762 | * full duplex. | |
2763 | */ | |
158bc065 | 2764 | reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); |
60045cbf | 2765 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
53adc9e8 | 2766 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
54d792f2 AL |
2767 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
2768 | PORT_PCS_CTRL_LINK_UP | | |
2769 | PORT_PCS_CTRL_DUPLEX_FULL | | |
2770 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
158bc065 | 2771 | if (mv88e6xxx_6065_family(ps)) |
54d792f2 AL |
2772 | reg |= PORT_PCS_CTRL_100; |
2773 | else | |
2774 | reg |= PORT_PCS_CTRL_1000; | |
2775 | } else { | |
2776 | reg |= PORT_PCS_CTRL_UNFORCED; | |
2777 | } | |
2778 | ||
158bc065 | 2779 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2780 | PORT_PCS_CTRL, reg); |
2781 | if (ret) | |
a1a6a4d1 | 2782 | return ret; |
54d792f2 AL |
2783 | } |
2784 | ||
2785 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
2786 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
2787 | * tunneling, determine priority by looking at 802.1p and IP | |
2788 | * priority fields (IP prio has precedence), and set STP state | |
2789 | * to Forwarding. | |
2790 | * | |
2791 | * If this is the CPU link, use DSA or EDSA tagging depending | |
2792 | * on which tagging mode was configured. | |
2793 | * | |
2794 | * If this is a link to another switch, use DSA tagging mode. | |
2795 | * | |
2796 | * If this is the upstream port for this switch, enable | |
2797 | * forwarding of unknown unicasts and multicasts. | |
2798 | */ | |
2799 | reg = 0; | |
158bc065 AL |
2800 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2801 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2802 | mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || | |
2803 | mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) | |
54d792f2 AL |
2804 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
2805 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
2806 | PORT_CONTROL_STATE_FORWARDING; | |
2807 | if (dsa_is_cpu_port(ds, port)) { | |
158bc065 | 2808 | if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) |
54d792f2 | 2809 | reg |= PORT_CONTROL_DSA_TAG; |
158bc065 AL |
2810 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2811 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2812 | mv88e6xxx_6320_family(ps)) { | |
5377b802 AL |
2813 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | |
2814 | PORT_CONTROL_FORWARD_UNKNOWN | | |
c047a1f9 | 2815 | PORT_CONTROL_FORWARD_UNKNOWN_MC; |
54d792f2 AL |
2816 | } |
2817 | ||
158bc065 AL |
2818 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2819 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2820 | mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || | |
2821 | mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) { | |
57d32310 | 2822 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; |
54d792f2 AL |
2823 | } |
2824 | } | |
6083ce71 | 2825 | if (dsa_is_dsa_port(ds, port)) { |
158bc065 | 2826 | if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) |
6083ce71 | 2827 | reg |= PORT_CONTROL_DSA_TAG; |
158bc065 AL |
2828 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2829 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2830 | mv88e6xxx_6320_family(ps)) { | |
54d792f2 | 2831 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
6083ce71 AL |
2832 | } |
2833 | ||
54d792f2 AL |
2834 | if (port == dsa_upstream_port(ds)) |
2835 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
2836 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
2837 | } | |
2838 | if (reg) { | |
158bc065 | 2839 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2840 | PORT_CONTROL, reg); |
2841 | if (ret) | |
a1a6a4d1 | 2842 | return ret; |
54d792f2 AL |
2843 | } |
2844 | ||
13a7ebb3 PU |
2845 | /* If this port is connected to a SerDes, make sure the SerDes is not |
2846 | * powered down. | |
2847 | */ | |
158bc065 AL |
2848 | if (mv88e6xxx_6352_family(ps)) { |
2849 | ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); | |
13a7ebb3 | 2850 | if (ret < 0) |
a1a6a4d1 | 2851 | return ret; |
13a7ebb3 PU |
2852 | ret &= PORT_STATUS_CMODE_MASK; |
2853 | if ((ret == PORT_STATUS_CMODE_100BASE_X) || | |
2854 | (ret == PORT_STATUS_CMODE_1000BASE_X) || | |
2855 | (ret == PORT_STATUS_CMODE_SGMII)) { | |
158bc065 | 2856 | ret = mv88e6xxx_power_on_serdes(ps); |
13a7ebb3 | 2857 | if (ret < 0) |
a1a6a4d1 | 2858 | return ret; |
13a7ebb3 PU |
2859 | } |
2860 | } | |
2861 | ||
8efdda4a | 2862 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
46fbe5e5 | 2863 | * 10240 bytes, disable 802.1q tags checking, don't discard tagged or |
8efdda4a VD |
2864 | * untagged frames on this port, do a destination address lookup on all |
2865 | * received packets as usual, disable ARP mirroring and don't send a | |
2866 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
2867 | */ |
2868 | reg = 0; | |
158bc065 AL |
2869 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2870 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2871 | mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) || | |
2872 | mv88e6xxx_6185_family(ps)) | |
54d792f2 AL |
2873 | reg = PORT_CONTROL_2_MAP_DA; |
2874 | ||
158bc065 AL |
2875 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2876 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps)) | |
54d792f2 AL |
2877 | reg |= PORT_CONTROL_2_JUMBO_10240; |
2878 | ||
158bc065 | 2879 | if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) { |
54d792f2 AL |
2880 | /* Set the upstream port this port should use */ |
2881 | reg |= dsa_upstream_port(ds); | |
2882 | /* enable forwarding of unknown multicast addresses to | |
2883 | * the upstream port | |
2884 | */ | |
2885 | if (port == dsa_upstream_port(ds)) | |
2886 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2887 | } | |
2888 | ||
46fbe5e5 | 2889 | reg |= PORT_CONTROL_2_8021Q_DISABLED; |
8efdda4a | 2890 | |
54d792f2 | 2891 | if (reg) { |
158bc065 | 2892 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2893 | PORT_CONTROL_2, reg); |
2894 | if (ret) | |
a1a6a4d1 | 2895 | return ret; |
54d792f2 AL |
2896 | } |
2897 | ||
2898 | /* Port Association Vector: when learning source addresses | |
2899 | * of packets, add the address to the address database using | |
2900 | * a port bitmap that has only the bit for this port set and | |
2901 | * the other bits clear. | |
2902 | */ | |
4c7ea3c0 | 2903 | reg = 1 << port; |
996ecb82 VD |
2904 | /* Disable learning for CPU port */ |
2905 | if (dsa_is_cpu_port(ds, port)) | |
65fa4027 | 2906 | reg = 0; |
4c7ea3c0 | 2907 | |
158bc065 | 2908 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg); |
54d792f2 | 2909 | if (ret) |
a1a6a4d1 | 2910 | return ret; |
54d792f2 AL |
2911 | |
2912 | /* Egress rate control 2: disable egress rate control. */ | |
158bc065 | 2913 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2, |
54d792f2 AL |
2914 | 0x0000); |
2915 | if (ret) | |
a1a6a4d1 | 2916 | return ret; |
54d792f2 | 2917 | |
158bc065 AL |
2918 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2919 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2920 | mv88e6xxx_6320_family(ps)) { | |
54d792f2 AL |
2921 | /* Do not limit the period of time that this port can |
2922 | * be paused for by the remote end or the period of | |
2923 | * time that this port can pause the remote end. | |
2924 | */ | |
158bc065 | 2925 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2926 | PORT_PAUSE_CTRL, 0x0000); |
2927 | if (ret) | |
a1a6a4d1 | 2928 | return ret; |
54d792f2 AL |
2929 | |
2930 | /* Port ATU control: disable limiting the number of | |
2931 | * address database entries that this port is allowed | |
2932 | * to use. | |
2933 | */ | |
158bc065 | 2934 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2935 | PORT_ATU_CONTROL, 0x0000); |
2936 | /* Priority Override: disable DA, SA and VTU priority | |
2937 | * override. | |
2938 | */ | |
158bc065 | 2939 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2940 | PORT_PRI_OVERRIDE, 0x0000); |
2941 | if (ret) | |
a1a6a4d1 | 2942 | return ret; |
54d792f2 AL |
2943 | |
2944 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
2945 | * value. | |
2946 | */ | |
158bc065 | 2947 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2948 | PORT_ETH_TYPE, ETH_P_EDSA); |
2949 | if (ret) | |
a1a6a4d1 | 2950 | return ret; |
54d792f2 AL |
2951 | /* Tag Remap: use an identity 802.1p prio -> switch |
2952 | * prio mapping. | |
2953 | */ | |
158bc065 | 2954 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2955 | PORT_TAG_REGMAP_0123, 0x3210); |
2956 | if (ret) | |
a1a6a4d1 | 2957 | return ret; |
54d792f2 AL |
2958 | |
2959 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
2960 | * prio mapping. | |
2961 | */ | |
158bc065 | 2962 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2963 | PORT_TAG_REGMAP_4567, 0x7654); |
2964 | if (ret) | |
a1a6a4d1 | 2965 | return ret; |
54d792f2 AL |
2966 | } |
2967 | ||
158bc065 AL |
2968 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
2969 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
2970 | mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || | |
2971 | mv88e6xxx_6320_family(ps)) { | |
54d792f2 | 2972 | /* Rate Control: disable ingress rate limiting. */ |
158bc065 | 2973 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), |
54d792f2 AL |
2974 | PORT_RATE_CONTROL, 0x0001); |
2975 | if (ret) | |
a1a6a4d1 | 2976 | return ret; |
54d792f2 AL |
2977 | } |
2978 | ||
366f0a0f GR |
2979 | /* Port Control 1: disable trunking, disable sending |
2980 | * learning messages to this port. | |
d827e88a | 2981 | */ |
158bc065 | 2982 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a | 2983 | if (ret) |
a1a6a4d1 | 2984 | return ret; |
d827e88a | 2985 | |
207afda1 | 2986 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
2987 | * database, and allow bidirectional communication between the |
2988 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 2989 | */ |
158bc065 | 2990 | ret = _mv88e6xxx_port_fid_set(ps, port, 0); |
2db9ce1f | 2991 | if (ret) |
a1a6a4d1 | 2992 | return ret; |
2db9ce1f | 2993 | |
158bc065 | 2994 | ret = _mv88e6xxx_port_based_vlan_map(ps, port); |
d827e88a | 2995 | if (ret) |
a1a6a4d1 | 2996 | return ret; |
d827e88a GR |
2997 | |
2998 | /* Default VLAN ID and priority: don't set a default VLAN | |
2999 | * ID, and set the default packet priority to zero. | |
3000 | */ | |
158bc065 | 3001 | ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN, |
47cf1e65 | 3002 | 0x0000); |
a1a6a4d1 VD |
3003 | if (ret) |
3004 | return ret; | |
dbde9e66 | 3005 | |
dbde9e66 AL |
3006 | return 0; |
3007 | } | |
3008 | ||
08a01261 | 3009 | static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps) |
acdaffcc | 3010 | { |
b0745e87 VD |
3011 | struct dsa_switch *ds = ps->ds; |
3012 | u32 upstream_port = dsa_upstream_port(ds); | |
119477bd | 3013 | u16 reg; |
552238b5 | 3014 | int err; |
54d792f2 AL |
3015 | int i; |
3016 | ||
119477bd VD |
3017 | /* Enable the PHY Polling Unit if present, don't discard any packets, |
3018 | * and mask all interrupt sources. | |
3019 | */ | |
3020 | reg = 0; | |
3021 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) || | |
3022 | mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE)) | |
3023 | reg |= GLOBAL_CONTROL_PPU_ENABLE; | |
3024 | ||
3025 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg); | |
3026 | if (err) | |
3027 | return err; | |
3028 | ||
b0745e87 VD |
3029 | /* Configure the upstream port, and configure it as the port to which |
3030 | * ingress and egress and ARP monitor frames are to be sent. | |
3031 | */ | |
3032 | reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | | |
3033 | upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | | |
3034 | upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; | |
3035 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); | |
3036 | if (err) | |
3037 | return err; | |
3038 | ||
50484ff4 VD |
3039 | /* Disable remote management, and set the switch's DSA device number. */ |
3040 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2, | |
3041 | GLOBAL_CONTROL_2_MULTIPLE_CASCADE | | |
3042 | (ds->index & 0x1f)); | |
3043 | if (err) | |
3044 | return err; | |
3045 | ||
54d792f2 AL |
3046 | /* Set the default address aging time to 5 minutes, and |
3047 | * enable address learn messages to be sent to all message | |
3048 | * ports. | |
3049 | */ | |
158bc065 | 3050 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, |
48ace4ef AL |
3051 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); |
3052 | if (err) | |
08a01261 | 3053 | return err; |
54d792f2 AL |
3054 | |
3055 | /* Configure the IP ToS mapping registers. */ | |
158bc065 | 3056 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); |
48ace4ef | 3057 | if (err) |
08a01261 | 3058 | return err; |
158bc065 | 3059 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); |
48ace4ef | 3060 | if (err) |
08a01261 | 3061 | return err; |
158bc065 | 3062 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); |
48ace4ef | 3063 | if (err) |
08a01261 | 3064 | return err; |
158bc065 | 3065 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); |
48ace4ef | 3066 | if (err) |
08a01261 | 3067 | return err; |
158bc065 | 3068 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); |
48ace4ef | 3069 | if (err) |
08a01261 | 3070 | return err; |
158bc065 | 3071 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); |
48ace4ef | 3072 | if (err) |
08a01261 | 3073 | return err; |
158bc065 | 3074 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); |
48ace4ef | 3075 | if (err) |
08a01261 | 3076 | return err; |
158bc065 | 3077 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); |
48ace4ef | 3078 | if (err) |
08a01261 | 3079 | return err; |
54d792f2 AL |
3080 | |
3081 | /* Configure the IEEE 802.1p priority mapping register. */ | |
158bc065 | 3082 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); |
48ace4ef | 3083 | if (err) |
08a01261 | 3084 | return err; |
54d792f2 AL |
3085 | |
3086 | /* Send all frames with destination addresses matching | |
3087 | * 01:80:c2:00:00:0x to the CPU port. | |
3088 | */ | |
158bc065 | 3089 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); |
48ace4ef | 3090 | if (err) |
08a01261 | 3091 | return err; |
54d792f2 AL |
3092 | |
3093 | /* Ignore removed tag data on doubly tagged packets, disable | |
3094 | * flow control messages, force flow control priority to the | |
3095 | * highest, and send all special multicast frames to the CPU | |
3096 | * port at the highest priority. | |
3097 | */ | |
158bc065 | 3098 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, |
48ace4ef AL |
3099 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | |
3100 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
3101 | if (err) | |
08a01261 | 3102 | return err; |
54d792f2 AL |
3103 | |
3104 | /* Program the DSA routing table. */ | |
3105 | for (i = 0; i < 32; i++) { | |
3106 | int nexthop = 0x1f; | |
3107 | ||
66472fc0 AL |
3108 | if (i != ds->index && i < DSA_MAX_SWITCHES) |
3109 | nexthop = ds->rtable[i] & 0x1f; | |
54d792f2 | 3110 | |
48ace4ef | 3111 | err = _mv88e6xxx_reg_write( |
158bc065 | 3112 | ps, REG_GLOBAL2, |
48ace4ef AL |
3113 | GLOBAL2_DEVICE_MAPPING, |
3114 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
3115 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop); | |
3116 | if (err) | |
08a01261 | 3117 | return err; |
54d792f2 AL |
3118 | } |
3119 | ||
3120 | /* Clear all trunk masks. */ | |
48ace4ef | 3121 | for (i = 0; i < 8; i++) { |
158bc065 | 3122 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, |
48ace4ef AL |
3123 | 0x8000 | |
3124 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
009a2b98 | 3125 | ((1 << ps->info->num_ports) - 1)); |
48ace4ef | 3126 | if (err) |
08a01261 | 3127 | return err; |
48ace4ef | 3128 | } |
54d792f2 AL |
3129 | |
3130 | /* Clear all trunk mappings. */ | |
48ace4ef AL |
3131 | for (i = 0; i < 16; i++) { |
3132 | err = _mv88e6xxx_reg_write( | |
158bc065 | 3133 | ps, REG_GLOBAL2, |
48ace4ef AL |
3134 | GLOBAL2_TRUNK_MAPPING, |
3135 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
3136 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
3137 | if (err) | |
08a01261 | 3138 | return err; |
48ace4ef | 3139 | } |
54d792f2 | 3140 | |
158bc065 AL |
3141 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
3142 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
3143 | mv88e6xxx_6320_family(ps)) { | |
54d792f2 AL |
3144 | /* Send all frames with destination addresses matching |
3145 | * 01:80:c2:00:00:2x to the CPU port. | |
3146 | */ | |
158bc065 | 3147 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, |
48ace4ef AL |
3148 | GLOBAL2_MGMT_EN_2X, 0xffff); |
3149 | if (err) | |
08a01261 | 3150 | return err; |
54d792f2 AL |
3151 | |
3152 | /* Initialise cross-chip port VLAN table to reset | |
3153 | * defaults. | |
3154 | */ | |
158bc065 | 3155 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, |
48ace4ef AL |
3156 | GLOBAL2_PVT_ADDR, 0x9000); |
3157 | if (err) | |
08a01261 | 3158 | return err; |
54d792f2 AL |
3159 | |
3160 | /* Clear the priority override table. */ | |
48ace4ef | 3161 | for (i = 0; i < 16; i++) { |
158bc065 | 3162 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, |
48ace4ef AL |
3163 | GLOBAL2_PRIO_OVERRIDE, |
3164 | 0x8000 | (i << 8)); | |
3165 | if (err) | |
08a01261 | 3166 | return err; |
48ace4ef | 3167 | } |
54d792f2 AL |
3168 | } |
3169 | ||
158bc065 AL |
3170 | if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || |
3171 | mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || | |
3172 | mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || | |
3173 | mv88e6xxx_6320_family(ps)) { | |
54d792f2 AL |
3174 | /* Disable ingress rate limiting by resetting all |
3175 | * ingress rate limit registers to their initial | |
3176 | * state. | |
3177 | */ | |
009a2b98 | 3178 | for (i = 0; i < ps->info->num_ports; i++) { |
158bc065 | 3179 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, |
48ace4ef AL |
3180 | GLOBAL2_INGRESS_OP, |
3181 | 0x9000 | (i << 8)); | |
3182 | if (err) | |
08a01261 | 3183 | return err; |
48ace4ef | 3184 | } |
54d792f2 AL |
3185 | } |
3186 | ||
db687a56 | 3187 | /* Clear the statistics counters for all ports */ |
158bc065 | 3188 | err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, |
48ace4ef AL |
3189 | GLOBAL_STATS_OP_FLUSH_ALL); |
3190 | if (err) | |
08a01261 | 3191 | return err; |
db687a56 AL |
3192 | |
3193 | /* Wait for the flush to complete. */ | |
158bc065 | 3194 | err = _mv88e6xxx_stats_wait(ps); |
08a01261 VD |
3195 | if (err) |
3196 | return err; | |
6b17e864 | 3197 | |
c161d0a5 | 3198 | /* Clear all ATU entries */ |
158bc065 | 3199 | err = _mv88e6xxx_atu_flush(ps, 0, true); |
08a01261 VD |
3200 | if (err) |
3201 | return err; | |
c161d0a5 | 3202 | |
6b17e864 | 3203 | /* Clear all the VTU and STU entries */ |
158bc065 | 3204 | err = _mv88e6xxx_vtu_stu_flush(ps); |
08a01261 VD |
3205 | if (err < 0) |
3206 | return err; | |
3207 | ||
3208 | return err; | |
3209 | } | |
3210 | ||
f81ec90f | 3211 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 3212 | { |
a1a6a4d1 | 3213 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
08a01261 | 3214 | int err; |
a1a6a4d1 VD |
3215 | int i; |
3216 | ||
3217 | ps->ds = ds; | |
b516d453 | 3218 | ds->slave_mii_bus = ps->mdio_bus; |
08a01261 | 3219 | |
08a01261 VD |
3220 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) |
3221 | mutex_init(&ps->eeprom_mutex); | |
3222 | ||
9f8b3ee1 | 3223 | mutex_lock(&ps->reg_lock); |
08a01261 VD |
3224 | |
3225 | err = mv88e6xxx_switch_reset(ps); | |
3226 | if (err) | |
3227 | goto unlock; | |
3228 | ||
3229 | err = mv88e6xxx_setup_global(ps); | |
a1a6a4d1 VD |
3230 | if (err) |
3231 | goto unlock; | |
3232 | ||
3233 | for (i = 0; i < ps->info->num_ports; i++) { | |
3234 | err = mv88e6xxx_setup_port(ps, i); | |
3235 | if (err) | |
3236 | goto unlock; | |
3237 | } | |
08a01261 | 3238 | |
6b17e864 | 3239 | unlock: |
9f8b3ee1 | 3240 | mutex_unlock(&ps->reg_lock); |
db687a56 | 3241 | |
48ace4ef | 3242 | return err; |
54d792f2 AL |
3243 | } |
3244 | ||
57d32310 VD |
3245 | static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page, |
3246 | int reg) | |
49143585 AL |
3247 | { |
3248 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
3249 | int ret; | |
3250 | ||
9f8b3ee1 | 3251 | mutex_lock(&ps->reg_lock); |
03a4a540 | 3252 | ret = _mv88e6xxx_mdio_page_read(ps, port, page, reg); |
9f8b3ee1 | 3253 | mutex_unlock(&ps->reg_lock); |
75baacf0 | 3254 | |
49143585 AL |
3255 | return ret; |
3256 | } | |
3257 | ||
57d32310 VD |
3258 | static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page, |
3259 | int reg, int val) | |
49143585 AL |
3260 | { |
3261 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
3262 | int ret; | |
3263 | ||
9f8b3ee1 | 3264 | mutex_lock(&ps->reg_lock); |
03a4a540 | 3265 | ret = _mv88e6xxx_mdio_page_write(ps, port, page, reg, val); |
9f8b3ee1 | 3266 | mutex_unlock(&ps->reg_lock); |
75baacf0 | 3267 | |
fd3a0ee4 AL |
3268 | return ret; |
3269 | } | |
3270 | ||
03a4a540 AL |
3271 | static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_priv_state *ps, |
3272 | int port) | |
fd3a0ee4 | 3273 | { |
009a2b98 | 3274 | if (port >= 0 && port < ps->info->num_ports) |
fd3a0ee4 AL |
3275 | return port; |
3276 | return -EINVAL; | |
3277 | } | |
3278 | ||
b516d453 | 3279 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum) |
fd3a0ee4 | 3280 | { |
b516d453 | 3281 | struct mv88e6xxx_priv_state *ps = bus->priv; |
03a4a540 | 3282 | int addr = mv88e6xxx_port_to_mdio_addr(ps, port); |
fd3a0ee4 AL |
3283 | int ret; |
3284 | ||
3285 | if (addr < 0) | |
158bc065 | 3286 | return 0xffff; |
fd3a0ee4 | 3287 | |
9f8b3ee1 | 3288 | mutex_lock(&ps->reg_lock); |
8c9983a2 VD |
3289 | |
3290 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) | |
03a4a540 | 3291 | ret = mv88e6xxx_mdio_read_ppu(ps, addr, regnum); |
6d5834a1 | 3292 | else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) |
03a4a540 | 3293 | ret = mv88e6xxx_mdio_read_indirect(ps, addr, regnum); |
8c9983a2 | 3294 | else |
03a4a540 | 3295 | ret = mv88e6xxx_mdio_read_direct(ps, addr, regnum); |
8c9983a2 | 3296 | |
9f8b3ee1 | 3297 | mutex_unlock(&ps->reg_lock); |
fd3a0ee4 AL |
3298 | return ret; |
3299 | } | |
3300 | ||
b516d453 | 3301 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum, |
03a4a540 | 3302 | u16 val) |
fd3a0ee4 | 3303 | { |
b516d453 | 3304 | struct mv88e6xxx_priv_state *ps = bus->priv; |
03a4a540 | 3305 | int addr = mv88e6xxx_port_to_mdio_addr(ps, port); |
fd3a0ee4 AL |
3306 | int ret; |
3307 | ||
3308 | if (addr < 0) | |
158bc065 | 3309 | return 0xffff; |
fd3a0ee4 | 3310 | |
9f8b3ee1 | 3311 | mutex_lock(&ps->reg_lock); |
8c9983a2 VD |
3312 | |
3313 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) | |
03a4a540 | 3314 | ret = mv88e6xxx_mdio_write_ppu(ps, addr, regnum, val); |
6d5834a1 | 3315 | else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) |
03a4a540 | 3316 | ret = mv88e6xxx_mdio_write_indirect(ps, addr, regnum, val); |
8c9983a2 | 3317 | else |
03a4a540 | 3318 | ret = mv88e6xxx_mdio_write_direct(ps, addr, regnum, val); |
8c9983a2 | 3319 | |
9f8b3ee1 | 3320 | mutex_unlock(&ps->reg_lock); |
fd3a0ee4 AL |
3321 | return ret; |
3322 | } | |
3323 | ||
b516d453 AL |
3324 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_priv_state *ps, |
3325 | struct device_node *np) | |
3326 | { | |
3327 | static int index; | |
3328 | struct mii_bus *bus; | |
3329 | int err; | |
3330 | ||
3331 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) | |
3332 | mv88e6xxx_ppu_state_init(ps); | |
3333 | ||
3334 | if (np) | |
3335 | ps->mdio_np = of_get_child_by_name(np, "mdio"); | |
3336 | ||
3337 | bus = devm_mdiobus_alloc(ps->dev); | |
3338 | if (!bus) | |
3339 | return -ENOMEM; | |
3340 | ||
3341 | bus->priv = (void *)ps; | |
3342 | if (np) { | |
3343 | bus->name = np->full_name; | |
3344 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); | |
3345 | } else { | |
3346 | bus->name = "mv88e6xxx SMI"; | |
3347 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
3348 | } | |
3349 | ||
3350 | bus->read = mv88e6xxx_mdio_read; | |
3351 | bus->write = mv88e6xxx_mdio_write; | |
3352 | bus->parent = ps->dev; | |
3353 | ||
3354 | if (ps->mdio_np) | |
3355 | err = of_mdiobus_register(bus, ps->mdio_np); | |
3356 | else | |
3357 | err = mdiobus_register(bus); | |
3358 | if (err) { | |
3359 | dev_err(ps->dev, "Cannot register MDIO bus (%d)\n", err); | |
3360 | goto out; | |
3361 | } | |
3362 | ps->mdio_bus = bus; | |
3363 | ||
3364 | return 0; | |
3365 | ||
3366 | out: | |
3367 | if (ps->mdio_np) | |
3368 | of_node_put(ps->mdio_np); | |
3369 | ||
3370 | return err; | |
3371 | } | |
3372 | ||
3373 | static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_priv_state *ps) | |
3374 | ||
3375 | { | |
3376 | struct mii_bus *bus = ps->mdio_bus; | |
3377 | ||
3378 | mdiobus_unregister(bus); | |
3379 | ||
3380 | if (ps->mdio_np) | |
3381 | of_node_put(ps->mdio_np); | |
3382 | } | |
3383 | ||
c22995c5 GR |
3384 | #ifdef CONFIG_NET_DSA_HWMON |
3385 | ||
3386 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
3387 | { | |
3388 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
3389 | int ret; | |
3390 | int val; | |
3391 | ||
3392 | *temp = 0; | |
3393 | ||
9f8b3ee1 | 3394 | mutex_lock(&ps->reg_lock); |
c22995c5 | 3395 | |
03a4a540 | 3396 | ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x6); |
c22995c5 GR |
3397 | if (ret < 0) |
3398 | goto error; | |
3399 | ||
3400 | /* Enable temperature sensor */ | |
03a4a540 | 3401 | ret = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a); |
c22995c5 GR |
3402 | if (ret < 0) |
3403 | goto error; | |
3404 | ||
03a4a540 | 3405 | ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret | (1 << 5)); |
c22995c5 GR |
3406 | if (ret < 0) |
3407 | goto error; | |
3408 | ||
3409 | /* Wait for temperature to stabilize */ | |
3410 | usleep_range(10000, 12000); | |
3411 | ||
03a4a540 | 3412 | val = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a); |
c22995c5 GR |
3413 | if (val < 0) { |
3414 | ret = val; | |
3415 | goto error; | |
3416 | } | |
3417 | ||
3418 | /* Disable temperature sensor */ | |
03a4a540 | 3419 | ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret & ~(1 << 5)); |
c22995c5 GR |
3420 | if (ret < 0) |
3421 | goto error; | |
3422 | ||
3423 | *temp = ((val & 0x1f) - 5) * 5; | |
3424 | ||
3425 | error: | |
03a4a540 | 3426 | mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x0); |
9f8b3ee1 | 3427 | mutex_unlock(&ps->reg_lock); |
c22995c5 GR |
3428 | return ret; |
3429 | } | |
3430 | ||
3431 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
3432 | { | |
158bc065 AL |
3433 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3434 | int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; | |
c22995c5 GR |
3435 | int ret; |
3436 | ||
3437 | *temp = 0; | |
3438 | ||
03a4a540 | 3439 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27); |
c22995c5 GR |
3440 | if (ret < 0) |
3441 | return ret; | |
3442 | ||
3443 | *temp = (ret & 0xff) - 25; | |
3444 | ||
3445 | return 0; | |
3446 | } | |
3447 | ||
f81ec90f | 3448 | static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) |
c22995c5 | 3449 | { |
158bc065 AL |
3450 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3451 | ||
6594f615 VD |
3452 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP)) |
3453 | return -EOPNOTSUPP; | |
3454 | ||
158bc065 | 3455 | if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) |
c22995c5 GR |
3456 | return mv88e63xx_get_temp(ds, temp); |
3457 | ||
3458 | return mv88e61xx_get_temp(ds, temp); | |
3459 | } | |
3460 | ||
f81ec90f | 3461 | static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) |
c22995c5 | 3462 | { |
158bc065 AL |
3463 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3464 | int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; | |
c22995c5 GR |
3465 | int ret; |
3466 | ||
6594f615 | 3467 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3468 | return -EOPNOTSUPP; |
3469 | ||
3470 | *temp = 0; | |
3471 | ||
03a4a540 | 3472 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
c22995c5 GR |
3473 | if (ret < 0) |
3474 | return ret; | |
3475 | ||
3476 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
3477 | ||
3478 | return 0; | |
3479 | } | |
3480 | ||
f81ec90f | 3481 | static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) |
c22995c5 | 3482 | { |
158bc065 AL |
3483 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3484 | int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; | |
c22995c5 GR |
3485 | int ret; |
3486 | ||
6594f615 | 3487 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3488 | return -EOPNOTSUPP; |
3489 | ||
03a4a540 | 3490 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
c22995c5 GR |
3491 | if (ret < 0) |
3492 | return ret; | |
3493 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
03a4a540 AL |
3494 | return mv88e6xxx_mdio_page_write(ds, phy, 6, 26, |
3495 | (ret & 0xe0ff) | (temp << 8)); | |
c22995c5 GR |
3496 | } |
3497 | ||
f81ec90f | 3498 | static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) |
c22995c5 | 3499 | { |
158bc065 AL |
3500 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
3501 | int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; | |
c22995c5 GR |
3502 | int ret; |
3503 | ||
6594f615 | 3504 | if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) |
c22995c5 GR |
3505 | return -EOPNOTSUPP; |
3506 | ||
3507 | *alarm = false; | |
3508 | ||
03a4a540 | 3509 | ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); |
c22995c5 GR |
3510 | if (ret < 0) |
3511 | return ret; | |
3512 | ||
3513 | *alarm = !!(ret & 0x40); | |
3514 | ||
3515 | return 0; | |
3516 | } | |
3517 | #endif /* CONFIG_NET_DSA_HWMON */ | |
3518 | ||
f81ec90f VD |
3519 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
3520 | [MV88E6085] = { | |
3521 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, | |
3522 | .family = MV88E6XXX_FAMILY_6097, | |
3523 | .name = "Marvell 88E6085", | |
3524 | .num_databases = 4096, | |
3525 | .num_ports = 10, | |
9dddd478 | 3526 | .port_base_addr = 0x10, |
f81ec90f VD |
3527 | .flags = MV88E6XXX_FLAGS_FAMILY_6097, |
3528 | }, | |
3529 | ||
3530 | [MV88E6095] = { | |
3531 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, | |
3532 | .family = MV88E6XXX_FAMILY_6095, | |
3533 | .name = "Marvell 88E6095/88E6095F", | |
3534 | .num_databases = 256, | |
3535 | .num_ports = 11, | |
9dddd478 | 3536 | .port_base_addr = 0x10, |
f81ec90f VD |
3537 | .flags = MV88E6XXX_FLAGS_FAMILY_6095, |
3538 | }, | |
3539 | ||
3540 | [MV88E6123] = { | |
3541 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, | |
3542 | .family = MV88E6XXX_FAMILY_6165, | |
3543 | .name = "Marvell 88E6123", | |
3544 | .num_databases = 4096, | |
3545 | .num_ports = 3, | |
9dddd478 | 3546 | .port_base_addr = 0x10, |
f81ec90f VD |
3547 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
3548 | }, | |
3549 | ||
3550 | [MV88E6131] = { | |
3551 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, | |
3552 | .family = MV88E6XXX_FAMILY_6185, | |
3553 | .name = "Marvell 88E6131", | |
3554 | .num_databases = 256, | |
3555 | .num_ports = 8, | |
9dddd478 | 3556 | .port_base_addr = 0x10, |
f81ec90f VD |
3557 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
3558 | }, | |
3559 | ||
3560 | [MV88E6161] = { | |
3561 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, | |
3562 | .family = MV88E6XXX_FAMILY_6165, | |
3563 | .name = "Marvell 88E6161", | |
3564 | .num_databases = 4096, | |
3565 | .num_ports = 6, | |
9dddd478 | 3566 | .port_base_addr = 0x10, |
f81ec90f VD |
3567 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
3568 | }, | |
3569 | ||
3570 | [MV88E6165] = { | |
3571 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, | |
3572 | .family = MV88E6XXX_FAMILY_6165, | |
3573 | .name = "Marvell 88E6165", | |
3574 | .num_databases = 4096, | |
3575 | .num_ports = 6, | |
9dddd478 | 3576 | .port_base_addr = 0x10, |
f81ec90f VD |
3577 | .flags = MV88E6XXX_FLAGS_FAMILY_6165, |
3578 | }, | |
3579 | ||
3580 | [MV88E6171] = { | |
3581 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, | |
3582 | .family = MV88E6XXX_FAMILY_6351, | |
3583 | .name = "Marvell 88E6171", | |
3584 | .num_databases = 4096, | |
3585 | .num_ports = 7, | |
9dddd478 | 3586 | .port_base_addr = 0x10, |
f81ec90f VD |
3587 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
3588 | }, | |
3589 | ||
3590 | [MV88E6172] = { | |
3591 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, | |
3592 | .family = MV88E6XXX_FAMILY_6352, | |
3593 | .name = "Marvell 88E6172", | |
3594 | .num_databases = 4096, | |
3595 | .num_ports = 7, | |
9dddd478 | 3596 | .port_base_addr = 0x10, |
f81ec90f VD |
3597 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
3598 | }, | |
3599 | ||
3600 | [MV88E6175] = { | |
3601 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, | |
3602 | .family = MV88E6XXX_FAMILY_6351, | |
3603 | .name = "Marvell 88E6175", | |
3604 | .num_databases = 4096, | |
3605 | .num_ports = 7, | |
9dddd478 | 3606 | .port_base_addr = 0x10, |
f81ec90f VD |
3607 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
3608 | }, | |
3609 | ||
3610 | [MV88E6176] = { | |
3611 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, | |
3612 | .family = MV88E6XXX_FAMILY_6352, | |
3613 | .name = "Marvell 88E6176", | |
3614 | .num_databases = 4096, | |
3615 | .num_ports = 7, | |
9dddd478 | 3616 | .port_base_addr = 0x10, |
f81ec90f VD |
3617 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
3618 | }, | |
3619 | ||
3620 | [MV88E6185] = { | |
3621 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, | |
3622 | .family = MV88E6XXX_FAMILY_6185, | |
3623 | .name = "Marvell 88E6185", | |
3624 | .num_databases = 256, | |
3625 | .num_ports = 10, | |
9dddd478 | 3626 | .port_base_addr = 0x10, |
f81ec90f VD |
3627 | .flags = MV88E6XXX_FLAGS_FAMILY_6185, |
3628 | }, | |
3629 | ||
3630 | [MV88E6240] = { | |
3631 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, | |
3632 | .family = MV88E6XXX_FAMILY_6352, | |
3633 | .name = "Marvell 88E6240", | |
3634 | .num_databases = 4096, | |
3635 | .num_ports = 7, | |
9dddd478 | 3636 | .port_base_addr = 0x10, |
f81ec90f VD |
3637 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
3638 | }, | |
3639 | ||
3640 | [MV88E6320] = { | |
3641 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, | |
3642 | .family = MV88E6XXX_FAMILY_6320, | |
3643 | .name = "Marvell 88E6320", | |
3644 | .num_databases = 4096, | |
3645 | .num_ports = 7, | |
9dddd478 | 3646 | .port_base_addr = 0x10, |
f81ec90f VD |
3647 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
3648 | }, | |
3649 | ||
3650 | [MV88E6321] = { | |
3651 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, | |
3652 | .family = MV88E6XXX_FAMILY_6320, | |
3653 | .name = "Marvell 88E6321", | |
3654 | .num_databases = 4096, | |
3655 | .num_ports = 7, | |
9dddd478 | 3656 | .port_base_addr = 0x10, |
f81ec90f VD |
3657 | .flags = MV88E6XXX_FLAGS_FAMILY_6320, |
3658 | }, | |
3659 | ||
3660 | [MV88E6350] = { | |
3661 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, | |
3662 | .family = MV88E6XXX_FAMILY_6351, | |
3663 | .name = "Marvell 88E6350", | |
3664 | .num_databases = 4096, | |
3665 | .num_ports = 7, | |
9dddd478 | 3666 | .port_base_addr = 0x10, |
f81ec90f VD |
3667 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
3668 | }, | |
3669 | ||
3670 | [MV88E6351] = { | |
3671 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, | |
3672 | .family = MV88E6XXX_FAMILY_6351, | |
3673 | .name = "Marvell 88E6351", | |
3674 | .num_databases = 4096, | |
3675 | .num_ports = 7, | |
9dddd478 | 3676 | .port_base_addr = 0x10, |
f81ec90f VD |
3677 | .flags = MV88E6XXX_FLAGS_FAMILY_6351, |
3678 | }, | |
3679 | ||
3680 | [MV88E6352] = { | |
3681 | .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, | |
3682 | .family = MV88E6XXX_FAMILY_6352, | |
3683 | .name = "Marvell 88E6352", | |
3684 | .num_databases = 4096, | |
3685 | .num_ports = 7, | |
9dddd478 | 3686 | .port_base_addr = 0x10, |
f81ec90f VD |
3687 | .flags = MV88E6XXX_FLAGS_FAMILY_6352, |
3688 | }, | |
3689 | }; | |
3690 | ||
5f7c0367 | 3691 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 3692 | { |
a439c061 | 3693 | int i; |
b9b37713 | 3694 | |
5f7c0367 VD |
3695 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
3696 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
3697 | return &mv88e6xxx_table[i]; | |
b9b37713 | 3698 | |
b9b37713 VD |
3699 | return NULL; |
3700 | } | |
3701 | ||
bc46a3d5 VD |
3702 | static int mv88e6xxx_detect(struct mv88e6xxx_priv_state *ps) |
3703 | { | |
3704 | const struct mv88e6xxx_info *info; | |
3705 | int id, prod_num, rev; | |
3706 | ||
9dddd478 | 3707 | id = mv88e6xxx_reg_read(ps, ps->info->port_base_addr, PORT_SWITCH_ID); |
bc46a3d5 VD |
3708 | if (id < 0) |
3709 | return id; | |
3710 | ||
3711 | prod_num = (id & 0xfff0) >> 4; | |
3712 | rev = id & 0x000f; | |
3713 | ||
3714 | info = mv88e6xxx_lookup_info(prod_num); | |
3715 | if (!info) | |
3716 | return -ENODEV; | |
3717 | ||
caac8545 | 3718 | /* Update the compatible info with the probed one */ |
bc46a3d5 VD |
3719 | ps->info = info; |
3720 | ||
3721 | dev_info(ps->dev, "switch 0x%x detected: %s, revision %u\n", | |
3722 | ps->info->prod_num, ps->info->name, rev); | |
3723 | ||
3724 | return 0; | |
3725 | } | |
3726 | ||
469d729f VD |
3727 | static struct mv88e6xxx_priv_state *mv88e6xxx_alloc_chip(struct device *dev) |
3728 | { | |
3729 | struct mv88e6xxx_priv_state *ps; | |
3730 | ||
3731 | ps = devm_kzalloc(dev, sizeof(*ps), GFP_KERNEL); | |
3732 | if (!ps) | |
3733 | return NULL; | |
3734 | ||
3735 | ps->dev = dev; | |
3736 | ||
3737 | mutex_init(&ps->reg_lock); | |
3738 | ||
3739 | return ps; | |
3740 | } | |
3741 | ||
4a70c4ab VD |
3742 | static int mv88e6xxx_smi_init(struct mv88e6xxx_priv_state *ps, |
3743 | struct mii_bus *bus, int sw_addr) | |
3744 | { | |
3745 | /* ADDR[0] pin is unavailable externally and considered zero */ | |
3746 | if (sw_addr & 0x1) | |
3747 | return -EINVAL; | |
3748 | ||
914b32f6 VD |
3749 | if (sw_addr == 0) |
3750 | ps->smi_ops = &mv88e6xxx_smi_single_chip_ops; | |
3751 | else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_MULTI_CHIP)) | |
3752 | ps->smi_ops = &mv88e6xxx_smi_multi_chip_ops; | |
3753 | else | |
3754 | return -EINVAL; | |
3755 | ||
4a70c4ab VD |
3756 | ps->bus = bus; |
3757 | ps->sw_addr = sw_addr; | |
3758 | ||
3759 | return 0; | |
3760 | } | |
3761 | ||
fcdce7d0 AL |
3762 | static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, |
3763 | struct device *host_dev, int sw_addr, | |
3764 | void **priv) | |
a77d43f1 AL |
3765 | { |
3766 | struct mv88e6xxx_priv_state *ps; | |
a439c061 | 3767 | struct mii_bus *bus; |
b516d453 | 3768 | int err; |
a77d43f1 | 3769 | |
a439c061 | 3770 | bus = dsa_host_dev_to_mii_bus(host_dev); |
c156913b AL |
3771 | if (!bus) |
3772 | return NULL; | |
3773 | ||
469d729f VD |
3774 | ps = mv88e6xxx_alloc_chip(dsa_dev); |
3775 | if (!ps) | |
3776 | return NULL; | |
3777 | ||
caac8545 VD |
3778 | /* Legacy SMI probing will only support chips similar to 88E6085 */ |
3779 | ps->info = &mv88e6xxx_table[MV88E6085]; | |
3780 | ||
4a70c4ab VD |
3781 | err = mv88e6xxx_smi_init(ps, bus, sw_addr); |
3782 | if (err) | |
3783 | goto free; | |
3784 | ||
bc46a3d5 VD |
3785 | err = mv88e6xxx_detect(ps); |
3786 | if (err) | |
469d729f | 3787 | goto free; |
a439c061 | 3788 | |
b516d453 AL |
3789 | err = mv88e6xxx_mdio_register(ps, NULL); |
3790 | if (err) | |
469d729f | 3791 | goto free; |
b516d453 | 3792 | |
a439c061 VD |
3793 | *priv = ps; |
3794 | ||
bc46a3d5 | 3795 | return ps->info->name; |
469d729f VD |
3796 | free: |
3797 | devm_kfree(dsa_dev, ps); | |
3798 | ||
3799 | return NULL; | |
a77d43f1 AL |
3800 | } |
3801 | ||
57d32310 | 3802 | static struct dsa_switch_driver mv88e6xxx_switch_driver = { |
f81ec90f | 3803 | .tag_protocol = DSA_TAG_PROTO_EDSA, |
fcdce7d0 | 3804 | .probe = mv88e6xxx_drv_probe, |
f81ec90f VD |
3805 | .setup = mv88e6xxx_setup, |
3806 | .set_addr = mv88e6xxx_set_addr, | |
f81ec90f VD |
3807 | .adjust_link = mv88e6xxx_adjust_link, |
3808 | .get_strings = mv88e6xxx_get_strings, | |
3809 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
3810 | .get_sset_count = mv88e6xxx_get_sset_count, | |
3811 | .set_eee = mv88e6xxx_set_eee, | |
3812 | .get_eee = mv88e6xxx_get_eee, | |
3813 | #ifdef CONFIG_NET_DSA_HWMON | |
3814 | .get_temp = mv88e6xxx_get_temp, | |
3815 | .get_temp_limit = mv88e6xxx_get_temp_limit, | |
3816 | .set_temp_limit = mv88e6xxx_set_temp_limit, | |
3817 | .get_temp_alarm = mv88e6xxx_get_temp_alarm, | |
3818 | #endif | |
f8cd8753 | 3819 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
3820 | .get_eeprom = mv88e6xxx_get_eeprom, |
3821 | .set_eeprom = mv88e6xxx_set_eeprom, | |
3822 | .get_regs_len = mv88e6xxx_get_regs_len, | |
3823 | .get_regs = mv88e6xxx_get_regs, | |
3824 | .port_bridge_join = mv88e6xxx_port_bridge_join, | |
3825 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
3826 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, | |
3827 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, | |
3828 | .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, | |
3829 | .port_vlan_add = mv88e6xxx_port_vlan_add, | |
3830 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
3831 | .port_vlan_dump = mv88e6xxx_port_vlan_dump, | |
3832 | .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, | |
3833 | .port_fdb_add = mv88e6xxx_port_fdb_add, | |
3834 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
3835 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
3836 | }; | |
3837 | ||
b7e66a5f VD |
3838 | static int mv88e6xxx_register_switch(struct mv88e6xxx_priv_state *ps, |
3839 | struct device_node *np) | |
3840 | { | |
3841 | struct device *dev = ps->dev; | |
3842 | struct dsa_switch *ds; | |
3843 | ||
3844 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); | |
3845 | if (!ds) | |
3846 | return -ENOMEM; | |
3847 | ||
3848 | ds->dev = dev; | |
3849 | ds->priv = ps; | |
3850 | ds->drv = &mv88e6xxx_switch_driver; | |
3851 | ||
3852 | dev_set_drvdata(dev, ds); | |
3853 | ||
3854 | return dsa_register_switch(ds, np); | |
3855 | } | |
3856 | ||
3857 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_priv_state *ps) | |
3858 | { | |
3859 | dsa_unregister_switch(ps->ds); | |
3860 | } | |
3861 | ||
57d32310 | 3862 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 3863 | { |
14c7b3c3 | 3864 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 3865 | struct device_node *np = dev->of_node; |
caac8545 | 3866 | const struct mv88e6xxx_info *compat_info; |
14c7b3c3 | 3867 | struct mv88e6xxx_priv_state *ps; |
f8cd8753 | 3868 | u32 eeprom_len; |
52638f71 | 3869 | int err; |
14c7b3c3 | 3870 | |
caac8545 VD |
3871 | compat_info = of_device_get_match_data(dev); |
3872 | if (!compat_info) | |
3873 | return -EINVAL; | |
3874 | ||
469d729f | 3875 | ps = mv88e6xxx_alloc_chip(dev); |
b7e66a5f | 3876 | if (!ps) |
14c7b3c3 AL |
3877 | return -ENOMEM; |
3878 | ||
caac8545 VD |
3879 | ps->info = compat_info; |
3880 | ||
4a70c4ab VD |
3881 | err = mv88e6xxx_smi_init(ps, mdiodev->bus, mdiodev->addr); |
3882 | if (err) | |
3883 | return err; | |
14c7b3c3 | 3884 | |
bc46a3d5 VD |
3885 | err = mv88e6xxx_detect(ps); |
3886 | if (err) | |
3887 | return err; | |
14c7b3c3 | 3888 | |
c6d19ab6 VD |
3889 | ps->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); |
3890 | if (IS_ERR(ps->reset)) | |
3891 | return PTR_ERR(ps->reset); | |
52638f71 | 3892 | |
f8cd8753 AL |
3893 | if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) && |
3894 | !of_property_read_u32(np, "eeprom-length", &eeprom_len)) | |
3895 | ps->eeprom_len = eeprom_len; | |
3896 | ||
aa8ac396 | 3897 | err = mv88e6xxx_mdio_register(ps, np); |
b516d453 AL |
3898 | if (err) |
3899 | return err; | |
3900 | ||
b7e66a5f | 3901 | err = mv88e6xxx_register_switch(ps, np); |
83c0afae AL |
3902 | if (err) { |
3903 | mv88e6xxx_mdio_unregister(ps); | |
3904 | return err; | |
3905 | } | |
3906 | ||
98e67308 BH |
3907 | return 0; |
3908 | } | |
14c7b3c3 AL |
3909 | |
3910 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
3911 | { | |
3912 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
3913 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
3914 | ||
b7e66a5f | 3915 | mv88e6xxx_unregister_switch(ps); |
b516d453 | 3916 | mv88e6xxx_mdio_unregister(ps); |
14c7b3c3 AL |
3917 | } |
3918 | ||
3919 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
3920 | { |
3921 | .compatible = "marvell,mv88e6085", | |
3922 | .data = &mv88e6xxx_table[MV88E6085], | |
3923 | }, | |
14c7b3c3 AL |
3924 | { /* sentinel */ }, |
3925 | }; | |
3926 | ||
3927 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
3928 | ||
3929 | static struct mdio_driver mv88e6xxx_driver = { | |
3930 | .probe = mv88e6xxx_probe, | |
3931 | .remove = mv88e6xxx_remove, | |
3932 | .mdiodrv.driver = { | |
3933 | .name = "mv88e6085", | |
3934 | .of_match_table = mv88e6xxx_of_match, | |
3935 | }, | |
3936 | }; | |
3937 | ||
3938 | static int __init mv88e6xxx_init(void) | |
3939 | { | |
3940 | register_switch_driver(&mv88e6xxx_switch_driver); | |
3941 | return mdio_driver_register(&mv88e6xxx_driver); | |
3942 | } | |
98e67308 BH |
3943 | module_init(mv88e6xxx_init); |
3944 | ||
3945 | static void __exit mv88e6xxx_cleanup(void) | |
3946 | { | |
14c7b3c3 | 3947 | mdio_driver_unregister(&mv88e6xxx_driver); |
f81ec90f | 3948 | unregister_switch_driver(&mv88e6xxx_switch_driver); |
98e67308 BH |
3949 | } |
3950 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
3951 | |
3952 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
3953 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
3954 | MODULE_LICENSE("GPL"); |