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91da11f8 | 1 | /* |
0d3cd4b6 VD |
2 | * Marvell 88e6xxx common definitions |
3 | * | |
91da11f8 LB |
4 | * Copyright (c) 2008 Marvell Semiconductor |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __MV88E6XXX_H | |
13 | #define __MV88E6XXX_H | |
14 | ||
194fea7b | 15 | #include <linux/if_vlan.h> |
dc30c35b | 16 | #include <linux/irq.h> |
52638f71 | 17 | #include <linux/gpio/consumer.h> |
4d56a29f | 18 | #include <linux/phy.h> |
194fea7b | 19 | |
80c4627b AL |
20 | #ifndef UINT64_MAX |
21 | #define UINT64_MAX (u64)(~((u64)0)) | |
22 | #endif | |
23 | ||
cca8b133 AL |
24 | #define SMI_CMD 0x00 |
25 | #define SMI_CMD_BUSY BIT(15) | |
26 | #define SMI_CMD_CLAUSE_22 BIT(12) | |
27 | #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
28 | #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
29 | #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) | |
30 | #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) | |
31 | #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) | |
32 | #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) | |
33 | #define SMI_DATA 0x01 | |
b2eb0662 | 34 | |
09cb7dfd VD |
35 | /* PHY Registers */ |
36 | #define PHY_PAGE 0x16 | |
37 | #define PHY_PAGE_COPPER 0x00 | |
38 | ||
39 | #define ADDR_SERDES 0x0f | |
40 | #define SERDES_PAGE_FIBER 0x01 | |
13a7ebb3 | 41 | |
cca8b133 AL |
42 | #define PORT_STATUS 0x00 |
43 | #define PORT_STATUS_PAUSE_EN BIT(15) | |
44 | #define PORT_STATUS_MY_PAUSE BIT(14) | |
45 | #define PORT_STATUS_HD_FLOW BIT(13) | |
46 | #define PORT_STATUS_PHY_DETECT BIT(12) | |
47 | #define PORT_STATUS_LINK BIT(11) | |
48 | #define PORT_STATUS_DUPLEX BIT(10) | |
49 | #define PORT_STATUS_SPEED_MASK 0x0300 | |
50 | #define PORT_STATUS_SPEED_10 0x0000 | |
51 | #define PORT_STATUS_SPEED_100 0x0100 | |
52 | #define PORT_STATUS_SPEED_1000 0x0200 | |
53 | #define PORT_STATUS_EEE BIT(6) /* 6352 */ | |
54 | #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ | |
55 | #define PORT_STATUS_MGMII BIT(6) /* 6185 */ | |
56 | #define PORT_STATUS_TX_PAUSED BIT(5) | |
57 | #define PORT_STATUS_FLOW_CTRL BIT(4) | |
13a7ebb3 PU |
58 | #define PORT_STATUS_CMODE_MASK 0x0f |
59 | #define PORT_STATUS_CMODE_100BASE_X 0x8 | |
60 | #define PORT_STATUS_CMODE_1000BASE_X 0x9 | |
61 | #define PORT_STATUS_CMODE_SGMII 0xa | |
f39908d3 AL |
62 | #define PORT_STATUS_CMODE_2500BASEX 0xb |
63 | #define PORT_STATUS_CMODE_XAUI 0xc | |
64 | #define PORT_STATUS_CMODE_RXAUI 0xd | |
cca8b133 | 65 | #define PORT_PCS_CTRL 0x01 |
e7e72ac0 AL |
66 | #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) |
67 | #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) | |
96a2b40c VD |
68 | #define PORT_PCS_CTRL_FORCE_SPEED BIT(13) /* 6390 */ |
69 | #define PORT_PCS_CTRL_ALTSPEED BIT(12) /* 6390 */ | |
70 | #define PORT_PCS_CTRL_200BASE BIT(12) /* 6352 */ | |
54d792f2 AL |
71 | #define PORT_PCS_CTRL_FC BIT(7) |
72 | #define PORT_PCS_CTRL_FORCE_FC BIT(6) | |
73 | #define PORT_PCS_CTRL_LINK_UP BIT(5) | |
74 | #define PORT_PCS_CTRL_FORCE_LINK BIT(4) | |
75 | #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) | |
76 | #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) | |
96a2b40c VD |
77 | #define PORT_PCS_CTRL_SPEED_MASK (0x03) |
78 | #define PORT_PCS_CTRL_SPEED_10 (0x00) | |
79 | #define PORT_PCS_CTRL_SPEED_100 (0x01) | |
80 | #define PORT_PCS_CTRL_SPEED_200 (0x02) /* 6065 and non Gb chips */ | |
81 | #define PORT_PCS_CTRL_SPEED_1000 (0x02) | |
82 | #define PORT_PCS_CTRL_SPEED_10000 (0x03) /* 6390X */ | |
83 | #define PORT_PCS_CTRL_SPEED_UNFORCED (0x03) | |
54d792f2 | 84 | #define PORT_PAUSE_CTRL 0x02 |
3ce0e65e AL |
85 | #define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15)) |
86 | #define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15)) | |
cca8b133 | 87 | #define PORT_SWITCH_ID 0x03 |
f6271e67 VD |
88 | #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a |
89 | #define PORT_SWITCH_ID_PROD_NUM_6095 0x095 | |
7d381a02 | 90 | #define PORT_SWITCH_ID_PROD_NUM_6097 0x099 |
f6271e67 VD |
91 | #define PORT_SWITCH_ID_PROD_NUM_6131 0x106 |
92 | #define PORT_SWITCH_ID_PROD_NUM_6320 0x115 | |
93 | #define PORT_SWITCH_ID_PROD_NUM_6123 0x121 | |
1558727a | 94 | #define PORT_SWITCH_ID_PROD_NUM_6141 0x340 |
f6271e67 VD |
95 | #define PORT_SWITCH_ID_PROD_NUM_6161 0x161 |
96 | #define PORT_SWITCH_ID_PROD_NUM_6165 0x165 | |
97 | #define PORT_SWITCH_ID_PROD_NUM_6171 0x171 | |
98 | #define PORT_SWITCH_ID_PROD_NUM_6172 0x172 | |
99 | #define PORT_SWITCH_ID_PROD_NUM_6175 0x175 | |
100 | #define PORT_SWITCH_ID_PROD_NUM_6176 0x176 | |
101 | #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 | |
1a3b39ec AL |
102 | #define PORT_SWITCH_ID_PROD_NUM_6190 0x190 |
103 | #define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0 | |
104 | #define PORT_SWITCH_ID_PROD_NUM_6191 0x191 | |
f6271e67 | 105 | #define PORT_SWITCH_ID_PROD_NUM_6240 0x240 |
1a3b39ec | 106 | #define PORT_SWITCH_ID_PROD_NUM_6290 0x290 |
f6271e67 | 107 | #define PORT_SWITCH_ID_PROD_NUM_6321 0x310 |
a75961d0 | 108 | #define PORT_SWITCH_ID_PROD_NUM_6341 0x341 |
f6271e67 VD |
109 | #define PORT_SWITCH_ID_PROD_NUM_6352 0x352 |
110 | #define PORT_SWITCH_ID_PROD_NUM_6350 0x371 | |
111 | #define PORT_SWITCH_ID_PROD_NUM_6351 0x375 | |
1a3b39ec AL |
112 | #define PORT_SWITCH_ID_PROD_NUM_6390 0x390 |
113 | #define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1 | |
cca8b133 | 114 | #define PORT_CONTROL 0x04 |
54d792f2 AL |
115 | #define PORT_CONTROL_USE_CORE_TAG BIT(15) |
116 | #define PORT_CONTROL_DROP_ON_LOCK BIT(14) | |
117 | #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) | |
118 | #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) | |
119 | #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) | |
120 | #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) | |
56995cbc | 121 | #define PORT_CONTROL_EGRESS_MASK (0x3 << 12) |
54d792f2 AL |
122 | #define PORT_CONTROL_HEADER BIT(11) |
123 | #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) | |
124 | #define PORT_CONTROL_DOUBLE_TAG BIT(9) | |
125 | #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) | |
126 | #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) | |
127 | #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) | |
128 | #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) | |
56995cbc | 129 | #define PORT_CONTROL_FRAME_MASK (0x3 << 8) |
54d792f2 AL |
130 | #define PORT_CONTROL_DSA_TAG BIT(8) |
131 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) | |
132 | #define PORT_CONTROL_TAG_IF_BOTH BIT(6) | |
133 | #define PORT_CONTROL_USE_IP BIT(5) | |
134 | #define PORT_CONTROL_USE_TAG BIT(4) | |
135 | #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) | |
136 | #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) | |
56995cbc AL |
137 | #define PORT_CONTROL_NOT_EGRESS_UNKNOWN_DA (0x0 << 2) |
138 | #define PORT_CONTROL_NOT_EGRESS_UNKNOWN_MULTICAST_DA (0x1 << 2) | |
139 | #define PORT_CONTROL_NOT_EGRESS_UNKNOWN_UNITCAST_DA (0x2 << 2) | |
140 | #define PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA (0x3 << 2) | |
cca8b133 AL |
141 | #define PORT_CONTROL_STATE_MASK 0x03 |
142 | #define PORT_CONTROL_STATE_DISABLED 0x00 | |
143 | #define PORT_CONTROL_STATE_BLOCKING 0x01 | |
144 | #define PORT_CONTROL_STATE_LEARNING 0x02 | |
145 | #define PORT_CONTROL_STATE_FORWARDING 0x03 | |
146 | #define PORT_CONTROL_1 0x05 | |
ea698f4f | 147 | #define PORT_CONTROL_1_MESSAGE_PORT BIT(15) |
2db9ce1f | 148 | #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) |
cca8b133 | 149 | #define PORT_BASE_VLAN 0x06 |
2db9ce1f | 150 | #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) |
cca8b133 | 151 | #define PORT_DEFAULT_VLAN 0x07 |
b8fee957 | 152 | #define PORT_DEFAULT_VLAN_MASK 0xfff |
cca8b133 | 153 | #define PORT_CONTROL_2 0x08 |
54d792f2 AL |
154 | #define PORT_CONTROL_2_IGNORE_FCS BIT(15) |
155 | #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) | |
156 | #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) | |
157 | #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) | |
158 | #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) | |
159 | #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) | |
160 | #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) | |
8efdda4a VD |
161 | #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) |
162 | #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) | |
163 | #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) | |
164 | #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) | |
165 | #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) | |
54d792f2 AL |
166 | #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) |
167 | #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) | |
168 | #define PORT_CONTROL_2_MAP_DA BIT(7) | |
169 | #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) | |
170 | #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) | |
171 | #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) | |
172 | #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) | |
a23b2961 | 173 | #define PORT_CONTROL_2_UPSTREAM_MASK 0x0f |
cca8b133 AL |
174 | #define PORT_RATE_CONTROL 0x09 |
175 | #define PORT_RATE_CONTROL_2 0x0a | |
176 | #define PORT_ASSOC_VECTOR 0x0b | |
4c7ea3c0 AL |
177 | #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) |
178 | #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) | |
179 | #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) | |
180 | #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) | |
181 | #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) | |
54d792f2 AL |
182 | #define PORT_ATU_CONTROL 0x0c |
183 | #define PORT_PRI_OVERRIDE 0x0d | |
184 | #define PORT_ETH_TYPE 0x0f | |
cca8b133 AL |
185 | #define PORT_IN_DISCARD_LO 0x10 |
186 | #define PORT_IN_DISCARD_HI 0x11 | |
187 | #define PORT_IN_FILTERED 0x12 | |
188 | #define PORT_OUT_FILTERED 0x13 | |
54d792f2 AL |
189 | #define PORT_TAG_REGMAP_0123 0x18 |
190 | #define PORT_TAG_REGMAP_4567 0x19 | |
ef0a7318 AL |
191 | #define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */ |
192 | #define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15) | |
193 | #define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12) | |
194 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12) | |
195 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12) | |
196 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12) | |
197 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12) | |
198 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12) | |
199 | #define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12) | |
200 | #define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9 | |
facd95b2 | 201 | |
cca8b133 AL |
202 | #define GLOBAL_STATUS 0x00 |
203 | #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ | |
17e708ba VD |
204 | #define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */ |
205 | #define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14) | |
206 | #define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14) | |
207 | #define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14) | |
208 | #define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14) | |
209 | #define GLOBAL_STATUS_INIT_READY BIT(11) | |
dc30c35b AL |
210 | #define GLOBAL_STATUS_IRQ_AVB 8 |
211 | #define GLOBAL_STATUS_IRQ_DEVICE 7 | |
212 | #define GLOBAL_STATUS_IRQ_STATS 6 | |
213 | #define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5 | |
214 | #define GLOBAL_STATUS_IRQ_VTU_DONE 4 | |
215 | #define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3 | |
216 | #define GLOBAL_STATUS_IRQ_ATU_DONE 2 | |
217 | #define GLOBAL_STATUS_IRQ_TCAM_DONE 1 | |
218 | #define GLOBAL_STATUS_IRQ_EEPROM_DONE 0 | |
cca8b133 AL |
219 | #define GLOBAL_MAC_01 0x01 |
220 | #define GLOBAL_MAC_23 0x02 | |
221 | #define GLOBAL_MAC_45 0x03 | |
6dc10bbc VD |
222 | #define GLOBAL_ATU_FID 0x01 |
223 | #define GLOBAL_VTU_FID 0x02 | |
b8fee957 VD |
224 | #define GLOBAL_VTU_FID_MASK 0xfff |
225 | #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ | |
226 | #define GLOBAL_VTU_SID_MASK 0x3f | |
cca8b133 AL |
227 | #define GLOBAL_CONTROL 0x04 |
228 | #define GLOBAL_CONTROL_SW_RESET BIT(15) | |
229 | #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) | |
230 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ | |
231 | #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ | |
232 | #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ | |
54d792f2 | 233 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
cca8b133 AL |
234 | #define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
235 | #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) | |
236 | #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) | |
237 | #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) | |
238 | #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) | |
239 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) | |
240 | #define GLOBAL_CONTROL_TCAM_EN BIT(1) | |
241 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) | |
242 | #define GLOBAL_VTU_OP 0x05 | |
6b17e864 VD |
243 | #define GLOBAL_VTU_OP_BUSY BIT(15) |
244 | #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) | |
7dad08d7 | 245 | #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
b8fee957 | 246 | #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
0d3b33e6 VD |
247 | #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
248 | #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) | |
cca8b133 | 249 | #define GLOBAL_VTU_VID 0x06 |
b8fee957 VD |
250 | #define GLOBAL_VTU_VID_MASK 0xfff |
251 | #define GLOBAL_VTU_VID_VALID BIT(12) | |
cca8b133 AL |
252 | #define GLOBAL_VTU_DATA_0_3 0x07 |
253 | #define GLOBAL_VTU_DATA_4_7 0x08 | |
254 | #define GLOBAL_VTU_DATA_8_11 0x09 | |
b8fee957 VD |
255 | #define GLOBAL_VTU_STU_DATA_MASK 0x03 |
256 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 | |
257 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 | |
258 | #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 | |
259 | #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 | |
0d3b33e6 VD |
260 | #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
261 | #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 | |
262 | #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 | |
263 | #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 | |
cca8b133 | 264 | #define GLOBAL_ATU_CONTROL 0x0a |
54d792f2 | 265 | #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
cca8b133 AL |
266 | #define GLOBAL_ATU_OP 0x0b |
267 | #define GLOBAL_ATU_OP_BUSY BIT(15) | |
268 | #define GLOBAL_ATU_OP_NOP (0 << 12) | |
7fb5e755 VD |
269 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
270 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) | |
cca8b133 AL |
271 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
272 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) | |
7fb5e755 VD |
273 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
274 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) | |
cca8b133 AL |
275 | #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
276 | #define GLOBAL_ATU_DATA 0x0c | |
8a0a265d | 277 | #define GLOBAL_ATU_DATA_TRUNK BIT(15) |
fd231c82 VD |
278 | #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
279 | #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 | |
8a0a265d AL |
280 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
281 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 | |
cca8b133 AL |
282 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
283 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 | |
284 | #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d | |
285 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e | |
286 | #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f | |
287 | #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 | |
288 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 | |
289 | #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e | |
290 | #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f | |
291 | #define GLOBAL_ATU_MAC_01 0x0d | |
292 | #define GLOBAL_ATU_MAC_23 0x0e | |
293 | #define GLOBAL_ATU_MAC_45 0x0f | |
294 | #define GLOBAL_IP_PRI_0 0x10 | |
295 | #define GLOBAL_IP_PRI_1 0x11 | |
296 | #define GLOBAL_IP_PRI_2 0x12 | |
297 | #define GLOBAL_IP_PRI_3 0x13 | |
298 | #define GLOBAL_IP_PRI_4 0x14 | |
299 | #define GLOBAL_IP_PRI_5 0x15 | |
300 | #define GLOBAL_IP_PRI_6 0x16 | |
301 | #define GLOBAL_IP_PRI_7 0x17 | |
302 | #define GLOBAL_IEEE_PRI 0x18 | |
303 | #define GLOBAL_CORE_TAG_TYPE 0x19 | |
304 | #define GLOBAL_MONITOR_CONTROL 0x1a | |
15966a2a | 305 | #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
33641994 | 306 | #define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12) |
15966a2a | 307 | #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 |
33641994 | 308 | #define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8) |
15966a2a | 309 | #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 |
33641994 | 310 | #define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4) |
15966a2a AL |
311 | #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 |
312 | #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) | |
33641994 AL |
313 | #define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15) |
314 | #define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8) | |
315 | #define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8) | |
316 | #define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8) | |
317 | #define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8) | |
318 | #define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8) | |
319 | #define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8) | |
320 | #define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8) | |
cca8b133 | 321 | #define GLOBAL_CONTROL_2 0x1c |
15966a2a AL |
322 | #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
323 | #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 | |
79523473 AL |
324 | #define GLOBAL_CONTROL_2_HIST_RX (0x1 << 6) |
325 | #define GLOBAL_CONTROL_2_HIST_TX (0x2 << 6) | |
326 | #define GLOBAL_CONTROL_2_HIST_RX_TX (0x3 << 6) | |
cca8b133 AL |
327 | #define GLOBAL_STATS_OP 0x1d |
328 | #define GLOBAL_STATS_OP_BUSY BIT(15) | |
329 | #define GLOBAL_STATS_OP_NOP (0 << 12) | |
330 | #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) | |
331 | #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) | |
332 | #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) | |
333 | #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) | |
334 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) | |
335 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) | |
336 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) | |
e0d8b615 AL |
337 | #define GLOBAL_STATS_OP_BANK_1_BIT_9 BIT(9) |
338 | #define GLOBAL_STATS_OP_BANK_1_BIT_10 BIT(10) | |
cca8b133 AL |
339 | #define GLOBAL_STATS_COUNTER_32 0x1e |
340 | #define GLOBAL_STATS_COUNTER_01 0x1f | |
defb05b9 | 341 | |
cca8b133 | 342 | #define GLOBAL2_INT_SOURCE 0x00 |
fcd25166 | 343 | #define GLOBAL2_INT_SOURCE_WATCHDOG 15 |
cca8b133 AL |
344 | #define GLOBAL2_INT_MASK 0x01 |
345 | #define GLOBAL2_MGMT_EN_2X 0x02 | |
346 | #define GLOBAL2_MGMT_EN_0X 0x03 | |
347 | #define GLOBAL2_FLOW_CONTROL 0x04 | |
348 | #define GLOBAL2_SWITCH_MGMT 0x05 | |
54d792f2 AL |
349 | #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) |
350 | #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) | |
351 | #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) | |
352 | #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) | |
353 | #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) | |
cca8b133 | 354 | #define GLOBAL2_DEVICE_MAPPING 0x06 |
54d792f2 AL |
355 | #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) |
356 | #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 | |
d35bd876 | 357 | #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f |
cca8b133 | 358 | #define GLOBAL2_TRUNK_MASK 0x07 |
54d792f2 AL |
359 | #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) |
360 | #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 | |
5154041f | 361 | #define GLOBAL2_TRUNK_MASK_HASK BIT(11) |
cca8b133 | 362 | #define GLOBAL2_TRUNK_MAPPING 0x08 |
54d792f2 AL |
363 | #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) |
364 | #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 | |
8ec61c7f VD |
365 | #define GLOBAL2_IRL_CMD 0x09 |
366 | #define GLOBAL2_IRL_CMD_BUSY BIT(15) | |
367 | #define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
368 | #define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
369 | #define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
370 | #define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY) | |
371 | #define GLOBAL2_IRL_DATA 0x0a | |
cca8b133 | 372 | #define GLOBAL2_PVT_ADDR 0x0b |
63ed880d VD |
373 | #define GLOBAL2_PVT_ADDR_BUSY BIT(15) |
374 | #define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
375 | #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
376 | #define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY) | |
cca8b133 AL |
377 | #define GLOBAL2_PVT_DATA 0x0c |
378 | #define GLOBAL2_SWITCH_MAC 0x0d | |
cca8b133 AL |
379 | #define GLOBAL2_ATU_STATS 0x0e |
380 | #define GLOBAL2_PRIO_OVERRIDE 0x0f | |
15966a2a AL |
381 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) |
382 | #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 | |
383 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) | |
384 | #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 | |
855b1932 VD |
385 | #define GLOBAL2_EEPROM_CMD 0x14 |
386 | #define GLOBAL2_EEPROM_CMD_BUSY BIT(15) | |
387 | #define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
388 | #define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
389 | #define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY) | |
390 | #define GLOBAL2_EEPROM_CMD_RUNNING BIT(11) | |
391 | #define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10) | |
392 | #define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff | |
cca8b133 | 393 | #define GLOBAL2_EEPROM_DATA 0x15 |
a75961d0 | 394 | #define GLOBAL2_EEPROM_ADDR 0x15 /* 6390, 6341 */ |
cca8b133 AL |
395 | #define GLOBAL2_PTP_AVB_OP 0x16 |
396 | #define GLOBAL2_PTP_AVB_DATA 0x17 | |
57c67cf5 VD |
397 | #define GLOBAL2_SMI_PHY_CMD 0x18 |
398 | #define GLOBAL2_SMI_PHY_CMD_BUSY BIT(15) | |
c61a6a71 | 399 | #define GLOBAL2_SMI_PHY_CMD_EXTERNAL BIT(13) |
57c67cf5 VD |
400 | #define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12) |
401 | #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA ((0x1 << 10) | \ | |
402 | GLOBAL2_SMI_PHY_CMD_MODE_22 | \ | |
403 | GLOBAL2_SMI_PHY_CMD_BUSY) | |
404 | #define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA ((0x2 << 10) | \ | |
405 | GLOBAL2_SMI_PHY_CMD_MODE_22 | \ | |
406 | GLOBAL2_SMI_PHY_CMD_BUSY) | |
cf3e80df AL |
407 | #define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_ADDR ((0x0 << 10) | \ |
408 | GLOBAL2_SMI_PHY_CMD_BUSY) | |
409 | #define GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA ((0x1 << 10) | \ | |
410 | GLOBAL2_SMI_PHY_CMD_BUSY) | |
411 | #define GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA ((0x3 << 10) | \ | |
412 | GLOBAL2_SMI_PHY_CMD_BUSY) | |
413 | ||
57c67cf5 | 414 | #define GLOBAL2_SMI_PHY_DATA 0x19 |
cca8b133 | 415 | #define GLOBAL2_SCRATCH_MISC 0x1a |
56d95e22 AL |
416 | #define GLOBAL2_SCRATCH_BUSY BIT(15) |
417 | #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 | |
418 | #define GLOBAL2_SCRATCH_VALUE_MASK 0xff | |
cca8b133 | 419 | #define GLOBAL2_WDOG_CONTROL 0x1b |
fcd25166 AL |
420 | #define GLOBAL2_WDOG_CONTROL_EGRESS_EVENT BIT(7) |
421 | #define GLOBAL2_WDOG_CONTROL_RMU_TIMEOUT BIT(6) | |
422 | #define GLOBAL2_WDOG_CONTROL_QC_ENABLE BIT(5) | |
423 | #define GLOBAL2_WDOG_CONTROL_EGRESS_HISTORY BIT(4) | |
424 | #define GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE BIT(3) | |
425 | #define GLOBAL2_WDOG_CONTROL_FORCE_IRQ BIT(2) | |
426 | #define GLOBAL2_WDOG_CONTROL_HISTORY BIT(1) | |
427 | #define GLOBAL2_WDOG_CONTROL_SWRESET BIT(0) | |
61303736 AL |
428 | #define GLOBAL2_WDOG_UPDATE BIT(15) |
429 | #define GLOBAL2_WDOG_INT_SOURCE (0x00 << 8) | |
430 | #define GLOBAL2_WDOG_INT_STATUS (0x10 << 8) | |
431 | #define GLOBAL2_WDOG_INT_ENABLE (0x11 << 8) | |
432 | #define GLOBAL2_WDOG_EVENT (0x12 << 8) | |
433 | #define GLOBAL2_WDOG_HISTORY (0x13 << 8) | |
434 | #define GLOBAL2_WDOG_DATA_MASK 0xff | |
435 | #define GLOBAL2_WDOG_CUT_THROUGH BIT(3) | |
436 | #define GLOBAL2_WDOG_QUEUE_CONTROLLER BIT(2) | |
437 | #define GLOBAL2_WDOG_EGRESS BIT(1) | |
438 | #define GLOBAL2_WDOG_FORCE_IRQ BIT(0) | |
cca8b133 AL |
439 | #define GLOBAL2_QOS_WEIGHT 0x1c |
440 | #define GLOBAL2_MISC 0x1d | |
defb05b9 | 441 | |
3285f9e8 VD |
442 | #define MV88E6XXX_N_FID 4096 |
443 | ||
56995cbc AL |
444 | enum mv88e6xxx_frame_mode { |
445 | MV88E6XXX_FRAME_MODE_NORMAL, | |
446 | MV88E6XXX_FRAME_MODE_DSA, | |
447 | MV88E6XXX_FRAME_MODE_PROVIDER, | |
448 | MV88E6XXX_FRAME_MODE_ETHERTYPE, | |
449 | }; | |
450 | ||
f81ec90f VD |
451 | /* List of supported models */ |
452 | enum mv88e6xxx_model { | |
453 | MV88E6085, | |
454 | MV88E6095, | |
7d381a02 | 455 | MV88E6097, |
f81ec90f VD |
456 | MV88E6123, |
457 | MV88E6131, | |
1558727a | 458 | MV88E6141, |
f81ec90f VD |
459 | MV88E6161, |
460 | MV88E6165, | |
461 | MV88E6171, | |
462 | MV88E6172, | |
463 | MV88E6175, | |
464 | MV88E6176, | |
465 | MV88E6185, | |
1a3b39ec AL |
466 | MV88E6190, |
467 | MV88E6190X, | |
468 | MV88E6191, | |
f81ec90f | 469 | MV88E6240, |
1a3b39ec | 470 | MV88E6290, |
f81ec90f VD |
471 | MV88E6320, |
472 | MV88E6321, | |
a75961d0 | 473 | MV88E6341, |
f81ec90f VD |
474 | MV88E6350, |
475 | MV88E6351, | |
476 | MV88E6352, | |
1a3b39ec AL |
477 | MV88E6390, |
478 | MV88E6390X, | |
f81ec90f VD |
479 | }; |
480 | ||
22356476 VD |
481 | enum mv88e6xxx_family { |
482 | MV88E6XXX_FAMILY_NONE, | |
483 | MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ | |
484 | MV88E6XXX_FAMILY_6095, /* 6092 6095 */ | |
485 | MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ | |
486 | MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ | |
487 | MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ | |
488 | MV88E6XXX_FAMILY_6320, /* 6320 6321 */ | |
a75961d0 | 489 | MV88E6XXX_FAMILY_6341, /* 6141 6341 */ |
22356476 VD |
490 | MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ |
491 | MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ | |
1a3b39ec | 492 | MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */ |
22356476 VD |
493 | }; |
494 | ||
8c9983a2 | 495 | enum mv88e6xxx_cap { |
aadbdb8a VD |
496 | /* Energy Efficient Ethernet. |
497 | */ | |
498 | MV88E6XXX_CAP_EEE, | |
499 | ||
a0ffff24 VD |
500 | /* Multi-chip Addressing Mode. |
501 | * Some chips respond to only 2 registers of its own SMI device address | |
502 | * when it is non-zero, and use indirect access to internal registers. | |
503 | */ | |
504 | MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */ | |
505 | MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */ | |
506 | ||
09cb7dfd VD |
507 | /* PHY Registers. |
508 | */ | |
509 | MV88E6XXX_CAP_PHY_PAGE, /* (0x16) Page Register */ | |
510 | ||
511 | /* Fiber/SERDES Registers (SMI address F). | |
512 | */ | |
513 | MV88E6XXX_CAP_SERDES, | |
514 | ||
6dc10bbc VD |
515 | /* Switch Global (1) Registers. |
516 | */ | |
517 | MV88E6XXX_CAP_G1_ATU_FID, /* (0x01) ATU FID Register */ | |
518 | MV88E6XXX_CAP_G1_VTU_FID, /* (0x02) VTU FID Register */ | |
519 | ||
9729934c VD |
520 | /* Switch Global 2 Registers. |
521 | * The device contains a second set of global 16-bit registers. | |
522 | */ | |
523 | MV88E6XXX_CAP_GLOBAL2, | |
dc30c35b | 524 | MV88E6XXX_CAP_G2_INT, /* (0x00) Interrupt Status */ |
47395ed2 VD |
525 | MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */ |
526 | MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */ | |
8ec61c7f VD |
527 | MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */ |
528 | MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */ | |
63ed880d VD |
529 | MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */ |
530 | MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */ | |
9bda889f | 531 | MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */ |
9729934c | 532 | |
cb9b9020 VD |
533 | /* Per VLAN Spanning Tree Unit (STU). |
534 | * The Port State database, if present, is accessed through VTU | |
535 | * operations and dedicated SID registers. See GLOBAL_VTU_SID. | |
536 | */ | |
537 | MV88E6XXX_CAP_STU, | |
538 | ||
54d77b5b VD |
539 | /* VLAN Table Unit. |
540 | * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP. | |
541 | */ | |
542 | MV88E6XXX_CAP_VTU, | |
8c9983a2 VD |
543 | }; |
544 | ||
545 | /* Bitmask of capabilities */ | |
d6b1023a AL |
546 | #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE) |
547 | ||
548 | #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD) | |
549 | #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA) | |
550 | ||
551 | #define MV88E6XXX_FLAG_PHY_PAGE BIT_ULL(MV88E6XXX_CAP_PHY_PAGE) | |
552 | ||
553 | #define MV88E6XXX_FLAG_SERDES BIT_ULL(MV88E6XXX_CAP_SERDES) | |
554 | ||
6dc10bbc VD |
555 | #define MV88E6XXX_FLAG_G1_VTU_FID BIT_ULL(MV88E6XXX_CAP_G1_VTU_FID) |
556 | ||
d6b1023a | 557 | #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2) |
dc30c35b | 558 | #define MV88E6XXX_FLAG_G2_INT BIT_ULL(MV88E6XXX_CAP_G2_INT) |
d6b1023a AL |
559 | #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X) |
560 | #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X) | |
561 | #define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD) | |
562 | #define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA) | |
563 | #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR) | |
564 | #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA) | |
d6b1023a | 565 | #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT) |
d6b1023a | 566 | |
d6b1023a | 567 | #define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU) |
d6b1023a | 568 | #define MV88E6XXX_FLAG_VTU BIT_ULL(MV88E6XXX_CAP_VTU) |
b5058d7a | 569 | |
8ec61c7f VD |
570 | /* Ingress Rate Limit unit */ |
571 | #define MV88E6XXX_FLAGS_IRL \ | |
572 | (MV88E6XXX_FLAG_G2_IRL_CMD | \ | |
573 | MV88E6XXX_FLAG_G2_IRL_DATA) | |
574 | ||
a0ffff24 VD |
575 | /* Multi-chip Addressing Mode */ |
576 | #define MV88E6XXX_FLAGS_MULTI_CHIP \ | |
577 | (MV88E6XXX_FLAG_SMI_CMD | \ | |
578 | MV88E6XXX_FLAG_SMI_DATA) | |
579 | ||
63ed880d VD |
580 | /* Cross-chip Port VLAN Table */ |
581 | #define MV88E6XXX_FLAGS_PVT \ | |
582 | (MV88E6XXX_FLAG_G2_PVT_ADDR | \ | |
583 | MV88E6XXX_FLAG_G2_PVT_DATA) | |
584 | ||
09cb7dfd VD |
585 | /* Fiber/SERDES Registers at SMI address F, page 1 */ |
586 | #define MV88E6XXX_FLAGS_SERDES \ | |
587 | (MV88E6XXX_FLAG_PHY_PAGE | \ | |
588 | MV88E6XXX_FLAG_SERDES) | |
589 | ||
8c9983a2 | 590 | #define MV88E6XXX_FLAGS_FAMILY_6095 \ |
9729934c | 591 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
47395ed2 | 592 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
a0ffff24 VD |
593 | MV88E6XXX_FLAG_VTU | \ |
594 | MV88E6XXX_FLAGS_MULTI_CHIP) | |
8c9983a2 VD |
595 | |
596 | #define MV88E6XXX_FLAGS_FAMILY_6097 \ | |
e606ca36 | 597 | (MV88E6XXX_FLAG_G1_VTU_FID | \ |
6dc10bbc | 598 | MV88E6XXX_FLAG_GLOBAL2 | \ |
56b46b43 | 599 | MV88E6XXX_FLAG_G2_INT | \ |
47395ed2 VD |
600 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
601 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
9bda889f | 602 | MV88E6XXX_FLAG_G2_POT | \ |
cb9b9020 | 603 | MV88E6XXX_FLAG_STU | \ |
63ed880d | 604 | MV88E6XXX_FLAG_VTU | \ |
8ec61c7f | 605 | MV88E6XXX_FLAGS_IRL | \ |
a0ffff24 | 606 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
63ed880d | 607 | MV88E6XXX_FLAGS_PVT) |
b5058d7a | 608 | |
6594f615 | 609 | #define MV88E6XXX_FLAGS_FAMILY_6165 \ |
e606ca36 | 610 | (MV88E6XXX_FLAG_G1_VTU_FID | \ |
6dc10bbc | 611 | MV88E6XXX_FLAG_GLOBAL2 | \ |
dc30c35b | 612 | MV88E6XXX_FLAG_G2_INT | \ |
47395ed2 VD |
613 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
614 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
9bda889f | 615 | MV88E6XXX_FLAG_G2_POT | \ |
914b32f6 | 616 | MV88E6XXX_FLAG_STU | \ |
63ed880d | 617 | MV88E6XXX_FLAG_VTU | \ |
8ec61c7f | 618 | MV88E6XXX_FLAGS_IRL | \ |
a0ffff24 | 619 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
63ed880d | 620 | MV88E6XXX_FLAGS_PVT) |
b5058d7a | 621 | |
8c9983a2 | 622 | #define MV88E6XXX_FLAGS_FAMILY_6185 \ |
9729934c | 623 | (MV88E6XXX_FLAG_GLOBAL2 | \ |
dc30c35b | 624 | MV88E6XXX_FLAG_G2_INT | \ |
47395ed2 | 625 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ |
a0ffff24 | 626 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
54d77b5b | 627 | MV88E6XXX_FLAG_VTU) |
b5058d7a | 628 | |
6d5834a1 | 629 | #define MV88E6XXX_FLAGS_FAMILY_6320 \ |
443d5a1b | 630 | (MV88E6XXX_FLAG_EEE | \ |
9729934c | 631 | MV88E6XXX_FLAG_GLOBAL2 | \ |
47395ed2 VD |
632 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
633 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
9bda889f | 634 | MV88E6XXX_FLAG_G2_POT | \ |
63ed880d | 635 | MV88E6XXX_FLAG_VTU | \ |
8ec61c7f | 636 | MV88E6XXX_FLAGS_IRL | \ |
a0ffff24 | 637 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
b3469dd8 | 638 | MV88E6XXX_FLAGS_PVT) |
b5058d7a | 639 | |
a75961d0 GC |
640 | #define MV88E6XXX_FLAGS_FAMILY_6341 \ |
641 | (MV88E6XXX_FLAG_EEE | \ | |
a75961d0 GC |
642 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
643 | MV88E6XXX_FLAG_GLOBAL2 | \ | |
644 | MV88E6XXX_FLAG_G2_INT | \ | |
645 | MV88E6XXX_FLAG_G2_POT | \ | |
646 | MV88E6XXX_FLAG_STU | \ | |
647 | MV88E6XXX_FLAG_VTU | \ | |
648 | MV88E6XXX_FLAGS_IRL | \ | |
649 | MV88E6XXX_FLAGS_MULTI_CHIP | \ | |
650 | MV88E6XXX_FLAGS_PVT | \ | |
651 | MV88E6XXX_FLAGS_SERDES) | |
652 | ||
6d5834a1 | 653 | #define MV88E6XXX_FLAGS_FAMILY_6351 \ |
e606ca36 | 654 | (MV88E6XXX_FLAG_G1_VTU_FID | \ |
2bbb33be | 655 | MV88E6XXX_FLAG_GLOBAL2 | \ |
dc30c35b | 656 | MV88E6XXX_FLAG_G2_INT | \ |
47395ed2 VD |
657 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
658 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
9bda889f | 659 | MV88E6XXX_FLAG_G2_POT | \ |
cb9b9020 | 660 | MV88E6XXX_FLAG_STU | \ |
63ed880d | 661 | MV88E6XXX_FLAG_VTU | \ |
8ec61c7f | 662 | MV88E6XXX_FLAGS_IRL | \ |
a0ffff24 | 663 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
b3469dd8 | 664 | MV88E6XXX_FLAGS_PVT) |
b5058d7a | 665 | |
6d5834a1 | 666 | #define MV88E6XXX_FLAGS_FAMILY_6352 \ |
443d5a1b | 667 | (MV88E6XXX_FLAG_EEE | \ |
6dc10bbc | 668 | MV88E6XXX_FLAG_G1_VTU_FID | \ |
9729934c | 669 | MV88E6XXX_FLAG_GLOBAL2 | \ |
dc30c35b | 670 | MV88E6XXX_FLAG_G2_INT | \ |
47395ed2 VD |
671 | MV88E6XXX_FLAG_G2_MGMT_EN_2X | \ |
672 | MV88E6XXX_FLAG_G2_MGMT_EN_0X | \ | |
9bda889f | 673 | MV88E6XXX_FLAG_G2_POT | \ |
cb9b9020 | 674 | MV88E6XXX_FLAG_STU | \ |
63ed880d | 675 | MV88E6XXX_FLAG_VTU | \ |
8ec61c7f | 676 | MV88E6XXX_FLAGS_IRL | \ |
a0ffff24 | 677 | MV88E6XXX_FLAGS_MULTI_CHIP | \ |
57c67cf5 | 678 | MV88E6XXX_FLAGS_PVT | \ |
b3469dd8 VD |
679 | MV88E6XXX_FLAGS_SERDES) |
680 | ||
1a3b39ec AL |
681 | #define MV88E6XXX_FLAGS_FAMILY_6390 \ |
682 | (MV88E6XXX_FLAG_EEE | \ | |
683 | MV88E6XXX_FLAG_GLOBAL2 | \ | |
61303736 | 684 | MV88E6XXX_FLAG_G2_INT | \ |
1a3b39ec | 685 | MV88E6XXX_FLAG_STU | \ |
1a3b39ec AL |
686 | MV88E6XXX_FLAG_VTU | \ |
687 | MV88E6XXX_FLAGS_IRL | \ | |
688 | MV88E6XXX_FLAGS_MULTI_CHIP | \ | |
689 | MV88E6XXX_FLAGS_PVT) | |
690 | ||
c0e4dadb AL |
691 | struct mv88e6xxx_ops; |
692 | ||
f6271e67 | 693 | struct mv88e6xxx_info { |
22356476 | 694 | enum mv88e6xxx_family family; |
f6271e67 VD |
695 | u16 prod_num; |
696 | const char *name; | |
cd5a2c82 | 697 | unsigned int num_databases; |
009a2b98 | 698 | unsigned int num_ports; |
9dddd478 | 699 | unsigned int port_base_addr; |
a935c052 | 700 | unsigned int global1_addr; |
acddbd21 | 701 | unsigned int age_time_coeff; |
dc30c35b | 702 | unsigned int g1_irqs; |
443d5a1b | 703 | enum dsa_tag_protocol tag_protocol; |
d6b1023a | 704 | unsigned long long flags; |
e606ca36 VD |
705 | |
706 | /* Mask for FromPort and ToPort value of PortVec used in ATU Move | |
707 | * operation. 0 means that the ATU Move operation is not supported. | |
708 | */ | |
709 | u8 atu_move_port_mask; | |
b3469dd8 | 710 | const struct mv88e6xxx_ops *ops; |
b9b37713 VD |
711 | }; |
712 | ||
fd231c82 | 713 | struct mv88e6xxx_atu_entry { |
fd231c82 VD |
714 | u8 state; |
715 | bool trunk; | |
01bd96c8 | 716 | u16 portvec; |
fd231c82 VD |
717 | u8 mac[ETH_ALEN]; |
718 | }; | |
719 | ||
b4e47c0f | 720 | struct mv88e6xxx_vtu_entry { |
b8fee957 VD |
721 | u16 vid; |
722 | u16 fid; | |
b8fee957 VD |
723 | u8 sid; |
724 | bool valid; | |
725 | u8 data[DSA_MAX_PORTS]; | |
726 | }; | |
727 | ||
c08026ab | 728 | struct mv88e6xxx_bus_ops; |
fcd25166 | 729 | struct mv88e6xxx_irq_ops; |
914b32f6 | 730 | |
dc30c35b AL |
731 | struct mv88e6xxx_irq { |
732 | u16 masked; | |
733 | struct irq_chip chip; | |
734 | struct irq_domain *domain; | |
735 | unsigned int nirqs; | |
736 | }; | |
737 | ||
fad09c73 | 738 | struct mv88e6xxx_chip { |
f6271e67 VD |
739 | const struct mv88e6xxx_info *info; |
740 | ||
7543a6d5 AL |
741 | /* The dsa_switch this private structure is related to */ |
742 | struct dsa_switch *ds; | |
743 | ||
158bc065 AL |
744 | /* The device this structure is associated to */ |
745 | struct device *dev; | |
746 | ||
9f8b3ee1 VD |
747 | /* This mutex protects the access to the switch registers */ |
748 | struct mutex reg_lock; | |
91da11f8 | 749 | |
a77d43f1 AL |
750 | /* The MII bus and the address on the bus that is used to |
751 | * communication with the switch | |
752 | */ | |
c08026ab | 753 | const struct mv88e6xxx_bus_ops *smi_ops; |
a77d43f1 AL |
754 | struct mii_bus *bus; |
755 | int sw_addr; | |
756 | ||
3675c8d7 | 757 | /* Handles automatic disabling and re-enabling of the PHY |
2e5f0320 LB |
758 | * polling unit. |
759 | */ | |
c08026ab | 760 | const struct mv88e6xxx_bus_ops *phy_ops; |
2e5f0320 LB |
761 | struct mutex ppu_mutex; |
762 | int ppu_disabled; | |
763 | struct work_struct ppu_work; | |
764 | struct timer_list ppu_timer; | |
2e5f0320 | 765 | |
3675c8d7 | 766 | /* This mutex serialises access to the statistics unit. |
91da11f8 LB |
767 | * Hold this mutex over snapshot + dump sequences. |
768 | */ | |
769 | struct mutex stats_mutex; | |
3ad50cca | 770 | |
52638f71 AL |
771 | /* A switch may have a GPIO line tied to its reset pin. Parse |
772 | * this from the device tree, and use it before performing | |
773 | * switch soft reset. | |
774 | */ | |
775 | struct gpio_desc *reset; | |
f8cd8753 AL |
776 | |
777 | /* set to size of eeprom if supported by the switch */ | |
778 | int eeprom_len; | |
b516d453 | 779 | |
a3c53be5 AL |
780 | /* List of mdio busses */ |
781 | struct list_head mdios; | |
dc30c35b AL |
782 | |
783 | /* There can be two interrupt controllers, which are chained | |
784 | * off a GPIO as interrupt source | |
785 | */ | |
786 | struct mv88e6xxx_irq g1_irq; | |
787 | struct mv88e6xxx_irq g2_irq; | |
788 | int irq; | |
8e757eba | 789 | int device_irq; |
fcd25166 | 790 | int watchdog_irq; |
91da11f8 LB |
791 | }; |
792 | ||
c08026ab | 793 | struct mv88e6xxx_bus_ops { |
fad09c73 VD |
794 | int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
795 | int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); | |
914b32f6 VD |
796 | }; |
797 | ||
0dd12d54 | 798 | struct mv88e6xxx_mdio_bus { |
a3c53be5 | 799 | struct mii_bus *bus; |
0dd12d54 | 800 | struct mv88e6xxx_chip *chip; |
a3c53be5 AL |
801 | struct list_head list; |
802 | bool external; | |
0dd12d54 AL |
803 | }; |
804 | ||
b3469dd8 | 805 | struct mv88e6xxx_ops { |
ee4dc2e7 VD |
806 | int (*get_eeprom)(struct mv88e6xxx_chip *chip, |
807 | struct ethtool_eeprom *eeprom, u8 *data); | |
808 | int (*set_eeprom)(struct mv88e6xxx_chip *chip, | |
809 | struct ethtool_eeprom *eeprom, u8 *data); | |
810 | ||
b073d4e2 VD |
811 | int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr); |
812 | ||
ee26a228 AL |
813 | int (*phy_read)(struct mv88e6xxx_chip *chip, |
814 | struct mii_bus *bus, | |
815 | int addr, int reg, u16 *val); | |
816 | int (*phy_write)(struct mv88e6xxx_chip *chip, | |
817 | struct mii_bus *bus, | |
818 | int addr, int reg, u16 val); | |
08ef7f10 | 819 | |
a199d8b6 VD |
820 | /* PHY Polling Unit (PPU) operations */ |
821 | int (*ppu_enable)(struct mv88e6xxx_chip *chip); | |
822 | int (*ppu_disable)(struct mv88e6xxx_chip *chip); | |
823 | ||
17e708ba VD |
824 | /* Switch Software Reset */ |
825 | int (*reset)(struct mv88e6xxx_chip *chip); | |
826 | ||
a0a0f622 VD |
827 | /* RGMII Receive/Transmit Timing Control |
828 | * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise. | |
829 | */ | |
830 | int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port, | |
831 | phy_interface_t mode); | |
832 | ||
08ef7f10 VD |
833 | #define LINK_FORCED_DOWN 0 |
834 | #define LINK_FORCED_UP 1 | |
835 | #define LINK_UNFORCED -2 | |
836 | ||
837 | /* Port's MAC link state | |
838 | * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down, | |
839 | * or LINK_UNFORCED for normal link detection. | |
840 | */ | |
841 | int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link); | |
7f1ae07b VD |
842 | |
843 | #define DUPLEX_UNFORCED -2 | |
844 | ||
845 | /* Port's MAC duplex mode | |
846 | * | |
847 | * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex, | |
848 | * or DUPLEX_UNFORCED for normal duplex detection. | |
849 | */ | |
850 | int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup); | |
96a2b40c VD |
851 | |
852 | #define SPEED_MAX INT_MAX | |
853 | #define SPEED_UNFORCED -2 | |
854 | ||
855 | /* Port's MAC speed (in Mbps) | |
856 | * | |
857 | * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid. | |
858 | * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value. | |
859 | */ | |
860 | int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed); | |
a605a0fe | 861 | |
ef0a7318 AL |
862 | int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port); |
863 | ||
56995cbc AL |
864 | int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port, |
865 | enum mv88e6xxx_frame_mode mode); | |
866 | int (*port_set_egress_unknowns)(struct mv88e6xxx_chip *chip, int port, | |
867 | bool on); | |
868 | int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port, | |
869 | u16 etype); | |
5f436666 | 870 | int (*port_jumbo_config)(struct mv88e6xxx_chip *chip, int port); |
56995cbc | 871 | |
ef70b111 | 872 | int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); |
b35d322a | 873 | int (*port_pause_config)(struct mv88e6xxx_chip *chip, int port); |
ef70b111 | 874 | |
f39908d3 AL |
875 | /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc. |
876 | * Some chips allow this to be configured on specific ports. | |
877 | */ | |
878 | int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port, | |
879 | phy_interface_t mode); | |
880 | ||
a23b2961 AL |
881 | /* Some devices have a per port register indicating what is |
882 | * the upstream port this port should forward to. | |
883 | */ | |
884 | int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port, | |
885 | int upstream_port); | |
886 | ||
a605a0fe AL |
887 | /* Snapshot the statistics for a port. The statistics can then |
888 | * be read back a leisure but still with a consistent view. | |
889 | */ | |
890 | int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port); | |
de227387 AL |
891 | |
892 | /* Set the histogram mode for statistics, when the control registers | |
893 | * are separated out of the STATS_OP register. | |
894 | */ | |
895 | int (*stats_set_histogram)(struct mv88e6xxx_chip *chip); | |
b3469dd8 | 896 | |
dfafe449 AL |
897 | /* Return the number of strings describing statistics */ |
898 | int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip); | |
899 | void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data); | |
052f947f AL |
900 | void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port, |
901 | uint64_t *data); | |
33641994 AL |
902 | int (*g1_set_cpu_port)(struct mv88e6xxx_chip *chip, int port); |
903 | int (*g1_set_egress_port)(struct mv88e6xxx_chip *chip, int port); | |
fcd25166 | 904 | const struct mv88e6xxx_irq_ops *watchdog_ops; |
6e55f698 AL |
905 | |
906 | /* Can be either in g1 or g2, so don't use a prefix */ | |
907 | int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip); | |
f5e2ed02 AL |
908 | }; |
909 | ||
fcd25166 AL |
910 | struct mv88e6xxx_irq_ops { |
911 | /* Action to be performed when the interrupt happens */ | |
912 | int (*irq_action)(struct mv88e6xxx_chip *chip, int irq); | |
913 | /* Setup the hardware to generate the interrupt */ | |
914 | int (*irq_setup)(struct mv88e6xxx_chip *chip); | |
915 | /* Reset the hardware to stop generating the interrupt */ | |
916 | void (*irq_free)(struct mv88e6xxx_chip *chip); | |
917 | }; | |
918 | ||
dfafe449 AL |
919 | #define STATS_TYPE_PORT BIT(0) |
920 | #define STATS_TYPE_BANK0 BIT(1) | |
921 | #define STATS_TYPE_BANK1 BIT(2) | |
922 | ||
91da11f8 LB |
923 | struct mv88e6xxx_hw_stat { |
924 | char string[ETH_GSTRING_LEN]; | |
925 | int sizeof_stat; | |
926 | int reg; | |
dfafe449 | 927 | int type; |
91da11f8 LB |
928 | }; |
929 | ||
fad09c73 | 930 | static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip, |
b5058d7a VD |
931 | unsigned long flags) |
932 | { | |
fad09c73 | 933 | return (chip->info->flags & flags) == flags; |
b5058d7a VD |
934 | } |
935 | ||
de33376b VD |
936 | static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip) |
937 | { | |
938 | return chip->info->num_databases; | |
939 | } | |
940 | ||
370b4ffb VD |
941 | static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip) |
942 | { | |
943 | return chip->info->num_ports; | |
944 | } | |
945 | ||
4d294af2 VD |
946 | static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip) |
947 | { | |
948 | return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0); | |
949 | } | |
950 | ||
ec561276 VD |
951 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); |
952 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); | |
953 | int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, | |
954 | u16 update); | |
955 | int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask); | |
956 | ||
91da11f8 | 957 | #endif |