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net: dsa: mv88e6xxx: fix 6085 frame mode masking
[mirror_ubuntu-bionic-kernel.git] / drivers / net / dsa / mv88e6xxx / port.c
CommitLineData
18abed21
VD		 1/*
2 * Marvell 88E6xxx Switch Port Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
4333d619
VD		 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
18abed21
VD		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
f39908d3 15#include <linux/phy.h>
4d5f2ba7
VD		 16
17#include "chip.h"
18abed21
VD		 18#include "port.h"
19
20int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
21 u16 *val)
22{
23 int addr = chip->info->port_base_addr + port;
24
25 return mv88e6xxx_read(chip, addr, reg, val);
26}
27
28int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
29 u16 val)
30{
31 int addr = chip->info->port_base_addr + port;
32
33 return mv88e6xxx_write(chip, addr, reg, val);
34}
e28def33 35
08ef7f10
VD		 36/* Offset 0x01: MAC (or PCS or Physical) Control Register
37 *
38 * Link, Duplex and Flow Control have one force bit, one value bit.
96a2b40c
VD		 39 *
40 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
41 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
42 * Newer chips need a ForcedSpd bit 13 set to consider the value.
08ef7f10
VD		 43 */
44
a0a0f622
VD		 45static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
46 phy_interface_t mode)
47{
48 u16 reg;
49 int err;
50
51 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
52 if (err)
53 return err;
54
55 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
56 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
57
58 switch (mode) {
59 case PHY_INTERFACE_MODE_RGMII_RXID:
60 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
61 break;
62 case PHY_INTERFACE_MODE_RGMII_TXID:
63 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
64 break;
65 case PHY_INTERFACE_MODE_RGMII_ID:
66 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
67 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
68 break;
fedf1865 69 case PHY_INTERFACE_MODE_RGMII:
a0a0f622 70 break;
fedf1865
AL		 71 default:
72 return 0;
a0a0f622
VD		 73 }
74
75 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
76 if (err)
77 return err;
78
79 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
80 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
81 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
82
83 return 0;
84}
85
86int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
87 phy_interface_t mode)
88{
89 if (port < 5)
90 return -EOPNOTSUPP;
91
92 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
93}
94
95int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
96 phy_interface_t mode)
97{
98 if (port != 0)
99 return -EOPNOTSUPP;
100
101 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
102}
103
08ef7f10
VD		 104int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
105{
106 u16 reg;
107 int err;
108
109 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
110 if (err)
111 return err;
112
113 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
114
115 switch (link) {
116 case LINK_FORCED_DOWN:
117 reg |= PORT_PCS_CTRL_FORCE_LINK;
118 break;
119 case LINK_FORCED_UP:
120 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
121 break;
122 case LINK_UNFORCED:
123 /* normal link detection */
124 break;
125 default:
126 return -EINVAL;
127 }
128
129 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
130 if (err)
131 return err;
132
133 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
134 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
135 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
136
137 return 0;
138}
139
7f1ae07b
VD		 140int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
141{
142 u16 reg;
143 int err;
144
145 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
146 if (err)
147 return err;
148
149 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
150
151 switch (dup) {
152 case DUPLEX_HALF:
153 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
154 break;
155 case DUPLEX_FULL:
156 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
157 break;
158 case DUPLEX_UNFORCED:
159 /* normal duplex detection */
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
166 if (err)
167 return err;
168
169 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
170 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
171 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
172
173 return 0;
174}
175
96a2b40c
VD		 176static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
177 int speed, bool alt_bit, bool force_bit)
178{
179 u16 reg, ctrl;
180 int err;
181
182 switch (speed) {
183 case 10:
184 ctrl = PORT_PCS_CTRL_SPEED_10;
185 break;
186 case 100:
187 ctrl = PORT_PCS_CTRL_SPEED_100;
188 break;
189 case 200:
190 if (alt_bit)
191 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
192 else
193 ctrl = PORT_PCS_CTRL_SPEED_200;
194 break;
195 case 1000:
196 ctrl = PORT_PCS_CTRL_SPEED_1000;
197 break;
198 case 2500:
740117a8 199 ctrl = PORT_PCS_CTRL_SPEED_10000 | PORT_PCS_CTRL_ALTSPEED;
96a2b40c
VD		 200 break;
201 case 10000:
202 /* all bits set, fall through... */
203 case SPEED_UNFORCED:
204 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
205 break;
206 default:
207 return -EOPNOTSUPP;
208 }
209
210 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
211 if (err)
212 return err;
213
214 reg &= ~PORT_PCS_CTRL_SPEED_MASK;
215 if (alt_bit)
216 reg &= ~PORT_PCS_CTRL_ALTSPEED;
217 if (force_bit) {
218 reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
0b6e3d03 219 if (speed != SPEED_UNFORCED)
96a2b40c
VD		 220 ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
221 }
222 reg |= ctrl;
223
224 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
225 if (err)
226 return err;
227
228 if (speed)
229 netdev_dbg(chip->ds->ports[port].netdev,
230 "Speed set to %d Mbps\n", speed);
231 else
232 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
233
234 return 0;
235}
236
237/* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
238int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
239{
240 if (speed == SPEED_MAX)
241 speed = 200;
242
243 if (speed > 200)
244 return -EOPNOTSUPP;
245
246 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
247 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
248}
249
250/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
251int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
252{
253 if (speed == SPEED_MAX)
254 speed = 1000;
255
256 if (speed == 200 || speed > 1000)
257 return -EOPNOTSUPP;
258
259 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
260}
261
262/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
263int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
264{
265 if (speed == SPEED_MAX)
266 speed = 1000;
267
268 if (speed > 1000)
269 return -EOPNOTSUPP;
270
271 if (speed == 200 && port < 5)
272 return -EOPNOTSUPP;
273
274 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
275}
276
277/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
278int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
279{
280 if (speed == SPEED_MAX)
281 speed = port < 9 ? 1000 : 2500;
282
283 if (speed > 2500)
284 return -EOPNOTSUPP;
285
286 if (speed == 200 && port != 0)
287 return -EOPNOTSUPP;
288
289 if (speed == 2500 && port < 9)
290 return -EOPNOTSUPP;
291
292 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
293}
294
295/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
296int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
297{
298 if (speed == SPEED_MAX)
299 speed = port < 9 ? 1000 : 10000;
300
301 if (speed == 200 && port != 0)
302 return -EOPNOTSUPP;
303
304 if (speed >= 2500 && port < 9)
305 return -EOPNOTSUPP;
306
307 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
308}
309
f39908d3
AL		 310int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
311 phy_interface_t mode)
312{
313 u16 reg;
314 u16 cmode;
315 int err;
316
317 if (mode == PHY_INTERFACE_MODE_NA)
318 return 0;
319
320 if (port != 9 && port != 10)
321 return -EOPNOTSUPP;
322
323 switch (mode) {
324 case PHY_INTERFACE_MODE_1000BASEX:
325 cmode = PORT_STATUS_CMODE_1000BASE_X;
326 break;
327 case PHY_INTERFACE_MODE_SGMII:
328 cmode = PORT_STATUS_CMODE_SGMII;
329 break;
330 case PHY_INTERFACE_MODE_2500BASEX:
331 cmode = PORT_STATUS_CMODE_2500BASEX;
332 break;
333 case PHY_INTERFACE_MODE_XGMII:
334 cmode = PORT_STATUS_CMODE_XAUI;
335 break;
336 case PHY_INTERFACE_MODE_RXAUI:
337 cmode = PORT_STATUS_CMODE_RXAUI;
338 break;
339 default:
340 cmode = 0;
341 }
342
343 if (cmode) {
344 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
345 if (err)
346 return err;
347
348 reg &= ~PORT_STATUS_CMODE_MASK;
349 reg |= cmode;
350
351 err = mv88e6xxx_port_write(chip, port, PORT_STATUS, reg);
352 if (err)
353 return err;
354 }
355
356 return 0;
357}
358
359int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
360{
361 int err;
362 u16 reg;
363
364 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
365 if (err)
366 return err;
367
368 *cmode = reg & PORT_STATUS_CMODE_MASK;
369
370 return 0;
371}
372
b35d322a
AL		 373/* Offset 0x02: Pause Control
374 *
375 * Do not limit the period of time that this port can be paused for by
376 * the remote end or the period of time that this port can pause the
377 * remote end.
378 */
379int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port)
380{
381 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
382}
383
3ce0e65e
AL		 384int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port)
385{
386 int err;
387
388 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
389 PORT_FLOW_CTRL_LIMIT_IN | 0);
390 if (err)
391 return err;
392
393 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
394 PORT_FLOW_CTRL_LIMIT_OUT | 0);
395}
396
e28def33
VD		 397/* Offset 0x04: Port Control Register */
398
399static const char * const mv88e6xxx_port_state_names[] = {
400 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
401 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
402 [PORT_CONTROL_STATE_LEARNING] = "Learning",
403 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
404};
405
406int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
407{
408 u16 reg;
409 int err;
410
411 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
412 if (err)
413 return err;
414
415 reg &= ~PORT_CONTROL_STATE_MASK;
416 reg |= state;
417
418 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
419 if (err)
420 return err;
421
422 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
423 mv88e6xxx_port_state_names[state]);
424
425 return 0;
426}
5a7921f4 427
56995cbc
AL		 428int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
429 u16 mode)
430{
431 int err;
432 u16 reg;
433
434 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
435 if (err)
436 return err;
437
438 reg &= ~PORT_CONTROL_EGRESS_MASK;
439 reg |= mode;
440
441 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
442}
443
444int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
445 enum mv88e6xxx_frame_mode mode)
446{
447 int err;
448 u16 reg;
449
450 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
451 if (err)
452 return err;
453
5461bd41 454 reg &= ~PORT_CONTROL_FRAME_MASK;
56995cbc
AL		 455
456 switch (mode) {
457 case MV88E6XXX_FRAME_MODE_NORMAL:
458 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
459 break;
460 case MV88E6XXX_FRAME_MODE_DSA:
461 reg |= PORT_CONTROL_FRAME_MODE_DSA;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
468}
469
470int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
471 enum mv88e6xxx_frame_mode mode)
472{
473 int err;
474 u16 reg;
475
476 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
477 if (err)
478 return err;
479
480 reg &= ~PORT_CONTROL_FRAME_MASK;
481
482 switch (mode) {
483 case MV88E6XXX_FRAME_MODE_NORMAL:
484 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
485 break;
486 case MV88E6XXX_FRAME_MODE_DSA:
487 reg |= PORT_CONTROL_FRAME_MODE_DSA;
488 break;
489 case MV88E6XXX_FRAME_MODE_PROVIDER:
490 reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
491 break;
492 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
493 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
494 break;
495 default:
496 return -EINVAL;
497 }
498
499 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
500}
501
601aeed3
VD		 502static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
503 int port, bool unicast)
56995cbc
AL		 504{
505 int err;
506 u16 reg;
507
508 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
509 if (err)
510 return err;
511
601aeed3 512 if (unicast)
56995cbc
AL		 513 reg |= PORT_CONTROL_FORWARD_UNKNOWN;
514 else
515 reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
516
517 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
518}
519
601aeed3
VD		 520int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
521 bool unicast, bool multicast)
56995cbc
AL		 522{
523 int err;
524 u16 reg;
525
526 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
527 if (err)
528 return err;
529
601aeed3
VD		 530 reg &= ~PORT_CONTROL_EGRESS_FLOODS_MASK;
531
532 if (unicast && multicast)
533 reg |= PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA;
534 else if (unicast)
535 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
536 else if (multicast)
537 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
56995cbc 538 else
601aeed3 539 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA;
56995cbc
AL		 540
541 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
542}
543
b4e48c50
VD		 544/* Offset 0x05: Port Control 1 */
545
ea698f4f
VD		 546int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
547 bool message_port)
548{
549 u16 val;
550 int err;
551
552 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &val);
553 if (err)
554 return err;
555
556 if (message_port)
557 val |= PORT_CONTROL_1_MESSAGE_PORT;
558 else
559 val &= ~PORT_CONTROL_1_MESSAGE_PORT;
560
561 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, val);
562}
563
5a7921f4
VD		 564/* Offset 0x06: Port Based VLAN Map */
565
566int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
567{
4d294af2 568 const u16 mask = mv88e6xxx_port_mask(chip);
5a7921f4
VD		 569 u16 reg;
570 int err;
571
572 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
573 if (err)
574 return err;
575
576 reg &= ~mask;
577 reg |= map & mask;
578
579 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
580 if (err)
581 return err;
582
583 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
584 map);
585
586 return 0;
587}
b4e48c50
VD		 588
589int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
590{
591 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
592 u16 reg;
593 int err;
594
595 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
596 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
597 if (err)
598 return err;
599
600 *fid = (reg & 0xf000) >> 12;
601
602 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
603 if (upper_mask) {
604 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
605 if (err)
606 return err;
607
608 *fid |= (reg & upper_mask) << 4;
609 }
610
611 return 0;
612}
613
614int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
615{
616 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
617 u16 reg;
618 int err;
619
620 if (fid >= mv88e6xxx_num_databases(chip))
621 return -EINVAL;
622
623 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
624 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
625 if (err)
626 return err;
627
628 reg &= 0x0fff;
629 reg |= (fid & 0x000f) << 12;
630
631 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
632 if (err)
633 return err;
634
635 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
636 if (upper_mask) {
637 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
638 if (err)
639 return err;
640
641 reg &= ~upper_mask;
642 reg |= (fid >> 4) & upper_mask;
643
644 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
645 if (err)
646 return err;
647 }
648
649 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
650
651 return 0;
652}
77064f37
VD		 653
654/* Offset 0x07: Default Port VLAN ID & Priority */
655
656int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
657{
658 u16 reg;
659 int err;
660
661 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
662 if (err)
663 return err;
664
665 *pvid = reg & PORT_DEFAULT_VLAN_MASK;
666
667 return 0;
668}
669
670int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
671{
672 u16 reg;
673 int err;
674
675 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
676 if (err)
677 return err;
678
679 reg &= ~PORT_DEFAULT_VLAN_MASK;
680 reg |= pvid & PORT_DEFAULT_VLAN_MASK;
681
682 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
683 if (err)
684 return err;
685
686 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
687 pvid);
688
689 return 0;
690}
385a0995
VD		 691
692/* Offset 0x08: Port Control 2 Register */
693
694static const char * const mv88e6xxx_port_8021q_mode_names[] = {
695 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
696 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
697 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
698 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
699};
700
601aeed3
VD		 701static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
702 int port, bool multicast)
a23b2961
AL		 703{
704 int err;
705 u16 reg;
706
707 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
708 if (err)
709 return err;
710
601aeed3
VD		 711 if (multicast)
712 reg |= PORT_CONTROL_2_DEFAULT_FORWARD;
a23b2961 713 else
601aeed3 714 reg &= ~PORT_CONTROL_2_DEFAULT_FORWARD;
a23b2961
AL		 715
716 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
717}
718
601aeed3
VD		 719int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
720 bool unicast, bool multicast)
721{
722 int err;
723
724 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
725 if (err)
726 return err;
727
728 return mv88e6185_port_set_default_forward(chip, port, multicast);
729}
730
a23b2961
AL		 731int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
732 int upstream_port)
733{
734 int err;
735 u16 reg;
736
737 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
738 if (err)
739 return err;
740
741 reg &= ~PORT_CONTROL_2_UPSTREAM_MASK;
742 reg |= upstream_port;
743
744 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
745}
746
385a0995
VD		 747int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
748 u16 mode)
749{
750 u16 reg;
751 int err;
752
753 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
754 if (err)
755 return err;
756
757 reg &= ~PORT_CONTROL_2_8021Q_MASK;
758 reg |= mode & PORT_CONTROL_2_8021Q_MASK;
759
760 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
761 if (err)
762 return err;
763
764 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
765 mv88e6xxx_port_8021q_mode_names[mode]);
766
767 return 0;
768}
ef0a7318 769
a23b2961
AL		 770int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
771{
772 u16 reg;
773 int err;
774
775 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
776 if (err)
777 return err;
778
779 reg |= PORT_CONTROL_2_MAP_DA;
780
781 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
782}
783
5f436666
AL		 784int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
785{
786 u16 reg;
787 int err;
788
789 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
790 if (err)
791 return err;
792
793 reg |= PORT_CONTROL_2_JUMBO_10240;
794
795 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
796}
797
ef70b111
AL		 798/* Offset 0x09: Port Rate Control */
799
800int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
801{
802 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);
803}
804
805int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
806{
807 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);
808}
809
c8c94891
VD		 810/* Offset 0x0C: Port ATU Control */
811
812int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
813{
814 return mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 0);
815}
816
9dbfb4e1
VD		 817/* Offset 0x0D: (Priority) Override Register */
818
819int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
820{
821 return mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 0);
822}
823
56995cbc
AL		 824/* Offset 0x0f: Port Ether type */
825
826int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
827 u16 etype)
828{
829 return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
830}
831
ef0a7318
AL		 832/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
833 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
834 */
835
836int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
837{
838 int err;
839
840 /* Use a direct priority mapping for all IEEE tagged frames */
841 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
842 if (err)
843 return err;
844
845 return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
846}
847
848static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
849 int port, u16 table,
850 u8 pointer, u16 data)
851{
852 u16 reg;
853
854 reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
855 table |
856 (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
857 data;
858
859 return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
860}
861
862int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
863{
864 int err, i;
865
866 for (i = 0; i <= 7; i++) {
867 err = mv88e6xxx_port_ieeepmt_write(
868 chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
869 i, (i | i << 4));
870 if (err)
871 return err;
872
873 err = mv88e6xxx_port_ieeepmt_write(
874 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
875 i, i);
876 if (err)
877 return err;
878
879 err = mv88e6xxx_port_ieeepmt_write(
880 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
881 i, i);
882 if (err)
883 return err;
884
885 err = mv88e6xxx_port_ieeepmt_write(
886 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,
887 i, i);
888 if (err)
889 return err;
890 }
891
892 return 0;
893}
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