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1 | /* |
2 | * Marvell 88E6xxx Switch PTP support | |
3 | * | |
4 | * Copyright (c) 2008 Marvell Semiconductor | |
5 | * | |
6 | * Copyright (c) 2017 National Instruments | |
7 | * Erik Hons <erik.hons@ni.com> | |
8 | * Brandon Streiff <brandon.streiff@ni.com> | |
9 | * Dane Wagner <dane.wagner@ni.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #ifndef _MV88E6XXX_PTP_H | |
18 | #define _MV88E6XXX_PTP_H | |
19 | ||
20 | #include "chip.h" | |
21 | ||
22 | /* Offset 0x00: TAI Global Config */ | |
23 | #define MV88E6XXX_TAI_CFG 0x00 | |
24 | ||
25 | /* Offset 0x01: Timestamp Clock Period (ps) */ | |
26 | #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 | |
27 | ||
28 | /* Offset 0x02/0x03: Trigger Generation Amount */ | |
29 | #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02 | |
30 | #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03 | |
31 | ||
32 | /* Offset 0x04: Clock Compensation */ | |
33 | #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04 | |
34 | ||
35 | /* Offset 0x05: Trigger Configuration */ | |
36 | #define MV88E6XXX_TAI_TRIG_CFG 0x05 | |
37 | ||
38 | /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ | |
39 | #define MV88E6XXX_TAI_IRL_AMOUNT 0x06 | |
40 | ||
41 | /* Offset 0x07: Ingress Rate Limiter Compensation */ | |
42 | #define MV88E6XXX_TAI_IRL_COMP 0x07 | |
43 | ||
44 | /* Offset 0x08: Ingress Rate Limiter Compensation */ | |
45 | #define MV88E6XXX_TAI_IRL_COMP_PS 0x08 | |
46 | ||
47 | /* Offset 0x09: Event Status */ | |
48 | #define MV88E6XXX_TAI_EVENT_STATUS 0x09 | |
49 | ||
50 | /* Offset 0x0A/0x0B: Event Time */ | |
51 | #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a | |
52 | #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b | |
53 | ||
54 | /* Offset 0x0E/0x0F: PTP Global Time */ | |
55 | #define MV88E6XXX_TAI_TIME_LO 0x0e | |
56 | #define MV88E6XXX_TAI_TIME_HI 0x0f | |
57 | ||
58 | /* Offset 0x10/0x11: Trig Generation Time */ | |
59 | #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10 | |
60 | #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11 | |
61 | ||
62 | /* Offset 0x12: Lock Status */ | |
63 | #define MV88E6XXX_TAI_LOCK_STATUS 0x12 | |
64 | ||
65 | #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP | |
66 | ||
67 | int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); | |
68 | void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); | |
69 | ||
70 | #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ | |
71 | ||
72 | static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) | |
73 | { | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) | |
78 | { | |
79 | } | |
80 | ||
81 | #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ | |
82 | ||
83 | #endif /* _MV88E6XXX_PTP_H */ |