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1 | /* |
2 | * Marvell 88E6xxx Switch PTP support | |
3 | * | |
4 | * Copyright (c) 2008 Marvell Semiconductor | |
5 | * | |
6 | * Copyright (c) 2017 National Instruments | |
7 | * Erik Hons <erik.hons@ni.com> | |
8 | * Brandon Streiff <brandon.streiff@ni.com> | |
9 | * Dane Wagner <dane.wagner@ni.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #ifndef _MV88E6XXX_PTP_H | |
18 | #define _MV88E6XXX_PTP_H | |
19 | ||
20 | #include "chip.h" | |
21 | ||
22 | /* Offset 0x00: TAI Global Config */ | |
23 | #define MV88E6XXX_TAI_CFG 0x00 | |
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24 | #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000 |
25 | #define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000 | |
26 | #define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000 | |
27 | #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000 | |
28 | #define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400 | |
29 | #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200 | |
30 | #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100 | |
31 | #define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080 | |
32 | #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008 | |
33 | #define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004 | |
34 | #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002 | |
35 | #define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001 | |
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36 | |
37 | /* Offset 0x01: Timestamp Clock Period (ps) */ | |
38 | #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01 | |
39 | ||
40 | /* Offset 0x02/0x03: Trigger Generation Amount */ | |
41 | #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02 | |
42 | #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03 | |
43 | ||
44 | /* Offset 0x04: Clock Compensation */ | |
45 | #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04 | |
46 | ||
47 | /* Offset 0x05: Trigger Configuration */ | |
48 | #define MV88E6XXX_TAI_TRIG_CFG 0x05 | |
49 | ||
50 | /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */ | |
51 | #define MV88E6XXX_TAI_IRL_AMOUNT 0x06 | |
52 | ||
53 | /* Offset 0x07: Ingress Rate Limiter Compensation */ | |
54 | #define MV88E6XXX_TAI_IRL_COMP 0x07 | |
55 | ||
56 | /* Offset 0x08: Ingress Rate Limiter Compensation */ | |
57 | #define MV88E6XXX_TAI_IRL_COMP_PS 0x08 | |
58 | ||
59 | /* Offset 0x09: Event Status */ | |
60 | #define MV88E6XXX_TAI_EVENT_STATUS 0x09 | |
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61 | #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000 |
62 | #define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200 | |
63 | #define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100 | |
64 | #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff | |
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65 | |
66 | /* Offset 0x0A/0x0B: Event Time */ | |
67 | #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a | |
68 | #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b | |
69 | ||
70 | /* Offset 0x0E/0x0F: PTP Global Time */ | |
71 | #define MV88E6XXX_TAI_TIME_LO 0x0e | |
72 | #define MV88E6XXX_TAI_TIME_HI 0x0f | |
73 | ||
74 | /* Offset 0x10/0x11: Trig Generation Time */ | |
75 | #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10 | |
76 | #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11 | |
77 | ||
78 | /* Offset 0x12: Lock Status */ | |
79 | #define MV88E6XXX_TAI_LOCK_STATUS 0x12 | |
80 | ||
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81 | /* Offset 0x00: Ether Type */ |
82 | #define MV88E6XXX_PTP_GC_ETYPE 0x00 | |
83 | ||
84 | /* Offset 0x01: Message ID */ | |
85 | #define MV88E6XXX_PTP_GC_MESSAGE_ID 0x01 | |
86 | ||
87 | /* Offset 0x02: Time Stamp Arrive Time */ | |
88 | #define MV88E6XXX_PTP_GC_TS_ARR_PTR 0x02 | |
89 | ||
90 | /* Offset 0x03: Port Arrival Interrupt Enable */ | |
91 | #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN 0x03 | |
92 | ||
93 | /* Offset 0x04: Port Departure Interrupt Enable */ | |
94 | #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN 0x04 | |
95 | ||
96 | /* Offset 0x05: Configuration */ | |
97 | #define MV88E6XXX_PTP_GC_CONFIG 0x05 | |
98 | #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1) | |
99 | #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0) | |
100 | ||
101 | /* Offset 0x8: Interrupt Status */ | |
102 | #define MV88E6XXX_PTP_GC_INT_STATUS 0x08 | |
103 | ||
104 | /* Offset 0x9/0xa: Global Time */ | |
105 | #define MV88E6XXX_PTP_GC_TIME_LO 0x09 | |
106 | #define MV88E6XXX_PTP_GC_TIME_HI 0x0A | |
107 | ||
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108 | #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP |
109 | ||
c6fe0ad2 | 110 | long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp); |
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111 | int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip); |
112 | void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip); | |
113 | ||
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114 | #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \ |
115 | ptp_clock_info) | |
116 | ||
6d2ac8ee | 117 | extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops; |
dfa54348 | 118 | extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops; |
6d2ac8ee | 119 | |
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120 | #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */ |
121 | ||
46182452 | 122 | static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp) |
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123 | { |
124 | return -1; | |
125 | } | |
126 | ||
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127 | static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip) |
128 | { | |
129 | return 0; | |
130 | } | |
131 | ||
46182452 | 132 | static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip) |
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133 | { |
134 | } | |
135 | ||
6d2ac8ee | 136 | static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {}; |
dfa54348 | 137 | static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {}; |
6d2ac8ee | 138 | |
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139 | #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */ |
140 | ||
141 | #endif /* _MV88E6XXX_PTP_H */ |