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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
87c8cefb | 11 | #include <linux/debugfs.h> |
19b2f97e | 12 | #include <linux/delay.h> |
defb05b9 | 13 | #include <linux/etherdevice.h> |
facd95b2 | 14 | #include <linux/if_bridge.h> |
19b2f97e | 15 | #include <linux/jiffies.h> |
91da11f8 | 16 | #include <linux/list.h> |
2bbba277 | 17 | #include <linux/module.h> |
91da11f8 LB |
18 | #include <linux/netdevice.h> |
19 | #include <linux/phy.h> | |
87c8cefb | 20 | #include <linux/seq_file.h> |
c8f0b869 | 21 | #include <net/dsa.h> |
91da11f8 LB |
22 | #include "mv88e6xxx.h" |
23 | ||
16fe24fc AL |
24 | /* MDIO bus access can be nested in the case of PHYs connected to the |
25 | * internal MDIO bus of the switch, which is accessed via MDIO bus of | |
26 | * the Ethernet interface. Avoid lockdep false positives by using | |
27 | * mutex_lock_nested(). | |
28 | */ | |
29 | static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum) | |
30 | { | |
31 | int ret; | |
32 | ||
33 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
34 | ret = bus->read(bus, addr, regnum); | |
35 | mutex_unlock(&bus->mdio_lock); | |
36 | ||
37 | return ret; | |
38 | } | |
39 | ||
40 | static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, | |
41 | u16 val) | |
42 | { | |
43 | int ret; | |
44 | ||
45 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
46 | ret = bus->write(bus, addr, regnum, val); | |
47 | mutex_unlock(&bus->mdio_lock); | |
48 | ||
49 | return ret; | |
50 | } | |
51 | ||
3675c8d7 | 52 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
53 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
54 | * will be directly accessible on some {device address,register address} | |
55 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
56 | * will only respond to SMI transactions to that specific address, and | |
57 | * an indirect addressing mechanism needs to be used to access its | |
58 | * registers. | |
59 | */ | |
60 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
61 | { | |
62 | int ret; | |
63 | int i; | |
64 | ||
65 | for (i = 0; i < 16; i++) { | |
16fe24fc | 66 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
67 | if (ret < 0) |
68 | return ret; | |
69 | ||
cca8b133 | 70 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
71 | return 0; |
72 | } | |
73 | ||
74 | return -ETIMEDOUT; | |
75 | } | |
76 | ||
77 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
78 | { | |
79 | int ret; | |
80 | ||
81 | if (sw_addr == 0) | |
16fe24fc | 82 | return mv88e6xxx_mdiobus_read(bus, addr, reg); |
91da11f8 | 83 | |
3675c8d7 | 84 | /* Wait for the bus to become free. */ |
91da11f8 LB |
85 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
86 | if (ret < 0) | |
87 | return ret; | |
88 | ||
3675c8d7 | 89 | /* Transmit the read command. */ |
16fe24fc AL |
90 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
91 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
92 | if (ret < 0) |
93 | return ret; | |
94 | ||
3675c8d7 | 95 | /* Wait for the read command to complete. */ |
91da11f8 LB |
96 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
97 | if (ret < 0) | |
98 | return ret; | |
99 | ||
3675c8d7 | 100 | /* Read the data. */ |
16fe24fc | 101 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
102 | if (ret < 0) |
103 | return ret; | |
104 | ||
105 | return ret & 0xffff; | |
106 | } | |
107 | ||
8d6d09e7 GR |
108 | /* Must be called with SMI mutex held */ |
109 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 110 | { |
b184e497 | 111 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
112 | int ret; |
113 | ||
b184e497 GR |
114 | if (bus == NULL) |
115 | return -EINVAL; | |
116 | ||
b184e497 | 117 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
118 | if (ret < 0) |
119 | return ret; | |
120 | ||
121 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
122 | addr, reg, ret); | |
123 | ||
91da11f8 LB |
124 | return ret; |
125 | } | |
126 | ||
8d6d09e7 GR |
127 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
128 | { | |
129 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
130 | int ret; | |
131 | ||
132 | mutex_lock(&ps->smi_mutex); | |
133 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
134 | mutex_unlock(&ps->smi_mutex); | |
135 | ||
136 | return ret; | |
137 | } | |
138 | ||
91da11f8 LB |
139 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
140 | int reg, u16 val) | |
141 | { | |
142 | int ret; | |
143 | ||
144 | if (sw_addr == 0) | |
16fe24fc | 145 | return mv88e6xxx_mdiobus_write(bus, addr, reg, val); |
91da11f8 | 146 | |
3675c8d7 | 147 | /* Wait for the bus to become free. */ |
91da11f8 LB |
148 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
149 | if (ret < 0) | |
150 | return ret; | |
151 | ||
3675c8d7 | 152 | /* Transmit the data to write. */ |
16fe24fc | 153 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
154 | if (ret < 0) |
155 | return ret; | |
156 | ||
3675c8d7 | 157 | /* Transmit the write command. */ |
16fe24fc AL |
158 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
159 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
160 | if (ret < 0) |
161 | return ret; | |
162 | ||
3675c8d7 | 163 | /* Wait for the write command to complete. */ |
91da11f8 LB |
164 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
165 | if (ret < 0) | |
166 | return ret; | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
8d6d09e7 GR |
171 | /* Must be called with SMI mutex held */ |
172 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
173 | u16 val) | |
91da11f8 | 174 | { |
b184e497 | 175 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 176 | |
b184e497 GR |
177 | if (bus == NULL) |
178 | return -EINVAL; | |
179 | ||
bb92ea5e VD |
180 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
181 | addr, reg, val); | |
182 | ||
8d6d09e7 GR |
183 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
184 | } | |
185 | ||
186 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
187 | { | |
188 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
189 | int ret; | |
190 | ||
91da11f8 | 191 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 192 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
193 | mutex_unlock(&ps->smi_mutex); |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
2e5f0320 LB |
198 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
199 | { | |
cca8b133 AL |
200 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
201 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
202 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
91da11f8 LB |
207 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
208 | { | |
209 | int i; | |
210 | int ret; | |
211 | ||
212 | for (i = 0; i < 6; i++) { | |
213 | int j; | |
214 | ||
3675c8d7 | 215 | /* Write the MAC address byte. */ |
cca8b133 AL |
216 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
217 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 218 | |
3675c8d7 | 219 | /* Wait for the write to complete. */ |
91da11f8 | 220 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
221 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
222 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
223 | break; |
224 | } | |
225 | if (j == 16) | |
226 | return -ETIMEDOUT; | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
3898c148 | 232 | /* Must be called with SMI mutex held */ |
fd3a0ee4 | 233 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
234 | { |
235 | if (addr >= 0) | |
3898c148 | 236 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
237 | return 0xffff; |
238 | } | |
239 | ||
3898c148 | 240 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
241 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
242 | u16 val) | |
91da11f8 LB |
243 | { |
244 | if (addr >= 0) | |
3898c148 | 245 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
246 | return 0; |
247 | } | |
248 | ||
2e5f0320 LB |
249 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
250 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
251 | { | |
252 | int ret; | |
19b2f97e | 253 | unsigned long timeout; |
2e5f0320 | 254 | |
cca8b133 AL |
255 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
256 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
257 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 258 | |
19b2f97e BG |
259 | timeout = jiffies + 1 * HZ; |
260 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 261 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 262 | usleep_range(1000, 2000); |
cca8b133 AL |
263 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
264 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 265 | return 0; |
2e5f0320 LB |
266 | } |
267 | ||
268 | return -ETIMEDOUT; | |
269 | } | |
270 | ||
271 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
272 | { | |
273 | int ret; | |
19b2f97e | 274 | unsigned long timeout; |
2e5f0320 | 275 | |
cca8b133 AL |
276 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
277 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 278 | |
19b2f97e BG |
279 | timeout = jiffies + 1 * HZ; |
280 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 281 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 282 | usleep_range(1000, 2000); |
cca8b133 AL |
283 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
284 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 285 | return 0; |
2e5f0320 LB |
286 | } |
287 | ||
288 | return -ETIMEDOUT; | |
289 | } | |
290 | ||
291 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
292 | { | |
293 | struct mv88e6xxx_priv_state *ps; | |
294 | ||
295 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
296 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 297 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 298 | |
85686581 BG |
299 | if (mv88e6xxx_ppu_enable(ds) == 0) |
300 | ps->ppu_disabled = 0; | |
301 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
302 | } |
303 | } | |
304 | ||
305 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
306 | { | |
307 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
308 | ||
309 | schedule_work(&ps->ppu_work); | |
310 | } | |
311 | ||
312 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
313 | { | |
a22adce5 | 314 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
315 | int ret; |
316 | ||
317 | mutex_lock(&ps->ppu_mutex); | |
318 | ||
3675c8d7 | 319 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
320 | * we can access the PHY registers. If it was already |
321 | * disabled, cancel the timer that is going to re-enable | |
322 | * it. | |
323 | */ | |
324 | if (!ps->ppu_disabled) { | |
85686581 BG |
325 | ret = mv88e6xxx_ppu_disable(ds); |
326 | if (ret < 0) { | |
327 | mutex_unlock(&ps->ppu_mutex); | |
328 | return ret; | |
329 | } | |
330 | ps->ppu_disabled = 1; | |
2e5f0320 | 331 | } else { |
85686581 BG |
332 | del_timer(&ps->ppu_timer); |
333 | ret = 0; | |
2e5f0320 LB |
334 | } |
335 | ||
336 | return ret; | |
337 | } | |
338 | ||
339 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
340 | { | |
a22adce5 | 341 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 342 | |
3675c8d7 | 343 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
344 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
345 | mutex_unlock(&ps->ppu_mutex); | |
346 | } | |
347 | ||
348 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
349 | { | |
a22adce5 | 350 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
351 | |
352 | mutex_init(&ps->ppu_mutex); | |
353 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
354 | init_timer(&ps->ppu_timer); | |
355 | ps->ppu_timer.data = (unsigned long)ps; | |
356 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
357 | } | |
358 | ||
359 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
360 | { | |
361 | int ret; | |
362 | ||
363 | ret = mv88e6xxx_ppu_access_get(ds); | |
364 | if (ret >= 0) { | |
85686581 BG |
365 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
366 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
367 | } |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
373 | int regnum, u16 val) | |
374 | { | |
375 | int ret; | |
376 | ||
377 | ret = mv88e6xxx_ppu_access_get(ds); | |
378 | if (ret >= 0) { | |
85686581 BG |
379 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
380 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
381 | } |
382 | ||
383 | return ret; | |
384 | } | |
385 | #endif | |
386 | ||
91da11f8 LB |
387 | void mv88e6xxx_poll_link(struct dsa_switch *ds) |
388 | { | |
389 | int i; | |
390 | ||
391 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
392 | struct net_device *dev; | |
2a9e7978 | 393 | int uninitialized_var(port_status); |
91da11f8 LB |
394 | int link; |
395 | int speed; | |
396 | int duplex; | |
397 | int fc; | |
398 | ||
399 | dev = ds->ports[i]; | |
400 | if (dev == NULL) | |
401 | continue; | |
402 | ||
403 | link = 0; | |
404 | if (dev->flags & IFF_UP) { | |
cca8b133 AL |
405 | port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), |
406 | PORT_STATUS); | |
91da11f8 LB |
407 | if (port_status < 0) |
408 | continue; | |
409 | ||
cca8b133 | 410 | link = !!(port_status & PORT_STATUS_LINK); |
91da11f8 LB |
411 | } |
412 | ||
413 | if (!link) { | |
414 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 415 | netdev_info(dev, "link down\n"); |
91da11f8 LB |
416 | netif_carrier_off(dev); |
417 | } | |
418 | continue; | |
419 | } | |
420 | ||
cca8b133 AL |
421 | switch (port_status & PORT_STATUS_SPEED_MASK) { |
422 | case PORT_STATUS_SPEED_10: | |
91da11f8 LB |
423 | speed = 10; |
424 | break; | |
cca8b133 | 425 | case PORT_STATUS_SPEED_100: |
91da11f8 LB |
426 | speed = 100; |
427 | break; | |
cca8b133 | 428 | case PORT_STATUS_SPEED_1000: |
91da11f8 LB |
429 | speed = 1000; |
430 | break; | |
431 | default: | |
432 | speed = -1; | |
433 | break; | |
434 | } | |
cca8b133 AL |
435 | duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0; |
436 | fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0; | |
91da11f8 LB |
437 | |
438 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
439 | netdev_info(dev, |
440 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
441 | speed, | |
442 | duplex ? "full" : "half", | |
443 | fc ? "en" : "dis"); | |
91da11f8 LB |
444 | netif_carrier_on(dev); |
445 | } | |
446 | } | |
447 | } | |
448 | ||
54d792f2 AL |
449 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
450 | { | |
451 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
452 | ||
453 | switch (ps->id) { | |
454 | case PORT_SWITCH_ID_6031: | |
455 | case PORT_SWITCH_ID_6061: | |
456 | case PORT_SWITCH_ID_6035: | |
457 | case PORT_SWITCH_ID_6065: | |
458 | return true; | |
459 | } | |
460 | return false; | |
461 | } | |
462 | ||
463 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
464 | { | |
465 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
466 | ||
467 | switch (ps->id) { | |
468 | case PORT_SWITCH_ID_6092: | |
469 | case PORT_SWITCH_ID_6095: | |
470 | return true; | |
471 | } | |
472 | return false; | |
473 | } | |
474 | ||
475 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
476 | { | |
477 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
478 | ||
479 | switch (ps->id) { | |
480 | case PORT_SWITCH_ID_6046: | |
481 | case PORT_SWITCH_ID_6085: | |
482 | case PORT_SWITCH_ID_6096: | |
483 | case PORT_SWITCH_ID_6097: | |
484 | return true; | |
485 | } | |
486 | return false; | |
487 | } | |
488 | ||
489 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
490 | { | |
491 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
492 | ||
493 | switch (ps->id) { | |
494 | case PORT_SWITCH_ID_6123: | |
495 | case PORT_SWITCH_ID_6161: | |
496 | case PORT_SWITCH_ID_6165: | |
497 | return true; | |
498 | } | |
499 | return false; | |
500 | } | |
501 | ||
502 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
503 | { | |
504 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
505 | ||
506 | switch (ps->id) { | |
507 | case PORT_SWITCH_ID_6121: | |
508 | case PORT_SWITCH_ID_6122: | |
509 | case PORT_SWITCH_ID_6152: | |
510 | case PORT_SWITCH_ID_6155: | |
511 | case PORT_SWITCH_ID_6182: | |
512 | case PORT_SWITCH_ID_6185: | |
513 | case PORT_SWITCH_ID_6108: | |
514 | case PORT_SWITCH_ID_6131: | |
515 | return true; | |
516 | } | |
517 | return false; | |
518 | } | |
519 | ||
c22995c5 | 520 | static bool mv88e6xxx_6320_family(struct dsa_switch *ds) |
7c3d0d67 AK |
521 | { |
522 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
523 | ||
524 | switch (ps->id) { | |
525 | case PORT_SWITCH_ID_6320: | |
526 | case PORT_SWITCH_ID_6321: | |
527 | return true; | |
528 | } | |
529 | return false; | |
530 | } | |
531 | ||
54d792f2 AL |
532 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) |
533 | { | |
534 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
535 | ||
536 | switch (ps->id) { | |
537 | case PORT_SWITCH_ID_6171: | |
538 | case PORT_SWITCH_ID_6175: | |
539 | case PORT_SWITCH_ID_6350: | |
540 | case PORT_SWITCH_ID_6351: | |
541 | return true; | |
542 | } | |
543 | return false; | |
544 | } | |
545 | ||
f3a8b6b6 AL |
546 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
547 | { | |
548 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
549 | ||
550 | switch (ps->id) { | |
f3a8b6b6 AL |
551 | case PORT_SWITCH_ID_6172: |
552 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
553 | case PORT_SWITCH_ID_6240: |
554 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
555 | return true; |
556 | } | |
557 | return false; | |
558 | } | |
559 | ||
31888234 AL |
560 | /* Must be called with SMI mutex held */ |
561 | static int _mv88e6xxx_stats_wait(struct dsa_switch *ds) | |
91da11f8 LB |
562 | { |
563 | int ret; | |
564 | int i; | |
565 | ||
566 | for (i = 0; i < 10; i++) { | |
31888234 | 567 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 568 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
569 | return 0; |
570 | } | |
571 | ||
572 | return -ETIMEDOUT; | |
573 | } | |
574 | ||
31888234 AL |
575 | /* Must be called with SMI mutex held */ |
576 | static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
91da11f8 LB |
577 | { |
578 | int ret; | |
579 | ||
7c3d0d67 | 580 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) |
f3a8b6b6 AL |
581 | port = (port + 1) << 5; |
582 | ||
3675c8d7 | 583 | /* Snapshot the hardware statistics counters for this port. */ |
31888234 AL |
584 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
585 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
586 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
587 | if (ret < 0) | |
588 | return ret; | |
91da11f8 | 589 | |
3675c8d7 | 590 | /* Wait for the snapshotting to complete. */ |
31888234 | 591 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
592 | if (ret < 0) |
593 | return ret; | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
31888234 AL |
598 | /* Must be called with SMI mutex held */ |
599 | static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
91da11f8 LB |
600 | { |
601 | u32 _val; | |
602 | int ret; | |
603 | ||
604 | *val = 0; | |
605 | ||
31888234 AL |
606 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
607 | GLOBAL_STATS_OP_READ_CAPTURED | | |
608 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
609 | if (ret < 0) |
610 | return; | |
611 | ||
31888234 | 612 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
613 | if (ret < 0) |
614 | return; | |
615 | ||
31888234 | 616 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
617 | if (ret < 0) |
618 | return; | |
619 | ||
620 | _val = ret << 16; | |
621 | ||
31888234 | 622 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
623 | if (ret < 0) |
624 | return; | |
625 | ||
626 | *val = _val | ret; | |
627 | } | |
628 | ||
e413e7e1 AL |
629 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
630 | { "in_good_octets", 8, 0x00, }, | |
631 | { "in_bad_octets", 4, 0x02, }, | |
632 | { "in_unicast", 4, 0x04, }, | |
633 | { "in_broadcasts", 4, 0x06, }, | |
634 | { "in_multicasts", 4, 0x07, }, | |
635 | { "in_pause", 4, 0x16, }, | |
636 | { "in_undersize", 4, 0x18, }, | |
637 | { "in_fragments", 4, 0x19, }, | |
638 | { "in_oversize", 4, 0x1a, }, | |
639 | { "in_jabber", 4, 0x1b, }, | |
640 | { "in_rx_error", 4, 0x1c, }, | |
641 | { "in_fcs_error", 4, 0x1d, }, | |
642 | { "out_octets", 8, 0x0e, }, | |
643 | { "out_unicast", 4, 0x10, }, | |
644 | { "out_broadcasts", 4, 0x13, }, | |
645 | { "out_multicasts", 4, 0x12, }, | |
646 | { "out_pause", 4, 0x15, }, | |
647 | { "excessive", 4, 0x11, }, | |
648 | { "collisions", 4, 0x1e, }, | |
649 | { "deferred", 4, 0x05, }, | |
650 | { "single", 4, 0x14, }, | |
651 | { "multiple", 4, 0x17, }, | |
652 | { "out_fcs_error", 4, 0x03, }, | |
653 | { "late", 4, 0x1f, }, | |
654 | { "hist_64bytes", 4, 0x08, }, | |
655 | { "hist_65_127bytes", 4, 0x09, }, | |
656 | { "hist_128_255bytes", 4, 0x0a, }, | |
657 | { "hist_256_511bytes", 4, 0x0b, }, | |
658 | { "hist_512_1023bytes", 4, 0x0c, }, | |
659 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
660 | /* Not all devices have the following counters */ | |
661 | { "sw_in_discards", 4, 0x110, }, | |
662 | { "sw_in_filtered", 2, 0x112, }, | |
663 | { "sw_out_filtered", 2, 0x113, }, | |
664 | ||
665 | }; | |
666 | ||
667 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
668 | { | |
669 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
670 | ||
671 | switch (ps->id) { | |
cca8b133 AL |
672 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
673 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
674 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
675 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
676 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
677 | return true; |
678 | default: | |
679 | return false; | |
680 | } | |
681 | } | |
682 | ||
683 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
684 | int nr_stats, | |
685 | struct mv88e6xxx_hw_stat *stats, | |
686 | int port, uint8_t *data) | |
91da11f8 LB |
687 | { |
688 | int i; | |
689 | ||
690 | for (i = 0; i < nr_stats; i++) { | |
691 | memcpy(data + i * ETH_GSTRING_LEN, | |
692 | stats[i].string, ETH_GSTRING_LEN); | |
693 | } | |
694 | } | |
695 | ||
80c4627b AL |
696 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, |
697 | int stat, | |
698 | struct mv88e6xxx_hw_stat *stats, | |
699 | int port) | |
700 | { | |
701 | struct mv88e6xxx_hw_stat *s = stats + stat; | |
702 | u32 low; | |
703 | u32 high = 0; | |
704 | int ret; | |
705 | u64 value; | |
706 | ||
707 | if (s->reg >= 0x100) { | |
708 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
709 | s->reg - 0x100); | |
710 | if (ret < 0) | |
711 | return UINT64_MAX; | |
712 | ||
713 | low = ret; | |
714 | if (s->sizeof_stat == 4) { | |
715 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
716 | s->reg - 0x100 + 1); | |
717 | if (ret < 0) | |
718 | return UINT64_MAX; | |
719 | high = ret; | |
720 | } | |
721 | } else { | |
722 | _mv88e6xxx_stats_read(ds, s->reg, &low); | |
723 | if (s->sizeof_stat == 8) | |
724 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
725 | } | |
726 | value = (((u64)high) << 16) | low; | |
727 | return value; | |
728 | } | |
729 | ||
e413e7e1 AL |
730 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
731 | int nr_stats, | |
732 | struct mv88e6xxx_hw_stat *stats, | |
733 | int port, uint64_t *data) | |
91da11f8 | 734 | { |
a22adce5 | 735 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
736 | int ret; |
737 | int i; | |
738 | ||
31888234 | 739 | mutex_lock(&ps->smi_mutex); |
91da11f8 | 740 | |
31888234 | 741 | ret = _mv88e6xxx_stats_snapshot(ds, port); |
91da11f8 | 742 | if (ret < 0) { |
31888234 | 743 | mutex_unlock(&ps->smi_mutex); |
91da11f8 LB |
744 | return; |
745 | } | |
746 | ||
3675c8d7 | 747 | /* Read each of the counters. */ |
80c4627b AL |
748 | for (i = 0; i < nr_stats; i++) |
749 | data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port); | |
91da11f8 | 750 | |
31888234 | 751 | mutex_unlock(&ps->smi_mutex); |
91da11f8 | 752 | } |
98e67308 | 753 | |
e413e7e1 AL |
754 | /* All the statistics in the table */ |
755 | void | |
756 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
757 | { | |
758 | if (have_sw_in_discards(ds)) | |
759 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
760 | mv88e6xxx_hw_stats, port, data); | |
761 | else | |
762 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
763 | mv88e6xxx_hw_stats, port, data); | |
764 | } | |
765 | ||
766 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
767 | { | |
768 | if (have_sw_in_discards(ds)) | |
769 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
770 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
771 | } | |
772 | ||
773 | void | |
774 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
775 | int port, uint64_t *data) | |
776 | { | |
777 | if (have_sw_in_discards(ds)) | |
778 | _mv88e6xxx_get_ethtool_stats( | |
779 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
780 | mv88e6xxx_hw_stats, port, data); | |
781 | else | |
782 | _mv88e6xxx_get_ethtool_stats( | |
783 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
784 | mv88e6xxx_hw_stats, port, data); | |
785 | } | |
786 | ||
a1ab91f3 GR |
787 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
788 | { | |
789 | return 32 * sizeof(u16); | |
790 | } | |
791 | ||
792 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
793 | struct ethtool_regs *regs, void *_p) | |
794 | { | |
795 | u16 *p = _p; | |
796 | int i; | |
797 | ||
798 | regs->version = 0; | |
799 | ||
800 | memset(p, 0xff, 32 * sizeof(u16)); | |
801 | ||
802 | for (i = 0; i < 32; i++) { | |
803 | int ret; | |
804 | ||
805 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
806 | if (ret >= 0) | |
807 | p[i] = ret; | |
808 | } | |
809 | } | |
810 | ||
3898c148 AL |
811 | /* Must be called with SMI lock held */ |
812 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, | |
813 | u16 mask) | |
f3044683 AL |
814 | { |
815 | unsigned long timeout = jiffies + HZ / 10; | |
816 | ||
817 | while (time_before(jiffies, timeout)) { | |
818 | int ret; | |
819 | ||
3898c148 AL |
820 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
821 | if (ret < 0) | |
822 | return ret; | |
f3044683 AL |
823 | if (!(ret & mask)) |
824 | return 0; | |
825 | ||
826 | usleep_range(1000, 2000); | |
827 | } | |
828 | return -ETIMEDOUT; | |
829 | } | |
830 | ||
3898c148 AL |
831 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
832 | { | |
833 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
834 | int ret; | |
835 | ||
836 | mutex_lock(&ps->smi_mutex); | |
837 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
838 | mutex_unlock(&ps->smi_mutex); | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 844 | { |
3898c148 AL |
845 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
846 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
847 | } |
848 | ||
849 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
850 | { | |
cca8b133 AL |
851 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
852 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
853 | } |
854 | ||
855 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
856 | { | |
cca8b133 AL |
857 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
858 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
859 | } |
860 | ||
facd95b2 GR |
861 | /* Must be called with SMI lock held */ |
862 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
863 | { | |
cca8b133 AL |
864 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
865 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
866 | } |
867 | ||
56d95e22 AL |
868 | /* Must be called with SMI lock held */ |
869 | static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds) | |
870 | { | |
871 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC, | |
872 | GLOBAL2_SCRATCH_BUSY); | |
873 | } | |
874 | ||
3898c148 | 875 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
876 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
877 | int regnum) | |
f3044683 AL |
878 | { |
879 | int ret; | |
880 | ||
3898c148 AL |
881 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
882 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
883 | regnum); | |
884 | if (ret < 0) | |
885 | return ret; | |
f3044683 | 886 | |
3898c148 | 887 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
888 | if (ret < 0) |
889 | return ret; | |
890 | ||
3898c148 | 891 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
892 | } |
893 | ||
3898c148 | 894 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
895 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
896 | int regnum, u16 val) | |
f3044683 | 897 | { |
3898c148 AL |
898 | int ret; |
899 | ||
900 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
901 | if (ret < 0) | |
902 | return ret; | |
f3044683 | 903 | |
3898c148 AL |
904 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
905 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
906 | regnum); | |
907 | ||
908 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
909 | } |
910 | ||
11b3b45d GR |
911 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
912 | { | |
2f40c698 | 913 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
914 | int reg; |
915 | ||
3898c148 | 916 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
917 | |
918 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 919 | if (reg < 0) |
2f40c698 | 920 | goto out; |
11b3b45d GR |
921 | |
922 | e->eee_enabled = !!(reg & 0x0200); | |
923 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
924 | ||
3898c148 | 925 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 926 | if (reg < 0) |
2f40c698 | 927 | goto out; |
11b3b45d | 928 | |
cca8b133 | 929 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 930 | reg = 0; |
11b3b45d | 931 | |
2f40c698 | 932 | out: |
3898c148 | 933 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 934 | return reg; |
11b3b45d GR |
935 | } |
936 | ||
937 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
938 | struct phy_device *phydev, struct ethtool_eee *e) | |
939 | { | |
2f40c698 AL |
940 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
941 | int reg; | |
11b3b45d GR |
942 | int ret; |
943 | ||
3898c148 | 944 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 945 | |
2f40c698 AL |
946 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
947 | if (ret < 0) | |
948 | goto out; | |
949 | ||
950 | reg = ret & ~0x0300; | |
951 | if (e->eee_enabled) | |
952 | reg |= 0x0200; | |
953 | if (e->tx_lpi_enabled) | |
954 | reg |= 0x0100; | |
955 | ||
956 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
957 | out: | |
3898c148 | 958 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
959 | |
960 | return ret; | |
11b3b45d GR |
961 | } |
962 | ||
facd95b2 GR |
963 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd) |
964 | { | |
965 | int ret; | |
966 | ||
a08df0f0 | 967 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid); |
facd95b2 GR |
968 | if (ret < 0) |
969 | return ret; | |
970 | ||
cca8b133 | 971 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
972 | if (ret < 0) |
973 | return ret; | |
974 | ||
975 | return _mv88e6xxx_atu_wait(ds); | |
976 | } | |
977 | ||
978 | static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid) | |
979 | { | |
980 | int ret; | |
981 | ||
982 | ret = _mv88e6xxx_atu_wait(ds); | |
983 | if (ret < 0) | |
984 | return ret; | |
985 | ||
cca8b133 | 986 | return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB); |
facd95b2 GR |
987 | } |
988 | ||
989 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) | |
990 | { | |
991 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 992 | int reg, ret = 0; |
facd95b2 GR |
993 | u8 oldstate; |
994 | ||
995 | mutex_lock(&ps->smi_mutex); | |
996 | ||
cca8b133 | 997 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
998 | if (reg < 0) { |
999 | ret = reg; | |
facd95b2 | 1000 | goto abort; |
538cc282 | 1001 | } |
facd95b2 | 1002 | |
cca8b133 | 1003 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
1004 | if (oldstate != state) { |
1005 | /* Flush forwarding database if we're moving a port | |
1006 | * from Learning or Forwarding state to Disabled or | |
1007 | * Blocking or Listening state. | |
1008 | */ | |
cca8b133 AL |
1009 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
1010 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
facd95b2 GR |
1011 | ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]); |
1012 | if (ret) | |
1013 | goto abort; | |
1014 | } | |
cca8b133 AL |
1015 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1016 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1017 | reg); | |
facd95b2 GR |
1018 | } |
1019 | ||
1020 | abort: | |
1021 | mutex_unlock(&ps->smi_mutex); | |
1022 | return ret; | |
1023 | } | |
1024 | ||
1025 | /* Must be called with smi lock held */ | |
1026 | static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port) | |
1027 | { | |
1028 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1029 | u8 fid = ps->fid[port]; | |
1030 | u16 reg = fid << 12; | |
1031 | ||
1032 | if (dsa_is_cpu_port(ds, port)) | |
1033 | reg |= ds->phys_port_mask; | |
1034 | else | |
1035 | reg |= (ps->bridge_mask[fid] | | |
1036 | (1 << dsa_upstream_port(ds))) & ~(1 << port); | |
1037 | ||
cca8b133 | 1038 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1039 | } |
1040 | ||
1041 | /* Must be called with smi lock held */ | |
1042 | static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid) | |
1043 | { | |
1044 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1045 | int port; | |
1046 | u32 mask; | |
1047 | int ret; | |
1048 | ||
1049 | mask = ds->phys_port_mask; | |
1050 | while (mask) { | |
1051 | port = __ffs(mask); | |
1052 | mask &= ~(1 << port); | |
1053 | if (ps->fid[port] != fid) | |
1054 | continue; | |
1055 | ||
1056 | ret = _mv88e6xxx_update_port_config(ds, port); | |
1057 | if (ret) | |
1058 | return ret; | |
1059 | } | |
1060 | ||
1061 | return _mv88e6xxx_flush_fid(ds, fid); | |
1062 | } | |
1063 | ||
1064 | /* Bridge handling functions */ | |
1065 | ||
1066 | int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1067 | { | |
1068 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1069 | int ret = 0; | |
1070 | u32 nmask; | |
1071 | int fid; | |
1072 | ||
1073 | /* If the bridge group is not empty, join that group. | |
1074 | * Otherwise create a new group. | |
1075 | */ | |
1076 | fid = ps->fid[port]; | |
1077 | nmask = br_port_mask & ~(1 << port); | |
1078 | if (nmask) | |
1079 | fid = ps->fid[__ffs(nmask)]; | |
1080 | ||
1081 | nmask = ps->bridge_mask[fid] | (1 << port); | |
1082 | if (nmask != br_port_mask) { | |
1083 | netdev_err(ds->ports[port], | |
1084 | "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1085 | fid, br_port_mask, nmask); | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | ||
1089 | mutex_lock(&ps->smi_mutex); | |
1090 | ||
1091 | ps->bridge_mask[fid] = br_port_mask; | |
1092 | ||
1093 | if (fid != ps->fid[port]) { | |
194fea7b | 1094 | clear_bit(ps->fid[port], ps->fid_bitmap); |
facd95b2 GR |
1095 | ps->fid[port] = fid; |
1096 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1097 | } | |
1098 | ||
1099 | mutex_unlock(&ps->smi_mutex); | |
1100 | ||
1101 | return ret; | |
1102 | } | |
1103 | ||
1104 | int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1105 | { | |
1106 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1107 | u8 fid, newfid; | |
1108 | int ret; | |
1109 | ||
1110 | fid = ps->fid[port]; | |
1111 | ||
1112 | if (ps->bridge_mask[fid] != br_port_mask) { | |
1113 | netdev_err(ds->ports[port], | |
1114 | "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1115 | fid, br_port_mask, ps->bridge_mask[fid]); | |
1116 | return -EINVAL; | |
1117 | } | |
1118 | ||
1119 | /* If the port was the last port of a bridge, we are done. | |
1120 | * Otherwise assign a new fid to the port, and fix up | |
1121 | * the bridge configuration. | |
1122 | */ | |
1123 | if (br_port_mask == (1 << port)) | |
1124 | return 0; | |
1125 | ||
1126 | mutex_lock(&ps->smi_mutex); | |
1127 | ||
194fea7b VD |
1128 | newfid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID, 1); |
1129 | if (unlikely(newfid > ps->num_ports)) { | |
1130 | netdev_err(ds->ports[port], "all first %d FIDs are used\n", | |
1131 | ps->num_ports); | |
1132 | ret = -ENOSPC; | |
1133 | goto unlock; | |
1134 | } | |
1135 | ||
facd95b2 | 1136 | ps->fid[port] = newfid; |
194fea7b | 1137 | set_bit(newfid, ps->fid_bitmap); |
facd95b2 GR |
1138 | ps->bridge_mask[fid] &= ~(1 << port); |
1139 | ps->bridge_mask[newfid] = 1 << port; | |
1140 | ||
1141 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1142 | if (!ret) | |
1143 | ret = _mv88e6xxx_update_bridge_config(ds, newfid); | |
1144 | ||
194fea7b | 1145 | unlock: |
facd95b2 GR |
1146 | mutex_unlock(&ps->smi_mutex); |
1147 | ||
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) | |
1152 | { | |
1153 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1154 | int stp_state; | |
1155 | ||
1156 | switch (state) { | |
1157 | case BR_STATE_DISABLED: | |
cca8b133 | 1158 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1159 | break; |
1160 | case BR_STATE_BLOCKING: | |
1161 | case BR_STATE_LISTENING: | |
cca8b133 | 1162 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1163 | break; |
1164 | case BR_STATE_LEARNING: | |
cca8b133 | 1165 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1166 | break; |
1167 | case BR_STATE_FORWARDING: | |
1168 | default: | |
cca8b133 | 1169 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1170 | break; |
1171 | } | |
1172 | ||
1173 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1174 | ||
1175 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1176 | * so we can not update the port state directly but need to schedule it. | |
1177 | */ | |
1178 | ps->port_state[port] = stp_state; | |
1179 | set_bit(port, &ps->port_state_update_mask); | |
1180 | schedule_work(&ps->bridge_work); | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
c5723ac5 VD |
1185 | static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds, |
1186 | const unsigned char *addr) | |
defb05b9 GR |
1187 | { |
1188 | int i, ret; | |
1189 | ||
1190 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1191 | ret = _mv88e6xxx_reg_write( |
1192 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1193 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1194 | if (ret < 0) |
1195 | return ret; | |
1196 | } | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
c5723ac5 | 1201 | static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr) |
defb05b9 GR |
1202 | { |
1203 | int i, ret; | |
1204 | ||
1205 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1206 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1207 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1208 | if (ret < 0) |
1209 | return ret; | |
1210 | addr[i * 2] = ret >> 8; | |
1211 | addr[i * 2 + 1] = ret & 0xff; | |
1212 | } | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
cdf09697 DM |
1217 | static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port, |
1218 | const unsigned char *addr, int state) | |
defb05b9 | 1219 | { |
cdf09697 DM |
1220 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1221 | u8 fid = ps->fid[port]; | |
6630e236 VD |
1222 | int ret; |
1223 | ||
defb05b9 GR |
1224 | ret = _mv88e6xxx_atu_wait(ds); |
1225 | if (ret < 0) | |
1226 | return ret; | |
1227 | ||
c5723ac5 | 1228 | ret = _mv88e6xxx_atu_mac_write(ds, addr); |
defb05b9 GR |
1229 | if (ret < 0) |
1230 | return ret; | |
1231 | ||
cdf09697 DM |
1232 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, |
1233 | (0x10 << port) | state); | |
1234 | if (ret) | |
87820510 VD |
1235 | return ret; |
1236 | ||
cdf09697 | 1237 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB); |
87820510 | 1238 | |
cdf09697 | 1239 | return ret; |
87820510 VD |
1240 | } |
1241 | ||
cdf09697 DM |
1242 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1243 | const unsigned char *addr, u16 vid) | |
87820510 | 1244 | { |
cdf09697 | 1245 | int state = is_multicast_ether_addr(addr) ? |
87820510 VD |
1246 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1247 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
cdf09697 | 1248 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
87820510 VD |
1249 | int ret; |
1250 | ||
1251 | mutex_lock(&ps->smi_mutex); | |
cdf09697 | 1252 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state); |
87820510 VD |
1253 | mutex_unlock(&ps->smi_mutex); |
1254 | ||
1255 | return ret; | |
1256 | } | |
1257 | ||
cdf09697 DM |
1258 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
1259 | const unsigned char *addr, u16 vid) | |
87820510 VD |
1260 | { |
1261 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87820510 VD |
1262 | int ret; |
1263 | ||
1264 | mutex_lock(&ps->smi_mutex); | |
cdf09697 DM |
1265 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, |
1266 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
87820510 VD |
1267 | mutex_unlock(&ps->smi_mutex); |
1268 | ||
1269 | return ret; | |
1270 | } | |
1271 | ||
cdf09697 DM |
1272 | static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port, |
1273 | unsigned char *addr, bool *is_static) | |
6630e236 VD |
1274 | { |
1275 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
cdf09697 DM |
1276 | u8 fid = ps->fid[port]; |
1277 | int ret, state; | |
defb05b9 | 1278 | |
cdf09697 DM |
1279 | ret = _mv88e6xxx_atu_wait(ds); |
1280 | if (ret < 0) | |
1281 | return ret; | |
6630e236 | 1282 | |
c5723ac5 | 1283 | ret = _mv88e6xxx_atu_mac_write(ds, addr); |
6630e236 | 1284 | if (ret < 0) |
cdf09697 | 1285 | return ret; |
6630e236 VD |
1286 | |
1287 | do { | |
cdf09697 DM |
1288 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
1289 | if (ret < 0) | |
1290 | return ret; | |
6630e236 | 1291 | |
cdf09697 | 1292 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
6630e236 | 1293 | if (ret < 0) |
cdf09697 DM |
1294 | return ret; |
1295 | state = ret & GLOBAL_ATU_DATA_STATE_MASK; | |
1296 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
1297 | return -ENOENT; | |
1298 | } while (!(((ret >> 4) & 0xff) & (1 << port))); | |
6630e236 | 1299 | |
c5723ac5 | 1300 | ret = _mv88e6xxx_atu_mac_read(ds, addr); |
cdf09697 DM |
1301 | if (ret < 0) |
1302 | return ret; | |
6630e236 | 1303 | |
cdf09697 DM |
1304 | *is_static = state == (is_multicast_ether_addr(addr) ? |
1305 | GLOBAL_ATU_DATA_STATE_MC_STATIC : | |
1306 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | /* get next entry for port */ | |
1312 | int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, | |
2a778e1b | 1313 | unsigned char *addr, u16 *vid, bool *is_static) |
cdf09697 DM |
1314 | { |
1315 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1316 | int ret; | |
6630e236 | 1317 | |
cdf09697 DM |
1318 | mutex_lock(&ps->smi_mutex); |
1319 | ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static); | |
defb05b9 GR |
1320 | mutex_unlock(&ps->smi_mutex); |
1321 | ||
1322 | return ret; | |
1323 | } | |
1324 | ||
facd95b2 GR |
1325 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1326 | { | |
1327 | struct mv88e6xxx_priv_state *ps; | |
1328 | struct dsa_switch *ds; | |
1329 | int port; | |
1330 | ||
1331 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1332 | ds = ((struct dsa_switch *)ps) - 1; | |
1333 | ||
1334 | while (ps->port_state_update_mask) { | |
1335 | port = __ffs(ps->port_state_update_mask); | |
1336 | clear_bit(port, &ps->port_state_update_mask); | |
1337 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1338 | } | |
1339 | } | |
1340 | ||
dbde9e66 | 1341 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1342 | { |
1343 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
facd95b2 | 1344 | int ret, fid; |
54d792f2 | 1345 | u16 reg; |
d827e88a GR |
1346 | |
1347 | mutex_lock(&ps->smi_mutex); | |
1348 | ||
54d792f2 AL |
1349 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1350 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1351 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
7c3d0d67 | 1352 | mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1353 | /* MAC Forcing register: don't force link, speed, |
1354 | * duplex or flow control state to any particular | |
1355 | * values on physical ports, but force the CPU port | |
1356 | * and all DSA ports to their maximum bandwidth and | |
1357 | * full duplex. | |
1358 | */ | |
1359 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
1360 | if (dsa_is_cpu_port(ds, port) || | |
1361 | ds->dsa_port_mask & (1 << port)) { | |
1362 | reg |= PORT_PCS_CTRL_FORCE_LINK | | |
1363 | PORT_PCS_CTRL_LINK_UP | | |
1364 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1365 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1366 | if (mv88e6xxx_6065_family(ds)) | |
1367 | reg |= PORT_PCS_CTRL_100; | |
1368 | else | |
1369 | reg |= PORT_PCS_CTRL_1000; | |
1370 | } else { | |
1371 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1372 | } | |
1373 | ||
1374 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1375 | PORT_PCS_CTRL, reg); | |
1376 | if (ret) | |
1377 | goto abort; | |
1378 | } | |
1379 | ||
1380 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1381 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1382 | * tunneling, determine priority by looking at 802.1p and IP | |
1383 | * priority fields (IP prio has precedence), and set STP state | |
1384 | * to Forwarding. | |
1385 | * | |
1386 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1387 | * on which tagging mode was configured. | |
1388 | * | |
1389 | * If this is a link to another switch, use DSA tagging mode. | |
1390 | * | |
1391 | * If this is the upstream port for this switch, enable | |
1392 | * forwarding of unknown unicasts and multicasts. | |
1393 | */ | |
1394 | reg = 0; | |
1395 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1396 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1397 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1398 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1399 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
1400 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1401 | PORT_CONTROL_STATE_FORWARDING; | |
1402 | if (dsa_is_cpu_port(ds, port)) { | |
1403 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1404 | reg |= PORT_CONTROL_DSA_TAG; | |
1405 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
1406 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
1407 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1408 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1409 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1410 | else | |
1411 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1412 | } | |
1413 | ||
1414 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1415 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1416 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1417 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1418 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1419 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1420 | } | |
1421 | } | |
1422 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1423 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
1424 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || |
1425 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1426 | if (ds->dsa_port_mask & (1 << port)) |
1427 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1428 | if (port == dsa_upstream_port(ds)) | |
1429 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1430 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1431 | } | |
1432 | if (reg) { | |
1433 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1434 | PORT_CONTROL, reg); | |
1435 | if (ret) | |
1436 | goto abort; | |
1437 | } | |
1438 | ||
1439 | /* Port Control 2: don't force a good FCS, set the maximum | |
1440 | * frame size to 10240 bytes, don't let the switch add or | |
1441 | * strip 802.1q tags, don't discard tagged or untagged frames | |
1442 | * on this port, do a destination address lookup on all | |
1443 | * received packets as usual, disable ARP mirroring and don't | |
1444 | * send a copy of all transmitted/received frames on this port | |
1445 | * to the CPU. | |
1446 | */ | |
1447 | reg = 0; | |
1448 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1449 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 | 1450 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1451 | reg = PORT_CONTROL_2_MAP_DA; |
1452 | ||
1453 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 | 1454 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1455 | reg |= PORT_CONTROL_2_JUMBO_10240; |
1456 | ||
1457 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
1458 | /* Set the upstream port this port should use */ | |
1459 | reg |= dsa_upstream_port(ds); | |
1460 | /* enable forwarding of unknown multicast addresses to | |
1461 | * the upstream port | |
1462 | */ | |
1463 | if (port == dsa_upstream_port(ds)) | |
1464 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
1465 | } | |
1466 | ||
1467 | if (reg) { | |
1468 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1469 | PORT_CONTROL_2, reg); | |
1470 | if (ret) | |
1471 | goto abort; | |
1472 | } | |
1473 | ||
1474 | /* Port Association Vector: when learning source addresses | |
1475 | * of packets, add the address to the address database using | |
1476 | * a port bitmap that has only the bit for this port set and | |
1477 | * the other bits clear. | |
1478 | */ | |
1479 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, | |
1480 | 1 << port); | |
1481 | if (ret) | |
1482 | goto abort; | |
1483 | ||
1484 | /* Egress rate control 2: disable egress rate control. */ | |
1485 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
1486 | 0x0000); | |
1487 | if (ret) | |
1488 | goto abort; | |
1489 | ||
1490 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
1491 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
1492 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1493 | /* Do not limit the period of time that this port can |
1494 | * be paused for by the remote end or the period of | |
1495 | * time that this port can pause the remote end. | |
1496 | */ | |
1497 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1498 | PORT_PAUSE_CTRL, 0x0000); | |
1499 | if (ret) | |
1500 | goto abort; | |
1501 | ||
1502 | /* Port ATU control: disable limiting the number of | |
1503 | * address database entries that this port is allowed | |
1504 | * to use. | |
1505 | */ | |
1506 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1507 | PORT_ATU_CONTROL, 0x0000); | |
1508 | /* Priority Override: disable DA, SA and VTU priority | |
1509 | * override. | |
1510 | */ | |
1511 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1512 | PORT_PRI_OVERRIDE, 0x0000); | |
1513 | if (ret) | |
1514 | goto abort; | |
1515 | ||
1516 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
1517 | * value. | |
1518 | */ | |
1519 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1520 | PORT_ETH_TYPE, ETH_P_EDSA); | |
1521 | if (ret) | |
1522 | goto abort; | |
1523 | /* Tag Remap: use an identity 802.1p prio -> switch | |
1524 | * prio mapping. | |
1525 | */ | |
1526 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1527 | PORT_TAG_REGMAP_0123, 0x3210); | |
1528 | if (ret) | |
1529 | goto abort; | |
1530 | ||
1531 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
1532 | * prio mapping. | |
1533 | */ | |
1534 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1535 | PORT_TAG_REGMAP_4567, 0x7654); | |
1536 | if (ret) | |
1537 | goto abort; | |
1538 | } | |
1539 | ||
1540 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1541 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
1542 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
1543 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1544 | /* Rate Control: disable ingress rate limiting. */ |
1545 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1546 | PORT_RATE_CONTROL, 0x0001); | |
1547 | if (ret) | |
1548 | goto abort; | |
1549 | } | |
1550 | ||
366f0a0f GR |
1551 | /* Port Control 1: disable trunking, disable sending |
1552 | * learning messages to this port. | |
d827e88a | 1553 | */ |
614f03fc | 1554 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
1555 | if (ret) |
1556 | goto abort; | |
1557 | ||
1558 | /* Port based VLAN map: give each port its own address | |
1559 | * database, allow the CPU port to talk to each of the 'real' | |
1560 | * ports, and allow each of the 'real' ports to only talk to | |
1561 | * the upstream port. | |
1562 | */ | |
194fea7b | 1563 | fid = port + 1; |
facd95b2 | 1564 | ps->fid[port] = fid; |
194fea7b | 1565 | set_bit(fid, ps->fid_bitmap); |
facd95b2 GR |
1566 | |
1567 | if (!dsa_is_cpu_port(ds, port)) | |
1568 | ps->bridge_mask[fid] = 1 << port; | |
d827e88a | 1569 | |
facd95b2 | 1570 | ret = _mv88e6xxx_update_port_config(ds, port); |
d827e88a GR |
1571 | if (ret) |
1572 | goto abort; | |
1573 | ||
1574 | /* Default VLAN ID and priority: don't set a default VLAN | |
1575 | * ID, and set the default packet priority to zero. | |
1576 | */ | |
47cf1e65 VD |
1577 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
1578 | 0x0000); | |
d827e88a GR |
1579 | abort: |
1580 | mutex_unlock(&ps->smi_mutex); | |
1581 | return ret; | |
1582 | } | |
1583 | ||
dbde9e66 AL |
1584 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
1585 | { | |
1586 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1587 | int ret; | |
1588 | int i; | |
1589 | ||
1590 | for (i = 0; i < ps->num_ports; i++) { | |
1591 | ret = mv88e6xxx_setup_port(ds, i); | |
1592 | if (ret < 0) | |
1593 | return ret; | |
1594 | } | |
1595 | return 0; | |
1596 | } | |
1597 | ||
87c8cefb AL |
1598 | static int mv88e6xxx_regs_show(struct seq_file *s, void *p) |
1599 | { | |
1600 | struct dsa_switch *ds = s->private; | |
1601 | ||
1602 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1603 | int reg, port; | |
1604 | ||
1605 | seq_puts(s, " GLOBAL GLOBAL2 "); | |
1606 | for (port = 0 ; port < ps->num_ports; port++) | |
1607 | seq_printf(s, " %2d ", port); | |
1608 | seq_puts(s, "\n"); | |
1609 | ||
1610 | for (reg = 0; reg < 32; reg++) { | |
1611 | seq_printf(s, "%2x: ", reg); | |
1612 | seq_printf(s, " %4x %4x ", | |
1613 | mv88e6xxx_reg_read(ds, REG_GLOBAL, reg), | |
1614 | mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg)); | |
1615 | ||
1616 | for (port = 0 ; port < ps->num_ports; port++) | |
1617 | seq_printf(s, "%4x ", | |
1618 | mv88e6xxx_reg_read(ds, REG_PORT(port), reg)); | |
1619 | seq_puts(s, "\n"); | |
1620 | } | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | static int mv88e6xxx_regs_open(struct inode *inode, struct file *file) | |
1626 | { | |
1627 | return single_open(file, mv88e6xxx_regs_show, inode->i_private); | |
1628 | } | |
1629 | ||
1630 | static const struct file_operations mv88e6xxx_regs_fops = { | |
1631 | .open = mv88e6xxx_regs_open, | |
1632 | .read = seq_read, | |
1633 | .llseek = no_llseek, | |
1634 | .release = single_release, | |
1635 | .owner = THIS_MODULE, | |
1636 | }; | |
1637 | ||
8a0a265d AL |
1638 | static void mv88e6xxx_atu_show_header(struct seq_file *s) |
1639 | { | |
1640 | seq_puts(s, "DB T/P Vec State Addr\n"); | |
1641 | } | |
1642 | ||
1643 | static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum, | |
1644 | unsigned char *addr, int data) | |
1645 | { | |
1646 | bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK); | |
1647 | int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >> | |
1648 | GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT); | |
1649 | int state = data & GLOBAL_ATU_DATA_STATE_MASK; | |
1650 | ||
1651 | seq_printf(s, "%03x %5s %10pb %x %pM\n", | |
1652 | dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr); | |
1653 | } | |
1654 | ||
1655 | static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds, | |
1656 | int dbnum) | |
1657 | { | |
1658 | unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
1659 | unsigned char addr[6]; | |
1660 | int ret, data, state; | |
1661 | ||
c5723ac5 | 1662 | ret = _mv88e6xxx_atu_mac_write(ds, bcast); |
8a0a265d AL |
1663 | if (ret < 0) |
1664 | return ret; | |
1665 | ||
1666 | do { | |
1667 | ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB); | |
1668 | if (ret < 0) | |
1669 | return ret; | |
1670 | data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); | |
1671 | if (data < 0) | |
1672 | return data; | |
1673 | ||
1674 | state = data & GLOBAL_ATU_DATA_STATE_MASK; | |
1675 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
1676 | break; | |
c5723ac5 | 1677 | ret = _mv88e6xxx_atu_mac_read(ds, addr); |
8a0a265d AL |
1678 | if (ret < 0) |
1679 | return ret; | |
1680 | mv88e6xxx_atu_show_entry(s, dbnum, addr, data); | |
1681 | } while (state != GLOBAL_ATU_DATA_STATE_UNUSED); | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | static int mv88e6xxx_atu_show(struct seq_file *s, void *p) | |
1687 | { | |
1688 | struct dsa_switch *ds = s->private; | |
1689 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1690 | int dbnum; | |
1691 | ||
1692 | mv88e6xxx_atu_show_header(s); | |
1693 | ||
1694 | for (dbnum = 0; dbnum < 255; dbnum++) { | |
1695 | mutex_lock(&ps->smi_mutex); | |
1696 | mv88e6xxx_atu_show_db(s, ds, dbnum); | |
1697 | mutex_unlock(&ps->smi_mutex); | |
1698 | } | |
1699 | ||
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | static int mv88e6xxx_atu_open(struct inode *inode, struct file *file) | |
1704 | { | |
1705 | return single_open(file, mv88e6xxx_atu_show, inode->i_private); | |
1706 | } | |
1707 | ||
1708 | static const struct file_operations mv88e6xxx_atu_fops = { | |
1709 | .open = mv88e6xxx_atu_open, | |
1710 | .read = seq_read, | |
1711 | .llseek = no_llseek, | |
1712 | .release = single_release, | |
1713 | .owner = THIS_MODULE, | |
1714 | }; | |
1715 | ||
532c7a35 AL |
1716 | static void mv88e6xxx_stats_show_header(struct seq_file *s, |
1717 | struct mv88e6xxx_priv_state *ps) | |
1718 | { | |
1719 | int port; | |
1720 | ||
1721 | seq_puts(s, " Statistic "); | |
1722 | for (port = 0 ; port < ps->num_ports; port++) | |
1723 | seq_printf(s, "Port %2d ", port); | |
1724 | seq_puts(s, "\n"); | |
1725 | } | |
1726 | ||
1727 | static int mv88e6xxx_stats_show(struct seq_file *s, void *p) | |
1728 | { | |
1729 | struct dsa_switch *ds = s->private; | |
1730 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1731 | struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats; | |
1732 | int port, stat, max_stats; | |
1733 | uint64_t value; | |
1734 | ||
1735 | if (have_sw_in_discards(ds)) | |
1736 | max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats); | |
1737 | else | |
1738 | max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
1739 | ||
1740 | mv88e6xxx_stats_show_header(s, ps); | |
1741 | ||
1742 | mutex_lock(&ps->smi_mutex); | |
1743 | ||
1744 | for (stat = 0; stat < max_stats; stat++) { | |
1745 | seq_printf(s, "%19s: ", stats[stat].string); | |
1746 | for (port = 0 ; port < ps->num_ports; port++) { | |
1747 | _mv88e6xxx_stats_snapshot(ds, port); | |
1748 | value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats, | |
1749 | port); | |
1750 | seq_printf(s, "%8llu ", value); | |
1751 | } | |
1752 | seq_puts(s, "\n"); | |
1753 | } | |
1754 | mutex_unlock(&ps->smi_mutex); | |
1755 | ||
1756 | return 0; | |
1757 | } | |
1758 | ||
1759 | static int mv88e6xxx_stats_open(struct inode *inode, struct file *file) | |
1760 | { | |
1761 | return single_open(file, mv88e6xxx_stats_show, inode->i_private); | |
1762 | } | |
1763 | ||
1764 | static const struct file_operations mv88e6xxx_stats_fops = { | |
1765 | .open = mv88e6xxx_stats_open, | |
1766 | .read = seq_read, | |
1767 | .llseek = no_llseek, | |
1768 | .release = single_release, | |
1769 | .owner = THIS_MODULE, | |
1770 | }; | |
1771 | ||
d35bd876 AL |
1772 | static int mv88e6xxx_device_map_show(struct seq_file *s, void *p) |
1773 | { | |
1774 | struct dsa_switch *ds = s->private; | |
1775 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1776 | int target, ret; | |
1777 | ||
1778 | seq_puts(s, "Target Port\n"); | |
1779 | ||
1780 | mutex_lock(&ps->smi_mutex); | |
1781 | for (target = 0; target < 32; target++) { | |
1782 | ret = _mv88e6xxx_reg_write( | |
1783 | ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1784 | target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT); | |
1785 | if (ret < 0) | |
1786 | goto out; | |
1787 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2, | |
1788 | GLOBAL2_DEVICE_MAPPING); | |
1789 | seq_printf(s, " %2d %2d\n", target, | |
1790 | ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK); | |
1791 | } | |
1792 | out: | |
1793 | mutex_unlock(&ps->smi_mutex); | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file) | |
1799 | { | |
1800 | return single_open(file, mv88e6xxx_device_map_show, inode->i_private); | |
1801 | } | |
1802 | ||
1803 | static const struct file_operations mv88e6xxx_device_map_fops = { | |
1804 | .open = mv88e6xxx_device_map_open, | |
1805 | .read = seq_read, | |
1806 | .llseek = no_llseek, | |
1807 | .release = single_release, | |
1808 | .owner = THIS_MODULE, | |
1809 | }; | |
1810 | ||
56d95e22 AL |
1811 | static int mv88e6xxx_scratch_show(struct seq_file *s, void *p) |
1812 | { | |
1813 | struct dsa_switch *ds = s->private; | |
1814 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1815 | int reg, ret; | |
1816 | ||
1817 | seq_puts(s, "Register Value\n"); | |
1818 | ||
1819 | mutex_lock(&ps->smi_mutex); | |
1820 | for (reg = 0; reg < 0x80; reg++) { | |
1821 | ret = _mv88e6xxx_reg_write( | |
1822 | ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC, | |
1823 | reg << GLOBAL2_SCRATCH_REGISTER_SHIFT); | |
1824 | if (ret < 0) | |
1825 | goto out; | |
1826 | ||
1827 | ret = _mv88e6xxx_scratch_wait(ds); | |
1828 | if (ret < 0) | |
1829 | goto out; | |
1830 | ||
1831 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2, | |
1832 | GLOBAL2_SCRATCH_MISC); | |
1833 | seq_printf(s, " %2x %2x\n", reg, | |
1834 | ret & GLOBAL2_SCRATCH_VALUE_MASK); | |
1835 | } | |
1836 | out: | |
1837 | mutex_unlock(&ps->smi_mutex); | |
1838 | ||
1839 | return 0; | |
1840 | } | |
1841 | ||
1842 | static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file) | |
1843 | { | |
1844 | return single_open(file, mv88e6xxx_scratch_show, inode->i_private); | |
1845 | } | |
1846 | ||
1847 | static const struct file_operations mv88e6xxx_scratch_fops = { | |
1848 | .open = mv88e6xxx_scratch_open, | |
1849 | .read = seq_read, | |
1850 | .llseek = no_llseek, | |
1851 | .release = single_release, | |
1852 | .owner = THIS_MODULE, | |
1853 | }; | |
1854 | ||
acdaffcc GR |
1855 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
1856 | { | |
1857 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87c8cefb | 1858 | char *name; |
acdaffcc GR |
1859 | |
1860 | mutex_init(&ps->smi_mutex); | |
acdaffcc | 1861 | |
cca8b133 | 1862 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 1863 | |
facd95b2 GR |
1864 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); |
1865 | ||
87c8cefb AL |
1866 | name = kasprintf(GFP_KERNEL, "dsa%d", ds->index); |
1867 | ps->dbgfs = debugfs_create_dir(name, NULL); | |
1868 | kfree(name); | |
1869 | ||
1870 | debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds, | |
1871 | &mv88e6xxx_regs_fops); | |
1872 | ||
8a0a265d AL |
1873 | debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds, |
1874 | &mv88e6xxx_atu_fops); | |
1875 | ||
532c7a35 AL |
1876 | debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds, |
1877 | &mv88e6xxx_stats_fops); | |
1878 | ||
d35bd876 AL |
1879 | debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds, |
1880 | &mv88e6xxx_device_map_fops); | |
56d95e22 AL |
1881 | |
1882 | debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds, | |
1883 | &mv88e6xxx_scratch_fops); | |
acdaffcc GR |
1884 | return 0; |
1885 | } | |
1886 | ||
54d792f2 AL |
1887 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
1888 | { | |
1889 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
24751e29 | 1890 | int ret; |
54d792f2 AL |
1891 | int i; |
1892 | ||
1893 | /* Set the default address aging time to 5 minutes, and | |
1894 | * enable address learn messages to be sent to all message | |
1895 | * ports. | |
1896 | */ | |
1897 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
1898 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
1899 | ||
1900 | /* Configure the IP ToS mapping registers. */ | |
1901 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
1902 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
1903 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
1904 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
1905 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
1906 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
1907 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
1908 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
1909 | ||
1910 | /* Configure the IEEE 802.1p priority mapping register. */ | |
1911 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
1912 | ||
1913 | /* Send all frames with destination addresses matching | |
1914 | * 01:80:c2:00:00:0x to the CPU port. | |
1915 | */ | |
1916 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
1917 | ||
1918 | /* Ignore removed tag data on doubly tagged packets, disable | |
1919 | * flow control messages, force flow control priority to the | |
1920 | * highest, and send all special multicast frames to the CPU | |
1921 | * port at the highest priority. | |
1922 | */ | |
1923 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
1924 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
1925 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
1926 | ||
1927 | /* Program the DSA routing table. */ | |
1928 | for (i = 0; i < 32; i++) { | |
1929 | int nexthop = 0x1f; | |
1930 | ||
1931 | if (ds->pd->rtable && | |
1932 | i != ds->index && i < ds->dst->pd->nr_chips) | |
1933 | nexthop = ds->pd->rtable[i] & 0x1f; | |
1934 | ||
1935 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1936 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
1937 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
1938 | nexthop); | |
1939 | } | |
1940 | ||
1941 | /* Clear all trunk masks. */ | |
1942 | for (i = 0; i < 8; i++) | |
1943 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
1944 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
1945 | ((1 << ps->num_ports) - 1)); | |
1946 | ||
1947 | /* Clear all trunk mappings. */ | |
1948 | for (i = 0; i < 16; i++) | |
1949 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
1950 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
1951 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
1952 | ||
1953 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
1954 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
1955 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1956 | /* Send all frames with destination addresses matching |
1957 | * 01:80:c2:00:00:2x to the CPU port. | |
1958 | */ | |
1959 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
1960 | ||
1961 | /* Initialise cross-chip port VLAN table to reset | |
1962 | * defaults. | |
1963 | */ | |
1964 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
1965 | ||
1966 | /* Clear the priority override table. */ | |
1967 | for (i = 0; i < 16; i++) | |
1968 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
1969 | 0x8000 | (i << 8)); | |
1970 | } | |
1971 | ||
1972 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1973 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
1974 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
1975 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1976 | /* Disable ingress rate limiting by resetting all |
1977 | * ingress rate limit registers to their initial | |
1978 | * state. | |
1979 | */ | |
1980 | for (i = 0; i < ps->num_ports; i++) | |
1981 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
1982 | 0x9000 | (i << 8)); | |
1983 | } | |
1984 | ||
db687a56 AL |
1985 | /* Clear the statistics counters for all ports */ |
1986 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); | |
1987 | ||
1988 | /* Wait for the flush to complete. */ | |
24751e29 VD |
1989 | mutex_lock(&ps->smi_mutex); |
1990 | ret = _mv88e6xxx_stats_wait(ds); | |
1991 | mutex_unlock(&ps->smi_mutex); | |
db687a56 | 1992 | |
24751e29 | 1993 | return ret; |
54d792f2 AL |
1994 | } |
1995 | ||
143a8307 AL |
1996 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
1997 | { | |
1998 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1999 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
2000 | unsigned long timeout; | |
2001 | int ret; | |
2002 | int i; | |
2003 | ||
2004 | /* Set all ports to the disabled state. */ | |
2005 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
2006 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
2007 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
2008 | } |
2009 | ||
2010 | /* Wait for transmit queues to drain. */ | |
2011 | usleep_range(2000, 4000); | |
2012 | ||
2013 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2014 | * needs to be active to support indirect phy register access | |
2015 | * through global registers 0x18 and 0x19. | |
2016 | */ | |
2017 | if (ppu_active) | |
2018 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
2019 | else | |
2020 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
2021 | ||
2022 | /* Wait up to one second for reset to complete. */ | |
2023 | timeout = jiffies + 1 * HZ; | |
2024 | while (time_before(jiffies, timeout)) { | |
2025 | ret = REG_READ(REG_GLOBAL, 0x00); | |
2026 | if ((ret & is_reset) == is_reset) | |
2027 | break; | |
2028 | usleep_range(1000, 2000); | |
2029 | } | |
2030 | if (time_after(jiffies, timeout)) | |
2031 | return -ETIMEDOUT; | |
2032 | ||
2033 | return 0; | |
2034 | } | |
2035 | ||
49143585 AL |
2036 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
2037 | { | |
2038 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2039 | int ret; | |
2040 | ||
3898c148 | 2041 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2042 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2043 | if (ret < 0) |
2044 | goto error; | |
fd3a0ee4 | 2045 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 2046 | error: |
fd3a0ee4 | 2047 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2048 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2049 | return ret; |
2050 | } | |
2051 | ||
2052 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
2053 | int reg, int val) | |
2054 | { | |
2055 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2056 | int ret; | |
2057 | ||
3898c148 | 2058 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2059 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2060 | if (ret < 0) |
2061 | goto error; | |
2062 | ||
fd3a0ee4 | 2063 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 2064 | error: |
fd3a0ee4 | 2065 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2066 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2067 | return ret; |
2068 | } | |
2069 | ||
2070 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
2071 | { | |
2072 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2073 | ||
2074 | if (port >= 0 && port < ps->num_ports) | |
2075 | return port; | |
2076 | return -EINVAL; | |
2077 | } | |
2078 | ||
2079 | int | |
2080 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
2081 | { | |
2082 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2083 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2084 | int ret; | |
2085 | ||
2086 | if (addr < 0) | |
2087 | return addr; | |
2088 | ||
3898c148 | 2089 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2090 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 2091 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2092 | return ret; |
2093 | } | |
2094 | ||
2095 | int | |
2096 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
2097 | { | |
2098 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2099 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2100 | int ret; | |
2101 | ||
2102 | if (addr < 0) | |
2103 | return addr; | |
2104 | ||
3898c148 | 2105 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2106 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 2107 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2108 | return ret; |
2109 | } | |
2110 | ||
2111 | int | |
2112 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
2113 | { | |
2114 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2115 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2116 | int ret; | |
2117 | ||
2118 | if (addr < 0) | |
2119 | return addr; | |
2120 | ||
3898c148 | 2121 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2122 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 2123 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2124 | return ret; |
2125 | } | |
2126 | ||
2127 | int | |
2128 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
2129 | u16 val) | |
2130 | { | |
2131 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2132 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2133 | int ret; | |
2134 | ||
2135 | if (addr < 0) | |
2136 | return addr; | |
2137 | ||
3898c148 | 2138 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2139 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 2140 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2141 | return ret; |
2142 | } | |
2143 | ||
c22995c5 GR |
2144 | #ifdef CONFIG_NET_DSA_HWMON |
2145 | ||
2146 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
2147 | { | |
2148 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2149 | int ret; | |
2150 | int val; | |
2151 | ||
2152 | *temp = 0; | |
2153 | ||
2154 | mutex_lock(&ps->smi_mutex); | |
2155 | ||
2156 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); | |
2157 | if (ret < 0) | |
2158 | goto error; | |
2159 | ||
2160 | /* Enable temperature sensor */ | |
2161 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2162 | if (ret < 0) | |
2163 | goto error; | |
2164 | ||
2165 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); | |
2166 | if (ret < 0) | |
2167 | goto error; | |
2168 | ||
2169 | /* Wait for temperature to stabilize */ | |
2170 | usleep_range(10000, 12000); | |
2171 | ||
2172 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2173 | if (val < 0) { | |
2174 | ret = val; | |
2175 | goto error; | |
2176 | } | |
2177 | ||
2178 | /* Disable temperature sensor */ | |
2179 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); | |
2180 | if (ret < 0) | |
2181 | goto error; | |
2182 | ||
2183 | *temp = ((val & 0x1f) - 5) * 5; | |
2184 | ||
2185 | error: | |
2186 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); | |
2187 | mutex_unlock(&ps->smi_mutex); | |
2188 | return ret; | |
2189 | } | |
2190 | ||
2191 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
2192 | { | |
2193 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2194 | int ret; | |
2195 | ||
2196 | *temp = 0; | |
2197 | ||
2198 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27); | |
2199 | if (ret < 0) | |
2200 | return ret; | |
2201 | ||
2202 | *temp = (ret & 0xff) - 25; | |
2203 | ||
2204 | return 0; | |
2205 | } | |
2206 | ||
2207 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
2208 | { | |
2209 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) | |
2210 | return mv88e63xx_get_temp(ds, temp); | |
2211 | ||
2212 | return mv88e61xx_get_temp(ds, temp); | |
2213 | } | |
2214 | ||
2215 | int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) | |
2216 | { | |
2217 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2218 | int ret; | |
2219 | ||
2220 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2221 | return -EOPNOTSUPP; | |
2222 | ||
2223 | *temp = 0; | |
2224 | ||
2225 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2226 | if (ret < 0) | |
2227 | return ret; | |
2228 | ||
2229 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
2230 | ||
2231 | return 0; | |
2232 | } | |
2233 | ||
2234 | int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) | |
2235 | { | |
2236 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2237 | int ret; | |
2238 | ||
2239 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2240 | return -EOPNOTSUPP; | |
2241 | ||
2242 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2243 | if (ret < 0) | |
2244 | return ret; | |
2245 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
2246 | return mv88e6xxx_phy_page_write(ds, phy, 6, 26, | |
2247 | (ret & 0xe0ff) | (temp << 8)); | |
2248 | } | |
2249 | ||
2250 | int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
2251 | { | |
2252 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2253 | int ret; | |
2254 | ||
2255 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2256 | return -EOPNOTSUPP; | |
2257 | ||
2258 | *alarm = false; | |
2259 | ||
2260 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2261 | if (ret < 0) | |
2262 | return ret; | |
2263 | ||
2264 | *alarm = !!(ret & 0x40); | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | #endif /* CONFIG_NET_DSA_HWMON */ | |
2269 | ||
98e67308 BH |
2270 | static int __init mv88e6xxx_init(void) |
2271 | { | |
2272 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2273 | register_switch_driver(&mv88e6131_switch_driver); | |
2274 | #endif | |
2275 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
2276 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 2277 | #endif |
3ad50cca GR |
2278 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2279 | register_switch_driver(&mv88e6352_switch_driver); | |
2280 | #endif | |
42f27253 AL |
2281 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2282 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
2283 | #endif |
2284 | return 0; | |
2285 | } | |
2286 | module_init(mv88e6xxx_init); | |
2287 | ||
2288 | static void __exit mv88e6xxx_cleanup(void) | |
2289 | { | |
42f27253 AL |
2290 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2291 | unregister_switch_driver(&mv88e6171_switch_driver); | |
2292 | #endif | |
4212b543 VD |
2293 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2294 | unregister_switch_driver(&mv88e6352_switch_driver); | |
2295 | #endif | |
98e67308 BH |
2296 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
2297 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
2298 | #endif | |
2299 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2300 | unregister_switch_driver(&mv88e6131_switch_driver); | |
2301 | #endif | |
2302 | } | |
2303 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
2304 | |
2305 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
2306 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
2307 | MODULE_LICENSE("GPL"); |