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[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
87c8cefb 14#include <linux/debugfs.h>
19b2f97e 15#include <linux/delay.h>
defb05b9 16#include <linux/etherdevice.h>
dea87024 17#include <linux/ethtool.h>
facd95b2 18#include <linux/if_bridge.h>
19b2f97e 19#include <linux/jiffies.h>
91da11f8 20#include <linux/list.h>
2bbba277 21#include <linux/module.h>
91da11f8
LB		 22#include <linux/netdevice.h>
23#include <linux/phy.h>
87c8cefb 24#include <linux/seq_file.h>
c8f0b869 25#include <net/dsa.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
16fe24fc
AL		 28/* MDIO bus access can be nested in the case of PHYs connected to the
29 * internal MDIO bus of the switch, which is accessed via MDIO bus of
30 * the Ethernet interface. Avoid lockdep false positives by using
31 * mutex_lock_nested().
32 */
33static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
34{
35 int ret;
36
37 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
38 ret = bus->read(bus, addr, regnum);
39 mutex_unlock(&bus->mdio_lock);
40
41 return ret;
42}
43
44static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
45 u16 val)
46{
47 int ret;
48
49 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
50 ret = bus->write(bus, addr, regnum, val);
51 mutex_unlock(&bus->mdio_lock);
52
53 return ret;
54}
55
3675c8d7 56/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 57 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
58 * will be directly accessible on some {device address,register address}
59 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
60 * will only respond to SMI transactions to that specific address, and
61 * an indirect addressing mechanism needs to be used to access its
62 * registers.
63 */
64static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
65{
66 int ret;
67 int i;
68
69 for (i = 0; i < 16; i++) {
16fe24fc 70 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
91da11f8
LB		 71 if (ret < 0)
72 return ret;
73
cca8b133 74 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 75 return 0;
76 }
77
78 return -ETIMEDOUT;
79}
80
81int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
82{
83 int ret;
84
85 if (sw_addr == 0)
16fe24fc 86 return mv88e6xxx_mdiobus_read(bus, addr, reg);
91da11f8 87
3675c8d7 88 /* Wait for the bus to become free. */
91da11f8
LB		 89 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
90 if (ret < 0)
91 return ret;
92
3675c8d7 93 /* Transmit the read command. */
16fe24fc
AL		 94 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
95 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 96 if (ret < 0)
97 return ret;
98
3675c8d7 99 /* Wait for the read command to complete. */
91da11f8
LB		 100 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
101 if (ret < 0)
102 return ret;
103
3675c8d7 104 /* Read the data. */
16fe24fc 105 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
91da11f8
LB		 106 if (ret < 0)
107 return ret;
108
109 return ret & 0xffff;
110}
111
8d6d09e7
GR		 112/* Must be called with SMI mutex held */
113static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 114{
b184e497 115 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 116 int ret;
117
b184e497
GR		 118 if (bus == NULL)
119 return -EINVAL;
120
b184e497 121 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 122 if (ret < 0)
123 return ret;
124
125 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
126 addr, reg, ret);
127
91da11f8
LB		 128 return ret;
129}
130
8d6d09e7
GR		 131int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
132{
133 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
134 int ret;
135
136 mutex_lock(&ps->smi_mutex);
137 ret = _mv88e6xxx_reg_read(ds, addr, reg);
138 mutex_unlock(&ps->smi_mutex);
139
140 return ret;
141}
142
91da11f8
LB		 143int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
144 int reg, u16 val)
145{
146 int ret;
147
148 if (sw_addr == 0)
16fe24fc 149 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
91da11f8 150
3675c8d7 151 /* Wait for the bus to become free. */
91da11f8
LB		 152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
3675c8d7 156 /* Transmit the data to write. */
16fe24fc 157 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 158 if (ret < 0)
159 return ret;
160
3675c8d7 161 /* Transmit the write command. */
16fe24fc
AL		 162 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
163 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 164 if (ret < 0)
165 return ret;
166
3675c8d7 167 /* Wait for the write command to complete. */
91da11f8
LB		 168 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
169 if (ret < 0)
170 return ret;
171
172 return 0;
173}
174
8d6d09e7
GR		 175/* Must be called with SMI mutex held */
176static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
177 u16 val)
91da11f8 178{
b184e497 179 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 180
b184e497
GR		 181 if (bus == NULL)
182 return -EINVAL;
183
bb92ea5e
VD		 184 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
185 addr, reg, val);
186
8d6d09e7
GR		 187 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
188}
189
190int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
191{
192 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
193 int ret;
194
91da11f8 195 mutex_lock(&ps->smi_mutex);
8d6d09e7 196 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 197 mutex_unlock(&ps->smi_mutex);
198
199 return ret;
200}
201
2e5f0320
LB		 202int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
203{
cca8b133
AL		 204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
206 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 207
208 return 0;
209}
210
91da11f8
LB		 211int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
212{
213 int i;
214 int ret;
215
216 for (i = 0; i < 6; i++) {
217 int j;
218
3675c8d7 219 /* Write the MAC address byte. */
cca8b133
AL		 220 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
221 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 222
3675c8d7 223 /* Wait for the write to complete. */
91da11f8 224 for (j = 0; j < 16; j++) {
cca8b133
AL		 225 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
226 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 227 break;
228 }
229 if (j == 16)
230 return -ETIMEDOUT;
231 }
232
233 return 0;
234}
235
3898c148 236/* Must be called with SMI mutex held */
fd3a0ee4 237static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 238{
239 if (addr >= 0)
3898c148 240 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 241 return 0xffff;
242}
243
3898c148 244/* Must be called with SMI mutex held */
fd3a0ee4
AL		 245static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
246 u16 val)
91da11f8
LB		 247{
248 if (addr >= 0)
3898c148 249 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 250 return 0;
251}
252
2e5f0320
LB		 253#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
254static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
255{
256 int ret;
19b2f97e 257 unsigned long timeout;
2e5f0320 258
cca8b133
AL		 259 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
260 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
261 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 262
19b2f97e
BG		 263 timeout = jiffies + 1 * HZ;
264 while (time_before(jiffies, timeout)) {
cca8b133 265 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 266 usleep_range(1000, 2000);
cca8b133
AL		 267 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
268 GLOBAL_STATUS_PPU_POLLING)
85686581 269 return 0;
2e5f0320
LB		 270 }
271
272 return -ETIMEDOUT;
273}
274
275static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
276{
277 int ret;
19b2f97e 278 unsigned long timeout;
2e5f0320 279
cca8b133
AL		 280 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
281 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 282
19b2f97e
BG		 283 timeout = jiffies + 1 * HZ;
284 while (time_before(jiffies, timeout)) {
cca8b133 285 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 286 usleep_range(1000, 2000);
cca8b133
AL		 287 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
288 GLOBAL_STATUS_PPU_POLLING)
85686581 289 return 0;
2e5f0320
LB		 290 }
291
292 return -ETIMEDOUT;
293}
294
295static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
296{
297 struct mv88e6xxx_priv_state *ps;
298
299 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
300 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 301 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 302
85686581
BG		 303 if (mv88e6xxx_ppu_enable(ds) == 0)
304 ps->ppu_disabled = 0;
305 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 306 }
307}
308
309static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
310{
311 struct mv88e6xxx_priv_state *ps = (void *)_ps;
312
313 schedule_work(&ps->ppu_work);
314}
315
316static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
317{
a22adce5 318 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 319 int ret;
320
321 mutex_lock(&ps->ppu_mutex);
322
3675c8d7 323 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 324 * we can access the PHY registers. If it was already
325 * disabled, cancel the timer that is going to re-enable
326 * it.
327 */
328 if (!ps->ppu_disabled) {
85686581
BG		 329 ret = mv88e6xxx_ppu_disable(ds);
330 if (ret < 0) {
331 mutex_unlock(&ps->ppu_mutex);
332 return ret;
333 }
334 ps->ppu_disabled = 1;
2e5f0320 335 } else {
85686581
BG		 336 del_timer(&ps->ppu_timer);
337 ret = 0;
2e5f0320
LB		 338 }
339
340 return ret;
341}
342
343static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
344{
a22adce5 345 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 346
3675c8d7 347 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 348 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
349 mutex_unlock(&ps->ppu_mutex);
350}
351
352void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
353{
a22adce5 354 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 355
356 mutex_init(&ps->ppu_mutex);
357 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
358 init_timer(&ps->ppu_timer);
359 ps->ppu_timer.data = (unsigned long)ps;
360 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
361}
362
363int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
364{
365 int ret;
366
367 ret = mv88e6xxx_ppu_access_get(ds);
368 if (ret >= 0) {
85686581
BG		 369 ret = mv88e6xxx_reg_read(ds, addr, regnum);
370 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 371 }
372
373 return ret;
374}
375
376int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
377 int regnum, u16 val)
378{
379 int ret;
380
381 ret = mv88e6xxx_ppu_access_get(ds);
382 if (ret >= 0) {
85686581
BG		 383 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
384 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 385 }
386
387 return ret;
388}
389#endif
390
54d792f2
AL		 391static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
392{
393 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
394
395 switch (ps->id) {
396 case PORT_SWITCH_ID_6031:
397 case PORT_SWITCH_ID_6061:
398 case PORT_SWITCH_ID_6035:
399 case PORT_SWITCH_ID_6065:
400 return true;
401 }
402 return false;
403}
404
405static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
406{
407 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
408
409 switch (ps->id) {
410 case PORT_SWITCH_ID_6092:
411 case PORT_SWITCH_ID_6095:
412 return true;
413 }
414 return false;
415}
416
417static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
418{
419 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
420
421 switch (ps->id) {
422 case PORT_SWITCH_ID_6046:
423 case PORT_SWITCH_ID_6085:
424 case PORT_SWITCH_ID_6096:
425 case PORT_SWITCH_ID_6097:
426 return true;
427 }
428 return false;
429}
430
431static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
432{
433 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
434
435 switch (ps->id) {
436 case PORT_SWITCH_ID_6123:
437 case PORT_SWITCH_ID_6161:
438 case PORT_SWITCH_ID_6165:
439 return true;
440 }
441 return false;
442}
443
444static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
445{
446 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
447
448 switch (ps->id) {
449 case PORT_SWITCH_ID_6121:
450 case PORT_SWITCH_ID_6122:
451 case PORT_SWITCH_ID_6152:
452 case PORT_SWITCH_ID_6155:
453 case PORT_SWITCH_ID_6182:
454 case PORT_SWITCH_ID_6185:
455 case PORT_SWITCH_ID_6108:
456 case PORT_SWITCH_ID_6131:
457 return true;
458 }
459 return false;
460}
461
c22995c5 462static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 463{
464 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
465
466 switch (ps->id) {
467 case PORT_SWITCH_ID_6320:
468 case PORT_SWITCH_ID_6321:
469 return true;
470 }
471 return false;
472}
473
54d792f2
AL		 474static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
475{
476 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
477
478 switch (ps->id) {
479 case PORT_SWITCH_ID_6171:
480 case PORT_SWITCH_ID_6175:
481 case PORT_SWITCH_ID_6350:
482 case PORT_SWITCH_ID_6351:
483 return true;
484 }
485 return false;
486}
487
f3a8b6b6
AL		 488static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
489{
490 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
491
492 switch (ps->id) {
f3a8b6b6
AL		 493 case PORT_SWITCH_ID_6172:
494 case PORT_SWITCH_ID_6176:
54d792f2
AL		 495 case PORT_SWITCH_ID_6240:
496 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 497 return true;
498 }
499 return false;
500}
501
dea87024
AL		 502/* We expect the switch to perform auto negotiation if there is a real
503 * phy. However, in the case of a fixed link phy, we force the port
504 * settings from the fixed link settings.
505 */
506void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
507 struct phy_device *phydev)
508{
509 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 510 u32 reg;
511 int ret;
dea87024
AL		 512
513 if (!phy_is_pseudo_fixed_link(phydev))
514 return;
515
516 mutex_lock(&ps->smi_mutex);
517
518 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
519 if (ret < 0)
520 goto out;
521
522 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
523 PORT_PCS_CTRL_FORCE_LINK |
524 PORT_PCS_CTRL_DUPLEX_FULL |
525 PORT_PCS_CTRL_FORCE_DUPLEX |
526 PORT_PCS_CTRL_UNFORCED);
527
528 reg |= PORT_PCS_CTRL_FORCE_LINK;
529 if (phydev->link)
530 reg |= PORT_PCS_CTRL_LINK_UP;
531
532 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
533 goto out;
534
535 switch (phydev->speed) {
536 case SPEED_1000:
537 reg |= PORT_PCS_CTRL_1000;
538 break;
539 case SPEED_100:
540 reg |= PORT_PCS_CTRL_100;
541 break;
542 case SPEED_10:
543 reg |= PORT_PCS_CTRL_10;
544 break;
545 default:
546 pr_info("Unknown speed");
547 goto out;
548 }
549
550 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
551 if (phydev->duplex == DUPLEX_FULL)
552 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
553
e7e72ac0
AL		 554 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
555 (port >= ps->num_ports - 2)) {
556 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
557 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
558 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
559 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
560 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
561 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
562 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
563 }
dea87024
AL		 564 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
565
566out:
567 mutex_unlock(&ps->smi_mutex);
568}
569
31888234
AL		 570/* Must be called with SMI mutex held */
571static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 572{
573 int ret;
574 int i;
575
576 for (i = 0; i < 10; i++) {
31888234 577 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 578 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 579 return 0;
580 }
581
582 return -ETIMEDOUT;
583}
584
31888234
AL		 585/* Must be called with SMI mutex held */
586static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 587{
588 int ret;
589
7c3d0d67 590 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 591 port = (port + 1) << 5;
592
3675c8d7 593 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 594 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
595 GLOBAL_STATS_OP_CAPTURE_PORT |
596 GLOBAL_STATS_OP_HIST_RX_TX | port);
597 if (ret < 0)
598 return ret;
91da11f8 599
3675c8d7 600 /* Wait for the snapshotting to complete. */
31888234 601 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 602 if (ret < 0)
603 return ret;
604
605 return 0;
606}
607
31888234
AL		 608/* Must be called with SMI mutex held */
609static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 610{
611 u32 _val;
612 int ret;
613
614 *val = 0;
615
31888234
AL		 616 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
617 GLOBAL_STATS_OP_READ_CAPTURED |
618 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 619 if (ret < 0)
620 return;
621
31888234 622 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 623 if (ret < 0)
624 return;
625
31888234 626 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 627 if (ret < 0)
628 return;
629
630 _val = ret << 16;
631
31888234 632 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 633 if (ret < 0)
634 return;
635
636 *val = _val | ret;
637}
638
e413e7e1
AL		 639static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
640 { "in_good_octets", 8, 0x00, },
641 { "in_bad_octets", 4, 0x02, },
642 { "in_unicast", 4, 0x04, },
643 { "in_broadcasts", 4, 0x06, },
644 { "in_multicasts", 4, 0x07, },
645 { "in_pause", 4, 0x16, },
646 { "in_undersize", 4, 0x18, },
647 { "in_fragments", 4, 0x19, },
648 { "in_oversize", 4, 0x1a, },
649 { "in_jabber", 4, 0x1b, },
650 { "in_rx_error", 4, 0x1c, },
651 { "in_fcs_error", 4, 0x1d, },
652 { "out_octets", 8, 0x0e, },
653 { "out_unicast", 4, 0x10, },
654 { "out_broadcasts", 4, 0x13, },
655 { "out_multicasts", 4, 0x12, },
656 { "out_pause", 4, 0x15, },
657 { "excessive", 4, 0x11, },
658 { "collisions", 4, 0x1e, },
659 { "deferred", 4, 0x05, },
660 { "single", 4, 0x14, },
661 { "multiple", 4, 0x17, },
662 { "out_fcs_error", 4, 0x03, },
663 { "late", 4, 0x1f, },
664 { "hist_64bytes", 4, 0x08, },
665 { "hist_65_127bytes", 4, 0x09, },
666 { "hist_128_255bytes", 4, 0x0a, },
667 { "hist_256_511bytes", 4, 0x0b, },
668 { "hist_512_1023bytes", 4, 0x0c, },
669 { "hist_1024_max_bytes", 4, 0x0d, },
670 /* Not all devices have the following counters */
671 { "sw_in_discards", 4, 0x110, },
672 { "sw_in_filtered", 2, 0x112, },
673 { "sw_out_filtered", 2, 0x113, },
674
675};
676
677static bool have_sw_in_discards(struct dsa_switch *ds)
678{
679 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
680
681 switch (ps->id) {
cca8b133
AL		 682 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
683 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
684 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
685 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
686 case PORT_SWITCH_ID_6352:
e413e7e1
AL		 687 return true;
688 default:
689 return false;
690 }
691}
692
693static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
694 int nr_stats,
695 struct mv88e6xxx_hw_stat *stats,
696 int port, uint8_t *data)
91da11f8
LB		 697{
698 int i;
699
700 for (i = 0; i < nr_stats; i++) {
701 memcpy(data + i * ETH_GSTRING_LEN,
702 stats[i].string, ETH_GSTRING_LEN);
703 }
704}
705
80c4627b
AL		 706static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
707 int stat,
708 struct mv88e6xxx_hw_stat *stats,
709 int port)
710{
711 struct mv88e6xxx_hw_stat *s = stats + stat;
712 u32 low;
713 u32 high = 0;
714 int ret;
715 u64 value;
716
717 if (s->reg >= 0x100) {
718 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
719 s->reg - 0x100);
720 if (ret < 0)
721 return UINT64_MAX;
722
723 low = ret;
724 if (s->sizeof_stat == 4) {
725 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
726 s->reg - 0x100 + 1);
727 if (ret < 0)
728 return UINT64_MAX;
729 high = ret;
730 }
731 } else {
732 _mv88e6xxx_stats_read(ds, s->reg, &low);
733 if (s->sizeof_stat == 8)
734 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
735 }
736 value = (((u64)high) << 16) | low;
737 return value;
738}
739
e413e7e1
AL		 740static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
741 int nr_stats,
742 struct mv88e6xxx_hw_stat *stats,
743 int port, uint64_t *data)
91da11f8 744{
a22adce5 745 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8
LB		 746 int ret;
747 int i;
748
31888234 749 mutex_lock(&ps->smi_mutex);
91da11f8 750
31888234 751 ret = _mv88e6xxx_stats_snapshot(ds, port);
91da11f8 752 if (ret < 0) {
31888234 753 mutex_unlock(&ps->smi_mutex);
91da11f8
LB		 754 return;
755 }
756
3675c8d7 757 /* Read each of the counters. */
80c4627b
AL		 758 for (i = 0; i < nr_stats; i++)
759 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
91da11f8 760
31888234 761 mutex_unlock(&ps->smi_mutex);
91da11f8 762}
98e67308 763
e413e7e1
AL		 764/* All the statistics in the table */
765void
766mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
767{
768 if (have_sw_in_discards(ds))
769 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
770 mv88e6xxx_hw_stats, port, data);
771 else
772 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
773 mv88e6xxx_hw_stats, port, data);
774}
775
776int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
777{
778 if (have_sw_in_discards(ds))
779 return ARRAY_SIZE(mv88e6xxx_hw_stats);
780 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
781}
782
783void
784mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
785 int port, uint64_t *data)
786{
787 if (have_sw_in_discards(ds))
788 _mv88e6xxx_get_ethtool_stats(
789 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
790 mv88e6xxx_hw_stats, port, data);
791 else
792 _mv88e6xxx_get_ethtool_stats(
793 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
794 mv88e6xxx_hw_stats, port, data);
795}
796
a1ab91f3
GR		 797int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
798{
799 return 32 * sizeof(u16);
800}
801
802void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
803 struct ethtool_regs *regs, void *_p)
804{
805 u16 *p = _p;
806 int i;
807
808 regs->version = 0;
809
810 memset(p, 0xff, 32 * sizeof(u16));
811
812 for (i = 0; i < 32; i++) {
813 int ret;
814
815 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
816 if (ret >= 0)
817 p[i] = ret;
818 }
819}
820
3898c148
AL		 821/* Must be called with SMI lock held */
822static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
823 u16 mask)
f3044683
AL		 824{
825 unsigned long timeout = jiffies + HZ / 10;
826
827 while (time_before(jiffies, timeout)) {
828 int ret;
829
3898c148
AL		 830 ret = _mv88e6xxx_reg_read(ds, reg, offset);
831 if (ret < 0)
832 return ret;
f3044683
AL		 833 if (!(ret & mask))
834 return 0;
835
836 usleep_range(1000, 2000);
837 }
838 return -ETIMEDOUT;
839}
840
3898c148
AL		 841static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
842{
843 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
844 int ret;
845
846 mutex_lock(&ps->smi_mutex);
847 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
848 mutex_unlock(&ps->smi_mutex);
849
850 return ret;
851}
852
853static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 854{
3898c148
AL		 855 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
856 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 857}
858
859int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
860{
cca8b133
AL		 861 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
862 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 863}
864
865int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
866{
cca8b133
AL		 867 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
868 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 869}
870
facd95b2
GR		 871/* Must be called with SMI lock held */
872static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
873{
cca8b133
AL		 874 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
875 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 876}
877
56d95e22
AL		 878/* Must be called with SMI lock held */
879static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
880{
881 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
882 GLOBAL2_SCRATCH_BUSY);
883}
884
3898c148 885/* Must be called with SMI mutex held */
fd3a0ee4
AL		 886static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
887 int regnum)
f3044683
AL		 888{
889 int ret;
890
3898c148
AL		 891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
892 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
893 regnum);
894 if (ret < 0)
895 return ret;
f3044683 896
3898c148 897 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 898 if (ret < 0)
899 return ret;
900
3898c148 901 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 902}
903
3898c148 904/* Must be called with SMI mutex held */
fd3a0ee4
AL		 905static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
906 int regnum, u16 val)
f3044683 907{
3898c148
AL		 908 int ret;
909
910 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
911 if (ret < 0)
912 return ret;
f3044683 913
3898c148
AL		 914 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
915 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
916 regnum);
917
918 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 919}
920
11b3b45d
GR		 921int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
922{
2f40c698 923 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 924 int reg;
925
3898c148 926 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 927
928 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 929 if (reg < 0)
2f40c698 930 goto out;
11b3b45d
GR		 931
932 e->eee_enabled = !!(reg & 0x0200);
933 e->tx_lpi_enabled = !!(reg & 0x0100);
934
3898c148 935 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 936 if (reg < 0)
2f40c698 937 goto out;
11b3b45d 938
cca8b133 939 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 940 reg = 0;
11b3b45d 941
2f40c698 942out:
3898c148 943 mutex_unlock(&ps->smi_mutex);
2f40c698 944 return reg;
11b3b45d
GR		 945}
946
947int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
948 struct phy_device *phydev, struct ethtool_eee *e)
949{
2f40c698
AL		 950 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
951 int reg;
11b3b45d
GR		 952 int ret;
953
3898c148 954 mutex_lock(&ps->smi_mutex);
11b3b45d 955
2f40c698
AL		 956 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
957 if (ret < 0)
958 goto out;
959
960 reg = ret & ~0x0300;
961 if (e->eee_enabled)
962 reg |= 0x0200;
963 if (e->tx_lpi_enabled)
964 reg |= 0x0100;
965
966 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
967out:
3898c148 968 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 969
970 return ret;
11b3b45d
GR		 971}
972
70cc99d1 973static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
facd95b2
GR		 974{
975 int ret;
976
cca8b133 977 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 978 if (ret < 0)
979 return ret;
980
981 return _mv88e6xxx_atu_wait(ds);
982}
983
37705b73
VD		 984static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
985 struct mv88e6xxx_atu_entry *entry)
986{
987 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
988
989 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
990 unsigned int mask, shift;
991
992 if (entry->trunk) {
993 data |= GLOBAL_ATU_DATA_TRUNK;
994 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
995 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
996 } else {
997 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
998 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
999 }
1000
1001 data |= (entry->portv_trunkid << shift) & mask;
1002 }
1003
1004 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1005}
1006
7fb5e755
VD		 1007static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1008 struct mv88e6xxx_atu_entry *entry,
1009 bool static_too)
facd95b2 1010{
7fb5e755
VD		 1011 int op;
1012 int err;
facd95b2 1013
7fb5e755
VD		 1014 err = _mv88e6xxx_atu_wait(ds);
1015 if (err)
1016 return err;
facd95b2 1017
7fb5e755
VD		 1018 err = _mv88e6xxx_atu_data_write(ds, entry);
1019 if (err)
1020 return err;
1021
1022 if (entry->fid) {
1023 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1024 entry->fid);
1025 if (err)
1026 return err;
1027
1028 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1029 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1030 } else {
1031 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1032 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1033 }
1034
1035 return _mv88e6xxx_atu_cmd(ds, op);
1036}
1037
1038static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1039{
1040 struct mv88e6xxx_atu_entry entry = {
1041 .fid = fid,
1042 .state = 0, /* EntryState bits must be 0 */
1043 };
70cc99d1 1044
7fb5e755
VD		 1045 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1046}
1047
1048static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
1049{
1050 return _mv88e6xxx_atu_flush(ds, fid, false);
facd95b2
GR		 1051}
1052
9f4d55d2
VD		 1053static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1054 int to_port, bool static_too)
1055{
1056 struct mv88e6xxx_atu_entry entry = {
1057 .trunk = false,
1058 .fid = fid,
1059 };
1060
1061 /* EntryState bits must be 0xF */
1062 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1063
1064 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1065 entry.portv_trunkid = (to_port & 0x0f) << 4;
1066 entry.portv_trunkid |= from_port & 0x0f;
1067
1068 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1069}
1070
1071static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1072 bool static_too)
1073{
1074 /* Destination port 0xF means remove the entries */
1075 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1076}
1077
facd95b2
GR		 1078static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1079{
1080 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
c3ffe6d2 1081 int reg, ret = 0;
facd95b2
GR		 1082 u8 oldstate;
1083
1084 mutex_lock(&ps->smi_mutex);
1085
cca8b133 1086 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
538cc282
GR		 1087 if (reg < 0) {
1088 ret = reg;
facd95b2 1089 goto abort;
538cc282 1090 }
facd95b2 1091
cca8b133 1092 oldstate = reg & PORT_CONTROL_STATE_MASK;
facd95b2
GR		 1093 if (oldstate != state) {
1094 /* Flush forwarding database if we're moving a port
1095 * from Learning or Forwarding state to Disabled or
1096 * Blocking or Listening state.
1097 */
cca8b133
AL		 1098 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1099 state <= PORT_CONTROL_STATE_BLOCKING) {
2b8157b1 1100 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2
GR		 1101 if (ret)
1102 goto abort;
1103 }
cca8b133
AL		 1104 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1105 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1106 reg);
facd95b2
GR		 1107 }
1108
1109abort:
1110 mutex_unlock(&ps->smi_mutex);
1111 return ret;
1112}
1113
1114/* Must be called with smi lock held */
1115static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1116{
1117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1118 u8 fid = ps->fid[port];
1119 u16 reg = fid << 12;
1120
1121 if (dsa_is_cpu_port(ds, port))
1122 reg |= ds->phys_port_mask;
1123 else
1124 reg |= (ps->bridge_mask[fid] |
1125 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1126
cca8b133 1127 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1128}
1129
1130/* Must be called with smi lock held */
1131static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1132{
1133 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1134 int port;
1135 u32 mask;
1136 int ret;
1137
1138 mask = ds->phys_port_mask;
1139 while (mask) {
1140 port = __ffs(mask);
1141 mask &= ~(1 << port);
1142 if (ps->fid[port] != fid)
1143 continue;
1144
1145 ret = _mv88e6xxx_update_port_config(ds, port);
1146 if (ret)
1147 return ret;
1148 }
1149
1150 return _mv88e6xxx_flush_fid(ds, fid);
1151}
1152
1153/* Bridge handling functions */
1154
1155int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1156{
1157 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1158 int ret = 0;
1159 u32 nmask;
1160 int fid;
1161
1162 /* If the bridge group is not empty, join that group.
1163 * Otherwise create a new group.
1164 */
1165 fid = ps->fid[port];
1166 nmask = br_port_mask & ~(1 << port);
1167 if (nmask)
1168 fid = ps->fid[__ffs(nmask)];
1169
1170 nmask = ps->bridge_mask[fid] | (1 << port);
1171 if (nmask != br_port_mask) {
1172 netdev_err(ds->ports[port],
1173 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1174 fid, br_port_mask, nmask);
1175 return -EINVAL;
1176 }
1177
1178 mutex_lock(&ps->smi_mutex);
1179
1180 ps->bridge_mask[fid] = br_port_mask;
1181
1182 if (fid != ps->fid[port]) {
194fea7b 1183 clear_bit(ps->fid[port], ps->fid_bitmap);
facd95b2
GR		 1184 ps->fid[port] = fid;
1185 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1186 }
1187
1188 mutex_unlock(&ps->smi_mutex);
1189
1190 return ret;
1191}
1192
1193int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1194{
1195 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1196 u8 fid, newfid;
1197 int ret;
1198
1199 fid = ps->fid[port];
1200
1201 if (ps->bridge_mask[fid] != br_port_mask) {
1202 netdev_err(ds->ports[port],
1203 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1204 fid, br_port_mask, ps->bridge_mask[fid]);
1205 return -EINVAL;
1206 }
1207
1208 /* If the port was the last port of a bridge, we are done.
1209 * Otherwise assign a new fid to the port, and fix up
1210 * the bridge configuration.
1211 */
1212 if (br_port_mask == (1 << port))
1213 return 0;
1214
1215 mutex_lock(&ps->smi_mutex);
1216
194fea7b
VD		 1217 newfid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID, 1);
1218 if (unlikely(newfid > ps->num_ports)) {
1219 netdev_err(ds->ports[port], "all first %d FIDs are used\n",
1220 ps->num_ports);
1221 ret = -ENOSPC;
1222 goto unlock;
1223 }
1224
facd95b2 1225 ps->fid[port] = newfid;
194fea7b 1226 set_bit(newfid, ps->fid_bitmap);
facd95b2
GR		 1227 ps->bridge_mask[fid] &= ~(1 << port);
1228 ps->bridge_mask[newfid] = 1 << port;
1229
1230 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1231 if (!ret)
1232 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1233
194fea7b 1234unlock:
facd95b2
GR		 1235 mutex_unlock(&ps->smi_mutex);
1236
1237 return ret;
1238}
1239
1240int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1241{
1242 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1243 int stp_state;
1244
1245 switch (state) {
1246 case BR_STATE_DISABLED:
cca8b133 1247 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1248 break;
1249 case BR_STATE_BLOCKING:
1250 case BR_STATE_LISTENING:
cca8b133 1251 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1252 break;
1253 case BR_STATE_LEARNING:
cca8b133 1254 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1255 break;
1256 case BR_STATE_FORWARDING:
1257 default:
cca8b133 1258 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1259 break;
1260 }
1261
1262 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1263
1264 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1265 * so we can not update the port state directly but need to schedule it.
1266 */
1267 ps->port_state[port] = stp_state;
1268 set_bit(port, &ps->port_state_update_mask);
1269 schedule_work(&ps->bridge_work);
1270
1271 return 0;
1272}
1273
b8fee957
VD		 1274int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1275{
1276 int ret;
1277
1278 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1279 if (ret < 0)
1280 return ret;
1281
1282 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1283
1284 return 0;
1285}
1286
0d3b33e6
VD		 1287int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1288{
1289 return mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1290 pvid & PORT_DEFAULT_VLAN_MASK);
1291}
1292
6b17e864
VD		 1293static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1294{
1295 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1296 GLOBAL_VTU_OP_BUSY);
1297}
1298
1299static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1300{
1301 int ret;
1302
1303 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1304 if (ret < 0)
1305 return ret;
1306
1307 return _mv88e6xxx_vtu_wait(ds);
1308}
1309
1310static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1311{
1312 int ret;
1313
1314 ret = _mv88e6xxx_vtu_wait(ds);
1315 if (ret < 0)
1316 return ret;
1317
1318 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1319}
1320
b8fee957
VD		 1321static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1322 struct mv88e6xxx_vtu_stu_entry *entry,
1323 unsigned int nibble_offset)
1324{
1325 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1326 u16 regs[3];
1327 int i;
1328 int ret;
1329
1330 for (i = 0; i < 3; ++i) {
1331 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1332 GLOBAL_VTU_DATA_0_3 + i);
1333 if (ret < 0)
1334 return ret;
1335
1336 regs[i] = ret;
1337 }
1338
1339 for (i = 0; i < ps->num_ports; ++i) {
1340 unsigned int shift = (i % 4) * 4 + nibble_offset;
1341 u16 reg = regs[i / 4];
1342
1343 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1344 }
1345
1346 return 0;
1347}
1348
7dad08d7
VD		 1349static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1350 struct mv88e6xxx_vtu_stu_entry *entry,
1351 unsigned int nibble_offset)
1352{
1353 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1354 u16 regs[3] = { 0 };
1355 int i;
1356 int ret;
1357
1358 for (i = 0; i < ps->num_ports; ++i) {
1359 unsigned int shift = (i % 4) * 4 + nibble_offset;
1360 u8 data = entry->data[i];
1361
1362 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1363 }
1364
1365 for (i = 0; i < 3; ++i) {
1366 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1367 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1368 if (ret < 0)
1369 return ret;
1370 }
1371
1372 return 0;
1373}
1374
b8fee957
VD		 1375static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, u16 vid,
1376 struct mv88e6xxx_vtu_stu_entry *entry)
1377{
1378 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1379 int ret;
1380
1381 ret = _mv88e6xxx_vtu_wait(ds);
1382 if (ret < 0)
1383 return ret;
1384
1385 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1386 vid & GLOBAL_VTU_VID_MASK);
1387 if (ret < 0)
1388 return ret;
1389
1390 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1391 if (ret < 0)
1392 return ret;
1393
1394 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1395 if (ret < 0)
1396 return ret;
1397
1398 next.vid = ret & GLOBAL_VTU_VID_MASK;
1399 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1400
1401 if (next.valid) {
1402 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1403 if (ret < 0)
1404 return ret;
1405
1406 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1407 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1408 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1409 GLOBAL_VTU_FID);
1410 if (ret < 0)
1411 return ret;
1412
1413 next.fid = ret & GLOBAL_VTU_FID_MASK;
1414
1415 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1416 GLOBAL_VTU_SID);
1417 if (ret < 0)
1418 return ret;
1419
1420 next.sid = ret & GLOBAL_VTU_SID_MASK;
1421 }
1422 }
1423
1424 *entry = next;
1425 return 0;
1426}
1427
7dad08d7
VD		 1428static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1429 struct mv88e6xxx_vtu_stu_entry *entry)
1430{
1431 u16 reg = 0;
1432 int ret;
1433
1434 ret = _mv88e6xxx_vtu_wait(ds);
1435 if (ret < 0)
1436 return ret;
1437
1438 if (!entry->valid)
1439 goto loadpurge;
1440
1441 /* Write port member tags */
1442 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1443 if (ret < 0)
1444 return ret;
1445
1446 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1447 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1448 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1449 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1450 if (ret < 0)
1451 return ret;
1452
1453 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1454 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1455 if (ret < 0)
1456 return ret;
1457 }
1458
1459 reg = GLOBAL_VTU_VID_VALID;
1460loadpurge:
1461 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1462 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1463 if (ret < 0)
1464 return ret;
1465
1466 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1467}
1468
0d3b33e6
VD		 1469static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1470 struct mv88e6xxx_vtu_stu_entry *entry)
1471{
1472 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1473 int ret;
1474
1475 ret = _mv88e6xxx_vtu_wait(ds);
1476 if (ret < 0)
1477 return ret;
1478
1479 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1480 sid & GLOBAL_VTU_SID_MASK);
1481 if (ret < 0)
1482 return ret;
1483
1484 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1485 if (ret < 0)
1486 return ret;
1487
1488 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1489 if (ret < 0)
1490 return ret;
1491
1492 next.sid = ret & GLOBAL_VTU_SID_MASK;
1493
1494 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1495 if (ret < 0)
1496 return ret;
1497
1498 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1499
1500 if (next.valid) {
1501 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1502 if (ret < 0)
1503 return ret;
1504 }
1505
1506 *entry = next;
1507 return 0;
1508}
1509
1510static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1511 struct mv88e6xxx_vtu_stu_entry *entry)
1512{
1513 u16 reg = 0;
1514 int ret;
1515
1516 ret = _mv88e6xxx_vtu_wait(ds);
1517 if (ret < 0)
1518 return ret;
1519
1520 if (!entry->valid)
1521 goto loadpurge;
1522
1523 /* Write port states */
1524 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1525 if (ret < 0)
1526 return ret;
1527
1528 reg = GLOBAL_VTU_VID_VALID;
1529loadpurge:
1530 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1531 if (ret < 0)
1532 return ret;
1533
1534 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1535 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1536 if (ret < 0)
1537 return ret;
1538
1539 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1540}
1541
1542static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1543 struct mv88e6xxx_vtu_stu_entry *entry)
1544{
1545 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1546 struct mv88e6xxx_vtu_stu_entry vlan = {
1547 .valid = true,
1548 .vid = vid,
1549 };
1550 int i;
1551
1552 /* exclude all ports except the CPU */
1553 for (i = 0; i < ps->num_ports; ++i)
1554 vlan.data[i] = dsa_is_cpu_port(ds, i) ?
1555 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED :
1556 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1557
1558 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1559 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1560 struct mv88e6xxx_vtu_stu_entry vstp;
1561 int err;
1562
1563 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1564 * implemented, only one STU entry is needed to cover all VTU
1565 * entries. Thus, validate the SID 0.
1566 */
1567 vlan.sid = 0;
1568 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1569 if (err)
1570 return err;
1571
1572 if (vstp.sid != vlan.sid || !vstp.valid) {
1573 memset(&vstp, 0, sizeof(vstp));
1574 vstp.valid = true;
1575 vstp.sid = vlan.sid;
1576
1577 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1578 if (err)
1579 return err;
1580 }
1581
1582 /* Non-bridged ports and bridge groups use FIDs from 1 to
1583 * num_ports; VLANs use FIDs from num_ports+1 to 4095.
1584 */
1585 vlan.fid = find_next_zero_bit(ps->fid_bitmap, VLAN_N_VID,
1586 ps->num_ports + 1);
1587 if (unlikely(vlan.fid == VLAN_N_VID)) {
1588 pr_err("no more FID available for VLAN %d\n", vid);
1589 return -ENOSPC;
1590 }
1591
7c400018
VD		 1592 /* Clear all MAC addresses from the new database */
1593 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
0d3b33e6
VD		 1594 if (err)
1595 return err;
1596
1597 set_bit(vlan.fid, ps->fid_bitmap);
1598 }
1599
1600 *entry = vlan;
1601 return 0;
1602}
1603
1604int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1605 bool untagged)
1606{
1607 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1608 struct mv88e6xxx_vtu_stu_entry vlan;
1609 int err;
1610
1611 mutex_lock(&ps->smi_mutex);
1612 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1613 if (err)
1614 goto unlock;
1615
1616 if (vlan.vid != vid || !vlan.valid) {
1617 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1618 if (err)
1619 goto unlock;
1620 }
1621
1622 vlan.data[port] = untagged ?
1623 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1624 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1625
1626 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1627unlock:
1628 mutex_unlock(&ps->smi_mutex);
1629
1630 return err;
1631}
1632
7dad08d7
VD		 1633int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1634{
1635 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1636 struct mv88e6xxx_vtu_stu_entry vlan;
1637 bool keep = false;
1638 int i, err;
1639
1640 mutex_lock(&ps->smi_mutex);
1641
1642 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1643 if (err)
1644 goto unlock;
1645
1646 if (vlan.vid != vid || !vlan.valid ||
1647 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1648 err = -ENOENT;
1649 goto unlock;
1650 }
1651
1652 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1653
1654 /* keep the VLAN unless all ports are excluded */
1655 for (i = 0; i < ps->num_ports; ++i) {
1656 if (dsa_is_cpu_port(ds, i))
1657 continue;
1658
1659 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1660 keep = true;
1661 break;
1662 }
1663 }
1664
1665 vlan.valid = keep;
1666 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1667 if (err)
1668 goto unlock;
1669
9f4d55d2
VD		 1670 err = _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1671 if (err)
1672 goto unlock;
1673
7dad08d7
VD		 1674 if (!keep)
1675 clear_bit(vlan.fid, ps->fid_bitmap);
1676
1677unlock:
1678 mutex_unlock(&ps->smi_mutex);
1679
1680 return err;
1681}
1682
02512b6f
VD		 1683static int _mv88e6xxx_port_vtu_getnext(struct dsa_switch *ds, int port, u16 vid,
1684 struct mv88e6xxx_vtu_stu_entry *entry)
1685{
1686 int err;
1687
1688 do {
1689 if (vid == 4095)
1690 return -ENOENT;
1691
1692 err = _mv88e6xxx_vtu_getnext(ds, vid, entry);
1693 if (err)
1694 return err;
1695
1696 if (!entry->valid)
1697 return -ENOENT;
1698
1699 vid = entry->vid;
1700 } while (entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED &&
1701 entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED);
1702
1703 return 0;
1704}
1705
b8fee957
VD		 1706int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1707 unsigned long *ports, unsigned long *untagged)
1708{
1709 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1710 struct mv88e6xxx_vtu_stu_entry next;
1711 int port;
1712 int err;
1713
1714 if (*vid == 4095)
1715 return -ENOENT;
1716
1717 mutex_lock(&ps->smi_mutex);
1718 err = _mv88e6xxx_vtu_getnext(ds, *vid, &next);
1719 mutex_unlock(&ps->smi_mutex);
1720
1721 if (err)
1722 return err;
1723
1724 if (!next.valid)
1725 return -ENOENT;
1726
1727 *vid = next.vid;
1728
1729 for (port = 0; port < ps->num_ports; ++port) {
1730 clear_bit(port, ports);
1731 clear_bit(port, untagged);
1732
1733 if (dsa_is_cpu_port(ds, port))
1734 continue;
1735
1736 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1737 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1738 set_bit(port, ports);
1739
1740 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1741 set_bit(port, untagged);
1742 }
1743
1744 return 0;
1745}
1746
c5723ac5
VD		 1747static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1748 const unsigned char *addr)
defb05b9
GR		 1749{
1750 int i, ret;
1751
1752 for (i = 0; i < 3; i++) {
cca8b133
AL		 1753 ret = _mv88e6xxx_reg_write(
1754 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1755 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 1756 if (ret < 0)
1757 return ret;
1758 }
1759
1760 return 0;
1761}
1762
c5723ac5 1763static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 1764{
1765 int i, ret;
1766
1767 for (i = 0; i < 3; i++) {
cca8b133
AL		 1768 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1769 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 1770 if (ret < 0)
1771 return ret;
1772 addr[i * 2] = ret >> 8;
1773 addr[i * 2 + 1] = ret & 0xff;
1774 }
1775
1776 return 0;
1777}
1778
fd231c82
VD		 1779static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1780 struct mv88e6xxx_atu_entry *entry)
defb05b9 1781{
6630e236
VD		 1782 int ret;
1783
defb05b9
GR		 1784 ret = _mv88e6xxx_atu_wait(ds);
1785 if (ret < 0)
1786 return ret;
1787
fd231c82 1788 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 1789 if (ret < 0)
1790 return ret;
1791
37705b73 1792 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 1793 if (ret < 0)
87820510
VD		 1794 return ret;
1795
70cc99d1
VD		 1796 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1797 if (ret < 0)
1798 return ret;
1799
1800 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 1801}
87820510 1802
fd231c82
VD		 1803static int _mv88e6xxx_port_vid_to_fid(struct dsa_switch *ds, int port, u16 vid)
1804{
1805 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
02512b6f
VD		 1806 struct mv88e6xxx_vtu_stu_entry vlan;
1807 int err;
fd231c82
VD		 1808
1809 if (vid == 0)
1810 return ps->fid[port];
1811
02512b6f
VD		 1812 err = _mv88e6xxx_port_vtu_getnext(ds, port, vid - 1, &vlan);
1813 if (err)
1814 return err;
1815
1816 if (vlan.vid == vid)
1817 return vlan.fid;
1818
fd231c82
VD		 1819 return -ENOENT;
1820}
1821
1822static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1823 const unsigned char *addr, u16 vid,
1824 u8 state)
1825{
1826 struct mv88e6xxx_atu_entry entry = { 0 };
1827 int ret;
1828
1829 ret = _mv88e6xxx_port_vid_to_fid(ds, port, vid);
1830 if (ret < 0)
1831 return ret;
1832
1833 entry.fid = ret;
1834 entry.state = state;
1835 ether_addr_copy(entry.mac, addr);
1836 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1837 entry.trunk = false;
1838 entry.portv_trunkid = BIT(port);
1839 }
1840
1841 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 1842}
1843
cdf09697
DM		 1844int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1845 const unsigned char *addr, u16 vid)
87820510 1846{
cdf09697 1847 int state = is_multicast_ether_addr(addr) ?
87820510
VD		 1848 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1849 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 1850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1851 int ret;
1852
1853 mutex_lock(&ps->smi_mutex);
fd231c82 1854 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid, state);
87820510
VD		 1855 mutex_unlock(&ps->smi_mutex);
1856
1857 return ret;
1858}
1859
cdf09697
DM		 1860int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1861 const unsigned char *addr, u16 vid)
87820510
VD		 1862{
1863 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1864 int ret;
1865
1866 mutex_lock(&ps->smi_mutex);
fd231c82 1867 ret = _mv88e6xxx_port_fdb_load(ds, port, addr, vid,
cdf09697 1868 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 1869 mutex_unlock(&ps->smi_mutex);
1870
1871 return ret;
1872}
1873
1d194046
VD		 1874static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1875 const unsigned char *addr,
1876 struct mv88e6xxx_atu_entry *entry)
6630e236 1877{
1d194046
VD		 1878 struct mv88e6xxx_atu_entry next = { 0 };
1879 int ret;
1880
1881 next.fid = fid;
defb05b9 1882
cdf09697
DM		 1883 ret = _mv88e6xxx_atu_wait(ds);
1884 if (ret < 0)
1885 return ret;
6630e236 1886
c5723ac5 1887 ret = _mv88e6xxx_atu_mac_write(ds, addr);
6630e236 1888 if (ret < 0)
cdf09697 1889 return ret;
6630e236 1890
70cc99d1
VD		 1891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1892 if (ret < 0)
1893 return ret;
1894
1895 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 1896 if (ret < 0)
1897 return ret;
6630e236 1898
1d194046
VD		 1899 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1900 if (ret < 0)
1901 return ret;
6630e236 1902
1d194046 1903 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 1904 if (ret < 0)
1905 return ret;
6630e236 1906
1d194046
VD		 1907 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1908 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1909 unsigned int mask, shift;
1910
1911 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1912 next.trunk = true;
1913 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1914 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1915 } else {
1916 next.trunk = false;
1917 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1918 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1919 }
1920
1921 next.portv_trunkid = (ret & mask) >> shift;
1922 }
cdf09697 1923
1d194046 1924 *entry = next;
cdf09697
DM		 1925 return 0;
1926}
1927
1928/* get next entry for port */
1929int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
2a778e1b 1930 unsigned char *addr, u16 *vid, bool *is_static)
cdf09697
DM		 1931{
1932 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d194046
VD		 1933 struct mv88e6xxx_atu_entry next;
1934 u16 fid;
cdf09697 1935 int ret;
6630e236 1936
cdf09697 1937 mutex_lock(&ps->smi_mutex);
1d194046
VD		 1938
1939 ret = _mv88e6xxx_port_vid_to_fid(ds, port, *vid);
1940 if (ret < 0)
1941 goto unlock;
1942 fid = ret;
1943
1944 do {
1945 if (is_broadcast_ether_addr(addr)) {
02512b6f
VD		 1946 struct mv88e6xxx_vtu_stu_entry vtu;
1947
1948 ret = _mv88e6xxx_port_vtu_getnext(ds, port, *vid, &vtu);
1949 if (ret < 0)
1950 goto unlock;
1951
1952 *vid = vtu.vid;
1953 fid = vtu.fid;
1d194046
VD		 1954 }
1955
1956 ret = _mv88e6xxx_atu_getnext(ds, fid, addr, &next);
1957 if (ret < 0)
1958 goto unlock;
1959
1960 ether_addr_copy(addr, next.mac);
1961
1962 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1963 continue;
1964 } while (next.trunk || (next.portv_trunkid & BIT(port)) == 0);
1965
1966 *is_static = next.state == (is_multicast_ether_addr(addr) ?
1967 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1968 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1969unlock:
defb05b9
GR		 1970 mutex_unlock(&ps->smi_mutex);
1971
1972 return ret;
1973}
1974
facd95b2
GR		 1975static void mv88e6xxx_bridge_work(struct work_struct *work)
1976{
1977 struct mv88e6xxx_priv_state *ps;
1978 struct dsa_switch *ds;
1979 int port;
1980
1981 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1982 ds = ((struct dsa_switch *)ps) - 1;
1983
1984 while (ps->port_state_update_mask) {
1985 port = __ffs(ps->port_state_update_mask);
1986 clear_bit(port, &ps->port_state_update_mask);
1987 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1988 }
1989}
1990
dbde9e66 1991static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 1992{
1993 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
facd95b2 1994 int ret, fid;
54d792f2 1995 u16 reg;
d827e88a
GR		 1996
1997 mutex_lock(&ps->smi_mutex);
1998
54d792f2
AL		 1999 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2000 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2001 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 2002 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2003 /* MAC Forcing register: don't force link, speed,
2004 * duplex or flow control state to any particular
2005 * values on physical ports, but force the CPU port
2006 * and all DSA ports to their maximum bandwidth and
2007 * full duplex.
2008 */
2009 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2010 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2011 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2012 reg |= PORT_PCS_CTRL_FORCE_LINK |
2013 PORT_PCS_CTRL_LINK_UP |
2014 PORT_PCS_CTRL_DUPLEX_FULL |
2015 PORT_PCS_CTRL_FORCE_DUPLEX;
2016 if (mv88e6xxx_6065_family(ds))
2017 reg |= PORT_PCS_CTRL_100;
2018 else
2019 reg |= PORT_PCS_CTRL_1000;
2020 } else {
2021 reg |= PORT_PCS_CTRL_UNFORCED;
2022 }
2023
2024 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2025 PORT_PCS_CTRL, reg);
2026 if (ret)
2027 goto abort;
2028 }
2029
2030 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2031 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2032 * tunneling, determine priority by looking at 802.1p and IP
2033 * priority fields (IP prio has precedence), and set STP state
2034 * to Forwarding.
2035 *
2036 * If this is the CPU link, use DSA or EDSA tagging depending
2037 * on which tagging mode was configured.
2038 *
2039 * If this is a link to another switch, use DSA tagging mode.
2040 *
2041 * If this is the upstream port for this switch, enable
2042 * forwarding of unknown unicasts and multicasts.
2043 */
2044 reg = 0;
2045 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2046 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2047 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2048 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2049 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2050 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2051 PORT_CONTROL_STATE_FORWARDING;
2052 if (dsa_is_cpu_port(ds, port)) {
2053 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2054 reg |= PORT_CONTROL_DSA_TAG;
2055 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2056 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2057 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2058 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2059 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2060 else
2061 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2062 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2063 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2064 }
2065
2066 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2067 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2068 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2069 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2070 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2071 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2072 }
2073 }
6083ce71
AL		 2074 if (dsa_is_dsa_port(ds, port)) {
2075 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2076 reg |= PORT_CONTROL_DSA_TAG;
2077 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2078 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2079 mv88e6xxx_6320_family(ds)) {
54d792f2 2080 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2081 }
2082
54d792f2
AL		 2083 if (port == dsa_upstream_port(ds))
2084 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2085 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2086 }
2087 if (reg) {
2088 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2089 PORT_CONTROL, reg);
2090 if (ret)
2091 goto abort;
2092 }
2093
8efdda4a
VD		 2094 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2095 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2096 * untagged frames on this port, do a destination address lookup on all
2097 * received packets as usual, disable ARP mirroring and don't send a
2098 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2099 */
2100 reg = 0;
2101 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2102 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67 2103 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2104 reg = PORT_CONTROL_2_MAP_DA;
2105
2106 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2107 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2108 reg |= PORT_CONTROL_2_JUMBO_10240;
2109
2110 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2111 /* Set the upstream port this port should use */
2112 reg |= dsa_upstream_port(ds);
2113 /* enable forwarding of unknown multicast addresses to
2114 * the upstream port
2115 */
2116 if (port == dsa_upstream_port(ds))
2117 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2118 }
2119
f5117ce4 2120 reg |= PORT_CONTROL_2_8021Q_FALLBACK;
8efdda4a 2121
54d792f2
AL		 2122 if (reg) {
2123 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2124 PORT_CONTROL_2, reg);
2125 if (ret)
2126 goto abort;
2127 }
2128
2129 /* Port Association Vector: when learning source addresses
2130 * of packets, add the address to the address database using
2131 * a port bitmap that has only the bit for this port set and
2132 * the other bits clear.
2133 */
2134 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
2135 1 << port);
2136 if (ret)
2137 goto abort;
2138
2139 /* Egress rate control 2: disable egress rate control. */
2140 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2141 0x0000);
2142 if (ret)
2143 goto abort;
2144
2145 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2146 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2147 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2148 /* Do not limit the period of time that this port can
2149 * be paused for by the remote end or the period of
2150 * time that this port can pause the remote end.
2151 */
2152 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2153 PORT_PAUSE_CTRL, 0x0000);
2154 if (ret)
2155 goto abort;
2156
2157 /* Port ATU control: disable limiting the number of
2158 * address database entries that this port is allowed
2159 * to use.
2160 */
2161 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2162 PORT_ATU_CONTROL, 0x0000);
2163 /* Priority Override: disable DA, SA and VTU priority
2164 * override.
2165 */
2166 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2167 PORT_PRI_OVERRIDE, 0x0000);
2168 if (ret)
2169 goto abort;
2170
2171 /* Port Ethertype: use the Ethertype DSA Ethertype
2172 * value.
2173 */
2174 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2175 PORT_ETH_TYPE, ETH_P_EDSA);
2176 if (ret)
2177 goto abort;
2178 /* Tag Remap: use an identity 802.1p prio -> switch
2179 * prio mapping.
2180 */
2181 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2182 PORT_TAG_REGMAP_0123, 0x3210);
2183 if (ret)
2184 goto abort;
2185
2186 /* Tag Remap 2: use an identity 802.1p prio -> switch
2187 * prio mapping.
2188 */
2189 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2190 PORT_TAG_REGMAP_4567, 0x7654);
2191 if (ret)
2192 goto abort;
2193 }
2194
2195 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2196 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2197 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2198 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2199 /* Rate Control: disable ingress rate limiting. */
2200 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2201 PORT_RATE_CONTROL, 0x0001);
2202 if (ret)
2203 goto abort;
2204 }
2205
366f0a0f
GR		 2206 /* Port Control 1: disable trunking, disable sending
2207 * learning messages to this port.
d827e88a 2208 */
614f03fc 2209 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2210 if (ret)
2211 goto abort;
2212
2213 /* Port based VLAN map: give each port its own address
2214 * database, allow the CPU port to talk to each of the 'real'
2215 * ports, and allow each of the 'real' ports to only talk to
2216 * the upstream port.
2217 */
194fea7b 2218 fid = port + 1;
facd95b2 2219 ps->fid[port] = fid;
194fea7b 2220 set_bit(fid, ps->fid_bitmap);
facd95b2
GR		 2221
2222 if (!dsa_is_cpu_port(ds, port))
2223 ps->bridge_mask[fid] = 1 << port;
d827e88a 2224
facd95b2 2225 ret = _mv88e6xxx_update_port_config(ds, port);
d827e88a
GR		 2226 if (ret)
2227 goto abort;
2228
2229 /* Default VLAN ID and priority: don't set a default VLAN
2230 * ID, and set the default packet priority to zero.
2231 */
47cf1e65
VD		 2232 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2233 0x0000);
d827e88a
GR		 2234abort:
2235 mutex_unlock(&ps->smi_mutex);
2236 return ret;
2237}
2238
dbde9e66
AL		 2239int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2240{
2241 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2242 int ret;
2243 int i;
2244
2245 for (i = 0; i < ps->num_ports; i++) {
2246 ret = mv88e6xxx_setup_port(ds, i);
2247 if (ret < 0)
2248 return ret;
2249 }
2250 return 0;
2251}
2252
87c8cefb
AL		 2253static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
2254{
2255 struct dsa_switch *ds = s->private;
2256
2257 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2258 int reg, port;
2259
2260 seq_puts(s, " GLOBAL GLOBAL2 ");
2261 for (port = 0 ; port < ps->num_ports; port++)
2262 seq_printf(s, " %2d ", port);
2263 seq_puts(s, "\n");
2264
2265 for (reg = 0; reg < 32; reg++) {
2266 seq_printf(s, "%2x: ", reg);
2267 seq_printf(s, " %4x %4x ",
2268 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
2269 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
2270
2271 for (port = 0 ; port < ps->num_ports; port++)
2272 seq_printf(s, "%4x ",
2273 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
2274 seq_puts(s, "\n");
2275 }
2276
2277 return 0;
2278}
2279
2280static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
2281{
2282 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
2283}
2284
2285static const struct file_operations mv88e6xxx_regs_fops = {
2286 .open = mv88e6xxx_regs_open,
2287 .read = seq_read,
2288 .llseek = no_llseek,
2289 .release = single_release,
2290 .owner = THIS_MODULE,
2291};
2292
8a0a265d
AL		 2293static void mv88e6xxx_atu_show_header(struct seq_file *s)
2294{
2295 seq_puts(s, "DB T/P Vec State Addr\n");
2296}
2297
2298static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
2299 unsigned char *addr, int data)
2300{
2301 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
2302 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
2303 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
2304 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
2305
2306 seq_printf(s, "%03x %5s %10pb %x %pM\n",
2307 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
2308}
2309
2310static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
2311 int dbnum)
2312{
2313 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2314 unsigned char addr[6];
2315 int ret, data, state;
2316
c5723ac5 2317 ret = _mv88e6xxx_atu_mac_write(ds, bcast);
8a0a265d
AL		 2318 if (ret < 0)
2319 return ret;
2320
2321 do {
70cc99d1
VD		 2322 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
2323 dbnum);
8a0a265d
AL		 2324 if (ret < 0)
2325 return ret;
70cc99d1
VD		 2326
2327 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
2328 if (ret < 0)
2329 return ret;
2330
8a0a265d
AL		 2331 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2332 if (data < 0)
2333 return data;
2334
2335 state = data & GLOBAL_ATU_DATA_STATE_MASK;
2336 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
2337 break;
c5723ac5 2338 ret = _mv88e6xxx_atu_mac_read(ds, addr);
8a0a265d
AL		 2339 if (ret < 0)
2340 return ret;
2341 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
2342 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
2343
2344 return 0;
2345}
2346
2347static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
2348{
2349 struct dsa_switch *ds = s->private;
2350 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2351 int dbnum;
2352
2353 mv88e6xxx_atu_show_header(s);
2354
2355 for (dbnum = 0; dbnum < 255; dbnum++) {
2356 mutex_lock(&ps->smi_mutex);
2357 mv88e6xxx_atu_show_db(s, ds, dbnum);
2358 mutex_unlock(&ps->smi_mutex);
2359 }
2360
2361 return 0;
2362}
2363
2364static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
2365{
2366 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
2367}
2368
2369static const struct file_operations mv88e6xxx_atu_fops = {
2370 .open = mv88e6xxx_atu_open,
2371 .read = seq_read,
2372 .llseek = no_llseek,
2373 .release = single_release,
2374 .owner = THIS_MODULE,
2375};
2376
532c7a35
AL		 2377static void mv88e6xxx_stats_show_header(struct seq_file *s,
2378 struct mv88e6xxx_priv_state *ps)
2379{
2380 int port;
2381
2382 seq_puts(s, " Statistic ");
2383 for (port = 0 ; port < ps->num_ports; port++)
2384 seq_printf(s, "Port %2d ", port);
2385 seq_puts(s, "\n");
2386}
2387
2388static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
2389{
2390 struct dsa_switch *ds = s->private;
2391 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2392 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
2393 int port, stat, max_stats;
2394 uint64_t value;
2395
2396 if (have_sw_in_discards(ds))
2397 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
2398 else
2399 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
2400
2401 mv88e6xxx_stats_show_header(s, ps);
2402
2403 mutex_lock(&ps->smi_mutex);
2404
2405 for (stat = 0; stat < max_stats; stat++) {
2406 seq_printf(s, "%19s: ", stats[stat].string);
2407 for (port = 0 ; port < ps->num_ports; port++) {
2408 _mv88e6xxx_stats_snapshot(ds, port);
2409 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
2410 port);
2411 seq_printf(s, "%8llu ", value);
2412 }
2413 seq_puts(s, "\n");
2414 }
2415 mutex_unlock(&ps->smi_mutex);
2416
2417 return 0;
2418}
2419
2420static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
2421{
2422 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
2423}
2424
2425static const struct file_operations mv88e6xxx_stats_fops = {
2426 .open = mv88e6xxx_stats_open,
2427 .read = seq_read,
2428 .llseek = no_llseek,
2429 .release = single_release,
2430 .owner = THIS_MODULE,
2431};
2432
d35bd876
AL		 2433static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
2434{
2435 struct dsa_switch *ds = s->private;
2436 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2437 int target, ret;
2438
2439 seq_puts(s, "Target Port\n");
2440
2441 mutex_lock(&ps->smi_mutex);
2442 for (target = 0; target < 32; target++) {
2443 ret = _mv88e6xxx_reg_write(
2444 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2445 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
2446 if (ret < 0)
2447 goto out;
2448 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2449 GLOBAL2_DEVICE_MAPPING);
2450 seq_printf(s, " %2d %2d\n", target,
2451 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
2452 }
2453out:
2454 mutex_unlock(&ps->smi_mutex);
2455
2456 return 0;
2457}
2458
2459static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
2460{
2461 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
2462}
2463
2464static const struct file_operations mv88e6xxx_device_map_fops = {
2465 .open = mv88e6xxx_device_map_open,
2466 .read = seq_read,
2467 .llseek = no_llseek,
2468 .release = single_release,
2469 .owner = THIS_MODULE,
2470};
2471
56d95e22
AL		 2472static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
2473{
2474 struct dsa_switch *ds = s->private;
2475 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2476 int reg, ret;
2477
2478 seq_puts(s, "Register Value\n");
2479
2480 mutex_lock(&ps->smi_mutex);
2481 for (reg = 0; reg < 0x80; reg++) {
2482 ret = _mv88e6xxx_reg_write(
2483 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
2484 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
2485 if (ret < 0)
2486 goto out;
2487
2488 ret = _mv88e6xxx_scratch_wait(ds);
2489 if (ret < 0)
2490 goto out;
2491
2492 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2493 GLOBAL2_SCRATCH_MISC);
2494 seq_printf(s, " %2x %2x\n", reg,
2495 ret & GLOBAL2_SCRATCH_VALUE_MASK);
2496 }
2497out:
2498 mutex_unlock(&ps->smi_mutex);
2499
2500 return 0;
2501}
2502
2503static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
2504{
2505 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
2506}
2507
2508static const struct file_operations mv88e6xxx_scratch_fops = {
2509 .open = mv88e6xxx_scratch_open,
2510 .read = seq_read,
2511 .llseek = no_llseek,
2512 .release = single_release,
2513 .owner = THIS_MODULE,
2514};
2515
acdaffcc
GR		 2516int mv88e6xxx_setup_common(struct dsa_switch *ds)
2517{
2518 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87c8cefb 2519 char *name;
acdaffcc
GR		 2520
2521 mutex_init(&ps->smi_mutex);
acdaffcc 2522
cca8b133 2523 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2524
facd95b2
GR		 2525 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2526
87c8cefb
AL		 2527 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
2528 ps->dbgfs = debugfs_create_dir(name, NULL);
2529 kfree(name);
2530
2531 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
2532 &mv88e6xxx_regs_fops);
2533
8a0a265d
AL		 2534 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
2535 &mv88e6xxx_atu_fops);
2536
532c7a35
AL		 2537 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
2538 &mv88e6xxx_stats_fops);
2539
d35bd876
AL		 2540 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
2541 &mv88e6xxx_device_map_fops);
56d95e22
AL		 2542
2543 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
2544 &mv88e6xxx_scratch_fops);
acdaffcc
GR		 2545 return 0;
2546}
2547
54d792f2
AL		 2548int mv88e6xxx_setup_global(struct dsa_switch *ds)
2549{
2550 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2551 int ret;
54d792f2
AL		 2552 int i;
2553
2554 /* Set the default address aging time to 5 minutes, and
2555 * enable address learn messages to be sent to all message
2556 * ports.
2557 */
2558 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2559 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2560
2561 /* Configure the IP ToS mapping registers. */
2562 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2563 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2564 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2565 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2566 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2567 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2568 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2569 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2570
2571 /* Configure the IEEE 802.1p priority mapping register. */
2572 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2573
2574 /* Send all frames with destination addresses matching
2575 * 01:80:c2:00:00:0x to the CPU port.
2576 */
2577 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2578
2579 /* Ignore removed tag data on doubly tagged packets, disable
2580 * flow control messages, force flow control priority to the
2581 * highest, and send all special multicast frames to the CPU
2582 * port at the highest priority.
2583 */
2584 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2585 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2586 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2587
2588 /* Program the DSA routing table. */
2589 for (i = 0; i < 32; i++) {
2590 int nexthop = 0x1f;
2591
2592 if (ds->pd->rtable &&
2593 i != ds->index && i < ds->dst->pd->nr_chips)
2594 nexthop = ds->pd->rtable[i] & 0x1f;
2595
2596 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2597 GLOBAL2_DEVICE_MAPPING_UPDATE |
2598 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2599 nexthop);
2600 }
2601
2602 /* Clear all trunk masks. */
2603 for (i = 0; i < 8; i++)
2604 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2605 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2606 ((1 << ps->num_ports) - 1));
2607
2608 /* Clear all trunk mappings. */
2609 for (i = 0; i < 16; i++)
2610 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2611 GLOBAL2_TRUNK_MAPPING_UPDATE |
2612 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2613
2614 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2615 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2616 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2617 /* Send all frames with destination addresses matching
2618 * 01:80:c2:00:00:2x to the CPU port.
2619 */
2620 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2621
2622 /* Initialise cross-chip port VLAN table to reset
2623 * defaults.
2624 */
2625 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2626
2627 /* Clear the priority override table. */
2628 for (i = 0; i < 16; i++)
2629 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2630 0x8000 | (i << 8));
2631 }
2632
2633 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2634 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2635 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2636 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2637 /* Disable ingress rate limiting by resetting all
2638 * ingress rate limit registers to their initial
2639 * state.
2640 */
2641 for (i = 0; i < ps->num_ports; i++)
2642 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2643 0x9000 | (i << 8));
2644 }
2645
db687a56
AL		 2646 /* Clear the statistics counters for all ports */
2647 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2648
2649 /* Wait for the flush to complete. */
24751e29
VD		 2650 mutex_lock(&ps->smi_mutex);
2651 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2652 if (ret < 0)
2653 goto unlock;
2654
c161d0a5
VD		 2655 /* Clear all ATU entries */
2656 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2657 if (ret < 0)
2658 goto unlock;
2659
6b17e864
VD		 2660 /* Clear all the VTU and STU entries */
2661 ret = _mv88e6xxx_vtu_stu_flush(ds);
2662unlock:
24751e29 2663 mutex_unlock(&ps->smi_mutex);
db687a56 2664
24751e29 2665 return ret;
54d792f2
AL		 2666}
2667
143a8307
AL		 2668int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2669{
2670 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2671 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2672 unsigned long timeout;
2673 int ret;
2674 int i;
2675
2676 /* Set all ports to the disabled state. */
2677 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2678 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2679 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2680 }
2681
2682 /* Wait for transmit queues to drain. */
2683 usleep_range(2000, 4000);
2684
2685 /* Reset the switch. Keep the PPU active if requested. The PPU
2686 * needs to be active to support indirect phy register access
2687 * through global registers 0x18 and 0x19.
2688 */
2689 if (ppu_active)
2690 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2691 else
2692 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2693
2694 /* Wait up to one second for reset to complete. */
2695 timeout = jiffies + 1 * HZ;
2696 while (time_before(jiffies, timeout)) {
2697 ret = REG_READ(REG_GLOBAL, 0x00);
2698 if ((ret & is_reset) == is_reset)
2699 break;
2700 usleep_range(1000, 2000);
2701 }
2702 if (time_after(jiffies, timeout))
2703 return -ETIMEDOUT;
2704
2705 return 0;
2706}
2707
49143585
AL		 2708int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2709{
2710 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2711 int ret;
2712
3898c148 2713 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2714 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2715 if (ret < 0)
2716 goto error;
fd3a0ee4 2717 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
49143585 2718error:
fd3a0ee4 2719 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2720 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2721 return ret;
2722}
2723
2724int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2725 int reg, int val)
2726{
2727 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2728 int ret;
2729
3898c148 2730 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2731 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2732 if (ret < 0)
2733 goto error;
2734
fd3a0ee4 2735 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
49143585 2736error:
fd3a0ee4 2737 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2738 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2739 return ret;
2740}
2741
2742static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2743{
2744 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2745
2746 if (port >= 0 && port < ps->num_ports)
2747 return port;
2748 return -EINVAL;
2749}
2750
2751int
2752mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2753{
2754 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2755 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2756 int ret;
2757
2758 if (addr < 0)
2759 return addr;
2760
3898c148 2761 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2762 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2763 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2764 return ret;
2765}
2766
2767int
2768mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2769{
2770 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2771 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2772 int ret;
2773
2774 if (addr < 0)
2775 return addr;
2776
3898c148 2777 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2778 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2779 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2780 return ret;
2781}
2782
2783int
2784mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2785{
2786 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2787 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2788 int ret;
2789
2790 if (addr < 0)
2791 return addr;
2792
3898c148 2793 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2794 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2795 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2796 return ret;
2797}
2798
2799int
2800mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2801 u16 val)
2802{
2803 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2804 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2805 int ret;
2806
2807 if (addr < 0)
2808 return addr;
2809
3898c148 2810 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2811 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2812 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2813 return ret;
2814}
2815
c22995c5
GR		 2816#ifdef CONFIG_NET_DSA_HWMON
2817
2818static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2819{
2820 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2821 int ret;
2822 int val;
2823
2824 *temp = 0;
2825
2826 mutex_lock(&ps->smi_mutex);
2827
2828 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2829 if (ret < 0)
2830 goto error;
2831
2832 /* Enable temperature sensor */
2833 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2834 if (ret < 0)
2835 goto error;
2836
2837 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2838 if (ret < 0)
2839 goto error;
2840
2841 /* Wait for temperature to stabilize */
2842 usleep_range(10000, 12000);
2843
2844 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2845 if (val < 0) {
2846 ret = val;
2847 goto error;
2848 }
2849
2850 /* Disable temperature sensor */
2851 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2852 if (ret < 0)
2853 goto error;
2854
2855 *temp = ((val & 0x1f) - 5) * 5;
2856
2857error:
2858 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2859 mutex_unlock(&ps->smi_mutex);
2860 return ret;
2861}
2862
2863static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2864{
2865 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2866 int ret;
2867
2868 *temp = 0;
2869
2870 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2871 if (ret < 0)
2872 return ret;
2873
2874 *temp = (ret & 0xff) - 25;
2875
2876 return 0;
2877}
2878
2879int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2880{
2881 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2882 return mv88e63xx_get_temp(ds, temp);
2883
2884 return mv88e61xx_get_temp(ds, temp);
2885}
2886
2887int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2888{
2889 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2890 int ret;
2891
2892 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2893 return -EOPNOTSUPP;
2894
2895 *temp = 0;
2896
2897 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2898 if (ret < 0)
2899 return ret;
2900
2901 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2902
2903 return 0;
2904}
2905
2906int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2907{
2908 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2909 int ret;
2910
2911 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2912 return -EOPNOTSUPP;
2913
2914 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2915 if (ret < 0)
2916 return ret;
2917 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2918 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2919 (ret & 0xe0ff) | (temp << 8));
2920}
2921
2922int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2923{
2924 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2925 int ret;
2926
2927 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2928 return -EOPNOTSUPP;
2929
2930 *alarm = false;
2931
2932 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2933 if (ret < 0)
2934 return ret;
2935
2936 *alarm = !!(ret & 0x40);
2937
2938 return 0;
2939}
2940#endif /* CONFIG_NET_DSA_HWMON */
2941
98e67308
BH		 2942static int __init mv88e6xxx_init(void)
2943{
2944#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2945 register_switch_driver(&mv88e6131_switch_driver);
2946#endif
2947#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2948 register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253 2949#endif
3ad50cca
GR		 2950#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2951 register_switch_driver(&mv88e6352_switch_driver);
2952#endif
42f27253
AL		 2953#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2954 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 2955#endif
2956 return 0;
2957}
2958module_init(mv88e6xxx_init);
2959
2960static void __exit mv88e6xxx_cleanup(void)
2961{
42f27253
AL		 2962#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2963 unregister_switch_driver(&mv88e6171_switch_driver);
2964#endif
4212b543
VD		 2965#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2966 unregister_switch_driver(&mv88e6352_switch_driver);
2967#endif
98e67308
BH		 2968#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2969 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2970#endif
2971#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2972 unregister_switch_driver(&mv88e6131_switch_driver);
2973#endif
2974}
2975module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 2976
2977MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2978MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2979MODULE_LICENSE("GPL");
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