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netdev_features: Add NETIF_F_TSO_MANGLEID to NETIF_F_ALL_TSO
[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
3996a4ff
VD		 28static void assert_smi_lock(struct dsa_switch *ds)
29{
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36}
37
3675c8d7 38/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47{
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
6e899e6c 52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 53 if (ret < 0)
54 return ret;
55
cca8b133 56 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 57 return 0;
58 }
59
60 return -ETIMEDOUT;
61}
62
b9b37713
VD		 63static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
91da11f8
LB		 65{
66 int ret;
67
68 if (sw_addr == 0)
6e899e6c 69 return mdiobus_read_nested(bus, addr, reg);
91da11f8 70
3675c8d7 71 /* Wait for the bus to become free. */
91da11f8
LB		 72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
3675c8d7 76 /* Transmit the read command. */
6e899e6c
NA		 77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 79 if (ret < 0)
80 return ret;
81
3675c8d7 82 /* Wait for the read command to complete. */
91da11f8
LB		 83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
3675c8d7 87 /* Read the data. */
6e899e6c 88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93}
94
8d6d09e7 95static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 96{
a77d43f1 97 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8
LB		 98 int ret;
99
3996a4ff
VD		 100 assert_smi_lock(ds);
101
a77d43f1 102 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
bb92ea5e
VD		 103 if (ret < 0)
104 return ret;
105
106 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
107 addr, reg, ret);
108
91da11f8
LB		 109 return ret;
110}
111
8d6d09e7
GR		 112int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
113{
114 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
115 int ret;
116
117 mutex_lock(&ps->smi_mutex);
118 ret = _mv88e6xxx_reg_read(ds, addr, reg);
119 mutex_unlock(&ps->smi_mutex);
120
121 return ret;
122}
123
b9b37713
VD		 124static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
125 int reg, u16 val)
91da11f8
LB		 126{
127 int ret;
128
129 if (sw_addr == 0)
6e899e6c 130 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 131
3675c8d7 132 /* Wait for the bus to become free. */
91da11f8
LB		 133 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
134 if (ret < 0)
135 return ret;
136
3675c8d7 137 /* Transmit the data to write. */
6e899e6c 138 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 139 if (ret < 0)
140 return ret;
141
3675c8d7 142 /* Transmit the write command. */
6e899e6c
NA		 143 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
144 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 145 if (ret < 0)
146 return ret;
147
3675c8d7 148 /* Wait for the write command to complete. */
91da11f8
LB		 149 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
150 if (ret < 0)
151 return ret;
152
153 return 0;
154}
155
8d6d09e7
GR		 156static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
157 u16 val)
91da11f8 158{
a77d43f1 159 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 160
3996a4ff
VD		 161 assert_smi_lock(ds);
162
bb92ea5e
VD		 163 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
164 addr, reg, val);
165
a77d43f1 166 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
8d6d09e7
GR		 167}
168
169int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
170{
171 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
172 int ret;
173
91da11f8 174 mutex_lock(&ps->smi_mutex);
8d6d09e7 175 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 176 mutex_unlock(&ps->smi_mutex);
177
178 return ret;
179}
180
2e5f0320
LB		 181int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
182{
cca8b133
AL		 183 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
184 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
185 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 186
187 return 0;
188}
189
91da11f8
LB		 190int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
191{
192 int i;
193 int ret;
194
195 for (i = 0; i < 6; i++) {
196 int j;
197
3675c8d7 198 /* Write the MAC address byte. */
cca8b133
AL		 199 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
200 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 201
3675c8d7 202 /* Wait for the write to complete. */
91da11f8 203 for (j = 0; j < 16; j++) {
cca8b133
AL		 204 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
205 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 206 break;
207 }
208 if (j == 16)
209 return -ETIMEDOUT;
210 }
211
212 return 0;
213}
214
fd3a0ee4 215static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 216{
217 if (addr >= 0)
3898c148 218 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 219 return 0xffff;
220}
221
fd3a0ee4
AL		 222static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
223 u16 val)
91da11f8
LB		 224{
225 if (addr >= 0)
3898c148 226 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 227 return 0;
228}
229
2e5f0320
LB		 230#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
231static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
232{
233 int ret;
19b2f97e 234 unsigned long timeout;
2e5f0320 235
cca8b133
AL		 236 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
237 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
238 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 239
19b2f97e
BG		 240 timeout = jiffies + 1 * HZ;
241 while (time_before(jiffies, timeout)) {
cca8b133 242 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 243 usleep_range(1000, 2000);
cca8b133
AL		 244 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
245 GLOBAL_STATUS_PPU_POLLING)
85686581 246 return 0;
2e5f0320
LB		 247 }
248
249 return -ETIMEDOUT;
250}
251
252static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
253{
254 int ret;
19b2f97e 255 unsigned long timeout;
2e5f0320 256
cca8b133
AL		 257 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
258 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 259
19b2f97e
BG		 260 timeout = jiffies + 1 * HZ;
261 while (time_before(jiffies, timeout)) {
cca8b133 262 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 263 usleep_range(1000, 2000);
cca8b133
AL		 264 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
265 GLOBAL_STATUS_PPU_POLLING)
85686581 266 return 0;
2e5f0320
LB		 267 }
268
269 return -ETIMEDOUT;
270}
271
272static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
273{
274 struct mv88e6xxx_priv_state *ps;
275
276 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
277 if (mutex_trylock(&ps->ppu_mutex)) {
7543a6d5 278 struct dsa_switch *ds = ps->ds;
2e5f0320 279
85686581
BG		 280 if (mv88e6xxx_ppu_enable(ds) == 0)
281 ps->ppu_disabled = 0;
282 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 283 }
284}
285
286static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
287{
288 struct mv88e6xxx_priv_state *ps = (void *)_ps;
289
290 schedule_work(&ps->ppu_work);
291}
292
293static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
294{
a22adce5 295 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 296 int ret;
297
298 mutex_lock(&ps->ppu_mutex);
299
3675c8d7 300 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 301 * we can access the PHY registers. If it was already
302 * disabled, cancel the timer that is going to re-enable
303 * it.
304 */
305 if (!ps->ppu_disabled) {
85686581
BG		 306 ret = mv88e6xxx_ppu_disable(ds);
307 if (ret < 0) {
308 mutex_unlock(&ps->ppu_mutex);
309 return ret;
310 }
311 ps->ppu_disabled = 1;
2e5f0320 312 } else {
85686581
BG		 313 del_timer(&ps->ppu_timer);
314 ret = 0;
2e5f0320
LB		 315 }
316
317 return ret;
318}
319
320static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
321{
a22adce5 322 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 323
3675c8d7 324 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 325 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
326 mutex_unlock(&ps->ppu_mutex);
327}
328
329void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
330{
a22adce5 331 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 332
333 mutex_init(&ps->ppu_mutex);
334 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
335 init_timer(&ps->ppu_timer);
336 ps->ppu_timer.data = (unsigned long)ps;
337 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
338}
339
340int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
341{
342 int ret;
343
344 ret = mv88e6xxx_ppu_access_get(ds);
345 if (ret >= 0) {
85686581
BG		 346 ret = mv88e6xxx_reg_read(ds, addr, regnum);
347 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 348 }
349
350 return ret;
351}
352
353int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
354 int regnum, u16 val)
355{
356 int ret;
357
358 ret = mv88e6xxx_ppu_access_get(ds);
359 if (ret >= 0) {
85686581
BG		 360 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
361 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 362 }
363
364 return ret;
365}
366#endif
367
54d792f2
AL		 368static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
369{
370 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
371
372 switch (ps->id) {
373 case PORT_SWITCH_ID_6031:
374 case PORT_SWITCH_ID_6061:
375 case PORT_SWITCH_ID_6035:
376 case PORT_SWITCH_ID_6065:
377 return true;
378 }
379 return false;
380}
381
382static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
383{
384 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
385
386 switch (ps->id) {
387 case PORT_SWITCH_ID_6092:
388 case PORT_SWITCH_ID_6095:
389 return true;
390 }
391 return false;
392}
393
394static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
395{
396 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
397
398 switch (ps->id) {
399 case PORT_SWITCH_ID_6046:
400 case PORT_SWITCH_ID_6085:
401 case PORT_SWITCH_ID_6096:
402 case PORT_SWITCH_ID_6097:
403 return true;
404 }
405 return false;
406}
407
408static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
409{
410 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
411
412 switch (ps->id) {
413 case PORT_SWITCH_ID_6123:
414 case PORT_SWITCH_ID_6161:
415 case PORT_SWITCH_ID_6165:
416 return true;
417 }
418 return false;
419}
420
421static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
422{
423 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
424
425 switch (ps->id) {
426 case PORT_SWITCH_ID_6121:
427 case PORT_SWITCH_ID_6122:
428 case PORT_SWITCH_ID_6152:
429 case PORT_SWITCH_ID_6155:
430 case PORT_SWITCH_ID_6182:
431 case PORT_SWITCH_ID_6185:
432 case PORT_SWITCH_ID_6108:
433 case PORT_SWITCH_ID_6131:
434 return true;
435 }
436 return false;
437}
438
c22995c5 439static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 440{
441 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
442
443 switch (ps->id) {
444 case PORT_SWITCH_ID_6320:
445 case PORT_SWITCH_ID_6321:
446 return true;
447 }
448 return false;
449}
450
54d792f2
AL		 451static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
452{
453 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454
455 switch (ps->id) {
456 case PORT_SWITCH_ID_6171:
457 case PORT_SWITCH_ID_6175:
458 case PORT_SWITCH_ID_6350:
459 case PORT_SWITCH_ID_6351:
460 return true;
461 }
462 return false;
463}
464
f3a8b6b6
AL		 465static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
466{
467 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468
469 switch (ps->id) {
f3a8b6b6
AL		 470 case PORT_SWITCH_ID_6172:
471 case PORT_SWITCH_ID_6176:
54d792f2
AL		 472 case PORT_SWITCH_ID_6240:
473 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 474 return true;
475 }
476 return false;
477}
478
f74df0be
VD		 479static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
480{
481 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
482
483 /* The following devices have 4-bit identifiers for 16 databases */
484 if (ps->id == PORT_SWITCH_ID_6061)
485 return 16;
486
487 /* The following devices have 6-bit identifiers for 64 databases */
488 if (ps->id == PORT_SWITCH_ID_6065)
489 return 64;
490
491 /* The following devices have 8-bit identifiers for 256 databases */
492 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
493 return 256;
494
495 /* The following devices have 12-bit identifiers for 4096 databases */
496 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
497 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
498 return 4096;
499
500 return 0;
501}
502
b426e5f7
VD		 503static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
504{
505 /* Does the device have dedicated FID registers for ATU and VTU ops? */
506 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
507 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
508 return true;
509
510 return false;
511}
512
2e7bd5ef
VD		 513static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
514{
515 /* Does the device have STU and dedicated SID registers for VTU ops? */
516 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
517 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
518 return true;
519
520 return false;
521}
522
dea87024
AL		 523/* We expect the switch to perform auto negotiation if there is a real
524 * phy. However, in the case of a fixed link phy, we force the port
525 * settings from the fixed link settings.
526 */
527void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
528 struct phy_device *phydev)
529{
530 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 531 u32 reg;
532 int ret;
dea87024
AL		 533
534 if (!phy_is_pseudo_fixed_link(phydev))
535 return;
536
537 mutex_lock(&ps->smi_mutex);
538
539 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
540 if (ret < 0)
541 goto out;
542
543 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
544 PORT_PCS_CTRL_FORCE_LINK |
545 PORT_PCS_CTRL_DUPLEX_FULL |
546 PORT_PCS_CTRL_FORCE_DUPLEX |
547 PORT_PCS_CTRL_UNFORCED);
548
549 reg |= PORT_PCS_CTRL_FORCE_LINK;
550 if (phydev->link)
551 reg |= PORT_PCS_CTRL_LINK_UP;
552
553 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
554 goto out;
555
556 switch (phydev->speed) {
557 case SPEED_1000:
558 reg |= PORT_PCS_CTRL_1000;
559 break;
560 case SPEED_100:
561 reg |= PORT_PCS_CTRL_100;
562 break;
563 case SPEED_10:
564 reg |= PORT_PCS_CTRL_10;
565 break;
566 default:
567 pr_info("Unknown speed");
568 goto out;
569 }
570
571 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
572 if (phydev->duplex == DUPLEX_FULL)
573 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
574
e7e72ac0
AL		 575 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
576 (port >= ps->num_ports - 2)) {
577 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
578 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
579 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
580 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
581 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
582 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
583 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
584 }
dea87024
AL		 585 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
586
587out:
588 mutex_unlock(&ps->smi_mutex);
589}
590
31888234 591static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 592{
593 int ret;
594 int i;
595
596 for (i = 0; i < 10; i++) {
31888234 597 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 598 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 599 return 0;
600 }
601
602 return -ETIMEDOUT;
603}
604
31888234 605static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 606{
607 int ret;
608
7c3d0d67 609 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 610 port = (port + 1) << 5;
611
3675c8d7 612 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 613 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
614 GLOBAL_STATS_OP_CAPTURE_PORT |
615 GLOBAL_STATS_OP_HIST_RX_TX | port);
616 if (ret < 0)
617 return ret;
91da11f8 618
3675c8d7 619 /* Wait for the snapshotting to complete. */
31888234 620 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 621 if (ret < 0)
622 return ret;
623
624 return 0;
625}
626
31888234 627static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 628{
629 u32 _val;
630 int ret;
631
632 *val = 0;
633
31888234
AL		 634 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
635 GLOBAL_STATS_OP_READ_CAPTURED |
636 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 637 if (ret < 0)
638 return;
639
31888234 640 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 641 if (ret < 0)
642 return;
643
31888234 644 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 645 if (ret < 0)
646 return;
647
648 _val = ret << 16;
649
31888234 650 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 651 if (ret < 0)
652 return;
653
654 *val = _val | ret;
655}
656
e413e7e1 657static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 658 { "in_good_octets", 8, 0x00, BANK0, },
659 { "in_bad_octets", 4, 0x02, BANK0, },
660 { "in_unicast", 4, 0x04, BANK0, },
661 { "in_broadcasts", 4, 0x06, BANK0, },
662 { "in_multicasts", 4, 0x07, BANK0, },
663 { "in_pause", 4, 0x16, BANK0, },
664 { "in_undersize", 4, 0x18, BANK0, },
665 { "in_fragments", 4, 0x19, BANK0, },
666 { "in_oversize", 4, 0x1a, BANK0, },
667 { "in_jabber", 4, 0x1b, BANK0, },
668 { "in_rx_error", 4, 0x1c, BANK0, },
669 { "in_fcs_error", 4, 0x1d, BANK0, },
670 { "out_octets", 8, 0x0e, BANK0, },
671 { "out_unicast", 4, 0x10, BANK0, },
672 { "out_broadcasts", 4, 0x13, BANK0, },
673 { "out_multicasts", 4, 0x12, BANK0, },
674 { "out_pause", 4, 0x15, BANK0, },
675 { "excessive", 4, 0x11, BANK0, },
676 { "collisions", 4, 0x1e, BANK0, },
677 { "deferred", 4, 0x05, BANK0, },
678 { "single", 4, 0x14, BANK0, },
679 { "multiple", 4, 0x17, BANK0, },
680 { "out_fcs_error", 4, 0x03, BANK0, },
681 { "late", 4, 0x1f, BANK0, },
682 { "hist_64bytes", 4, 0x08, BANK0, },
683 { "hist_65_127bytes", 4, 0x09, BANK0, },
684 { "hist_128_255bytes", 4, 0x0a, BANK0, },
685 { "hist_256_511bytes", 4, 0x0b, BANK0, },
686 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
687 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
688 { "sw_in_discards", 4, 0x10, PORT, },
689 { "sw_in_filtered", 2, 0x12, PORT, },
690 { "sw_out_filtered", 2, 0x13, PORT, },
691 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
695 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
696 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
704 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
705 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
706 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
707 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
708 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
709 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
710 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
711 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
712 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
713 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
714 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
715 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
716 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 717};
718
f5e2ed02
AL		 719static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
720 struct mv88e6xxx_hw_stat *stat)
e413e7e1 721{
f5e2ed02
AL		 722 switch (stat->type) {
723 case BANK0:
e413e7e1 724 return true;
f5e2ed02
AL		 725 case BANK1:
726 return mv88e6xxx_6320_family(ds);
727 case PORT:
728 return mv88e6xxx_6095_family(ds) ||
729 mv88e6xxx_6185_family(ds) ||
730 mv88e6xxx_6097_family(ds) ||
731 mv88e6xxx_6165_family(ds) ||
732 mv88e6xxx_6351_family(ds) ||
733 mv88e6xxx_6352_family(ds);
91da11f8 734 }
f5e2ed02 735 return false;
91da11f8
LB		 736}
737
80c4627b 738static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
f5e2ed02 739 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 740 int port)
741{
80c4627b
AL		 742 u32 low;
743 u32 high = 0;
744 int ret;
745 u64 value;
746
f5e2ed02
AL		 747 switch (s->type) {
748 case PORT:
749 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
80c4627b
AL		 750 if (ret < 0)
751 return UINT64_MAX;
752
753 low = ret;
754 if (s->sizeof_stat == 4) {
755 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
f5e2ed02 756 s->reg + 1);
80c4627b
AL		 757 if (ret < 0)
758 return UINT64_MAX;
759 high = ret;
760 }
f5e2ed02
AL		 761 break;
762 case BANK0:
763 case BANK1:
80c4627b
AL		 764 _mv88e6xxx_stats_read(ds, s->reg, &low);
765 if (s->sizeof_stat == 8)
766 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
767 }
768 value = (((u64)high) << 16) | low;
769 return value;
770}
771
f5e2ed02 772void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 773{
f5e2ed02
AL		 774 struct mv88e6xxx_hw_stat *stat;
775 int i, j;
91da11f8 776
f5e2ed02
AL		 777 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
778 stat = &mv88e6xxx_hw_stats[i];
779 if (mv88e6xxx_has_stat(ds, stat)) {
780 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
781 ETH_GSTRING_LEN);
782 j++;
783 }
91da11f8 784 }
e413e7e1
AL		 785}
786
787int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
788{
f5e2ed02
AL		 789 struct mv88e6xxx_hw_stat *stat;
790 int i, j;
791
792 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
793 stat = &mv88e6xxx_hw_stats[i];
794 if (mv88e6xxx_has_stat(ds, stat))
795 j++;
796 }
797 return j;
e413e7e1
AL		 798}
799
800void
801mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
802 int port, uint64_t *data)
803{
f5e2ed02
AL		 804 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
805 struct mv88e6xxx_hw_stat *stat;
806 int ret;
807 int i, j;
808
809 mutex_lock(&ps->smi_mutex);
810
811 ret = _mv88e6xxx_stats_snapshot(ds, port);
812 if (ret < 0) {
813 mutex_unlock(&ps->smi_mutex);
814 return;
815 }
816 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
817 stat = &mv88e6xxx_hw_stats[i];
818 if (mv88e6xxx_has_stat(ds, stat)) {
819 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
820 j++;
821 }
822 }
823
824 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 825}
826
a1ab91f3
GR		 827int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
828{
829 return 32 * sizeof(u16);
830}
831
832void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
833 struct ethtool_regs *regs, void *_p)
834{
835 u16 *p = _p;
836 int i;
837
838 regs->version = 0;
839
840 memset(p, 0xff, 32 * sizeof(u16));
841
842 for (i = 0; i < 32; i++) {
843 int ret;
844
845 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
846 if (ret >= 0)
847 p[i] = ret;
848 }
849}
850
3898c148
AL		 851static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
852 u16 mask)
f3044683
AL		 853{
854 unsigned long timeout = jiffies + HZ / 10;
855
856 while (time_before(jiffies, timeout)) {
857 int ret;
858
3898c148
AL		 859 ret = _mv88e6xxx_reg_read(ds, reg, offset);
860 if (ret < 0)
861 return ret;
f3044683
AL		 862 if (!(ret & mask))
863 return 0;
864
865 usleep_range(1000, 2000);
866 }
867 return -ETIMEDOUT;
868}
869
3898c148
AL		 870static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
871{
872 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
873 int ret;
874
875 mutex_lock(&ps->smi_mutex);
876 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
877 mutex_unlock(&ps->smi_mutex);
878
879 return ret;
880}
881
882static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 883{
3898c148
AL		 884 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
885 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 886}
887
888int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
889{
cca8b133
AL		 890 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
891 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 892}
893
894int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
895{
cca8b133
AL		 896 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
897 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 898}
899
facd95b2
GR		 900static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
901{
cca8b133
AL		 902 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
903 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 904}
905
fd3a0ee4
AL		 906static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
907 int regnum)
f3044683
AL		 908{
909 int ret;
910
3898c148
AL		 911 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
912 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
913 regnum);
914 if (ret < 0)
915 return ret;
f3044683 916
3898c148 917 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 918 if (ret < 0)
919 return ret;
920
3898c148 921 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 922}
923
fd3a0ee4
AL		 924static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
925 int regnum, u16 val)
f3044683 926{
3898c148
AL		 927 int ret;
928
929 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
930 if (ret < 0)
931 return ret;
f3044683 932
3898c148
AL		 933 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
934 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
935 regnum);
936
937 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 938}
939
11b3b45d
GR		 940int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
941{
2f40c698 942 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 943 int reg;
944
3898c148 945 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 946
947 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 948 if (reg < 0)
2f40c698 949 goto out;
11b3b45d
GR		 950
951 e->eee_enabled = !!(reg & 0x0200);
952 e->tx_lpi_enabled = !!(reg & 0x0100);
953
3898c148 954 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 955 if (reg < 0)
2f40c698 956 goto out;
11b3b45d 957
cca8b133 958 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 959 reg = 0;
11b3b45d 960
2f40c698 961out:
3898c148 962 mutex_unlock(&ps->smi_mutex);
2f40c698 963 return reg;
11b3b45d
GR		 964}
965
966int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
967 struct phy_device *phydev, struct ethtool_eee *e)
968{
2f40c698
AL		 969 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
970 int reg;
11b3b45d
GR		 971 int ret;
972
3898c148 973 mutex_lock(&ps->smi_mutex);
11b3b45d 974
2f40c698
AL		 975 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
976 if (ret < 0)
977 goto out;
978
979 reg = ret & ~0x0300;
980 if (e->eee_enabled)
981 reg |= 0x0200;
982 if (e->tx_lpi_enabled)
983 reg |= 0x0100;
984
985 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
986out:
3898c148 987 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 988
989 return ret;
11b3b45d
GR		 990}
991
b426e5f7 992static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
facd95b2
GR		 993{
994 int ret;
995
b426e5f7
VD		 996 if (mv88e6xxx_has_fid_reg(ds)) {
997 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
998 if (ret < 0)
999 return ret;
11ea809f
VD		 1000 } else if (mv88e6xxx_num_databases(ds) == 256) {
1001 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1002 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1003 if (ret < 0)
1004 return ret;
1005
1006 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1007 (ret & 0xfff) |
1008 ((fid << 8) & 0xf000));
1009 if (ret < 0)
1010 return ret;
1011
1012 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1013 cmd |= fid & 0xf;
b426e5f7
VD		 1014 }
1015
cca8b133 1016 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1017 if (ret < 0)
1018 return ret;
1019
1020 return _mv88e6xxx_atu_wait(ds);
1021}
1022
37705b73
VD		 1023static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
1024 struct mv88e6xxx_atu_entry *entry)
1025{
1026 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1027
1028 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1029 unsigned int mask, shift;
1030
1031 if (entry->trunk) {
1032 data |= GLOBAL_ATU_DATA_TRUNK;
1033 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1034 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1035 } else {
1036 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1037 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1038 }
1039
1040 data |= (entry->portv_trunkid << shift) & mask;
1041 }
1042
1043 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1044}
1045
7fb5e755
VD		 1046static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1047 struct mv88e6xxx_atu_entry *entry,
1048 bool static_too)
facd95b2 1049{
7fb5e755
VD		 1050 int op;
1051 int err;
facd95b2 1052
7fb5e755
VD		 1053 err = _mv88e6xxx_atu_wait(ds);
1054 if (err)
1055 return err;
facd95b2 1056
7fb5e755
VD		 1057 err = _mv88e6xxx_atu_data_write(ds, entry);
1058 if (err)
1059 return err;
1060
1061 if (entry->fid) {
7fb5e755
VD		 1062 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1063 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1064 } else {
1065 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1066 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1067 }
1068
b426e5f7 1069 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
7fb5e755
VD		 1070}
1071
1072static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1073{
1074 struct mv88e6xxx_atu_entry entry = {
1075 .fid = fid,
1076 .state = 0, /* EntryState bits must be 0 */
1077 };
70cc99d1 1078
7fb5e755
VD		 1079 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1080}
1081
9f4d55d2
VD		 1082static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1083 int to_port, bool static_too)
1084{
1085 struct mv88e6xxx_atu_entry entry = {
1086 .trunk = false,
1087 .fid = fid,
1088 };
1089
1090 /* EntryState bits must be 0xF */
1091 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1092
1093 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1094 entry.portv_trunkid = (to_port & 0x0f) << 4;
1095 entry.portv_trunkid |= from_port & 0x0f;
1096
1097 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1098}
1099
1100static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1101 bool static_too)
1102{
1103 /* Destination port 0xF means remove the entries */
1104 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1105}
1106
2d9deae4
VD		 1107static const char * const mv88e6xxx_port_state_names[] = {
1108 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1109 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1110 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1111 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1112};
1113
1114static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
facd95b2 1115{
c3ffe6d2 1116 int reg, ret = 0;
facd95b2
GR		 1117 u8 oldstate;
1118
cca8b133 1119 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1120 if (reg < 0)
1121 return reg;
facd95b2 1122
cca8b133 1123 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1124
facd95b2
GR		 1125 if (oldstate != state) {
1126 /* Flush forwarding database if we're moving a port
1127 * from Learning or Forwarding state to Disabled or
1128 * Blocking or Listening state.
1129 */
2d9deae4
VD		 1130 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1131 oldstate == PORT_CONTROL_STATE_FORWARDING)
1132 && (state == PORT_CONTROL_STATE_DISABLED ||
1133 state == PORT_CONTROL_STATE_BLOCKING)) {
2b8157b1 1134 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2 1135 if (ret)
2d9deae4 1136 return ret;
facd95b2 1137 }
2d9deae4 1138
cca8b133
AL		 1139 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1140 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1141 reg);
2d9deae4
VD		 1142 if (ret)
1143 return ret;
1144
1145 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1146 mv88e6xxx_port_state_names[state],
1147 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1148 }
1149
facd95b2
GR		 1150 return ret;
1151}
1152
b7666efe 1153static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
facd95b2
GR		 1154{
1155 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 1156 struct net_device *bridge = ps->ports[port].bridge_dev;
ede8098d 1157 const u16 mask = (1 << ps->num_ports) - 1;
b7666efe 1158 u16 output_ports = 0;
ede8098d 1159 int reg;
b7666efe
VD		 1160 int i;
1161
1162 /* allow CPU port or DSA link(s) to send frames to every port */
1163 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1164 output_ports = mask;
1165 } else {
1166 for (i = 0; i < ps->num_ports; ++i) {
1167 /* allow sending frames to every group member */
1168 if (bridge && ps->ports[i].bridge_dev == bridge)
1169 output_ports |= BIT(i);
1170
1171 /* allow sending frames to CPU port and DSA link(s) */
1172 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1173 output_ports |= BIT(i);
1174 }
1175 }
1176
1177 /* prevent frames from going back out of the port they came in on */
1178 output_ports &= ~BIT(port);
facd95b2 1179
ede8098d
VD		 1180 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1181 if (reg < 0)
1182 return reg;
facd95b2 1183
ede8098d
VD		 1184 reg &= ~mask;
1185 reg |= output_ports & mask;
facd95b2 1186
ede8098d 1187 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1188}
1189
43c44a9f 1190void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
facd95b2
GR		 1191{
1192 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1193 int stp_state;
1194
1195 switch (state) {
1196 case BR_STATE_DISABLED:
cca8b133 1197 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1198 break;
1199 case BR_STATE_BLOCKING:
1200 case BR_STATE_LISTENING:
cca8b133 1201 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1202 break;
1203 case BR_STATE_LEARNING:
cca8b133 1204 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1205 break;
1206 case BR_STATE_FORWARDING:
1207 default:
cca8b133 1208 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1209 break;
1210 }
1211
43c44a9f 1212 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
facd95b2
GR		 1213 * so we can not update the port state directly but need to schedule it.
1214 */
d715fa64 1215 ps->ports[port].state = stp_state;
2d9deae4 1216 set_bit(port, ps->port_state_update_mask);
facd95b2 1217 schedule_work(&ps->bridge_work);
facd95b2
GR		 1218}
1219
5da96031
VD		 1220static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1221 u16 *old)
76e398a6 1222{
5da96031 1223 u16 pvid;
76e398a6
VD		 1224 int ret;
1225
1226 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1227 if (ret < 0)
1228 return ret;
1229
5da96031
VD		 1230 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1231
1232 if (new) {
1233 ret &= ~PORT_DEFAULT_VLAN_MASK;
1234 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1235
1236 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1237 PORT_DEFAULT_VLAN, ret);
1238 if (ret < 0)
1239 return ret;
1240
1241 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1242 pvid);
1243 }
1244
1245 if (old)
1246 *old = pvid;
76e398a6
VD		 1247
1248 return 0;
1249}
1250
5da96031
VD		 1251static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1252{
1253 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1254}
1255
76e398a6 1256static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
0d3b33e6 1257{
5da96031 1258 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
0d3b33e6
VD		 1259}
1260
6b17e864
VD		 1261static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1262{
1263 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1264 GLOBAL_VTU_OP_BUSY);
1265}
1266
1267static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1268{
1269 int ret;
1270
1271 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1272 if (ret < 0)
1273 return ret;
1274
1275 return _mv88e6xxx_vtu_wait(ds);
1276}
1277
1278static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1279{
1280 int ret;
1281
1282 ret = _mv88e6xxx_vtu_wait(ds);
1283 if (ret < 0)
1284 return ret;
1285
1286 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1287}
1288
b8fee957
VD		 1289static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1290 struct mv88e6xxx_vtu_stu_entry *entry,
1291 unsigned int nibble_offset)
1292{
1293 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1294 u16 regs[3];
1295 int i;
1296 int ret;
1297
1298 for (i = 0; i < 3; ++i) {
1299 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1300 GLOBAL_VTU_DATA_0_3 + i);
1301 if (ret < 0)
1302 return ret;
1303
1304 regs[i] = ret;
1305 }
1306
1307 for (i = 0; i < ps->num_ports; ++i) {
1308 unsigned int shift = (i % 4) * 4 + nibble_offset;
1309 u16 reg = regs[i / 4];
1310
1311 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1312 }
1313
1314 return 0;
1315}
1316
7dad08d7
VD		 1317static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1318 struct mv88e6xxx_vtu_stu_entry *entry,
1319 unsigned int nibble_offset)
1320{
1321 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1322 u16 regs[3] = { 0 };
1323 int i;
1324 int ret;
1325
1326 for (i = 0; i < ps->num_ports; ++i) {
1327 unsigned int shift = (i % 4) * 4 + nibble_offset;
1328 u8 data = entry->data[i];
1329
1330 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1331 }
1332
1333 for (i = 0; i < 3; ++i) {
1334 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1335 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1336 if (ret < 0)
1337 return ret;
1338 }
1339
1340 return 0;
1341}
1342
36d04ba1
VD		 1343static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1344{
1345 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1346 vid & GLOBAL_VTU_VID_MASK);
1347}
1348
1349static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1350 struct mv88e6xxx_vtu_stu_entry *entry)
1351{
1352 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1353 int ret;
1354
1355 ret = _mv88e6xxx_vtu_wait(ds);
1356 if (ret < 0)
1357 return ret;
1358
b8fee957
VD		 1359 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1360 if (ret < 0)
1361 return ret;
1362
1363 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1364 if (ret < 0)
1365 return ret;
1366
1367 next.vid = ret & GLOBAL_VTU_VID_MASK;
1368 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1369
1370 if (next.valid) {
1371 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1372 if (ret < 0)
1373 return ret;
1374
b426e5f7 1375 if (mv88e6xxx_has_fid_reg(ds)) {
b8fee957
VD		 1376 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1377 GLOBAL_VTU_FID);
1378 if (ret < 0)
1379 return ret;
1380
1381 next.fid = ret & GLOBAL_VTU_FID_MASK;
11ea809f
VD		 1382 } else if (mv88e6xxx_num_databases(ds) == 256) {
1383 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1384 * VTU DBNum[3:0] are located in VTU Operation 3:0
1385 */
1386 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1387 GLOBAL_VTU_OP);
1388 if (ret < 0)
1389 return ret;
1390
1391 next.fid = (ret & 0xf00) >> 4;
1392 next.fid |= ret & 0xf;
2e7bd5ef 1393 }
b8fee957 1394
2e7bd5ef 1395 if (mv88e6xxx_has_stu(ds)) {
b8fee957
VD		 1396 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1397 GLOBAL_VTU_SID);
1398 if (ret < 0)
1399 return ret;
1400
1401 next.sid = ret & GLOBAL_VTU_SID_MASK;
1402 }
1403 }
1404
1405 *entry = next;
1406 return 0;
1407}
1408
ceff5eff
VD		 1409int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1410 struct switchdev_obj_port_vlan *vlan,
1411 int (*cb)(struct switchdev_obj *obj))
1412{
1413 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1414 struct mv88e6xxx_vtu_stu_entry next;
1415 u16 pvid;
1416 int err;
1417
1418 mutex_lock(&ps->smi_mutex);
1419
1420 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1421 if (err)
1422 goto unlock;
1423
1424 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1425 if (err)
1426 goto unlock;
1427
1428 do {
1429 err = _mv88e6xxx_vtu_getnext(ds, &next);
1430 if (err)
1431 break;
1432
1433 if (!next.valid)
1434 break;
1435
1436 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1437 continue;
1438
1439 /* reinit and dump this VLAN obj */
1440 vlan->vid_begin = vlan->vid_end = next.vid;
1441 vlan->flags = 0;
1442
1443 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1444 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1445
1446 if (next.vid == pvid)
1447 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1448
1449 err = cb(&vlan->obj);
1450 if (err)
1451 break;
1452 } while (next.vid < GLOBAL_VTU_VID_MASK);
1453
1454unlock:
1455 mutex_unlock(&ps->smi_mutex);
1456
1457 return err;
1458}
1459
7dad08d7
VD		 1460static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1461 struct mv88e6xxx_vtu_stu_entry *entry)
1462{
11ea809f 1463 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1464 u16 reg = 0;
1465 int ret;
1466
1467 ret = _mv88e6xxx_vtu_wait(ds);
1468 if (ret < 0)
1469 return ret;
1470
1471 if (!entry->valid)
1472 goto loadpurge;
1473
1474 /* Write port member tags */
1475 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1476 if (ret < 0)
1477 return ret;
1478
2e7bd5ef 1479 if (mv88e6xxx_has_stu(ds)) {
7dad08d7
VD		 1480 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1481 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1482 if (ret < 0)
1483 return ret;
b426e5f7 1484 }
7dad08d7 1485
b426e5f7 1486 if (mv88e6xxx_has_fid_reg(ds)) {
7dad08d7
VD		 1487 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1488 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1489 if (ret < 0)
1490 return ret;
11ea809f
VD		 1491 } else if (mv88e6xxx_num_databases(ds) == 256) {
1492 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1493 * VTU DBNum[3:0] are located in VTU Operation 3:0
1494 */
1495 op |= (entry->fid & 0xf0) << 8;
1496 op |= entry->fid & 0xf;
7dad08d7
VD		 1497 }
1498
1499 reg = GLOBAL_VTU_VID_VALID;
1500loadpurge:
1501 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1502 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1503 if (ret < 0)
1504 return ret;
1505
11ea809f 1506 return _mv88e6xxx_vtu_cmd(ds, op);
7dad08d7
VD		 1507}
1508
0d3b33e6
VD		 1509static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1510 struct mv88e6xxx_vtu_stu_entry *entry)
1511{
1512 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1513 int ret;
1514
1515 ret = _mv88e6xxx_vtu_wait(ds);
1516 if (ret < 0)
1517 return ret;
1518
1519 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1520 sid & GLOBAL_VTU_SID_MASK);
1521 if (ret < 0)
1522 return ret;
1523
1524 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1525 if (ret < 0)
1526 return ret;
1527
1528 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1529 if (ret < 0)
1530 return ret;
1531
1532 next.sid = ret & GLOBAL_VTU_SID_MASK;
1533
1534 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1535 if (ret < 0)
1536 return ret;
1537
1538 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1539
1540 if (next.valid) {
1541 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1542 if (ret < 0)
1543 return ret;
1544 }
1545
1546 *entry = next;
1547 return 0;
1548}
1549
1550static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1551 struct mv88e6xxx_vtu_stu_entry *entry)
1552{
1553 u16 reg = 0;
1554 int ret;
1555
1556 ret = _mv88e6xxx_vtu_wait(ds);
1557 if (ret < 0)
1558 return ret;
1559
1560 if (!entry->valid)
1561 goto loadpurge;
1562
1563 /* Write port states */
1564 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1565 if (ret < 0)
1566 return ret;
1567
1568 reg = GLOBAL_VTU_VID_VALID;
1569loadpurge:
1570 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1571 if (ret < 0)
1572 return ret;
1573
1574 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1576 if (ret < 0)
1577 return ret;
1578
1579 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1580}
1581
2db9ce1f
VD		 1582static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1583 u16 *old)
1584{
f74df0be 1585 u16 upper_mask;
2db9ce1f
VD		 1586 u16 fid;
1587 int ret;
1588
f74df0be
VD		 1589 if (mv88e6xxx_num_databases(ds) == 4096)
1590 upper_mask = 0xff;
11ea809f
VD		 1591 else if (mv88e6xxx_num_databases(ds) == 256)
1592 upper_mask = 0xf;
f74df0be
VD		 1593 else
1594 return -EOPNOTSUPP;
1595
2db9ce1f
VD		 1596 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1597 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1598 if (ret < 0)
1599 return ret;
1600
1601 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1602
1603 if (new) {
1604 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1605 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1606
1607 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1608 ret);
1609 if (ret < 0)
1610 return ret;
1611 }
1612
1613 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1614 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1615 if (ret < 0)
1616 return ret;
1617
f74df0be 1618 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1619
1620 if (new) {
f74df0be
VD		 1621 ret &= ~upper_mask;
1622 ret |= (*new >> 4) & upper_mask;
2db9ce1f
VD		 1623
1624 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1625 ret);
1626 if (ret < 0)
1627 return ret;
1628
1629 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1630 }
1631
1632 if (old)
1633 *old = fid;
1634
1635 return 0;
1636}
1637
1638static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1639{
1640 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1641}
1642
1643static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1644{
1645 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1646}
1647
3285f9e8
VD		 1648static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1649{
2db9ce1f 1650 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3285f9e8
VD		 1651 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1652 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1653 int i, err;
3285f9e8
VD		 1654
1655 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1656
2db9ce1f
VD		 1657 /* Set every FID bit used by the (un)bridged ports */
1658 for (i = 0; i < ps->num_ports; ++i) {
1659 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1660 if (err)
1661 return err;
1662
1663 set_bit(*fid, fid_bitmap);
1664 }
1665
3285f9e8
VD		 1666 /* Set every FID bit used by the VLAN entries */
1667 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1668 if (err)
1669 return err;
1670
1671 do {
1672 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1673 if (err)
1674 return err;
1675
1676 if (!vlan.valid)
1677 break;
1678
1679 set_bit(vlan.fid, fid_bitmap);
1680 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1681
1682 /* The reset value 0x000 is used to indicate that multiple address
1683 * databases are not needed. Return the next positive available.
1684 */
1685 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
f74df0be 1686 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
3285f9e8
VD		 1687 return -ENOSPC;
1688
1689 /* Clear the database */
1690 return _mv88e6xxx_atu_flush(ds, *fid, true);
1691}
1692
2fb5ef09
VD		 1693static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1694 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6
VD		 1695{
1696 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1697 struct mv88e6xxx_vtu_stu_entry vlan = {
1698 .valid = true,
1699 .vid = vid,
1700 };
3285f9e8
VD		 1701 int i, err;
1702
1703 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1704 if (err)
1705 return err;
0d3b33e6 1706
3d131f07 1707 /* exclude all ports except the CPU and DSA ports */
0d3b33e6 1708 for (i = 0; i < ps->num_ports; ++i)
3d131f07
VD		 1709 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1710 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1711 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6
VD		 1712
1713 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1714 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1715 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1716
1717 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1718 * implemented, only one STU entry is needed to cover all VTU
1719 * entries. Thus, validate the SID 0.
1720 */
1721 vlan.sid = 0;
1722 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1723 if (err)
1724 return err;
1725
1726 if (vstp.sid != vlan.sid || !vstp.valid) {
1727 memset(&vstp, 0, sizeof(vstp));
1728 vstp.valid = true;
1729 vstp.sid = vlan.sid;
1730
1731 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1732 if (err)
1733 return err;
1734 }
0d3b33e6
VD		 1735 }
1736
1737 *entry = vlan;
1738 return 0;
1739}
1740
2fb5ef09
VD		 1741static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1742 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1743{
1744 int err;
1745
1746 if (!vid)
1747 return -EINVAL;
1748
1749 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1750 if (err)
1751 return err;
1752
1753 err = _mv88e6xxx_vtu_getnext(ds, entry);
1754 if (err)
1755 return err;
1756
1757 if (entry->vid != vid || !entry->valid) {
1758 if (!creat)
1759 return -EOPNOTSUPP;
1760 /* -ENOENT would've been more appropriate, but switchdev expects
1761 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1762 */
1763
1764 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1765 }
1766
1767 return err;
1768}
1769
da9c359e
VD		 1770static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1771 u16 vid_begin, u16 vid_end)
1772{
1773 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1774 struct mv88e6xxx_vtu_stu_entry vlan;
1775 int i, err;
1776
1777 if (!vid_begin)
1778 return -EOPNOTSUPP;
1779
1780 mutex_lock(&ps->smi_mutex);
1781
1782 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1783 if (err)
1784 goto unlock;
1785
1786 do {
1787 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1788 if (err)
1789 goto unlock;
1790
1791 if (!vlan.valid)
1792 break;
1793
1794 if (vlan.vid > vid_end)
1795 break;
1796
1797 for (i = 0; i < ps->num_ports; ++i) {
1798 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1799 continue;
1800
1801 if (vlan.data[i] ==
1802 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1803 continue;
1804
1805 if (ps->ports[i].bridge_dev ==
1806 ps->ports[port].bridge_dev)
1807 break; /* same bridge, check next VLAN */
1808
1809 netdev_warn(ds->ports[port],
1810 "hardware VLAN %d already used by %s\n",
1811 vlan.vid,
1812 netdev_name(ps->ports[i].bridge_dev));
1813 err = -EOPNOTSUPP;
1814 goto unlock;
1815 }
1816 } while (vlan.vid < vid_end);
1817
1818unlock:
1819 mutex_unlock(&ps->smi_mutex);
1820
1821 return err;
1822}
1823
214cdb99
VD		 1824static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1825 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1826 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1827 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1828 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1829};
1830
1831int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1832 bool vlan_filtering)
1833{
1834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1835 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1836 PORT_CONTROL_2_8021Q_DISABLED;
1837 int ret;
1838
1839 mutex_lock(&ps->smi_mutex);
1840
1841 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1842 if (ret < 0)
1843 goto unlock;
1844
1845 old = ret & PORT_CONTROL_2_8021Q_MASK;
1846
5220ef1e
VD		 1847 if (new != old) {
1848 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1849 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 1850
5220ef1e
VD		 1851 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1852 ret);
1853 if (ret < 0)
1854 goto unlock;
1855
1856 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1857 mv88e6xxx_port_8021q_mode_names[new],
1858 mv88e6xxx_port_8021q_mode_names[old]);
1859 }
214cdb99 1860
5220ef1e 1861 ret = 0;
214cdb99
VD		 1862unlock:
1863 mutex_unlock(&ps->smi_mutex);
1864
1865 return ret;
1866}
1867
76e398a6
VD		 1868int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1869 const struct switchdev_obj_port_vlan *vlan,
1870 struct switchdev_trans *trans)
1871{
da9c359e
VD		 1872 int err;
1873
da9c359e
VD		 1874 /* If the requested port doesn't belong to the same bridge as the VLAN
1875 * members, do not support it (yet) and fallback to software VLAN.
1876 */
1877 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1878 vlan->vid_end);
1879 if (err)
1880 return err;
1881
76e398a6
VD		 1882 /* We don't need any dynamic resource from the kernel (yet),
1883 * so skip the prepare phase.
1884 */
1885 return 0;
1886}
1887
1888static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1889 bool untagged)
0d3b33e6 1890{
0d3b33e6
VD		 1891 struct mv88e6xxx_vtu_stu_entry vlan;
1892 int err;
1893
2fb5ef09 1894 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
0d3b33e6 1895 if (err)
76e398a6 1896 return err;
0d3b33e6 1897
0d3b33e6
VD		 1898 vlan.data[port] = untagged ?
1899 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1900 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1901
76e398a6
VD		 1902 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1903}
1904
4d5770b3
VD		 1905void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1906 const struct switchdev_obj_port_vlan *vlan,
1907 struct switchdev_trans *trans)
76e398a6
VD		 1908{
1909 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1910 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1911 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1912 u16 vid;
76e398a6
VD		 1913
1914 mutex_lock(&ps->smi_mutex);
1915
4d5770b3
VD		 1916 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1917 if (_mv88e6xxx_port_vlan_add(ds, port, vid, untagged))
1918 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
1919 vid, untagged ? 'u' : 't');
76e398a6 1920
4d5770b3
VD		 1921 if (pvid && _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end))
1922 netdev_err(ds->ports[port], "failed to set PVID %d\n",
1923 vlan->vid_end);
0d3b33e6 1924
4d5770b3 1925 mutex_unlock(&ps->smi_mutex);
0d3b33e6
VD		 1926}
1927
76e398a6 1928static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
7dad08d7
VD		 1929{
1930 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1931 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1932 int i, err;
1933
2fb5ef09 1934 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
7dad08d7 1935 if (err)
76e398a6 1936 return err;
7dad08d7 1937
2fb5ef09
VD		 1938 /* Tell switchdev if this VLAN is handled in software */
1939 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1940 return -EOPNOTSUPP;
7dad08d7
VD		 1941
1942 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1943
1944 /* keep the VLAN unless all ports are excluded */
f02bdffc 1945 vlan.valid = false;
7dad08d7 1946 for (i = 0; i < ps->num_ports; ++i) {
3d131f07 1947 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1948 continue;
1949
1950 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1951 vlan.valid = true;
7dad08d7
VD		 1952 break;
1953 }
1954 }
1955
7dad08d7 1956 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
76e398a6
VD		 1957 if (err)
1958 return err;
1959
1960 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1961}
1962
1963int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1964 const struct switchdev_obj_port_vlan *vlan)
1965{
1966 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1967 u16 pvid, vid;
1968 int err = 0;
1969
1970 mutex_lock(&ps->smi_mutex);
1971
1972 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
7dad08d7
VD		 1973 if (err)
1974 goto unlock;
1975
76e398a6
VD		 1976 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1977 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1978 if (err)
1979 goto unlock;
1980
1981 if (vid == pvid) {
46fbe5e5 1982 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
76e398a6
VD		 1983 if (err)
1984 goto unlock;
1985 }
1986 }
1987
7dad08d7
VD		 1988unlock:
1989 mutex_unlock(&ps->smi_mutex);
1990
1991 return err;
1992}
1993
c5723ac5
VD		 1994static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1995 const unsigned char *addr)
defb05b9
GR		 1996{
1997 int i, ret;
1998
1999 for (i = 0; i < 3; i++) {
cca8b133
AL		 2000 ret = _mv88e6xxx_reg_write(
2001 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2002 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2003 if (ret < 0)
2004 return ret;
2005 }
2006
2007 return 0;
2008}
2009
c5723ac5 2010static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 2011{
2012 int i, ret;
2013
2014 for (i = 0; i < 3; i++) {
cca8b133
AL		 2015 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
2016 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2017 if (ret < 0)
2018 return ret;
2019 addr[i * 2] = ret >> 8;
2020 addr[i * 2 + 1] = ret & 0xff;
2021 }
2022
2023 return 0;
2024}
2025
fd231c82
VD		 2026static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
2027 struct mv88e6xxx_atu_entry *entry)
defb05b9 2028{
6630e236
VD		 2029 int ret;
2030
defb05b9
GR		 2031 ret = _mv88e6xxx_atu_wait(ds);
2032 if (ret < 0)
2033 return ret;
2034
fd231c82 2035 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 2036 if (ret < 0)
2037 return ret;
2038
37705b73 2039 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 2040 if (ret < 0)
87820510
VD		 2041 return ret;
2042
b426e5f7 2043 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2044}
87820510 2045
fd231c82
VD		 2046static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2047 const unsigned char *addr, u16 vid,
2048 u8 state)
2049{
2050 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2051 struct mv88e6xxx_vtu_stu_entry vlan;
2052 int err;
2053
2db9ce1f
VD		 2054 /* Null VLAN ID corresponds to the port private database */
2055 if (vid == 0)
2056 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2057 else
2058 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
3285f9e8
VD		 2059 if (err)
2060 return err;
fd231c82 2061
3285f9e8 2062 entry.fid = vlan.fid;
fd231c82
VD		 2063 entry.state = state;
2064 ether_addr_copy(entry.mac, addr);
2065 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2066 entry.trunk = false;
2067 entry.portv_trunkid = BIT(port);
2068 }
2069
2070 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 2071}
2072
146a3206
VD		 2073int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2074 const struct switchdev_obj_port_fdb *fdb,
2075 struct switchdev_trans *trans)
2076{
2077 /* We don't need any dynamic resource from the kernel (yet),
2078 * so skip the prepare phase.
2079 */
2080 return 0;
2081}
2082
8497aa61
VD		 2083void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2084 const struct switchdev_obj_port_fdb *fdb,
2085 struct switchdev_trans *trans)
87820510 2086{
1f36faf2 2087 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2088 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2089 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2090 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2091
2092 mutex_lock(&ps->smi_mutex);
8497aa61
VD		 2093 if (_mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state))
2094 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2095 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2096}
2097
cdf09697 2098int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 2099 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2100{
2101 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2102 int ret;
2103
2104 mutex_lock(&ps->smi_mutex);
8057b3e7 2105 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 2106 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2107 mutex_unlock(&ps->smi_mutex);
2108
2109 return ret;
2110}
2111
1d194046 2112static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 2113 struct mv88e6xxx_atu_entry *entry)
6630e236 2114{
1d194046
VD		 2115 struct mv88e6xxx_atu_entry next = { 0 };
2116 int ret;
2117
2118 next.fid = fid;
defb05b9 2119
cdf09697
DM		 2120 ret = _mv88e6xxx_atu_wait(ds);
2121 if (ret < 0)
2122 return ret;
6630e236 2123
b426e5f7 2124 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2125 if (ret < 0)
2126 return ret;
6630e236 2127
1d194046
VD		 2128 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2129 if (ret < 0)
2130 return ret;
6630e236 2131
1d194046 2132 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2133 if (ret < 0)
2134 return ret;
6630e236 2135
1d194046
VD		 2136 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2137 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2138 unsigned int mask, shift;
2139
2140 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2141 next.trunk = true;
2142 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2143 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2144 } else {
2145 next.trunk = false;
2146 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2147 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2148 }
2149
2150 next.portv_trunkid = (ret & mask) >> shift;
2151 }
cdf09697 2152
1d194046 2153 *entry = next;
cdf09697
DM		 2154 return 0;
2155}
2156
74b6ba0d
VD		 2157static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2158 int port,
2159 struct switchdev_obj_port_fdb *fdb,
2160 int (*cb)(struct switchdev_obj *obj))
2161{
2162 struct mv88e6xxx_atu_entry addr = {
2163 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2164 };
2165 int err;
2166
2167 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2168 if (err)
2169 return err;
2170
2171 do {
2172 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2173 if (err)
2174 break;
2175
2176 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2177 break;
2178
2179 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2180 bool is_static = addr.state ==
2181 (is_multicast_ether_addr(addr.mac) ?
2182 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2183 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2184
2185 fdb->vid = vid;
2186 ether_addr_copy(fdb->addr, addr.mac);
2187 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2188
2189 err = cb(&fdb->obj);
2190 if (err)
2191 break;
2192 }
2193 } while (!is_broadcast_ether_addr(addr.mac));
2194
2195 return err;
2196}
2197
f33475bd
VD		 2198int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2199 struct switchdev_obj_port_fdb *fdb,
2200 int (*cb)(struct switchdev_obj *obj))
2201{
2202 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2203 struct mv88e6xxx_vtu_stu_entry vlan = {
2204 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2205 };
2db9ce1f 2206 u16 fid;
f33475bd
VD		 2207 int err;
2208
2209 mutex_lock(&ps->smi_mutex);
2210
2db9ce1f
VD		 2211 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2212 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2213 if (err)
2214 goto unlock;
2215
2216 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2217 if (err)
2218 goto unlock;
2219
74b6ba0d 2220 /* Dump VLANs' Filtering Information Databases */
f33475bd
VD		 2221 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2222 if (err)
2223 goto unlock;
2224
2225 do {
f33475bd
VD		 2226 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2227 if (err)
74b6ba0d 2228 break;
f33475bd
VD		 2229
2230 if (!vlan.valid)
2231 break;
2232
74b6ba0d
VD		 2233 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2234 fdb, cb);
f33475bd 2235 if (err)
74b6ba0d 2236 break;
f33475bd
VD		 2237 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2238
2239unlock:
2240 mutex_unlock(&ps->smi_mutex);
2241
2242 return err;
2243}
2244
a6692754
VD		 2245int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2246 struct net_device *bridge)
e79a8bcb 2247{
a6692754 2248 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466dfa07
VD		 2249 u16 fid;
2250 int i, err;
2251
2252 mutex_lock(&ps->smi_mutex);
2253
2254 /* Get or create the bridge FID and assign it to the port */
2255 for (i = 0; i < ps->num_ports; ++i)
2256 if (ps->ports[i].bridge_dev == bridge)
2257 break;
2258
2259 if (i < ps->num_ports)
2260 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2261 else
2262 err = _mv88e6xxx_fid_new(ds, &fid);
2263 if (err)
2264 goto unlock;
2265
2266 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2267 if (err)
2268 goto unlock;
a6692754 2269
b7666efe 2270 /* Assign the bridge and remap each port's VLANTable */
a6692754 2271 ps->ports[port].bridge_dev = bridge;
b7666efe
VD		 2272
2273 for (i = 0; i < ps->num_ports; ++i) {
2274 if (ps->ports[i].bridge_dev == bridge) {
2275 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2276 if (err)
2277 break;
2278 }
2279 }
2280
466dfa07
VD		 2281unlock:
2282 mutex_unlock(&ps->smi_mutex);
a6692754 2283
466dfa07 2284 return err;
e79a8bcb
VD		 2285}
2286
16bfa702 2287void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2288{
a6692754 2289 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2290 struct net_device *bridge = ps->ports[port].bridge_dev;
466dfa07 2291 u16 fid;
16bfa702 2292 int i;
466dfa07
VD		 2293
2294 mutex_lock(&ps->smi_mutex);
2295
2296 /* Give the port a fresh Filtering Information Database */
16bfa702
VD		 2297 if (_mv88e6xxx_fid_new(ds, &fid) ||
2298 _mv88e6xxx_port_fid_set(ds, port, fid))
2299 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
a6692754 2300
b7666efe 2301 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2302 ps->ports[port].bridge_dev = NULL;
b7666efe 2303
16bfa702
VD		 2304 for (i = 0; i < ps->num_ports; ++i)
2305 if (i == port || ps->ports[i].bridge_dev == bridge)
2306 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2307 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2308
466dfa07 2309 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2310}
2311
facd95b2
GR		 2312static void mv88e6xxx_bridge_work(struct work_struct *work)
2313{
2314 struct mv88e6xxx_priv_state *ps;
2315 struct dsa_switch *ds;
2316 int port;
2317
2318 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
7543a6d5 2319 ds = ps->ds;
facd95b2 2320
2d9deae4
VD		 2321 mutex_lock(&ps->smi_mutex);
2322
2323 for (port = 0; port < ps->num_ports; ++port)
2324 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2325 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2326 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2327 mv88e6xxx_port_state_names[ps->ports[port].state]);
2328
2329 mutex_unlock(&ps->smi_mutex);
facd95b2
GR		 2330}
2331
75baacf0
PU		 2332static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2333 int reg, int val)
2334{
2335 int ret;
2336
2337 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2338 if (ret < 0)
2339 goto restore_page_0;
2340
2341 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2342restore_page_0:
2343 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2344
2345 return ret;
2346}
2347
2348static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2349 int reg)
2350{
2351 int ret;
2352
2353 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2354 if (ret < 0)
2355 goto restore_page_0;
2356
2357 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2358restore_page_0:
2359 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2360
2361 return ret;
2362}
2363
13a7ebb3
PU		 2364static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2365{
2366 int ret;
2367
2368 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2369 MII_BMCR);
2370 if (ret < 0)
2371 return ret;
2372
2373 if (ret & BMCR_PDOWN) {
2374 ret &= ~BMCR_PDOWN;
2375 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2376 PAGE_FIBER_SERDES, MII_BMCR,
2377 ret);
2378 }
2379
2380 return ret;
2381}
2382
dbde9e66 2383static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2384{
2385 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2386 int ret;
54d792f2 2387 u16 reg;
d827e88a
GR		 2388
2389 mutex_lock(&ps->smi_mutex);
2390
54d792f2
AL		 2391 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2392 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2393 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 2394 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2395 /* MAC Forcing register: don't force link, speed,
2396 * duplex or flow control state to any particular
2397 * values on physical ports, but force the CPU port
2398 * and all DSA ports to their maximum bandwidth and
2399 * full duplex.
2400 */
2401 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2402 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2403 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2404 reg |= PORT_PCS_CTRL_FORCE_LINK |
2405 PORT_PCS_CTRL_LINK_UP |
2406 PORT_PCS_CTRL_DUPLEX_FULL |
2407 PORT_PCS_CTRL_FORCE_DUPLEX;
2408 if (mv88e6xxx_6065_family(ds))
2409 reg |= PORT_PCS_CTRL_100;
2410 else
2411 reg |= PORT_PCS_CTRL_1000;
2412 } else {
2413 reg |= PORT_PCS_CTRL_UNFORCED;
2414 }
2415
2416 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2417 PORT_PCS_CTRL, reg);
2418 if (ret)
2419 goto abort;
2420 }
2421
2422 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2423 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2424 * tunneling, determine priority by looking at 802.1p and IP
2425 * priority fields (IP prio has precedence), and set STP state
2426 * to Forwarding.
2427 *
2428 * If this is the CPU link, use DSA or EDSA tagging depending
2429 * on which tagging mode was configured.
2430 *
2431 * If this is a link to another switch, use DSA tagging mode.
2432 *
2433 * If this is the upstream port for this switch, enable
2434 * forwarding of unknown unicasts and multicasts.
2435 */
2436 reg = 0;
2437 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2438 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2439 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2440 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2441 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2442 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2443 PORT_CONTROL_STATE_FORWARDING;
2444 if (dsa_is_cpu_port(ds, port)) {
2445 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2446 reg |= PORT_CONTROL_DSA_TAG;
2447 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2448 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2449 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2450 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2451 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2452 else
2453 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2454 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2455 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2456 }
2457
2458 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2459 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2460 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2461 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2462 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2463 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2464 }
2465 }
6083ce71
AL		 2466 if (dsa_is_dsa_port(ds, port)) {
2467 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2468 reg |= PORT_CONTROL_DSA_TAG;
2469 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2470 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2471 mv88e6xxx_6320_family(ds)) {
54d792f2 2472 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2473 }
2474
54d792f2
AL		 2475 if (port == dsa_upstream_port(ds))
2476 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2477 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2478 }
2479 if (reg) {
2480 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2481 PORT_CONTROL, reg);
2482 if (ret)
2483 goto abort;
2484 }
2485
13a7ebb3
PU		 2486 /* If this port is connected to a SerDes, make sure the SerDes is not
2487 * powered down.
2488 */
2489 if (mv88e6xxx_6352_family(ds)) {
2490 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2491 if (ret < 0)
2492 goto abort;
2493 ret &= PORT_STATUS_CMODE_MASK;
2494 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2495 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2496 (ret == PORT_STATUS_CMODE_SGMII)) {
2497 ret = mv88e6xxx_power_on_serdes(ds);
2498 if (ret < 0)
2499 goto abort;
2500 }
2501 }
2502
8efdda4a 2503 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2504 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2505 * untagged frames on this port, do a destination address lookup on all
2506 * received packets as usual, disable ARP mirroring and don't send a
2507 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2508 */
2509 reg = 0;
2510 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2511 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
f93dd042
VD		 2512 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds) ||
2513 mv88e6xxx_6185_family(ds))
54d792f2
AL		 2514 reg = PORT_CONTROL_2_MAP_DA;
2515
2516 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2517 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2518 reg |= PORT_CONTROL_2_JUMBO_10240;
2519
2520 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2521 /* Set the upstream port this port should use */
2522 reg |= dsa_upstream_port(ds);
2523 /* enable forwarding of unknown multicast addresses to
2524 * the upstream port
2525 */
2526 if (port == dsa_upstream_port(ds))
2527 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2528 }
2529
46fbe5e5 2530 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2531
54d792f2
AL		 2532 if (reg) {
2533 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2534 PORT_CONTROL_2, reg);
2535 if (ret)
2536 goto abort;
2537 }
2538
2539 /* Port Association Vector: when learning source addresses
2540 * of packets, add the address to the address database using
2541 * a port bitmap that has only the bit for this port set and
2542 * the other bits clear.
2543 */
4c7ea3c0
AL		 2544 reg = 1 << port;
2545 /* Disable learning for DSA and CPU ports */
2546 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2547 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2548
2549 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2550 if (ret)
2551 goto abort;
2552
2553 /* Egress rate control 2: disable egress rate control. */
2554 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2555 0x0000);
2556 if (ret)
2557 goto abort;
2558
2559 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2560 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2561 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2562 /* Do not limit the period of time that this port can
2563 * be paused for by the remote end or the period of
2564 * time that this port can pause the remote end.
2565 */
2566 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2567 PORT_PAUSE_CTRL, 0x0000);
2568 if (ret)
2569 goto abort;
2570
2571 /* Port ATU control: disable limiting the number of
2572 * address database entries that this port is allowed
2573 * to use.
2574 */
2575 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2576 PORT_ATU_CONTROL, 0x0000);
2577 /* Priority Override: disable DA, SA and VTU priority
2578 * override.
2579 */
2580 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2581 PORT_PRI_OVERRIDE, 0x0000);
2582 if (ret)
2583 goto abort;
2584
2585 /* Port Ethertype: use the Ethertype DSA Ethertype
2586 * value.
2587 */
2588 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2589 PORT_ETH_TYPE, ETH_P_EDSA);
2590 if (ret)
2591 goto abort;
2592 /* Tag Remap: use an identity 802.1p prio -> switch
2593 * prio mapping.
2594 */
2595 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2596 PORT_TAG_REGMAP_0123, 0x3210);
2597 if (ret)
2598 goto abort;
2599
2600 /* Tag Remap 2: use an identity 802.1p prio -> switch
2601 * prio mapping.
2602 */
2603 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2604 PORT_TAG_REGMAP_4567, 0x7654);
2605 if (ret)
2606 goto abort;
2607 }
2608
2609 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2610 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2611 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2612 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2613 /* Rate Control: disable ingress rate limiting. */
2614 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2615 PORT_RATE_CONTROL, 0x0001);
2616 if (ret)
2617 goto abort;
2618 }
2619
366f0a0f
GR		 2620 /* Port Control 1: disable trunking, disable sending
2621 * learning messages to this port.
d827e88a 2622 */
614f03fc 2623 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2624 if (ret)
2625 goto abort;
2626
2db9ce1f 2627 /* Port based VLAN map: give each port its own address
b7666efe
VD		 2628 * database, and allow bidirectional communication between the
2629 * CPU and DSA port(s), and the other ports.
d827e88a 2630 */
2db9ce1f
VD		 2631 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2632 if (ret)
2633 goto abort;
2634
b7666efe 2635 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
d827e88a
GR		 2636 if (ret)
2637 goto abort;
2638
2639 /* Default VLAN ID and priority: don't set a default VLAN
2640 * ID, and set the default packet priority to zero.
2641 */
47cf1e65
VD		 2642 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2643 0x0000);
d827e88a
GR		 2644abort:
2645 mutex_unlock(&ps->smi_mutex);
2646 return ret;
2647}
2648
dbde9e66
AL		 2649int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2650{
2651 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2652 int ret;
2653 int i;
2654
2655 for (i = 0; i < ps->num_ports; i++) {
2656 ret = mv88e6xxx_setup_port(ds, i);
2657 if (ret < 0)
2658 return ret;
2659 }
2660 return 0;
2661}
2662
acdaffcc
GR		 2663int mv88e6xxx_setup_common(struct dsa_switch *ds)
2664{
2665 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2666
7543a6d5 2667 ps->ds = ds;
acdaffcc 2668 mutex_init(&ps->smi_mutex);
acdaffcc 2669
cca8b133 2670 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2671
facd95b2
GR		 2672 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2673
acdaffcc
GR		 2674 return 0;
2675}
2676
54d792f2
AL		 2677int mv88e6xxx_setup_global(struct dsa_switch *ds)
2678{
2679 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2680 int ret;
54d792f2
AL		 2681 int i;
2682
2683 /* Set the default address aging time to 5 minutes, and
2684 * enable address learn messages to be sent to all message
2685 * ports.
2686 */
2687 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2688 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2689
2690 /* Configure the IP ToS mapping registers. */
2691 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2692 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2693 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2694 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2695 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2696 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2697 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2698 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2699
2700 /* Configure the IEEE 802.1p priority mapping register. */
2701 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2702
2703 /* Send all frames with destination addresses matching
2704 * 01:80:c2:00:00:0x to the CPU port.
2705 */
2706 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2707
2708 /* Ignore removed tag data on doubly tagged packets, disable
2709 * flow control messages, force flow control priority to the
2710 * highest, and send all special multicast frames to the CPU
2711 * port at the highest priority.
2712 */
2713 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2714 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2715 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2716
2717 /* Program the DSA routing table. */
2718 for (i = 0; i < 32; i++) {
2719 int nexthop = 0x1f;
2720
2721 if (ds->pd->rtable &&
2722 i != ds->index && i < ds->dst->pd->nr_chips)
2723 nexthop = ds->pd->rtable[i] & 0x1f;
2724
2725 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2726 GLOBAL2_DEVICE_MAPPING_UPDATE |
2727 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2728 nexthop);
2729 }
2730
2731 /* Clear all trunk masks. */
2732 for (i = 0; i < 8; i++)
2733 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2734 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2735 ((1 << ps->num_ports) - 1));
2736
2737 /* Clear all trunk mappings. */
2738 for (i = 0; i < 16; i++)
2739 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2740 GLOBAL2_TRUNK_MAPPING_UPDATE |
2741 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2742
2743 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2744 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2745 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2746 /* Send all frames with destination addresses matching
2747 * 01:80:c2:00:00:2x to the CPU port.
2748 */
2749 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2750
2751 /* Initialise cross-chip port VLAN table to reset
2752 * defaults.
2753 */
2754 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2755
2756 /* Clear the priority override table. */
2757 for (i = 0; i < 16; i++)
2758 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2759 0x8000 | (i << 8));
2760 }
2761
2762 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2763 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2764 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2765 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2766 /* Disable ingress rate limiting by resetting all
2767 * ingress rate limit registers to their initial
2768 * state.
2769 */
2770 for (i = 0; i < ps->num_ports; i++)
2771 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2772 0x9000 | (i << 8));
2773 }
2774
db687a56
AL		 2775 /* Clear the statistics counters for all ports */
2776 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2777
2778 /* Wait for the flush to complete. */
24751e29
VD		 2779 mutex_lock(&ps->smi_mutex);
2780 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2781 if (ret < 0)
2782 goto unlock;
2783
c161d0a5
VD		 2784 /* Clear all ATU entries */
2785 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2786 if (ret < 0)
2787 goto unlock;
2788
6b17e864
VD		 2789 /* Clear all the VTU and STU entries */
2790 ret = _mv88e6xxx_vtu_stu_flush(ds);
2791unlock:
24751e29 2792 mutex_unlock(&ps->smi_mutex);
db687a56 2793
24751e29 2794 return ret;
54d792f2
AL		 2795}
2796
143a8307
AL		 2797int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2798{
2799 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2800 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
c8c1b39a 2801 struct gpio_desc *gpiod = ds->pd->reset;
143a8307
AL		 2802 unsigned long timeout;
2803 int ret;
2804 int i;
2805
2806 /* Set all ports to the disabled state. */
2807 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2808 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2809 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2810 }
2811
2812 /* Wait for transmit queues to drain. */
2813 usleep_range(2000, 4000);
2814
c8c1b39a
AL		 2815 /* If there is a gpio connected to the reset pin, toggle it */
2816 if (gpiod) {
2817 gpiod_set_value_cansleep(gpiod, 1);
2818 usleep_range(10000, 20000);
2819 gpiod_set_value_cansleep(gpiod, 0);
2820 usleep_range(10000, 20000);
2821 }
2822
143a8307
AL		 2823 /* Reset the switch. Keep the PPU active if requested. The PPU
2824 * needs to be active to support indirect phy register access
2825 * through global registers 0x18 and 0x19.
2826 */
2827 if (ppu_active)
2828 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2829 else
2830 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2831
2832 /* Wait up to one second for reset to complete. */
2833 timeout = jiffies + 1 * HZ;
2834 while (time_before(jiffies, timeout)) {
2835 ret = REG_READ(REG_GLOBAL, 0x00);
2836 if ((ret & is_reset) == is_reset)
2837 break;
2838 usleep_range(1000, 2000);
2839 }
2840 if (time_after(jiffies, timeout))
2841 return -ETIMEDOUT;
2842
2843 return 0;
2844}
2845
49143585
AL		 2846int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2847{
2848 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2849 int ret;
2850
3898c148 2851 mutex_lock(&ps->smi_mutex);
75baacf0 2852 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
3898c148 2853 mutex_unlock(&ps->smi_mutex);
75baacf0 2854
49143585
AL		 2855 return ret;
2856}
2857
2858int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2859 int reg, int val)
2860{
2861 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2862 int ret;
2863
3898c148 2864 mutex_lock(&ps->smi_mutex);
75baacf0 2865 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
3898c148 2866 mutex_unlock(&ps->smi_mutex);
75baacf0 2867
fd3a0ee4
AL		 2868 return ret;
2869}
2870
2871static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2872{
2873 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2874
2875 if (port >= 0 && port < ps->num_ports)
2876 return port;
2877 return -EINVAL;
2878}
2879
2880int
2881mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2882{
2883 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2884 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2885 int ret;
2886
2887 if (addr < 0)
2888 return addr;
2889
3898c148 2890 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2891 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2892 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2893 return ret;
2894}
2895
2896int
2897mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2898{
2899 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2900 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2901 int ret;
2902
2903 if (addr < 0)
2904 return addr;
2905
3898c148 2906 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2907 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2908 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2909 return ret;
2910}
2911
2912int
2913mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2914{
2915 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2916 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2917 int ret;
2918
2919 if (addr < 0)
2920 return addr;
2921
3898c148 2922 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2923 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2924 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2925 return ret;
2926}
2927
2928int
2929mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2930 u16 val)
2931{
2932 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2933 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2934 int ret;
2935
2936 if (addr < 0)
2937 return addr;
2938
3898c148 2939 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2940 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2941 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2942 return ret;
2943}
2944
c22995c5
GR		 2945#ifdef CONFIG_NET_DSA_HWMON
2946
2947static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2948{
2949 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2950 int ret;
2951 int val;
2952
2953 *temp = 0;
2954
2955 mutex_lock(&ps->smi_mutex);
2956
2957 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2958 if (ret < 0)
2959 goto error;
2960
2961 /* Enable temperature sensor */
2962 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2963 if (ret < 0)
2964 goto error;
2965
2966 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2967 if (ret < 0)
2968 goto error;
2969
2970 /* Wait for temperature to stabilize */
2971 usleep_range(10000, 12000);
2972
2973 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2974 if (val < 0) {
2975 ret = val;
2976 goto error;
2977 }
2978
2979 /* Disable temperature sensor */
2980 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2981 if (ret < 0)
2982 goto error;
2983
2984 *temp = ((val & 0x1f) - 5) * 5;
2985
2986error:
2987 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2988 mutex_unlock(&ps->smi_mutex);
2989 return ret;
2990}
2991
2992static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2993{
2994 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2995 int ret;
2996
2997 *temp = 0;
2998
2999 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3000 if (ret < 0)
3001 return ret;
3002
3003 *temp = (ret & 0xff) - 25;
3004
3005 return 0;
3006}
3007
3008int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3009{
3010 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
3011 return mv88e63xx_get_temp(ds, temp);
3012
3013 return mv88e61xx_get_temp(ds, temp);
3014}
3015
3016int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3017{
3018 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3019 int ret;
3020
3021 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3022 return -EOPNOTSUPP;
3023
3024 *temp = 0;
3025
3026 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3027 if (ret < 0)
3028 return ret;
3029
3030 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3031
3032 return 0;
3033}
3034
3035int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3036{
3037 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3038 int ret;
3039
3040 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3041 return -EOPNOTSUPP;
3042
3043 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3044 if (ret < 0)
3045 return ret;
3046 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3047 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3048 (ret & 0xe0ff) | (temp << 8));
3049}
3050
3051int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3052{
3053 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3054 int ret;
3055
3056 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3057 return -EOPNOTSUPP;
3058
3059 *alarm = false;
3060
3061 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3062 if (ret < 0)
3063 return ret;
3064
3065 *alarm = !!(ret & 0x40);
3066
3067 return 0;
3068}
3069#endif /* CONFIG_NET_DSA_HWMON */
3070
c156913b 3071static char *mv88e6xxx_lookup_name(struct mii_bus *bus, int sw_addr,
a77d43f1
AL		 3072 const struct mv88e6xxx_switch_id *table,
3073 unsigned int num)
b9b37713 3074{
b9b37713
VD		 3075 int i, ret;
3076
3077 if (!bus)
3078 return NULL;
3079
3080 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3081 if (ret < 0)
3082 return NULL;
3083
3084 /* Look up the exact switch ID */
3085 for (i = 0; i < num; ++i)
3086 if (table[i].id == ret)
3087 return table[i].name;
3088
3089 /* Look up only the product number */
3090 for (i = 0; i < num; ++i) {
3091 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
c156913b
AL		 3092 dev_warn(&bus->dev,
3093 "unknown revision %d, using base switch 0x%x\n",
b9b37713
VD		 3094 ret & PORT_SWITCH_ID_REV_MASK,
3095 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
3096 return table[i].name;
3097 }
3098 }
3099
3100 return NULL;
3101}
3102
a77d43f1
AL		 3103char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3104 int sw_addr, void **priv,
3105 const struct mv88e6xxx_switch_id *table,
3106 unsigned int num)
3107{
3108 struct mv88e6xxx_priv_state *ps;
c156913b 3109 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
a77d43f1
AL		 3110 char *name;
3111
c156913b
AL		 3112 if (!bus)
3113 return NULL;
3114
3115 name = mv88e6xxx_lookup_name(bus, sw_addr, table, num);
a77d43f1
AL		 3116 if (name) {
3117 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3118 if (!ps)
3119 return NULL;
3120 *priv = ps;
3121 ps->bus = dsa_host_dev_to_mii_bus(host_dev);
3122 if (!ps->bus)
3123 return NULL;
3124 ps->sw_addr = sw_addr;
3125 }
3126 return name;
3127}
3128
98e67308
BH		 3129static int __init mv88e6xxx_init(void)
3130{
3131#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3132 register_switch_driver(&mv88e6131_switch_driver);
3133#endif
ca3dfa51
AL		 3134#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3135 register_switch_driver(&mv88e6123_switch_driver);
42f27253 3136#endif
3ad50cca
GR		 3137#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3138 register_switch_driver(&mv88e6352_switch_driver);
3139#endif
42f27253
AL		 3140#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3141 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 3142#endif
3143 return 0;
3144}
3145module_init(mv88e6xxx_init);
3146
3147static void __exit mv88e6xxx_cleanup(void)
3148{
42f27253
AL		 3149#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3150 unregister_switch_driver(&mv88e6171_switch_driver);
3151#endif
4212b543
VD		 3152#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3153 unregister_switch_driver(&mv88e6352_switch_driver);
3154#endif
ca3dfa51
AL		 3155#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3156 unregister_switch_driver(&mv88e6123_switch_driver);
98e67308
BH		 3157#endif
3158#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3159 unregister_switch_driver(&mv88e6131_switch_driver);
3160#endif
3161}
3162module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3163
3164MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3165MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3166MODULE_LICENSE("GPL");
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