]>
Commit | Line | Data |
---|---|---|
91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
b8fee957 VD |
5 | * Copyright (c) 2015 CMC Electronics, Inc. |
6 | * Added support for VLAN Table Unit operations | |
7 | * | |
91da11f8 LB |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
19b2f97e | 14 | #include <linux/delay.h> |
defb05b9 | 15 | #include <linux/etherdevice.h> |
dea87024 | 16 | #include <linux/ethtool.h> |
facd95b2 | 17 | #include <linux/if_bridge.h> |
19b2f97e | 18 | #include <linux/jiffies.h> |
91da11f8 | 19 | #include <linux/list.h> |
2bbba277 | 20 | #include <linux/module.h> |
91da11f8 LB |
21 | #include <linux/netdevice.h> |
22 | #include <linux/phy.h> | |
c8f0b869 | 23 | #include <net/dsa.h> |
1f36faf2 | 24 | #include <net/switchdev.h> |
91da11f8 LB |
25 | #include "mv88e6xxx.h" |
26 | ||
3675c8d7 | 27 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
28 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
29 | * will be directly accessible on some {device address,register address} | |
30 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
31 | * will only respond to SMI transactions to that specific address, and | |
32 | * an indirect addressing mechanism needs to be used to access its | |
33 | * registers. | |
34 | */ | |
35 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
36 | { | |
37 | int ret; | |
38 | int i; | |
39 | ||
40 | for (i = 0; i < 16; i++) { | |
6e899e6c | 41 | ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
42 | if (ret < 0) |
43 | return ret; | |
44 | ||
cca8b133 | 45 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
46 | return 0; |
47 | } | |
48 | ||
49 | return -ETIMEDOUT; | |
50 | } | |
51 | ||
52 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
53 | { | |
54 | int ret; | |
55 | ||
56 | if (sw_addr == 0) | |
6e899e6c | 57 | return mdiobus_read_nested(bus, addr, reg); |
91da11f8 | 58 | |
3675c8d7 | 59 | /* Wait for the bus to become free. */ |
91da11f8 LB |
60 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
61 | if (ret < 0) | |
62 | return ret; | |
63 | ||
3675c8d7 | 64 | /* Transmit the read command. */ |
6e899e6c NA |
65 | ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, |
66 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
67 | if (ret < 0) |
68 | return ret; | |
69 | ||
3675c8d7 | 70 | /* Wait for the read command to complete. */ |
91da11f8 LB |
71 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
72 | if (ret < 0) | |
73 | return ret; | |
74 | ||
3675c8d7 | 75 | /* Read the data. */ |
6e899e6c | 76 | ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
77 | if (ret < 0) |
78 | return ret; | |
79 | ||
80 | return ret & 0xffff; | |
81 | } | |
82 | ||
8d6d09e7 GR |
83 | /* Must be called with SMI mutex held */ |
84 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 85 | { |
b184e497 | 86 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
87 | int ret; |
88 | ||
b184e497 GR |
89 | if (bus == NULL) |
90 | return -EINVAL; | |
91 | ||
b184e497 | 92 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
93 | if (ret < 0) |
94 | return ret; | |
95 | ||
96 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
97 | addr, reg, ret); | |
98 | ||
91da11f8 LB |
99 | return ret; |
100 | } | |
101 | ||
8d6d09e7 GR |
102 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
103 | { | |
104 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
105 | int ret; | |
106 | ||
107 | mutex_lock(&ps->smi_mutex); | |
108 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
109 | mutex_unlock(&ps->smi_mutex); | |
110 | ||
111 | return ret; | |
112 | } | |
113 | ||
91da11f8 LB |
114 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
115 | int reg, u16 val) | |
116 | { | |
117 | int ret; | |
118 | ||
119 | if (sw_addr == 0) | |
6e899e6c | 120 | return mdiobus_write_nested(bus, addr, reg, val); |
91da11f8 | 121 | |
3675c8d7 | 122 | /* Wait for the bus to become free. */ |
91da11f8 LB |
123 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
124 | if (ret < 0) | |
125 | return ret; | |
126 | ||
3675c8d7 | 127 | /* Transmit the data to write. */ |
6e899e6c | 128 | ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
129 | if (ret < 0) |
130 | return ret; | |
131 | ||
3675c8d7 | 132 | /* Transmit the write command. */ |
6e899e6c NA |
133 | ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, |
134 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
135 | if (ret < 0) |
136 | return ret; | |
137 | ||
3675c8d7 | 138 | /* Wait for the write command to complete. */ |
91da11f8 LB |
139 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
140 | if (ret < 0) | |
141 | return ret; | |
142 | ||
143 | return 0; | |
144 | } | |
145 | ||
8d6d09e7 GR |
146 | /* Must be called with SMI mutex held */ |
147 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
148 | u16 val) | |
91da11f8 | 149 | { |
b184e497 | 150 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 151 | |
b184e497 GR |
152 | if (bus == NULL) |
153 | return -EINVAL; | |
154 | ||
bb92ea5e VD |
155 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
156 | addr, reg, val); | |
157 | ||
8d6d09e7 GR |
158 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
159 | } | |
160 | ||
161 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
162 | { | |
163 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
164 | int ret; | |
165 | ||
91da11f8 | 166 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 167 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
168 | mutex_unlock(&ps->smi_mutex); |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
2e5f0320 LB |
173 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
174 | { | |
cca8b133 AL |
175 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
176 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
177 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
178 | |
179 | return 0; | |
180 | } | |
181 | ||
91da11f8 LB |
182 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
183 | { | |
184 | int i; | |
185 | int ret; | |
186 | ||
187 | for (i = 0; i < 6; i++) { | |
188 | int j; | |
189 | ||
3675c8d7 | 190 | /* Write the MAC address byte. */ |
cca8b133 AL |
191 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
192 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 193 | |
3675c8d7 | 194 | /* Wait for the write to complete. */ |
91da11f8 | 195 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
196 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
197 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
198 | break; |
199 | } | |
200 | if (j == 16) | |
201 | return -ETIMEDOUT; | |
202 | } | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
3898c148 | 207 | /* Must be called with SMI mutex held */ |
fd3a0ee4 | 208 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
209 | { |
210 | if (addr >= 0) | |
3898c148 | 211 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
212 | return 0xffff; |
213 | } | |
214 | ||
3898c148 | 215 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
216 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
217 | u16 val) | |
91da11f8 LB |
218 | { |
219 | if (addr >= 0) | |
3898c148 | 220 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
221 | return 0; |
222 | } | |
223 | ||
2e5f0320 LB |
224 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
225 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
226 | { | |
227 | int ret; | |
19b2f97e | 228 | unsigned long timeout; |
2e5f0320 | 229 | |
cca8b133 AL |
230 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
231 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
232 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 233 | |
19b2f97e BG |
234 | timeout = jiffies + 1 * HZ; |
235 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 236 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 237 | usleep_range(1000, 2000); |
cca8b133 AL |
238 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
239 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 240 | return 0; |
2e5f0320 LB |
241 | } |
242 | ||
243 | return -ETIMEDOUT; | |
244 | } | |
245 | ||
246 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
247 | { | |
248 | int ret; | |
19b2f97e | 249 | unsigned long timeout; |
2e5f0320 | 250 | |
cca8b133 AL |
251 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
252 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 253 | |
19b2f97e BG |
254 | timeout = jiffies + 1 * HZ; |
255 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 256 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 257 | usleep_range(1000, 2000); |
cca8b133 AL |
258 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
259 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 260 | return 0; |
2e5f0320 LB |
261 | } |
262 | ||
263 | return -ETIMEDOUT; | |
264 | } | |
265 | ||
266 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
267 | { | |
268 | struct mv88e6xxx_priv_state *ps; | |
269 | ||
270 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
271 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 272 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 273 | |
85686581 BG |
274 | if (mv88e6xxx_ppu_enable(ds) == 0) |
275 | ps->ppu_disabled = 0; | |
276 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
277 | } |
278 | } | |
279 | ||
280 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
281 | { | |
282 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
283 | ||
284 | schedule_work(&ps->ppu_work); | |
285 | } | |
286 | ||
287 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
288 | { | |
a22adce5 | 289 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
290 | int ret; |
291 | ||
292 | mutex_lock(&ps->ppu_mutex); | |
293 | ||
3675c8d7 | 294 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
295 | * we can access the PHY registers. If it was already |
296 | * disabled, cancel the timer that is going to re-enable | |
297 | * it. | |
298 | */ | |
299 | if (!ps->ppu_disabled) { | |
85686581 BG |
300 | ret = mv88e6xxx_ppu_disable(ds); |
301 | if (ret < 0) { | |
302 | mutex_unlock(&ps->ppu_mutex); | |
303 | return ret; | |
304 | } | |
305 | ps->ppu_disabled = 1; | |
2e5f0320 | 306 | } else { |
85686581 BG |
307 | del_timer(&ps->ppu_timer); |
308 | ret = 0; | |
2e5f0320 LB |
309 | } |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
314 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
315 | { | |
a22adce5 | 316 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 317 | |
3675c8d7 | 318 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
319 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
320 | mutex_unlock(&ps->ppu_mutex); | |
321 | } | |
322 | ||
323 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
324 | { | |
a22adce5 | 325 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
326 | |
327 | mutex_init(&ps->ppu_mutex); | |
328 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
329 | init_timer(&ps->ppu_timer); | |
330 | ps->ppu_timer.data = (unsigned long)ps; | |
331 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
332 | } | |
333 | ||
334 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
335 | { | |
336 | int ret; | |
337 | ||
338 | ret = mv88e6xxx_ppu_access_get(ds); | |
339 | if (ret >= 0) { | |
85686581 BG |
340 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
341 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
342 | } |
343 | ||
344 | return ret; | |
345 | } | |
346 | ||
347 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
348 | int regnum, u16 val) | |
349 | { | |
350 | int ret; | |
351 | ||
352 | ret = mv88e6xxx_ppu_access_get(ds); | |
353 | if (ret >= 0) { | |
85686581 BG |
354 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
355 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
356 | } |
357 | ||
358 | return ret; | |
359 | } | |
360 | #endif | |
361 | ||
54d792f2 AL |
362 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
363 | { | |
364 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
365 | ||
366 | switch (ps->id) { | |
367 | case PORT_SWITCH_ID_6031: | |
368 | case PORT_SWITCH_ID_6061: | |
369 | case PORT_SWITCH_ID_6035: | |
370 | case PORT_SWITCH_ID_6065: | |
371 | return true; | |
372 | } | |
373 | return false; | |
374 | } | |
375 | ||
376 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
377 | { | |
378 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
379 | ||
380 | switch (ps->id) { | |
381 | case PORT_SWITCH_ID_6092: | |
382 | case PORT_SWITCH_ID_6095: | |
383 | return true; | |
384 | } | |
385 | return false; | |
386 | } | |
387 | ||
388 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
389 | { | |
390 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
391 | ||
392 | switch (ps->id) { | |
393 | case PORT_SWITCH_ID_6046: | |
394 | case PORT_SWITCH_ID_6085: | |
395 | case PORT_SWITCH_ID_6096: | |
396 | case PORT_SWITCH_ID_6097: | |
397 | return true; | |
398 | } | |
399 | return false; | |
400 | } | |
401 | ||
402 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
403 | { | |
404 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
405 | ||
406 | switch (ps->id) { | |
407 | case PORT_SWITCH_ID_6123: | |
408 | case PORT_SWITCH_ID_6161: | |
409 | case PORT_SWITCH_ID_6165: | |
410 | return true; | |
411 | } | |
412 | return false; | |
413 | } | |
414 | ||
415 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
416 | { | |
417 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
418 | ||
419 | switch (ps->id) { | |
420 | case PORT_SWITCH_ID_6121: | |
421 | case PORT_SWITCH_ID_6122: | |
422 | case PORT_SWITCH_ID_6152: | |
423 | case PORT_SWITCH_ID_6155: | |
424 | case PORT_SWITCH_ID_6182: | |
425 | case PORT_SWITCH_ID_6185: | |
426 | case PORT_SWITCH_ID_6108: | |
427 | case PORT_SWITCH_ID_6131: | |
428 | return true; | |
429 | } | |
430 | return false; | |
431 | } | |
432 | ||
c22995c5 | 433 | static bool mv88e6xxx_6320_family(struct dsa_switch *ds) |
7c3d0d67 AK |
434 | { |
435 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
436 | ||
437 | switch (ps->id) { | |
438 | case PORT_SWITCH_ID_6320: | |
439 | case PORT_SWITCH_ID_6321: | |
440 | return true; | |
441 | } | |
442 | return false; | |
443 | } | |
444 | ||
54d792f2 AL |
445 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) |
446 | { | |
447 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
448 | ||
449 | switch (ps->id) { | |
450 | case PORT_SWITCH_ID_6171: | |
451 | case PORT_SWITCH_ID_6175: | |
452 | case PORT_SWITCH_ID_6350: | |
453 | case PORT_SWITCH_ID_6351: | |
454 | return true; | |
455 | } | |
456 | return false; | |
457 | } | |
458 | ||
f3a8b6b6 AL |
459 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
460 | { | |
461 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
462 | ||
463 | switch (ps->id) { | |
f3a8b6b6 AL |
464 | case PORT_SWITCH_ID_6172: |
465 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
466 | case PORT_SWITCH_ID_6240: |
467 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
468 | return true; |
469 | } | |
470 | return false; | |
471 | } | |
472 | ||
dea87024 AL |
473 | /* We expect the switch to perform auto negotiation if there is a real |
474 | * phy. However, in the case of a fixed link phy, we force the port | |
475 | * settings from the fixed link settings. | |
476 | */ | |
477 | void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, | |
478 | struct phy_device *phydev) | |
479 | { | |
480 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
49052871 AL |
481 | u32 reg; |
482 | int ret; | |
dea87024 AL |
483 | |
484 | if (!phy_is_pseudo_fixed_link(phydev)) | |
485 | return; | |
486 | ||
487 | mutex_lock(&ps->smi_mutex); | |
488 | ||
489 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
490 | if (ret < 0) | |
491 | goto out; | |
492 | ||
493 | reg = ret & ~(PORT_PCS_CTRL_LINK_UP | | |
494 | PORT_PCS_CTRL_FORCE_LINK | | |
495 | PORT_PCS_CTRL_DUPLEX_FULL | | |
496 | PORT_PCS_CTRL_FORCE_DUPLEX | | |
497 | PORT_PCS_CTRL_UNFORCED); | |
498 | ||
499 | reg |= PORT_PCS_CTRL_FORCE_LINK; | |
500 | if (phydev->link) | |
501 | reg |= PORT_PCS_CTRL_LINK_UP; | |
502 | ||
503 | if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100) | |
504 | goto out; | |
505 | ||
506 | switch (phydev->speed) { | |
507 | case SPEED_1000: | |
508 | reg |= PORT_PCS_CTRL_1000; | |
509 | break; | |
510 | case SPEED_100: | |
511 | reg |= PORT_PCS_CTRL_100; | |
512 | break; | |
513 | case SPEED_10: | |
514 | reg |= PORT_PCS_CTRL_10; | |
515 | break; | |
516 | default: | |
517 | pr_info("Unknown speed"); | |
518 | goto out; | |
519 | } | |
520 | ||
521 | reg |= PORT_PCS_CTRL_FORCE_DUPLEX; | |
522 | if (phydev->duplex == DUPLEX_FULL) | |
523 | reg |= PORT_PCS_CTRL_DUPLEX_FULL; | |
524 | ||
e7e72ac0 AL |
525 | if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) && |
526 | (port >= ps->num_ports - 2)) { | |
527 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) | |
528 | reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; | |
529 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
530 | reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; | |
531 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
532 | reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | | |
533 | PORT_PCS_CTRL_RGMII_DELAY_TXCLK); | |
534 | } | |
dea87024 AL |
535 | _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg); |
536 | ||
537 | out: | |
538 | mutex_unlock(&ps->smi_mutex); | |
539 | } | |
540 | ||
31888234 AL |
541 | /* Must be called with SMI mutex held */ |
542 | static int _mv88e6xxx_stats_wait(struct dsa_switch *ds) | |
91da11f8 LB |
543 | { |
544 | int ret; | |
545 | int i; | |
546 | ||
547 | for (i = 0; i < 10; i++) { | |
31888234 | 548 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 549 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
550 | return 0; |
551 | } | |
552 | ||
553 | return -ETIMEDOUT; | |
554 | } | |
555 | ||
31888234 AL |
556 | /* Must be called with SMI mutex held */ |
557 | static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
91da11f8 LB |
558 | { |
559 | int ret; | |
560 | ||
7c3d0d67 | 561 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) |
f3a8b6b6 AL |
562 | port = (port + 1) << 5; |
563 | ||
3675c8d7 | 564 | /* Snapshot the hardware statistics counters for this port. */ |
31888234 AL |
565 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
566 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
567 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
568 | if (ret < 0) | |
569 | return ret; | |
91da11f8 | 570 | |
3675c8d7 | 571 | /* Wait for the snapshotting to complete. */ |
31888234 | 572 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
573 | if (ret < 0) |
574 | return ret; | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
31888234 AL |
579 | /* Must be called with SMI mutex held */ |
580 | static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
91da11f8 LB |
581 | { |
582 | u32 _val; | |
583 | int ret; | |
584 | ||
585 | *val = 0; | |
586 | ||
31888234 AL |
587 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
588 | GLOBAL_STATS_OP_READ_CAPTURED | | |
589 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
590 | if (ret < 0) |
591 | return; | |
592 | ||
31888234 | 593 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
594 | if (ret < 0) |
595 | return; | |
596 | ||
31888234 | 597 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
598 | if (ret < 0) |
599 | return; | |
600 | ||
601 | _val = ret << 16; | |
602 | ||
31888234 | 603 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
604 | if (ret < 0) |
605 | return; | |
606 | ||
607 | *val = _val | ret; | |
608 | } | |
609 | ||
e413e7e1 AL |
610 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
611 | { "in_good_octets", 8, 0x00, }, | |
612 | { "in_bad_octets", 4, 0x02, }, | |
613 | { "in_unicast", 4, 0x04, }, | |
614 | { "in_broadcasts", 4, 0x06, }, | |
615 | { "in_multicasts", 4, 0x07, }, | |
616 | { "in_pause", 4, 0x16, }, | |
617 | { "in_undersize", 4, 0x18, }, | |
618 | { "in_fragments", 4, 0x19, }, | |
619 | { "in_oversize", 4, 0x1a, }, | |
620 | { "in_jabber", 4, 0x1b, }, | |
621 | { "in_rx_error", 4, 0x1c, }, | |
622 | { "in_fcs_error", 4, 0x1d, }, | |
623 | { "out_octets", 8, 0x0e, }, | |
624 | { "out_unicast", 4, 0x10, }, | |
625 | { "out_broadcasts", 4, 0x13, }, | |
626 | { "out_multicasts", 4, 0x12, }, | |
627 | { "out_pause", 4, 0x15, }, | |
628 | { "excessive", 4, 0x11, }, | |
629 | { "collisions", 4, 0x1e, }, | |
630 | { "deferred", 4, 0x05, }, | |
631 | { "single", 4, 0x14, }, | |
632 | { "multiple", 4, 0x17, }, | |
633 | { "out_fcs_error", 4, 0x03, }, | |
634 | { "late", 4, 0x1f, }, | |
635 | { "hist_64bytes", 4, 0x08, }, | |
636 | { "hist_65_127bytes", 4, 0x09, }, | |
637 | { "hist_128_255bytes", 4, 0x0a, }, | |
638 | { "hist_256_511bytes", 4, 0x0b, }, | |
639 | { "hist_512_1023bytes", 4, 0x0c, }, | |
640 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
641 | /* Not all devices have the following counters */ | |
642 | { "sw_in_discards", 4, 0x110, }, | |
643 | { "sw_in_filtered", 2, 0x112, }, | |
644 | { "sw_out_filtered", 2, 0x113, }, | |
645 | ||
646 | }; | |
647 | ||
648 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
649 | { | |
650 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
651 | ||
652 | switch (ps->id) { | |
cca8b133 AL |
653 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
654 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
655 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
656 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
657 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
658 | return true; |
659 | default: | |
660 | return false; | |
661 | } | |
662 | } | |
663 | ||
664 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
665 | int nr_stats, | |
666 | struct mv88e6xxx_hw_stat *stats, | |
667 | int port, uint8_t *data) | |
91da11f8 LB |
668 | { |
669 | int i; | |
670 | ||
671 | for (i = 0; i < nr_stats; i++) { | |
672 | memcpy(data + i * ETH_GSTRING_LEN, | |
673 | stats[i].string, ETH_GSTRING_LEN); | |
674 | } | |
675 | } | |
676 | ||
80c4627b AL |
677 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, |
678 | int stat, | |
679 | struct mv88e6xxx_hw_stat *stats, | |
680 | int port) | |
681 | { | |
682 | struct mv88e6xxx_hw_stat *s = stats + stat; | |
683 | u32 low; | |
684 | u32 high = 0; | |
685 | int ret; | |
686 | u64 value; | |
687 | ||
688 | if (s->reg >= 0x100) { | |
689 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
690 | s->reg - 0x100); | |
691 | if (ret < 0) | |
692 | return UINT64_MAX; | |
693 | ||
694 | low = ret; | |
695 | if (s->sizeof_stat == 4) { | |
696 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
697 | s->reg - 0x100 + 1); | |
698 | if (ret < 0) | |
699 | return UINT64_MAX; | |
700 | high = ret; | |
701 | } | |
702 | } else { | |
703 | _mv88e6xxx_stats_read(ds, s->reg, &low); | |
704 | if (s->sizeof_stat == 8) | |
705 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
706 | } | |
707 | value = (((u64)high) << 16) | low; | |
708 | return value; | |
709 | } | |
710 | ||
e413e7e1 AL |
711 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
712 | int nr_stats, | |
713 | struct mv88e6xxx_hw_stat *stats, | |
714 | int port, uint64_t *data) | |
91da11f8 | 715 | { |
a22adce5 | 716 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
717 | int ret; |
718 | int i; | |
719 | ||
31888234 | 720 | mutex_lock(&ps->smi_mutex); |
91da11f8 | 721 | |
31888234 | 722 | ret = _mv88e6xxx_stats_snapshot(ds, port); |
91da11f8 | 723 | if (ret < 0) { |
31888234 | 724 | mutex_unlock(&ps->smi_mutex); |
91da11f8 LB |
725 | return; |
726 | } | |
727 | ||
3675c8d7 | 728 | /* Read each of the counters. */ |
80c4627b AL |
729 | for (i = 0; i < nr_stats; i++) |
730 | data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port); | |
91da11f8 | 731 | |
31888234 | 732 | mutex_unlock(&ps->smi_mutex); |
91da11f8 | 733 | } |
98e67308 | 734 | |
e413e7e1 AL |
735 | /* All the statistics in the table */ |
736 | void | |
737 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
738 | { | |
739 | if (have_sw_in_discards(ds)) | |
740 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
741 | mv88e6xxx_hw_stats, port, data); | |
742 | else | |
743 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
744 | mv88e6xxx_hw_stats, port, data); | |
745 | } | |
746 | ||
747 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
748 | { | |
749 | if (have_sw_in_discards(ds)) | |
750 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
751 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
752 | } | |
753 | ||
754 | void | |
755 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
756 | int port, uint64_t *data) | |
757 | { | |
758 | if (have_sw_in_discards(ds)) | |
759 | _mv88e6xxx_get_ethtool_stats( | |
760 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
761 | mv88e6xxx_hw_stats, port, data); | |
762 | else | |
763 | _mv88e6xxx_get_ethtool_stats( | |
764 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
765 | mv88e6xxx_hw_stats, port, data); | |
766 | } | |
767 | ||
a1ab91f3 GR |
768 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
769 | { | |
770 | return 32 * sizeof(u16); | |
771 | } | |
772 | ||
773 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
774 | struct ethtool_regs *regs, void *_p) | |
775 | { | |
776 | u16 *p = _p; | |
777 | int i; | |
778 | ||
779 | regs->version = 0; | |
780 | ||
781 | memset(p, 0xff, 32 * sizeof(u16)); | |
782 | ||
783 | for (i = 0; i < 32; i++) { | |
784 | int ret; | |
785 | ||
786 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
787 | if (ret >= 0) | |
788 | p[i] = ret; | |
789 | } | |
790 | } | |
791 | ||
3898c148 AL |
792 | /* Must be called with SMI lock held */ |
793 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, | |
794 | u16 mask) | |
f3044683 AL |
795 | { |
796 | unsigned long timeout = jiffies + HZ / 10; | |
797 | ||
798 | while (time_before(jiffies, timeout)) { | |
799 | int ret; | |
800 | ||
3898c148 AL |
801 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
802 | if (ret < 0) | |
803 | return ret; | |
f3044683 AL |
804 | if (!(ret & mask)) |
805 | return 0; | |
806 | ||
807 | usleep_range(1000, 2000); | |
808 | } | |
809 | return -ETIMEDOUT; | |
810 | } | |
811 | ||
3898c148 AL |
812 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
813 | { | |
814 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
815 | int ret; | |
816 | ||
817 | mutex_lock(&ps->smi_mutex); | |
818 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
819 | mutex_unlock(&ps->smi_mutex); | |
820 | ||
821 | return ret; | |
822 | } | |
823 | ||
824 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 825 | { |
3898c148 AL |
826 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
827 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
828 | } |
829 | ||
830 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
831 | { | |
cca8b133 AL |
832 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
833 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
834 | } |
835 | ||
836 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
837 | { | |
cca8b133 AL |
838 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
839 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
840 | } |
841 | ||
facd95b2 GR |
842 | /* Must be called with SMI lock held */ |
843 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
844 | { | |
cca8b133 AL |
845 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
846 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
847 | } |
848 | ||
3898c148 | 849 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
850 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
851 | int regnum) | |
f3044683 AL |
852 | { |
853 | int ret; | |
854 | ||
3898c148 AL |
855 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
856 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
857 | regnum); | |
858 | if (ret < 0) | |
859 | return ret; | |
f3044683 | 860 | |
3898c148 | 861 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
862 | if (ret < 0) |
863 | return ret; | |
864 | ||
3898c148 | 865 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
866 | } |
867 | ||
3898c148 | 868 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
869 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
870 | int regnum, u16 val) | |
f3044683 | 871 | { |
3898c148 AL |
872 | int ret; |
873 | ||
874 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
875 | if (ret < 0) | |
876 | return ret; | |
f3044683 | 877 | |
3898c148 AL |
878 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
879 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
880 | regnum); | |
881 | ||
882 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
883 | } |
884 | ||
11b3b45d GR |
885 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
886 | { | |
2f40c698 | 887 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
888 | int reg; |
889 | ||
3898c148 | 890 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
891 | |
892 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 893 | if (reg < 0) |
2f40c698 | 894 | goto out; |
11b3b45d GR |
895 | |
896 | e->eee_enabled = !!(reg & 0x0200); | |
897 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
898 | ||
3898c148 | 899 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 900 | if (reg < 0) |
2f40c698 | 901 | goto out; |
11b3b45d | 902 | |
cca8b133 | 903 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 904 | reg = 0; |
11b3b45d | 905 | |
2f40c698 | 906 | out: |
3898c148 | 907 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 908 | return reg; |
11b3b45d GR |
909 | } |
910 | ||
911 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
912 | struct phy_device *phydev, struct ethtool_eee *e) | |
913 | { | |
2f40c698 AL |
914 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
915 | int reg; | |
11b3b45d GR |
916 | int ret; |
917 | ||
3898c148 | 918 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 919 | |
2f40c698 AL |
920 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
921 | if (ret < 0) | |
922 | goto out; | |
923 | ||
924 | reg = ret & ~0x0300; | |
925 | if (e->eee_enabled) | |
926 | reg |= 0x0200; | |
927 | if (e->tx_lpi_enabled) | |
928 | reg |= 0x0100; | |
929 | ||
930 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
931 | out: | |
3898c148 | 932 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
933 | |
934 | return ret; | |
11b3b45d GR |
935 | } |
936 | ||
70cc99d1 | 937 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd) |
facd95b2 GR |
938 | { |
939 | int ret; | |
940 | ||
cca8b133 | 941 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
942 | if (ret < 0) |
943 | return ret; | |
944 | ||
945 | return _mv88e6xxx_atu_wait(ds); | |
946 | } | |
947 | ||
37705b73 VD |
948 | static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds, |
949 | struct mv88e6xxx_atu_entry *entry) | |
950 | { | |
951 | u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; | |
952 | ||
953 | if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
954 | unsigned int mask, shift; | |
955 | ||
956 | if (entry->trunk) { | |
957 | data |= GLOBAL_ATU_DATA_TRUNK; | |
958 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
959 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
960 | } else { | |
961 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
962 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
963 | } | |
964 | ||
965 | data |= (entry->portv_trunkid << shift) & mask; | |
966 | } | |
967 | ||
968 | return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data); | |
969 | } | |
970 | ||
7fb5e755 VD |
971 | static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds, |
972 | struct mv88e6xxx_atu_entry *entry, | |
973 | bool static_too) | |
facd95b2 | 974 | { |
7fb5e755 VD |
975 | int op; |
976 | int err; | |
facd95b2 | 977 | |
7fb5e755 VD |
978 | err = _mv88e6xxx_atu_wait(ds); |
979 | if (err) | |
980 | return err; | |
facd95b2 | 981 | |
7fb5e755 VD |
982 | err = _mv88e6xxx_atu_data_write(ds, entry); |
983 | if (err) | |
984 | return err; | |
985 | ||
986 | if (entry->fid) { | |
987 | err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, | |
988 | entry->fid); | |
989 | if (err) | |
990 | return err; | |
991 | ||
992 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : | |
993 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; | |
994 | } else { | |
995 | op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : | |
996 | GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; | |
997 | } | |
998 | ||
999 | return _mv88e6xxx_atu_cmd(ds, op); | |
1000 | } | |
1001 | ||
1002 | static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too) | |
1003 | { | |
1004 | struct mv88e6xxx_atu_entry entry = { | |
1005 | .fid = fid, | |
1006 | .state = 0, /* EntryState bits must be 0 */ | |
1007 | }; | |
70cc99d1 | 1008 | |
7fb5e755 VD |
1009 | return _mv88e6xxx_atu_flush_move(ds, &entry, static_too); |
1010 | } | |
1011 | ||
9f4d55d2 VD |
1012 | static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port, |
1013 | int to_port, bool static_too) | |
1014 | { | |
1015 | struct mv88e6xxx_atu_entry entry = { | |
1016 | .trunk = false, | |
1017 | .fid = fid, | |
1018 | }; | |
1019 | ||
1020 | /* EntryState bits must be 0xF */ | |
1021 | entry.state = GLOBAL_ATU_DATA_STATE_MASK; | |
1022 | ||
1023 | /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ | |
1024 | entry.portv_trunkid = (to_port & 0x0f) << 4; | |
1025 | entry.portv_trunkid |= from_port & 0x0f; | |
1026 | ||
1027 | return _mv88e6xxx_atu_flush_move(ds, &entry, static_too); | |
1028 | } | |
1029 | ||
1030 | static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port, | |
1031 | bool static_too) | |
1032 | { | |
1033 | /* Destination port 0xF means remove the entries */ | |
1034 | return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too); | |
1035 | } | |
1036 | ||
facd95b2 GR |
1037 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) |
1038 | { | |
1039 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 1040 | int reg, ret = 0; |
facd95b2 GR |
1041 | u8 oldstate; |
1042 | ||
1043 | mutex_lock(&ps->smi_mutex); | |
1044 | ||
cca8b133 | 1045 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
1046 | if (reg < 0) { |
1047 | ret = reg; | |
facd95b2 | 1048 | goto abort; |
538cc282 | 1049 | } |
facd95b2 | 1050 | |
cca8b133 | 1051 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
1052 | if (oldstate != state) { |
1053 | /* Flush forwarding database if we're moving a port | |
1054 | * from Learning or Forwarding state to Disabled or | |
1055 | * Blocking or Listening state. | |
1056 | */ | |
cca8b133 AL |
1057 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
1058 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
2b8157b1 | 1059 | ret = _mv88e6xxx_atu_remove(ds, 0, port, false); |
facd95b2 GR |
1060 | if (ret) |
1061 | goto abort; | |
1062 | } | |
cca8b133 AL |
1063 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1064 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1065 | reg); | |
facd95b2 GR |
1066 | } |
1067 | ||
1068 | abort: | |
1069 | mutex_unlock(&ps->smi_mutex); | |
1070 | return ret; | |
1071 | } | |
1072 | ||
ede8098d VD |
1073 | static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port, |
1074 | u16 output_ports) | |
facd95b2 GR |
1075 | { |
1076 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
ede8098d VD |
1077 | const u16 mask = (1 << ps->num_ports) - 1; |
1078 | int reg; | |
facd95b2 | 1079 | |
ede8098d VD |
1080 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN); |
1081 | if (reg < 0) | |
1082 | return reg; | |
facd95b2 | 1083 | |
ede8098d VD |
1084 | reg &= ~mask; |
1085 | reg |= output_ports & mask; | |
facd95b2 | 1086 | |
ede8098d | 1087 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1088 | } |
1089 | ||
facd95b2 GR |
1090 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) |
1091 | { | |
1092 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1093 | int stp_state; | |
1094 | ||
1095 | switch (state) { | |
1096 | case BR_STATE_DISABLED: | |
cca8b133 | 1097 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1098 | break; |
1099 | case BR_STATE_BLOCKING: | |
1100 | case BR_STATE_LISTENING: | |
cca8b133 | 1101 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1102 | break; |
1103 | case BR_STATE_LEARNING: | |
cca8b133 | 1104 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1105 | break; |
1106 | case BR_STATE_FORWARDING: | |
1107 | default: | |
cca8b133 | 1108 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1109 | break; |
1110 | } | |
1111 | ||
1112 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1113 | ||
1114 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1115 | * so we can not update the port state directly but need to schedule it. | |
1116 | */ | |
1117 | ps->port_state[port] = stp_state; | |
1118 | set_bit(port, &ps->port_state_update_mask); | |
1119 | schedule_work(&ps->bridge_work); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
76e398a6 VD |
1124 | static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid) |
1125 | { | |
1126 | int ret; | |
1127 | ||
1128 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN); | |
1129 | if (ret < 0) | |
1130 | return ret; | |
1131 | ||
1132 | *pvid = ret & PORT_DEFAULT_VLAN_MASK; | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
b8fee957 VD |
1137 | int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid) |
1138 | { | |
1139 | int ret; | |
1140 | ||
1141 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN); | |
1142 | if (ret < 0) | |
1143 | return ret; | |
1144 | ||
1145 | *pvid = ret & PORT_DEFAULT_VLAN_MASK; | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
76e398a6 | 1150 | static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid) |
0d3b33e6 | 1151 | { |
76e398a6 | 1152 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
0d3b33e6 VD |
1153 | pvid & PORT_DEFAULT_VLAN_MASK); |
1154 | } | |
1155 | ||
6b17e864 VD |
1156 | static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds) |
1157 | { | |
1158 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP, | |
1159 | GLOBAL_VTU_OP_BUSY); | |
1160 | } | |
1161 | ||
1162 | static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op) | |
1163 | { | |
1164 | int ret; | |
1165 | ||
1166 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op); | |
1167 | if (ret < 0) | |
1168 | return ret; | |
1169 | ||
1170 | return _mv88e6xxx_vtu_wait(ds); | |
1171 | } | |
1172 | ||
1173 | static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds) | |
1174 | { | |
1175 | int ret; | |
1176 | ||
1177 | ret = _mv88e6xxx_vtu_wait(ds); | |
1178 | if (ret < 0) | |
1179 | return ret; | |
1180 | ||
1181 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL); | |
1182 | } | |
1183 | ||
b8fee957 VD |
1184 | static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds, |
1185 | struct mv88e6xxx_vtu_stu_entry *entry, | |
1186 | unsigned int nibble_offset) | |
1187 | { | |
1188 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1189 | u16 regs[3]; | |
1190 | int i; | |
1191 | int ret; | |
1192 | ||
1193 | for (i = 0; i < 3; ++i) { | |
1194 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1195 | GLOBAL_VTU_DATA_0_3 + i); | |
1196 | if (ret < 0) | |
1197 | return ret; | |
1198 | ||
1199 | regs[i] = ret; | |
1200 | } | |
1201 | ||
1202 | for (i = 0; i < ps->num_ports; ++i) { | |
1203 | unsigned int shift = (i % 4) * 4 + nibble_offset; | |
1204 | u16 reg = regs[i / 4]; | |
1205 | ||
1206 | entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
7dad08d7 VD |
1212 | static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds, |
1213 | struct mv88e6xxx_vtu_stu_entry *entry, | |
1214 | unsigned int nibble_offset) | |
1215 | { | |
1216 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1217 | u16 regs[3] = { 0 }; | |
1218 | int i; | |
1219 | int ret; | |
1220 | ||
1221 | for (i = 0; i < ps->num_ports; ++i) { | |
1222 | unsigned int shift = (i % 4) * 4 + nibble_offset; | |
1223 | u8 data = entry->data[i]; | |
1224 | ||
1225 | regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; | |
1226 | } | |
1227 | ||
1228 | for (i = 0; i < 3; ++i) { | |
1229 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, | |
1230 | GLOBAL_VTU_DATA_0_3 + i, regs[i]); | |
1231 | if (ret < 0) | |
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
36d04ba1 VD |
1238 | static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid) |
1239 | { | |
1240 | return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, | |
1241 | vid & GLOBAL_VTU_VID_MASK); | |
1242 | } | |
1243 | ||
1244 | static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, | |
b8fee957 VD |
1245 | struct mv88e6xxx_vtu_stu_entry *entry) |
1246 | { | |
1247 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1248 | int ret; | |
1249 | ||
1250 | ret = _mv88e6xxx_vtu_wait(ds); | |
1251 | if (ret < 0) | |
1252 | return ret; | |
1253 | ||
b8fee957 VD |
1254 | ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT); |
1255 | if (ret < 0) | |
1256 | return ret; | |
1257 | ||
1258 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID); | |
1259 | if (ret < 0) | |
1260 | return ret; | |
1261 | ||
1262 | next.vid = ret & GLOBAL_VTU_VID_MASK; | |
1263 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1264 | ||
1265 | if (next.valid) { | |
1266 | ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0); | |
1267 | if (ret < 0) | |
1268 | return ret; | |
1269 | ||
1270 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1271 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1272 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1273 | GLOBAL_VTU_FID); | |
1274 | if (ret < 0) | |
1275 | return ret; | |
1276 | ||
1277 | next.fid = ret & GLOBAL_VTU_FID_MASK; | |
1278 | ||
1279 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, | |
1280 | GLOBAL_VTU_SID); | |
1281 | if (ret < 0) | |
1282 | return ret; | |
1283 | ||
1284 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | *entry = next; | |
1289 | return 0; | |
1290 | } | |
1291 | ||
7dad08d7 VD |
1292 | static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds, |
1293 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1294 | { | |
1295 | u16 reg = 0; | |
1296 | int ret; | |
1297 | ||
1298 | ret = _mv88e6xxx_vtu_wait(ds); | |
1299 | if (ret < 0) | |
1300 | return ret; | |
1301 | ||
1302 | if (!entry->valid) | |
1303 | goto loadpurge; | |
1304 | ||
1305 | /* Write port member tags */ | |
1306 | ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0); | |
1307 | if (ret < 0) | |
1308 | return ret; | |
1309 | ||
1310 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1311 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1312 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
1313 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg); | |
1314 | if (ret < 0) | |
1315 | return ret; | |
1316 | ||
1317 | reg = entry->fid & GLOBAL_VTU_FID_MASK; | |
1318 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg); | |
1319 | if (ret < 0) | |
1320 | return ret; | |
1321 | } | |
1322 | ||
1323 | reg = GLOBAL_VTU_VID_VALID; | |
1324 | loadpurge: | |
1325 | reg |= entry->vid & GLOBAL_VTU_VID_MASK; | |
1326 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg); | |
1327 | if (ret < 0) | |
1328 | return ret; | |
1329 | ||
1330 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE); | |
1331 | } | |
1332 | ||
0d3b33e6 VD |
1333 | static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid, |
1334 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1335 | { | |
1336 | struct mv88e6xxx_vtu_stu_entry next = { 0 }; | |
1337 | int ret; | |
1338 | ||
1339 | ret = _mv88e6xxx_vtu_wait(ds); | |
1340 | if (ret < 0) | |
1341 | return ret; | |
1342 | ||
1343 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, | |
1344 | sid & GLOBAL_VTU_SID_MASK); | |
1345 | if (ret < 0) | |
1346 | return ret; | |
1347 | ||
1348 | ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT); | |
1349 | if (ret < 0) | |
1350 | return ret; | |
1351 | ||
1352 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID); | |
1353 | if (ret < 0) | |
1354 | return ret; | |
1355 | ||
1356 | next.sid = ret & GLOBAL_VTU_SID_MASK; | |
1357 | ||
1358 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID); | |
1359 | if (ret < 0) | |
1360 | return ret; | |
1361 | ||
1362 | next.valid = !!(ret & GLOBAL_VTU_VID_VALID); | |
1363 | ||
1364 | if (next.valid) { | |
1365 | ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2); | |
1366 | if (ret < 0) | |
1367 | return ret; | |
1368 | } | |
1369 | ||
1370 | *entry = next; | |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds, | |
1375 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1376 | { | |
1377 | u16 reg = 0; | |
1378 | int ret; | |
1379 | ||
1380 | ret = _mv88e6xxx_vtu_wait(ds); | |
1381 | if (ret < 0) | |
1382 | return ret; | |
1383 | ||
1384 | if (!entry->valid) | |
1385 | goto loadpurge; | |
1386 | ||
1387 | /* Write port states */ | |
1388 | ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2); | |
1389 | if (ret < 0) | |
1390 | return ret; | |
1391 | ||
1392 | reg = GLOBAL_VTU_VID_VALID; | |
1393 | loadpurge: | |
1394 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg); | |
1395 | if (ret < 0) | |
1396 | return ret; | |
1397 | ||
1398 | reg = entry->sid & GLOBAL_VTU_SID_MASK; | |
1399 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg); | |
1400 | if (ret < 0) | |
1401 | return ret; | |
1402 | ||
1403 | return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE); | |
1404 | } | |
1405 | ||
1406 | static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid, | |
1407 | struct mv88e6xxx_vtu_stu_entry *entry) | |
1408 | { | |
1409 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1410 | struct mv88e6xxx_vtu_stu_entry vlan = { | |
1411 | .valid = true, | |
1412 | .vid = vid, | |
f02bdffc | 1413 | .fid = vid, /* We use one FID per VLAN */ |
0d3b33e6 VD |
1414 | }; |
1415 | int i; | |
1416 | ||
1417 | /* exclude all ports except the CPU */ | |
1418 | for (i = 0; i < ps->num_ports; ++i) | |
1419 | vlan.data[i] = dsa_is_cpu_port(ds, i) ? | |
1420 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED : | |
1421 | GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1422 | ||
1423 | if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) || | |
1424 | mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) { | |
1425 | struct mv88e6xxx_vtu_stu_entry vstp; | |
1426 | int err; | |
1427 | ||
1428 | /* Adding a VTU entry requires a valid STU entry. As VSTP is not | |
1429 | * implemented, only one STU entry is needed to cover all VTU | |
1430 | * entries. Thus, validate the SID 0. | |
1431 | */ | |
1432 | vlan.sid = 0; | |
1433 | err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp); | |
1434 | if (err) | |
1435 | return err; | |
1436 | ||
1437 | if (vstp.sid != vlan.sid || !vstp.valid) { | |
1438 | memset(&vstp, 0, sizeof(vstp)); | |
1439 | vstp.valid = true; | |
1440 | vstp.sid = vlan.sid; | |
1441 | ||
1442 | err = _mv88e6xxx_stu_loadpurge(ds, &vstp); | |
1443 | if (err) | |
1444 | return err; | |
1445 | } | |
1446 | ||
7c400018 VD |
1447 | /* Clear all MAC addresses from the new database */ |
1448 | err = _mv88e6xxx_atu_flush(ds, vlan.fid, true); | |
0d3b33e6 VD |
1449 | if (err) |
1450 | return err; | |
0d3b33e6 VD |
1451 | } |
1452 | ||
1453 | *entry = vlan; | |
1454 | return 0; | |
1455 | } | |
1456 | ||
76e398a6 VD |
1457 | int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
1458 | const struct switchdev_obj_port_vlan *vlan, | |
1459 | struct switchdev_trans *trans) | |
1460 | { | |
1461 | /* We don't need any dynamic resource from the kernel (yet), | |
1462 | * so skip the prepare phase. | |
1463 | */ | |
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid, | |
1468 | bool untagged) | |
0d3b33e6 | 1469 | { |
0d3b33e6 VD |
1470 | struct mv88e6xxx_vtu_stu_entry vlan; |
1471 | int err; | |
1472 | ||
36d04ba1 VD |
1473 | err = _mv88e6xxx_vtu_vid_write(ds, vid - 1); |
1474 | if (err) | |
76e398a6 | 1475 | return err; |
36d04ba1 VD |
1476 | |
1477 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
0d3b33e6 | 1478 | if (err) |
76e398a6 | 1479 | return err; |
0d3b33e6 VD |
1480 | |
1481 | if (vlan.vid != vid || !vlan.valid) { | |
1482 | err = _mv88e6xxx_vlan_init(ds, vid, &vlan); | |
1483 | if (err) | |
76e398a6 | 1484 | return err; |
0d3b33e6 VD |
1485 | } |
1486 | ||
1487 | vlan.data[port] = untagged ? | |
1488 | GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : | |
1489 | GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; | |
1490 | ||
76e398a6 VD |
1491 | return _mv88e6xxx_vtu_loadpurge(ds, &vlan); |
1492 | } | |
1493 | ||
1494 | int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, | |
1495 | const struct switchdev_obj_port_vlan *vlan, | |
1496 | struct switchdev_trans *trans) | |
1497 | { | |
1498 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1499 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; | |
1500 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
1501 | u16 vid; | |
1502 | int err = 0; | |
1503 | ||
1504 | mutex_lock(&ps->smi_mutex); | |
1505 | ||
1506 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { | |
1507 | err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged); | |
1508 | if (err) | |
1509 | goto unlock; | |
1510 | } | |
1511 | ||
1512 | /* no PVID with ranges, otherwise it's a bug */ | |
1513 | if (pvid) | |
1514 | err = _mv88e6xxx_port_pvid_set(ds, port, vid); | |
0d3b33e6 VD |
1515 | unlock: |
1516 | mutex_unlock(&ps->smi_mutex); | |
1517 | ||
1518 | return err; | |
1519 | } | |
1520 | ||
76e398a6 | 1521 | static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid) |
7dad08d7 VD |
1522 | { |
1523 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1524 | struct mv88e6xxx_vtu_stu_entry vlan; | |
7dad08d7 VD |
1525 | int i, err; |
1526 | ||
36d04ba1 VD |
1527 | err = _mv88e6xxx_vtu_vid_write(ds, vid - 1); |
1528 | if (err) | |
76e398a6 | 1529 | return err; |
36d04ba1 VD |
1530 | |
1531 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
7dad08d7 | 1532 | if (err) |
76e398a6 | 1533 | return err; |
7dad08d7 VD |
1534 | |
1535 | if (vlan.vid != vid || !vlan.valid || | |
76e398a6 VD |
1536 | vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
1537 | return -ENOENT; | |
7dad08d7 VD |
1538 | |
1539 | vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; | |
1540 | ||
1541 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 1542 | vlan.valid = false; |
7dad08d7 VD |
1543 | for (i = 0; i < ps->num_ports; ++i) { |
1544 | if (dsa_is_cpu_port(ds, i)) | |
1545 | continue; | |
1546 | ||
1547 | if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 1548 | vlan.valid = true; |
7dad08d7 VD |
1549 | break; |
1550 | } | |
1551 | } | |
1552 | ||
7dad08d7 | 1553 | err = _mv88e6xxx_vtu_loadpurge(ds, &vlan); |
76e398a6 VD |
1554 | if (err) |
1555 | return err; | |
1556 | ||
1557 | return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false); | |
1558 | } | |
1559 | ||
1560 | int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, | |
1561 | const struct switchdev_obj_port_vlan *vlan) | |
1562 | { | |
1563 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1564 | u16 pvid, vid; | |
1565 | int err = 0; | |
1566 | ||
1567 | mutex_lock(&ps->smi_mutex); | |
1568 | ||
1569 | err = _mv88e6xxx_port_pvid_get(ds, port, &pvid); | |
7dad08d7 VD |
1570 | if (err) |
1571 | goto unlock; | |
1572 | ||
76e398a6 VD |
1573 | for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { |
1574 | err = _mv88e6xxx_port_vlan_del(ds, port, vid); | |
1575 | if (err) | |
1576 | goto unlock; | |
1577 | ||
1578 | if (vid == pvid) { | |
1579 | err = _mv88e6xxx_port_pvid_set(ds, port, 0); | |
1580 | if (err) | |
1581 | goto unlock; | |
1582 | } | |
1583 | } | |
1584 | ||
7dad08d7 VD |
1585 | unlock: |
1586 | mutex_unlock(&ps->smi_mutex); | |
1587 | ||
1588 | return err; | |
1589 | } | |
1590 | ||
b8fee957 VD |
1591 | int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid, |
1592 | unsigned long *ports, unsigned long *untagged) | |
1593 | { | |
1594 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1595 | struct mv88e6xxx_vtu_stu_entry next; | |
1596 | int port; | |
1597 | int err; | |
1598 | ||
1599 | if (*vid == 4095) | |
1600 | return -ENOENT; | |
1601 | ||
1602 | mutex_lock(&ps->smi_mutex); | |
36d04ba1 VD |
1603 | err = _mv88e6xxx_vtu_vid_write(ds, *vid); |
1604 | if (err) | |
1605 | goto unlock; | |
1606 | ||
1607 | err = _mv88e6xxx_vtu_getnext(ds, &next); | |
1608 | unlock: | |
b8fee957 VD |
1609 | mutex_unlock(&ps->smi_mutex); |
1610 | ||
1611 | if (err) | |
1612 | return err; | |
1613 | ||
1614 | if (!next.valid) | |
1615 | return -ENOENT; | |
1616 | ||
1617 | *vid = next.vid; | |
1618 | ||
1619 | for (port = 0; port < ps->num_ports; ++port) { | |
1620 | clear_bit(port, ports); | |
1621 | clear_bit(port, untagged); | |
1622 | ||
1623 | if (dsa_is_cpu_port(ds, port)) | |
1624 | continue; | |
1625 | ||
1626 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED || | |
1627 | next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1628 | set_bit(port, ports); | |
1629 | ||
1630 | if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) | |
1631 | set_bit(port, untagged); | |
1632 | } | |
1633 | ||
1634 | return 0; | |
1635 | } | |
1636 | ||
c5723ac5 VD |
1637 | static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds, |
1638 | const unsigned char *addr) | |
defb05b9 GR |
1639 | { |
1640 | int i, ret; | |
1641 | ||
1642 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1643 | ret = _mv88e6xxx_reg_write( |
1644 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1645 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1646 | if (ret < 0) |
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
c5723ac5 | 1653 | static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr) |
defb05b9 GR |
1654 | { |
1655 | int i, ret; | |
1656 | ||
1657 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1658 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1659 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1660 | if (ret < 0) |
1661 | return ret; | |
1662 | addr[i * 2] = ret >> 8; | |
1663 | addr[i * 2 + 1] = ret & 0xff; | |
1664 | } | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | ||
fd231c82 VD |
1669 | static int _mv88e6xxx_atu_load(struct dsa_switch *ds, |
1670 | struct mv88e6xxx_atu_entry *entry) | |
defb05b9 | 1671 | { |
6630e236 VD |
1672 | int ret; |
1673 | ||
defb05b9 GR |
1674 | ret = _mv88e6xxx_atu_wait(ds); |
1675 | if (ret < 0) | |
1676 | return ret; | |
1677 | ||
fd231c82 | 1678 | ret = _mv88e6xxx_atu_mac_write(ds, entry->mac); |
defb05b9 GR |
1679 | if (ret < 0) |
1680 | return ret; | |
1681 | ||
37705b73 | 1682 | ret = _mv88e6xxx_atu_data_write(ds, entry); |
fd231c82 | 1683 | if (ret < 0) |
87820510 VD |
1684 | return ret; |
1685 | ||
70cc99d1 VD |
1686 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid); |
1687 | if (ret < 0) | |
1688 | return ret; | |
1689 | ||
1690 | return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB); | |
fd231c82 | 1691 | } |
87820510 | 1692 | |
fd231c82 VD |
1693 | static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port, |
1694 | const unsigned char *addr, u16 vid, | |
1695 | u8 state) | |
1696 | { | |
1697 | struct mv88e6xxx_atu_entry entry = { 0 }; | |
fd231c82 | 1698 | |
f02bdffc | 1699 | entry.fid = vid; /* We use one FID per VLAN */ |
fd231c82 VD |
1700 | entry.state = state; |
1701 | ether_addr_copy(entry.mac, addr); | |
1702 | if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1703 | entry.trunk = false; | |
1704 | entry.portv_trunkid = BIT(port); | |
1705 | } | |
1706 | ||
1707 | return _mv88e6xxx_atu_load(ds, &entry); | |
87820510 VD |
1708 | } |
1709 | ||
146a3206 VD |
1710 | int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
1711 | const struct switchdev_obj_port_fdb *fdb, | |
1712 | struct switchdev_trans *trans) | |
1713 | { | |
f02bdffc VD |
1714 | /* We don't use per-port FDB */ |
1715 | if (fdb->vid == 0) | |
1716 | return -EOPNOTSUPP; | |
1717 | ||
146a3206 VD |
1718 | /* We don't need any dynamic resource from the kernel (yet), |
1719 | * so skip the prepare phase. | |
1720 | */ | |
1721 | return 0; | |
1722 | } | |
1723 | ||
cdf09697 | 1724 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1f36faf2 VD |
1725 | const struct switchdev_obj_port_fdb *fdb, |
1726 | struct switchdev_trans *trans) | |
87820510 | 1727 | { |
1f36faf2 | 1728 | int state = is_multicast_ether_addr(fdb->addr) ? |
87820510 VD |
1729 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1730 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
cdf09697 | 1731 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
87820510 VD |
1732 | int ret; |
1733 | ||
1734 | mutex_lock(&ps->smi_mutex); | |
1f36faf2 | 1735 | ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state); |
87820510 VD |
1736 | mutex_unlock(&ps->smi_mutex); |
1737 | ||
1738 | return ret; | |
1739 | } | |
1740 | ||
cdf09697 | 1741 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
8057b3e7 | 1742 | const struct switchdev_obj_port_fdb *fdb) |
87820510 VD |
1743 | { |
1744 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87820510 VD |
1745 | int ret; |
1746 | ||
1747 | mutex_lock(&ps->smi_mutex); | |
8057b3e7 | 1748 | ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, |
cdf09697 | 1749 | GLOBAL_ATU_DATA_STATE_UNUSED); |
87820510 VD |
1750 | mutex_unlock(&ps->smi_mutex); |
1751 | ||
1752 | return ret; | |
1753 | } | |
1754 | ||
1d194046 | 1755 | static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid, |
1d194046 | 1756 | struct mv88e6xxx_atu_entry *entry) |
6630e236 | 1757 | { |
1d194046 VD |
1758 | struct mv88e6xxx_atu_entry next = { 0 }; |
1759 | int ret; | |
1760 | ||
1761 | next.fid = fid; | |
defb05b9 | 1762 | |
cdf09697 DM |
1763 | ret = _mv88e6xxx_atu_wait(ds); |
1764 | if (ret < 0) | |
1765 | return ret; | |
6630e236 | 1766 | |
70cc99d1 VD |
1767 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid); |
1768 | if (ret < 0) | |
1769 | return ret; | |
1770 | ||
1771 | ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB); | |
1d194046 VD |
1772 | if (ret < 0) |
1773 | return ret; | |
6630e236 | 1774 | |
1d194046 VD |
1775 | ret = _mv88e6xxx_atu_mac_read(ds, next.mac); |
1776 | if (ret < 0) | |
1777 | return ret; | |
6630e236 | 1778 | |
1d194046 | 1779 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
cdf09697 DM |
1780 | if (ret < 0) |
1781 | return ret; | |
6630e236 | 1782 | |
1d194046 VD |
1783 | next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1784 | if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { | |
1785 | unsigned int mask, shift; | |
1786 | ||
1787 | if (ret & GLOBAL_ATU_DATA_TRUNK) { | |
1788 | next.trunk = true; | |
1789 | mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; | |
1790 | shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; | |
1791 | } else { | |
1792 | next.trunk = false; | |
1793 | mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; | |
1794 | shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; | |
1795 | } | |
1796 | ||
1797 | next.portv_trunkid = (ret & mask) >> shift; | |
1798 | } | |
cdf09697 | 1799 | |
1d194046 | 1800 | *entry = next; |
cdf09697 DM |
1801 | return 0; |
1802 | } | |
1803 | ||
f33475bd VD |
1804 | int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
1805 | struct switchdev_obj_port_fdb *fdb, | |
1806 | int (*cb)(struct switchdev_obj *obj)) | |
1807 | { | |
1808 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1809 | struct mv88e6xxx_vtu_stu_entry vlan = { | |
1810 | .vid = GLOBAL_VTU_VID_MASK, /* all ones */ | |
1811 | }; | |
1812 | int err; | |
1813 | ||
1814 | mutex_lock(&ps->smi_mutex); | |
1815 | ||
1816 | err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid); | |
1817 | if (err) | |
1818 | goto unlock; | |
1819 | ||
1820 | do { | |
1821 | struct mv88e6xxx_atu_entry addr = { | |
1822 | .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, | |
1823 | }; | |
1824 | ||
1825 | err = _mv88e6xxx_vtu_getnext(ds, &vlan); | |
1826 | if (err) | |
1827 | goto unlock; | |
1828 | ||
1829 | if (!vlan.valid) | |
1830 | break; | |
1831 | ||
1832 | err = _mv88e6xxx_atu_mac_write(ds, addr.mac); | |
1833 | if (err) | |
1834 | goto unlock; | |
1835 | ||
1836 | do { | |
1837 | err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr); | |
1838 | if (err) | |
1839 | goto unlock; | |
1840 | ||
1841 | if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
1842 | break; | |
1843 | ||
1844 | if (!addr.trunk && addr.portv_trunkid & BIT(port)) { | |
1845 | bool is_static = addr.state == | |
1846 | (is_multicast_ether_addr(addr.mac) ? | |
1847 | GLOBAL_ATU_DATA_STATE_MC_STATIC : | |
1848 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
1849 | ||
1850 | fdb->vid = vlan.vid; | |
1851 | ether_addr_copy(fdb->addr, addr.mac); | |
1852 | fdb->ndm_state = is_static ? NUD_NOARP : | |
1853 | NUD_REACHABLE; | |
1854 | ||
1855 | err = cb(&fdb->obj); | |
1856 | if (err) | |
1857 | goto unlock; | |
1858 | } | |
1859 | } while (!is_broadcast_ether_addr(addr.mac)); | |
1860 | ||
1861 | } while (vlan.vid < GLOBAL_VTU_VID_MASK); | |
1862 | ||
1863 | unlock: | |
1864 | mutex_unlock(&ps->smi_mutex); | |
1865 | ||
1866 | return err; | |
1867 | } | |
1868 | ||
facd95b2 GR |
1869 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1870 | { | |
1871 | struct mv88e6xxx_priv_state *ps; | |
1872 | struct dsa_switch *ds; | |
1873 | int port; | |
1874 | ||
1875 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1876 | ds = ((struct dsa_switch *)ps) - 1; | |
1877 | ||
1878 | while (ps->port_state_update_mask) { | |
1879 | port = __ffs(ps->port_state_update_mask); | |
1880 | clear_bit(port, &ps->port_state_update_mask); | |
1881 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1882 | } | |
1883 | } | |
1884 | ||
dbde9e66 | 1885 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1886 | { |
1887 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
f02bdffc | 1888 | int ret; |
54d792f2 | 1889 | u16 reg; |
d827e88a GR |
1890 | |
1891 | mutex_lock(&ps->smi_mutex); | |
1892 | ||
54d792f2 AL |
1893 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1894 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1895 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
7c3d0d67 | 1896 | mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1897 | /* MAC Forcing register: don't force link, speed, |
1898 | * duplex or flow control state to any particular | |
1899 | * values on physical ports, but force the CPU port | |
1900 | * and all DSA ports to their maximum bandwidth and | |
1901 | * full duplex. | |
1902 | */ | |
1903 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
60045cbf | 1904 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
53adc9e8 | 1905 | reg &= ~PORT_PCS_CTRL_UNFORCED; |
54d792f2 AL |
1906 | reg |= PORT_PCS_CTRL_FORCE_LINK | |
1907 | PORT_PCS_CTRL_LINK_UP | | |
1908 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1909 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1910 | if (mv88e6xxx_6065_family(ds)) | |
1911 | reg |= PORT_PCS_CTRL_100; | |
1912 | else | |
1913 | reg |= PORT_PCS_CTRL_1000; | |
1914 | } else { | |
1915 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1916 | } | |
1917 | ||
1918 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1919 | PORT_PCS_CTRL, reg); | |
1920 | if (ret) | |
1921 | goto abort; | |
1922 | } | |
1923 | ||
1924 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1925 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1926 | * tunneling, determine priority by looking at 802.1p and IP | |
1927 | * priority fields (IP prio has precedence), and set STP state | |
1928 | * to Forwarding. | |
1929 | * | |
1930 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1931 | * on which tagging mode was configured. | |
1932 | * | |
1933 | * If this is a link to another switch, use DSA tagging mode. | |
1934 | * | |
1935 | * If this is the upstream port for this switch, enable | |
1936 | * forwarding of unknown unicasts and multicasts. | |
1937 | */ | |
1938 | reg = 0; | |
1939 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1940 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1941 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1942 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1943 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | |
1944 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1945 | PORT_CONTROL_STATE_FORWARDING; | |
1946 | if (dsa_is_cpu_port(ds, port)) { | |
1947 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1948 | reg |= PORT_CONTROL_DSA_TAG; | |
1949 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
1950 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
1951 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
1952 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1953 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1954 | else | |
1955 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
c047a1f9 AL |
1956 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | |
1957 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
54d792f2 AL |
1958 | } |
1959 | ||
1960 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1961 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1962 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
7c3d0d67 | 1963 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) { |
54d792f2 AL |
1964 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) |
1965 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1966 | } | |
1967 | } | |
6083ce71 AL |
1968 | if (dsa_is_dsa_port(ds, port)) { |
1969 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1970 | reg |= PORT_CONTROL_DSA_TAG; | |
1971 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1972 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1973 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 | 1974 | reg |= PORT_CONTROL_FRAME_MODE_DSA; |
6083ce71 AL |
1975 | } |
1976 | ||
54d792f2 AL |
1977 | if (port == dsa_upstream_port(ds)) |
1978 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1979 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1980 | } | |
1981 | if (reg) { | |
1982 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1983 | PORT_CONTROL, reg); | |
1984 | if (ret) | |
1985 | goto abort; | |
1986 | } | |
1987 | ||
8efdda4a VD |
1988 | /* Port Control 2: don't force a good FCS, set the maximum frame size to |
1989 | * 10240 bytes, enable secure 802.1q tags, don't discard tagged or | |
1990 | * untagged frames on this port, do a destination address lookup on all | |
1991 | * received packets as usual, disable ARP mirroring and don't send a | |
1992 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 AL |
1993 | */ |
1994 | reg = 0; | |
1995 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1996 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 | 1997 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
1998 | reg = PORT_CONTROL_2_MAP_DA; |
1999 | ||
2000 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 | 2001 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds)) |
54d792f2 AL |
2002 | reg |= PORT_CONTROL_2_JUMBO_10240; |
2003 | ||
2004 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
2005 | /* Set the upstream port this port should use */ | |
2006 | reg |= dsa_upstream_port(ds); | |
2007 | /* enable forwarding of unknown multicast addresses to | |
2008 | * the upstream port | |
2009 | */ | |
2010 | if (port == dsa_upstream_port(ds)) | |
2011 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
2012 | } | |
2013 | ||
5fe7f680 | 2014 | reg |= PORT_CONTROL_2_8021Q_SECURE; |
8efdda4a | 2015 | |
54d792f2 AL |
2016 | if (reg) { |
2017 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2018 | PORT_CONTROL_2, reg); | |
2019 | if (ret) | |
2020 | goto abort; | |
2021 | } | |
2022 | ||
2023 | /* Port Association Vector: when learning source addresses | |
2024 | * of packets, add the address to the address database using | |
2025 | * a port bitmap that has only the bit for this port set and | |
2026 | * the other bits clear. | |
2027 | */ | |
2028 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, | |
2029 | 1 << port); | |
2030 | if (ret) | |
2031 | goto abort; | |
2032 | ||
2033 | /* Egress rate control 2: disable egress rate control. */ | |
2034 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
2035 | 0x0000); | |
2036 | if (ret) | |
2037 | goto abort; | |
2038 | ||
2039 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
2040 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
2041 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2042 | /* Do not limit the period of time that this port can |
2043 | * be paused for by the remote end or the period of | |
2044 | * time that this port can pause the remote end. | |
2045 | */ | |
2046 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2047 | PORT_PAUSE_CTRL, 0x0000); | |
2048 | if (ret) | |
2049 | goto abort; | |
2050 | ||
2051 | /* Port ATU control: disable limiting the number of | |
2052 | * address database entries that this port is allowed | |
2053 | * to use. | |
2054 | */ | |
2055 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2056 | PORT_ATU_CONTROL, 0x0000); | |
2057 | /* Priority Override: disable DA, SA and VTU priority | |
2058 | * override. | |
2059 | */ | |
2060 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2061 | PORT_PRI_OVERRIDE, 0x0000); | |
2062 | if (ret) | |
2063 | goto abort; | |
2064 | ||
2065 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
2066 | * value. | |
2067 | */ | |
2068 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2069 | PORT_ETH_TYPE, ETH_P_EDSA); | |
2070 | if (ret) | |
2071 | goto abort; | |
2072 | /* Tag Remap: use an identity 802.1p prio -> switch | |
2073 | * prio mapping. | |
2074 | */ | |
2075 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2076 | PORT_TAG_REGMAP_0123, 0x3210); | |
2077 | if (ret) | |
2078 | goto abort; | |
2079 | ||
2080 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
2081 | * prio mapping. | |
2082 | */ | |
2083 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2084 | PORT_TAG_REGMAP_4567, 0x7654); | |
2085 | if (ret) | |
2086 | goto abort; | |
2087 | } | |
2088 | ||
2089 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
2090 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
2091 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
2092 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2093 | /* Rate Control: disable ingress rate limiting. */ |
2094 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
2095 | PORT_RATE_CONTROL, 0x0001); | |
2096 | if (ret) | |
2097 | goto abort; | |
2098 | } | |
2099 | ||
366f0a0f GR |
2100 | /* Port Control 1: disable trunking, disable sending |
2101 | * learning messages to this port. | |
d827e88a | 2102 | */ |
614f03fc | 2103 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
2104 | if (ret) |
2105 | goto abort; | |
2106 | ||
f02bdffc | 2107 | /* Port based VLAN map: do not give each port its own address |
5fe7f680 | 2108 | * database, and allow every port to egress frames on all other ports. |
d827e88a | 2109 | */ |
5fe7f680 | 2110 | reg = BIT(ps->num_ports) - 1; /* all ports */ |
ede8098d | 2111 | ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port); |
d827e88a GR |
2112 | if (ret) |
2113 | goto abort; | |
2114 | ||
2115 | /* Default VLAN ID and priority: don't set a default VLAN | |
2116 | * ID, and set the default packet priority to zero. | |
2117 | */ | |
47cf1e65 VD |
2118 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
2119 | 0x0000); | |
d827e88a GR |
2120 | abort: |
2121 | mutex_unlock(&ps->smi_mutex); | |
2122 | return ret; | |
2123 | } | |
2124 | ||
dbde9e66 AL |
2125 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
2126 | { | |
2127 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2128 | int ret; | |
2129 | int i; | |
2130 | ||
2131 | for (i = 0; i < ps->num_ports; i++) { | |
2132 | ret = mv88e6xxx_setup_port(ds, i); | |
2133 | if (ret < 0) | |
2134 | return ret; | |
2135 | } | |
2136 | return 0; | |
2137 | } | |
2138 | ||
acdaffcc GR |
2139 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
2140 | { | |
2141 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2142 | ||
2143 | mutex_init(&ps->smi_mutex); | |
acdaffcc | 2144 | |
cca8b133 | 2145 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 2146 | |
facd95b2 GR |
2147 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); |
2148 | ||
acdaffcc GR |
2149 | return 0; |
2150 | } | |
2151 | ||
54d792f2 AL |
2152 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
2153 | { | |
2154 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
24751e29 | 2155 | int ret; |
54d792f2 AL |
2156 | int i; |
2157 | ||
2158 | /* Set the default address aging time to 5 minutes, and | |
2159 | * enable address learn messages to be sent to all message | |
2160 | * ports. | |
2161 | */ | |
2162 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
2163 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
2164 | ||
2165 | /* Configure the IP ToS mapping registers. */ | |
2166 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
2167 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
2168 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
2169 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
2170 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
2171 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
2172 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
2173 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
2174 | ||
2175 | /* Configure the IEEE 802.1p priority mapping register. */ | |
2176 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
2177 | ||
2178 | /* Send all frames with destination addresses matching | |
2179 | * 01:80:c2:00:00:0x to the CPU port. | |
2180 | */ | |
2181 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
2182 | ||
2183 | /* Ignore removed tag data on doubly tagged packets, disable | |
2184 | * flow control messages, force flow control priority to the | |
2185 | * highest, and send all special multicast frames to the CPU | |
2186 | * port at the highest priority. | |
2187 | */ | |
2188 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
2189 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
2190 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
2191 | ||
2192 | /* Program the DSA routing table. */ | |
2193 | for (i = 0; i < 32; i++) { | |
2194 | int nexthop = 0x1f; | |
2195 | ||
2196 | if (ds->pd->rtable && | |
2197 | i != ds->index && i < ds->dst->pd->nr_chips) | |
2198 | nexthop = ds->pd->rtable[i] & 0x1f; | |
2199 | ||
2200 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
2201 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
2202 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
2203 | nexthop); | |
2204 | } | |
2205 | ||
2206 | /* Clear all trunk masks. */ | |
2207 | for (i = 0; i < 8; i++) | |
2208 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
2209 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
2210 | ((1 << ps->num_ports) - 1)); | |
2211 | ||
2212 | /* Clear all trunk mappings. */ | |
2213 | for (i = 0; i < 16; i++) | |
2214 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
2215 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
2216 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
2217 | ||
2218 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
7c3d0d67 AK |
2219 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || |
2220 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2221 | /* Send all frames with destination addresses matching |
2222 | * 01:80:c2:00:00:2x to the CPU port. | |
2223 | */ | |
2224 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
2225 | ||
2226 | /* Initialise cross-chip port VLAN table to reset | |
2227 | * defaults. | |
2228 | */ | |
2229 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
2230 | ||
2231 | /* Clear the priority override table. */ | |
2232 | for (i = 0; i < 16; i++) | |
2233 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
2234 | 0x8000 | (i << 8)); | |
2235 | } | |
2236 | ||
2237 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
2238 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
7c3d0d67 AK |
2239 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || |
2240 | mv88e6xxx_6320_family(ds)) { | |
54d792f2 AL |
2241 | /* Disable ingress rate limiting by resetting all |
2242 | * ingress rate limit registers to their initial | |
2243 | * state. | |
2244 | */ | |
2245 | for (i = 0; i < ps->num_ports; i++) | |
2246 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
2247 | 0x9000 | (i << 8)); | |
2248 | } | |
2249 | ||
db687a56 AL |
2250 | /* Clear the statistics counters for all ports */ |
2251 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); | |
2252 | ||
2253 | /* Wait for the flush to complete. */ | |
24751e29 VD |
2254 | mutex_lock(&ps->smi_mutex); |
2255 | ret = _mv88e6xxx_stats_wait(ds); | |
6b17e864 VD |
2256 | if (ret < 0) |
2257 | goto unlock; | |
2258 | ||
c161d0a5 VD |
2259 | /* Clear all ATU entries */ |
2260 | ret = _mv88e6xxx_atu_flush(ds, 0, true); | |
2261 | if (ret < 0) | |
2262 | goto unlock; | |
2263 | ||
6b17e864 VD |
2264 | /* Clear all the VTU and STU entries */ |
2265 | ret = _mv88e6xxx_vtu_stu_flush(ds); | |
2266 | unlock: | |
24751e29 | 2267 | mutex_unlock(&ps->smi_mutex); |
db687a56 | 2268 | |
24751e29 | 2269 | return ret; |
54d792f2 AL |
2270 | } |
2271 | ||
143a8307 AL |
2272 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
2273 | { | |
2274 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2275 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
2276 | unsigned long timeout; | |
2277 | int ret; | |
2278 | int i; | |
2279 | ||
2280 | /* Set all ports to the disabled state. */ | |
2281 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
2282 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
2283 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
2284 | } |
2285 | ||
2286 | /* Wait for transmit queues to drain. */ | |
2287 | usleep_range(2000, 4000); | |
2288 | ||
2289 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2290 | * needs to be active to support indirect phy register access | |
2291 | * through global registers 0x18 and 0x19. | |
2292 | */ | |
2293 | if (ppu_active) | |
2294 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
2295 | else | |
2296 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
2297 | ||
2298 | /* Wait up to one second for reset to complete. */ | |
2299 | timeout = jiffies + 1 * HZ; | |
2300 | while (time_before(jiffies, timeout)) { | |
2301 | ret = REG_READ(REG_GLOBAL, 0x00); | |
2302 | if ((ret & is_reset) == is_reset) | |
2303 | break; | |
2304 | usleep_range(1000, 2000); | |
2305 | } | |
2306 | if (time_after(jiffies, timeout)) | |
2307 | return -ETIMEDOUT; | |
2308 | ||
2309 | return 0; | |
2310 | } | |
2311 | ||
49143585 AL |
2312 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
2313 | { | |
2314 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2315 | int ret; | |
2316 | ||
3898c148 | 2317 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2318 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2319 | if (ret < 0) |
2320 | goto error; | |
fd3a0ee4 | 2321 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 2322 | error: |
fd3a0ee4 | 2323 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2324 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2325 | return ret; |
2326 | } | |
2327 | ||
2328 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
2329 | int reg, int val) | |
2330 | { | |
2331 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2332 | int ret; | |
2333 | ||
3898c148 | 2334 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2335 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2336 | if (ret < 0) |
2337 | goto error; | |
2338 | ||
fd3a0ee4 | 2339 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 2340 | error: |
fd3a0ee4 | 2341 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2342 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2343 | return ret; |
2344 | } | |
2345 | ||
2346 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
2347 | { | |
2348 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2349 | ||
2350 | if (port >= 0 && port < ps->num_ports) | |
2351 | return port; | |
2352 | return -EINVAL; | |
2353 | } | |
2354 | ||
2355 | int | |
2356 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
2357 | { | |
2358 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2359 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2360 | int ret; | |
2361 | ||
2362 | if (addr < 0) | |
2363 | return addr; | |
2364 | ||
3898c148 | 2365 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2366 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 2367 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2368 | return ret; |
2369 | } | |
2370 | ||
2371 | int | |
2372 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
2373 | { | |
2374 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2375 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2376 | int ret; | |
2377 | ||
2378 | if (addr < 0) | |
2379 | return addr; | |
2380 | ||
3898c148 | 2381 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2382 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 2383 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2384 | return ret; |
2385 | } | |
2386 | ||
2387 | int | |
2388 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
2389 | { | |
2390 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2391 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2392 | int ret; | |
2393 | ||
2394 | if (addr < 0) | |
2395 | return addr; | |
2396 | ||
3898c148 | 2397 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2398 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 2399 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2400 | return ret; |
2401 | } | |
2402 | ||
2403 | int | |
2404 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
2405 | u16 val) | |
2406 | { | |
2407 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2408 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2409 | int ret; | |
2410 | ||
2411 | if (addr < 0) | |
2412 | return addr; | |
2413 | ||
3898c148 | 2414 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2415 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 2416 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2417 | return ret; |
2418 | } | |
2419 | ||
c22995c5 GR |
2420 | #ifdef CONFIG_NET_DSA_HWMON |
2421 | ||
2422 | static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) | |
2423 | { | |
2424 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2425 | int ret; | |
2426 | int val; | |
2427 | ||
2428 | *temp = 0; | |
2429 | ||
2430 | mutex_lock(&ps->smi_mutex); | |
2431 | ||
2432 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); | |
2433 | if (ret < 0) | |
2434 | goto error; | |
2435 | ||
2436 | /* Enable temperature sensor */ | |
2437 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2438 | if (ret < 0) | |
2439 | goto error; | |
2440 | ||
2441 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); | |
2442 | if (ret < 0) | |
2443 | goto error; | |
2444 | ||
2445 | /* Wait for temperature to stabilize */ | |
2446 | usleep_range(10000, 12000); | |
2447 | ||
2448 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); | |
2449 | if (val < 0) { | |
2450 | ret = val; | |
2451 | goto error; | |
2452 | } | |
2453 | ||
2454 | /* Disable temperature sensor */ | |
2455 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); | |
2456 | if (ret < 0) | |
2457 | goto error; | |
2458 | ||
2459 | *temp = ((val & 0x1f) - 5) * 5; | |
2460 | ||
2461 | error: | |
2462 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); | |
2463 | mutex_unlock(&ps->smi_mutex); | |
2464 | return ret; | |
2465 | } | |
2466 | ||
2467 | static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) | |
2468 | { | |
2469 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2470 | int ret; | |
2471 | ||
2472 | *temp = 0; | |
2473 | ||
2474 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27); | |
2475 | if (ret < 0) | |
2476 | return ret; | |
2477 | ||
2478 | *temp = (ret & 0xff) - 25; | |
2479 | ||
2480 | return 0; | |
2481 | } | |
2482 | ||
2483 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
2484 | { | |
2485 | if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds)) | |
2486 | return mv88e63xx_get_temp(ds, temp); | |
2487 | ||
2488 | return mv88e61xx_get_temp(ds, temp); | |
2489 | } | |
2490 | ||
2491 | int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) | |
2492 | { | |
2493 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2494 | int ret; | |
2495 | ||
2496 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2497 | return -EOPNOTSUPP; | |
2498 | ||
2499 | *temp = 0; | |
2500 | ||
2501 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2502 | if (ret < 0) | |
2503 | return ret; | |
2504 | ||
2505 | *temp = (((ret >> 8) & 0x1f) * 5) - 25; | |
2506 | ||
2507 | return 0; | |
2508 | } | |
2509 | ||
2510 | int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) | |
2511 | { | |
2512 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2513 | int ret; | |
2514 | ||
2515 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2516 | return -EOPNOTSUPP; | |
2517 | ||
2518 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2519 | if (ret < 0) | |
2520 | return ret; | |
2521 | temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); | |
2522 | return mv88e6xxx_phy_page_write(ds, phy, 6, 26, | |
2523 | (ret & 0xe0ff) | (temp << 8)); | |
2524 | } | |
2525 | ||
2526 | int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) | |
2527 | { | |
2528 | int phy = mv88e6xxx_6320_family(ds) ? 3 : 0; | |
2529 | int ret; | |
2530 | ||
2531 | if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds)) | |
2532 | return -EOPNOTSUPP; | |
2533 | ||
2534 | *alarm = false; | |
2535 | ||
2536 | ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); | |
2537 | if (ret < 0) | |
2538 | return ret; | |
2539 | ||
2540 | *alarm = !!(ret & 0x40); | |
2541 | ||
2542 | return 0; | |
2543 | } | |
2544 | #endif /* CONFIG_NET_DSA_HWMON */ | |
2545 | ||
98e67308 BH |
2546 | static int __init mv88e6xxx_init(void) |
2547 | { | |
2548 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2549 | register_switch_driver(&mv88e6131_switch_driver); | |
2550 | #endif | |
2551 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
2552 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 2553 | #endif |
3ad50cca GR |
2554 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2555 | register_switch_driver(&mv88e6352_switch_driver); | |
2556 | #endif | |
42f27253 AL |
2557 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2558 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
2559 | #endif |
2560 | return 0; | |
2561 | } | |
2562 | module_init(mv88e6xxx_init); | |
2563 | ||
2564 | static void __exit mv88e6xxx_cleanup(void) | |
2565 | { | |
42f27253 AL |
2566 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2567 | unregister_switch_driver(&mv88e6171_switch_driver); | |
2568 | #endif | |
4212b543 VD |
2569 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2570 | unregister_switch_driver(&mv88e6352_switch_driver); | |
2571 | #endif | |
98e67308 BH |
2572 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
2573 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
2574 | #endif | |
2575 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2576 | unregister_switch_driver(&mv88e6131_switch_driver); | |
2577 | #endif | |
2578 | } | |
2579 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
2580 | |
2581 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
2582 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
2583 | MODULE_LICENSE("GPL"); |