[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx.c

/*
 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
 * will be directly accessible on some {device address,register address}
 * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
 * will only respond to SMI transactions to that specific address, and
 * an indirect addressing mechanism needs to be used to access its
 * registers.
 */
static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
		ret = mdiobus_read(bus, sw_addr, 0);
		if (ret < 0)
			return ret;

		if ((ret & 0x8000) == 0)
			return 0;
	}

	return -ETIMEDOUT;
}

int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
{
	int ret;

	if (sw_addr == 0)
		return mdiobus_read(bus, addr, reg);

	/* Wait for the bus to become free. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Transmit the read command. */
	ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
	if (ret < 0)
		return ret;

	/* Wait for the read command to complete. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Read the data. */
	ret = mdiobus_read(bus, sw_addr, 1);
	if (ret < 0)
		return ret;

	return ret & 0xffff;
}

/* Must be called with SMI mutex held */
static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
	int ret;

	if (bus == NULL)
		return -EINVAL;

	ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
	if (ret < 0)
		return ret;

	dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
		addr, reg, ret);

	return ret;
}

int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->smi_mutex);
	ret = _mv88e6xxx_reg_read(ds, addr, reg);
	mutex_unlock(&ps->smi_mutex);

	return ret;
}

int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
			  int reg, u16 val)
{
	int ret;

	if (sw_addr == 0)
		return mdiobus_write(bus, addr, reg, val);

	/* Wait for the bus to become free. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Transmit the data to write. */
	ret = mdiobus_write(bus, sw_addr, 1, val);
	if (ret < 0)
		return ret;

	/* Transmit the write command. */
	ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
	if (ret < 0)
		return ret;

	/* Wait for the write command to complete. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	return 0;
}

/* Must be called with SMI mutex held */
static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
				u16 val)
{
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);

	if (bus == NULL)
		return -EINVAL;

	dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
		addr, reg, val);

	return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
}

int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->smi_mutex);
	ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
	mutex_unlock(&ps->smi_mutex);

	return ret;
}

int mv88e6xxx_config_prio(struct dsa_switch *ds)
{
	/* Configure the IP ToS mapping registers. */
	REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
	REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
	REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
	REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
	REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
	REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
	REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
	REG_WRITE(REG_GLOBAL, 0x17, 0xffff);

	/* Configure the IEEE 802.1p priority mapping register. */
	REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);

	return 0;
}

int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
{
	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);

	return 0;
}

int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
{
	int i;
	int ret;

	for (i = 0; i < 6; i++) {
		int j;

		/* Write the MAC address byte. */
		REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);

		/* Wait for the write to complete. */
		for (j = 0; j < 16; j++) {
			ret = REG_READ(REG_GLOBAL2, 0x0d);
			if ((ret & 0x8000) == 0)
				break;
		}
		if (j == 16)
			return -ETIMEDOUT;
	}

	return 0;
}

int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
{
	if (addr >= 0)
		return mv88e6xxx_reg_read(ds, addr, regnum);
	return 0xffff;
}

int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
{
	if (addr >= 0)
		return mv88e6xxx_reg_write(ds, addr, regnum, val);
	return 0;
}

#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
{
	int ret;
	unsigned long timeout;

	ret = REG_READ(REG_GLOBAL, 0x04);
	REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);

	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		usleep_range(1000, 2000);
		if ((ret & 0xc000) != 0xc000)
			return 0;
	}

	return -ETIMEDOUT;
}

static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
{
	int ret;
	unsigned long timeout;

	ret = REG_READ(REG_GLOBAL, 0x04);
	REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);

	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		usleep_range(1000, 2000);
		if ((ret & 0xc000) == 0xc000)
			return 0;
	}

	return -ETIMEDOUT;
}

static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
{
	struct mv88e6xxx_priv_state *ps;

	ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
	if (mutex_trylock(&ps->ppu_mutex)) {
		struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;

		if (mv88e6xxx_ppu_enable(ds) == 0)
			ps->ppu_disabled = 0;
		mutex_unlock(&ps->ppu_mutex);
	}
}

static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
{
	struct mv88e6xxx_priv_state *ps = (void *)_ps;

	schedule_work(&ps->ppu_work);
}

static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->ppu_mutex);

	/* If the PHY polling unit is enabled, disable it so that
	 * we can access the PHY registers.  If it was already
	 * disabled, cancel the timer that is going to re-enable
	 * it.
	 */
	if (!ps->ppu_disabled) {
		ret = mv88e6xxx_ppu_disable(ds);
		if (ret < 0) {
			mutex_unlock(&ps->ppu_mutex);
			return ret;
		}
		ps->ppu_disabled = 1;
	} else {
		del_timer(&ps->ppu_timer);
		ret = 0;
	}

	return ret;
}

static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	/* Schedule a timer to re-enable the PHY polling unit. */
	mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
	mutex_unlock(&ps->ppu_mutex);
}

void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	mutex_init(&ps->ppu_mutex);
	INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
	init_timer(&ps->ppu_timer);
	ps->ppu_timer.data = (unsigned long)ps;
	ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
}

int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
{
	int ret;

	ret = mv88e6xxx_ppu_access_get(ds);
	if (ret >= 0) {
		ret = mv88e6xxx_reg_read(ds, addr, regnum);
		mv88e6xxx_ppu_access_put(ds);
	}

	return ret;
}

int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
			    int regnum, u16 val)
{
	int ret;

	ret = mv88e6xxx_ppu_access_get(ds);
	if (ret >= 0) {
		ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
		mv88e6xxx_ppu_access_put(ds);
	}

	return ret;
}
#endif

void mv88e6xxx_poll_link(struct dsa_switch *ds)
{
	int i;

	for (i = 0; i < DSA_MAX_PORTS; i++) {
		struct net_device *dev;
		int uninitialized_var(port_status);
		int link;
		int speed;
		int duplex;
		int fc;

		dev = ds->ports[i];
		if (dev == NULL)
			continue;

		link = 0;
		if (dev->flags & IFF_UP) {
			port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
			if (port_status < 0)
				continue;

			link = !!(port_status & 0x0800);
		}

		if (!link) {
			if (netif_carrier_ok(dev)) {
				netdev_info(dev, "link down\n");
				netif_carrier_off(dev);
			}
			continue;
		}

		switch (port_status & 0x0300) {
		case 0x0000:
			speed = 10;
			break;
		case 0x0100:
			speed = 100;
			break;
		case 0x0200:
			speed = 1000;
			break;
		default:
			speed = -1;
			break;
		}
		duplex = (port_status & 0x0400) ? 1 : 0;
		fc = (port_status & 0x8000) ? 1 : 0;

		if (!netif_carrier_ok(dev)) {
			netdev_info(dev,
				    "link up, %d Mb/s, %s duplex, flow control %sabled\n",
				    speed,
				    duplex ? "full" : "half",
				    fc ? "en" : "dis");
			netif_carrier_on(dev);
		}
	}
}

static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
{
	int ret;
	int i;

	for (i = 0; i < 10; i++) {
		ret = REG_READ(REG_GLOBAL, 0x1d);
		if ((ret & 0x8000) == 0)
			return 0;
	}

	return -ETIMEDOUT;
}

static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
{
	int ret;

	/* Snapshot the hardware statistics counters for this port. */
	REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);

	/* Wait for the snapshotting to complete. */
	ret = mv88e6xxx_stats_wait(ds);
	if (ret < 0)
		return ret;

	return 0;
}

static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
{
	u32 _val;
	int ret;

	*val = 0;

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
	if (ret < 0)
		return;

	ret = mv88e6xxx_stats_wait(ds);
	if (ret < 0)
		return;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
	if (ret < 0)
		return;

	_val = ret << 16;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
	if (ret < 0)
		return;

	*val = _val | ret;
}

void mv88e6xxx_get_strings(struct dsa_switch *ds,
			   int nr_stats, struct mv88e6xxx_hw_stat *stats,
			   int port, uint8_t *data)
{
	int i;

	for (i = 0; i < nr_stats; i++) {
		memcpy(data + i * ETH_GSTRING_LEN,
		       stats[i].string, ETH_GSTRING_LEN);
	}
}

void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
				 int nr_stats, struct mv88e6xxx_hw_stat *stats,
				 int port, uint64_t *data)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;
	int i;

	mutex_lock(&ps->stats_mutex);

	ret = mv88e6xxx_stats_snapshot(ds, port);
	if (ret < 0) {
		mutex_unlock(&ps->stats_mutex);
		return;
	}

	/* Read each of the counters. */
	for (i = 0; i < nr_stats; i++) {
		struct mv88e6xxx_hw_stat *s = stats + i;
		u32 low;
		u32 high = 0;

		if (s->reg >= 0x100) {
			int ret;

			ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
						 s->reg - 0x100);
			if (ret < 0)
				goto error;
			low = ret;
			if (s->sizeof_stat == 4) {
				ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
							 s->reg - 0x100 + 1);
				if (ret < 0)
					goto error;
				high = ret;
			}
			data[i] = (((u64)high) << 16) | low;
			continue;
		}
		mv88e6xxx_stats_read(ds, s->reg, &low);
		if (s->sizeof_stat == 8)
			mv88e6xxx_stats_read(ds, s->reg + 1, &high);

		data[i] = (((u64)high) << 32) | low;
	}
error:
	mutex_unlock(&ps->stats_mutex);
}

int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
{
	return 32 * sizeof(u16);
}

void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			struct ethtool_regs *regs, void *_p)
{
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

	for (i = 0; i < 32; i++) {
		int ret;

		ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
		if (ret >= 0)
			p[i] = ret;
	}
}

#ifdef CONFIG_NET_DSA_HWMON

int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;
	int val;

	*temp = 0;

	mutex_lock(&ps->phy_mutex);

	ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
	if (ret < 0)
		goto error;

	/* Enable temperature sensor */
	ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
	if (ret < 0)
		goto error;

	/* Wait for temperature to stabilize */
	usleep_range(10000, 12000);

	val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	if (val < 0) {
		ret = val;
		goto error;
	}

	/* Disable temperature sensor */
	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
	if (ret < 0)
		goto error;

	*temp = ((val & 0x1f) - 5) * 5;

error:
	mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
	mutex_unlock(&ps->phy_mutex);
	return ret;
}
#endif /* CONFIG_NET_DSA_HWMON */

static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
{
	unsigned long timeout = jiffies + HZ / 10;

	while (time_before(jiffies, timeout)) {
		int ret;

		ret = REG_READ(reg, offset);
		if (!(ret & mask))
			return 0;

		usleep_range(1000, 2000);
	}
	return -ETIMEDOUT;
}

int mv88e6xxx_phy_wait(struct dsa_switch *ds)
{
	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
}

int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
{
	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
}

int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
{
	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
}

int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
{
	int ret;

	REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);

	ret = mv88e6xxx_phy_wait(ds);
	if (ret < 0)
		return ret;

	return REG_READ(REG_GLOBAL2, 0x19);
}

int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
				 u16 val)
{
	REG_WRITE(REG_GLOBAL2, 0x19, val);
	REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);

	return mv88e6xxx_phy_wait(ds);
}

int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
{
	int reg;

	reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
	if (reg < 0)
		return -EOPNOTSUPP;

	e->eee_enabled = !!(reg & 0x0200);
	e->tx_lpi_enabled = !!(reg & 0x0100);

	reg = REG_READ(REG_PORT(port), 0);
	e->eee_active = !!(reg & 0x0040);

	return 0;
}

static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
				    bool eee_enabled, bool tx_lpi_enabled)
{
	int reg, nreg;

	reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
	if (reg < 0)
		return reg;

	nreg = reg & ~0x0300;
	if (eee_enabled)
		nreg |= 0x0200;
	if (tx_lpi_enabled)
		nreg |= 0x0100;

	if (nreg != reg)
		return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);

	return 0;
}

int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
		      struct phy_device *phydev, struct ethtool_eee *e)
{
	int ret;

	ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
				       e->tx_lpi_enabled);
	if (ret)
		return -EOPNOTSUPP;

	return 0;
}

int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret, reg;

	mutex_lock(&ps->smi_mutex);

	/* Port Control 1: disable trunking, disable sending
	 * learning messages to this port.
	 */
	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
	if (ret)
		goto abort;

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	reg = (port & 0xf) << 12;
	if (dsa_is_cpu_port(ds, port))
		reg |= ds->phys_port_mask;
	else
		reg |= 1 << dsa_upstream_port(ds);

	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
	if (ret)
		goto abort;

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
abort:
	mutex_unlock(&ps->smi_mutex);
	return ret;
}

int mv88e6xxx_setup_common(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	mutex_init(&ps->smi_mutex);
	mutex_init(&ps->stats_mutex);
	mutex_init(&ps->phy_mutex);

	return 0;
}

static int __init mv88e6xxx_init(void)
{
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	register_switch_driver(&mv88e6131_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	register_switch_driver(&mv88e6123_61_65_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
	register_switch_driver(&mv88e6352_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	register_switch_driver(&mv88e6171_switch_driver);
#endif
	return 0;
}
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	unregister_switch_driver(&mv88e6171_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	unregister_switch_driver(&mv88e6123_61_65_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	unregister_switch_driver(&mv88e6131_switch_driver);
#endif
}
module_exit(mv88e6xxx_cleanup);

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");
Commit	Line	Data
91da11f8 LB	1	/*
	2	* net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
	3	* Copyright (c) 2008 Marvell Semiconductor
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
19b2f97e BG	11	#include <linux/delay.h>
19b2f97e BG	12	#include <linux/jiffies.h>
91da11f8	13	#include <linux/list.h>
2bbba277	14	#include <linux/module.h>
91da11f8 LB	15	#include <linux/netdevice.h>
91da11f8 LB	16	#include <linux/phy.h>
c8f0b869	17	#include <net/dsa.h>
91da11f8 LB	18	#include "mv88e6xxx.h"
91da11f8 LB	19
3675c8d7	20	/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8 LB	21	* use all 32 SMI bus addresses on its SMI bus, and all switch registers
	22	* will be directly accessible on some {device address,register address}
	23	* pair. If the ADDR[4:0] pins are not strapped to zero, the switch
	24	* will only respond to SMI transactions to that specific address, and
	25	* an indirect addressing mechanism needs to be used to access its
	26	* registers.
	27	*/
	28	static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
	29	{
	30	int ret;
	31	int i;
	32
	33	for (i = 0; i < 16; i++) {
	34	ret = mdiobus_read(bus, sw_addr, 0);
	35	if (ret < 0)
	36	return ret;
	37
	38	if ((ret & 0x8000) == 0)
	39	return 0;
	40	}
	41
	42	return -ETIMEDOUT;
	43	}
	44
	45	int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
	46	{
	47	int ret;
	48
	49	if (sw_addr == 0)
	50	return mdiobus_read(bus, addr, reg);
	51
3675c8d7	52	/* Wait for the bus to become free. */
91da11f8 LB	53	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	54	if (ret < 0)
	55	return ret;
	56
3675c8d7	57	/* Transmit the read command. */
91da11f8 LB	58	ret = mdiobus_write(bus, sw_addr, 0, 0x9800 \| (addr << 5) \| reg);
	59	if (ret < 0)
	60	return ret;
	61
3675c8d7	62	/* Wait for the read command to complete. */
91da11f8 LB	63	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	64	if (ret < 0)
	65	return ret;
	66
3675c8d7	67	/* Read the data. */
91da11f8 LB	68	ret = mdiobus_read(bus, sw_addr, 1);
	69	if (ret < 0)
	70	return ret;
	71
	72	return ret & 0xffff;
	73	}
	74
8d6d09e7 GR	75	/* Must be called with SMI mutex held */
8d6d09e7 GR	76	static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8	77	{
b184e497	78	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 LB	79	int ret;
91da11f8 LB	80
b184e497 GR	81	if (bus == NULL)
	82	return -EINVAL;
	83
b184e497	84	ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e VD	85	if (ret < 0)
	86	return ret;
	87
	88	dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
	89	addr, reg, ret);
	90
91da11f8 LB	91	return ret;
	92	}
	93
8d6d09e7 GR	94	int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
	95	{
	96	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	97	int ret;
	98
	99	mutex_lock(&ps->smi_mutex);
	100	ret = _mv88e6xxx_reg_read(ds, addr, reg);
	101	mutex_unlock(&ps->smi_mutex);
	102
	103	return ret;
	104	}
	105
91da11f8 LB	106	int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
	107	int reg, u16 val)
	108	{
	109	int ret;
	110
	111	if (sw_addr == 0)
	112	return mdiobus_write(bus, addr, reg, val);
	113
3675c8d7	114	/* Wait for the bus to become free. */
91da11f8 LB	115	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	116	if (ret < 0)
	117	return ret;
	118
3675c8d7	119	/* Transmit the data to write. */
91da11f8 LB	120	ret = mdiobus_write(bus, sw_addr, 1, val);
	121	if (ret < 0)
	122	return ret;
	123
3675c8d7	124	/* Transmit the write command. */
91da11f8 LB	125	ret = mdiobus_write(bus, sw_addr, 0, 0x9400 \| (addr << 5) \| reg);
	126	if (ret < 0)
	127	return ret;
	128
3675c8d7	129	/* Wait for the write command to complete. */
91da11f8 LB	130	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	131	if (ret < 0)
	132	return ret;
	133
	134	return 0;
	135	}
	136
8d6d09e7 GR	137	/* Must be called with SMI mutex held */
	138	static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
	139	u16 val)
91da11f8	140	{
b184e497	141	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8	142
b184e497 GR	143	if (bus == NULL)
	144	return -EINVAL;
	145
bb92ea5e VD	146	dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
	147	addr, reg, val);
	148
8d6d09e7 GR	149	return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
	150	}
	151
	152	int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
	153	{
	154	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	155	int ret;
	156
91da11f8	157	mutex_lock(&ps->smi_mutex);
8d6d09e7	158	ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8 LB	159	mutex_unlock(&ps->smi_mutex);
	160
	161	return ret;
	162	}
	163
	164	int mv88e6xxx_config_prio(struct dsa_switch *ds)
	165	{
3675c8d7	166	/* Configure the IP ToS mapping registers. */
91da11f8 LB	167	REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
	168	REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
	169	REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
	170	REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
	171	REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
	172	REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
	173	REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
	174	REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
	175
3675c8d7	176	/* Configure the IEEE 802.1p priority mapping register. */
91da11f8 LB	177	REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
	178
	179	return 0;
	180	}
	181
2e5f0320 LB	182	int mv88e6xxx_set_addr_direct(struct dsa_switch ds, u8 addr)
	183	{
	184	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) \| addr[1]);
	185	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) \| addr[3]);
	186	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) \| addr[5]);
	187
	188	return 0;
	189	}
	190
91da11f8 LB	191	int mv88e6xxx_set_addr_indirect(struct dsa_switch ds, u8 addr)
	192	{
	193	int i;
	194	int ret;
	195
	196	for (i = 0; i < 6; i++) {
	197	int j;
	198
3675c8d7	199	/* Write the MAC address byte. */
91da11f8 LB	200	REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 \| (i << 8) \| addr[i]);
91da11f8 LB	201
3675c8d7	202	/* Wait for the write to complete. */
91da11f8 LB	203	for (j = 0; j < 16; j++) {
	204	ret = REG_READ(REG_GLOBAL2, 0x0d);
	205	if ((ret & 0x8000) == 0)
	206	break;
	207	}
	208	if (j == 16)
	209	return -ETIMEDOUT;
	210	}
	211
	212	return 0;
	213	}
	214
	215	int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
	216	{
	217	if (addr >= 0)
	218	return mv88e6xxx_reg_read(ds, addr, regnum);
	219	return 0xffff;
	220	}
	221
	222	int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
	223	{
	224	if (addr >= 0)
	225	return mv88e6xxx_reg_write(ds, addr, regnum, val);
	226	return 0;
	227	}
	228
2e5f0320 LB	229	#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
	230	static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
	231	{
	232	int ret;
19b2f97e	233	unsigned long timeout;
2e5f0320 LB	234
	235	ret = REG_READ(REG_GLOBAL, 0x04);
	236	REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
	237
19b2f97e BG	238	timeout = jiffies + 1 * HZ;
19b2f97e BG	239	while (time_before(jiffies, timeout)) {
85686581	240	ret = REG_READ(REG_GLOBAL, 0x00);
19b2f97e	241	usleep_range(1000, 2000);
85686581 BG	242	if ((ret & 0xc000) != 0xc000)
85686581 BG	243	return 0;
2e5f0320 LB	244	}
	245
	246	return -ETIMEDOUT;
	247	}
	248
	249	static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
	250	{
	251	int ret;
19b2f97e	252	unsigned long timeout;
2e5f0320 LB	253
	254	ret = REG_READ(REG_GLOBAL, 0x04);
	255	REG_WRITE(REG_GLOBAL, 0x04, ret \| 0x4000);
	256
19b2f97e BG	257	timeout = jiffies + 1 * HZ;
19b2f97e BG	258	while (time_before(jiffies, timeout)) {
85686581	259	ret = REG_READ(REG_GLOBAL, 0x00);
19b2f97e	260	usleep_range(1000, 2000);
85686581 BG	261	if ((ret & 0xc000) == 0xc000)
85686581 BG	262	return 0;
2e5f0320 LB	263	}
	264
	265	return -ETIMEDOUT;
	266	}
	267
	268	static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
	269	{
	270	struct mv88e6xxx_priv_state *ps;
	271
	272	ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
	273	if (mutex_trylock(&ps->ppu_mutex)) {
85686581	274	struct dsa_switch ds = ((struct dsa_switch )ps) - 1;
2e5f0320	275
85686581 BG	276	if (mv88e6xxx_ppu_enable(ds) == 0)
	277	ps->ppu_disabled = 0;
	278	mutex_unlock(&ps->ppu_mutex);
2e5f0320 LB	279	}
	280	}
	281
	282	static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
	283	{
	284	struct mv88e6xxx_priv_state ps = (void )_ps;
	285
	286	schedule_work(&ps->ppu_work);
	287	}
	288
	289	static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
	290	{
a22adce5	291	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 LB	292	int ret;
	293
	294	mutex_lock(&ps->ppu_mutex);
	295
3675c8d7	296	/* If the PHY polling unit is enabled, disable it so that
2e5f0320 LB	297	* we can access the PHY registers. If it was already
	298	* disabled, cancel the timer that is going to re-enable
	299	* it.
	300	*/
	301	if (!ps->ppu_disabled) {
85686581 BG	302	ret = mv88e6xxx_ppu_disable(ds);
	303	if (ret < 0) {
	304	mutex_unlock(&ps->ppu_mutex);
	305	return ret;
	306	}
	307	ps->ppu_disabled = 1;
2e5f0320	308	} else {
85686581 BG	309	del_timer(&ps->ppu_timer);
85686581 BG	310	ret = 0;
2e5f0320 LB	311	}
	312
	313	return ret;
	314	}
	315
	316	static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
	317	{
a22adce5	318	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320	319
3675c8d7	320	/* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320 LB	321	mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
	322	mutex_unlock(&ps->ppu_mutex);
	323	}
	324
	325	void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
	326	{
a22adce5	327	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 LB	328
	329	mutex_init(&ps->ppu_mutex);
	330	INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
	331	init_timer(&ps->ppu_timer);
	332	ps->ppu_timer.data = (unsigned long)ps;
	333	ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
	334	}
	335
	336	int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
	337	{
	338	int ret;
	339
	340	ret = mv88e6xxx_ppu_access_get(ds);
	341	if (ret >= 0) {
85686581 BG	342	ret = mv88e6xxx_reg_read(ds, addr, regnum);
85686581 BG	343	mv88e6xxx_ppu_access_put(ds);
2e5f0320 LB	344	}
	345
	346	return ret;
	347	}
	348
	349	int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
	350	int regnum, u16 val)
	351	{
	352	int ret;
	353
	354	ret = mv88e6xxx_ppu_access_get(ds);
	355	if (ret >= 0) {
85686581 BG	356	ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
85686581 BG	357	mv88e6xxx_ppu_access_put(ds);
2e5f0320 LB	358	}
	359
	360	return ret;
	361	}
	362	#endif
	363
91da11f8 LB	364	void mv88e6xxx_poll_link(struct dsa_switch *ds)
	365	{
	366	int i;
	367
	368	for (i = 0; i < DSA_MAX_PORTS; i++) {
	369	struct net_device *dev;
2a9e7978	370	int uninitialized_var(port_status);
91da11f8 LB	371	int link;
	372	int speed;
	373	int duplex;
	374	int fc;
	375
	376	dev = ds->ports[i];
	377	if (dev == NULL)
	378	continue;
	379
	380	link = 0;
	381	if (dev->flags & IFF_UP) {
	382	port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
	383	if (port_status < 0)
	384	continue;
	385
	386	link = !!(port_status & 0x0800);
	387	}
	388
	389	if (!link) {
	390	if (netif_carrier_ok(dev)) {
ab381a93	391	netdev_info(dev, "link down\n");
91da11f8 LB	392	netif_carrier_off(dev);
	393	}
	394	continue;
	395	}
	396
	397	switch (port_status & 0x0300) {
	398	case 0x0000:
	399	speed = 10;
	400	break;
	401	case 0x0100:
	402	speed = 100;
	403	break;
	404	case 0x0200:
	405	speed = 1000;
	406	break;
	407	default:
	408	speed = -1;
	409	break;
	410	}
	411	duplex = (port_status & 0x0400) ? 1 : 0;
	412	fc = (port_status & 0x8000) ? 1 : 0;
	413
	414	if (!netif_carrier_ok(dev)) {
ab381a93 BG	415	netdev_info(dev,
	416	"link up, %d Mb/s, %s duplex, flow control %sabled\n",
	417	speed,
	418	duplex ? "full" : "half",
	419	fc ? "en" : "dis");
91da11f8 LB	420	netif_carrier_on(dev);
	421	}
	422	}
	423	}
	424
	425	static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
	426	{
	427	int ret;
	428	int i;
	429
	430	for (i = 0; i < 10; i++) {
1ded3f59	431	ret = REG_READ(REG_GLOBAL, 0x1d);
91da11f8 LB	432	if ((ret & 0x8000) == 0)
	433	return 0;
	434	}
	435
	436	return -ETIMEDOUT;
	437	}
	438
	439	static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
	440	{
	441	int ret;
	442
3675c8d7	443	/* Snapshot the hardware statistics counters for this port. */
91da11f8 LB	444	REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 \| port);
91da11f8 LB	445
3675c8d7	446	/* Wait for the snapshotting to complete. */
91da11f8 LB	447	ret = mv88e6xxx_stats_wait(ds);
	448	if (ret < 0)
	449	return ret;
	450
	451	return 0;
	452	}
	453
	454	static void mv88e6xxx_stats_read(struct dsa_switch ds, int stat, u32 val)
	455	{
	456	u32 _val;
	457	int ret;
	458
	459	*val = 0;
	460
	461	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 \| stat);
	462	if (ret < 0)
	463	return;
	464
	465	ret = mv88e6xxx_stats_wait(ds);
	466	if (ret < 0)
	467	return;
	468
	469	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
	470	if (ret < 0)
	471	return;
	472
	473	_val = ret << 16;
	474
	475	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
	476	if (ret < 0)
	477	return;
	478
	479	*val = _val \| ret;
	480	}
	481
	482	void mv88e6xxx_get_strings(struct dsa_switch *ds,
	483	int nr_stats, struct mv88e6xxx_hw_stat *stats,
	484	int port, uint8_t *data)
	485	{
	486	int i;
	487
	488	for (i = 0; i < nr_stats; i++) {
	489	memcpy(data + i * ETH_GSTRING_LEN,
	490	stats[i].string, ETH_GSTRING_LEN);
	491	}
	492	}
	493
	494	void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
	495	int nr_stats, struct mv88e6xxx_hw_stat *stats,
	496	int port, uint64_t *data)
	497	{
a22adce5	498	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 LB	499	int ret;
	500	int i;
	501
	502	mutex_lock(&ps->stats_mutex);
	503
	504	ret = mv88e6xxx_stats_snapshot(ds, port);
	505	if (ret < 0) {
	506	mutex_unlock(&ps->stats_mutex);
	507	return;
	508	}
	509
3675c8d7	510	/* Read each of the counters. */
91da11f8 LB	511	for (i = 0; i < nr_stats; i++) {
	512	struct mv88e6xxx_hw_stat *s = stats + i;
	513	u32 low;
17ee3e04 GR	514	u32 high = 0;
	515
	516	if (s->reg >= 0x100) {
	517	int ret;
	518
	519	ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
	520	s->reg - 0x100);
	521	if (ret < 0)
	522	goto error;
	523	low = ret;
	524	if (s->sizeof_stat == 4) {
	525	ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
	526	s->reg - 0x100 + 1);
	527	if (ret < 0)
	528	goto error;
	529	high = ret;
	530	}
	531	data[i] = (((u64)high) << 16) \| low;
	532	continue;
	533	}
91da11f8 LB	534	mv88e6xxx_stats_read(ds, s->reg, &low);
	535	if (s->sizeof_stat == 8)
	536	mv88e6xxx_stats_read(ds, s->reg + 1, &high);
91da11f8 LB	537
	538	data[i] = (((u64)high) << 32) \| low;
	539	}
17ee3e04	540	error:
91da11f8 LB	541	mutex_unlock(&ps->stats_mutex);
91da11f8 LB	542	}
98e67308	543
a1ab91f3 GR	544	int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
	545	{
	546	return 32 * sizeof(u16);
	547	}
	548
	549	void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
	550	struct ethtool_regs regs, void _p)
	551	{
	552	u16 *p = _p;
	553	int i;
	554
	555	regs->version = 0;
	556
	557	memset(p, 0xff, 32 * sizeof(u16));
	558
	559	for (i = 0; i < 32; i++) {
	560	int ret;
	561
	562	ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
	563	if (ret >= 0)
	564	p[i] = ret;
	565	}
	566	}
	567
eaa23765 AL	568	#ifdef CONFIG_NET_DSA_HWMON
	569
	570	int mv88e6xxx_get_temp(struct dsa_switch ds, int temp)
	571	{
	572	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	573	int ret;
	574	int val;
	575
	576	*temp = 0;
	577
	578	mutex_lock(&ps->phy_mutex);
	579
	580	ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
	581	if (ret < 0)
	582	goto error;
	583
	584	/* Enable temperature sensor */
	585	ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	586	if (ret < 0)
	587	goto error;
	588
	589	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret \| (1 << 5));
	590	if (ret < 0)
	591	goto error;
	592
	593	/* Wait for temperature to stabilize */
	594	usleep_range(10000, 12000);
	595
	596	val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	597	if (val < 0) {
	598	ret = val;
	599	goto error;
	600	}
	601
	602	/* Disable temperature sensor */
	603	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
	604	if (ret < 0)
	605	goto error;
	606
	607	temp = ((val & 0x1f) - 5) 5;
	608
	609	error:
	610	mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
	611	mutex_unlock(&ps->phy_mutex);
	612	return ret;
	613	}
	614	#endif /* CONFIG_NET_DSA_HWMON */
	615
f3044683 AL	616	static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
	617	{
	618	unsigned long timeout = jiffies + HZ / 10;
	619
	620	while (time_before(jiffies, timeout)) {
	621	int ret;
	622
	623	ret = REG_READ(reg, offset);
	624	if (!(ret & mask))
	625	return 0;
	626
	627	usleep_range(1000, 2000);
	628	}
	629	return -ETIMEDOUT;
	630	}
	631
	632	int mv88e6xxx_phy_wait(struct dsa_switch *ds)
	633	{
	634	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
	635	}
	636
	637	int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
	638	{
	639	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
	640	}
	641
	642	int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
	643	{
	644	return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
	645	}
	646
	647	int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
	648	{
	649	int ret;
	650
	651	REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 \| (addr << 5) \| regnum);
	652
	653	ret = mv88e6xxx_phy_wait(ds);
	654	if (ret < 0)
	655	return ret;
	656
	657	return REG_READ(REG_GLOBAL2, 0x19);
	658	}
	659
	660	int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
	661	u16 val)
	662	{
	663	REG_WRITE(REG_GLOBAL2, 0x19, val);
	664	REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 \| (addr << 5) \| regnum);
	665
	666	return mv88e6xxx_phy_wait(ds);
	667	}
	668
11b3b45d GR	669	int mv88e6xxx_get_eee(struct dsa_switch ds, int port, struct ethtool_eee e)
	670	{
	671	int reg;
	672
	673	reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
	674	if (reg < 0)
	675	return -EOPNOTSUPP;
	676
	677	e->eee_enabled = !!(reg & 0x0200);
	678	e->tx_lpi_enabled = !!(reg & 0x0100);
	679
	680	reg = REG_READ(REG_PORT(port), 0);
	681	e->eee_active = !!(reg & 0x0040);
	682
	683	return 0;
	684	}
	685
	686	static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
	687	bool eee_enabled, bool tx_lpi_enabled)
	688	{
	689	int reg, nreg;
	690
	691	reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
	692	if (reg < 0)
	693	return reg;
	694
	695	nreg = reg & ~0x0300;
	696	if (eee_enabled)
	697	nreg \|= 0x0200;
	698	if (tx_lpi_enabled)
	699	nreg \|= 0x0100;
	700
	701	if (nreg != reg)
	702	return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
	703
	704	return 0;
	705	}
	706
	707	int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
	708	struct phy_device phydev, struct ethtool_eee e)
	709	{
	710	int ret;
	711
	712	ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
	713	e->tx_lpi_enabled);
	714	if (ret)
	715	return -EOPNOTSUPP;
	716
	717	return 0;
	718	}
	719
d827e88a GR	720	int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
	721	{
	722	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	723	int ret, reg;
	724
	725	mutex_lock(&ps->smi_mutex);
	726
366f0a0f GR	727	/* Port Control 1: disable trunking, disable sending
366f0a0f GR	728	* learning messages to this port.
d827e88a	729	*/
366f0a0f	730	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
d827e88a GR	731	if (ret)
	732	goto abort;
	733
	734	/* Port based VLAN map: give each port its own address
	735	* database, allow the CPU port to talk to each of the 'real'
	736	* ports, and allow each of the 'real' ports to only talk to
	737	* the upstream port.
	738	*/
	739	reg = (port & 0xf) << 12;
	740	if (dsa_is_cpu_port(ds, port))
	741	reg \|= ds->phys_port_mask;
	742	else
	743	reg \|= 1 << dsa_upstream_port(ds);
	744
	745	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
	746	if (ret)
	747	goto abort;
	748
	749	/* Default VLAN ID and priority: don't set a default VLAN
	750	* ID, and set the default packet priority to zero.
	751	*/
	752	ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
	753	abort:
	754	mutex_unlock(&ps->smi_mutex);
	755	return ret;
	756	}
	757
acdaffcc GR	758	int mv88e6xxx_setup_common(struct dsa_switch *ds)
	759	{
	760	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	761
	762	mutex_init(&ps->smi_mutex);
	763	mutex_init(&ps->stats_mutex);
	764	mutex_init(&ps->phy_mutex);
	765
	766	return 0;
	767	}
	768
98e67308 BH	769	static int __init mv88e6xxx_init(void)
	770	{
	771	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	772	register_switch_driver(&mv88e6131_switch_driver);
	773	#endif
	774	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	775	register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253	776	#endif
3ad50cca GR	777	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
	778	register_switch_driver(&mv88e6352_switch_driver);
	779	#endif
42f27253 AL	780	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
42f27253 AL	781	register_switch_driver(&mv88e6171_switch_driver);
98e67308 BH	782	#endif
	783	return 0;
	784	}
	785	module_init(mv88e6xxx_init);
	786
	787	static void __exit mv88e6xxx_cleanup(void)
	788	{
42f27253 AL	789	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	790	unregister_switch_driver(&mv88e6171_switch_driver);
	791	#endif
98e67308 BH	792	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	793	unregister_switch_driver(&mv88e6123_61_65_switch_driver);
	794	#endif
	795	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	796	unregister_switch_driver(&mv88e6131_switch_driver);
	797	#endif
	798	}
	799	module_exit(mv88e6xxx_cleanup);
3d825ede BH	800
	801	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
	802	MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
	803	MODULE_LICENSE("GPL");