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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
87c8cefb | 11 | #include <linux/debugfs.h> |
19b2f97e | 12 | #include <linux/delay.h> |
defb05b9 | 13 | #include <linux/etherdevice.h> |
facd95b2 | 14 | #include <linux/if_bridge.h> |
19b2f97e | 15 | #include <linux/jiffies.h> |
91da11f8 | 16 | #include <linux/list.h> |
2bbba277 | 17 | #include <linux/module.h> |
91da11f8 LB |
18 | #include <linux/netdevice.h> |
19 | #include <linux/phy.h> | |
87c8cefb | 20 | #include <linux/seq_file.h> |
c8f0b869 | 21 | #include <net/dsa.h> |
91da11f8 LB |
22 | #include "mv88e6xxx.h" |
23 | ||
16fe24fc AL |
24 | /* MDIO bus access can be nested in the case of PHYs connected to the |
25 | * internal MDIO bus of the switch, which is accessed via MDIO bus of | |
26 | * the Ethernet interface. Avoid lockdep false positives by using | |
27 | * mutex_lock_nested(). | |
28 | */ | |
29 | static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum) | |
30 | { | |
31 | int ret; | |
32 | ||
33 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
34 | ret = bus->read(bus, addr, regnum); | |
35 | mutex_unlock(&bus->mdio_lock); | |
36 | ||
37 | return ret; | |
38 | } | |
39 | ||
40 | static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, | |
41 | u16 val) | |
42 | { | |
43 | int ret; | |
44 | ||
45 | mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING); | |
46 | ret = bus->write(bus, addr, regnum, val); | |
47 | mutex_unlock(&bus->mdio_lock); | |
48 | ||
49 | return ret; | |
50 | } | |
51 | ||
3675c8d7 | 52 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
53 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
54 | * will be directly accessible on some {device address,register address} | |
55 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
56 | * will only respond to SMI transactions to that specific address, and | |
57 | * an indirect addressing mechanism needs to be used to access its | |
58 | * registers. | |
59 | */ | |
60 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
61 | { | |
62 | int ret; | |
63 | int i; | |
64 | ||
65 | for (i = 0; i < 16; i++) { | |
16fe24fc | 66 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
67 | if (ret < 0) |
68 | return ret; | |
69 | ||
cca8b133 | 70 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
71 | return 0; |
72 | } | |
73 | ||
74 | return -ETIMEDOUT; | |
75 | } | |
76 | ||
77 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
78 | { | |
79 | int ret; | |
80 | ||
81 | if (sw_addr == 0) | |
16fe24fc | 82 | return mv88e6xxx_mdiobus_read(bus, addr, reg); |
91da11f8 | 83 | |
3675c8d7 | 84 | /* Wait for the bus to become free. */ |
91da11f8 LB |
85 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
86 | if (ret < 0) | |
87 | return ret; | |
88 | ||
3675c8d7 | 89 | /* Transmit the read command. */ |
16fe24fc AL |
90 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
91 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
92 | if (ret < 0) |
93 | return ret; | |
94 | ||
3675c8d7 | 95 | /* Wait for the read command to complete. */ |
91da11f8 LB |
96 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
97 | if (ret < 0) | |
98 | return ret; | |
99 | ||
3675c8d7 | 100 | /* Read the data. */ |
16fe24fc | 101 | ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
102 | if (ret < 0) |
103 | return ret; | |
104 | ||
105 | return ret & 0xffff; | |
106 | } | |
107 | ||
8d6d09e7 GR |
108 | /* Must be called with SMI mutex held */ |
109 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 110 | { |
b184e497 | 111 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
112 | int ret; |
113 | ||
b184e497 GR |
114 | if (bus == NULL) |
115 | return -EINVAL; | |
116 | ||
b184e497 | 117 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
118 | if (ret < 0) |
119 | return ret; | |
120 | ||
121 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
122 | addr, reg, ret); | |
123 | ||
91da11f8 LB |
124 | return ret; |
125 | } | |
126 | ||
8d6d09e7 GR |
127 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
128 | { | |
129 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
130 | int ret; | |
131 | ||
132 | mutex_lock(&ps->smi_mutex); | |
133 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
134 | mutex_unlock(&ps->smi_mutex); | |
135 | ||
136 | return ret; | |
137 | } | |
138 | ||
91da11f8 LB |
139 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
140 | int reg, u16 val) | |
141 | { | |
142 | int ret; | |
143 | ||
144 | if (sw_addr == 0) | |
16fe24fc | 145 | return mv88e6xxx_mdiobus_write(bus, addr, reg, val); |
91da11f8 | 146 | |
3675c8d7 | 147 | /* Wait for the bus to become free. */ |
91da11f8 LB |
148 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
149 | if (ret < 0) | |
150 | return ret; | |
151 | ||
3675c8d7 | 152 | /* Transmit the data to write. */ |
16fe24fc | 153 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
154 | if (ret < 0) |
155 | return ret; | |
156 | ||
3675c8d7 | 157 | /* Transmit the write command. */ |
16fe24fc AL |
158 | ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD, |
159 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
160 | if (ret < 0) |
161 | return ret; | |
162 | ||
3675c8d7 | 163 | /* Wait for the write command to complete. */ |
91da11f8 LB |
164 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
165 | if (ret < 0) | |
166 | return ret; | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
8d6d09e7 GR |
171 | /* Must be called with SMI mutex held */ |
172 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
173 | u16 val) | |
91da11f8 | 174 | { |
b184e497 | 175 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 176 | |
b184e497 GR |
177 | if (bus == NULL) |
178 | return -EINVAL; | |
179 | ||
bb92ea5e VD |
180 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
181 | addr, reg, val); | |
182 | ||
8d6d09e7 GR |
183 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
184 | } | |
185 | ||
186 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
187 | { | |
188 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
189 | int ret; | |
190 | ||
91da11f8 | 191 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 192 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
193 | mutex_unlock(&ps->smi_mutex); |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
2e5f0320 LB |
198 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
199 | { | |
cca8b133 AL |
200 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
201 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
202 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
203 | |
204 | return 0; | |
205 | } | |
206 | ||
91da11f8 LB |
207 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
208 | { | |
209 | int i; | |
210 | int ret; | |
211 | ||
212 | for (i = 0; i < 6; i++) { | |
213 | int j; | |
214 | ||
3675c8d7 | 215 | /* Write the MAC address byte. */ |
cca8b133 AL |
216 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
217 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 218 | |
3675c8d7 | 219 | /* Wait for the write to complete. */ |
91da11f8 | 220 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
221 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
222 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
223 | break; |
224 | } | |
225 | if (j == 16) | |
226 | return -ETIMEDOUT; | |
227 | } | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
3898c148 | 232 | /* Must be called with SMI mutex held */ |
fd3a0ee4 | 233 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) |
91da11f8 LB |
234 | { |
235 | if (addr >= 0) | |
3898c148 | 236 | return _mv88e6xxx_reg_read(ds, addr, regnum); |
91da11f8 LB |
237 | return 0xffff; |
238 | } | |
239 | ||
3898c148 | 240 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
241 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, |
242 | u16 val) | |
91da11f8 LB |
243 | { |
244 | if (addr >= 0) | |
3898c148 | 245 | return _mv88e6xxx_reg_write(ds, addr, regnum, val); |
91da11f8 LB |
246 | return 0; |
247 | } | |
248 | ||
2e5f0320 LB |
249 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
250 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
251 | { | |
252 | int ret; | |
19b2f97e | 253 | unsigned long timeout; |
2e5f0320 | 254 | |
cca8b133 AL |
255 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
256 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
257 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 258 | |
19b2f97e BG |
259 | timeout = jiffies + 1 * HZ; |
260 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 261 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 262 | usleep_range(1000, 2000); |
cca8b133 AL |
263 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
264 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 265 | return 0; |
2e5f0320 LB |
266 | } |
267 | ||
268 | return -ETIMEDOUT; | |
269 | } | |
270 | ||
271 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
272 | { | |
273 | int ret; | |
19b2f97e | 274 | unsigned long timeout; |
2e5f0320 | 275 | |
cca8b133 AL |
276 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
277 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 278 | |
19b2f97e BG |
279 | timeout = jiffies + 1 * HZ; |
280 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 281 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 282 | usleep_range(1000, 2000); |
cca8b133 AL |
283 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
284 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 285 | return 0; |
2e5f0320 LB |
286 | } |
287 | ||
288 | return -ETIMEDOUT; | |
289 | } | |
290 | ||
291 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
292 | { | |
293 | struct mv88e6xxx_priv_state *ps; | |
294 | ||
295 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
296 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 297 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 298 | |
85686581 BG |
299 | if (mv88e6xxx_ppu_enable(ds) == 0) |
300 | ps->ppu_disabled = 0; | |
301 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
302 | } |
303 | } | |
304 | ||
305 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
306 | { | |
307 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
308 | ||
309 | schedule_work(&ps->ppu_work); | |
310 | } | |
311 | ||
312 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
313 | { | |
a22adce5 | 314 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
315 | int ret; |
316 | ||
317 | mutex_lock(&ps->ppu_mutex); | |
318 | ||
3675c8d7 | 319 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
320 | * we can access the PHY registers. If it was already |
321 | * disabled, cancel the timer that is going to re-enable | |
322 | * it. | |
323 | */ | |
324 | if (!ps->ppu_disabled) { | |
85686581 BG |
325 | ret = mv88e6xxx_ppu_disable(ds); |
326 | if (ret < 0) { | |
327 | mutex_unlock(&ps->ppu_mutex); | |
328 | return ret; | |
329 | } | |
330 | ps->ppu_disabled = 1; | |
2e5f0320 | 331 | } else { |
85686581 BG |
332 | del_timer(&ps->ppu_timer); |
333 | ret = 0; | |
2e5f0320 LB |
334 | } |
335 | ||
336 | return ret; | |
337 | } | |
338 | ||
339 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
340 | { | |
a22adce5 | 341 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 342 | |
3675c8d7 | 343 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
344 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
345 | mutex_unlock(&ps->ppu_mutex); | |
346 | } | |
347 | ||
348 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
349 | { | |
a22adce5 | 350 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
351 | |
352 | mutex_init(&ps->ppu_mutex); | |
353 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
354 | init_timer(&ps->ppu_timer); | |
355 | ps->ppu_timer.data = (unsigned long)ps; | |
356 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
357 | } | |
358 | ||
359 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
360 | { | |
361 | int ret; | |
362 | ||
363 | ret = mv88e6xxx_ppu_access_get(ds); | |
364 | if (ret >= 0) { | |
85686581 BG |
365 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
366 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
367 | } |
368 | ||
369 | return ret; | |
370 | } | |
371 | ||
372 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
373 | int regnum, u16 val) | |
374 | { | |
375 | int ret; | |
376 | ||
377 | ret = mv88e6xxx_ppu_access_get(ds); | |
378 | if (ret >= 0) { | |
85686581 BG |
379 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
380 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
381 | } |
382 | ||
383 | return ret; | |
384 | } | |
385 | #endif | |
386 | ||
91da11f8 LB |
387 | void mv88e6xxx_poll_link(struct dsa_switch *ds) |
388 | { | |
389 | int i; | |
390 | ||
391 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
392 | struct net_device *dev; | |
2a9e7978 | 393 | int uninitialized_var(port_status); |
91da11f8 LB |
394 | int link; |
395 | int speed; | |
396 | int duplex; | |
397 | int fc; | |
398 | ||
399 | dev = ds->ports[i]; | |
400 | if (dev == NULL) | |
401 | continue; | |
402 | ||
403 | link = 0; | |
404 | if (dev->flags & IFF_UP) { | |
cca8b133 AL |
405 | port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), |
406 | PORT_STATUS); | |
91da11f8 LB |
407 | if (port_status < 0) |
408 | continue; | |
409 | ||
cca8b133 | 410 | link = !!(port_status & PORT_STATUS_LINK); |
91da11f8 LB |
411 | } |
412 | ||
413 | if (!link) { | |
414 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 415 | netdev_info(dev, "link down\n"); |
91da11f8 LB |
416 | netif_carrier_off(dev); |
417 | } | |
418 | continue; | |
419 | } | |
420 | ||
cca8b133 AL |
421 | switch (port_status & PORT_STATUS_SPEED_MASK) { |
422 | case PORT_STATUS_SPEED_10: | |
91da11f8 LB |
423 | speed = 10; |
424 | break; | |
cca8b133 | 425 | case PORT_STATUS_SPEED_100: |
91da11f8 LB |
426 | speed = 100; |
427 | break; | |
cca8b133 | 428 | case PORT_STATUS_SPEED_1000: |
91da11f8 LB |
429 | speed = 1000; |
430 | break; | |
431 | default: | |
432 | speed = -1; | |
433 | break; | |
434 | } | |
cca8b133 AL |
435 | duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0; |
436 | fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0; | |
91da11f8 LB |
437 | |
438 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
439 | netdev_info(dev, |
440 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
441 | speed, | |
442 | duplex ? "full" : "half", | |
443 | fc ? "en" : "dis"); | |
91da11f8 LB |
444 | netif_carrier_on(dev); |
445 | } | |
446 | } | |
447 | } | |
448 | ||
54d792f2 AL |
449 | static bool mv88e6xxx_6065_family(struct dsa_switch *ds) |
450 | { | |
451 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
452 | ||
453 | switch (ps->id) { | |
454 | case PORT_SWITCH_ID_6031: | |
455 | case PORT_SWITCH_ID_6061: | |
456 | case PORT_SWITCH_ID_6035: | |
457 | case PORT_SWITCH_ID_6065: | |
458 | return true; | |
459 | } | |
460 | return false; | |
461 | } | |
462 | ||
463 | static bool mv88e6xxx_6095_family(struct dsa_switch *ds) | |
464 | { | |
465 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
466 | ||
467 | switch (ps->id) { | |
468 | case PORT_SWITCH_ID_6092: | |
469 | case PORT_SWITCH_ID_6095: | |
470 | return true; | |
471 | } | |
472 | return false; | |
473 | } | |
474 | ||
475 | static bool mv88e6xxx_6097_family(struct dsa_switch *ds) | |
476 | { | |
477 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
478 | ||
479 | switch (ps->id) { | |
480 | case PORT_SWITCH_ID_6046: | |
481 | case PORT_SWITCH_ID_6085: | |
482 | case PORT_SWITCH_ID_6096: | |
483 | case PORT_SWITCH_ID_6097: | |
484 | return true; | |
485 | } | |
486 | return false; | |
487 | } | |
488 | ||
489 | static bool mv88e6xxx_6165_family(struct dsa_switch *ds) | |
490 | { | |
491 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
492 | ||
493 | switch (ps->id) { | |
494 | case PORT_SWITCH_ID_6123: | |
495 | case PORT_SWITCH_ID_6161: | |
496 | case PORT_SWITCH_ID_6165: | |
497 | return true; | |
498 | } | |
499 | return false; | |
500 | } | |
501 | ||
502 | static bool mv88e6xxx_6185_family(struct dsa_switch *ds) | |
503 | { | |
504 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
505 | ||
506 | switch (ps->id) { | |
507 | case PORT_SWITCH_ID_6121: | |
508 | case PORT_SWITCH_ID_6122: | |
509 | case PORT_SWITCH_ID_6152: | |
510 | case PORT_SWITCH_ID_6155: | |
511 | case PORT_SWITCH_ID_6182: | |
512 | case PORT_SWITCH_ID_6185: | |
513 | case PORT_SWITCH_ID_6108: | |
514 | case PORT_SWITCH_ID_6131: | |
515 | return true; | |
516 | } | |
517 | return false; | |
518 | } | |
519 | ||
520 | static bool mv88e6xxx_6351_family(struct dsa_switch *ds) | |
521 | { | |
522 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
523 | ||
524 | switch (ps->id) { | |
525 | case PORT_SWITCH_ID_6171: | |
526 | case PORT_SWITCH_ID_6175: | |
527 | case PORT_SWITCH_ID_6350: | |
528 | case PORT_SWITCH_ID_6351: | |
529 | return true; | |
530 | } | |
531 | return false; | |
532 | } | |
533 | ||
f3a8b6b6 AL |
534 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
535 | { | |
536 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
537 | ||
538 | switch (ps->id) { | |
f3a8b6b6 AL |
539 | case PORT_SWITCH_ID_6172: |
540 | case PORT_SWITCH_ID_6176: | |
54d792f2 AL |
541 | case PORT_SWITCH_ID_6240: |
542 | case PORT_SWITCH_ID_6352: | |
f3a8b6b6 AL |
543 | return true; |
544 | } | |
545 | return false; | |
546 | } | |
547 | ||
31888234 AL |
548 | /* Must be called with SMI mutex held */ |
549 | static int _mv88e6xxx_stats_wait(struct dsa_switch *ds) | |
91da11f8 LB |
550 | { |
551 | int ret; | |
552 | int i; | |
553 | ||
554 | for (i = 0; i < 10; i++) { | |
31888234 | 555 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP); |
cca8b133 | 556 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) |
91da11f8 LB |
557 | return 0; |
558 | } | |
559 | ||
560 | return -ETIMEDOUT; | |
561 | } | |
562 | ||
31888234 AL |
563 | /* Must be called with SMI mutex held */ |
564 | static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
91da11f8 LB |
565 | { |
566 | int ret; | |
567 | ||
f3a8b6b6 AL |
568 | if (mv88e6xxx_6352_family(ds)) |
569 | port = (port + 1) << 5; | |
570 | ||
3675c8d7 | 571 | /* Snapshot the hardware statistics counters for this port. */ |
31888234 AL |
572 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
573 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
574 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
575 | if (ret < 0) | |
576 | return ret; | |
91da11f8 | 577 | |
3675c8d7 | 578 | /* Wait for the snapshotting to complete. */ |
31888234 | 579 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
580 | if (ret < 0) |
581 | return ret; | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
31888234 AL |
586 | /* Must be called with SMI mutex held */ |
587 | static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
91da11f8 LB |
588 | { |
589 | u32 _val; | |
590 | int ret; | |
591 | ||
592 | *val = 0; | |
593 | ||
31888234 AL |
594 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
595 | GLOBAL_STATS_OP_READ_CAPTURED | | |
596 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
597 | if (ret < 0) |
598 | return; | |
599 | ||
31888234 | 600 | ret = _mv88e6xxx_stats_wait(ds); |
91da11f8 LB |
601 | if (ret < 0) |
602 | return; | |
603 | ||
31888234 | 604 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
605 | if (ret < 0) |
606 | return; | |
607 | ||
608 | _val = ret << 16; | |
609 | ||
31888234 | 610 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
611 | if (ret < 0) |
612 | return; | |
613 | ||
614 | *val = _val | ret; | |
615 | } | |
616 | ||
e413e7e1 AL |
617 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
618 | { "in_good_octets", 8, 0x00, }, | |
619 | { "in_bad_octets", 4, 0x02, }, | |
620 | { "in_unicast", 4, 0x04, }, | |
621 | { "in_broadcasts", 4, 0x06, }, | |
622 | { "in_multicasts", 4, 0x07, }, | |
623 | { "in_pause", 4, 0x16, }, | |
624 | { "in_undersize", 4, 0x18, }, | |
625 | { "in_fragments", 4, 0x19, }, | |
626 | { "in_oversize", 4, 0x1a, }, | |
627 | { "in_jabber", 4, 0x1b, }, | |
628 | { "in_rx_error", 4, 0x1c, }, | |
629 | { "in_fcs_error", 4, 0x1d, }, | |
630 | { "out_octets", 8, 0x0e, }, | |
631 | { "out_unicast", 4, 0x10, }, | |
632 | { "out_broadcasts", 4, 0x13, }, | |
633 | { "out_multicasts", 4, 0x12, }, | |
634 | { "out_pause", 4, 0x15, }, | |
635 | { "excessive", 4, 0x11, }, | |
636 | { "collisions", 4, 0x1e, }, | |
637 | { "deferred", 4, 0x05, }, | |
638 | { "single", 4, 0x14, }, | |
639 | { "multiple", 4, 0x17, }, | |
640 | { "out_fcs_error", 4, 0x03, }, | |
641 | { "late", 4, 0x1f, }, | |
642 | { "hist_64bytes", 4, 0x08, }, | |
643 | { "hist_65_127bytes", 4, 0x09, }, | |
644 | { "hist_128_255bytes", 4, 0x0a, }, | |
645 | { "hist_256_511bytes", 4, 0x0b, }, | |
646 | { "hist_512_1023bytes", 4, 0x0c, }, | |
647 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
648 | /* Not all devices have the following counters */ | |
649 | { "sw_in_discards", 4, 0x110, }, | |
650 | { "sw_in_filtered", 2, 0x112, }, | |
651 | { "sw_out_filtered", 2, 0x113, }, | |
652 | ||
653 | }; | |
654 | ||
655 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
656 | { | |
657 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
658 | ||
659 | switch (ps->id) { | |
cca8b133 AL |
660 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
661 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
662 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
663 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
664 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
665 | return true; |
666 | default: | |
667 | return false; | |
668 | } | |
669 | } | |
670 | ||
671 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
672 | int nr_stats, | |
673 | struct mv88e6xxx_hw_stat *stats, | |
674 | int port, uint8_t *data) | |
91da11f8 LB |
675 | { |
676 | int i; | |
677 | ||
678 | for (i = 0; i < nr_stats; i++) { | |
679 | memcpy(data + i * ETH_GSTRING_LEN, | |
680 | stats[i].string, ETH_GSTRING_LEN); | |
681 | } | |
682 | } | |
683 | ||
80c4627b AL |
684 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds, |
685 | int stat, | |
686 | struct mv88e6xxx_hw_stat *stats, | |
687 | int port) | |
688 | { | |
689 | struct mv88e6xxx_hw_stat *s = stats + stat; | |
690 | u32 low; | |
691 | u32 high = 0; | |
692 | int ret; | |
693 | u64 value; | |
694 | ||
695 | if (s->reg >= 0x100) { | |
696 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
697 | s->reg - 0x100); | |
698 | if (ret < 0) | |
699 | return UINT64_MAX; | |
700 | ||
701 | low = ret; | |
702 | if (s->sizeof_stat == 4) { | |
703 | ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), | |
704 | s->reg - 0x100 + 1); | |
705 | if (ret < 0) | |
706 | return UINT64_MAX; | |
707 | high = ret; | |
708 | } | |
709 | } else { | |
710 | _mv88e6xxx_stats_read(ds, s->reg, &low); | |
711 | if (s->sizeof_stat == 8) | |
712 | _mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
713 | } | |
714 | value = (((u64)high) << 16) | low; | |
715 | return value; | |
716 | } | |
717 | ||
e413e7e1 AL |
718 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
719 | int nr_stats, | |
720 | struct mv88e6xxx_hw_stat *stats, | |
721 | int port, uint64_t *data) | |
91da11f8 | 722 | { |
a22adce5 | 723 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
724 | int ret; |
725 | int i; | |
726 | ||
31888234 | 727 | mutex_lock(&ps->smi_mutex); |
91da11f8 | 728 | |
31888234 | 729 | ret = _mv88e6xxx_stats_snapshot(ds, port); |
91da11f8 | 730 | if (ret < 0) { |
31888234 | 731 | mutex_unlock(&ps->smi_mutex); |
91da11f8 LB |
732 | return; |
733 | } | |
734 | ||
3675c8d7 | 735 | /* Read each of the counters. */ |
80c4627b AL |
736 | for (i = 0; i < nr_stats; i++) |
737 | data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port); | |
91da11f8 | 738 | |
31888234 | 739 | mutex_unlock(&ps->smi_mutex); |
91da11f8 | 740 | } |
98e67308 | 741 | |
e413e7e1 AL |
742 | /* All the statistics in the table */ |
743 | void | |
744 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
745 | { | |
746 | if (have_sw_in_discards(ds)) | |
747 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
748 | mv88e6xxx_hw_stats, port, data); | |
749 | else | |
750 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
751 | mv88e6xxx_hw_stats, port, data); | |
752 | } | |
753 | ||
754 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
755 | { | |
756 | if (have_sw_in_discards(ds)) | |
757 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
758 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
759 | } | |
760 | ||
761 | void | |
762 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
763 | int port, uint64_t *data) | |
764 | { | |
765 | if (have_sw_in_discards(ds)) | |
766 | _mv88e6xxx_get_ethtool_stats( | |
767 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
768 | mv88e6xxx_hw_stats, port, data); | |
769 | else | |
770 | _mv88e6xxx_get_ethtool_stats( | |
771 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
772 | mv88e6xxx_hw_stats, port, data); | |
773 | } | |
774 | ||
a1ab91f3 GR |
775 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
776 | { | |
777 | return 32 * sizeof(u16); | |
778 | } | |
779 | ||
780 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
781 | struct ethtool_regs *regs, void *_p) | |
782 | { | |
783 | u16 *p = _p; | |
784 | int i; | |
785 | ||
786 | regs->version = 0; | |
787 | ||
788 | memset(p, 0xff, 32 * sizeof(u16)); | |
789 | ||
790 | for (i = 0; i < 32; i++) { | |
791 | int ret; | |
792 | ||
793 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
794 | if (ret >= 0) | |
795 | p[i] = ret; | |
796 | } | |
797 | } | |
798 | ||
eaa23765 AL |
799 | #ifdef CONFIG_NET_DSA_HWMON |
800 | ||
801 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
802 | { | |
803 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
804 | int ret; | |
805 | int val; | |
806 | ||
807 | *temp = 0; | |
808 | ||
3898c148 | 809 | mutex_lock(&ps->smi_mutex); |
eaa23765 | 810 | |
fd3a0ee4 | 811 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); |
eaa23765 AL |
812 | if (ret < 0) |
813 | goto error; | |
814 | ||
815 | /* Enable temperature sensor */ | |
fd3a0ee4 | 816 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
817 | if (ret < 0) |
818 | goto error; | |
819 | ||
fd3a0ee4 | 820 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); |
eaa23765 AL |
821 | if (ret < 0) |
822 | goto error; | |
823 | ||
824 | /* Wait for temperature to stabilize */ | |
825 | usleep_range(10000, 12000); | |
826 | ||
fd3a0ee4 | 827 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
828 | if (val < 0) { |
829 | ret = val; | |
830 | goto error; | |
831 | } | |
832 | ||
833 | /* Disable temperature sensor */ | |
fd3a0ee4 | 834 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); |
eaa23765 AL |
835 | if (ret < 0) |
836 | goto error; | |
837 | ||
838 | *temp = ((val & 0x1f) - 5) * 5; | |
839 | ||
840 | error: | |
fd3a0ee4 | 841 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); |
3898c148 | 842 | mutex_unlock(&ps->smi_mutex); |
eaa23765 AL |
843 | return ret; |
844 | } | |
845 | #endif /* CONFIG_NET_DSA_HWMON */ | |
846 | ||
3898c148 AL |
847 | /* Must be called with SMI lock held */ |
848 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, | |
849 | u16 mask) | |
f3044683 AL |
850 | { |
851 | unsigned long timeout = jiffies + HZ / 10; | |
852 | ||
853 | while (time_before(jiffies, timeout)) { | |
854 | int ret; | |
855 | ||
3898c148 AL |
856 | ret = _mv88e6xxx_reg_read(ds, reg, offset); |
857 | if (ret < 0) | |
858 | return ret; | |
f3044683 AL |
859 | if (!(ret & mask)) |
860 | return 0; | |
861 | ||
862 | usleep_range(1000, 2000); | |
863 | } | |
864 | return -ETIMEDOUT; | |
865 | } | |
866 | ||
3898c148 AL |
867 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
868 | { | |
869 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
870 | int ret; | |
871 | ||
872 | mutex_lock(&ps->smi_mutex); | |
873 | ret = _mv88e6xxx_wait(ds, reg, offset, mask); | |
874 | mutex_unlock(&ps->smi_mutex); | |
875 | ||
876 | return ret; | |
877 | } | |
878 | ||
879 | static int _mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
f3044683 | 880 | { |
3898c148 AL |
881 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
882 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
883 | } |
884 | ||
885 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
886 | { | |
cca8b133 AL |
887 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
888 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
889 | } |
890 | ||
891 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
892 | { | |
cca8b133 AL |
893 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
894 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
895 | } |
896 | ||
facd95b2 GR |
897 | /* Must be called with SMI lock held */ |
898 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
899 | { | |
cca8b133 AL |
900 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
901 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
902 | } |
903 | ||
56d95e22 AL |
904 | /* Must be called with SMI lock held */ |
905 | static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds) | |
906 | { | |
907 | return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC, | |
908 | GLOBAL2_SCRATCH_BUSY); | |
909 | } | |
910 | ||
3898c148 | 911 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
912 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, |
913 | int regnum) | |
f3044683 AL |
914 | { |
915 | int ret; | |
916 | ||
3898c148 AL |
917 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
918 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | | |
919 | regnum); | |
920 | if (ret < 0) | |
921 | return ret; | |
f3044683 | 922 | |
3898c148 | 923 | ret = _mv88e6xxx_phy_wait(ds); |
f3044683 AL |
924 | if (ret < 0) |
925 | return ret; | |
926 | ||
3898c148 | 927 | return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
928 | } |
929 | ||
3898c148 | 930 | /* Must be called with SMI mutex held */ |
fd3a0ee4 AL |
931 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, |
932 | int regnum, u16 val) | |
f3044683 | 933 | { |
3898c148 AL |
934 | int ret; |
935 | ||
936 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); | |
937 | if (ret < 0) | |
938 | return ret; | |
f3044683 | 939 | |
3898c148 AL |
940 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
941 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | | |
942 | regnum); | |
943 | ||
944 | return _mv88e6xxx_phy_wait(ds); | |
f3044683 AL |
945 | } |
946 | ||
11b3b45d GR |
947 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
948 | { | |
2f40c698 | 949 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
950 | int reg; |
951 | ||
3898c148 | 952 | mutex_lock(&ps->smi_mutex); |
2f40c698 AL |
953 | |
954 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 955 | if (reg < 0) |
2f40c698 | 956 | goto out; |
11b3b45d GR |
957 | |
958 | e->eee_enabled = !!(reg & 0x0200); | |
959 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
960 | ||
3898c148 | 961 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 962 | if (reg < 0) |
2f40c698 | 963 | goto out; |
11b3b45d | 964 | |
cca8b133 | 965 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 966 | reg = 0; |
11b3b45d | 967 | |
2f40c698 | 968 | out: |
3898c148 | 969 | mutex_unlock(&ps->smi_mutex); |
2f40c698 | 970 | return reg; |
11b3b45d GR |
971 | } |
972 | ||
973 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
974 | struct phy_device *phydev, struct ethtool_eee *e) | |
975 | { | |
2f40c698 AL |
976 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
977 | int reg; | |
11b3b45d GR |
978 | int ret; |
979 | ||
3898c148 | 980 | mutex_lock(&ps->smi_mutex); |
11b3b45d | 981 | |
2f40c698 AL |
982 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
983 | if (ret < 0) | |
984 | goto out; | |
985 | ||
986 | reg = ret & ~0x0300; | |
987 | if (e->eee_enabled) | |
988 | reg |= 0x0200; | |
989 | if (e->tx_lpi_enabled) | |
990 | reg |= 0x0100; | |
991 | ||
992 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
993 | out: | |
3898c148 | 994 | mutex_unlock(&ps->smi_mutex); |
2f40c698 AL |
995 | |
996 | return ret; | |
11b3b45d GR |
997 | } |
998 | ||
facd95b2 GR |
999 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd) |
1000 | { | |
1001 | int ret; | |
1002 | ||
1003 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid); | |
1004 | if (ret < 0) | |
1005 | return ret; | |
1006 | ||
cca8b133 | 1007 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
1008 | if (ret < 0) |
1009 | return ret; | |
1010 | ||
1011 | return _mv88e6xxx_atu_wait(ds); | |
1012 | } | |
1013 | ||
1014 | static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid) | |
1015 | { | |
1016 | int ret; | |
1017 | ||
1018 | ret = _mv88e6xxx_atu_wait(ds); | |
1019 | if (ret < 0) | |
1020 | return ret; | |
1021 | ||
cca8b133 | 1022 | return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB); |
facd95b2 GR |
1023 | } |
1024 | ||
1025 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) | |
1026 | { | |
1027 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 1028 | int reg, ret = 0; |
facd95b2 GR |
1029 | u8 oldstate; |
1030 | ||
1031 | mutex_lock(&ps->smi_mutex); | |
1032 | ||
cca8b133 | 1033 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
1034 | if (reg < 0) { |
1035 | ret = reg; | |
facd95b2 | 1036 | goto abort; |
538cc282 | 1037 | } |
facd95b2 | 1038 | |
cca8b133 | 1039 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
1040 | if (oldstate != state) { |
1041 | /* Flush forwarding database if we're moving a port | |
1042 | * from Learning or Forwarding state to Disabled or | |
1043 | * Blocking or Listening state. | |
1044 | */ | |
cca8b133 AL |
1045 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
1046 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
facd95b2 GR |
1047 | ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]); |
1048 | if (ret) | |
1049 | goto abort; | |
1050 | } | |
cca8b133 AL |
1051 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
1052 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
1053 | reg); | |
facd95b2 GR |
1054 | } |
1055 | ||
1056 | abort: | |
1057 | mutex_unlock(&ps->smi_mutex); | |
1058 | return ret; | |
1059 | } | |
1060 | ||
1061 | /* Must be called with smi lock held */ | |
1062 | static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port) | |
1063 | { | |
1064 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1065 | u8 fid = ps->fid[port]; | |
1066 | u16 reg = fid << 12; | |
1067 | ||
1068 | if (dsa_is_cpu_port(ds, port)) | |
1069 | reg |= ds->phys_port_mask; | |
1070 | else | |
1071 | reg |= (ps->bridge_mask[fid] | | |
1072 | (1 << dsa_upstream_port(ds))) & ~(1 << port); | |
1073 | ||
cca8b133 | 1074 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
1075 | } |
1076 | ||
1077 | /* Must be called with smi lock held */ | |
1078 | static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid) | |
1079 | { | |
1080 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1081 | int port; | |
1082 | u32 mask; | |
1083 | int ret; | |
1084 | ||
1085 | mask = ds->phys_port_mask; | |
1086 | while (mask) { | |
1087 | port = __ffs(mask); | |
1088 | mask &= ~(1 << port); | |
1089 | if (ps->fid[port] != fid) | |
1090 | continue; | |
1091 | ||
1092 | ret = _mv88e6xxx_update_port_config(ds, port); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | } | |
1096 | ||
1097 | return _mv88e6xxx_flush_fid(ds, fid); | |
1098 | } | |
1099 | ||
1100 | /* Bridge handling functions */ | |
1101 | ||
1102 | int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1103 | { | |
1104 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1105 | int ret = 0; | |
1106 | u32 nmask; | |
1107 | int fid; | |
1108 | ||
1109 | /* If the bridge group is not empty, join that group. | |
1110 | * Otherwise create a new group. | |
1111 | */ | |
1112 | fid = ps->fid[port]; | |
1113 | nmask = br_port_mask & ~(1 << port); | |
1114 | if (nmask) | |
1115 | fid = ps->fid[__ffs(nmask)]; | |
1116 | ||
1117 | nmask = ps->bridge_mask[fid] | (1 << port); | |
1118 | if (nmask != br_port_mask) { | |
1119 | netdev_err(ds->ports[port], | |
1120 | "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1121 | fid, br_port_mask, nmask); | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | ||
1125 | mutex_lock(&ps->smi_mutex); | |
1126 | ||
1127 | ps->bridge_mask[fid] = br_port_mask; | |
1128 | ||
1129 | if (fid != ps->fid[port]) { | |
1130 | ps->fid_mask |= 1 << ps->fid[port]; | |
1131 | ps->fid[port] = fid; | |
1132 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1133 | } | |
1134 | ||
1135 | mutex_unlock(&ps->smi_mutex); | |
1136 | ||
1137 | return ret; | |
1138 | } | |
1139 | ||
1140 | int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1141 | { | |
1142 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1143 | u8 fid, newfid; | |
1144 | int ret; | |
1145 | ||
1146 | fid = ps->fid[port]; | |
1147 | ||
1148 | if (ps->bridge_mask[fid] != br_port_mask) { | |
1149 | netdev_err(ds->ports[port], | |
1150 | "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1151 | fid, br_port_mask, ps->bridge_mask[fid]); | |
1152 | return -EINVAL; | |
1153 | } | |
1154 | ||
1155 | /* If the port was the last port of a bridge, we are done. | |
1156 | * Otherwise assign a new fid to the port, and fix up | |
1157 | * the bridge configuration. | |
1158 | */ | |
1159 | if (br_port_mask == (1 << port)) | |
1160 | return 0; | |
1161 | ||
1162 | mutex_lock(&ps->smi_mutex); | |
1163 | ||
1164 | newfid = __ffs(ps->fid_mask); | |
1165 | ps->fid[port] = newfid; | |
40a71660 | 1166 | ps->fid_mask &= ~(1 << newfid); |
facd95b2 GR |
1167 | ps->bridge_mask[fid] &= ~(1 << port); |
1168 | ps->bridge_mask[newfid] = 1 << port; | |
1169 | ||
1170 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1171 | if (!ret) | |
1172 | ret = _mv88e6xxx_update_bridge_config(ds, newfid); | |
1173 | ||
1174 | mutex_unlock(&ps->smi_mutex); | |
1175 | ||
1176 | return ret; | |
1177 | } | |
1178 | ||
1179 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) | |
1180 | { | |
1181 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1182 | int stp_state; | |
1183 | ||
1184 | switch (state) { | |
1185 | case BR_STATE_DISABLED: | |
cca8b133 | 1186 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1187 | break; |
1188 | case BR_STATE_BLOCKING: | |
1189 | case BR_STATE_LISTENING: | |
cca8b133 | 1190 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1191 | break; |
1192 | case BR_STATE_LEARNING: | |
cca8b133 | 1193 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1194 | break; |
1195 | case BR_STATE_FORWARDING: | |
1196 | default: | |
cca8b133 | 1197 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1198 | break; |
1199 | } | |
1200 | ||
1201 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1202 | ||
1203 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1204 | * so we can not update the port state directly but need to schedule it. | |
1205 | */ | |
1206 | ps->port_state[port] = stp_state; | |
1207 | set_bit(port, &ps->port_state_update_mask); | |
1208 | schedule_work(&ps->bridge_work); | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
defb05b9 GR |
1213 | static int __mv88e6xxx_write_addr(struct dsa_switch *ds, |
1214 | const unsigned char *addr) | |
1215 | { | |
1216 | int i, ret; | |
1217 | ||
1218 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1219 | ret = _mv88e6xxx_reg_write( |
1220 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1221 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1222 | if (ret < 0) |
1223 | return ret; | |
1224 | } | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr) | |
1230 | { | |
1231 | int i, ret; | |
1232 | ||
1233 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1234 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1235 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1236 | if (ret < 0) |
1237 | return ret; | |
1238 | addr[i * 2] = ret >> 8; | |
1239 | addr[i * 2 + 1] = ret & 0xff; | |
1240 | } | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port, | |
1246 | const unsigned char *addr, int state) | |
1247 | { | |
1248 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1249 | u8 fid = ps->fid[port]; | |
1250 | int ret; | |
1251 | ||
1252 | ret = _mv88e6xxx_atu_wait(ds); | |
1253 | if (ret < 0) | |
1254 | return ret; | |
1255 | ||
1256 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1257 | if (ret < 0) | |
1258 | return ret; | |
1259 | ||
cca8b133 | 1260 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, |
defb05b9 GR |
1261 | (0x10 << port) | state); |
1262 | if (ret) | |
1263 | return ret; | |
1264 | ||
cca8b133 | 1265 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB); |
defb05b9 GR |
1266 | |
1267 | return ret; | |
1268 | } | |
1269 | ||
1270 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, | |
1271 | const unsigned char *addr, u16 vid) | |
1272 | { | |
1273 | int state = is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1274 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1275 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
defb05b9 GR |
1276 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1277 | int ret; | |
1278 | ||
1279 | mutex_lock(&ps->smi_mutex); | |
1280 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state); | |
1281 | mutex_unlock(&ps->smi_mutex); | |
1282 | ||
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, | |
1287 | const unsigned char *addr, u16 vid) | |
1288 | { | |
1289 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1290 | int ret; | |
1291 | ||
1292 | mutex_lock(&ps->smi_mutex); | |
cca8b133 AL |
1293 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, |
1294 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
defb05b9 GR |
1295 | mutex_unlock(&ps->smi_mutex); |
1296 | ||
1297 | return ret; | |
1298 | } | |
1299 | ||
1300 | static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port, | |
1301 | unsigned char *addr, bool *is_static) | |
1302 | { | |
1303 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1304 | u8 fid = ps->fid[port]; | |
1305 | int ret, state; | |
1306 | ||
1307 | ret = _mv88e6xxx_atu_wait(ds); | |
1308 | if (ret < 0) | |
1309 | return ret; | |
1310 | ||
1311 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1312 | if (ret < 0) | |
1313 | return ret; | |
1314 | ||
1315 | do { | |
cca8b133 | 1316 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
defb05b9 GR |
1317 | if (ret < 0) |
1318 | return ret; | |
1319 | ||
cca8b133 | 1320 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
defb05b9 GR |
1321 | if (ret < 0) |
1322 | return ret; | |
cca8b133 AL |
1323 | state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1324 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
defb05b9 GR |
1325 | return -ENOENT; |
1326 | } while (!(((ret >> 4) & 0xff) & (1 << port))); | |
1327 | ||
1328 | ret = __mv88e6xxx_read_addr(ds, addr); | |
1329 | if (ret < 0) | |
1330 | return ret; | |
1331 | ||
1332 | *is_static = state == (is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1333 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1334 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
defb05b9 GR |
1335 | |
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | /* get next entry for port */ | |
1340 | int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, | |
1341 | unsigned char *addr, bool *is_static) | |
1342 | { | |
1343 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1344 | int ret; | |
1345 | ||
1346 | mutex_lock(&ps->smi_mutex); | |
1347 | ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static); | |
1348 | mutex_unlock(&ps->smi_mutex); | |
1349 | ||
1350 | return ret; | |
1351 | } | |
1352 | ||
facd95b2 GR |
1353 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1354 | { | |
1355 | struct mv88e6xxx_priv_state *ps; | |
1356 | struct dsa_switch *ds; | |
1357 | int port; | |
1358 | ||
1359 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1360 | ds = ((struct dsa_switch *)ps) - 1; | |
1361 | ||
1362 | while (ps->port_state_update_mask) { | |
1363 | port = __ffs(ps->port_state_update_mask); | |
1364 | clear_bit(port, &ps->port_state_update_mask); | |
1365 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1366 | } | |
1367 | } | |
1368 | ||
dbde9e66 | 1369 | static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port) |
d827e88a GR |
1370 | { |
1371 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
facd95b2 | 1372 | int ret, fid; |
54d792f2 | 1373 | u16 reg; |
d827e88a GR |
1374 | |
1375 | mutex_lock(&ps->smi_mutex); | |
1376 | ||
54d792f2 AL |
1377 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || |
1378 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1379 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) || | |
1380 | mv88e6xxx_6065_family(ds)) { | |
1381 | /* MAC Forcing register: don't force link, speed, | |
1382 | * duplex or flow control state to any particular | |
1383 | * values on physical ports, but force the CPU port | |
1384 | * and all DSA ports to their maximum bandwidth and | |
1385 | * full duplex. | |
1386 | */ | |
1387 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); | |
1388 | if (dsa_is_cpu_port(ds, port) || | |
1389 | ds->dsa_port_mask & (1 << port)) { | |
1390 | reg |= PORT_PCS_CTRL_FORCE_LINK | | |
1391 | PORT_PCS_CTRL_LINK_UP | | |
1392 | PORT_PCS_CTRL_DUPLEX_FULL | | |
1393 | PORT_PCS_CTRL_FORCE_DUPLEX; | |
1394 | if (mv88e6xxx_6065_family(ds)) | |
1395 | reg |= PORT_PCS_CTRL_100; | |
1396 | else | |
1397 | reg |= PORT_PCS_CTRL_1000; | |
1398 | } else { | |
1399 | reg |= PORT_PCS_CTRL_UNFORCED; | |
1400 | } | |
1401 | ||
1402 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1403 | PORT_PCS_CTRL, reg); | |
1404 | if (ret) | |
1405 | goto abort; | |
1406 | } | |
1407 | ||
1408 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
1409 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
1410 | * tunneling, determine priority by looking at 802.1p and IP | |
1411 | * priority fields (IP prio has precedence), and set STP state | |
1412 | * to Forwarding. | |
1413 | * | |
1414 | * If this is the CPU link, use DSA or EDSA tagging depending | |
1415 | * on which tagging mode was configured. | |
1416 | * | |
1417 | * If this is a link to another switch, use DSA tagging mode. | |
1418 | * | |
1419 | * If this is the upstream port for this switch, enable | |
1420 | * forwarding of unknown unicasts and multicasts. | |
1421 | */ | |
1422 | reg = 0; | |
1423 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1424 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1425 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1426 | mv88e6xxx_6185_family(ds)) | |
1427 | reg = PORT_CONTROL_IGMP_MLD_SNOOP | | |
1428 | PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | | |
1429 | PORT_CONTROL_STATE_FORWARDING; | |
1430 | if (dsa_is_cpu_port(ds, port)) { | |
1431 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) | |
1432 | reg |= PORT_CONTROL_DSA_TAG; | |
1433 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1434 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1435 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1436 | reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; | |
1437 | else | |
1438 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1439 | } | |
1440 | ||
1441 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1442 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1443 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) || | |
1444 | mv88e6xxx_6185_family(ds)) { | |
1445 | if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) | |
1446 | reg |= PORT_CONTROL_EGRESS_ADD_TAG; | |
1447 | } | |
1448 | } | |
1449 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1450 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1451 | mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) { | |
1452 | if (ds->dsa_port_mask & (1 << port)) | |
1453 | reg |= PORT_CONTROL_FRAME_MODE_DSA; | |
1454 | if (port == dsa_upstream_port(ds)) | |
1455 | reg |= PORT_CONTROL_FORWARD_UNKNOWN | | |
1456 | PORT_CONTROL_FORWARD_UNKNOWN_MC; | |
1457 | } | |
1458 | if (reg) { | |
1459 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1460 | PORT_CONTROL, reg); | |
1461 | if (ret) | |
1462 | goto abort; | |
1463 | } | |
1464 | ||
1465 | /* Port Control 2: don't force a good FCS, set the maximum | |
1466 | * frame size to 10240 bytes, don't let the switch add or | |
1467 | * strip 802.1q tags, don't discard tagged or untagged frames | |
1468 | * on this port, do a destination address lookup on all | |
1469 | * received packets as usual, disable ARP mirroring and don't | |
1470 | * send a copy of all transmitted/received frames on this port | |
1471 | * to the CPU. | |
1472 | */ | |
1473 | reg = 0; | |
1474 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1475 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1476 | mv88e6xxx_6095_family(ds)) | |
1477 | reg = PORT_CONTROL_2_MAP_DA; | |
1478 | ||
1479 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1480 | mv88e6xxx_6165_family(ds)) | |
1481 | reg |= PORT_CONTROL_2_JUMBO_10240; | |
1482 | ||
1483 | if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) { | |
1484 | /* Set the upstream port this port should use */ | |
1485 | reg |= dsa_upstream_port(ds); | |
1486 | /* enable forwarding of unknown multicast addresses to | |
1487 | * the upstream port | |
1488 | */ | |
1489 | if (port == dsa_upstream_port(ds)) | |
1490 | reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; | |
1491 | } | |
1492 | ||
1493 | if (reg) { | |
1494 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1495 | PORT_CONTROL_2, reg); | |
1496 | if (ret) | |
1497 | goto abort; | |
1498 | } | |
1499 | ||
1500 | /* Port Association Vector: when learning source addresses | |
1501 | * of packets, add the address to the address database using | |
1502 | * a port bitmap that has only the bit for this port set and | |
1503 | * the other bits clear. | |
1504 | */ | |
1505 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, | |
1506 | 1 << port); | |
1507 | if (ret) | |
1508 | goto abort; | |
1509 | ||
1510 | /* Egress rate control 2: disable egress rate control. */ | |
1511 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2, | |
1512 | 0x0000); | |
1513 | if (ret) | |
1514 | goto abort; | |
1515 | ||
1516 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1517 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1518 | /* Do not limit the period of time that this port can | |
1519 | * be paused for by the remote end or the period of | |
1520 | * time that this port can pause the remote end. | |
1521 | */ | |
1522 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1523 | PORT_PAUSE_CTRL, 0x0000); | |
1524 | if (ret) | |
1525 | goto abort; | |
1526 | ||
1527 | /* Port ATU control: disable limiting the number of | |
1528 | * address database entries that this port is allowed | |
1529 | * to use. | |
1530 | */ | |
1531 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1532 | PORT_ATU_CONTROL, 0x0000); | |
1533 | /* Priority Override: disable DA, SA and VTU priority | |
1534 | * override. | |
1535 | */ | |
1536 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1537 | PORT_PRI_OVERRIDE, 0x0000); | |
1538 | if (ret) | |
1539 | goto abort; | |
1540 | ||
1541 | /* Port Ethertype: use the Ethertype DSA Ethertype | |
1542 | * value. | |
1543 | */ | |
1544 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1545 | PORT_ETH_TYPE, ETH_P_EDSA); | |
1546 | if (ret) | |
1547 | goto abort; | |
1548 | /* Tag Remap: use an identity 802.1p prio -> switch | |
1549 | * prio mapping. | |
1550 | */ | |
1551 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1552 | PORT_TAG_REGMAP_0123, 0x3210); | |
1553 | if (ret) | |
1554 | goto abort; | |
1555 | ||
1556 | /* Tag Remap 2: use an identity 802.1p prio -> switch | |
1557 | * prio mapping. | |
1558 | */ | |
1559 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1560 | PORT_TAG_REGMAP_4567, 0x7654); | |
1561 | if (ret) | |
1562 | goto abort; | |
1563 | } | |
1564 | ||
1565 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1566 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1567 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1568 | /* Rate Control: disable ingress rate limiting. */ | |
1569 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), | |
1570 | PORT_RATE_CONTROL, 0x0001); | |
1571 | if (ret) | |
1572 | goto abort; | |
1573 | } | |
1574 | ||
366f0a0f GR |
1575 | /* Port Control 1: disable trunking, disable sending |
1576 | * learning messages to this port. | |
d827e88a | 1577 | */ |
614f03fc | 1578 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000); |
d827e88a GR |
1579 | if (ret) |
1580 | goto abort; | |
1581 | ||
1582 | /* Port based VLAN map: give each port its own address | |
1583 | * database, allow the CPU port to talk to each of the 'real' | |
1584 | * ports, and allow each of the 'real' ports to only talk to | |
1585 | * the upstream port. | |
1586 | */ | |
facd95b2 GR |
1587 | fid = __ffs(ps->fid_mask); |
1588 | ps->fid[port] = fid; | |
1589 | ps->fid_mask &= ~(1 << fid); | |
1590 | ||
1591 | if (!dsa_is_cpu_port(ds, port)) | |
1592 | ps->bridge_mask[fid] = 1 << port; | |
d827e88a | 1593 | |
facd95b2 | 1594 | ret = _mv88e6xxx_update_port_config(ds, port); |
d827e88a GR |
1595 | if (ret) |
1596 | goto abort; | |
1597 | ||
1598 | /* Default VLAN ID and priority: don't set a default VLAN | |
1599 | * ID, and set the default packet priority to zero. | |
1600 | */ | |
47cf1e65 VD |
1601 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
1602 | 0x0000); | |
d827e88a GR |
1603 | abort: |
1604 | mutex_unlock(&ps->smi_mutex); | |
1605 | return ret; | |
1606 | } | |
1607 | ||
dbde9e66 AL |
1608 | int mv88e6xxx_setup_ports(struct dsa_switch *ds) |
1609 | { | |
1610 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1611 | int ret; | |
1612 | int i; | |
1613 | ||
1614 | for (i = 0; i < ps->num_ports; i++) { | |
1615 | ret = mv88e6xxx_setup_port(ds, i); | |
1616 | if (ret < 0) | |
1617 | return ret; | |
1618 | } | |
1619 | return 0; | |
1620 | } | |
1621 | ||
87c8cefb AL |
1622 | static int mv88e6xxx_regs_show(struct seq_file *s, void *p) |
1623 | { | |
1624 | struct dsa_switch *ds = s->private; | |
1625 | ||
1626 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1627 | int reg, port; | |
1628 | ||
1629 | seq_puts(s, " GLOBAL GLOBAL2 "); | |
1630 | for (port = 0 ; port < ps->num_ports; port++) | |
1631 | seq_printf(s, " %2d ", port); | |
1632 | seq_puts(s, "\n"); | |
1633 | ||
1634 | for (reg = 0; reg < 32; reg++) { | |
1635 | seq_printf(s, "%2x: ", reg); | |
1636 | seq_printf(s, " %4x %4x ", | |
1637 | mv88e6xxx_reg_read(ds, REG_GLOBAL, reg), | |
1638 | mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg)); | |
1639 | ||
1640 | for (port = 0 ; port < ps->num_ports; port++) | |
1641 | seq_printf(s, "%4x ", | |
1642 | mv88e6xxx_reg_read(ds, REG_PORT(port), reg)); | |
1643 | seq_puts(s, "\n"); | |
1644 | } | |
1645 | ||
1646 | return 0; | |
1647 | } | |
1648 | ||
1649 | static int mv88e6xxx_regs_open(struct inode *inode, struct file *file) | |
1650 | { | |
1651 | return single_open(file, mv88e6xxx_regs_show, inode->i_private); | |
1652 | } | |
1653 | ||
1654 | static const struct file_operations mv88e6xxx_regs_fops = { | |
1655 | .open = mv88e6xxx_regs_open, | |
1656 | .read = seq_read, | |
1657 | .llseek = no_llseek, | |
1658 | .release = single_release, | |
1659 | .owner = THIS_MODULE, | |
1660 | }; | |
1661 | ||
8a0a265d AL |
1662 | static void mv88e6xxx_atu_show_header(struct seq_file *s) |
1663 | { | |
1664 | seq_puts(s, "DB T/P Vec State Addr\n"); | |
1665 | } | |
1666 | ||
1667 | static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum, | |
1668 | unsigned char *addr, int data) | |
1669 | { | |
1670 | bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK); | |
1671 | int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >> | |
1672 | GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT); | |
1673 | int state = data & GLOBAL_ATU_DATA_STATE_MASK; | |
1674 | ||
1675 | seq_printf(s, "%03x %5s %10pb %x %pM\n", | |
1676 | dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr); | |
1677 | } | |
1678 | ||
1679 | static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds, | |
1680 | int dbnum) | |
1681 | { | |
1682 | unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
1683 | unsigned char addr[6]; | |
1684 | int ret, data, state; | |
1685 | ||
1686 | ret = __mv88e6xxx_write_addr(ds, bcast); | |
1687 | if (ret < 0) | |
1688 | return ret; | |
1689 | ||
1690 | do { | |
1691 | ret = _mv88e6xxx_atu_cmd(ds, dbnum, GLOBAL_ATU_OP_GET_NEXT_DB); | |
1692 | if (ret < 0) | |
1693 | return ret; | |
1694 | data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); | |
1695 | if (data < 0) | |
1696 | return data; | |
1697 | ||
1698 | state = data & GLOBAL_ATU_DATA_STATE_MASK; | |
1699 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
1700 | break; | |
1701 | ret = __mv88e6xxx_read_addr(ds, addr); | |
1702 | if (ret < 0) | |
1703 | return ret; | |
1704 | mv88e6xxx_atu_show_entry(s, dbnum, addr, data); | |
1705 | } while (state != GLOBAL_ATU_DATA_STATE_UNUSED); | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
1710 | static int mv88e6xxx_atu_show(struct seq_file *s, void *p) | |
1711 | { | |
1712 | struct dsa_switch *ds = s->private; | |
1713 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1714 | int dbnum; | |
1715 | ||
1716 | mv88e6xxx_atu_show_header(s); | |
1717 | ||
1718 | for (dbnum = 0; dbnum < 255; dbnum++) { | |
1719 | mutex_lock(&ps->smi_mutex); | |
1720 | mv88e6xxx_atu_show_db(s, ds, dbnum); | |
1721 | mutex_unlock(&ps->smi_mutex); | |
1722 | } | |
1723 | ||
1724 | return 0; | |
1725 | } | |
1726 | ||
1727 | static int mv88e6xxx_atu_open(struct inode *inode, struct file *file) | |
1728 | { | |
1729 | return single_open(file, mv88e6xxx_atu_show, inode->i_private); | |
1730 | } | |
1731 | ||
1732 | static const struct file_operations mv88e6xxx_atu_fops = { | |
1733 | .open = mv88e6xxx_atu_open, | |
1734 | .read = seq_read, | |
1735 | .llseek = no_llseek, | |
1736 | .release = single_release, | |
1737 | .owner = THIS_MODULE, | |
1738 | }; | |
1739 | ||
532c7a35 AL |
1740 | static void mv88e6xxx_stats_show_header(struct seq_file *s, |
1741 | struct mv88e6xxx_priv_state *ps) | |
1742 | { | |
1743 | int port; | |
1744 | ||
1745 | seq_puts(s, " Statistic "); | |
1746 | for (port = 0 ; port < ps->num_ports; port++) | |
1747 | seq_printf(s, "Port %2d ", port); | |
1748 | seq_puts(s, "\n"); | |
1749 | } | |
1750 | ||
1751 | static int mv88e6xxx_stats_show(struct seq_file *s, void *p) | |
1752 | { | |
1753 | struct dsa_switch *ds = s->private; | |
1754 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1755 | struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats; | |
1756 | int port, stat, max_stats; | |
1757 | uint64_t value; | |
1758 | ||
1759 | if (have_sw_in_discards(ds)) | |
1760 | max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats); | |
1761 | else | |
1762 | max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
1763 | ||
1764 | mv88e6xxx_stats_show_header(s, ps); | |
1765 | ||
1766 | mutex_lock(&ps->smi_mutex); | |
1767 | ||
1768 | for (stat = 0; stat < max_stats; stat++) { | |
1769 | seq_printf(s, "%19s: ", stats[stat].string); | |
1770 | for (port = 0 ; port < ps->num_ports; port++) { | |
1771 | _mv88e6xxx_stats_snapshot(ds, port); | |
1772 | value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats, | |
1773 | port); | |
1774 | seq_printf(s, "%8llu ", value); | |
1775 | } | |
1776 | seq_puts(s, "\n"); | |
1777 | } | |
1778 | mutex_unlock(&ps->smi_mutex); | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | static int mv88e6xxx_stats_open(struct inode *inode, struct file *file) | |
1784 | { | |
1785 | return single_open(file, mv88e6xxx_stats_show, inode->i_private); | |
1786 | } | |
1787 | ||
1788 | static const struct file_operations mv88e6xxx_stats_fops = { | |
1789 | .open = mv88e6xxx_stats_open, | |
1790 | .read = seq_read, | |
1791 | .llseek = no_llseek, | |
1792 | .release = single_release, | |
1793 | .owner = THIS_MODULE, | |
1794 | }; | |
1795 | ||
d35bd876 AL |
1796 | static int mv88e6xxx_device_map_show(struct seq_file *s, void *p) |
1797 | { | |
1798 | struct dsa_switch *ds = s->private; | |
1799 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1800 | int target, ret; | |
1801 | ||
1802 | seq_puts(s, "Target Port\n"); | |
1803 | ||
1804 | mutex_lock(&ps->smi_mutex); | |
1805 | for (target = 0; target < 32; target++) { | |
1806 | ret = _mv88e6xxx_reg_write( | |
1807 | ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1808 | target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT); | |
1809 | if (ret < 0) | |
1810 | goto out; | |
1811 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2, | |
1812 | GLOBAL2_DEVICE_MAPPING); | |
1813 | seq_printf(s, " %2d %2d\n", target, | |
1814 | ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK); | |
1815 | } | |
1816 | out: | |
1817 | mutex_unlock(&ps->smi_mutex); | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | ||
1822 | static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file) | |
1823 | { | |
1824 | return single_open(file, mv88e6xxx_device_map_show, inode->i_private); | |
1825 | } | |
1826 | ||
1827 | static const struct file_operations mv88e6xxx_device_map_fops = { | |
1828 | .open = mv88e6xxx_device_map_open, | |
1829 | .read = seq_read, | |
1830 | .llseek = no_llseek, | |
1831 | .release = single_release, | |
1832 | .owner = THIS_MODULE, | |
1833 | }; | |
1834 | ||
56d95e22 AL |
1835 | static int mv88e6xxx_scratch_show(struct seq_file *s, void *p) |
1836 | { | |
1837 | struct dsa_switch *ds = s->private; | |
1838 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1839 | int reg, ret; | |
1840 | ||
1841 | seq_puts(s, "Register Value\n"); | |
1842 | ||
1843 | mutex_lock(&ps->smi_mutex); | |
1844 | for (reg = 0; reg < 0x80; reg++) { | |
1845 | ret = _mv88e6xxx_reg_write( | |
1846 | ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC, | |
1847 | reg << GLOBAL2_SCRATCH_REGISTER_SHIFT); | |
1848 | if (ret < 0) | |
1849 | goto out; | |
1850 | ||
1851 | ret = _mv88e6xxx_scratch_wait(ds); | |
1852 | if (ret < 0) | |
1853 | goto out; | |
1854 | ||
1855 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2, | |
1856 | GLOBAL2_SCRATCH_MISC); | |
1857 | seq_printf(s, " %2x %2x\n", reg, | |
1858 | ret & GLOBAL2_SCRATCH_VALUE_MASK); | |
1859 | } | |
1860 | out: | |
1861 | mutex_unlock(&ps->smi_mutex); | |
1862 | ||
1863 | return 0; | |
1864 | } | |
1865 | ||
1866 | static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file) | |
1867 | { | |
1868 | return single_open(file, mv88e6xxx_scratch_show, inode->i_private); | |
1869 | } | |
1870 | ||
1871 | static const struct file_operations mv88e6xxx_scratch_fops = { | |
1872 | .open = mv88e6xxx_scratch_open, | |
1873 | .read = seq_read, | |
1874 | .llseek = no_llseek, | |
1875 | .release = single_release, | |
1876 | .owner = THIS_MODULE, | |
1877 | }; | |
1878 | ||
acdaffcc GR |
1879 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
1880 | { | |
1881 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
87c8cefb | 1882 | char *name; |
acdaffcc GR |
1883 | |
1884 | mutex_init(&ps->smi_mutex); | |
acdaffcc | 1885 | |
cca8b133 | 1886 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 1887 | |
facd95b2 GR |
1888 | ps->fid_mask = (1 << DSA_MAX_PORTS) - 1; |
1889 | ||
1890 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); | |
1891 | ||
87c8cefb AL |
1892 | name = kasprintf(GFP_KERNEL, "dsa%d", ds->index); |
1893 | ps->dbgfs = debugfs_create_dir(name, NULL); | |
1894 | kfree(name); | |
1895 | ||
1896 | debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds, | |
1897 | &mv88e6xxx_regs_fops); | |
1898 | ||
8a0a265d AL |
1899 | debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds, |
1900 | &mv88e6xxx_atu_fops); | |
1901 | ||
532c7a35 AL |
1902 | debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds, |
1903 | &mv88e6xxx_stats_fops); | |
1904 | ||
d35bd876 AL |
1905 | debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds, |
1906 | &mv88e6xxx_device_map_fops); | |
56d95e22 AL |
1907 | |
1908 | debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds, | |
1909 | &mv88e6xxx_scratch_fops); | |
acdaffcc GR |
1910 | return 0; |
1911 | } | |
1912 | ||
54d792f2 AL |
1913 | int mv88e6xxx_setup_global(struct dsa_switch *ds) |
1914 | { | |
1915 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1916 | int i; | |
1917 | ||
1918 | /* Set the default address aging time to 5 minutes, and | |
1919 | * enable address learn messages to be sent to all message | |
1920 | * ports. | |
1921 | */ | |
1922 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, | |
1923 | 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); | |
1924 | ||
1925 | /* Configure the IP ToS mapping registers. */ | |
1926 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); | |
1927 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
1928 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
1929 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
1930 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
1931 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
1932 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
1933 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
1934 | ||
1935 | /* Configure the IEEE 802.1p priority mapping register. */ | |
1936 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); | |
1937 | ||
1938 | /* Send all frames with destination addresses matching | |
1939 | * 01:80:c2:00:00:0x to the CPU port. | |
1940 | */ | |
1941 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); | |
1942 | ||
1943 | /* Ignore removed tag data on doubly tagged packets, disable | |
1944 | * flow control messages, force flow control priority to the | |
1945 | * highest, and send all special multicast frames to the CPU | |
1946 | * port at the highest priority. | |
1947 | */ | |
1948 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, | |
1949 | 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | | |
1950 | GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); | |
1951 | ||
1952 | /* Program the DSA routing table. */ | |
1953 | for (i = 0; i < 32; i++) { | |
1954 | int nexthop = 0x1f; | |
1955 | ||
1956 | if (ds->pd->rtable && | |
1957 | i != ds->index && i < ds->dst->pd->nr_chips) | |
1958 | nexthop = ds->pd->rtable[i] & 0x1f; | |
1959 | ||
1960 | REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, | |
1961 | GLOBAL2_DEVICE_MAPPING_UPDATE | | |
1962 | (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | | |
1963 | nexthop); | |
1964 | } | |
1965 | ||
1966 | /* Clear all trunk masks. */ | |
1967 | for (i = 0; i < 8; i++) | |
1968 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK, | |
1969 | 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | | |
1970 | ((1 << ps->num_ports) - 1)); | |
1971 | ||
1972 | /* Clear all trunk mappings. */ | |
1973 | for (i = 0; i < 16; i++) | |
1974 | REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, | |
1975 | GLOBAL2_TRUNK_MAPPING_UPDATE | | |
1976 | (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); | |
1977 | ||
1978 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1979 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) { | |
1980 | /* Send all frames with destination addresses matching | |
1981 | * 01:80:c2:00:00:2x to the CPU port. | |
1982 | */ | |
1983 | REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff); | |
1984 | ||
1985 | /* Initialise cross-chip port VLAN table to reset | |
1986 | * defaults. | |
1987 | */ | |
1988 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000); | |
1989 | ||
1990 | /* Clear the priority override table. */ | |
1991 | for (i = 0; i < 16; i++) | |
1992 | REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, | |
1993 | 0x8000 | (i << 8)); | |
1994 | } | |
1995 | ||
1996 | if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) || | |
1997 | mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) || | |
1998 | mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) { | |
1999 | /* Disable ingress rate limiting by resetting all | |
2000 | * ingress rate limit registers to their initial | |
2001 | * state. | |
2002 | */ | |
2003 | for (i = 0; i < ps->num_ports; i++) | |
2004 | REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP, | |
2005 | 0x9000 | (i << 8)); | |
2006 | } | |
2007 | ||
db687a56 AL |
2008 | /* Clear the statistics counters for all ports */ |
2009 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); | |
2010 | ||
2011 | /* Wait for the flush to complete. */ | |
2012 | _mv88e6xxx_stats_wait(ds); | |
2013 | ||
54d792f2 AL |
2014 | return 0; |
2015 | } | |
2016 | ||
143a8307 AL |
2017 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
2018 | { | |
2019 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2020 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
2021 | unsigned long timeout; | |
2022 | int ret; | |
2023 | int i; | |
2024 | ||
2025 | /* Set all ports to the disabled state. */ | |
2026 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
2027 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
2028 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
2029 | } |
2030 | ||
2031 | /* Wait for transmit queues to drain. */ | |
2032 | usleep_range(2000, 4000); | |
2033 | ||
2034 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
2035 | * needs to be active to support indirect phy register access | |
2036 | * through global registers 0x18 and 0x19. | |
2037 | */ | |
2038 | if (ppu_active) | |
2039 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
2040 | else | |
2041 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
2042 | ||
2043 | /* Wait up to one second for reset to complete. */ | |
2044 | timeout = jiffies + 1 * HZ; | |
2045 | while (time_before(jiffies, timeout)) { | |
2046 | ret = REG_READ(REG_GLOBAL, 0x00); | |
2047 | if ((ret & is_reset) == is_reset) | |
2048 | break; | |
2049 | usleep_range(1000, 2000); | |
2050 | } | |
2051 | if (time_after(jiffies, timeout)) | |
2052 | return -ETIMEDOUT; | |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
49143585 AL |
2057 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
2058 | { | |
2059 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2060 | int ret; | |
2061 | ||
3898c148 | 2062 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2063 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2064 | if (ret < 0) |
2065 | goto error; | |
fd3a0ee4 | 2066 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 2067 | error: |
fd3a0ee4 | 2068 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2069 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2070 | return ret; |
2071 | } | |
2072 | ||
2073 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
2074 | int reg, int val) | |
2075 | { | |
2076 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2077 | int ret; | |
2078 | ||
3898c148 | 2079 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2080 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
2081 | if (ret < 0) |
2082 | goto error; | |
2083 | ||
fd3a0ee4 | 2084 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 2085 | error: |
fd3a0ee4 | 2086 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
3898c148 | 2087 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2088 | return ret; |
2089 | } | |
2090 | ||
2091 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
2092 | { | |
2093 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2094 | ||
2095 | if (port >= 0 && port < ps->num_ports) | |
2096 | return port; | |
2097 | return -EINVAL; | |
2098 | } | |
2099 | ||
2100 | int | |
2101 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
2102 | { | |
2103 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2104 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2105 | int ret; | |
2106 | ||
2107 | if (addr < 0) | |
2108 | return addr; | |
2109 | ||
3898c148 | 2110 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2111 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); |
3898c148 | 2112 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2113 | return ret; |
2114 | } | |
2115 | ||
2116 | int | |
2117 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
2118 | { | |
2119 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2120 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2121 | int ret; | |
2122 | ||
2123 | if (addr < 0) | |
2124 | return addr; | |
2125 | ||
3898c148 | 2126 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2127 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); |
3898c148 | 2128 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2129 | return ret; |
2130 | } | |
2131 | ||
2132 | int | |
2133 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
2134 | { | |
2135 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2136 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2137 | int ret; | |
2138 | ||
2139 | if (addr < 0) | |
2140 | return addr; | |
2141 | ||
3898c148 | 2142 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2143 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); |
3898c148 | 2144 | mutex_unlock(&ps->smi_mutex); |
fd3a0ee4 AL |
2145 | return ret; |
2146 | } | |
2147 | ||
2148 | int | |
2149 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
2150 | u16 val) | |
2151 | { | |
2152 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
2153 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
2154 | int ret; | |
2155 | ||
2156 | if (addr < 0) | |
2157 | return addr; | |
2158 | ||
3898c148 | 2159 | mutex_lock(&ps->smi_mutex); |
fd3a0ee4 | 2160 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); |
3898c148 | 2161 | mutex_unlock(&ps->smi_mutex); |
49143585 AL |
2162 | return ret; |
2163 | } | |
2164 | ||
98e67308 BH |
2165 | static int __init mv88e6xxx_init(void) |
2166 | { | |
2167 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2168 | register_switch_driver(&mv88e6131_switch_driver); | |
2169 | #endif | |
2170 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
2171 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 2172 | #endif |
3ad50cca GR |
2173 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2174 | register_switch_driver(&mv88e6352_switch_driver); | |
2175 | #endif | |
42f27253 AL |
2176 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2177 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
2178 | #endif |
2179 | return 0; | |
2180 | } | |
2181 | module_init(mv88e6xxx_init); | |
2182 | ||
2183 | static void __exit mv88e6xxx_cleanup(void) | |
2184 | { | |
42f27253 AL |
2185 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
2186 | unregister_switch_driver(&mv88e6171_switch_driver); | |
2187 | #endif | |
4212b543 VD |
2188 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
2189 | unregister_switch_driver(&mv88e6352_switch_driver); | |
2190 | #endif | |
98e67308 BH |
2191 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
2192 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
2193 | #endif | |
2194 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
2195 | unregister_switch_driver(&mv88e6131_switch_driver); | |
2196 | #endif | |
2197 | } | |
2198 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
2199 | |
2200 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
2201 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
2202 | MODULE_LICENSE("GPL"); |