[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx.c

/*
 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
 * will be directly accessible on some {device address,register address}
 * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
 * will only respond to SMI transactions to that specific address, and
 * an indirect addressing mechanism needs to be used to access its
 * registers.
 */
static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
{
	int ret;
	int i;

	for (i = 0; i < 16; i++) {
		ret = mdiobus_read(bus, sw_addr, 0);
		if (ret < 0)
			return ret;

		if ((ret & 0x8000) == 0)
			return 0;
	}

	return -ETIMEDOUT;
}

int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
{
	int ret;

	if (sw_addr == 0)
		return mdiobus_read(bus, addr, reg);

	/* Wait for the bus to become free. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Transmit the read command. */
	ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
	if (ret < 0)
		return ret;

	/* Wait for the read command to complete. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Read the data. */
	ret = mdiobus_read(bus, sw_addr, 1);
	if (ret < 0)
		return ret;

	return ret & 0xffff;
}

int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
	int ret;

	if (bus == NULL)
		return -EINVAL;

	mutex_lock(&ps->smi_mutex);
	ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
	mutex_unlock(&ps->smi_mutex);

	return ret;
}

int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
			  int reg, u16 val)
{
	int ret;

	if (sw_addr == 0)
		return mdiobus_write(bus, addr, reg, val);

	/* Wait for the bus to become free. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	/* Transmit the data to write. */
	ret = mdiobus_write(bus, sw_addr, 1, val);
	if (ret < 0)
		return ret;

	/* Transmit the write command. */
	ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
	if (ret < 0)
		return ret;

	/* Wait for the write command to complete. */
	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	if (ret < 0)
		return ret;

	return 0;
}

int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
	int ret;

	if (bus == NULL)
		return -EINVAL;

	mutex_lock(&ps->smi_mutex);
	ret = __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
	mutex_unlock(&ps->smi_mutex);

	return ret;
}

int mv88e6xxx_config_prio(struct dsa_switch *ds)
{
	/* Configure the IP ToS mapping registers. */
	REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
	REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
	REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
	REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
	REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
	REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
	REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
	REG_WRITE(REG_GLOBAL, 0x17, 0xffff);

	/* Configure the IEEE 802.1p priority mapping register. */
	REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);

	return 0;
}

int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
{
	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);

	return 0;
}

int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
{
	int i;
	int ret;

	for (i = 0; i < 6; i++) {
		int j;

		/* Write the MAC address byte. */
		REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);

		/* Wait for the write to complete. */
		for (j = 0; j < 16; j++) {
			ret = REG_READ(REG_GLOBAL2, 0x0d);
			if ((ret & 0x8000) == 0)
				break;
		}
		if (j == 16)
			return -ETIMEDOUT;
	}

	return 0;
}

int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
{
	if (addr >= 0)
		return mv88e6xxx_reg_read(ds, addr, regnum);
	return 0xffff;
}

int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
{
	if (addr >= 0)
		return mv88e6xxx_reg_write(ds, addr, regnum, val);
	return 0;
}

#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
{
	int ret;
	unsigned long timeout;

	ret = REG_READ(REG_GLOBAL, 0x04);
	REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);

	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		usleep_range(1000, 2000);
		if ((ret & 0xc000) != 0xc000)
			return 0;
	}

	return -ETIMEDOUT;
}

static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
{
	int ret;
	unsigned long timeout;

	ret = REG_READ(REG_GLOBAL, 0x04);
	REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);

	timeout = jiffies + 1 * HZ;
	while (time_before(jiffies, timeout)) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		usleep_range(1000, 2000);
		if ((ret & 0xc000) == 0xc000)
			return 0;
	}

	return -ETIMEDOUT;
}

static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
{
	struct mv88e6xxx_priv_state *ps;

	ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
	if (mutex_trylock(&ps->ppu_mutex)) {
		struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;

		if (mv88e6xxx_ppu_enable(ds) == 0)
			ps->ppu_disabled = 0;
		mutex_unlock(&ps->ppu_mutex);
	}
}

static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
{
	struct mv88e6xxx_priv_state *ps = (void *)_ps;

	schedule_work(&ps->ppu_work);
}

static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;

	mutex_lock(&ps->ppu_mutex);

	/* If the PHY polling unit is enabled, disable it so that
	 * we can access the PHY registers.  If it was already
	 * disabled, cancel the timer that is going to re-enable
	 * it.
	 */
	if (!ps->ppu_disabled) {
		ret = mv88e6xxx_ppu_disable(ds);
		if (ret < 0) {
			mutex_unlock(&ps->ppu_mutex);
			return ret;
		}
		ps->ppu_disabled = 1;
	} else {
		del_timer(&ps->ppu_timer);
		ret = 0;
	}

	return ret;
}

static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	/* Schedule a timer to re-enable the PHY polling unit. */
	mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
	mutex_unlock(&ps->ppu_mutex);
}

void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);

	mutex_init(&ps->ppu_mutex);
	INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
	init_timer(&ps->ppu_timer);
	ps->ppu_timer.data = (unsigned long)ps;
	ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
}

int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
{
	int ret;

	ret = mv88e6xxx_ppu_access_get(ds);
	if (ret >= 0) {
		ret = mv88e6xxx_reg_read(ds, addr, regnum);
		mv88e6xxx_ppu_access_put(ds);
	}

	return ret;
}

int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
			    int regnum, u16 val)
{
	int ret;

	ret = mv88e6xxx_ppu_access_get(ds);
	if (ret >= 0) {
		ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
		mv88e6xxx_ppu_access_put(ds);
	}

	return ret;
}
#endif

void mv88e6xxx_poll_link(struct dsa_switch *ds)
{
	int i;

	for (i = 0; i < DSA_MAX_PORTS; i++) {
		struct net_device *dev;
		int uninitialized_var(port_status);
		int link;
		int speed;
		int duplex;
		int fc;

		dev = ds->ports[i];
		if (dev == NULL)
			continue;

		link = 0;
		if (dev->flags & IFF_UP) {
			port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
			if (port_status < 0)
				continue;

			link = !!(port_status & 0x0800);
		}

		if (!link) {
			if (netif_carrier_ok(dev)) {
				netdev_info(dev, "link down\n");
				netif_carrier_off(dev);
			}
			continue;
		}

		switch (port_status & 0x0300) {
		case 0x0000:
			speed = 10;
			break;
		case 0x0100:
			speed = 100;
			break;
		case 0x0200:
			speed = 1000;
			break;
		default:
			speed = -1;
			break;
		}
		duplex = (port_status & 0x0400) ? 1 : 0;
		fc = (port_status & 0x8000) ? 1 : 0;

		if (!netif_carrier_ok(dev)) {
			netdev_info(dev,
				    "link up, %d Mb/s, %s duplex, flow control %sabled\n",
				    speed,
				    duplex ? "full" : "half",
				    fc ? "en" : "dis");
			netif_carrier_on(dev);
		}
	}
}

static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
{
	int ret;
	int i;

	for (i = 0; i < 10; i++) {
		ret = REG_READ(REG_GLOBAL, 0x1d);
		if ((ret & 0x8000) == 0)
			return 0;
	}

	return -ETIMEDOUT;
}

static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
{
	int ret;

	/* Snapshot the hardware statistics counters for this port. */
	REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);

	/* Wait for the snapshotting to complete. */
	ret = mv88e6xxx_stats_wait(ds);
	if (ret < 0)
		return ret;

	return 0;
}

static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
{
	u32 _val;
	int ret;

	*val = 0;

	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
	if (ret < 0)
		return;

	ret = mv88e6xxx_stats_wait(ds);
	if (ret < 0)
		return;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
	if (ret < 0)
		return;

	_val = ret << 16;

	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
	if (ret < 0)
		return;

	*val = _val | ret;
}

void mv88e6xxx_get_strings(struct dsa_switch *ds,
			   int nr_stats, struct mv88e6xxx_hw_stat *stats,
			   int port, uint8_t *data)
{
	int i;

	for (i = 0; i < nr_stats; i++) {
		memcpy(data + i * ETH_GSTRING_LEN,
		       stats[i].string, ETH_GSTRING_LEN);
	}
}

void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
				 int nr_stats, struct mv88e6xxx_hw_stat *stats,
				 int port, uint64_t *data)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;
	int i;

	mutex_lock(&ps->stats_mutex);

	ret = mv88e6xxx_stats_snapshot(ds, port);
	if (ret < 0) {
		mutex_unlock(&ps->stats_mutex);
		return;
	}

	/* Read each of the counters. */
	for (i = 0; i < nr_stats; i++) {
		struct mv88e6xxx_hw_stat *s = stats + i;
		u32 low;
		u32 high = 0;

		if (s->reg >= 0x100) {
			int ret;

			ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
						 s->reg - 0x100);
			if (ret < 0)
				goto error;
			low = ret;
			if (s->sizeof_stat == 4) {
				ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
							 s->reg - 0x100 + 1);
				if (ret < 0)
					goto error;
				high = ret;
			}
			data[i] = (((u64)high) << 16) | low;
			continue;
		}
		mv88e6xxx_stats_read(ds, s->reg, &low);
		if (s->sizeof_stat == 8)
			mv88e6xxx_stats_read(ds, s->reg + 1, &high);

		data[i] = (((u64)high) << 32) | low;
	}
error:
	mutex_unlock(&ps->stats_mutex);
}

int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
{
	return 32 * sizeof(u16);
}

void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
			struct ethtool_regs *regs, void *_p)
{
	u16 *p = _p;
	int i;

	regs->version = 0;

	memset(p, 0xff, 32 * sizeof(u16));

	for (i = 0; i < 32; i++) {
		int ret;

		ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
		if (ret >= 0)
			p[i] = ret;
	}
}

#ifdef CONFIG_NET_DSA_HWMON

int  mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
{
	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	int ret;
	int val;

	*temp = 0;

	mutex_lock(&ps->phy_mutex);

	ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
	if (ret < 0)
		goto error;

	/* Enable temperature sensor */
	ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	if (ret < 0)
		goto error;

	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
	if (ret < 0)
		goto error;

	/* Wait for temperature to stabilize */
	usleep_range(10000, 12000);

	val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	if (val < 0) {
		ret = val;
		goto error;
	}

	/* Disable temperature sensor */
	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
	if (ret < 0)
		goto error;

	*temp = ((val & 0x1f) - 5) * 5;

error:
	mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
	mutex_unlock(&ps->phy_mutex);
	return ret;
}
#endif /* CONFIG_NET_DSA_HWMON */

static int __init mv88e6xxx_init(void)
{
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	register_switch_driver(&mv88e6131_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	register_switch_driver(&mv88e6123_61_65_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
	register_switch_driver(&mv88e6352_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	register_switch_driver(&mv88e6171_switch_driver);
#endif
	return 0;
}
module_init(mv88e6xxx_init);

static void __exit mv88e6xxx_cleanup(void)
{
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	unregister_switch_driver(&mv88e6171_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	unregister_switch_driver(&mv88e6123_61_65_switch_driver);
#endif
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	unregister_switch_driver(&mv88e6131_switch_driver);
#endif
}
module_exit(mv88e6xxx_cleanup);

MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
MODULE_LICENSE("GPL");
Commit	Line	Data
91da11f8 LB	1	/*
	2	* net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
	3	* Copyright (c) 2008 Marvell Semiconductor
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
19b2f97e BG	11	#include <linux/delay.h>
19b2f97e BG	12	#include <linux/jiffies.h>
91da11f8	13	#include <linux/list.h>
2bbba277	14	#include <linux/module.h>
91da11f8 LB	15	#include <linux/netdevice.h>
91da11f8 LB	16	#include <linux/phy.h>
c8f0b869	17	#include <net/dsa.h>
91da11f8 LB	18	#include "mv88e6xxx.h"
91da11f8 LB	19
3675c8d7	20	/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8 LB	21	* use all 32 SMI bus addresses on its SMI bus, and all switch registers
	22	* will be directly accessible on some {device address,register address}
	23	* pair. If the ADDR[4:0] pins are not strapped to zero, the switch
	24	* will only respond to SMI transactions to that specific address, and
	25	* an indirect addressing mechanism needs to be used to access its
	26	* registers.
	27	*/
	28	static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
	29	{
	30	int ret;
	31	int i;
	32
	33	for (i = 0; i < 16; i++) {
	34	ret = mdiobus_read(bus, sw_addr, 0);
	35	if (ret < 0)
	36	return ret;
	37
	38	if ((ret & 0x8000) == 0)
	39	return 0;
	40	}
	41
	42	return -ETIMEDOUT;
	43	}
	44
	45	int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
	46	{
	47	int ret;
	48
	49	if (sw_addr == 0)
	50	return mdiobus_read(bus, addr, reg);
	51
3675c8d7	52	/* Wait for the bus to become free. */
91da11f8 LB	53	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	54	if (ret < 0)
	55	return ret;
	56
3675c8d7	57	/* Transmit the read command. */
91da11f8 LB	58	ret = mdiobus_write(bus, sw_addr, 0, 0x9800 \| (addr << 5) \| reg);
	59	if (ret < 0)
	60	return ret;
	61
3675c8d7	62	/* Wait for the read command to complete. */
91da11f8 LB	63	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	64	if (ret < 0)
	65	return ret;
	66
3675c8d7	67	/* Read the data. */
91da11f8 LB	68	ret = mdiobus_read(bus, sw_addr, 1);
	69	if (ret < 0)
	70	return ret;
	71
	72	return ret & 0xffff;
	73	}
	74
	75	int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
	76	{
a22adce5	77	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b184e497	78	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 LB	79	int ret;
91da11f8 LB	80
b184e497 GR	81	if (bus == NULL)
	82	return -EINVAL;
	83
91da11f8	84	mutex_lock(&ps->smi_mutex);
b184e497	85	ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
91da11f8 LB	86	mutex_unlock(&ps->smi_mutex);
	87
	88	return ret;
	89	}
	90
	91	int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
	92	int reg, u16 val)
	93	{
	94	int ret;
	95
	96	if (sw_addr == 0)
	97	return mdiobus_write(bus, addr, reg, val);
	98
3675c8d7	99	/* Wait for the bus to become free. */
91da11f8 LB	100	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	101	if (ret < 0)
	102	return ret;
	103
3675c8d7	104	/* Transmit the data to write. */
91da11f8 LB	105	ret = mdiobus_write(bus, sw_addr, 1, val);
	106	if (ret < 0)
	107	return ret;
	108
3675c8d7	109	/* Transmit the write command. */
91da11f8 LB	110	ret = mdiobus_write(bus, sw_addr, 0, 0x9400 \| (addr << 5) \| reg);
	111	if (ret < 0)
	112	return ret;
	113
3675c8d7	114	/* Wait for the write command to complete. */
91da11f8 LB	115	ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
	116	if (ret < 0)
	117	return ret;
	118
	119	return 0;
	120	}
	121
	122	int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
	123	{
a22adce5	124	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b184e497	125	struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 LB	126	int ret;
91da11f8 LB	127
b184e497 GR	128	if (bus == NULL)
	129	return -EINVAL;
	130
91da11f8	131	mutex_lock(&ps->smi_mutex);
b184e497	132	ret = __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
91da11f8 LB	133	mutex_unlock(&ps->smi_mutex);
	134
	135	return ret;
	136	}
	137
	138	int mv88e6xxx_config_prio(struct dsa_switch *ds)
	139	{
3675c8d7	140	/* Configure the IP ToS mapping registers. */
91da11f8 LB	141	REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
	142	REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
	143	REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
	144	REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
	145	REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
	146	REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
	147	REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
	148	REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
	149
3675c8d7	150	/* Configure the IEEE 802.1p priority mapping register. */
91da11f8 LB	151	REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
	152
	153	return 0;
	154	}
	155
2e5f0320 LB	156	int mv88e6xxx_set_addr_direct(struct dsa_switch ds, u8 addr)
	157	{
	158	REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) \| addr[1]);
	159	REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) \| addr[3]);
	160	REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) \| addr[5]);
	161
	162	return 0;
	163	}
	164
91da11f8 LB	165	int mv88e6xxx_set_addr_indirect(struct dsa_switch ds, u8 addr)
	166	{
	167	int i;
	168	int ret;
	169
	170	for (i = 0; i < 6; i++) {
	171	int j;
	172
3675c8d7	173	/* Write the MAC address byte. */
91da11f8 LB	174	REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 \| (i << 8) \| addr[i]);
91da11f8 LB	175
3675c8d7	176	/* Wait for the write to complete. */
91da11f8 LB	177	for (j = 0; j < 16; j++) {
	178	ret = REG_READ(REG_GLOBAL2, 0x0d);
	179	if ((ret & 0x8000) == 0)
	180	break;
	181	}
	182	if (j == 16)
	183	return -ETIMEDOUT;
	184	}
	185
	186	return 0;
	187	}
	188
	189	int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
	190	{
	191	if (addr >= 0)
	192	return mv88e6xxx_reg_read(ds, addr, regnum);
	193	return 0xffff;
	194	}
	195
	196	int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
	197	{
	198	if (addr >= 0)
	199	return mv88e6xxx_reg_write(ds, addr, regnum, val);
	200	return 0;
	201	}
	202
2e5f0320 LB	203	#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
	204	static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
	205	{
	206	int ret;
19b2f97e	207	unsigned long timeout;
2e5f0320 LB	208
	209	ret = REG_READ(REG_GLOBAL, 0x04);
	210	REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
	211
19b2f97e BG	212	timeout = jiffies + 1 * HZ;
19b2f97e BG	213	while (time_before(jiffies, timeout)) {
85686581	214	ret = REG_READ(REG_GLOBAL, 0x00);
19b2f97e	215	usleep_range(1000, 2000);
85686581 BG	216	if ((ret & 0xc000) != 0xc000)
85686581 BG	217	return 0;
2e5f0320 LB	218	}
	219
	220	return -ETIMEDOUT;
	221	}
	222
	223	static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
	224	{
	225	int ret;
19b2f97e	226	unsigned long timeout;
2e5f0320 LB	227
	228	ret = REG_READ(REG_GLOBAL, 0x04);
	229	REG_WRITE(REG_GLOBAL, 0x04, ret \| 0x4000);
	230
19b2f97e BG	231	timeout = jiffies + 1 * HZ;
19b2f97e BG	232	while (time_before(jiffies, timeout)) {
85686581	233	ret = REG_READ(REG_GLOBAL, 0x00);
19b2f97e	234	usleep_range(1000, 2000);
85686581 BG	235	if ((ret & 0xc000) == 0xc000)
85686581 BG	236	return 0;
2e5f0320 LB	237	}
	238
	239	return -ETIMEDOUT;
	240	}
	241
	242	static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
	243	{
	244	struct mv88e6xxx_priv_state *ps;
	245
	246	ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
	247	if (mutex_trylock(&ps->ppu_mutex)) {
85686581	248	struct dsa_switch ds = ((struct dsa_switch )ps) - 1;
2e5f0320	249
85686581 BG	250	if (mv88e6xxx_ppu_enable(ds) == 0)
	251	ps->ppu_disabled = 0;
	252	mutex_unlock(&ps->ppu_mutex);
2e5f0320 LB	253	}
	254	}
	255
	256	static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
	257	{
	258	struct mv88e6xxx_priv_state ps = (void )_ps;
	259
	260	schedule_work(&ps->ppu_work);
	261	}
	262
	263	static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
	264	{
a22adce5	265	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 LB	266	int ret;
	267
	268	mutex_lock(&ps->ppu_mutex);
	269
3675c8d7	270	/* If the PHY polling unit is enabled, disable it so that
2e5f0320 LB	271	* we can access the PHY registers. If it was already
	272	* disabled, cancel the timer that is going to re-enable
	273	* it.
	274	*/
	275	if (!ps->ppu_disabled) {
85686581 BG	276	ret = mv88e6xxx_ppu_disable(ds);
	277	if (ret < 0) {
	278	mutex_unlock(&ps->ppu_mutex);
	279	return ret;
	280	}
	281	ps->ppu_disabled = 1;
2e5f0320	282	} else {
85686581 BG	283	del_timer(&ps->ppu_timer);
85686581 BG	284	ret = 0;
2e5f0320 LB	285	}
	286
	287	return ret;
	288	}
	289
	290	static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
	291	{
a22adce5	292	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320	293
3675c8d7	294	/* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320 LB	295	mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
	296	mutex_unlock(&ps->ppu_mutex);
	297	}
	298
	299	void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
	300	{
a22adce5	301	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 LB	302
	303	mutex_init(&ps->ppu_mutex);
	304	INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
	305	init_timer(&ps->ppu_timer);
	306	ps->ppu_timer.data = (unsigned long)ps;
	307	ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
	308	}
	309
	310	int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
	311	{
	312	int ret;
	313
	314	ret = mv88e6xxx_ppu_access_get(ds);
	315	if (ret >= 0) {
85686581 BG	316	ret = mv88e6xxx_reg_read(ds, addr, regnum);
85686581 BG	317	mv88e6xxx_ppu_access_put(ds);
2e5f0320 LB	318	}
	319
	320	return ret;
	321	}
	322
	323	int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
	324	int regnum, u16 val)
	325	{
	326	int ret;
	327
	328	ret = mv88e6xxx_ppu_access_get(ds);
	329	if (ret >= 0) {
85686581 BG	330	ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
85686581 BG	331	mv88e6xxx_ppu_access_put(ds);
2e5f0320 LB	332	}
	333
	334	return ret;
	335	}
	336	#endif
	337
91da11f8 LB	338	void mv88e6xxx_poll_link(struct dsa_switch *ds)
	339	{
	340	int i;
	341
	342	for (i = 0; i < DSA_MAX_PORTS; i++) {
	343	struct net_device *dev;
2a9e7978	344	int uninitialized_var(port_status);
91da11f8 LB	345	int link;
	346	int speed;
	347	int duplex;
	348	int fc;
	349
	350	dev = ds->ports[i];
	351	if (dev == NULL)
	352	continue;
	353
	354	link = 0;
	355	if (dev->flags & IFF_UP) {
	356	port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
	357	if (port_status < 0)
	358	continue;
	359
	360	link = !!(port_status & 0x0800);
	361	}
	362
	363	if (!link) {
	364	if (netif_carrier_ok(dev)) {
ab381a93	365	netdev_info(dev, "link down\n");
91da11f8 LB	366	netif_carrier_off(dev);
	367	}
	368	continue;
	369	}
	370
	371	switch (port_status & 0x0300) {
	372	case 0x0000:
	373	speed = 10;
	374	break;
	375	case 0x0100:
	376	speed = 100;
	377	break;
	378	case 0x0200:
	379	speed = 1000;
	380	break;
	381	default:
	382	speed = -1;
	383	break;
	384	}
	385	duplex = (port_status & 0x0400) ? 1 : 0;
	386	fc = (port_status & 0x8000) ? 1 : 0;
	387
	388	if (!netif_carrier_ok(dev)) {
ab381a93 BG	389	netdev_info(dev,
	390	"link up, %d Mb/s, %s duplex, flow control %sabled\n",
	391	speed,
	392	duplex ? "full" : "half",
	393	fc ? "en" : "dis");
91da11f8 LB	394	netif_carrier_on(dev);
	395	}
	396	}
	397	}
	398
	399	static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
	400	{
	401	int ret;
	402	int i;
	403
	404	for (i = 0; i < 10; i++) {
1ded3f59	405	ret = REG_READ(REG_GLOBAL, 0x1d);
91da11f8 LB	406	if ((ret & 0x8000) == 0)
	407	return 0;
	408	}
	409
	410	return -ETIMEDOUT;
	411	}
	412
	413	static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
	414	{
	415	int ret;
	416
3675c8d7	417	/* Snapshot the hardware statistics counters for this port. */
91da11f8 LB	418	REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 \| port);
91da11f8 LB	419
3675c8d7	420	/* Wait for the snapshotting to complete. */
91da11f8 LB	421	ret = mv88e6xxx_stats_wait(ds);
	422	if (ret < 0)
	423	return ret;
	424
	425	return 0;
	426	}
	427
	428	static void mv88e6xxx_stats_read(struct dsa_switch ds, int stat, u32 val)
	429	{
	430	u32 _val;
	431	int ret;
	432
	433	*val = 0;
	434
	435	ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 \| stat);
	436	if (ret < 0)
	437	return;
	438
	439	ret = mv88e6xxx_stats_wait(ds);
	440	if (ret < 0)
	441	return;
	442
	443	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
	444	if (ret < 0)
	445	return;
	446
	447	_val = ret << 16;
	448
	449	ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
	450	if (ret < 0)
	451	return;
	452
	453	*val = _val \| ret;
	454	}
	455
	456	void mv88e6xxx_get_strings(struct dsa_switch *ds,
	457	int nr_stats, struct mv88e6xxx_hw_stat *stats,
	458	int port, uint8_t *data)
	459	{
	460	int i;
	461
	462	for (i = 0; i < nr_stats; i++) {
	463	memcpy(data + i * ETH_GSTRING_LEN,
	464	stats[i].string, ETH_GSTRING_LEN);
	465	}
	466	}
	467
	468	void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
	469	int nr_stats, struct mv88e6xxx_hw_stat *stats,
	470	int port, uint64_t *data)
	471	{
a22adce5	472	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 LB	473	int ret;
	474	int i;
	475
	476	mutex_lock(&ps->stats_mutex);
	477
	478	ret = mv88e6xxx_stats_snapshot(ds, port);
	479	if (ret < 0) {
	480	mutex_unlock(&ps->stats_mutex);
	481	return;
	482	}
	483
3675c8d7	484	/* Read each of the counters. */
91da11f8 LB	485	for (i = 0; i < nr_stats; i++) {
	486	struct mv88e6xxx_hw_stat *s = stats + i;
	487	u32 low;
17ee3e04 GR	488	u32 high = 0;
	489
	490	if (s->reg >= 0x100) {
	491	int ret;
	492
	493	ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
	494	s->reg - 0x100);
	495	if (ret < 0)
	496	goto error;
	497	low = ret;
	498	if (s->sizeof_stat == 4) {
	499	ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
	500	s->reg - 0x100 + 1);
	501	if (ret < 0)
	502	goto error;
	503	high = ret;
	504	}
	505	data[i] = (((u64)high) << 16) \| low;
	506	continue;
	507	}
91da11f8 LB	508	mv88e6xxx_stats_read(ds, s->reg, &low);
	509	if (s->sizeof_stat == 8)
	510	mv88e6xxx_stats_read(ds, s->reg + 1, &high);
91da11f8 LB	511
	512	data[i] = (((u64)high) << 32) \| low;
	513	}
17ee3e04	514	error:
91da11f8 LB	515	mutex_unlock(&ps->stats_mutex);
91da11f8 LB	516	}
98e67308	517
a1ab91f3 GR	518	int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
	519	{
	520	return 32 * sizeof(u16);
	521	}
	522
	523	void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
	524	struct ethtool_regs regs, void _p)
	525	{
	526	u16 *p = _p;
	527	int i;
	528
	529	regs->version = 0;
	530
	531	memset(p, 0xff, 32 * sizeof(u16));
	532
	533	for (i = 0; i < 32; i++) {
	534	int ret;
	535
	536	ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
	537	if (ret >= 0)
	538	p[i] = ret;
	539	}
	540	}
	541
eaa23765 AL	542	#ifdef CONFIG_NET_DSA_HWMON
	543
	544	int mv88e6xxx_get_temp(struct dsa_switch ds, int temp)
	545	{
	546	struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
	547	int ret;
	548	int val;
	549
	550	*temp = 0;
	551
	552	mutex_lock(&ps->phy_mutex);
	553
	554	ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
	555	if (ret < 0)
	556	goto error;
	557
	558	/* Enable temperature sensor */
	559	ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	560	if (ret < 0)
	561	goto error;
	562
	563	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret \| (1 << 5));
	564	if (ret < 0)
	565	goto error;
	566
	567	/* Wait for temperature to stabilize */
	568	usleep_range(10000, 12000);
	569
	570	val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
	571	if (val < 0) {
	572	ret = val;
	573	goto error;
	574	}
	575
	576	/* Disable temperature sensor */
	577	ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
	578	if (ret < 0)
	579	goto error;
	580
	581	temp = ((val & 0x1f) - 5) 5;
	582
	583	error:
	584	mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
	585	mutex_unlock(&ps->phy_mutex);
	586	return ret;
	587	}
	588	#endif /* CONFIG_NET_DSA_HWMON */
	589
98e67308 BH	590	static int __init mv88e6xxx_init(void)
	591	{
	592	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	593	register_switch_driver(&mv88e6131_switch_driver);
	594	#endif
	595	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	596	register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253	597	#endif
3ad50cca GR	598	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
	599	register_switch_driver(&mv88e6352_switch_driver);
	600	#endif
42f27253 AL	601	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
42f27253 AL	602	register_switch_driver(&mv88e6171_switch_driver);
98e67308 BH	603	#endif
	604	return 0;
	605	}
	606	module_init(mv88e6xxx_init);
	607
	608	static void __exit mv88e6xxx_cleanup(void)
	609	{
42f27253 AL	610	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
	611	unregister_switch_driver(&mv88e6171_switch_driver);
	612	#endif
98e67308 BH	613	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
	614	unregister_switch_driver(&mv88e6123_61_65_switch_driver);
	615	#endif
	616	#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
	617	unregister_switch_driver(&mv88e6131_switch_driver);
	618	#endif
	619	}
	620	module_exit(mv88e6xxx_cleanup);
3d825ede BH	621
	622	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
	623	MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
	624	MODULE_LICENSE("GPL");