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Merge tag 'efi-urgent-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / dsa / qca8k.c
CommitLineData
63a786a3 1// SPDX-License-Identifier: GPL-2.0
6b93fb46
JC		 2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
abb48f80 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6b93fb46 6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6b93fb46
JC		 7 */
8
9#include <linux/module.h>
10#include <linux/phy.h>
11#include <linux/netdevice.h>
12#include <net/dsa.h>
6b93fb46 13#include <linux/of_net.h>
759bafb8 14#include <linux/of_mdio.h>
6b93fb46
JC		 15#include <linux/of_platform.h>
16#include <linux/if_bridge.h>
17#include <linux/mdio.h>
b3591c2a 18#include <linux/phylink.h>
f32ae8a5 19#include <linux/gpio/consumer.h>
6b93fb46
JC		 20#include <linux/etherdevice.h>
21
22#include "qca8k.h"
23
24#define MIB_DESC(_s, _o, _n) \
25 { \
26 .size = (_s), \
27 .offset = (_o), \
28 .name = (_n), \
29 }
30
31static const struct qca8k_mib_desc ar8327_mib[] = {
32 MIB_DESC(1, 0x00, "RxBroad"),
33 MIB_DESC(1, 0x04, "RxPause"),
34 MIB_DESC(1, 0x08, "RxMulti"),
35 MIB_DESC(1, 0x0c, "RxFcsErr"),
36 MIB_DESC(1, 0x10, "RxAlignErr"),
37 MIB_DESC(1, 0x14, "RxRunt"),
38 MIB_DESC(1, 0x18, "RxFragment"),
39 MIB_DESC(1, 0x1c, "Rx64Byte"),
40 MIB_DESC(1, 0x20, "Rx128Byte"),
41 MIB_DESC(1, 0x24, "Rx256Byte"),
42 MIB_DESC(1, 0x28, "Rx512Byte"),
43 MIB_DESC(1, 0x2c, "Rx1024Byte"),
44 MIB_DESC(1, 0x30, "Rx1518Byte"),
45 MIB_DESC(1, 0x34, "RxMaxByte"),
46 MIB_DESC(1, 0x38, "RxTooLong"),
47 MIB_DESC(2, 0x3c, "RxGoodByte"),
48 MIB_DESC(2, 0x44, "RxBadByte"),
49 MIB_DESC(1, 0x4c, "RxOverFlow"),
50 MIB_DESC(1, 0x50, "Filtered"),
51 MIB_DESC(1, 0x54, "TxBroad"),
52 MIB_DESC(1, 0x58, "TxPause"),
53 MIB_DESC(1, 0x5c, "TxMulti"),
54 MIB_DESC(1, 0x60, "TxUnderRun"),
55 MIB_DESC(1, 0x64, "Tx64Byte"),
56 MIB_DESC(1, 0x68, "Tx128Byte"),
57 MIB_DESC(1, 0x6c, "Tx256Byte"),
58 MIB_DESC(1, 0x70, "Tx512Byte"),
59 MIB_DESC(1, 0x74, "Tx1024Byte"),
60 MIB_DESC(1, 0x78, "Tx1518Byte"),
61 MIB_DESC(1, 0x7c, "TxMaxByte"),
62 MIB_DESC(1, 0x80, "TxOverSize"),
63 MIB_DESC(2, 0x84, "TxByte"),
64 MIB_DESC(1, 0x8c, "TxCollision"),
65 MIB_DESC(1, 0x90, "TxAbortCol"),
66 MIB_DESC(1, 0x94, "TxMultiCol"),
67 MIB_DESC(1, 0x98, "TxSingleCol"),
68 MIB_DESC(1, 0x9c, "TxExcDefer"),
69 MIB_DESC(1, 0xa0, "TxDefer"),
70 MIB_DESC(1, 0xa4, "TxLateCol"),
71};
72
73/* The 32bit switch registers are accessed indirectly. To achieve this we need
74 * to set the page of the register. Track the last page that was set to reduce
75 * mdio writes
76 */
77static u16 qca8k_current_page = 0xffff;
78
79static void
80qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
81{
82 regaddr >>= 1;
83 *r1 = regaddr & 0x1e;
84
85 regaddr >>= 5;
86 *r2 = regaddr & 0x7;
87
88 regaddr >>= 3;
89 *page = regaddr & 0x3ff;
90}
91
7c9896e3
YY		 92static int
93qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
6b93fb46 94{
6b93fb46
JC		 95 int ret;
96
97 ret = bus->read(bus, phy_id, regnum);
98 if (ret >= 0) {
7c9896e3 99 *val = ret;
6b93fb46 100 ret = bus->read(bus, phy_id, regnum + 1);
7c9896e3 101 *val |= ret << 16;
6b93fb46
JC		 102 }
103
104 if (ret < 0) {
105 dev_err_ratelimited(&bus->dev,
106 "failed to read qca8k 32bit register\n");
7c9896e3 107 *val = 0;
6b93fb46
JC		 108 return ret;
109 }
110
7c9896e3 111 return 0;
6b93fb46
JC		 112}
113
114static void
115qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
116{
117 u16 lo, hi;
118 int ret;
119
120 lo = val & 0xffff;
121 hi = (u16)(val >> 16);
122
123 ret = bus->write(bus, phy_id, regnum, lo);
124 if (ret >= 0)
125 ret = bus->write(bus, phy_id, regnum + 1, hi);
126 if (ret < 0)
127 dev_err_ratelimited(&bus->dev,
128 "failed to write qca8k 32bit register\n");
129}
130
ba5707ec 131static int
6b93fb46
JC		 132qca8k_set_page(struct mii_bus *bus, u16 page)
133{
ba5707ec
AS		 134 int ret;
135
6b93fb46 136 if (page == qca8k_current_page)
ba5707ec 137 return 0;
6b93fb46 138
ba5707ec
AS		 139 ret = bus->write(bus, 0x18, 0, page);
140 if (ret < 0) {
6b93fb46
JC		 141 dev_err_ratelimited(&bus->dev,
142 "failed to set qca8k page\n");
ba5707ec
AS		 143 return ret;
144 }
145
6b93fb46 146 qca8k_current_page = page;
617960d7 147 usleep_range(1000, 2000);
ba5707ec 148 return 0;
6b93fb46
JC		 149}
150
7c9896e3
YY		 151static int
152qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
6b93fb46 153{
504bf659 154 struct mii_bus *bus = priv->bus;
6b93fb46 155 u16 r1, r2, page;
7c9896e3 156 int ret;
6b93fb46
JC		 157
158 qca8k_split_addr(reg, &r1, &r2, &page);
159
504bf659 160 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
6b93fb46 161
7c9896e3
YY		 162 ret = qca8k_set_page(bus, page);
163 if (ret < 0)
ba5707ec
AS		 164 goto exit;
165
7c9896e3 166 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
6b93fb46 167
ba5707ec 168exit:
504bf659 169 mutex_unlock(&bus->mdio_lock);
7c9896e3 170 return ret;
6b93fb46
JC		 171}
172
d7805757 173static int
6b93fb46
JC		 174qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
175{
504bf659 176 struct mii_bus *bus = priv->bus;
6b93fb46 177 u16 r1, r2, page;
ba5707ec 178 int ret;
6b93fb46
JC		 179
180 qca8k_split_addr(reg, &r1, &r2, &page);
181
504bf659 182 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
6b93fb46 183
ba5707ec
AS		 184 ret = qca8k_set_page(bus, page);
185 if (ret < 0)
186 goto exit;
187
504bf659 188 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
6b93fb46 189
ba5707ec 190exit:
504bf659 191 mutex_unlock(&bus->mdio_lock);
d7805757 192 return ret;
6b93fb46
JC		 193}
194
aaf42142
AS		 195static int
196qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
6b93fb46 197{
504bf659 198 struct mii_bus *bus = priv->bus;
6b93fb46 199 u16 r1, r2, page;
aaf42142
AS		 200 u32 val;
201 int ret;
6b93fb46
JC		 202
203 qca8k_split_addr(reg, &r1, &r2, &page);
204
504bf659 205 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
6b93fb46 206
ba5707ec
AS		 207 ret = qca8k_set_page(bus, page);
208 if (ret < 0)
209 goto exit;
210
7c9896e3
YY		 211 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
212 if (ret < 0)
aaf42142 213 goto exit;
aaf42142
AS		 214
215 val &= ~mask;
216 val |= write_val;
217 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
6b93fb46 218
ba5707ec 219exit:
504bf659 220 mutex_unlock(&bus->mdio_lock);
6b93fb46
JC		 221
222 return ret;
223}
224
aaf42142 225static int
6b93fb46
JC		 226qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
227{
aaf42142 228 return qca8k_rmw(priv, reg, 0, val);
6b93fb46
JC		 229}
230
aaf42142 231static int
6b93fb46
JC		 232qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
233{
aaf42142 234 return qca8k_rmw(priv, reg, val, 0);
6b93fb46
JC		 235}
236
237static int
238qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
239{
240 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
6b93fb46 241
7c9896e3 242 return qca8k_read(priv, reg, val);
6b93fb46
JC		 243}
244
245static int
246qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
247{
248 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
249
d7805757 250 return qca8k_write(priv, reg, val);
6b93fb46
JC		 251}
252
253static const struct regmap_range qca8k_readable_ranges[] = {
254 regmap_reg_range(0x0000, 0x00e4), /* Global control */
255 regmap_reg_range(0x0100, 0x0168), /* EEE control */
256 regmap_reg_range(0x0200, 0x0270), /* Parser control */
257 regmap_reg_range(0x0400, 0x0454), /* ACL */
258 regmap_reg_range(0x0600, 0x0718), /* Lookup */
259 regmap_reg_range(0x0800, 0x0b70), /* QM */
260 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
261 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
262 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
263 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
264 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
265 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
266 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
267 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
268 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
269
270};
271
7e3108fa 272static const struct regmap_access_table qca8k_readable_table = {
6b93fb46
JC		 273 .yes_ranges = qca8k_readable_ranges,
274 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
275};
276
fcfbfd68 277static struct regmap_config qca8k_regmap_config = {
6b93fb46
JC		 278 .reg_bits = 16,
279 .val_bits = 32,
280 .reg_stride = 4,
281 .max_register = 0x16ac, /* end MIB - Port6 range */
282 .reg_read = qca8k_regmap_read,
283 .reg_write = qca8k_regmap_write,
284 .rd_table = &qca8k_readable_table,
285};
286
287static int
288qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
289{
7c9896e3 290 int ret, ret1;
2ad255f2 291 u32 val;
6b93fb46 292
7c9896e3 293 ret = read_poll_timeout(qca8k_read, ret1, !(val & mask),
2ad255f2 294 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
7c9896e3 295 priv, reg, &val);
6b93fb46 296
2ad255f2
AS		 297 /* Check if qca8k_read has failed for a different reason
298 * before returning -ETIMEDOUT
299 */
7c9896e3
YY		 300 if (ret < 0 && ret1 < 0)
301 return ret1;
6b93fb46 302
2ad255f2 303 return ret;
6b93fb46
JC		 304}
305
028f5f8e 306static int
6b93fb46
JC		 307qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
308{
028f5f8e 309 u32 reg[4], val;
7c9896e3 310 int i, ret;
6b93fb46
JC		 311
312 /* load the ARL table into an array */
028f5f8e 313 for (i = 0; i < 4; i++) {
7c9896e3
YY		 314 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
315 if (ret < 0)
316 return ret;
028f5f8e
AS		 317
318 reg[i] = val;
319 }
6b93fb46
JC		 320
321 /* vid - 83:72 */
322 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
323 /* aging - 67:64 */
324 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
325 /* portmask - 54:48 */
326 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
327 /* mac - 47:0 */
328 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
329 fdb->mac[1] = reg[1] & 0xff;
330 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
331 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
332 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
333 fdb->mac[5] = reg[0] & 0xff;
028f5f8e
AS		 334
335 return 0;
6b93fb46
JC		 336}
337
338static void
339qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
340 u8 aging)
341{
342 u32 reg[3] = { 0 };
343 int i;
344
345 /* vid - 83:72 */
346 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
347 /* aging - 67:64 */
348 reg[2] |= aging & QCA8K_ATU_STATUS_M;
349 /* portmask - 54:48 */
350 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
351 /* mac - 47:0 */
352 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
353 reg[1] |= mac[1];
354 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
355 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
356 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
357 reg[0] |= mac[5];
358
359 /* load the array into the ARL table */
360 for (i = 0; i < 3; i++)
361 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
362}
363
364static int
365qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
366{
367 u32 reg;
d7805757 368 int ret;
6b93fb46
JC		 369
370 /* Set the command and FDB index */
371 reg = QCA8K_ATU_FUNC_BUSY;
372 reg |= cmd;
373 if (port >= 0) {
374 reg |= QCA8K_ATU_FUNC_PORT_EN;
375 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
376 }
377
378 /* Write the function register triggering the table access */
d7805757
AS		 379 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
380 if (ret)
381 return ret;
6b93fb46
JC		 382
383 /* wait for completion */
b7c818d1
AS		 384 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
385 if (ret)
386 return ret;
6b93fb46
JC		 387
388 /* Check for table full violation when adding an entry */
389 if (cmd == QCA8K_FDB_LOAD) {
7c9896e3
YY		 390 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
391 if (ret < 0)
392 return ret;
6b93fb46
JC		 393 if (reg & QCA8K_ATU_FUNC_FULL)
394 return -1;
395 }
396
397 return 0;
398}
399
400static int
401qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
402{
403 int ret;
404
405 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
406 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
028f5f8e
AS		 407 if (ret < 0)
408 return ret;
6b93fb46 409
028f5f8e 410 return qca8k_fdb_read(priv, fdb);
6b93fb46
JC		 411}
412
413static int
414qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
415 u16 vid, u8 aging)
416{
417 int ret;
418
419 mutex_lock(&priv->reg_mutex);
420 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
421 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
422 mutex_unlock(&priv->reg_mutex);
423
424 return ret;
425}
426
427static int
428qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
429{
430 int ret;
431
432 mutex_lock(&priv->reg_mutex);
433 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
434 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
435 mutex_unlock(&priv->reg_mutex);
436
437 return ret;
438}
439
440static void
441qca8k_fdb_flush(struct qca8k_priv *priv)
442{
443 mutex_lock(&priv->reg_mutex);
444 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
445 mutex_unlock(&priv->reg_mutex);
446}
447
69462fe6
JM		 448static int
449qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
450{
451 u32 reg;
d7805757 452 int ret;
69462fe6
JM		 453
454 /* Set the command and VLAN index */
455 reg = QCA8K_VTU_FUNC1_BUSY;
456 reg |= cmd;
457 reg |= vid << QCA8K_VTU_FUNC1_VID_S;
458
459 /* Write the function register triggering the table access */
d7805757
AS		 460 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
461 if (ret)
462 return ret;
69462fe6
JM		 463
464 /* wait for completion */
b7c818d1
AS		 465 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
466 if (ret)
467 return ret;
69462fe6
JM		 468
469 /* Check for table full violation when adding an entry */
470 if (cmd == QCA8K_VLAN_LOAD) {
7c9896e3
YY		 471 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
472 if (ret < 0)
473 return ret;
69462fe6
JM		 474 if (reg & QCA8K_VTU_FUNC1_FULL)
475 return -ENOMEM;
476 }
477
478 return 0;
479}
480
481static int
482qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
483{
484 u32 reg;
485 int ret;
486
487 /*
488 We do the right thing with VLAN 0 and treat it as untagged while
489 preserving the tag on egress.
490 */
491 if (vid == 0)
492 return 0;
493
494 mutex_lock(&priv->reg_mutex);
495 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
496 if (ret < 0)
497 goto out;
498
7c9896e3
YY		 499 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
500 if (ret < 0)
0d56e5c1 501 goto out;
69462fe6
JM		 502 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
503 reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
504 if (untagged)
505 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
506 QCA8K_VTU_FUNC0_EG_MODE_S(port);
507 else
508 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
509 QCA8K_VTU_FUNC0_EG_MODE_S(port);
510
d7805757
AS		 511 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
512 if (ret)
0d56e5c1 513 goto out;
69462fe6
JM		 514 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
515
516out:
517 mutex_unlock(&priv->reg_mutex);
518
519 return ret;
520}
521
522static int
523qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
524{
525 u32 reg, mask;
526 int ret, i;
527 bool del;
528
529 mutex_lock(&priv->reg_mutex);
530 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
531 if (ret < 0)
532 goto out;
533
7c9896e3
YY		 534 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
535 if (ret < 0)
0d56e5c1 536 goto out;
69462fe6
JM		 537 reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
538 reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
539 QCA8K_VTU_FUNC0_EG_MODE_S(port);
540
541 /* Check if we're the last member to be removed */
542 del = true;
543 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
544 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
545 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
546
547 if ((reg & mask) != mask) {
548 del = false;
549 break;
550 }
551 }
552
553 if (del) {
554 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
555 } else {
d7805757
AS		 556 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
557 if (ret)
0d56e5c1 558 goto out;
69462fe6
JM		 559 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
560 }
561
562out:
563 mutex_unlock(&priv->reg_mutex);
564
565 return ret;
566}
567
d7805757 568static int
6b93fb46
JC		 569qca8k_mib_init(struct qca8k_priv *priv)
570{
d7805757
AS		 571 int ret;
572
6b93fb46 573 mutex_lock(&priv->reg_mutex);
aaf42142
AS		 574 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
575 if (ret)
576 goto exit;
577
b7c818d1
AS		 578 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
579 if (ret)
580 goto exit;
aaf42142
AS		 581
582 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
583 if (ret)
584 goto exit;
d7805757
AS		 585
586 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
587
aaf42142 588exit:
6b93fb46 589 mutex_unlock(&priv->reg_mutex);
d7805757 590 return ret;
6b93fb46
JC		 591}
592
6b93fb46
JC		 593static void
594qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
595{
eee1fe64 596 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
6b93fb46
JC		 597
598 /* Port 0 and 6 have no internal PHY */
38222b1a 599 if (port > 0 && port < 6)
6b93fb46
JC		 600 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
601
602 if (enable)
603 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
604 else
605 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
606}
607
db460c54
CL		 608static u32
609qca8k_port_to_phy(int port)
610{
611 /* From Andrew Lunn:
612 * Port 0 has no internal phy.
613 * Port 1 has an internal PHY at MDIO address 0.
614 * Port 2 has an internal PHY at MDIO address 1.
615 * ...
616 * Port 5 has an internal PHY at MDIO address 4.
617 * Port 6 has no internal PHY.
618 */
619
620 return port - 1;
621}
622
60df02b6 623static int
759bafb8 624qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
60df02b6
AS		 625{
626 u16 r1, r2, page;
627 u32 val;
7c9896e3 628 int ret, ret1;
60df02b6
AS		 629
630 qca8k_split_addr(reg, &r1, &r2, &page);
631
7c9896e3 632 ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
60df02b6 633 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
7c9896e3 634 bus, 0x10 | r2, r1, &val);
60df02b6
AS		 635
636 /* Check if qca8k_read has failed for a different reason
637 * before returnting -ETIMEDOUT
638 */
7c9896e3
YY		 639 if (ret < 0 && ret1 < 0)
640 return ret1;
60df02b6
AS		 641
642 return ret;
643}
644
db460c54 645static int
ce062a0a 646qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)
db460c54 647{
60df02b6 648 u16 r1, r2, page;
759bafb8 649 u32 val;
d7805757 650 int ret;
db460c54
CL		 651
652 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
653 return -EINVAL;
654
db460c54
CL		 655 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
656 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
657 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
658 QCA8K_MDIO_MASTER_DATA(data);
659
60df02b6
AS		 660 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
661
b7ebac35 662 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
60df02b6 663
b7ebac35 664 ret = qca8k_set_page(bus, page);
d7805757 665 if (ret)
60df02b6
AS		 666 goto exit;
667
b7ebac35 668 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
db460c54 669
b7ebac35 670 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
60df02b6
AS		 671 QCA8K_MDIO_MASTER_BUSY);
672
673exit:
63c33bbf 674 /* even if the busy_wait timeouts try to clear the MASTER_EN */
b7ebac35 675 qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
759bafb8 676
b7ebac35 677 mutex_unlock(&bus->mdio_lock);
63c33bbf
AS		 678
679 return ret;
db460c54
CL		 680}
681
682static int
ce062a0a 683qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)
db460c54 684{
60df02b6 685 u16 r1, r2, page;
759bafb8 686 u32 val;
d7805757 687 int ret;
db460c54
CL		 688
689 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
690 return -EINVAL;
691
db460c54
CL		 692 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
693 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
694 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
695
60df02b6 696 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
db460c54 697
b7ebac35 698 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
60df02b6 699
b7ebac35 700 ret = qca8k_set_page(bus, page);
b7c818d1 701 if (ret)
60df02b6 702 goto exit;
db460c54 703
b7ebac35 704 qca8k_mii_write32(bus, 0x10 | r2, r1, val);
028f5f8e 705
b7ebac35 706 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
60df02b6
AS		 707 QCA8K_MDIO_MASTER_BUSY);
708 if (ret)
709 goto exit;
710
7c9896e3 711 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
db460c54 712
60df02b6 713exit:
759bafb8 714 /* even if the busy_wait timeouts try to clear the MASTER_EN */
b7ebac35 715 qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
759bafb8 716
b7ebac35 717 mutex_unlock(&bus->mdio_lock);
60df02b6 718
7c9896e3
YY		 719 if (ret >= 0)
720 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
60df02b6 721
7c9896e3 722 return ret;
db460c54
CL		 723}
724
ce062a0a
AS		 725static int
726qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
727{
728 struct qca8k_priv *priv = slave_bus->priv;
729 struct mii_bus *bus = priv->bus;
730
731 return qca8k_mdio_write(bus, phy, regnum, data);
732}
733
734static int
735qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
736{
737 struct qca8k_priv *priv = slave_bus->priv;
738 struct mii_bus *bus = priv->bus;
739
740 return qca8k_mdio_read(bus, phy, regnum);
741}
742
db460c54
CL		 743static int
744qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
745{
746 struct qca8k_priv *priv = ds->priv;
747
759bafb8
AS		 748 /* Check if the legacy mapping should be used and the
749 * port is not correctly mapped to the right PHY in the
750 * devicetree
751 */
752 if (priv->legacy_phy_port_mapping)
753 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
754
755 return qca8k_mdio_write(priv->bus, port, regnum, data);
db460c54
CL		 756}
757
758static int
759qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
760{
761 struct qca8k_priv *priv = ds->priv;
762 int ret;
763
759bafb8
AS		 764 /* Check if the legacy mapping should be used and the
765 * port is not correctly mapped to the right PHY in the
766 * devicetree
767 */
768 if (priv->legacy_phy_port_mapping)
769 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
770
771 ret = qca8k_mdio_read(priv->bus, port, regnum);
db460c54
CL		 772
773 if (ret < 0)
774 return 0xffff;
775
776 return ret;
777}
778
759bafb8
AS		 779static int
780qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
781{
782 struct dsa_switch *ds = priv->ds;
783 struct mii_bus *bus;
784
785 bus = devm_mdiobus_alloc(ds->dev);
786
787 if (!bus)
788 return -ENOMEM;
789
790 bus->priv = (void *)priv;
791 bus->name = "qca8k slave mii";
ce062a0a
AS		 792 bus->read = qca8k_internal_mdio_read;
793 bus->write = qca8k_internal_mdio_write;
759bafb8
AS		 794 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
795 ds->index);
796
797 bus->parent = ds->dev;
798 bus->phy_mask = ~ds->phys_mii_mask;
799
800 ds->slave_mii_bus = bus;
801
802 return devm_of_mdiobus_register(priv->dev, bus, mdio);
803}
804
db460c54
CL		 805static int
806qca8k_setup_mdio_bus(struct qca8k_priv *priv)
807{
808 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
759bafb8
AS		 809 struct device_node *ports, *port, *mdio;
810 phy_interface_t mode;
db460c54
CL		 811 int err;
812
813 ports = of_get_child_by_name(priv->dev->of_node, "ports");
1ee0591a
AS		 814 if (!ports)
815 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
816
db460c54
CL		 817 if (!ports)
818 return -EINVAL;
819
820 for_each_available_child_of_node(ports, port) {
821 err = of_property_read_u32(port, "reg", &reg);
f26e0cca
ND		 822 if (err) {
823 of_node_put(port);
824 of_node_put(ports);
db460c54 825 return err;
f26e0cca 826 }
db460c54
CL		 827
828 if (!dsa_is_user_port(priv->ds, reg))
829 continue;
830
759bafb8
AS		 831 of_get_phy_mode(port, &mode);
832
833 if (of_property_read_bool(port, "phy-handle") &&
834 mode != PHY_INTERFACE_MODE_INTERNAL)
db460c54
CL		 835 external_mdio_mask |= BIT(reg);
836 else
837 internal_mdio_mask |= BIT(reg);
838 }
839
f26e0cca 840 of_node_put(ports);
db460c54
CL		 841 if (!external_mdio_mask && !internal_mdio_mask) {
842 dev_err(priv->dev, "no PHYs are defined.\n");
843 return -EINVAL;
844 }
845
846 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
847 * the MDIO_MASTER register also _disconnects_ the external MDC
848 * passthrough to the internal PHYs. It's not possible to use both
849 * configurations at the same time!
850 *
851 * Because this came up during the review process:
852 * If the external mdio-bus driver is capable magically disabling
853 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
854 * accessors for the time being, it would be possible to pull this
855 * off.
856 */
857 if (!!external_mdio_mask && !!internal_mdio_mask) {
858 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
859 return -EINVAL;
860 }
861
862 if (external_mdio_mask) {
863 /* Make sure to disable the internal mdio bus in cases
864 * a dt-overlay and driver reload changed the configuration
865 */
866
aaf42142
AS		 867 return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
868 QCA8K_MDIO_MASTER_EN);
db460c54
CL		 869 }
870
759bafb8
AS		 871 /* Check if the devicetree declare the port:phy mapping */
872 mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
873 if (of_device_is_available(mdio)) {
874 err = qca8k_mdio_register(priv, mdio);
875 if (err)
876 of_node_put(mdio);
877
878 return err;
879 }
880
881 /* If a mapping can't be found the legacy mapping is used,
882 * using the qca8k_port_to_phy function
883 */
884 priv->legacy_phy_port_mapping = true;
db460c54
CL		 885 priv->ops.phy_read = qca8k_phy_read;
886 priv->ops.phy_write = qca8k_phy_write;
759bafb8 887
db460c54
CL		 888 return 0;
889}
890
e4b9977c
AS		 891static int
892qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
893{
894 struct device_node *port_dn;
895 phy_interface_t mode;
896 struct dsa_port *dp;
897 u32 val;
898
899 /* CPU port is already checked */
900 dp = dsa_to_port(priv->ds, 0);
901
902 port_dn = dp->dn;
903
904 /* Check if port 0 is set to the correct type */
905 of_get_phy_mode(port_dn, &mode);
906 if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
907 mode != PHY_INTERFACE_MODE_RGMII_RXID &&
908 mode != PHY_INTERFACE_MODE_RGMII_TXID) {
909 return 0;
910 }
911
912 switch (mode) {
913 case PHY_INTERFACE_MODE_RGMII_ID:
914 case PHY_INTERFACE_MODE_RGMII_RXID:
915 if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
916 val = 2;
917 else
918 /* Switch regs accept value in ns, convert ps to ns */
919 val = val / 1000;
920
921 if (val > QCA8K_MAX_DELAY) {
922 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
923 val = 3;
924 }
925
926 priv->rgmii_rx_delay = val;
927 /* Stop here if we need to check only for rx delay */
928 if (mode != PHY_INTERFACE_MODE_RGMII_ID)
929 break;
930
931 fallthrough;
932 case PHY_INTERFACE_MODE_RGMII_TXID:
933 if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
934 val = 1;
935 else
936 /* Switch regs accept value in ns, convert ps to ns */
937 val = val / 1000;
938
939 if (val > QCA8K_MAX_DELAY) {
940 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
941 val = 3;
942 }
943
944 priv->rgmii_tx_delay = val;
945 break;
946 default:
947 return 0;
948 }
949
950 return 0;
951}
952
6b93fb46
JC		 953static int
954qca8k_setup(struct dsa_switch *ds)
955{
956 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
0c65b2b9 957 int ret, i;
83a3ceb3 958 u32 mask;
6b93fb46
JC		 959
960 /* Make sure that port 0 is the cpu port */
961 if (!dsa_is_cpu_port(ds, 0)) {
5d9e0684 962 dev_err(priv->dev, "port 0 is not the CPU port");
6b93fb46
JC		 963 return -EINVAL;
964 }
965
966 mutex_init(&priv->reg_mutex);
967
968 /* Start by setting up the register mapping */
969 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
970 &qca8k_regmap_config);
971 if (IS_ERR(priv->regmap))
5d9e0684 972 dev_warn(priv->dev, "regmap initialization failed");
6b93fb46 973
db460c54
CL		 974 ret = qca8k_setup_mdio_bus(priv);
975 if (ret)
976 return ret;
977
e4b9977c
AS		 978 ret = qca8k_setup_of_rgmii_delay(priv);
979 if (ret)
980 return ret;
981
b3591c2a 982 /* Enable CPU Port */
aaf42142
AS		 983 ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
984 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
985 if (ret) {
986 dev_err(priv->dev, "failed enabling CPU port");
987 return ret;
988 }
6b93fb46
JC		 989
990 /* Enable MIB counters */
d7805757
AS		 991 ret = qca8k_mib_init(priv);
992 if (ret)
993 dev_warn(priv->dev, "mib init failed");
6b93fb46
JC		 994
995 /* Enable QCA header mode on the cpu port */
d7805757
AS		 996 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
997 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
998 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
999 if (ret) {
1000 dev_err(priv->dev, "failed enabling QCA header mode");
1001 return ret;
1002 }
6b93fb46
JC		 1003
1004 /* Disable forwarding by default on all ports */
aaf42142
AS		 1005 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1006 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1007 QCA8K_PORT_LOOKUP_MEMBER, 0);
1008 if (ret)
1009 return ret;
1010 }
6b93fb46 1011
b3591c2a 1012 /* Disable MAC by default on all ports */
6b93fb46 1013 for (i = 1; i < QCA8K_NUM_PORTS; i++)
b3591c2a 1014 qca8k_port_set_status(priv, i, 0);
6b93fb46
JC		 1015
1016 /* Forward all unknown frames to CPU port for Linux processing */
d7805757
AS		 1017 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1018 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
1019 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
1020 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
1021 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
1022 if (ret)
1023 return ret;
6b93fb46
JC		 1024
1025 /* Setup connection between CPU port & user ports */
7ae6d93c 1026 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
6b93fb46
JC		 1027 /* CPU port gets connected to all user ports of the switch */
1028 if (dsa_is_cpu_port(ds, i)) {
aaf42142
AS		 1029 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
1030 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1031 if (ret)
1032 return ret;
6b93fb46
JC		 1033 }
1034
a997b337 1035 /* Individual user ports get connected to CPU port only */
4a5b85ff 1036 if (dsa_is_user_port(ds, i)) {
6b93fb46
JC		 1037 int shift = 16 * (i % 2);
1038
aaf42142
AS		 1039 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1040 QCA8K_PORT_LOOKUP_MEMBER,
1041 BIT(QCA8K_CPU_PORT));
1042 if (ret)
1043 return ret;
6b93fb46
JC		 1044
1045 /* Enable ARP Auto-learning by default */
aaf42142
AS		 1046 ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1047 QCA8K_PORT_LOOKUP_LEARN);
1048 if (ret)
1049 return ret;
6b93fb46
JC		 1050
1051 /* For port based vlans to work we need to set the
1052 * default egress vid
1053 */
aaf42142
AS		 1054 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1055 0xfff << shift,
1056 QCA8K_PORT_VID_DEF << shift);
1057 if (ret)
1058 return ret;
1059
d7805757
AS		 1060 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1061 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1062 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1063 if (ret)
1064 return ret;
6b93fb46
JC		 1065 }
1066 }
1067
83a3ceb3
AS		 1068 /* The port 5 of the qca8337 have some problem in flood condition. The
1069 * original legacy driver had some specific buffer and priority settings
1070 * for the different port suggested by the QCA switch team. Add this
1071 * missing settings to improve switch stability under load condition.
1072 * This problem is limited to qca8337 and other qca8k switch are not affected.
1073 */
1074 if (priv->switch_id == QCA8K_ID_QCA8337) {
1075 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1076 switch (i) {
1077 /* The 2 CPU port and port 5 requires some different
1078 * priority than any other ports.
1079 */
1080 case 0:
1081 case 5:
1082 case 6:
1083 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1084 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1085 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1086 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1087 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1088 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1089 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1090 break;
1091 default:
1092 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1093 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1094 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1095 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1096 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1097 }
1098 qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1099
1100 mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1101 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1102 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1103 QCA8K_PORT_HOL_CTRL1_WRED_EN;
1104 qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1105 QCA8K_PORT_HOL_CTRL1_ING_BUF |
1106 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1107 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1108 QCA8K_PORT_HOL_CTRL1_WRED_EN,
1109 mask);
1110 }
1111 }
1112
0fc57e4b
AS		 1113 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1114 if (priv->switch_id == QCA8K_ID_QCA8327) {
1115 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1116 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1117 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1118 QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
1119 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
1120 mask);
1121 }
1122
f58d2598
JM		 1123 /* Setup our port MTUs to match power on defaults */
1124 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1125 priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
d7805757
AS		 1126 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1127 if (ret)
1128 dev_warn(priv->dev, "failed setting MTU settings");
f58d2598 1129
6b93fb46
JC		 1130 /* Flush the FDB table */
1131 qca8k_fdb_flush(priv);
1132
f6dadd55
JM		 1133 /* We don't have interrupts for link changes, so we need to poll */
1134 ds->pcs_poll = true;
1135
6b93fb46
JC		 1136 return 0;
1137}
1138
9bb2289f 1139static void
b3591c2a
JM		 1140qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1141 const struct phylink_link_state *state)
9bb2289f
MV		 1142{
1143 struct qca8k_priv *priv = ds->priv;
f6dadd55 1144 u32 reg, val;
9fe99de0 1145 int ret;
9bb2289f 1146
b3591c2a
JM		 1147 switch (port) {
1148 case 0: /* 1st CPU port */
1149 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1150 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
e4b9977c
AS		 1151 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1152 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
b3591c2a
JM		 1153 state->interface != PHY_INTERFACE_MODE_SGMII)
1154 return;
1155
1156 reg = QCA8K_REG_PORT0_PAD_CTRL;
1157 break;
1158 case 1:
1159 case 2:
1160 case 3:
1161 case 4:
1162 case 5:
1163 /* Internal PHY, nothing to do */
9bb2289f 1164 return;
b3591c2a
JM		 1165 case 6: /* 2nd CPU port / external PHY */
1166 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1167 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
e4b9977c
AS		 1168 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1169 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
b3591c2a
JM		 1170 state->interface != PHY_INTERFACE_MODE_SGMII &&
1171 state->interface != PHY_INTERFACE_MODE_1000BASEX)
1172 return;
9bb2289f 1173
b3591c2a 1174 reg = QCA8K_REG_PORT6_PAD_CTRL;
9bb2289f 1175 break;
b3591c2a
JM		 1176 default:
1177 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1178 return;
1179 }
1180
1181 if (port != 6 && phylink_autoneg_inband(mode)) {
1182 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1183 __func__);
1184 return;
1185 }
1186
1187 switch (state->interface) {
1188 case PHY_INTERFACE_MODE_RGMII:
1189 /* RGMII mode means no delay so don't enable the delay */
1190 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
9bb2289f 1191 break;
b3591c2a 1192 case PHY_INTERFACE_MODE_RGMII_ID:
e4b9977c
AS		 1193 case PHY_INTERFACE_MODE_RGMII_TXID:
1194 case PHY_INTERFACE_MODE_RGMII_RXID:
b3591c2a
JM		 1195 /* RGMII_ID needs internal delay. This is enabled through
1196 * PORT5_PAD_CTRL for all ports, rather than individual port
1197 * registers
1198 */
1199 qca8k_write(priv, reg,
1200 QCA8K_PORT_PAD_RGMII_EN |
e4b9977c
AS		 1201 QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
1202 QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
1203 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1204 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
5bf9ff3b
AS		 1205 /* QCA8337 requires to set rgmii rx delay */
1206 if (priv->switch_id == QCA8K_ID_QCA8337)
1207 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1208 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
b3591c2a
JM		 1209 break;
1210 case PHY_INTERFACE_MODE_SGMII:
1211 case PHY_INTERFACE_MODE_1000BASEX:
1212 /* Enable SGMII on the port */
1213 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
f6dadd55
JM		 1214
1215 /* Enable/disable SerDes auto-negotiation as necessary */
9fe99de0
YY		 1216 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1217 if (ret)
1218 return;
f6dadd55
JM		 1219 if (phylink_autoneg_inband(mode))
1220 val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1221 else
1222 val |= QCA8K_PWS_SERDES_AEN_DIS;
1223 qca8k_write(priv, QCA8K_REG_PWS, val);
1224
1225 /* Configure the SGMII parameters */
9fe99de0
YY		 1226 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1227 if (ret)
1228 return;
f6dadd55
JM		 1229
1230 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1231 QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
1232
1233 if (dsa_is_cpu_port(ds, port)) {
1234 /* CPU port, we're talking to the CPU MAC, be a PHY */
1235 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1236 val |= QCA8K_SGMII_MODE_CTRL_PHY;
1237 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1238 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1239 val |= QCA8K_SGMII_MODE_CTRL_MAC;
1240 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1241 val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1242 val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1243 }
1244
1245 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
b3591c2a
JM		 1246 break;
1247 default:
1248 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1249 phy_modes(state->interface), port);
1250 return;
1251 }
1252}
1253
1254static void
1255qca8k_phylink_validate(struct dsa_switch *ds, int port,
1256 unsigned long *supported,
1257 struct phylink_link_state *state)
1258{
1259 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1260
1261 switch (port) {
1262 case 0: /* 1st CPU port */
1263 if (state->interface != PHY_INTERFACE_MODE_NA &&
1264 state->interface != PHY_INTERFACE_MODE_RGMII &&
1265 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
e4b9977c
AS		 1266 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1267 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
b3591c2a
JM		 1268 state->interface != PHY_INTERFACE_MODE_SGMII)
1269 goto unsupported;
1270 break;
1271 case 1:
1272 case 2:
1273 case 3:
1274 case 4:
1275 case 5:
1276 /* Internal PHY */
1277 if (state->interface != PHY_INTERFACE_MODE_NA &&
759bafb8
AS		 1278 state->interface != PHY_INTERFACE_MODE_GMII &&
1279 state->interface != PHY_INTERFACE_MODE_INTERNAL)
b3591c2a
JM		 1280 goto unsupported;
1281 break;
1282 case 6: /* 2nd CPU port / external PHY */
1283 if (state->interface != PHY_INTERFACE_MODE_NA &&
1284 state->interface != PHY_INTERFACE_MODE_RGMII &&
1285 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
e4b9977c
AS		 1286 state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1287 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
b3591c2a
JM		 1288 state->interface != PHY_INTERFACE_MODE_SGMII &&
1289 state->interface != PHY_INTERFACE_MODE_1000BASEX)
1290 goto unsupported;
9bb2289f
MV		 1291 break;
1292 default:
b3591c2a
JM		 1293unsupported:
1294 linkmode_zero(supported);
9bb2289f
MV		 1295 return;
1296 }
1297
b3591c2a
JM		 1298 phylink_set_port_modes(mask);
1299 phylink_set(mask, Autoneg);
1300
1301 phylink_set(mask, 1000baseT_Full);
1302 phylink_set(mask, 10baseT_Half);
1303 phylink_set(mask, 10baseT_Full);
1304 phylink_set(mask, 100baseT_Half);
1305 phylink_set(mask, 100baseT_Full);
1306
1307 if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1308 phylink_set(mask, 1000baseX_Full);
1309
1310 phylink_set(mask, Pause);
1311 phylink_set(mask, Asym_Pause);
1312
1313 linkmode_and(supported, supported, mask);
1314 linkmode_and(state->advertising, state->advertising, mask);
1315}
1316
1317static int
1318qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1319 struct phylink_link_state *state)
1320{
1321 struct qca8k_priv *priv = ds->priv;
1322 u32 reg;
7c9896e3 1323 int ret;
b3591c2a 1324
7c9896e3
YY		 1325 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1326 if (ret < 0)
1327 return ret;
b3591c2a
JM		 1328
1329 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1330 state->an_complete = state->link;
1331 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1332 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1333 DUPLEX_HALF;
1334
1335 switch (reg & QCA8K_PORT_STATUS_SPEED) {
1336 case QCA8K_PORT_STATUS_SPEED_10:
1337 state->speed = SPEED_10;
1338 break;
1339 case QCA8K_PORT_STATUS_SPEED_100:
1340 state->speed = SPEED_100;
1341 break;
1342 case QCA8K_PORT_STATUS_SPEED_1000:
1343 state->speed = SPEED_1000;
1344 break;
1345 default:
1346 state->speed = SPEED_UNKNOWN;
1347 break;
1348 }
1349
1350 state->pause = MLO_PAUSE_NONE;
1351 if (reg & QCA8K_PORT_STATUS_RXFLOW)
1352 state->pause |= MLO_PAUSE_RX;
1353 if (reg & QCA8K_PORT_STATUS_TXFLOW)
1354 state->pause |= MLO_PAUSE_TX;
1355
1356 return 1;
1357}
9bb2289f 1358
b3591c2a
JM		 1359static void
1360qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1361 phy_interface_t interface)
1362{
1363 struct qca8k_priv *priv = ds->priv;
9bb2289f 1364
9bb2289f 1365 qca8k_port_set_status(priv, port, 0);
b3591c2a
JM		 1366}
1367
1368static void
1369qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1370 phy_interface_t interface, struct phy_device *phydev,
1371 int speed, int duplex, bool tx_pause, bool rx_pause)
1372{
1373 struct qca8k_priv *priv = ds->priv;
1374 u32 reg;
1375
1376 if (phylink_autoneg_inband(mode)) {
1377 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1378 } else {
1379 switch (speed) {
1380 case SPEED_10:
1381 reg = QCA8K_PORT_STATUS_SPEED_10;
1382 break;
1383 case SPEED_100:
1384 reg = QCA8K_PORT_STATUS_SPEED_100;
1385 break;
1386 case SPEED_1000:
1387 reg = QCA8K_PORT_STATUS_SPEED_1000;
1388 break;
1389 default:
1390 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1391 break;
1392 }
1393
1394 if (duplex == DUPLEX_FULL)
1395 reg |= QCA8K_PORT_STATUS_DUPLEX;
1396
1397 if (rx_pause || dsa_is_cpu_port(ds, port))
1398 reg |= QCA8K_PORT_STATUS_RXFLOW;
1399
1400 if (tx_pause || dsa_is_cpu_port(ds, port))
1401 reg |= QCA8K_PORT_STATUS_TXFLOW;
1402 }
1403
1404 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1405
9bb2289f 1406 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
9bb2289f
MV		 1407}
1408
6b93fb46 1409static void
89f09048 1410qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
6b93fb46
JC		 1411{
1412 int i;
1413
89f09048
FF		 1414 if (stringset != ETH_SS_STATS)
1415 return;
1416
6b93fb46
JC		 1417 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1418 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1419 ETH_GSTRING_LEN);
1420}
1421
1422static void
1423qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1424 uint64_t *data)
1425{
1426 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1427 const struct qca8k_mib_desc *mib;
028f5f8e 1428 u32 reg, i, val;
aa3d020b 1429 u32 hi = 0;
7c9896e3 1430 int ret;
6b93fb46
JC		 1431
1432 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1433 mib = &ar8327_mib[i];
1434 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1435
7c9896e3
YY		 1436 ret = qca8k_read(priv, reg, &val);
1437 if (ret < 0)
028f5f8e
AS		 1438 continue;
1439
6b93fb46 1440 if (mib->size == 2) {
aa3d020b 1441 ret = qca8k_read(priv, reg + 4, &hi);
7c9896e3 1442 if (ret < 0)
028f5f8e 1443 continue;
6b93fb46 1444 }
028f5f8e
AS		 1445
1446 data[i] = val;
1447 if (mib->size == 2)
aa3d020b 1448 data[i] |= (u64)hi << 32;
6b93fb46
JC		 1449 }
1450}
1451
1452static int
89f09048 1453qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
6b93fb46 1454{
89f09048
FF		 1455 if (sset != ETH_SS_STATS)
1456 return 0;
1457
6b93fb46
JC		 1458 return ARRAY_SIZE(ar8327_mib);
1459}
1460
46587e4a 1461static int
08f50061 1462qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
6b93fb46
JC		 1463{
1464 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1465 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1466 u32 reg;
d7805757 1467 int ret;
6b93fb46
JC		 1468
1469 mutex_lock(&priv->reg_mutex);
7c9896e3 1470 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
3d0167f2 1471 if (ret < 0)
028f5f8e 1472 goto exit;
028f5f8e 1473
46587e4a 1474 if (eee->eee_enabled)
6b93fb46
JC		 1475 reg |= lpi_en;
1476 else
1477 reg &= ~lpi_en;
d7805757 1478 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
6b93fb46 1479
028f5f8e
AS		 1480exit:
1481 mutex_unlock(&priv->reg_mutex);
1482 return ret;
6b93fb46
JC		 1483}
1484
1485static int
08f50061 1486qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
6b93fb46 1487{
193da90e
VD		 1488 /* Nothing to do on the port's MAC */
1489 return 0;
6b93fb46
JC		 1490}
1491
1492static void
1493qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1494{
1495 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1496 u32 stp_state;
1497
1498 switch (state) {
1499 case BR_STATE_DISABLED:
1500 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1501 break;
1502 case BR_STATE_BLOCKING:
1503 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1504 break;
1505 case BR_STATE_LISTENING:
1506 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1507 break;
1508 case BR_STATE_LEARNING:
1509 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1510 break;
1511 case BR_STATE_FORWARDING:
1512 default:
1513 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1514 break;
1515 }
1516
1517 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1518 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1519}
1520
1521static int
922754a4 1522qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 1523{
1524 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1525 int port_mask = BIT(QCA8K_CPU_PORT);
aaf42142 1526 int i, ret;
6b93fb46 1527
6b93fb46 1528 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 1529 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 1530 continue;
1531 /* Add this port to the portvlan mask of the other ports
1532 * in the bridge
1533 */
aaf42142
AS		 1534 ret = qca8k_reg_set(priv,
1535 QCA8K_PORT_LOOKUP_CTRL(i),
1536 BIT(port));
1537 if (ret)
1538 return ret;
6b93fb46
JC		 1539 if (i != port)
1540 port_mask |= BIT(i);
1541 }
aaf42142 1542
6b93fb46 1543 /* Add all other ports to this ports portvlan mask */
aaf42142
AS		 1544 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1545 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
6b93fb46 1546
aaf42142 1547 return ret;
6b93fb46
JC		 1548}
1549
1550static void
f123f2fb 1551qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 1552{
1553 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1554 int i;
1555
1556 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 1557 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 1558 continue;
1559 /* Remove this port to the portvlan mask of the other ports
1560 * in the bridge
1561 */
1562 qca8k_reg_clear(priv,
1563 QCA8K_PORT_LOOKUP_CTRL(i),
1564 BIT(port));
1565 }
922754a4 1566
6b93fb46
JC		 1567 /* Set the cpu port to be the only one in the portvlan mask of
1568 * this port
1569 */
1570 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1571 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
1572}
1573
1574static int
1575qca8k_port_enable(struct dsa_switch *ds, int port,
1576 struct phy_device *phy)
1577{
1578 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1579
1580 qca8k_port_set_status(priv, port, 1);
1581 priv->port_sts[port].enabled = 1;
1582
b3591c2a
JM		 1583 if (dsa_is_user_port(ds, port))
1584 phy_support_asym_pause(phy);
abb48f80 1585
6b93fb46
JC		 1586 return 0;
1587}
1588
1589static void
75104db0 1590qca8k_port_disable(struct dsa_switch *ds, int port)
6b93fb46
JC		 1591{
1592 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1593
1594 qca8k_port_set_status(priv, port, 0);
1595 priv->port_sts[port].enabled = 0;
1596}
1597
f58d2598
JM		 1598static int
1599qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1600{
1601 struct qca8k_priv *priv = ds->priv;
1602 int i, mtu = 0;
1603
1604 priv->port_mtu[port] = new_mtu;
1605
1606 for (i = 0; i < QCA8K_NUM_PORTS; i++)
99cab710
JM		 1607 if (priv->port_mtu[i] > mtu)
1608 mtu = priv->port_mtu[i];
f58d2598
JM		 1609
1610 /* Include L2 header / FCS length */
d7805757 1611 return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
f58d2598
JM		 1612}
1613
1614static int
1615qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1616{
1617 return QCA8K_MAX_MTU;
1618}
1619
6b93fb46
JC		 1620static int
1621qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1622 u16 port_mask, u16 vid)
1623{
1624 /* Set the vid to the port vlan id if no vid is set */
1625 if (!vid)
e9d204fd 1626 vid = QCA8K_PORT_VID_DEF;
6b93fb46
JC		 1627
1628 return qca8k_fdb_add(priv, addr, port_mask, vid,
1629 QCA8K_ATU_STATUS_STATIC);
1630}
1631
1632static int
6b93fb46 1633qca8k_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1634 const unsigned char *addr, u16 vid)
6b93fb46
JC		 1635{
1636 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1637 u16 port_mask = BIT(port);
1638
1b6dd556 1639 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
6b93fb46
JC		 1640}
1641
1642static int
1643qca8k_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1644 const unsigned char *addr, u16 vid)
6b93fb46
JC		 1645{
1646 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1647 u16 port_mask = BIT(port);
6b93fb46
JC		 1648
1649 if (!vid)
e9d204fd 1650 vid = QCA8K_PORT_VID_DEF;
6b93fb46 1651
6c2c1dcb 1652 return qca8k_fdb_del(priv, addr, port_mask, vid);
6b93fb46
JC		 1653}
1654
1655static int
1656qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1657 dsa_fdb_dump_cb_t *cb, void *data)
6b93fb46
JC		 1658{
1659 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1660 struct qca8k_fdb _fdb = { 0 };
1661 int cnt = QCA8K_NUM_FDB_RECORDS;
2bedde1a 1662 bool is_static;
6b93fb46
JC		 1663 int ret = 0;
1664
1665 mutex_lock(&priv->reg_mutex);
1666 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1667 if (!_fdb.aging)
1668 break;
2bedde1a
AS		 1669 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1670 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
6b93fb46
JC		 1671 if (ret)
1672 break;
1673 }
1674 mutex_unlock(&priv->reg_mutex);
1675
1676 return 0;
1677}
1678
69462fe6 1679static int
89153ed6
VO		 1680qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1681 struct netlink_ext_ack *extack)
69462fe6
JM		 1682{
1683 struct qca8k_priv *priv = ds->priv;
aaf42142 1684 int ret;
69462fe6
JM		 1685
1686 if (vlan_filtering) {
aaf42142
AS		 1687 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1688 QCA8K_PORT_LOOKUP_VLAN_MODE,
1689 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
69462fe6 1690 } else {
aaf42142
AS		 1691 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1692 QCA8K_PORT_LOOKUP_VLAN_MODE,
1693 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
69462fe6
JM		 1694 }
1695
aaf42142 1696 return ret;
69462fe6
JM		 1697}
1698
1699static int
69462fe6 1700qca8k_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1701 const struct switchdev_obj_port_vlan *vlan,
1702 struct netlink_ext_ack *extack)
69462fe6
JM		 1703{
1704 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1705 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1706 struct qca8k_priv *priv = ds->priv;
d7805757 1707 int ret;
69462fe6 1708
b7a9e0da 1709 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1958d581 1710 if (ret) {
69462fe6 1711 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1958d581
VO		 1712 return ret;
1713 }
69462fe6
JM		 1714
1715 if (pvid) {
1716 int shift = 16 * (port % 2);
1717
aaf42142
AS		 1718 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1719 0xfff << shift, vlan->vid << shift);
1720 if (ret)
1721 return ret;
1722
d7805757
AS		 1723 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1724 QCA8K_PORT_VLAN_CVID(vlan->vid) |
1725 QCA8K_PORT_VLAN_SVID(vlan->vid));
69462fe6 1726 }
1958d581 1727
aaf42142 1728 return ret;
69462fe6
JM		 1729}
1730
1731static int
1732qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1733 const struct switchdev_obj_port_vlan *vlan)
1734{
1735 struct qca8k_priv *priv = ds->priv;
d7805757 1736 int ret;
69462fe6 1737
b7a9e0da 1738 ret = qca8k_vlan_del(priv, port, vlan->vid);
69462fe6
JM		 1739 if (ret)
1740 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1741
1742 return ret;
1743}
1744
a46aec02
AS		 1745static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
1746{
1747 struct qca8k_priv *priv = ds->priv;
1748
1749 /* Communicate to the phy internal driver the switch revision.
1750 * Based on the switch revision different values needs to be
1751 * set to the dbg and mmd reg on the phy.
1752 * The first 2 bit are used to communicate the switch revision
1753 * to the phy driver.
1754 */
1755 if (port > 0 && port < 6)
1756 return priv->switch_revision;
1757
1758 return 0;
1759}
1760
6b93fb46 1761static enum dsa_tag_protocol
4d776482
FF		 1762qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1763 enum dsa_tag_protocol mp)
6b93fb46
JC		 1764{
1765 return DSA_TAG_PROTO_QCA;
1766}
1767
a82f67af 1768static const struct dsa_switch_ops qca8k_switch_ops = {
6b93fb46
JC		 1769 .get_tag_protocol = qca8k_get_tag_protocol,
1770 .setup = qca8k_setup,
6b93fb46 1771 .get_strings = qca8k_get_strings,
6b93fb46
JC		 1772 .get_ethtool_stats = qca8k_get_ethtool_stats,
1773 .get_sset_count = qca8k_get_sset_count,
08f50061
VD		 1774 .get_mac_eee = qca8k_get_mac_eee,
1775 .set_mac_eee = qca8k_set_mac_eee,
6b93fb46
JC		 1776 .port_enable = qca8k_port_enable,
1777 .port_disable = qca8k_port_disable,
f58d2598
JM		 1778 .port_change_mtu = qca8k_port_change_mtu,
1779 .port_max_mtu = qca8k_port_max_mtu,
6b93fb46
JC		 1780 .port_stp_state_set = qca8k_port_stp_state_set,
1781 .port_bridge_join = qca8k_port_bridge_join,
1782 .port_bridge_leave = qca8k_port_bridge_leave,
6b93fb46
JC		 1783 .port_fdb_add = qca8k_port_fdb_add,
1784 .port_fdb_del = qca8k_port_fdb_del,
1785 .port_fdb_dump = qca8k_port_fdb_dump,
69462fe6 1786 .port_vlan_filtering = qca8k_port_vlan_filtering,
69462fe6
JM		 1787 .port_vlan_add = qca8k_port_vlan_add,
1788 .port_vlan_del = qca8k_port_vlan_del,
b3591c2a
JM		 1789 .phylink_validate = qca8k_phylink_validate,
1790 .phylink_mac_link_state = qca8k_phylink_mac_link_state,
1791 .phylink_mac_config = qca8k_phylink_mac_config,
1792 .phylink_mac_link_down = qca8k_phylink_mac_link_down,
1793 .phylink_mac_link_up = qca8k_phylink_mac_link_up,
a46aec02 1794 .get_phy_flags = qca8k_get_phy_flags,
6b93fb46
JC		 1795};
1796
95ffeaf1
AS		 1797static int qca8k_read_switch_id(struct qca8k_priv *priv)
1798{
1799 const struct qca8k_match_data *data;
1800 u32 val;
1801 u8 id;
7c9896e3 1802 int ret;
95ffeaf1
AS		 1803
1804 /* get the switches ID from the compatible */
1805 data = of_device_get_match_data(priv->dev);
1806 if (!data)
1807 return -ENODEV;
1808
7c9896e3
YY		 1809 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
1810 if (ret < 0)
95ffeaf1
AS		 1811 return -ENODEV;
1812
1813 id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
1814 if (id != data->id) {
1815 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
1816 return -ENODEV;
1817 }
1818
1819 priv->switch_id = id;
1820
1821 /* Save revision to communicate to the internal PHY driver */
1822 priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
1823
1824 return 0;
1825}
1826
6b93fb46
JC		 1827static int
1828qca8k_sw_probe(struct mdio_device *mdiodev)
1829{
1830 struct qca8k_priv *priv;
95ffeaf1 1831 int ret;
6b93fb46
JC		 1832
1833 /* allocate the private data struct so that we can probe the switches
1834 * ID register
1835 */
1836 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1837 if (!priv)
1838 return -ENOMEM;
1839
1840 priv->bus = mdiodev->bus;
9bb2289f 1841 priv->dev = &mdiodev->dev;
6b93fb46 1842
a653f2f5
CL		 1843 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
1844 GPIOD_ASIS);
1845 if (IS_ERR(priv->reset_gpio))
1846 return PTR_ERR(priv->reset_gpio);
1847
1848 if (priv->reset_gpio) {
1849 gpiod_set_value_cansleep(priv->reset_gpio, 1);
1850 /* The active low duration must be greater than 10 ms
1851 * and checkpatch.pl wants 20 ms.
1852 */
1853 msleep(20);
1854 gpiod_set_value_cansleep(priv->reset_gpio, 0);
1855 }
1856
95ffeaf1
AS		 1857 /* Check the detected switch id */
1858 ret = qca8k_read_switch_id(priv);
1859 if (ret)
1860 return ret;
6b93fb46 1861
67122a79 1862 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
6b93fb46
JC		 1863 if (!priv->ds)
1864 return -ENOMEM;
1865
7e99e347 1866 priv->ds->dev = &mdiodev->dev;
f0d532c4 1867 priv->ds->num_ports = QCA8K_NUM_PORTS;
6b93fb46 1868 priv->ds->priv = priv;
db460c54
CL		 1869 priv->ops = qca8k_switch_ops;
1870 priv->ds->ops = &priv->ops;
6b93fb46
JC		 1871 mutex_init(&priv->reg_mutex);
1872 dev_set_drvdata(&mdiodev->dev, priv);
1873
23c9ee49 1874 return dsa_register_switch(priv->ds);
6b93fb46
JC		 1875}
1876
1877static void
1878qca8k_sw_remove(struct mdio_device *mdiodev)
1879{
1880 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1881 int i;
1882
0650bf52
VO		 1883 if (!priv)
1884 return;
1885
6b93fb46
JC		 1886 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1887 qca8k_port_set_status(priv, i, 0);
1888
1889 dsa_unregister_switch(priv->ds);
0650bf52
VO		 1890
1891 dev_set_drvdata(&mdiodev->dev, NULL);
1892}
1893
1894static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
1895{
1896 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1897
1898 if (!priv)
1899 return;
1900
1901 dsa_switch_shutdown(priv->ds);
1902
1903 dev_set_drvdata(&mdiodev->dev, NULL);
6b93fb46
JC		 1904}
1905
1906#ifdef CONFIG_PM_SLEEP
1907static void
1908qca8k_set_pm(struct qca8k_priv *priv, int enable)
1909{
1910 int i;
1911
1912 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1913 if (!priv->port_sts[i].enabled)
1914 continue;
1915
1916 qca8k_port_set_status(priv, i, enable);
1917 }
1918}
1919
1920static int qca8k_suspend(struct device *dev)
1921{
717de370 1922 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1923
1924 qca8k_set_pm(priv, 0);
1925
1926 return dsa_switch_suspend(priv->ds);
1927}
1928
1929static int qca8k_resume(struct device *dev)
1930{
717de370 1931 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1932
1933 qca8k_set_pm(priv, 1);
1934
1935 return dsa_switch_resume(priv->ds);
1936}
1937#endif /* CONFIG_PM_SLEEP */
1938
1939static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1940 qca8k_suspend, qca8k_resume);
1941
6e82a457
AS		 1942static const struct qca8k_match_data qca832x = {
1943 .id = QCA8K_ID_QCA8327,
1944};
1945
1946static const struct qca8k_match_data qca833x = {
1947 .id = QCA8K_ID_QCA8337,
1948};
1949
6b93fb46 1950static const struct of_device_id qca8k_of_match[] = {
6e82a457
AS		 1951 { .compatible = "qca,qca8327", .data = &qca832x },
1952 { .compatible = "qca,qca8334", .data = &qca833x },
1953 { .compatible = "qca,qca8337", .data = &qca833x },
6b93fb46
JC		 1954 { /* sentinel */ },
1955};
1956
1957static struct mdio_driver qca8kmdio_driver = {
1958 .probe = qca8k_sw_probe,
1959 .remove = qca8k_sw_remove,
0650bf52 1960 .shutdown = qca8k_sw_shutdown,
6b93fb46
JC		 1961 .mdiodrv.driver = {
1962 .name = "qca8k",
1963 .of_match_table = qca8k_of_match,
1964 .pm = &qca8k_pm_ops,
1965 },
1966};
1967
a084ab33 1968mdio_module_driver(qca8kmdio_driver);
6b93fb46
JC		 1969
1970MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1971MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1972MODULE_LICENSE("GPL v2");
1973MODULE_ALIAS("platform:qca8k");
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