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8aa9ebcc VO |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH | |
3 | * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> | |
4 | */ | |
5 | ||
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
7 | ||
8 | #include <linux/delay.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/printk.h> | |
11 | #include <linux/spi/spi.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/gpio/consumer.h> | |
ad9f299a | 14 | #include <linux/phylink.h> |
8aa9ebcc VO |
15 | #include <linux/of.h> |
16 | #include <linux/of_net.h> | |
17 | #include <linux/of_mdio.h> | |
18 | #include <linux/of_device.h> | |
3ad1d171 | 19 | #include <linux/pcs/pcs-xpcs.h> |
8aa9ebcc VO |
20 | #include <linux/netdev_features.h> |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/if_bridge.h> | |
23 | #include <linux/if_ether.h> | |
227d07a0 | 24 | #include <linux/dsa/8021q.h> |
8aa9ebcc | 25 | #include "sja1105.h" |
317ab5b8 | 26 | #include "sja1105_tas.h" |
8aa9ebcc | 27 | |
4d942354 | 28 | #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull |
ed040abc | 29 | #define SJA1105_DEFAULT_VLAN (VLAN_N_VID - 1) |
4d942354 | 30 | |
ac02a451 VO |
31 | static const struct dsa_switch_ops sja1105_switch_ops; |
32 | ||
8aa9ebcc VO |
33 | static void sja1105_hw_reset(struct gpio_desc *gpio, unsigned int pulse_len, |
34 | unsigned int startup_delay) | |
35 | { | |
36 | gpiod_set_value_cansleep(gpio, 1); | |
37 | /* Wait for minimum reset pulse length */ | |
38 | msleep(pulse_len); | |
39 | gpiod_set_value_cansleep(gpio, 0); | |
40 | /* Wait until chip is ready after reset */ | |
41 | msleep(startup_delay); | |
42 | } | |
43 | ||
44 | static void | |
45 | sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd, | |
46 | int from, int to, bool allow) | |
47 | { | |
4d942354 | 48 | if (allow) |
8aa9ebcc | 49 | l2_fwd[from].reach_port |= BIT(to); |
4d942354 | 50 | else |
8aa9ebcc | 51 | l2_fwd[from].reach_port &= ~BIT(to); |
8aa9ebcc VO |
52 | } |
53 | ||
7f7ccdea VO |
54 | static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd, |
55 | int from, int to) | |
56 | { | |
57 | return !!(l2_fwd[from].reach_port & BIT(to)); | |
58 | } | |
59 | ||
bef0746c VO |
60 | static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid) |
61 | { | |
62 | struct sja1105_vlan_lookup_entry *vlan; | |
63 | int count, i; | |
64 | ||
65 | vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; | |
66 | count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; | |
67 | ||
68 | for (i = 0; i < count; i++) | |
69 | if (vlan[i].vlanid == vid) | |
70 | return i; | |
71 | ||
72 | /* Return an invalid entry index if not found */ | |
73 | return -1; | |
74 | } | |
75 | ||
76 | static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop) | |
77 | { | |
78 | struct sja1105_private *priv = ds->priv; | |
79 | struct sja1105_mac_config_entry *mac; | |
80 | ||
81 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
82 | ||
83 | if (mac[port].drpuntag == drop) | |
84 | return 0; | |
85 | ||
86 | mac[port].drpuntag = drop; | |
87 | ||
88 | return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
89 | &mac[port], true); | |
90 | } | |
91 | ||
cde8078e VO |
92 | static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid) |
93 | { | |
94 | struct sja1105_mac_config_entry *mac; | |
95 | ||
96 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
97 | ||
98 | if (mac[port].vlanid == pvid) | |
99 | return 0; | |
100 | ||
101 | mac[port].vlanid = pvid; | |
102 | ||
103 | return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
104 | &mac[port], true); | |
105 | } | |
106 | ||
107 | static int sja1105_commit_pvid(struct dsa_switch *ds, int port) | |
108 | { | |
109 | struct dsa_port *dp = dsa_to_port(ds, port); | |
110 | struct sja1105_private *priv = ds->priv; | |
bef0746c VO |
111 | struct sja1105_vlan_lookup_entry *vlan; |
112 | bool drop_untagged = false; | |
113 | int match, rc; | |
cde8078e VO |
114 | u16 pvid; |
115 | ||
116 | if (dp->bridge_dev && br_vlan_enabled(dp->bridge_dev)) | |
117 | pvid = priv->bridge_pvid[port]; | |
118 | else | |
119 | pvid = priv->tag_8021q_pvid[port]; | |
120 | ||
bef0746c VO |
121 | rc = sja1105_pvid_apply(priv, port, pvid); |
122 | if (rc) | |
123 | return rc; | |
124 | ||
125 | vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; | |
126 | ||
127 | match = sja1105_is_vlan_configured(priv, pvid); | |
128 | ||
129 | if (match < 0 || !(vlan[match].vmemb_port & BIT(port))) | |
130 | drop_untagged = true; | |
131 | ||
132 | return sja1105_drop_untagged(ds, port, drop_untagged); | |
cde8078e VO |
133 | } |
134 | ||
8aa9ebcc VO |
135 | static int sja1105_init_mac_settings(struct sja1105_private *priv) |
136 | { | |
137 | struct sja1105_mac_config_entry default_mac = { | |
138 | /* Enable all 8 priority queues on egress. | |
139 | * Every queue i holds top[i] - base[i] frames. | |
140 | * Sum of top[i] - base[i] is 511 (max hardware limit). | |
141 | */ | |
142 | .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF}, | |
143 | .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, | |
144 | .enabled = {true, true, true, true, true, true, true, true}, | |
145 | /* Keep standard IFG of 12 bytes on egress. */ | |
146 | .ifg = 0, | |
147 | /* Always put the MAC speed in automatic mode, where it can be | |
1fd4a173 | 148 | * adjusted at runtime by PHYLINK. |
8aa9ebcc | 149 | */ |
41fed17f | 150 | .speed = priv->info->port_speed[SJA1105_SPEED_AUTO], |
8aa9ebcc VO |
151 | /* No static correction for 1-step 1588 events */ |
152 | .tp_delin = 0, | |
153 | .tp_delout = 0, | |
154 | /* Disable aging for critical TTEthernet traffic */ | |
155 | .maxage = 0xFF, | |
156 | /* Internal VLAN (pvid) to apply to untagged ingress */ | |
157 | .vlanprio = 0, | |
e3502b82 | 158 | .vlanid = 1, |
8aa9ebcc VO |
159 | .ing_mirr = false, |
160 | .egr_mirr = false, | |
161 | /* Don't drop traffic with other EtherType than ETH_P_IP */ | |
162 | .drpnona664 = false, | |
163 | /* Don't drop double-tagged traffic */ | |
164 | .drpdtag = false, | |
165 | /* Don't drop untagged traffic */ | |
166 | .drpuntag = false, | |
167 | /* Don't retag 802.1p (VID 0) traffic with the pvid */ | |
168 | .retag = false, | |
640f763f VO |
169 | /* Disable learning and I/O on user ports by default - |
170 | * STP will enable it. | |
171 | */ | |
172 | .dyn_learn = false, | |
8aa9ebcc VO |
173 | .egress = false, |
174 | .ingress = false, | |
175 | }; | |
176 | struct sja1105_mac_config_entry *mac; | |
542043e9 | 177 | struct dsa_switch *ds = priv->ds; |
8aa9ebcc VO |
178 | struct sja1105_table *table; |
179 | int i; | |
180 | ||
181 | table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; | |
182 | ||
183 | /* Discard previous MAC Configuration Table */ | |
184 | if (table->entry_count) { | |
185 | kfree(table->entries); | |
186 | table->entry_count = 0; | |
187 | } | |
188 | ||
fd6f2c25 | 189 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
190 | table->ops->unpacked_entry_size, GFP_KERNEL); |
191 | if (!table->entries) | |
192 | return -ENOMEM; | |
193 | ||
fd6f2c25 | 194 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
195 | |
196 | mac = table->entries; | |
197 | ||
542043e9 | 198 | for (i = 0; i < ds->num_ports; i++) { |
8aa9ebcc | 199 | mac[i] = default_mac; |
b0b33b04 VO |
200 | |
201 | /* Let sja1105_bridge_stp_state_set() keep address learning | |
202 | * enabled for the CPU port. | |
203 | */ | |
204 | if (dsa_is_cpu_port(ds, i)) | |
205 | priv->learn_ena |= BIT(i); | |
640f763f | 206 | } |
8aa9ebcc VO |
207 | |
208 | return 0; | |
209 | } | |
210 | ||
5d645df9 | 211 | static int sja1105_init_mii_settings(struct sja1105_private *priv) |
8aa9ebcc VO |
212 | { |
213 | struct device *dev = &priv->spidev->dev; | |
214 | struct sja1105_xmii_params_entry *mii; | |
542043e9 | 215 | struct dsa_switch *ds = priv->ds; |
8aa9ebcc VO |
216 | struct sja1105_table *table; |
217 | int i; | |
218 | ||
219 | table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS]; | |
220 | ||
221 | /* Discard previous xMII Mode Parameters Table */ | |
222 | if (table->entry_count) { | |
223 | kfree(table->entries); | |
224 | table->entry_count = 0; | |
225 | } | |
226 | ||
fd6f2c25 | 227 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
228 | table->ops->unpacked_entry_size, GFP_KERNEL); |
229 | if (!table->entries) | |
230 | return -ENOMEM; | |
231 | ||
1fd4a173 | 232 | /* Override table based on PHYLINK DT bindings */ |
fd6f2c25 | 233 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
234 | |
235 | mii = table->entries; | |
236 | ||
542043e9 | 237 | for (i = 0; i < ds->num_ports; i++) { |
5d645df9 VO |
238 | sja1105_mii_role_t role = XMII_MAC; |
239 | ||
ee9d0cb6 VO |
240 | if (dsa_is_unused_port(priv->ds, i)) |
241 | continue; | |
242 | ||
5d645df9 | 243 | switch (priv->phy_mode[i]) { |
5a8f0974 VO |
244 | case PHY_INTERFACE_MODE_INTERNAL: |
245 | if (priv->info->internal_phy[i] == SJA1105_NO_PHY) | |
246 | goto unsupported; | |
247 | ||
248 | mii->xmii_mode[i] = XMII_MODE_MII; | |
249 | if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX) | |
250 | mii->special[i] = true; | |
251 | ||
252 | break; | |
5d645df9 VO |
253 | case PHY_INTERFACE_MODE_REVMII: |
254 | role = XMII_PHY; | |
255 | fallthrough; | |
8aa9ebcc | 256 | case PHY_INTERFACE_MODE_MII: |
91a05078 VO |
257 | if (!priv->info->supports_mii[i]) |
258 | goto unsupported; | |
259 | ||
8aa9ebcc VO |
260 | mii->xmii_mode[i] = XMII_MODE_MII; |
261 | break; | |
5d645df9 VO |
262 | case PHY_INTERFACE_MODE_REVRMII: |
263 | role = XMII_PHY; | |
264 | fallthrough; | |
8aa9ebcc | 265 | case PHY_INTERFACE_MODE_RMII: |
91a05078 VO |
266 | if (!priv->info->supports_rmii[i]) |
267 | goto unsupported; | |
268 | ||
8aa9ebcc VO |
269 | mii->xmii_mode[i] = XMII_MODE_RMII; |
270 | break; | |
271 | case PHY_INTERFACE_MODE_RGMII: | |
272 | case PHY_INTERFACE_MODE_RGMII_ID: | |
273 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
274 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
91a05078 VO |
275 | if (!priv->info->supports_rgmii[i]) |
276 | goto unsupported; | |
277 | ||
8aa9ebcc VO |
278 | mii->xmii_mode[i] = XMII_MODE_RGMII; |
279 | break; | |
ffe10e67 | 280 | case PHY_INTERFACE_MODE_SGMII: |
91a05078 VO |
281 | if (!priv->info->supports_sgmii[i]) |
282 | goto unsupported; | |
283 | ||
284 | mii->xmii_mode[i] = XMII_MODE_SGMII; | |
ece578bc | 285 | mii->special[i] = true; |
91a05078 VO |
286 | break; |
287 | case PHY_INTERFACE_MODE_2500BASEX: | |
288 | if (!priv->info->supports_2500basex[i]) | |
289 | goto unsupported; | |
290 | ||
ffe10e67 | 291 | mii->xmii_mode[i] = XMII_MODE_SGMII; |
ece578bc | 292 | mii->special[i] = true; |
ffe10e67 | 293 | break; |
91a05078 | 294 | unsupported: |
8aa9ebcc | 295 | default: |
91a05078 | 296 | dev_err(dev, "Unsupported PHY mode %s on port %d!\n", |
5d645df9 | 297 | phy_modes(priv->phy_mode[i]), i); |
6729188d | 298 | return -EINVAL; |
8aa9ebcc VO |
299 | } |
300 | ||
5d645df9 | 301 | mii->phy_mac[i] = role; |
8aa9ebcc VO |
302 | } |
303 | return 0; | |
304 | } | |
305 | ||
306 | static int sja1105_init_static_fdb(struct sja1105_private *priv) | |
307 | { | |
4d942354 | 308 | struct sja1105_l2_lookup_entry *l2_lookup; |
8aa9ebcc | 309 | struct sja1105_table *table; |
4d942354 | 310 | int port; |
8aa9ebcc VO |
311 | |
312 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; | |
313 | ||
4d942354 VO |
314 | /* We only populate the FDB table through dynamic L2 Address Lookup |
315 | * entries, except for a special entry at the end which is a catch-all | |
316 | * for unknown multicast and will be used to control flooding domain. | |
291d1e72 | 317 | */ |
8aa9ebcc VO |
318 | if (table->entry_count) { |
319 | kfree(table->entries); | |
320 | table->entry_count = 0; | |
321 | } | |
4d942354 VO |
322 | |
323 | if (!priv->info->can_limit_mcast_flood) | |
324 | return 0; | |
325 | ||
326 | table->entries = kcalloc(1, table->ops->unpacked_entry_size, | |
327 | GFP_KERNEL); | |
328 | if (!table->entries) | |
329 | return -ENOMEM; | |
330 | ||
331 | table->entry_count = 1; | |
332 | l2_lookup = table->entries; | |
333 | ||
334 | /* All L2 multicast addresses have an odd first octet */ | |
335 | l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST; | |
336 | l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST; | |
337 | l2_lookup[0].lockeds = true; | |
338 | l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1; | |
339 | ||
340 | /* Flood multicast to every port by default */ | |
341 | for (port = 0; port < priv->ds->num_ports; port++) | |
342 | if (!dsa_is_unused_port(priv->ds, port)) | |
343 | l2_lookup[0].destports |= BIT(port); | |
344 | ||
8aa9ebcc VO |
345 | return 0; |
346 | } | |
347 | ||
348 | static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) | |
349 | { | |
8aa9ebcc | 350 | struct sja1105_l2_lookup_params_entry default_l2_lookup_params = { |
8456721d VO |
351 | /* Learned FDB entries are forgotten after 300 seconds */ |
352 | .maxage = SJA1105_AGEING_TIME_MS(300000), | |
8aa9ebcc VO |
353 | /* All entries within a FDB bin are available for learning */ |
354 | .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE, | |
1da73821 VO |
355 | /* And the P/Q/R/S equivalent setting: */ |
356 | .start_dynspc = 0, | |
8aa9ebcc VO |
357 | /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */ |
358 | .poly = 0x97, | |
359 | /* This selects between Independent VLAN Learning (IVL) and | |
360 | * Shared VLAN Learning (SVL) | |
361 | */ | |
6d7c7d94 | 362 | .shared_learn = true, |
8aa9ebcc VO |
363 | /* Don't discard management traffic based on ENFPORT - |
364 | * we don't perform SMAC port enforcement anyway, so | |
365 | * what we are setting here doesn't matter. | |
366 | */ | |
367 | .no_enf_hostprt = false, | |
368 | /* Don't learn SMAC for mac_fltres1 and mac_fltres0. | |
369 | * Maybe correlate with no_linklocal_learn from bridge driver? | |
370 | */ | |
371 | .no_mgmt_learn = true, | |
1da73821 VO |
372 | /* P/Q/R/S only */ |
373 | .use_static = true, | |
374 | /* Dynamically learned FDB entries can overwrite other (older) | |
375 | * dynamic FDB entries | |
376 | */ | |
377 | .owr_dyn = true, | |
378 | .drpnolearn = true, | |
8aa9ebcc | 379 | }; |
542043e9 | 380 | struct dsa_switch *ds = priv->ds; |
f238fef1 | 381 | int port, num_used_ports = 0; |
542043e9 VO |
382 | struct sja1105_table *table; |
383 | u64 max_fdb_entries; | |
542043e9 VO |
384 | |
385 | for (port = 0; port < ds->num_ports; port++) | |
f238fef1 VO |
386 | if (!dsa_is_unused_port(ds, port)) |
387 | num_used_ports++; | |
388 | ||
389 | max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports; | |
390 | ||
391 | for (port = 0; port < ds->num_ports; port++) { | |
392 | if (dsa_is_unused_port(ds, port)) | |
393 | continue; | |
394 | ||
542043e9 | 395 | default_l2_lookup_params.maxaddrp[port] = max_fdb_entries; |
f238fef1 | 396 | } |
8aa9ebcc VO |
397 | |
398 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; | |
399 | ||
400 | if (table->entry_count) { | |
401 | kfree(table->entries); | |
402 | table->entry_count = 0; | |
403 | } | |
404 | ||
fd6f2c25 | 405 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
406 | table->ops->unpacked_entry_size, GFP_KERNEL); |
407 | if (!table->entries) | |
408 | return -ENOMEM; | |
409 | ||
fd6f2c25 | 410 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
411 | |
412 | /* This table only has a single entry */ | |
413 | ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] = | |
414 | default_l2_lookup_params; | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
ed040abc VO |
419 | /* Set up a default VLAN for untagged traffic injected from the CPU |
420 | * using management routes (e.g. STP, PTP) as opposed to tag_8021q. | |
421 | * All DT-defined ports are members of this VLAN, and there are no | |
422 | * restrictions on forwarding (since the CPU selects the destination). | |
423 | * Frames from this VLAN will always be transmitted as untagged, and | |
424 | * neither the bridge nor the 8021q module cannot create this VLAN ID. | |
425 | */ | |
8aa9ebcc VO |
426 | static int sja1105_init_static_vlan(struct sja1105_private *priv) |
427 | { | |
428 | struct sja1105_table *table; | |
429 | struct sja1105_vlan_lookup_entry pvid = { | |
3e77e59b | 430 | .type_entry = SJA1110_VLAN_D_TAG, |
8aa9ebcc VO |
431 | .ving_mirr = 0, |
432 | .vegr_mirr = 0, | |
433 | .vmemb_port = 0, | |
434 | .vlan_bc = 0, | |
435 | .tag_port = 0, | |
ed040abc | 436 | .vlanid = SJA1105_DEFAULT_VLAN, |
8aa9ebcc | 437 | }; |
ec5ae610 VO |
438 | struct dsa_switch *ds = priv->ds; |
439 | int port; | |
8aa9ebcc VO |
440 | |
441 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; | |
442 | ||
8aa9ebcc VO |
443 | if (table->entry_count) { |
444 | kfree(table->entries); | |
445 | table->entry_count = 0; | |
446 | } | |
447 | ||
c75857b0 | 448 | table->entries = kzalloc(table->ops->unpacked_entry_size, |
8aa9ebcc VO |
449 | GFP_KERNEL); |
450 | if (!table->entries) | |
451 | return -ENOMEM; | |
452 | ||
453 | table->entry_count = 1; | |
454 | ||
ec5ae610 | 455 | for (port = 0; port < ds->num_ports; port++) { |
ec5ae610 VO |
456 | if (dsa_is_unused_port(ds, port)) |
457 | continue; | |
458 | ||
459 | pvid.vmemb_port |= BIT(port); | |
460 | pvid.vlan_bc |= BIT(port); | |
461 | pvid.tag_port &= ~BIT(port); | |
462 | ||
c5130029 | 463 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { |
6dfd23d3 VO |
464 | priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN; |
465 | priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN; | |
466 | } | |
8aa9ebcc VO |
467 | } |
468 | ||
469 | ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid; | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int sja1105_init_l2_forwarding(struct sja1105_private *priv) | |
474 | { | |
475 | struct sja1105_l2_forwarding_entry *l2fwd; | |
542043e9 | 476 | struct dsa_switch *ds = priv->ds; |
0f9b762c | 477 | struct dsa_switch_tree *dst; |
8aa9ebcc | 478 | struct sja1105_table *table; |
0f9b762c | 479 | struct dsa_link *dl; |
3fa21270 VO |
480 | int port, tc; |
481 | int from, to; | |
8aa9ebcc VO |
482 | |
483 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING]; | |
484 | ||
485 | if (table->entry_count) { | |
486 | kfree(table->entries); | |
487 | table->entry_count = 0; | |
488 | } | |
489 | ||
fd6f2c25 | 490 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
491 | table->ops->unpacked_entry_size, GFP_KERNEL); |
492 | if (!table->entries) | |
493 | return -ENOMEM; | |
494 | ||
fd6f2c25 | 495 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
496 | |
497 | l2fwd = table->entries; | |
498 | ||
3fa21270 VO |
499 | /* First 5 entries in the L2 Forwarding Table define the forwarding |
500 | * rules and the VLAN PCP to ingress queue mapping. | |
501 | * Set up the ingress queue mapping first. | |
502 | */ | |
503 | for (port = 0; port < ds->num_ports; port++) { | |
504 | if (dsa_is_unused_port(ds, port)) | |
505 | continue; | |
506 | ||
507 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) | |
508 | l2fwd[port].vlan_pmap[tc] = tc; | |
509 | } | |
8aa9ebcc | 510 | |
3fa21270 VO |
511 | /* Then manage the forwarding domain for user ports. These can forward |
512 | * only to the always-on domain (CPU port and DSA links) | |
513 | */ | |
514 | for (from = 0; from < ds->num_ports; from++) { | |
515 | if (!dsa_is_user_port(ds, from)) | |
f238fef1 VO |
516 | continue; |
517 | ||
3fa21270 VO |
518 | for (to = 0; to < ds->num_ports; to++) { |
519 | if (!dsa_is_cpu_port(ds, to) && | |
520 | !dsa_is_dsa_port(ds, to)) | |
521 | continue; | |
8aa9ebcc | 522 | |
3fa21270 VO |
523 | l2fwd[from].bc_domain |= BIT(to); |
524 | l2fwd[from].fl_domain |= BIT(to); | |
7f7ccdea | 525 | |
3fa21270 VO |
526 | sja1105_port_allow_traffic(l2fwd, from, to, true); |
527 | } | |
528 | } | |
529 | ||
530 | /* Then manage the forwarding domain for DSA links and CPU ports (the | |
531 | * always-on domain). These can send packets to any enabled port except | |
532 | * themselves. | |
533 | */ | |
534 | for (from = 0; from < ds->num_ports; from++) { | |
535 | if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from)) | |
8aa9ebcc VO |
536 | continue; |
537 | ||
3fa21270 VO |
538 | for (to = 0; to < ds->num_ports; to++) { |
539 | if (dsa_is_unused_port(ds, to)) | |
540 | continue; | |
4d942354 | 541 | |
3fa21270 VO |
542 | if (from == to) |
543 | continue; | |
544 | ||
545 | l2fwd[from].bc_domain |= BIT(to); | |
546 | l2fwd[from].fl_domain |= BIT(to); | |
547 | ||
548 | sja1105_port_allow_traffic(l2fwd, from, to, true); | |
549 | } | |
550 | } | |
551 | ||
0f9b762c VO |
552 | /* In odd topologies ("H" connections where there is a DSA link to |
553 | * another switch which also has its own CPU port), TX packets can loop | |
554 | * back into the system (they are flooded from CPU port 1 to the DSA | |
555 | * link, and from there to CPU port 2). Prevent this from happening by | |
556 | * cutting RX from DSA links towards our CPU port, if the remote switch | |
557 | * has its own CPU port and therefore doesn't need ours for network | |
558 | * stack termination. | |
559 | */ | |
560 | dst = ds->dst; | |
561 | ||
562 | list_for_each_entry(dl, &dst->rtable, list) { | |
563 | if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp) | |
564 | continue; | |
565 | ||
566 | from = dl->dp->index; | |
567 | to = dsa_upstream_port(ds, from); | |
568 | ||
569 | dev_warn(ds->dev, | |
570 | "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n", | |
571 | from, to); | |
572 | ||
573 | sja1105_port_allow_traffic(l2fwd, from, to, false); | |
574 | ||
575 | l2fwd[from].bc_domain &= ~BIT(to); | |
576 | l2fwd[from].fl_domain &= ~BIT(to); | |
577 | } | |
578 | ||
3fa21270 VO |
579 | /* Finally, manage the egress flooding domain. All ports start up with |
580 | * flooding enabled, including the CPU port and DSA links. | |
581 | */ | |
582 | for (port = 0; port < ds->num_ports; port++) { | |
583 | if (dsa_is_unused_port(ds, port)) | |
584 | continue; | |
4d942354 | 585 | |
3fa21270 VO |
586 | priv->ucast_egress_floods |= BIT(port); |
587 | priv->bcast_egress_floods |= BIT(port); | |
8aa9ebcc | 588 | } |
f238fef1 | 589 | |
8aa9ebcc VO |
590 | /* Next 8 entries define VLAN PCP mapping from ingress to egress. |
591 | * Create a one-to-one mapping. | |
592 | */ | |
3fa21270 VO |
593 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) { |
594 | for (port = 0; port < ds->num_ports; port++) { | |
595 | if (dsa_is_unused_port(ds, port)) | |
f238fef1 VO |
596 | continue; |
597 | ||
3fa21270 | 598 | l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc; |
f238fef1 | 599 | } |
3e77e59b | 600 | |
3fa21270 | 601 | l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true; |
3e77e59b VO |
602 | } |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static int sja1110_init_pcp_remapping(struct sja1105_private *priv) | |
608 | { | |
609 | struct sja1110_pcp_remapping_entry *pcp_remap; | |
610 | struct dsa_switch *ds = priv->ds; | |
611 | struct sja1105_table *table; | |
612 | int port, tc; | |
613 | ||
614 | table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING]; | |
615 | ||
616 | /* Nothing to do for SJA1105 */ | |
617 | if (!table->ops->max_entry_count) | |
618 | return 0; | |
619 | ||
620 | if (table->entry_count) { | |
621 | kfree(table->entries); | |
622 | table->entry_count = 0; | |
623 | } | |
624 | ||
625 | table->entries = kcalloc(table->ops->max_entry_count, | |
626 | table->ops->unpacked_entry_size, GFP_KERNEL); | |
627 | if (!table->entries) | |
628 | return -ENOMEM; | |
629 | ||
630 | table->entry_count = table->ops->max_entry_count; | |
631 | ||
632 | pcp_remap = table->entries; | |
633 | ||
634 | /* Repeat the configuration done for vlan_pmap */ | |
635 | for (port = 0; port < ds->num_ports; port++) { | |
636 | if (dsa_is_unused_port(ds, port)) | |
637 | continue; | |
638 | ||
639 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) | |
640 | pcp_remap[port].egrpcp[tc] = tc; | |
f238fef1 | 641 | } |
8aa9ebcc VO |
642 | |
643 | return 0; | |
644 | } | |
645 | ||
646 | static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv) | |
647 | { | |
1bf658ee | 648 | struct sja1105_l2_forwarding_params_entry *l2fwd_params; |
8aa9ebcc VO |
649 | struct sja1105_table *table; |
650 | ||
651 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; | |
652 | ||
653 | if (table->entry_count) { | |
654 | kfree(table->entries); | |
655 | table->entry_count = 0; | |
656 | } | |
657 | ||
fd6f2c25 | 658 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
659 | table->ops->unpacked_entry_size, GFP_KERNEL); |
660 | if (!table->entries) | |
661 | return -ENOMEM; | |
662 | ||
fd6f2c25 | 663 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
664 | |
665 | /* This table only has a single entry */ | |
1bf658ee VO |
666 | l2fwd_params = table->entries; |
667 | ||
668 | /* Disallow dynamic reconfiguration of vlan_pmap */ | |
669 | l2fwd_params->max_dynp = 0; | |
670 | /* Use a single memory partition for all ingress queues */ | |
671 | l2fwd_params->part_spc[0] = priv->info->max_frame_mem; | |
8aa9ebcc VO |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
aaa270c6 VO |
676 | void sja1105_frame_memory_partitioning(struct sja1105_private *priv) |
677 | { | |
678 | struct sja1105_l2_forwarding_params_entry *l2_fwd_params; | |
679 | struct sja1105_vl_forwarding_params_entry *vl_fwd_params; | |
680 | struct sja1105_table *table; | |
aaa270c6 | 681 | |
aaa270c6 VO |
682 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; |
683 | l2_fwd_params = table->entries; | |
0fac6aa0 | 684 | l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY; |
aaa270c6 VO |
685 | |
686 | /* If we have any critical-traffic virtual links, we need to reserve | |
687 | * some frame buffer memory for them. At the moment, hardcode the value | |
688 | * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks | |
689 | * remaining for best-effort traffic. TODO: figure out a more flexible | |
690 | * way to perform the frame buffer partitioning. | |
691 | */ | |
692 | if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count) | |
693 | return; | |
694 | ||
695 | table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS]; | |
696 | vl_fwd_params = table->entries; | |
697 | ||
698 | l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY; | |
699 | vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY; | |
700 | } | |
701 | ||
ceec8bc0 VO |
702 | /* SJA1110 TDMACONFIGIDX values: |
703 | * | |
704 | * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports | |
705 | * -----+----------------+---------------+---------------+--------------- | |
706 | * 0 | 0, [5:10] | [1:2] | [3:4] | retag | |
707 | * 1 |0, [5:10], retag| [1:2] | [3:4] | - | |
708 | * 2 | 0, [5:10] | [1:3], retag | 4 | - | |
709 | * 3 | 0, [5:10] |[1:2], 4, retag| 3 | - | |
710 | * 4 | 0, 2, [5:10] | 1, retag | [3:4] | - | |
711 | * 5 | 0, 1, [5:10] | 2, retag | [3:4] | - | |
712 | * 14 | 0, [5:10] | [1:4], retag | - | - | |
713 | * 15 | [5:10] | [0:4], retag | - | - | |
714 | */ | |
715 | static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv) | |
716 | { | |
717 | struct sja1105_general_params_entry *general_params; | |
718 | struct sja1105_table *table; | |
719 | bool port_1_is_base_tx; | |
720 | bool port_3_is_2500; | |
721 | bool port_4_is_2500; | |
722 | u64 tdmaconfigidx; | |
723 | ||
724 | if (priv->info->device_id != SJA1110_DEVICE_ID) | |
725 | return; | |
726 | ||
727 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
728 | general_params = table->entries; | |
729 | ||
730 | /* All the settings below are "as opposed to SGMII", which is the | |
731 | * other pinmuxing option. | |
732 | */ | |
733 | port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL; | |
734 | port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX; | |
735 | port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX; | |
736 | ||
737 | if (port_1_is_base_tx) | |
738 | /* Retagging port will operate at 1 Gbps */ | |
739 | tdmaconfigidx = 5; | |
740 | else if (port_3_is_2500 && port_4_is_2500) | |
741 | /* Retagging port will operate at 100 Mbps */ | |
742 | tdmaconfigidx = 1; | |
743 | else if (port_3_is_2500) | |
744 | /* Retagging port will operate at 1 Gbps */ | |
745 | tdmaconfigidx = 3; | |
746 | else if (port_4_is_2500) | |
747 | /* Retagging port will operate at 1 Gbps */ | |
748 | tdmaconfigidx = 2; | |
749 | else | |
750 | /* Retagging port will operate at 1 Gbps */ | |
751 | tdmaconfigidx = 14; | |
752 | ||
753 | general_params->tdmaconfigidx = tdmaconfigidx; | |
754 | } | |
755 | ||
30a100e6 VO |
756 | static int sja1105_init_topology(struct sja1105_private *priv, |
757 | struct sja1105_general_params_entry *general_params) | |
758 | { | |
759 | struct dsa_switch *ds = priv->ds; | |
760 | int port; | |
761 | ||
762 | /* The host port is the destination for traffic matching mac_fltres1 | |
763 | * and mac_fltres0 on all ports except itself. Default to an invalid | |
764 | * value. | |
765 | */ | |
766 | general_params->host_port = ds->num_ports; | |
767 | ||
768 | /* Link-local traffic received on casc_port will be forwarded | |
769 | * to host_port without embedding the source port and device ID | |
770 | * info in the destination MAC address, and no RX timestamps will be | |
771 | * taken either (presumably because it is a cascaded port and a | |
772 | * downstream SJA switch already did that). | |
773 | * To disable the feature, we need to do different things depending on | |
774 | * switch generation. On SJA1105 we need to set an invalid port, while | |
775 | * on SJA1110 which support multiple cascaded ports, this field is a | |
776 | * bitmask so it must be left zero. | |
777 | */ | |
778 | if (!priv->info->multiple_cascade_ports) | |
779 | general_params->casc_port = ds->num_ports; | |
780 | ||
781 | for (port = 0; port < ds->num_ports; port++) { | |
782 | bool is_upstream = dsa_is_upstream_port(ds, port); | |
783 | bool is_dsa_link = dsa_is_dsa_port(ds, port); | |
784 | ||
785 | /* Upstream ports can be dedicated CPU ports or | |
786 | * upstream-facing DSA links | |
787 | */ | |
788 | if (is_upstream) { | |
789 | if (general_params->host_port == ds->num_ports) { | |
790 | general_params->host_port = port; | |
791 | } else { | |
792 | dev_err(ds->dev, | |
793 | "Port %llu is already a host port, configuring %d as one too is not supported\n", | |
794 | general_params->host_port, port); | |
795 | return -EINVAL; | |
796 | } | |
797 | } | |
798 | ||
799 | /* Cascade ports are downstream-facing DSA links */ | |
800 | if (is_dsa_link && !is_upstream) { | |
801 | if (priv->info->multiple_cascade_ports) { | |
802 | general_params->casc_port |= BIT(port); | |
803 | } else if (general_params->casc_port == ds->num_ports) { | |
804 | general_params->casc_port = port; | |
805 | } else { | |
806 | dev_err(ds->dev, | |
807 | "Port %llu is already a cascade port, configuring %d as one too is not supported\n", | |
808 | general_params->casc_port, port); | |
809 | return -EINVAL; | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
814 | if (general_params->host_port == ds->num_ports) { | |
815 | dev_err(ds->dev, "No host port configured\n"); | |
816 | return -EINVAL; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
8aa9ebcc VO |
822 | static int sja1105_init_general_params(struct sja1105_private *priv) |
823 | { | |
824 | struct sja1105_general_params_entry default_general_params = { | |
511e6ca0 VO |
825 | /* Allow dynamic changing of the mirror port */ |
826 | .mirr_ptacu = true, | |
8aa9ebcc | 827 | .switchid = priv->ds->index, |
5f06c63b VO |
828 | /* Priority queue for link-local management frames |
829 | * (both ingress to and egress from CPU - PTP, STP etc) | |
830 | */ | |
08fde09a | 831 | .hostprio = 7, |
8aa9ebcc VO |
832 | .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A, |
833 | .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK, | |
42824463 | 834 | .incl_srcpt1 = false, |
8aa9ebcc VO |
835 | .send_meta1 = false, |
836 | .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B, | |
837 | .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK, | |
42824463 | 838 | .incl_srcpt0 = false, |
8aa9ebcc | 839 | .send_meta0 = false, |
511e6ca0 | 840 | /* Default to an invalid value */ |
542043e9 | 841 | .mirr_port = priv->ds->num_ports, |
8aa9ebcc | 842 | /* No TTEthernet */ |
dfacc5a2 | 843 | .vllupformat = SJA1105_VL_FORMAT_PSFP, |
8aa9ebcc VO |
844 | .vlmarker = 0, |
845 | .vlmask = 0, | |
846 | /* Only update correctionField for 1-step PTP (L2 transport) */ | |
847 | .ignore2stf = 0, | |
6666cebc VO |
848 | /* Forcefully disable VLAN filtering by telling |
849 | * the switch that VLAN has a different EtherType. | |
850 | */ | |
851 | .tpid = ETH_P_SJA1105, | |
852 | .tpid2 = ETH_P_SJA1105, | |
29305260 VO |
853 | /* Enable the TTEthernet engine on SJA1110 */ |
854 | .tte_en = true, | |
4913b8eb VO |
855 | /* Set up the EtherType for control packets on SJA1110 */ |
856 | .header_type = ETH_P_SJA1110, | |
8aa9ebcc | 857 | }; |
6c0de59b | 858 | struct sja1105_general_params_entry *general_params; |
8aa9ebcc | 859 | struct sja1105_table *table; |
30a100e6 | 860 | int rc; |
df2a81a3 | 861 | |
30a100e6 VO |
862 | rc = sja1105_init_topology(priv, &default_general_params); |
863 | if (rc) | |
864 | return rc; | |
8aa9ebcc VO |
865 | |
866 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
867 | ||
868 | if (table->entry_count) { | |
869 | kfree(table->entries); | |
870 | table->entry_count = 0; | |
871 | } | |
872 | ||
fd6f2c25 | 873 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
874 | table->ops->unpacked_entry_size, GFP_KERNEL); |
875 | if (!table->entries) | |
876 | return -ENOMEM; | |
877 | ||
fd6f2c25 | 878 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc | 879 | |
6c0de59b VO |
880 | general_params = table->entries; |
881 | ||
8aa9ebcc | 882 | /* This table only has a single entry */ |
6c0de59b | 883 | general_params[0] = default_general_params; |
8aa9ebcc | 884 | |
ceec8bc0 VO |
885 | sja1110_select_tdmaconfigidx(priv); |
886 | ||
8aa9ebcc VO |
887 | return 0; |
888 | } | |
889 | ||
79d5511c VO |
890 | static int sja1105_init_avb_params(struct sja1105_private *priv) |
891 | { | |
892 | struct sja1105_avb_params_entry *avb; | |
893 | struct sja1105_table *table; | |
894 | ||
895 | table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS]; | |
896 | ||
897 | /* Discard previous AVB Parameters Table */ | |
898 | if (table->entry_count) { | |
899 | kfree(table->entries); | |
900 | table->entry_count = 0; | |
901 | } | |
902 | ||
fd6f2c25 | 903 | table->entries = kcalloc(table->ops->max_entry_count, |
79d5511c VO |
904 | table->ops->unpacked_entry_size, GFP_KERNEL); |
905 | if (!table->entries) | |
906 | return -ENOMEM; | |
907 | ||
fd6f2c25 | 908 | table->entry_count = table->ops->max_entry_count; |
79d5511c VO |
909 | |
910 | avb = table->entries; | |
911 | ||
912 | /* Configure the MAC addresses for meta frames */ | |
913 | avb->destmeta = SJA1105_META_DMAC; | |
914 | avb->srcmeta = SJA1105_META_SMAC; | |
747e5eb3 VO |
915 | /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by |
916 | * default. This is because there might be boards with a hardware | |
917 | * layout where enabling the pin as output might cause an electrical | |
918 | * clash. On E/T the pin is always an output, which the board designers | |
919 | * probably already knew, so even if there are going to be electrical | |
920 | * issues, there's nothing we can do. | |
921 | */ | |
922 | avb->cas_master = false; | |
79d5511c VO |
923 | |
924 | return 0; | |
925 | } | |
926 | ||
a7cc081c VO |
927 | /* The L2 policing table is 2-stage. The table is looked up for each frame |
928 | * according to the ingress port, whether it was broadcast or not, and the | |
929 | * classified traffic class (given by VLAN PCP). This portion of the lookup is | |
930 | * fixed, and gives access to the SHARINDX, an indirection register pointing | |
931 | * within the policing table itself, which is used to resolve the policer that | |
932 | * will be used for this frame. | |
933 | * | |
934 | * Stage 1 Stage 2 | |
935 | * +------------+--------+ +---------------------------------+ | |
936 | * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU | | |
937 | * +------------+--------+ +---------------------------------+ | |
938 | * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU | | |
939 | * +------------+--------+ +---------------------------------+ | |
940 | * ... | Policer 2: Rate, Burst, MTU | | |
941 | * +------------+--------+ +---------------------------------+ | |
942 | * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU | | |
943 | * +------------+--------+ +---------------------------------+ | |
944 | * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU | | |
945 | * +------------+--------+ +---------------------------------+ | |
946 | * ... | Policer 5: Rate, Burst, MTU | | |
947 | * +------------+--------+ +---------------------------------+ | |
948 | * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU | | |
949 | * +------------+--------+ +---------------------------------+ | |
950 | * ... | Policer 7: Rate, Burst, MTU | | |
951 | * +------------+--------+ +---------------------------------+ | |
952 | * |Port 4 TC 7 |SHARINDX| ... | |
953 | * +------------+--------+ | |
954 | * |Port 0 BCAST|SHARINDX| ... | |
955 | * +------------+--------+ | |
956 | * |Port 1 BCAST|SHARINDX| ... | |
957 | * +------------+--------+ | |
958 | * ... ... | |
959 | * +------------+--------+ +---------------------------------+ | |
960 | * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU | | |
961 | * +------------+--------+ +---------------------------------+ | |
962 | * | |
963 | * In this driver, we shall use policers 0-4 as statically alocated port | |
964 | * (matchall) policers. So we need to make the SHARINDX for all lookups | |
965 | * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast | |
966 | * lookup) equal. | |
967 | * The remaining policers (40) shall be dynamically allocated for flower | |
968 | * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff. | |
969 | */ | |
8aa9ebcc VO |
970 | #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000) |
971 | ||
8aa9ebcc VO |
972 | static int sja1105_init_l2_policing(struct sja1105_private *priv) |
973 | { | |
974 | struct sja1105_l2_policing_entry *policing; | |
542043e9 | 975 | struct dsa_switch *ds = priv->ds; |
8aa9ebcc | 976 | struct sja1105_table *table; |
a7cc081c | 977 | int port, tc; |
8aa9ebcc VO |
978 | |
979 | table = &priv->static_config.tables[BLK_IDX_L2_POLICING]; | |
980 | ||
981 | /* Discard previous L2 Policing Table */ | |
982 | if (table->entry_count) { | |
983 | kfree(table->entries); | |
984 | table->entry_count = 0; | |
985 | } | |
986 | ||
fd6f2c25 | 987 | table->entries = kcalloc(table->ops->max_entry_count, |
8aa9ebcc VO |
988 | table->ops->unpacked_entry_size, GFP_KERNEL); |
989 | if (!table->entries) | |
990 | return -ENOMEM; | |
991 | ||
fd6f2c25 | 992 | table->entry_count = table->ops->max_entry_count; |
8aa9ebcc VO |
993 | |
994 | policing = table->entries; | |
995 | ||
a7cc081c | 996 | /* Setup shared indices for the matchall policers */ |
542043e9 | 997 | for (port = 0; port < ds->num_ports; port++) { |
38fbe91f | 998 | int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port; |
542043e9 | 999 | int bcast = (ds->num_ports * SJA1105_NUM_TC) + port; |
a7cc081c VO |
1000 | |
1001 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) | |
1002 | policing[port * SJA1105_NUM_TC + tc].sharindx = port; | |
1003 | ||
1004 | policing[bcast].sharindx = port; | |
38fbe91f VO |
1005 | /* Only SJA1110 has multicast policers */ |
1006 | if (mcast <= table->ops->max_entry_count) | |
1007 | policing[mcast].sharindx = port; | |
a7cc081c VO |
1008 | } |
1009 | ||
1010 | /* Setup the matchall policer parameters */ | |
542043e9 | 1011 | for (port = 0; port < ds->num_ports; port++) { |
c279c726 VO |
1012 | int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; |
1013 | ||
777e55e3 | 1014 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) |
c279c726 | 1015 | mtu += VLAN_HLEN; |
8aa9ebcc | 1016 | |
a7cc081c VO |
1017 | policing[port].smax = 65535; /* Burst size in bytes */ |
1018 | policing[port].rate = SJA1105_RATE_MBPS(1000); | |
1019 | policing[port].maxlen = mtu; | |
1020 | policing[port].partition = 0; | |
8aa9ebcc | 1021 | } |
a7cc081c | 1022 | |
8aa9ebcc VO |
1023 | return 0; |
1024 | } | |
1025 | ||
5d645df9 | 1026 | static int sja1105_static_config_load(struct sja1105_private *priv) |
8aa9ebcc VO |
1027 | { |
1028 | int rc; | |
1029 | ||
1030 | sja1105_static_config_free(&priv->static_config); | |
1031 | rc = sja1105_static_config_init(&priv->static_config, | |
1032 | priv->info->static_ops, | |
1033 | priv->info->device_id); | |
1034 | if (rc) | |
1035 | return rc; | |
1036 | ||
1037 | /* Build static configuration */ | |
1038 | rc = sja1105_init_mac_settings(priv); | |
1039 | if (rc < 0) | |
1040 | return rc; | |
5d645df9 | 1041 | rc = sja1105_init_mii_settings(priv); |
8aa9ebcc VO |
1042 | if (rc < 0) |
1043 | return rc; | |
1044 | rc = sja1105_init_static_fdb(priv); | |
1045 | if (rc < 0) | |
1046 | return rc; | |
1047 | rc = sja1105_init_static_vlan(priv); | |
1048 | if (rc < 0) | |
1049 | return rc; | |
1050 | rc = sja1105_init_l2_lookup_params(priv); | |
1051 | if (rc < 0) | |
1052 | return rc; | |
1053 | rc = sja1105_init_l2_forwarding(priv); | |
1054 | if (rc < 0) | |
1055 | return rc; | |
1056 | rc = sja1105_init_l2_forwarding_params(priv); | |
1057 | if (rc < 0) | |
1058 | return rc; | |
1059 | rc = sja1105_init_l2_policing(priv); | |
1060 | if (rc < 0) | |
1061 | return rc; | |
1062 | rc = sja1105_init_general_params(priv); | |
79d5511c VO |
1063 | if (rc < 0) |
1064 | return rc; | |
1065 | rc = sja1105_init_avb_params(priv); | |
3e77e59b VO |
1066 | if (rc < 0) |
1067 | return rc; | |
1068 | rc = sja1110_init_pcp_remapping(priv); | |
8aa9ebcc VO |
1069 | if (rc < 0) |
1070 | return rc; | |
1071 | ||
1072 | /* Send initial configuration to hardware via SPI */ | |
1073 | return sja1105_static_config_upload(priv); | |
1074 | } | |
1075 | ||
29afb83a | 1076 | static int sja1105_parse_rgmii_delays(struct sja1105_private *priv) |
f5b8631c | 1077 | { |
542043e9 | 1078 | struct dsa_switch *ds = priv->ds; |
29afb83a | 1079 | int port; |
f5b8631c | 1080 | |
29afb83a VO |
1081 | for (port = 0; port < ds->num_ports; port++) { |
1082 | if (!priv->fixed_link[port]) | |
f5b8631c VO |
1083 | continue; |
1084 | ||
29afb83a VO |
1085 | if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_RXID || |
1086 | priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID) | |
1087 | priv->rgmii_rx_delay[port] = true; | |
f5b8631c | 1088 | |
29afb83a VO |
1089 | if (priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_TXID || |
1090 | priv->phy_mode[port] == PHY_INTERFACE_MODE_RGMII_ID) | |
1091 | priv->rgmii_tx_delay[port] = true; | |
f5b8631c | 1092 | |
29afb83a VO |
1093 | if ((priv->rgmii_rx_delay[port] || priv->rgmii_tx_delay[port]) && |
1094 | !priv->info->setup_rgmii_delay) | |
f5b8631c VO |
1095 | return -EINVAL; |
1096 | } | |
1097 | return 0; | |
1098 | } | |
1099 | ||
8aa9ebcc | 1100 | static int sja1105_parse_ports_node(struct sja1105_private *priv, |
8aa9ebcc VO |
1101 | struct device_node *ports_node) |
1102 | { | |
1103 | struct device *dev = &priv->spidev->dev; | |
1104 | struct device_node *child; | |
1105 | ||
27afe0d3 | 1106 | for_each_available_child_of_node(ports_node, child) { |
8aa9ebcc | 1107 | struct device_node *phy_node; |
0c65b2b9 | 1108 | phy_interface_t phy_mode; |
8aa9ebcc | 1109 | u32 index; |
0c65b2b9 | 1110 | int err; |
8aa9ebcc VO |
1111 | |
1112 | /* Get switch port number from DT */ | |
1113 | if (of_property_read_u32(child, "reg", &index) < 0) { | |
1114 | dev_err(dev, "Port number not defined in device tree " | |
1115 | "(property \"reg\")\n"); | |
7ba771e3 | 1116 | of_node_put(child); |
8aa9ebcc VO |
1117 | return -ENODEV; |
1118 | } | |
1119 | ||
1120 | /* Get PHY mode from DT */ | |
0c65b2b9 AL |
1121 | err = of_get_phy_mode(child, &phy_mode); |
1122 | if (err) { | |
8aa9ebcc VO |
1123 | dev_err(dev, "Failed to read phy-mode or " |
1124 | "phy-interface-type property for port %d\n", | |
1125 | index); | |
7ba771e3 | 1126 | of_node_put(child); |
8aa9ebcc VO |
1127 | return -ENODEV; |
1128 | } | |
8aa9ebcc VO |
1129 | |
1130 | phy_node = of_parse_phandle(child, "phy-handle", 0); | |
1131 | if (!phy_node) { | |
1132 | if (!of_phy_is_fixed_link(child)) { | |
1133 | dev_err(dev, "phy-handle or fixed-link " | |
1134 | "properties missing!\n"); | |
7ba771e3 | 1135 | of_node_put(child); |
8aa9ebcc VO |
1136 | return -ENODEV; |
1137 | } | |
1138 | /* phy-handle is missing, but fixed-link isn't. | |
1139 | * So it's a fixed link. Default to PHY role. | |
1140 | */ | |
29afb83a | 1141 | priv->fixed_link[index] = true; |
8aa9ebcc | 1142 | } else { |
8aa9ebcc VO |
1143 | of_node_put(phy_node); |
1144 | } | |
1145 | ||
bf4edf4a | 1146 | priv->phy_mode[index] = phy_mode; |
8aa9ebcc VO |
1147 | } |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
5d645df9 | 1152 | static int sja1105_parse_dt(struct sja1105_private *priv) |
8aa9ebcc VO |
1153 | { |
1154 | struct device *dev = &priv->spidev->dev; | |
1155 | struct device_node *switch_node = dev->of_node; | |
1156 | struct device_node *ports_node; | |
1157 | int rc; | |
1158 | ||
1159 | ports_node = of_get_child_by_name(switch_node, "ports"); | |
15074a36 VO |
1160 | if (!ports_node) |
1161 | ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); | |
8aa9ebcc VO |
1162 | if (!ports_node) { |
1163 | dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); | |
1164 | return -ENODEV; | |
1165 | } | |
1166 | ||
5d645df9 | 1167 | rc = sja1105_parse_ports_node(priv, ports_node); |
8aa9ebcc VO |
1168 | of_node_put(ports_node); |
1169 | ||
1170 | return rc; | |
1171 | } | |
1172 | ||
c44d0535 | 1173 | /* Convert link speed from SJA1105 to ethtool encoding */ |
41fed17f VO |
1174 | static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv, |
1175 | u64 speed) | |
1176 | { | |
1177 | if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) | |
1178 | return SPEED_10; | |
1179 | if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) | |
1180 | return SPEED_100; | |
1181 | if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) | |
1182 | return SPEED_1000; | |
1183 | if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS]) | |
1184 | return SPEED_2500; | |
1185 | return SPEED_UNKNOWN; | |
1186 | } | |
8aa9ebcc | 1187 | |
8400cff6 | 1188 | /* Set link speed in the MAC configuration for a specific port. */ |
8aa9ebcc | 1189 | static int sja1105_adjust_port_config(struct sja1105_private *priv, int port, |
8400cff6 | 1190 | int speed_mbps) |
8aa9ebcc | 1191 | { |
8aa9ebcc VO |
1192 | struct sja1105_mac_config_entry *mac; |
1193 | struct device *dev = priv->ds->dev; | |
41fed17f | 1194 | u64 speed; |
8aa9ebcc VO |
1195 | int rc; |
1196 | ||
8400cff6 VO |
1197 | /* On P/Q/R/S, one can read from the device via the MAC reconfiguration |
1198 | * tables. On E/T, MAC reconfig tables are not readable, only writable. | |
1199 | * We have to *know* what the MAC looks like. For the sake of keeping | |
1200 | * the code common, we'll use the static configuration tables as a | |
1201 | * reasonable approximation for both E/T and P/Q/R/S. | |
1202 | */ | |
8aa9ebcc VO |
1203 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
1204 | ||
f4cfcfbd | 1205 | switch (speed_mbps) { |
c44d0535 | 1206 | case SPEED_UNKNOWN: |
a979a0ab VO |
1207 | /* PHYLINK called sja1105_mac_config() to inform us about |
1208 | * the state->interface, but AN has not completed and the | |
1209 | * speed is not yet valid. UM10944.pdf says that setting | |
1210 | * SJA1105_SPEED_AUTO at runtime disables the port, so that is | |
1211 | * ok for power consumption in case AN will never complete - | |
1212 | * otherwise PHYLINK should come back with a new update. | |
1213 | */ | |
41fed17f | 1214 | speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; |
f4cfcfbd | 1215 | break; |
c44d0535 | 1216 | case SPEED_10: |
41fed17f | 1217 | speed = priv->info->port_speed[SJA1105_SPEED_10MBPS]; |
f4cfcfbd | 1218 | break; |
c44d0535 | 1219 | case SPEED_100: |
41fed17f | 1220 | speed = priv->info->port_speed[SJA1105_SPEED_100MBPS]; |
f4cfcfbd | 1221 | break; |
c44d0535 | 1222 | case SPEED_1000: |
41fed17f | 1223 | speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; |
f4cfcfbd | 1224 | break; |
56b63466 VO |
1225 | case SPEED_2500: |
1226 | speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; | |
1227 | break; | |
f4cfcfbd | 1228 | default: |
8aa9ebcc VO |
1229 | dev_err(dev, "Invalid speed %iMbps\n", speed_mbps); |
1230 | return -EINVAL; | |
1231 | } | |
1232 | ||
8400cff6 VO |
1233 | /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration |
1234 | * table, since this will be used for the clocking setup, and we no | |
1235 | * longer need to store it in the static config (already told hardware | |
1236 | * we want auto during upload phase). | |
ffe10e67 VO |
1237 | * Actually for the SGMII port, the MAC is fixed at 1 Gbps and |
1238 | * we need to configure the PCS only (if even that). | |
8aa9ebcc | 1239 | */ |
91a05078 | 1240 | if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII) |
41fed17f | 1241 | mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; |
56b63466 VO |
1242 | else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX) |
1243 | mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; | |
ffe10e67 VO |
1244 | else |
1245 | mac[port].speed = speed; | |
8aa9ebcc | 1246 | |
8aa9ebcc | 1247 | /* Write to the dynamic reconfiguration tables */ |
8400cff6 VO |
1248 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, |
1249 | &mac[port], true); | |
8aa9ebcc VO |
1250 | if (rc < 0) { |
1251 | dev_err(dev, "Failed to write MAC config: %d\n", rc); | |
1252 | return rc; | |
1253 | } | |
1254 | ||
1255 | /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at | |
1256 | * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and | |
1257 | * RMII no change of the clock setup is required. Actually, changing | |
1258 | * the clock setup does interrupt the clock signal for a certain time | |
1259 | * which causes trouble for all PHYs relying on this signal. | |
1260 | */ | |
91a05078 | 1261 | if (!phy_interface_mode_is_rgmii(priv->phy_mode[port])) |
8aa9ebcc VO |
1262 | return 0; |
1263 | ||
1264 | return sja1105_clocking_setup_port(priv, port); | |
1265 | } | |
1266 | ||
39710229 VO |
1267 | /* The SJA1105 MAC programming model is through the static config (the xMII |
1268 | * Mode table cannot be dynamically reconfigured), and we have to program | |
1269 | * that early (earlier than PHYLINK calls us, anyway). | |
1270 | * So just error out in case the connected PHY attempts to change the initial | |
1271 | * system interface MII protocol from what is defined in the DT, at least for | |
1272 | * now. | |
1273 | */ | |
1274 | static bool sja1105_phy_mode_mismatch(struct sja1105_private *priv, int port, | |
1275 | phy_interface_t interface) | |
1276 | { | |
bf4edf4a | 1277 | return priv->phy_mode[port] != interface; |
39710229 VO |
1278 | } |
1279 | ||
af7cd036 | 1280 | static void sja1105_mac_config(struct dsa_switch *ds, int port, |
ffe10e67 | 1281 | unsigned int mode, |
af7cd036 | 1282 | const struct phylink_link_state *state) |
8aa9ebcc | 1283 | { |
3ad1d171 | 1284 | struct dsa_port *dp = dsa_to_port(ds, port); |
8aa9ebcc | 1285 | struct sja1105_private *priv = ds->priv; |
3ad1d171 | 1286 | struct dw_xpcs *xpcs; |
8aa9ebcc | 1287 | |
ec8582d1 VO |
1288 | if (sja1105_phy_mode_mismatch(priv, port, state->interface)) { |
1289 | dev_err(ds->dev, "Changing PHY mode to %s not supported!\n", | |
1290 | phy_modes(state->interface)); | |
39710229 | 1291 | return; |
ec8582d1 | 1292 | } |
39710229 | 1293 | |
3ad1d171 | 1294 | xpcs = priv->xpcs[port]; |
ffe10e67 | 1295 | |
3ad1d171 VO |
1296 | if (xpcs) |
1297 | phylink_set_pcs(dp->pl, &xpcs->pcs); | |
8400cff6 VO |
1298 | } |
1299 | ||
1300 | static void sja1105_mac_link_down(struct dsa_switch *ds, int port, | |
1301 | unsigned int mode, | |
1302 | phy_interface_t interface) | |
1303 | { | |
1304 | sja1105_inhibit_tx(ds->priv, BIT(port), true); | |
1305 | } | |
1306 | ||
1307 | static void sja1105_mac_link_up(struct dsa_switch *ds, int port, | |
1308 | unsigned int mode, | |
1309 | phy_interface_t interface, | |
5b502a7b RK |
1310 | struct phy_device *phydev, |
1311 | int speed, int duplex, | |
1312 | bool tx_pause, bool rx_pause) | |
8400cff6 | 1313 | { |
ec8582d1 VO |
1314 | struct sja1105_private *priv = ds->priv; |
1315 | ||
1316 | sja1105_adjust_port_config(priv, port, speed); | |
1317 | ||
1318 | sja1105_inhibit_tx(priv, BIT(port), false); | |
8aa9ebcc VO |
1319 | } |
1320 | ||
ad9f299a VO |
1321 | static void sja1105_phylink_validate(struct dsa_switch *ds, int port, |
1322 | unsigned long *supported, | |
1323 | struct phylink_link_state *state) | |
1324 | { | |
1325 | /* Construct a new mask which exhaustively contains all link features | |
1326 | * supported by the MAC, and then apply that (logical AND) to what will | |
1327 | * be sent to the PHY for "marketing". | |
1328 | */ | |
1329 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; | |
1330 | struct sja1105_private *priv = ds->priv; | |
1331 | struct sja1105_xmii_params_entry *mii; | |
1332 | ||
1333 | mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; | |
1334 | ||
39710229 VO |
1335 | /* include/linux/phylink.h says: |
1336 | * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink | |
1337 | * expects the MAC driver to return all supported link modes. | |
1338 | */ | |
1339 | if (state->interface != PHY_INTERFACE_MODE_NA && | |
1340 | sja1105_phy_mode_mismatch(priv, port, state->interface)) { | |
1341 | bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
1342 | return; | |
1343 | } | |
1344 | ||
ad9f299a VO |
1345 | /* The MAC does not support pause frames, and also doesn't |
1346 | * support half-duplex traffic modes. | |
1347 | */ | |
1348 | phylink_set(mask, Autoneg); | |
1349 | phylink_set(mask, MII); | |
1350 | phylink_set(mask, 10baseT_Full); | |
1351 | phylink_set(mask, 100baseT_Full); | |
ca68e138 | 1352 | phylink_set(mask, 100baseT1_Full); |
ffe10e67 VO |
1353 | if (mii->xmii_mode[port] == XMII_MODE_RGMII || |
1354 | mii->xmii_mode[port] == XMII_MODE_SGMII) | |
ad9f299a | 1355 | phylink_set(mask, 1000baseT_Full); |
56b63466 VO |
1356 | if (priv->info->supports_2500basex[port]) { |
1357 | phylink_set(mask, 2500baseT_Full); | |
1358 | phylink_set(mask, 2500baseX_Full); | |
1359 | } | |
ad9f299a VO |
1360 | |
1361 | bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); | |
1362 | bitmap_and(state->advertising, state->advertising, mask, | |
1363 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
1364 | } | |
1365 | ||
60f6053f VO |
1366 | static int |
1367 | sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port, | |
1368 | const struct sja1105_l2_lookup_entry *requested) | |
1369 | { | |
1370 | struct sja1105_l2_lookup_entry *l2_lookup; | |
1371 | struct sja1105_table *table; | |
1372 | int i; | |
1373 | ||
1374 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; | |
1375 | l2_lookup = table->entries; | |
1376 | ||
1377 | for (i = 0; i < table->entry_count; i++) | |
1378 | if (l2_lookup[i].macaddr == requested->macaddr && | |
1379 | l2_lookup[i].vlanid == requested->vlanid && | |
1380 | l2_lookup[i].destports & BIT(port)) | |
1381 | return i; | |
1382 | ||
1383 | return -1; | |
1384 | } | |
1385 | ||
1386 | /* We want FDB entries added statically through the bridge command to persist | |
1387 | * across switch resets, which are a common thing during normal SJA1105 | |
1388 | * operation. So we have to back them up in the static configuration tables | |
1389 | * and hence apply them on next static config upload... yay! | |
1390 | */ | |
1391 | static int | |
1392 | sja1105_static_fdb_change(struct sja1105_private *priv, int port, | |
1393 | const struct sja1105_l2_lookup_entry *requested, | |
1394 | bool keep) | |
1395 | { | |
1396 | struct sja1105_l2_lookup_entry *l2_lookup; | |
1397 | struct sja1105_table *table; | |
1398 | int rc, match; | |
1399 | ||
1400 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; | |
1401 | ||
1402 | match = sja1105_find_static_fdb_entry(priv, port, requested); | |
1403 | if (match < 0) { | |
1404 | /* Can't delete a missing entry. */ | |
1405 | if (!keep) | |
1406 | return 0; | |
1407 | ||
1408 | /* No match => new entry */ | |
1409 | rc = sja1105_table_resize(table, table->entry_count + 1); | |
1410 | if (rc) | |
1411 | return rc; | |
1412 | ||
1413 | match = table->entry_count - 1; | |
1414 | } | |
1415 | ||
1416 | /* Assign pointer after the resize (it may be new memory) */ | |
1417 | l2_lookup = table->entries; | |
1418 | ||
1419 | /* We have a match. | |
1420 | * If the job was to add this FDB entry, it's already done (mostly | |
1421 | * anyway, since the port forwarding mask may have changed, case in | |
1422 | * which we update it). | |
1423 | * Otherwise we have to delete it. | |
1424 | */ | |
1425 | if (keep) { | |
1426 | l2_lookup[match] = *requested; | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | /* To remove, the strategy is to overwrite the element with | |
1431 | * the last one, and then reduce the array size by 1 | |
1432 | */ | |
1433 | l2_lookup[match] = l2_lookup[table->entry_count - 1]; | |
1434 | return sja1105_table_resize(table, table->entry_count - 1); | |
1435 | } | |
1436 | ||
291d1e72 VO |
1437 | /* First-generation switches have a 4-way set associative TCAM that |
1438 | * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of | |
1439 | * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin). | |
1440 | * For the placement of a newly learnt FDB entry, the switch selects the bin | |
1441 | * based on a hash function, and the way within that bin incrementally. | |
1442 | */ | |
09c1b412 | 1443 | static int sja1105et_fdb_index(int bin, int way) |
291d1e72 VO |
1444 | { |
1445 | return bin * SJA1105ET_FDB_BIN_SIZE + way; | |
1446 | } | |
1447 | ||
9dfa6911 VO |
1448 | static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin, |
1449 | const u8 *addr, u16 vid, | |
1450 | struct sja1105_l2_lookup_entry *match, | |
1451 | int *last_unused) | |
291d1e72 VO |
1452 | { |
1453 | int way; | |
1454 | ||
1455 | for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) { | |
1456 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
1457 | int index = sja1105et_fdb_index(bin, way); | |
1458 | ||
1459 | /* Skip unused entries, optionally marking them | |
1460 | * into the return value | |
1461 | */ | |
1462 | if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1463 | index, &l2_lookup)) { | |
1464 | if (last_unused) | |
1465 | *last_unused = way; | |
1466 | continue; | |
1467 | } | |
1468 | ||
1469 | if (l2_lookup.macaddr == ether_addr_to_u64(addr) && | |
1470 | l2_lookup.vlanid == vid) { | |
1471 | if (match) | |
1472 | *match = l2_lookup; | |
1473 | return way; | |
1474 | } | |
1475 | } | |
1476 | /* Return an invalid entry index if not found */ | |
1477 | return -1; | |
1478 | } | |
1479 | ||
9dfa6911 VO |
1480 | int sja1105et_fdb_add(struct dsa_switch *ds, int port, |
1481 | const unsigned char *addr, u16 vid) | |
291d1e72 VO |
1482 | { |
1483 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
1484 | struct sja1105_private *priv = ds->priv; | |
1485 | struct device *dev = ds->dev; | |
1486 | int last_unused = -1; | |
60f6053f | 1487 | int bin, way, rc; |
291d1e72 | 1488 | |
9dfa6911 | 1489 | bin = sja1105et_fdb_hash(priv, addr, vid); |
291d1e72 | 1490 | |
9dfa6911 VO |
1491 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, |
1492 | &l2_lookup, &last_unused); | |
291d1e72 VO |
1493 | if (way >= 0) { |
1494 | /* We have an FDB entry. Is our port in the destination | |
1495 | * mask? If yes, we need to do nothing. If not, we need | |
1496 | * to rewrite the entry by adding this port to it. | |
1497 | */ | |
1498 | if (l2_lookup.destports & BIT(port)) | |
1499 | return 0; | |
1500 | l2_lookup.destports |= BIT(port); | |
1501 | } else { | |
1502 | int index = sja1105et_fdb_index(bin, way); | |
1503 | ||
1504 | /* We don't have an FDB entry. We construct a new one and | |
1505 | * try to find a place for it within the FDB table. | |
1506 | */ | |
1507 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
1508 | l2_lookup.destports = BIT(port); | |
1509 | l2_lookup.vlanid = vid; | |
1510 | ||
1511 | if (last_unused >= 0) { | |
1512 | way = last_unused; | |
1513 | } else { | |
1514 | /* Bin is full, need to evict somebody. | |
1515 | * Choose victim at random. If you get these messages | |
1516 | * often, you may need to consider changing the | |
1517 | * distribution function: | |
1518 | * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly | |
1519 | */ | |
1520 | get_random_bytes(&way, sizeof(u8)); | |
1521 | way %= SJA1105ET_FDB_BIN_SIZE; | |
1522 | dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n", | |
1523 | bin, addr, way); | |
1524 | /* Evict entry */ | |
1525 | sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
1526 | index, NULL, false); | |
1527 | } | |
1528 | } | |
1529 | l2_lookup.index = sja1105et_fdb_index(bin, way); | |
1530 | ||
60f6053f VO |
1531 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, |
1532 | l2_lookup.index, &l2_lookup, | |
1533 | true); | |
1534 | if (rc < 0) | |
1535 | return rc; | |
1536 | ||
1537 | return sja1105_static_fdb_change(priv, port, &l2_lookup, true); | |
291d1e72 VO |
1538 | } |
1539 | ||
9dfa6911 VO |
1540 | int sja1105et_fdb_del(struct dsa_switch *ds, int port, |
1541 | const unsigned char *addr, u16 vid) | |
291d1e72 VO |
1542 | { |
1543 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
1544 | struct sja1105_private *priv = ds->priv; | |
60f6053f | 1545 | int index, bin, way, rc; |
291d1e72 VO |
1546 | bool keep; |
1547 | ||
9dfa6911 VO |
1548 | bin = sja1105et_fdb_hash(priv, addr, vid); |
1549 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, | |
1550 | &l2_lookup, NULL); | |
291d1e72 VO |
1551 | if (way < 0) |
1552 | return 0; | |
1553 | index = sja1105et_fdb_index(bin, way); | |
1554 | ||
1555 | /* We have an FDB entry. Is our port in the destination mask? If yes, | |
1556 | * we need to remove it. If the resulting port mask becomes empty, we | |
1557 | * need to completely evict the FDB entry. | |
1558 | * Otherwise we just write it back. | |
1559 | */ | |
7752e937 VO |
1560 | l2_lookup.destports &= ~BIT(port); |
1561 | ||
291d1e72 VO |
1562 | if (l2_lookup.destports) |
1563 | keep = true; | |
1564 | else | |
1565 | keep = false; | |
1566 | ||
60f6053f VO |
1567 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, |
1568 | index, &l2_lookup, keep); | |
1569 | if (rc < 0) | |
1570 | return rc; | |
1571 | ||
1572 | return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); | |
291d1e72 VO |
1573 | } |
1574 | ||
9dfa6911 VO |
1575 | int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, |
1576 | const unsigned char *addr, u16 vid) | |
1577 | { | |
1da73821 VO |
1578 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1579 | struct sja1105_private *priv = ds->priv; | |
1580 | int rc, i; | |
1581 | ||
1582 | /* Search for an existing entry in the FDB table */ | |
1583 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
1584 | l2_lookup.vlanid = vid; | |
1585 | l2_lookup.iotag = SJA1105_S_TAG; | |
1586 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); | |
0fac6aa0 | 1587 | if (priv->vlan_aware) { |
6d7c7d94 VO |
1588 | l2_lookup.mask_vlanid = VLAN_VID_MASK; |
1589 | l2_lookup.mask_iotag = BIT(0); | |
1590 | } else { | |
1591 | l2_lookup.mask_vlanid = 0; | |
1592 | l2_lookup.mask_iotag = 0; | |
1593 | } | |
1da73821 VO |
1594 | l2_lookup.destports = BIT(port); |
1595 | ||
1596 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1597 | SJA1105_SEARCH, &l2_lookup); | |
1598 | if (rc == 0) { | |
1599 | /* Found and this port is already in the entry's | |
1600 | * port mask => job done | |
1601 | */ | |
1602 | if (l2_lookup.destports & BIT(port)) | |
1603 | return 0; | |
1604 | /* l2_lookup.index is populated by the switch in case it | |
1605 | * found something. | |
1606 | */ | |
1607 | l2_lookup.destports |= BIT(port); | |
1608 | goto skip_finding_an_index; | |
1609 | } | |
1610 | ||
1611 | /* Not found, so try to find an unused spot in the FDB. | |
1612 | * This is slightly inefficient because the strategy is knock-knock at | |
1613 | * every possible position from 0 to 1023. | |
1614 | */ | |
1615 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { | |
1616 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1617 | i, NULL); | |
1618 | if (rc < 0) | |
1619 | break; | |
1620 | } | |
1621 | if (i == SJA1105_MAX_L2_LOOKUP_COUNT) { | |
1622 | dev_err(ds->dev, "FDB is full, cannot add entry.\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
17ae6555 | 1625 | l2_lookup.lockeds = true; |
1da73821 VO |
1626 | l2_lookup.index = i; |
1627 | ||
1628 | skip_finding_an_index: | |
60f6053f VO |
1629 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, |
1630 | l2_lookup.index, &l2_lookup, | |
1631 | true); | |
1632 | if (rc < 0) | |
1633 | return rc; | |
1634 | ||
1635 | return sja1105_static_fdb_change(priv, port, &l2_lookup, true); | |
9dfa6911 VO |
1636 | } |
1637 | ||
1638 | int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, | |
1639 | const unsigned char *addr, u16 vid) | |
1640 | { | |
1da73821 VO |
1641 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1642 | struct sja1105_private *priv = ds->priv; | |
1643 | bool keep; | |
1644 | int rc; | |
1645 | ||
1646 | l2_lookup.macaddr = ether_addr_to_u64(addr); | |
1647 | l2_lookup.vlanid = vid; | |
1648 | l2_lookup.iotag = SJA1105_S_TAG; | |
1649 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); | |
0fac6aa0 | 1650 | if (priv->vlan_aware) { |
6d7c7d94 VO |
1651 | l2_lookup.mask_vlanid = VLAN_VID_MASK; |
1652 | l2_lookup.mask_iotag = BIT(0); | |
1653 | } else { | |
1654 | l2_lookup.mask_vlanid = 0; | |
1655 | l2_lookup.mask_iotag = 0; | |
1656 | } | |
1da73821 VO |
1657 | l2_lookup.destports = BIT(port); |
1658 | ||
1659 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1660 | SJA1105_SEARCH, &l2_lookup); | |
1661 | if (rc < 0) | |
1662 | return 0; | |
1663 | ||
1664 | l2_lookup.destports &= ~BIT(port); | |
1665 | ||
1666 | /* Decide whether we remove just this port from the FDB entry, | |
1667 | * or if we remove it completely. | |
1668 | */ | |
1669 | if (l2_lookup.destports) | |
1670 | keep = true; | |
1671 | else | |
1672 | keep = false; | |
1673 | ||
60f6053f VO |
1674 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, |
1675 | l2_lookup.index, &l2_lookup, keep); | |
1676 | if (rc < 0) | |
1677 | return rc; | |
1678 | ||
1679 | return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); | |
9dfa6911 VO |
1680 | } |
1681 | ||
1682 | static int sja1105_fdb_add(struct dsa_switch *ds, int port, | |
1683 | const unsigned char *addr, u16 vid) | |
1684 | { | |
1685 | struct sja1105_private *priv = ds->priv; | |
b3ee526a | 1686 | |
6d7c7d94 | 1687 | return priv->info->fdb_add_cmd(ds, port, addr, vid); |
9dfa6911 VO |
1688 | } |
1689 | ||
1690 | static int sja1105_fdb_del(struct dsa_switch *ds, int port, | |
1691 | const unsigned char *addr, u16 vid) | |
1692 | { | |
1693 | struct sja1105_private *priv = ds->priv; | |
b3ee526a | 1694 | |
6d7c7d94 | 1695 | return priv->info->fdb_del_cmd(ds, port, addr, vid); |
9dfa6911 VO |
1696 | } |
1697 | ||
291d1e72 VO |
1698 | static int sja1105_fdb_dump(struct dsa_switch *ds, int port, |
1699 | dsa_fdb_dump_cb_t *cb, void *data) | |
1700 | { | |
1701 | struct sja1105_private *priv = ds->priv; | |
1702 | struct device *dev = ds->dev; | |
1703 | int i; | |
1704 | ||
1705 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { | |
1706 | struct sja1105_l2_lookup_entry l2_lookup = {0}; | |
1707 | u8 macaddr[ETH_ALEN]; | |
1708 | int rc; | |
1709 | ||
1710 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, | |
1711 | i, &l2_lookup); | |
1712 | /* No fdb entry at i, not an issue */ | |
def84604 | 1713 | if (rc == -ENOENT) |
291d1e72 VO |
1714 | continue; |
1715 | if (rc) { | |
1716 | dev_err(dev, "Failed to dump FDB: %d\n", rc); | |
1717 | return rc; | |
1718 | } | |
1719 | ||
1720 | /* FDB dump callback is per port. This means we have to | |
1721 | * disregard a valid entry if it's not for this port, even if | |
1722 | * only to revisit it later. This is inefficient because the | |
1723 | * 1024-sized FDB table needs to be traversed 4 times through | |
1724 | * SPI during a 'bridge fdb show' command. | |
1725 | */ | |
1726 | if (!(l2_lookup.destports & BIT(port))) | |
1727 | continue; | |
4d942354 VO |
1728 | |
1729 | /* We need to hide the FDB entry for unknown multicast */ | |
1730 | if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST && | |
1731 | l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST) | |
1732 | continue; | |
1733 | ||
291d1e72 | 1734 | u64_to_ether_addr(l2_lookup.macaddr, macaddr); |
93647594 | 1735 | |
6d7c7d94 | 1736 | /* We need to hide the dsa_8021q VLANs from the user. */ |
0fac6aa0 | 1737 | if (!priv->vlan_aware) |
6d7c7d94 | 1738 | l2_lookup.vlanid = 0; |
17ae6555 | 1739 | cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data); |
291d1e72 VO |
1740 | } |
1741 | return 0; | |
1742 | } | |
1743 | ||
a52b2da7 VO |
1744 | static int sja1105_mdb_add(struct dsa_switch *ds, int port, |
1745 | const struct switchdev_obj_port_mdb *mdb) | |
291d1e72 | 1746 | { |
a52b2da7 | 1747 | return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid); |
291d1e72 VO |
1748 | } |
1749 | ||
1750 | static int sja1105_mdb_del(struct dsa_switch *ds, int port, | |
1751 | const struct switchdev_obj_port_mdb *mdb) | |
1752 | { | |
1753 | return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid); | |
1754 | } | |
1755 | ||
7f7ccdea VO |
1756 | /* Common function for unicast and broadcast flood configuration. |
1757 | * Flooding is configured between each {ingress, egress} port pair, and since | |
1758 | * the bridge's semantics are those of "egress flooding", it means we must | |
1759 | * enable flooding towards this port from all ingress ports that are in the | |
1760 | * same forwarding domain. | |
1761 | */ | |
1762 | static int sja1105_manage_flood_domains(struct sja1105_private *priv) | |
1763 | { | |
1764 | struct sja1105_l2_forwarding_entry *l2_fwd; | |
1765 | struct dsa_switch *ds = priv->ds; | |
1766 | int from, to, rc; | |
1767 | ||
1768 | l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; | |
1769 | ||
1770 | for (from = 0; from < ds->num_ports; from++) { | |
1771 | u64 fl_domain = 0, bc_domain = 0; | |
1772 | ||
1773 | for (to = 0; to < priv->ds->num_ports; to++) { | |
1774 | if (!sja1105_can_forward(l2_fwd, from, to)) | |
1775 | continue; | |
1776 | ||
1777 | if (priv->ucast_egress_floods & BIT(to)) | |
1778 | fl_domain |= BIT(to); | |
1779 | if (priv->bcast_egress_floods & BIT(to)) | |
1780 | bc_domain |= BIT(to); | |
1781 | } | |
1782 | ||
1783 | /* Nothing changed, nothing to do */ | |
1784 | if (l2_fwd[from].fl_domain == fl_domain && | |
1785 | l2_fwd[from].bc_domain == bc_domain) | |
1786 | continue; | |
1787 | ||
1788 | l2_fwd[from].fl_domain = fl_domain; | |
1789 | l2_fwd[from].bc_domain = bc_domain; | |
1790 | ||
1791 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, | |
1792 | from, &l2_fwd[from], true); | |
1793 | if (rc < 0) | |
1794 | return rc; | |
1795 | } | |
1796 | ||
1797 | return 0; | |
1798 | } | |
1799 | ||
8aa9ebcc VO |
1800 | static int sja1105_bridge_member(struct dsa_switch *ds, int port, |
1801 | struct net_device *br, bool member) | |
1802 | { | |
1803 | struct sja1105_l2_forwarding_entry *l2_fwd; | |
1804 | struct sja1105_private *priv = ds->priv; | |
1805 | int i, rc; | |
1806 | ||
1807 | l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; | |
1808 | ||
542043e9 | 1809 | for (i = 0; i < ds->num_ports; i++) { |
8aa9ebcc VO |
1810 | /* Add this port to the forwarding matrix of the |
1811 | * other ports in the same bridge, and viceversa. | |
1812 | */ | |
1813 | if (!dsa_is_user_port(ds, i)) | |
1814 | continue; | |
1815 | /* For the ports already under the bridge, only one thing needs | |
1816 | * to be done, and that is to add this port to their | |
1817 | * reachability domain. So we can perform the SPI write for | |
1818 | * them immediately. However, for this port itself (the one | |
1819 | * that is new to the bridge), we need to add all other ports | |
1820 | * to its reachability domain. So we do that incrementally in | |
1821 | * this loop, and perform the SPI write only at the end, once | |
1822 | * the domain contains all other bridge ports. | |
1823 | */ | |
1824 | if (i == port) | |
1825 | continue; | |
1826 | if (dsa_to_port(ds, i)->bridge_dev != br) | |
1827 | continue; | |
1828 | sja1105_port_allow_traffic(l2_fwd, i, port, member); | |
1829 | sja1105_port_allow_traffic(l2_fwd, port, i, member); | |
1830 | ||
1831 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, | |
1832 | i, &l2_fwd[i], true); | |
1833 | if (rc < 0) | |
1834 | return rc; | |
1835 | } | |
1836 | ||
7f7ccdea VO |
1837 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, |
1838 | port, &l2_fwd[port], true); | |
1839 | if (rc) | |
1840 | return rc; | |
1841 | ||
cde8078e VO |
1842 | rc = sja1105_commit_pvid(ds, port); |
1843 | if (rc) | |
1844 | return rc; | |
1845 | ||
7f7ccdea | 1846 | return sja1105_manage_flood_domains(priv); |
8aa9ebcc VO |
1847 | } |
1848 | ||
640f763f VO |
1849 | static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port, |
1850 | u8 state) | |
1851 | { | |
1852 | struct sja1105_private *priv = ds->priv; | |
1853 | struct sja1105_mac_config_entry *mac; | |
1854 | ||
1855 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
1856 | ||
1857 | switch (state) { | |
1858 | case BR_STATE_DISABLED: | |
1859 | case BR_STATE_BLOCKING: | |
1860 | /* From UM10944 description of DRPDTAG (why put this there?): | |
1861 | * "Management traffic flows to the port regardless of the state | |
1862 | * of the INGRESS flag". So BPDUs are still be allowed to pass. | |
1863 | * At the moment no difference between DISABLED and BLOCKING. | |
1864 | */ | |
1865 | mac[port].ingress = false; | |
1866 | mac[port].egress = false; | |
1867 | mac[port].dyn_learn = false; | |
1868 | break; | |
1869 | case BR_STATE_LISTENING: | |
1870 | mac[port].ingress = true; | |
1871 | mac[port].egress = false; | |
1872 | mac[port].dyn_learn = false; | |
1873 | break; | |
1874 | case BR_STATE_LEARNING: | |
1875 | mac[port].ingress = true; | |
1876 | mac[port].egress = false; | |
4d942354 | 1877 | mac[port].dyn_learn = !!(priv->learn_ena & BIT(port)); |
640f763f VO |
1878 | break; |
1879 | case BR_STATE_FORWARDING: | |
1880 | mac[port].ingress = true; | |
1881 | mac[port].egress = true; | |
4d942354 | 1882 | mac[port].dyn_learn = !!(priv->learn_ena & BIT(port)); |
640f763f VO |
1883 | break; |
1884 | default: | |
1885 | dev_err(ds->dev, "invalid STP state: %d\n", state); | |
1886 | return; | |
1887 | } | |
1888 | ||
1889 | sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
1890 | &mac[port], true); | |
1891 | } | |
1892 | ||
8aa9ebcc VO |
1893 | static int sja1105_bridge_join(struct dsa_switch *ds, int port, |
1894 | struct net_device *br) | |
1895 | { | |
1896 | return sja1105_bridge_member(ds, port, br, true); | |
1897 | } | |
1898 | ||
1899 | static void sja1105_bridge_leave(struct dsa_switch *ds, int port, | |
1900 | struct net_device *br) | |
1901 | { | |
1902 | sja1105_bridge_member(ds, port, br, false); | |
1903 | } | |
1904 | ||
4d752508 VO |
1905 | #define BYTES_PER_KBIT (1000LL / 8) |
1906 | ||
1907 | static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv) | |
1908 | { | |
1909 | int i; | |
1910 | ||
1911 | for (i = 0; i < priv->info->num_cbs_shapers; i++) | |
1912 | if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope) | |
1913 | return i; | |
1914 | ||
1915 | return -1; | |
1916 | } | |
1917 | ||
1918 | static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port, | |
1919 | int prio) | |
1920 | { | |
1921 | int i; | |
1922 | ||
1923 | for (i = 0; i < priv->info->num_cbs_shapers; i++) { | |
1924 | struct sja1105_cbs_entry *cbs = &priv->cbs[i]; | |
1925 | ||
1926 | if (cbs->port == port && cbs->prio == prio) { | |
1927 | memset(cbs, 0, sizeof(*cbs)); | |
1928 | return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, | |
1929 | i, cbs, true); | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | return 0; | |
1934 | } | |
1935 | ||
1936 | static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port, | |
1937 | struct tc_cbs_qopt_offload *offload) | |
1938 | { | |
1939 | struct sja1105_private *priv = ds->priv; | |
1940 | struct sja1105_cbs_entry *cbs; | |
1941 | int index; | |
1942 | ||
1943 | if (!offload->enable) | |
1944 | return sja1105_delete_cbs_shaper(priv, port, offload->queue); | |
1945 | ||
1946 | index = sja1105_find_unused_cbs_shaper(priv); | |
1947 | if (index < 0) | |
1948 | return -ENOSPC; | |
1949 | ||
1950 | cbs = &priv->cbs[index]; | |
1951 | cbs->port = port; | |
1952 | cbs->prio = offload->queue; | |
1953 | /* locredit and sendslope are negative by definition. In hardware, | |
1954 | * positive values must be provided, and the negative sign is implicit. | |
1955 | */ | |
1956 | cbs->credit_hi = offload->hicredit; | |
1957 | cbs->credit_lo = abs(offload->locredit); | |
1958 | /* User space is in kbits/sec, hardware in bytes/sec */ | |
1959 | cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT; | |
1960 | cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT); | |
1961 | /* Convert the negative values from 64-bit 2's complement | |
1962 | * to 32-bit 2's complement (for the case of 0x80000000 whose | |
1963 | * negative is still negative). | |
1964 | */ | |
1965 | cbs->credit_lo &= GENMASK_ULL(31, 0); | |
1966 | cbs->send_slope &= GENMASK_ULL(31, 0); | |
1967 | ||
1968 | return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs, | |
1969 | true); | |
1970 | } | |
1971 | ||
1972 | static int sja1105_reload_cbs(struct sja1105_private *priv) | |
1973 | { | |
1974 | int rc = 0, i; | |
1975 | ||
be7f62ee VO |
1976 | /* The credit based shapers are only allocated if |
1977 | * CONFIG_NET_SCH_CBS is enabled. | |
1978 | */ | |
1979 | if (!priv->cbs) | |
1980 | return 0; | |
1981 | ||
4d752508 VO |
1982 | for (i = 0; i < priv->info->num_cbs_shapers; i++) { |
1983 | struct sja1105_cbs_entry *cbs = &priv->cbs[i]; | |
1984 | ||
1985 | if (!cbs->idle_slope && !cbs->send_slope) | |
1986 | continue; | |
1987 | ||
1988 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs, | |
1989 | true); | |
1990 | if (rc) | |
1991 | break; | |
1992 | } | |
1993 | ||
1994 | return rc; | |
1995 | } | |
1996 | ||
2eea1fa8 VO |
1997 | static const char * const sja1105_reset_reasons[] = { |
1998 | [SJA1105_VLAN_FILTERING] = "VLAN filtering", | |
1999 | [SJA1105_RX_HWTSTAMPING] = "RX timestamping", | |
2000 | [SJA1105_AGEING_TIME] = "Ageing time", | |
2001 | [SJA1105_SCHEDULING] = "Time-aware scheduling", | |
c279c726 | 2002 | [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing", |
dfacc5a2 | 2003 | [SJA1105_VIRTUAL_LINKS] = "Virtual links", |
2eea1fa8 VO |
2004 | }; |
2005 | ||
6666cebc VO |
2006 | /* For situations where we need to change a setting at runtime that is only |
2007 | * available through the static configuration, resetting the switch in order | |
2008 | * to upload the new static config is unavoidable. Back up the settings we | |
2009 | * modify at runtime (currently only MAC) and restore them after uploading, | |
2010 | * such that this operation is relatively seamless. | |
2011 | */ | |
2eea1fa8 VO |
2012 | int sja1105_static_config_reload(struct sja1105_private *priv, |
2013 | enum sja1105_reset_reason reason) | |
6666cebc | 2014 | { |
6cf99c13 VO |
2015 | struct ptp_system_timestamp ptp_sts_before; |
2016 | struct ptp_system_timestamp ptp_sts_after; | |
82760d7f | 2017 | int speed_mbps[SJA1105_MAX_NUM_PORTS]; |
84db00f2 | 2018 | u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0}; |
6666cebc | 2019 | struct sja1105_mac_config_entry *mac; |
6cf99c13 VO |
2020 | struct dsa_switch *ds = priv->ds; |
2021 | s64 t1, t2, t3, t4; | |
2022 | s64 t12, t34; | |
6666cebc | 2023 | int rc, i; |
6cf99c13 | 2024 | s64 now; |
6666cebc | 2025 | |
af580ae2 VO |
2026 | mutex_lock(&priv->mgmt_lock); |
2027 | ||
6666cebc VO |
2028 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
2029 | ||
8400cff6 VO |
2030 | /* Back up the dynamic link speed changed by sja1105_adjust_port_config |
2031 | * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the | |
2032 | * switch wants to see in the static config in order to allow us to | |
2033 | * change it through the dynamic interface later. | |
6666cebc | 2034 | */ |
542043e9 | 2035 | for (i = 0; i < ds->num_ports; i++) { |
3ad1d171 VO |
2036 | u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1); |
2037 | ||
41fed17f VO |
2038 | speed_mbps[i] = sja1105_port_speed_to_ethtool(priv, |
2039 | mac[i].speed); | |
2040 | mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; | |
6666cebc | 2041 | |
3ad1d171 VO |
2042 | if (priv->xpcs[i]) |
2043 | bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr); | |
84db00f2 | 2044 | } |
ffe10e67 | 2045 | |
6cf99c13 VO |
2046 | /* No PTP operations can run right now */ |
2047 | mutex_lock(&priv->ptp_data.lock); | |
2048 | ||
2049 | rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before); | |
61c77533 VO |
2050 | if (rc < 0) { |
2051 | mutex_unlock(&priv->ptp_data.lock); | |
2052 | goto out; | |
2053 | } | |
6cf99c13 | 2054 | |
6666cebc VO |
2055 | /* Reset switch and send updated static configuration */ |
2056 | rc = sja1105_static_config_upload(priv); | |
61c77533 VO |
2057 | if (rc < 0) { |
2058 | mutex_unlock(&priv->ptp_data.lock); | |
2059 | goto out; | |
2060 | } | |
6cf99c13 VO |
2061 | |
2062 | rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after); | |
61c77533 VO |
2063 | if (rc < 0) { |
2064 | mutex_unlock(&priv->ptp_data.lock); | |
2065 | goto out; | |
2066 | } | |
6cf99c13 VO |
2067 | |
2068 | t1 = timespec64_to_ns(&ptp_sts_before.pre_ts); | |
2069 | t2 = timespec64_to_ns(&ptp_sts_before.post_ts); | |
2070 | t3 = timespec64_to_ns(&ptp_sts_after.pre_ts); | |
2071 | t4 = timespec64_to_ns(&ptp_sts_after.post_ts); | |
2072 | /* Mid point, corresponds to pre-reset PTPCLKVAL */ | |
2073 | t12 = t1 + (t2 - t1) / 2; | |
2074 | /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */ | |
2075 | t34 = t3 + (t4 - t3) / 2; | |
2076 | /* Advance PTPCLKVAL by the time it took since its readout */ | |
2077 | now += (t34 - t12); | |
2078 | ||
2079 | __sja1105_ptp_adjtime(ds, now); | |
2080 | ||
6cf99c13 | 2081 | mutex_unlock(&priv->ptp_data.lock); |
6666cebc | 2082 | |
2eea1fa8 VO |
2083 | dev_info(priv->ds->dev, |
2084 | "Reset switch and programmed static config. Reason: %s\n", | |
2085 | sja1105_reset_reasons[reason]); | |
2086 | ||
6666cebc VO |
2087 | /* Configure the CGU (PLLs) for MII and RMII PHYs. |
2088 | * For these interfaces there is no dynamic configuration | |
2089 | * needed, since PLLs have same settings at all speeds. | |
2090 | */ | |
cb5a82d2 VO |
2091 | if (priv->info->clocking_setup) { |
2092 | rc = priv->info->clocking_setup(priv); | |
2093 | if (rc < 0) | |
2094 | goto out; | |
2095 | } | |
6666cebc | 2096 | |
542043e9 | 2097 | for (i = 0; i < ds->num_ports; i++) { |
3ad1d171 VO |
2098 | struct dw_xpcs *xpcs = priv->xpcs[i]; |
2099 | unsigned int mode; | |
84db00f2 | 2100 | |
8400cff6 | 2101 | rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]); |
6666cebc VO |
2102 | if (rc < 0) |
2103 | goto out; | |
ffe10e67 | 2104 | |
3ad1d171 | 2105 | if (!xpcs) |
84db00f2 VO |
2106 | continue; |
2107 | ||
3ad1d171 VO |
2108 | if (bmcr[i] & BMCR_ANENABLE) |
2109 | mode = MLO_AN_INBAND; | |
2110 | else if (priv->fixed_link[i]) | |
2111 | mode = MLO_AN_FIXED; | |
2112 | else | |
2113 | mode = MLO_AN_PHY; | |
ffe10e67 | 2114 | |
3ad1d171 VO |
2115 | rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode); |
2116 | if (rc < 0) | |
2117 | goto out; | |
ffe10e67 | 2118 | |
3ad1d171 | 2119 | if (!phylink_autoneg_inband(mode)) { |
ffe10e67 VO |
2120 | int speed = SPEED_UNKNOWN; |
2121 | ||
56b63466 VO |
2122 | if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX) |
2123 | speed = SPEED_2500; | |
2124 | else if (bmcr[i] & BMCR_SPEED1000) | |
ffe10e67 | 2125 | speed = SPEED_1000; |
84db00f2 | 2126 | else if (bmcr[i] & BMCR_SPEED100) |
ffe10e67 | 2127 | speed = SPEED_100; |
053d8ad1 | 2128 | else |
ffe10e67 VO |
2129 | speed = SPEED_10; |
2130 | ||
3ad1d171 VO |
2131 | xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i], |
2132 | speed, DUPLEX_FULL); | |
ffe10e67 VO |
2133 | } |
2134 | } | |
4d752508 VO |
2135 | |
2136 | rc = sja1105_reload_cbs(priv); | |
2137 | if (rc < 0) | |
2138 | goto out; | |
6666cebc | 2139 | out: |
af580ae2 VO |
2140 | mutex_unlock(&priv->mgmt_lock); |
2141 | ||
6666cebc VO |
2142 | return rc; |
2143 | } | |
2144 | ||
8aa9ebcc | 2145 | static enum dsa_tag_protocol |
4d776482 FF |
2146 | sja1105_get_tag_protocol(struct dsa_switch *ds, int port, |
2147 | enum dsa_tag_protocol mp) | |
8aa9ebcc | 2148 | { |
4913b8eb VO |
2149 | struct sja1105_private *priv = ds->priv; |
2150 | ||
2151 | return priv->info->tag_proto; | |
8aa9ebcc VO |
2152 | } |
2153 | ||
070ca3bb VO |
2154 | /* The TPID setting belongs to the General Parameters table, |
2155 | * which can only be partially reconfigured at runtime (and not the TPID). | |
2156 | * So a switch reset is required. | |
2157 | */ | |
89153ed6 VO |
2158 | int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, |
2159 | struct netlink_ext_ack *extack) | |
6666cebc | 2160 | { |
6d7c7d94 | 2161 | struct sja1105_l2_lookup_params_entry *l2_lookup_params; |
070ca3bb | 2162 | struct sja1105_general_params_entry *general_params; |
6666cebc | 2163 | struct sja1105_private *priv = ds->priv; |
070ca3bb | 2164 | struct sja1105_table *table; |
dfacc5a2 | 2165 | struct sja1105_rule *rule; |
070ca3bb | 2166 | u16 tpid, tpid2; |
6666cebc VO |
2167 | int rc; |
2168 | ||
bae33f2b VO |
2169 | list_for_each_entry(rule, &priv->flow_block.rules, list) { |
2170 | if (rule->type == SJA1105_RULE_VL) { | |
89153ed6 VO |
2171 | NL_SET_ERR_MSG_MOD(extack, |
2172 | "Cannot change VLAN filtering with active VL rules"); | |
bae33f2b | 2173 | return -EBUSY; |
dfacc5a2 VO |
2174 | } |
2175 | } | |
2176 | ||
070ca3bb | 2177 | if (enabled) { |
6666cebc | 2178 | /* Enable VLAN filtering. */ |
54fa49ee VO |
2179 | tpid = ETH_P_8021Q; |
2180 | tpid2 = ETH_P_8021AD; | |
070ca3bb | 2181 | } else { |
6666cebc | 2182 | /* Disable VLAN filtering. */ |
070ca3bb VO |
2183 | tpid = ETH_P_SJA1105; |
2184 | tpid2 = ETH_P_SJA1105; | |
2185 | } | |
2186 | ||
38b5beea VO |
2187 | for (port = 0; port < ds->num_ports; port++) { |
2188 | struct sja1105_port *sp = &priv->ports[port]; | |
2189 | ||
2190 | if (enabled) | |
2191 | sp->xmit_tpid = priv->info->qinq_tpid; | |
2192 | else | |
2193 | sp->xmit_tpid = ETH_P_SJA1105; | |
2194 | } | |
2195 | ||
0fac6aa0 | 2196 | if (priv->vlan_aware == enabled) |
cfa36b1f VO |
2197 | return 0; |
2198 | ||
0fac6aa0 | 2199 | priv->vlan_aware = enabled; |
7f14937f | 2200 | |
070ca3bb VO |
2201 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; |
2202 | general_params = table->entries; | |
f9a1a764 | 2203 | /* EtherType used to identify inner tagged (C-tag) VLAN traffic */ |
54fa49ee VO |
2204 | general_params->tpid = tpid; |
2205 | /* EtherType used to identify outer tagged (S-tag) VLAN traffic */ | |
070ca3bb | 2206 | general_params->tpid2 = tpid2; |
42824463 VO |
2207 | /* When VLAN filtering is on, we need to at least be able to |
2208 | * decode management traffic through the "backup plan". | |
2209 | */ | |
2210 | general_params->incl_srcpt1 = enabled; | |
2211 | general_params->incl_srcpt0 = enabled; | |
070ca3bb | 2212 | |
6d7c7d94 | 2213 | /* VLAN filtering => independent VLAN learning. |
2cafa72e | 2214 | * No VLAN filtering (or best effort) => shared VLAN learning. |
6d7c7d94 VO |
2215 | * |
2216 | * In shared VLAN learning mode, untagged traffic still gets | |
2217 | * pvid-tagged, and the FDB table gets populated with entries | |
2218 | * containing the "real" (pvid or from VLAN tag) VLAN ID. | |
2219 | * However the switch performs a masked L2 lookup in the FDB, | |
2220 | * effectively only looking up a frame's DMAC (and not VID) for the | |
2221 | * forwarding decision. | |
2222 | * | |
2223 | * This is extremely convenient for us, because in modes with | |
2224 | * vlan_filtering=0, dsa_8021q actually installs unique pvid's into | |
2225 | * each front panel port. This is good for identification but breaks | |
2226 | * learning badly - the VID of the learnt FDB entry is unique, aka | |
2227 | * no frames coming from any other port are going to have it. So | |
2228 | * for forwarding purposes, this is as though learning was broken | |
2229 | * (all frames get flooded). | |
2230 | */ | |
2231 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; | |
2232 | l2_lookup_params = table->entries; | |
0fac6aa0 | 2233 | l2_lookup_params->shared_learn = !priv->vlan_aware; |
aaa270c6 | 2234 | |
6dfd23d3 VO |
2235 | for (port = 0; port < ds->num_ports; port++) { |
2236 | if (dsa_is_unused_port(ds, port)) | |
2237 | continue; | |
2238 | ||
2239 | rc = sja1105_commit_pvid(ds, port); | |
2240 | if (rc) | |
2241 | return rc; | |
2242 | } | |
aef31718 | 2243 | |
2eea1fa8 | 2244 | rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING); |
6666cebc | 2245 | if (rc) |
89153ed6 | 2246 | NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype"); |
6666cebc | 2247 | |
0fac6aa0 | 2248 | return rc; |
6666cebc VO |
2249 | } |
2250 | ||
6dfd23d3 VO |
2251 | static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid, |
2252 | u16 flags) | |
2253 | { | |
2254 | struct sja1105_vlan_lookup_entry *vlan; | |
2255 | struct sja1105_table *table; | |
2256 | int match, rc; | |
5899ee36 | 2257 | |
6dfd23d3 VO |
2258 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; |
2259 | ||
2260 | match = sja1105_is_vlan_configured(priv, vid); | |
2261 | if (match < 0) { | |
2262 | rc = sja1105_table_resize(table, table->entry_count + 1); | |
2263 | if (rc) | |
2264 | return rc; | |
2265 | match = table->entry_count - 1; | |
5899ee36 VO |
2266 | } |
2267 | ||
6dfd23d3 VO |
2268 | /* Assign pointer after the resize (it's new memory) */ |
2269 | vlan = table->entries; | |
2270 | ||
2271 | vlan[match].type_entry = SJA1110_VLAN_D_TAG; | |
2272 | vlan[match].vlanid = vid; | |
2273 | vlan[match].vlan_bc |= BIT(port); | |
2274 | vlan[match].vmemb_port |= BIT(port); | |
2275 | if (flags & BRIDGE_VLAN_INFO_UNTAGGED) | |
2276 | vlan[match].tag_port &= ~BIT(port); | |
2277 | else | |
2278 | vlan[match].tag_port |= BIT(port); | |
5899ee36 | 2279 | |
6dfd23d3 VO |
2280 | return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, |
2281 | &vlan[match], true); | |
5899ee36 VO |
2282 | } |
2283 | ||
6dfd23d3 | 2284 | static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid) |
5899ee36 | 2285 | { |
6dfd23d3 VO |
2286 | struct sja1105_vlan_lookup_entry *vlan; |
2287 | struct sja1105_table *table; | |
2288 | bool keep = true; | |
2289 | int match, rc; | |
5899ee36 | 2290 | |
6dfd23d3 VO |
2291 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; |
2292 | ||
2293 | match = sja1105_is_vlan_configured(priv, vid); | |
2294 | /* Can't delete a missing entry. */ | |
2295 | if (match < 0) | |
2296 | return 0; | |
2297 | ||
2298 | /* Assign pointer after the resize (it's new memory) */ | |
2299 | vlan = table->entries; | |
2300 | ||
2301 | vlan[match].vlanid = vid; | |
2302 | vlan[match].vlan_bc &= ~BIT(port); | |
2303 | vlan[match].vmemb_port &= ~BIT(port); | |
2304 | /* Also unset tag_port, just so we don't have a confusing bitmap | |
2305 | * (no practical purpose). | |
2306 | */ | |
2307 | vlan[match].tag_port &= ~BIT(port); | |
2308 | ||
2309 | /* If there's no port left as member of this VLAN, | |
2310 | * it's time for it to go. | |
2311 | */ | |
2312 | if (!vlan[match].vmemb_port) | |
2313 | keep = false; | |
2314 | ||
2315 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, | |
2316 | &vlan[match], keep); | |
2317 | if (rc < 0) | |
2318 | return rc; | |
2319 | ||
2320 | if (!keep) | |
2321 | return sja1105_table_delete_entry(table, match); | |
5899ee36 VO |
2322 | |
2323 | return 0; | |
2324 | } | |
2325 | ||
6dfd23d3 VO |
2326 | static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port, |
2327 | const struct switchdev_obj_port_vlan *vlan, | |
2328 | struct netlink_ext_ack *extack) | |
6666cebc VO |
2329 | { |
2330 | struct sja1105_private *priv = ds->priv; | |
884be12f | 2331 | u16 flags = vlan->flags; |
6666cebc VO |
2332 | int rc; |
2333 | ||
0fac6aa0 | 2334 | /* Be sure to deny alterations to the configuration done by tag_8021q. |
1958d581 | 2335 | */ |
0fac6aa0 | 2336 | if (vid_is_dsa_8021q(vlan->vid)) { |
31046a5f VO |
2337 | NL_SET_ERR_MSG_MOD(extack, |
2338 | "Range 1024-3071 reserved for dsa_8021q operation"); | |
1958d581 VO |
2339 | return -EBUSY; |
2340 | } | |
2341 | ||
c5130029 VO |
2342 | /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */ |
2343 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
884be12f VO |
2344 | flags = 0; |
2345 | ||
2346 | rc = sja1105_vlan_add(priv, port, vlan->vid, flags); | |
6dfd23d3 | 2347 | if (rc) |
1958d581 | 2348 | return rc; |
ec5ae610 | 2349 | |
6dfd23d3 VO |
2350 | if (vlan->flags & BRIDGE_VLAN_INFO_PVID) |
2351 | priv->bridge_pvid[port] = vlan->vid; | |
ec5ae610 | 2352 | |
6dfd23d3 | 2353 | return sja1105_commit_pvid(ds, port); |
6666cebc VO |
2354 | } |
2355 | ||
6dfd23d3 VO |
2356 | static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port, |
2357 | const struct switchdev_obj_port_vlan *vlan) | |
6666cebc VO |
2358 | { |
2359 | struct sja1105_private *priv = ds->priv; | |
bef0746c | 2360 | int rc; |
ec5ae610 | 2361 | |
bef0746c VO |
2362 | rc = sja1105_vlan_del(priv, port, vlan->vid); |
2363 | if (rc) | |
2364 | return rc; | |
2365 | ||
2366 | /* In case the pvid was deleted, make sure that untagged packets will | |
2367 | * be dropped. | |
2368 | */ | |
2369 | return sja1105_commit_pvid(ds, port); | |
6666cebc VO |
2370 | } |
2371 | ||
5899ee36 VO |
2372 | static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, |
2373 | u16 flags) | |
2374 | { | |
2375 | struct sja1105_private *priv = ds->priv; | |
2376 | int rc; | |
2377 | ||
6dfd23d3 VO |
2378 | rc = sja1105_vlan_add(priv, port, vid, flags); |
2379 | if (rc) | |
5899ee36 VO |
2380 | return rc; |
2381 | ||
6dfd23d3 VO |
2382 | if (flags & BRIDGE_VLAN_INFO_PVID) |
2383 | priv->tag_8021q_pvid[port] = vid; | |
2384 | ||
2385 | return sja1105_commit_pvid(ds, port); | |
5899ee36 VO |
2386 | } |
2387 | ||
2388 | static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) | |
2389 | { | |
2390 | struct sja1105_private *priv = ds->priv; | |
5899ee36 | 2391 | |
6dfd23d3 | 2392 | return sja1105_vlan_del(priv, port, vid); |
5899ee36 VO |
2393 | } |
2394 | ||
4fbc08bd VO |
2395 | static int sja1105_prechangeupper(struct dsa_switch *ds, int port, |
2396 | struct netdev_notifier_changeupper_info *info) | |
2397 | { | |
2398 | struct netlink_ext_ack *extack = info->info.extack; | |
2399 | struct net_device *upper = info->upper_dev; | |
19fa937a VO |
2400 | struct dsa_switch_tree *dst = ds->dst; |
2401 | struct dsa_port *dp; | |
4fbc08bd VO |
2402 | |
2403 | if (is_vlan_dev(upper)) { | |
2404 | NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported"); | |
2405 | return -EBUSY; | |
2406 | } | |
2407 | ||
19fa937a VO |
2408 | if (netif_is_bridge_master(upper)) { |
2409 | list_for_each_entry(dp, &dst->ports, list) { | |
2410 | if (dp->bridge_dev && dp->bridge_dev != upper && | |
2411 | br_vlan_enabled(dp->bridge_dev)) { | |
2412 | NL_SET_ERR_MSG_MOD(extack, | |
2413 | "Only one VLAN-aware bridge is supported"); | |
2414 | return -EBUSY; | |
2415 | } | |
2416 | } | |
2417 | } | |
2418 | ||
4fbc08bd VO |
2419 | return 0; |
2420 | } | |
2421 | ||
8aa9ebcc VO |
2422 | /* The programming model for the SJA1105 switch is "all-at-once" via static |
2423 | * configuration tables. Some of these can be dynamically modified at runtime, | |
2424 | * but not the xMII mode parameters table. | |
2425 | * Furthermode, some PHYs may not have crystals for generating their clocks | |
2426 | * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's | |
2427 | * ref_clk pin. So port clocking needs to be initialized early, before | |
2428 | * connecting to PHYs is attempted, otherwise they won't respond through MDIO. | |
2429 | * Setting correct PHY link speed does not matter now. | |
2430 | * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY | |
2431 | * bindings are not yet parsed by DSA core. We need to parse early so that we | |
2432 | * can populate the xMII mode parameters table. | |
2433 | */ | |
2434 | static int sja1105_setup(struct dsa_switch *ds) | |
2435 | { | |
8aa9ebcc VO |
2436 | struct sja1105_private *priv = ds->priv; |
2437 | int rc; | |
2438 | ||
5d645df9 | 2439 | rc = sja1105_parse_dt(priv); |
8aa9ebcc VO |
2440 | if (rc < 0) { |
2441 | dev_err(ds->dev, "Failed to parse DT: %d\n", rc); | |
2442 | return rc; | |
2443 | } | |
f5b8631c VO |
2444 | |
2445 | /* Error out early if internal delays are required through DT | |
2446 | * and we can't apply them. | |
2447 | */ | |
29afb83a | 2448 | rc = sja1105_parse_rgmii_delays(priv); |
f5b8631c VO |
2449 | if (rc < 0) { |
2450 | dev_err(ds->dev, "RGMII delay not supported\n"); | |
2451 | return rc; | |
2452 | } | |
2453 | ||
61c77126 | 2454 | rc = sja1105_ptp_clock_register(ds); |
bb77f36a VO |
2455 | if (rc < 0) { |
2456 | dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc); | |
2457 | return rc; | |
2458 | } | |
5a8f0974 VO |
2459 | |
2460 | rc = sja1105_mdiobus_register(ds); | |
2461 | if (rc < 0) { | |
2462 | dev_err(ds->dev, "Failed to register MDIO bus: %pe\n", | |
2463 | ERR_PTR(rc)); | |
2464 | goto out_ptp_clock_unregister; | |
2465 | } | |
2466 | ||
cb5a82d2 VO |
2467 | if (priv->info->disable_microcontroller) { |
2468 | rc = priv->info->disable_microcontroller(priv); | |
2469 | if (rc < 0) { | |
2470 | dev_err(ds->dev, | |
2471 | "Failed to disable microcontroller: %pe\n", | |
2472 | ERR_PTR(rc)); | |
2473 | goto out_mdiobus_unregister; | |
2474 | } | |
2475 | } | |
2476 | ||
8aa9ebcc | 2477 | /* Create and send configuration down to device */ |
5d645df9 | 2478 | rc = sja1105_static_config_load(priv); |
8aa9ebcc VO |
2479 | if (rc < 0) { |
2480 | dev_err(ds->dev, "Failed to load static config: %d\n", rc); | |
5a8f0974 | 2481 | goto out_mdiobus_unregister; |
8aa9ebcc | 2482 | } |
cb5a82d2 | 2483 | |
8aa9ebcc | 2484 | /* Configure the CGU (PHY link modes and speeds) */ |
cb5a82d2 VO |
2485 | if (priv->info->clocking_setup) { |
2486 | rc = priv->info->clocking_setup(priv); | |
2487 | if (rc < 0) { | |
2488 | dev_err(ds->dev, | |
2489 | "Failed to configure MII clocking: %pe\n", | |
2490 | ERR_PTR(rc)); | |
2491 | goto out_static_config_free; | |
2492 | } | |
8aa9ebcc | 2493 | } |
cb5a82d2 | 2494 | |
6666cebc VO |
2495 | /* On SJA1105, VLAN filtering per se is always enabled in hardware. |
2496 | * The only thing we can do to disable it is lie about what the 802.1Q | |
2497 | * EtherType is. | |
2498 | * So it will still try to apply VLAN filtering, but all ingress | |
2499 | * traffic (except frames received with EtherType of ETH_P_SJA1105) | |
2500 | * will be internally tagged with a distorted VLAN header where the | |
2501 | * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid. | |
2502 | */ | |
2503 | ds->vlan_filtering_is_global = true; | |
884be12f | 2504 | ds->untag_bridge_pvid = true; |
b6ad86e6 VO |
2505 | /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */ |
2506 | ds->num_fwd_offloading_bridges = 7; | |
8aa9ebcc | 2507 | |
5f06c63b VO |
2508 | /* Advertise the 8 egress queues */ |
2509 | ds->num_tx_queues = SJA1105_NUM_TC; | |
2510 | ||
c279c726 VO |
2511 | ds->mtu_enforcement_ingress = true; |
2512 | ||
0a7bdbc2 | 2513 | rc = sja1105_devlink_setup(ds); |
2cafa72e | 2514 | if (rc < 0) |
cec279a8 | 2515 | goto out_static_config_free; |
2cafa72e | 2516 | |
bbed0bbd | 2517 | rtnl_lock(); |
328621f6 | 2518 | rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); |
bbed0bbd | 2519 | rtnl_unlock(); |
cec279a8 VO |
2520 | if (rc) |
2521 | goto out_devlink_teardown; | |
2522 | ||
2523 | return 0; | |
2524 | ||
2525 | out_devlink_teardown: | |
2526 | sja1105_devlink_teardown(ds); | |
5a8f0974 VO |
2527 | out_mdiobus_unregister: |
2528 | sja1105_mdiobus_unregister(ds); | |
cec279a8 VO |
2529 | out_ptp_clock_unregister: |
2530 | sja1105_ptp_clock_unregister(ds); | |
2531 | out_static_config_free: | |
2532 | sja1105_static_config_free(&priv->static_config); | |
bbed0bbd VO |
2533 | |
2534 | return rc; | |
227d07a0 VO |
2535 | } |
2536 | ||
f3097be2 VO |
2537 | static void sja1105_teardown(struct dsa_switch *ds) |
2538 | { | |
2539 | struct sja1105_private *priv = ds->priv; | |
a68578c2 VO |
2540 | int port; |
2541 | ||
328621f6 VO |
2542 | rtnl_lock(); |
2543 | dsa_tag_8021q_unregister(ds); | |
2544 | rtnl_unlock(); | |
2545 | ||
542043e9 | 2546 | for (port = 0; port < ds->num_ports; port++) { |
a68578c2 VO |
2547 | struct sja1105_port *sp = &priv->ports[port]; |
2548 | ||
2549 | if (!dsa_is_user_port(ds, port)) | |
2550 | continue; | |
2551 | ||
52c0d4e3 VO |
2552 | if (sp->xmit_worker) |
2553 | kthread_destroy_worker(sp->xmit_worker); | |
a68578c2 | 2554 | } |
f3097be2 | 2555 | |
0a7bdbc2 | 2556 | sja1105_devlink_teardown(ds); |
a6af7763 | 2557 | sja1105_flower_teardown(ds); |
317ab5b8 | 2558 | sja1105_tas_teardown(ds); |
61c77126 | 2559 | sja1105_ptp_clock_unregister(ds); |
6cb0abbd | 2560 | sja1105_static_config_free(&priv->static_config); |
f3097be2 VO |
2561 | } |
2562 | ||
a68578c2 VO |
2563 | static void sja1105_port_disable(struct dsa_switch *ds, int port) |
2564 | { | |
2565 | struct sja1105_private *priv = ds->priv; | |
2566 | struct sja1105_port *sp = &priv->ports[port]; | |
2567 | ||
2568 | if (!dsa_is_user_port(ds, port)) | |
2569 | return; | |
2570 | ||
2571 | kthread_cancel_work_sync(&sp->xmit_work); | |
2572 | skb_queue_purge(&sp->xmit_queue); | |
2573 | } | |
2574 | ||
227d07a0 | 2575 | static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot, |
47ed985e | 2576 | struct sk_buff *skb, bool takets) |
227d07a0 VO |
2577 | { |
2578 | struct sja1105_mgmt_entry mgmt_route = {0}; | |
2579 | struct sja1105_private *priv = ds->priv; | |
2580 | struct ethhdr *hdr; | |
2581 | int timeout = 10; | |
2582 | int rc; | |
2583 | ||
2584 | hdr = eth_hdr(skb); | |
2585 | ||
2586 | mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest); | |
2587 | mgmt_route.destports = BIT(port); | |
2588 | mgmt_route.enfport = 1; | |
47ed985e VO |
2589 | mgmt_route.tsreg = 0; |
2590 | mgmt_route.takets = takets; | |
227d07a0 VO |
2591 | |
2592 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, | |
2593 | slot, &mgmt_route, true); | |
2594 | if (rc < 0) { | |
2595 | kfree_skb(skb); | |
2596 | return rc; | |
2597 | } | |
2598 | ||
2599 | /* Transfer skb to the host port. */ | |
68bb8ea8 | 2600 | dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave); |
227d07a0 VO |
2601 | |
2602 | /* Wait until the switch has processed the frame */ | |
2603 | do { | |
2604 | rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE, | |
2605 | slot, &mgmt_route); | |
2606 | if (rc < 0) { | |
2607 | dev_err_ratelimited(priv->ds->dev, | |
2608 | "failed to poll for mgmt route\n"); | |
2609 | continue; | |
2610 | } | |
2611 | ||
2612 | /* UM10944: The ENFPORT flag of the respective entry is | |
2613 | * cleared when a match is found. The host can use this | |
2614 | * flag as an acknowledgment. | |
2615 | */ | |
2616 | cpu_relax(); | |
2617 | } while (mgmt_route.enfport && --timeout); | |
2618 | ||
2619 | if (!timeout) { | |
2620 | /* Clean up the management route so that a follow-up | |
2621 | * frame may not match on it by mistake. | |
2a7e7409 VO |
2622 | * This is only hardware supported on P/Q/R/S - on E/T it is |
2623 | * a no-op and we are silently discarding the -EOPNOTSUPP. | |
227d07a0 VO |
2624 | */ |
2625 | sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, | |
2626 | slot, &mgmt_route, false); | |
2627 | dev_err_ratelimited(priv->ds->dev, "xmit timed out\n"); | |
2628 | } | |
2629 | ||
2630 | return NETDEV_TX_OK; | |
2631 | } | |
2632 | ||
a68578c2 VO |
2633 | #define work_to_port(work) \ |
2634 | container_of((work), struct sja1105_port, xmit_work) | |
2635 | #define tagger_to_sja1105(t) \ | |
2636 | container_of((t), struct sja1105_private, tagger_data) | |
2637 | ||
227d07a0 VO |
2638 | /* Deferred work is unfortunately necessary because setting up the management |
2639 | * route cannot be done from atomit context (SPI transfer takes a sleepable | |
2640 | * lock on the bus) | |
2641 | */ | |
a68578c2 | 2642 | static void sja1105_port_deferred_xmit(struct kthread_work *work) |
227d07a0 | 2643 | { |
a68578c2 VO |
2644 | struct sja1105_port *sp = work_to_port(work); |
2645 | struct sja1105_tagger_data *tagger_data = sp->data; | |
2646 | struct sja1105_private *priv = tagger_to_sja1105(tagger_data); | |
2647 | int port = sp - priv->ports; | |
2648 | struct sk_buff *skb; | |
227d07a0 | 2649 | |
a68578c2 | 2650 | while ((skb = skb_dequeue(&sp->xmit_queue)) != NULL) { |
c4b364ce | 2651 | struct sk_buff *clone = SJA1105_SKB_CB(skb)->clone; |
47ed985e | 2652 | |
a68578c2 | 2653 | mutex_lock(&priv->mgmt_lock); |
47ed985e | 2654 | |
a68578c2 | 2655 | sja1105_mgmt_xmit(priv->ds, port, 0, skb, !!clone); |
47ed985e | 2656 | |
a68578c2 VO |
2657 | /* The clone, if there, was made by dsa_skb_tx_timestamp */ |
2658 | if (clone) | |
2659 | sja1105_ptp_txtstamp_skb(priv->ds, port, clone); | |
47ed985e | 2660 | |
a68578c2 VO |
2661 | mutex_unlock(&priv->mgmt_lock); |
2662 | } | |
8aa9ebcc VO |
2663 | } |
2664 | ||
8456721d VO |
2665 | /* The MAXAGE setting belongs to the L2 Forwarding Parameters table, |
2666 | * which cannot be reconfigured at runtime. So a switch reset is required. | |
2667 | */ | |
2668 | static int sja1105_set_ageing_time(struct dsa_switch *ds, | |
2669 | unsigned int ageing_time) | |
2670 | { | |
2671 | struct sja1105_l2_lookup_params_entry *l2_lookup_params; | |
2672 | struct sja1105_private *priv = ds->priv; | |
2673 | struct sja1105_table *table; | |
2674 | unsigned int maxage; | |
2675 | ||
2676 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; | |
2677 | l2_lookup_params = table->entries; | |
2678 | ||
2679 | maxage = SJA1105_AGEING_TIME_MS(ageing_time); | |
2680 | ||
2681 | if (l2_lookup_params->maxage == maxage) | |
2682 | return 0; | |
2683 | ||
2684 | l2_lookup_params->maxage = maxage; | |
2685 | ||
2eea1fa8 | 2686 | return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME); |
8456721d VO |
2687 | } |
2688 | ||
c279c726 VO |
2689 | static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu) |
2690 | { | |
c279c726 VO |
2691 | struct sja1105_l2_policing_entry *policing; |
2692 | struct sja1105_private *priv = ds->priv; | |
c279c726 VO |
2693 | |
2694 | new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; | |
2695 | ||
777e55e3 | 2696 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) |
c279c726 VO |
2697 | new_mtu += VLAN_HLEN; |
2698 | ||
2699 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; | |
2700 | ||
a7cc081c | 2701 | if (policing[port].maxlen == new_mtu) |
c279c726 VO |
2702 | return 0; |
2703 | ||
a7cc081c | 2704 | policing[port].maxlen = new_mtu; |
c279c726 VO |
2705 | |
2706 | return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); | |
2707 | } | |
2708 | ||
2709 | static int sja1105_get_max_mtu(struct dsa_switch *ds, int port) | |
2710 | { | |
2711 | return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN; | |
2712 | } | |
2713 | ||
317ab5b8 VO |
2714 | static int sja1105_port_setup_tc(struct dsa_switch *ds, int port, |
2715 | enum tc_setup_type type, | |
2716 | void *type_data) | |
2717 | { | |
2718 | switch (type) { | |
2719 | case TC_SETUP_QDISC_TAPRIO: | |
2720 | return sja1105_setup_tc_taprio(ds, port, type_data); | |
4d752508 VO |
2721 | case TC_SETUP_QDISC_CBS: |
2722 | return sja1105_setup_tc_cbs(ds, port, type_data); | |
317ab5b8 VO |
2723 | default: |
2724 | return -EOPNOTSUPP; | |
2725 | } | |
2726 | } | |
2727 | ||
511e6ca0 VO |
2728 | /* We have a single mirror (@to) port, but can configure ingress and egress |
2729 | * mirroring on all other (@from) ports. | |
2730 | * We need to allow mirroring rules only as long as the @to port is always the | |
2731 | * same, and we need to unset the @to port from mirr_port only when there is no | |
2732 | * mirroring rule that references it. | |
2733 | */ | |
2734 | static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to, | |
2735 | bool ingress, bool enabled) | |
2736 | { | |
2737 | struct sja1105_general_params_entry *general_params; | |
2738 | struct sja1105_mac_config_entry *mac; | |
542043e9 | 2739 | struct dsa_switch *ds = priv->ds; |
511e6ca0 VO |
2740 | struct sja1105_table *table; |
2741 | bool already_enabled; | |
2742 | u64 new_mirr_port; | |
2743 | int rc; | |
2744 | ||
2745 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; | |
2746 | general_params = table->entries; | |
2747 | ||
2748 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
2749 | ||
542043e9 | 2750 | already_enabled = (general_params->mirr_port != ds->num_ports); |
511e6ca0 VO |
2751 | if (already_enabled && enabled && general_params->mirr_port != to) { |
2752 | dev_err(priv->ds->dev, | |
2753 | "Delete mirroring rules towards port %llu first\n", | |
2754 | general_params->mirr_port); | |
2755 | return -EBUSY; | |
2756 | } | |
2757 | ||
2758 | new_mirr_port = to; | |
2759 | if (!enabled) { | |
2760 | bool keep = false; | |
2761 | int port; | |
2762 | ||
2763 | /* Anybody still referencing mirr_port? */ | |
542043e9 | 2764 | for (port = 0; port < ds->num_ports; port++) { |
511e6ca0 VO |
2765 | if (mac[port].ing_mirr || mac[port].egr_mirr) { |
2766 | keep = true; | |
2767 | break; | |
2768 | } | |
2769 | } | |
2770 | /* Unset already_enabled for next time */ | |
2771 | if (!keep) | |
542043e9 | 2772 | new_mirr_port = ds->num_ports; |
511e6ca0 VO |
2773 | } |
2774 | if (new_mirr_port != general_params->mirr_port) { | |
2775 | general_params->mirr_port = new_mirr_port; | |
2776 | ||
2777 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS, | |
2778 | 0, general_params, true); | |
2779 | if (rc < 0) | |
2780 | return rc; | |
2781 | } | |
2782 | ||
2783 | if (ingress) | |
2784 | mac[from].ing_mirr = enabled; | |
2785 | else | |
2786 | mac[from].egr_mirr = enabled; | |
2787 | ||
2788 | return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from, | |
2789 | &mac[from], true); | |
2790 | } | |
2791 | ||
2792 | static int sja1105_mirror_add(struct dsa_switch *ds, int port, | |
2793 | struct dsa_mall_mirror_tc_entry *mirror, | |
2794 | bool ingress) | |
2795 | { | |
2796 | return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, | |
2797 | ingress, true); | |
2798 | } | |
2799 | ||
2800 | static void sja1105_mirror_del(struct dsa_switch *ds, int port, | |
2801 | struct dsa_mall_mirror_tc_entry *mirror) | |
2802 | { | |
2803 | sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, | |
2804 | mirror->ingress, false); | |
2805 | } | |
2806 | ||
a7cc081c VO |
2807 | static int sja1105_port_policer_add(struct dsa_switch *ds, int port, |
2808 | struct dsa_mall_policer_tc_entry *policer) | |
2809 | { | |
2810 | struct sja1105_l2_policing_entry *policing; | |
2811 | struct sja1105_private *priv = ds->priv; | |
2812 | ||
2813 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; | |
2814 | ||
2815 | /* In hardware, every 8 microseconds the credit level is incremented by | |
2816 | * the value of RATE bytes divided by 64, up to a maximum of SMAX | |
2817 | * bytes. | |
2818 | */ | |
2819 | policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec, | |
2820 | 1000000); | |
5f035af7 | 2821 | policing[port].smax = policer->burst; |
a7cc081c VO |
2822 | |
2823 | return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); | |
2824 | } | |
2825 | ||
2826 | static void sja1105_port_policer_del(struct dsa_switch *ds, int port) | |
2827 | { | |
2828 | struct sja1105_l2_policing_entry *policing; | |
2829 | struct sja1105_private *priv = ds->priv; | |
2830 | ||
2831 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; | |
2832 | ||
2833 | policing[port].rate = SJA1105_RATE_MBPS(1000); | |
2834 | policing[port].smax = 65535; | |
2835 | ||
2836 | sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); | |
2837 | } | |
2838 | ||
4d942354 VO |
2839 | static int sja1105_port_set_learning(struct sja1105_private *priv, int port, |
2840 | bool enabled) | |
2841 | { | |
2842 | struct sja1105_mac_config_entry *mac; | |
2843 | int rc; | |
2844 | ||
2845 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; | |
2846 | ||
4c44fc5e | 2847 | mac[port].dyn_learn = enabled; |
4d942354 VO |
2848 | |
2849 | rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, | |
2850 | &mac[port], true); | |
2851 | if (rc) | |
2852 | return rc; | |
2853 | ||
2854 | if (enabled) | |
2855 | priv->learn_ena |= BIT(port); | |
2856 | else | |
2857 | priv->learn_ena &= ~BIT(port); | |
2858 | ||
2859 | return 0; | |
2860 | } | |
2861 | ||
4d942354 VO |
2862 | static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to, |
2863 | struct switchdev_brport_flags flags) | |
2864 | { | |
7f7ccdea VO |
2865 | if (flags.mask & BR_FLOOD) { |
2866 | if (flags.val & BR_FLOOD) | |
2867 | priv->ucast_egress_floods |= BIT(to); | |
2868 | else | |
6a5166e0 | 2869 | priv->ucast_egress_floods &= ~BIT(to); |
7f7ccdea | 2870 | } |
4d942354 | 2871 | |
7f7ccdea VO |
2872 | if (flags.mask & BR_BCAST_FLOOD) { |
2873 | if (flags.val & BR_BCAST_FLOOD) | |
2874 | priv->bcast_egress_floods |= BIT(to); | |
2875 | else | |
6a5166e0 | 2876 | priv->bcast_egress_floods &= ~BIT(to); |
4d942354 VO |
2877 | } |
2878 | ||
7f7ccdea | 2879 | return sja1105_manage_flood_domains(priv); |
4d942354 VO |
2880 | } |
2881 | ||
2882 | static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to, | |
2883 | struct switchdev_brport_flags flags, | |
2884 | struct netlink_ext_ack *extack) | |
2885 | { | |
2886 | struct sja1105_l2_lookup_entry *l2_lookup; | |
2887 | struct sja1105_table *table; | |
2888 | int match; | |
2889 | ||
2890 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; | |
2891 | l2_lookup = table->entries; | |
2892 | ||
2893 | for (match = 0; match < table->entry_count; match++) | |
2894 | if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST && | |
2895 | l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST) | |
2896 | break; | |
2897 | ||
2898 | if (match == table->entry_count) { | |
2899 | NL_SET_ERR_MSG_MOD(extack, | |
2900 | "Could not find FDB entry for unknown multicast"); | |
2901 | return -ENOSPC; | |
2902 | } | |
2903 | ||
2904 | if (flags.val & BR_MCAST_FLOOD) | |
2905 | l2_lookup[match].destports |= BIT(to); | |
2906 | else | |
2907 | l2_lookup[match].destports &= ~BIT(to); | |
2908 | ||
2909 | return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, | |
2910 | l2_lookup[match].index, | |
2911 | &l2_lookup[match], | |
2912 | true); | |
2913 | } | |
2914 | ||
2915 | static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port, | |
2916 | struct switchdev_brport_flags flags, | |
2917 | struct netlink_ext_ack *extack) | |
2918 | { | |
2919 | struct sja1105_private *priv = ds->priv; | |
2920 | ||
2921 | if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | | |
2922 | BR_BCAST_FLOOD)) | |
2923 | return -EINVAL; | |
2924 | ||
2925 | if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) && | |
2926 | !priv->info->can_limit_mcast_flood) { | |
2927 | bool multicast = !!(flags.val & BR_MCAST_FLOOD); | |
2928 | bool unicast = !!(flags.val & BR_FLOOD); | |
2929 | ||
2930 | if (unicast != multicast) { | |
2931 | NL_SET_ERR_MSG_MOD(extack, | |
2932 | "This chip cannot configure multicast flooding independently of unicast"); | |
2933 | return -EINVAL; | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port, | |
2941 | struct switchdev_brport_flags flags, | |
2942 | struct netlink_ext_ack *extack) | |
2943 | { | |
2944 | struct sja1105_private *priv = ds->priv; | |
2945 | int rc; | |
2946 | ||
2947 | if (flags.mask & BR_LEARNING) { | |
2948 | bool learn_ena = !!(flags.val & BR_LEARNING); | |
2949 | ||
2950 | rc = sja1105_port_set_learning(priv, port, learn_ena); | |
2951 | if (rc) | |
2952 | return rc; | |
2953 | } | |
2954 | ||
2955 | if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) { | |
2956 | rc = sja1105_port_ucast_bcast_flood(priv, port, flags); | |
2957 | if (rc) | |
2958 | return rc; | |
2959 | } | |
2960 | ||
2961 | /* For chips that can't offload BR_MCAST_FLOOD independently, there | |
2962 | * is nothing to do here, we ensured the configuration is in sync by | |
2963 | * offloading BR_FLOOD. | |
2964 | */ | |
2965 | if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) { | |
2966 | rc = sja1105_port_mcast_flood(priv, port, flags, | |
2967 | extack); | |
2968 | if (rc) | |
2969 | return rc; | |
2970 | } | |
2971 | ||
2972 | return 0; | |
2973 | } | |
2974 | ||
8aa9ebcc VO |
2975 | static const struct dsa_switch_ops sja1105_switch_ops = { |
2976 | .get_tag_protocol = sja1105_get_tag_protocol, | |
2977 | .setup = sja1105_setup, | |
f3097be2 | 2978 | .teardown = sja1105_teardown, |
8456721d | 2979 | .set_ageing_time = sja1105_set_ageing_time, |
c279c726 VO |
2980 | .port_change_mtu = sja1105_change_mtu, |
2981 | .port_max_mtu = sja1105_get_max_mtu, | |
ad9f299a | 2982 | .phylink_validate = sja1105_phylink_validate, |
af7cd036 | 2983 | .phylink_mac_config = sja1105_mac_config, |
8400cff6 VO |
2984 | .phylink_mac_link_up = sja1105_mac_link_up, |
2985 | .phylink_mac_link_down = sja1105_mac_link_down, | |
52c34e6e VO |
2986 | .get_strings = sja1105_get_strings, |
2987 | .get_ethtool_stats = sja1105_get_ethtool_stats, | |
2988 | .get_sset_count = sja1105_get_sset_count, | |
bb77f36a | 2989 | .get_ts_info = sja1105_get_ts_info, |
a68578c2 | 2990 | .port_disable = sja1105_port_disable, |
291d1e72 VO |
2991 | .port_fdb_dump = sja1105_fdb_dump, |
2992 | .port_fdb_add = sja1105_fdb_add, | |
2993 | .port_fdb_del = sja1105_fdb_del, | |
8aa9ebcc VO |
2994 | .port_bridge_join = sja1105_bridge_join, |
2995 | .port_bridge_leave = sja1105_bridge_leave, | |
4d942354 VO |
2996 | .port_pre_bridge_flags = sja1105_port_pre_bridge_flags, |
2997 | .port_bridge_flags = sja1105_port_bridge_flags, | |
640f763f | 2998 | .port_stp_state_set = sja1105_bridge_stp_state_set, |
6666cebc | 2999 | .port_vlan_filtering = sja1105_vlan_filtering, |
6dfd23d3 VO |
3000 | .port_vlan_add = sja1105_bridge_vlan_add, |
3001 | .port_vlan_del = sja1105_bridge_vlan_del, | |
291d1e72 VO |
3002 | .port_mdb_add = sja1105_mdb_add, |
3003 | .port_mdb_del = sja1105_mdb_del, | |
a602afd2 VO |
3004 | .port_hwtstamp_get = sja1105_hwtstamp_get, |
3005 | .port_hwtstamp_set = sja1105_hwtstamp_set, | |
f3097be2 | 3006 | .port_rxtstamp = sja1105_port_rxtstamp, |
47ed985e | 3007 | .port_txtstamp = sja1105_port_txtstamp, |
317ab5b8 | 3008 | .port_setup_tc = sja1105_port_setup_tc, |
511e6ca0 VO |
3009 | .port_mirror_add = sja1105_mirror_add, |
3010 | .port_mirror_del = sja1105_mirror_del, | |
a7cc081c VO |
3011 | .port_policer_add = sja1105_port_policer_add, |
3012 | .port_policer_del = sja1105_port_policer_del, | |
a6af7763 VO |
3013 | .cls_flower_add = sja1105_cls_flower_add, |
3014 | .cls_flower_del = sja1105_cls_flower_del, | |
834f8933 | 3015 | .cls_flower_stats = sja1105_cls_flower_stats, |
ff4cf8ea | 3016 | .devlink_info_get = sja1105_devlink_info_get, |
5da11eb4 VO |
3017 | .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add, |
3018 | .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del, | |
4fbc08bd | 3019 | .port_prechangeupper = sja1105_prechangeupper, |
b6ad86e6 VO |
3020 | .port_bridge_tx_fwd_offload = dsa_tag_8021q_bridge_tx_fwd_offload, |
3021 | .port_bridge_tx_fwd_unoffload = dsa_tag_8021q_bridge_tx_fwd_unoffload, | |
8aa9ebcc VO |
3022 | }; |
3023 | ||
0b0e2997 VO |
3024 | static const struct of_device_id sja1105_dt_ids[]; |
3025 | ||
8aa9ebcc VO |
3026 | static int sja1105_check_device_id(struct sja1105_private *priv) |
3027 | { | |
3028 | const struct sja1105_regs *regs = priv->info->regs; | |
3029 | u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0}; | |
3030 | struct device *dev = &priv->spidev->dev; | |
0b0e2997 | 3031 | const struct of_device_id *match; |
dff79620 | 3032 | u32 device_id; |
8aa9ebcc VO |
3033 | u64 part_no; |
3034 | int rc; | |
3035 | ||
34d76e9f VO |
3036 | rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id, |
3037 | NULL); | |
8aa9ebcc VO |
3038 | if (rc < 0) |
3039 | return rc; | |
3040 | ||
1bd44870 VO |
3041 | rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id, |
3042 | SJA1105_SIZE_DEVICE_ID); | |
8aa9ebcc VO |
3043 | if (rc < 0) |
3044 | return rc; | |
3045 | ||
3046 | sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID); | |
3047 | ||
5978fac0 | 3048 | for (match = sja1105_dt_ids; match->compatible[0]; match++) { |
0b0e2997 VO |
3049 | const struct sja1105_info *info = match->data; |
3050 | ||
3051 | /* Is what's been probed in our match table at all? */ | |
3052 | if (info->device_id != device_id || info->part_no != part_no) | |
3053 | continue; | |
3054 | ||
3055 | /* But is it what's in the device tree? */ | |
3056 | if (priv->info->device_id != device_id || | |
3057 | priv->info->part_no != part_no) { | |
3058 | dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n", | |
3059 | priv->info->name, info->name); | |
3060 | /* It isn't. No problem, pick that up. */ | |
3061 | priv->info = info; | |
3062 | } | |
3063 | ||
3064 | return 0; | |
8aa9ebcc VO |
3065 | } |
3066 | ||
0b0e2997 VO |
3067 | dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n", |
3068 | device_id, part_no); | |
3069 | ||
3070 | return -ENODEV; | |
8aa9ebcc VO |
3071 | } |
3072 | ||
3073 | static int sja1105_probe(struct spi_device *spi) | |
3074 | { | |
844d7edc | 3075 | struct sja1105_tagger_data *tagger_data; |
8aa9ebcc VO |
3076 | struct device *dev = &spi->dev; |
3077 | struct sja1105_private *priv; | |
718bad0e | 3078 | size_t max_xfer, max_msg; |
8aa9ebcc | 3079 | struct dsa_switch *ds; |
a68578c2 | 3080 | int rc, port; |
8aa9ebcc VO |
3081 | |
3082 | if (!dev->of_node) { | |
3083 | dev_err(dev, "No DTS bindings for SJA1105 driver\n"); | |
3084 | return -EINVAL; | |
3085 | } | |
3086 | ||
3087 | priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL); | |
3088 | if (!priv) | |
3089 | return -ENOMEM; | |
3090 | ||
3091 | /* Configure the optional reset pin and bring up switch */ | |
3092 | priv->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); | |
3093 | if (IS_ERR(priv->reset_gpio)) | |
3094 | dev_dbg(dev, "reset-gpios not defined, ignoring\n"); | |
3095 | else | |
3096 | sja1105_hw_reset(priv->reset_gpio, 1, 1); | |
3097 | ||
3098 | /* Populate our driver private structure (priv) based on | |
3099 | * the device tree node that was probed (spi) | |
3100 | */ | |
3101 | priv->spidev = spi; | |
3102 | spi_set_drvdata(spi, priv); | |
3103 | ||
3104 | /* Configure the SPI bus */ | |
3105 | spi->bits_per_word = 8; | |
3106 | rc = spi_setup(spi); | |
3107 | if (rc < 0) { | |
3108 | dev_err(dev, "Could not init SPI\n"); | |
3109 | return rc; | |
3110 | } | |
3111 | ||
718bad0e VO |
3112 | /* In sja1105_xfer, we send spi_messages composed of two spi_transfers: |
3113 | * a small one for the message header and another one for the current | |
3114 | * chunk of the packed buffer. | |
3115 | * Check that the restrictions imposed by the SPI controller are | |
3116 | * respected: the chunk buffer is smaller than the max transfer size, | |
3117 | * and the total length of the chunk plus its message header is smaller | |
3118 | * than the max message size. | |
3119 | * We do that during probe time since the maximum transfer size is a | |
3120 | * runtime invariant. | |
3121 | */ | |
3122 | max_xfer = spi_max_transfer_size(spi); | |
3123 | max_msg = spi_max_message_size(spi); | |
3124 | ||
3125 | /* We need to send at least one 64-bit word of SPI payload per message | |
3126 | * in order to be able to make useful progress. | |
3127 | */ | |
3128 | if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) { | |
3129 | dev_err(dev, "SPI master cannot send large enough buffers, aborting\n"); | |
3130 | return -EINVAL; | |
3131 | } | |
3132 | ||
3133 | priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN; | |
3134 | if (priv->max_xfer_len > max_xfer) | |
3135 | priv->max_xfer_len = max_xfer; | |
3136 | if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER) | |
3137 | priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER; | |
3138 | ||
8aa9ebcc VO |
3139 | priv->info = of_device_get_match_data(dev); |
3140 | ||
3141 | /* Detect hardware device */ | |
3142 | rc = sja1105_check_device_id(priv); | |
3143 | if (rc < 0) { | |
3144 | dev_err(dev, "Device ID check failed: %d\n", rc); | |
3145 | return rc; | |
3146 | } | |
3147 | ||
3148 | dev_info(dev, "Probed switch chip: %s\n", priv->info->name); | |
3149 | ||
7e99e347 | 3150 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
8aa9ebcc VO |
3151 | if (!ds) |
3152 | return -ENOMEM; | |
3153 | ||
7e99e347 | 3154 | ds->dev = dev; |
3e77e59b | 3155 | ds->num_ports = priv->info->num_ports; |
8aa9ebcc VO |
3156 | ds->ops = &sja1105_switch_ops; |
3157 | ds->priv = priv; | |
3158 | priv->ds = ds; | |
3159 | ||
844d7edc | 3160 | tagger_data = &priv->tagger_data; |
844d7edc | 3161 | |
d5a619bf VD |
3162 | mutex_init(&priv->ptp_data.lock); |
3163 | mutex_init(&priv->mgmt_lock); | |
3164 | ||
3165 | sja1105_tas_setup(ds); | |
a6af7763 | 3166 | sja1105_flower_setup(ds); |
d5a619bf VD |
3167 | |
3168 | rc = dsa_register_switch(priv->ds); | |
3169 | if (rc) | |
328621f6 | 3170 | return rc; |
d5a619bf | 3171 | |
4d752508 VO |
3172 | if (IS_ENABLED(CONFIG_NET_SCH_CBS)) { |
3173 | priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers, | |
3174 | sizeof(struct sja1105_cbs_entry), | |
3175 | GFP_KERNEL); | |
dc596e3f VO |
3176 | if (!priv->cbs) { |
3177 | rc = -ENOMEM; | |
3178 | goto out_unregister_switch; | |
3179 | } | |
4d752508 VO |
3180 | } |
3181 | ||
227d07a0 | 3182 | /* Connections between dsa_port and sja1105_port */ |
542043e9 | 3183 | for (port = 0; port < ds->num_ports; port++) { |
a68578c2 VO |
3184 | struct sja1105_port *sp = &priv->ports[port]; |
3185 | struct dsa_port *dp = dsa_to_port(ds, port); | |
3186 | struct net_device *slave; | |
3187 | ||
3188 | if (!dsa_is_user_port(ds, port)) | |
3189 | continue; | |
227d07a0 | 3190 | |
a68578c2 VO |
3191 | dp->priv = sp; |
3192 | sp->dp = dp; | |
844d7edc | 3193 | sp->data = tagger_data; |
a68578c2 VO |
3194 | slave = dp->slave; |
3195 | kthread_init_work(&sp->xmit_work, sja1105_port_deferred_xmit); | |
3196 | sp->xmit_worker = kthread_create_worker(0, "%s_xmit", | |
3197 | slave->name); | |
3198 | if (IS_ERR(sp->xmit_worker)) { | |
3199 | rc = PTR_ERR(sp->xmit_worker); | |
3200 | dev_err(ds->dev, | |
3201 | "failed to create deferred xmit thread: %d\n", | |
3202 | rc); | |
dc596e3f | 3203 | goto out_destroy_workers; |
a68578c2 VO |
3204 | } |
3205 | skb_queue_head_init(&sp->xmit_queue); | |
38b5beea | 3206 | sp->xmit_tpid = ETH_P_SJA1105; |
227d07a0 | 3207 | } |
227d07a0 | 3208 | |
d5a619bf | 3209 | return 0; |
dc596e3f VO |
3210 | |
3211 | out_destroy_workers: | |
a68578c2 VO |
3212 | while (port-- > 0) { |
3213 | struct sja1105_port *sp = &priv->ports[port]; | |
3214 | ||
3215 | if (!dsa_is_user_port(ds, port)) | |
3216 | continue; | |
3217 | ||
3218 | kthread_destroy_worker(sp->xmit_worker); | |
3219 | } | |
dc596e3f VO |
3220 | |
3221 | out_unregister_switch: | |
3222 | dsa_unregister_switch(ds); | |
3223 | ||
a68578c2 | 3224 | return rc; |
8aa9ebcc VO |
3225 | } |
3226 | ||
3227 | static int sja1105_remove(struct spi_device *spi) | |
3228 | { | |
3229 | struct sja1105_private *priv = spi_get_drvdata(spi); | |
cedf4670 VO |
3230 | struct dsa_switch *ds = priv->ds; |
3231 | ||
3232 | dsa_unregister_switch(ds); | |
8aa9ebcc | 3233 | |
8aa9ebcc VO |
3234 | return 0; |
3235 | } | |
3236 | ||
3237 | static const struct of_device_id sja1105_dt_ids[] = { | |
3238 | { .compatible = "nxp,sja1105e", .data = &sja1105e_info }, | |
3239 | { .compatible = "nxp,sja1105t", .data = &sja1105t_info }, | |
3240 | { .compatible = "nxp,sja1105p", .data = &sja1105p_info }, | |
3241 | { .compatible = "nxp,sja1105q", .data = &sja1105q_info }, | |
3242 | { .compatible = "nxp,sja1105r", .data = &sja1105r_info }, | |
3243 | { .compatible = "nxp,sja1105s", .data = &sja1105s_info }, | |
3e77e59b VO |
3244 | { .compatible = "nxp,sja1110a", .data = &sja1110a_info }, |
3245 | { .compatible = "nxp,sja1110b", .data = &sja1110b_info }, | |
3246 | { .compatible = "nxp,sja1110c", .data = &sja1110c_info }, | |
3247 | { .compatible = "nxp,sja1110d", .data = &sja1110d_info }, | |
8aa9ebcc VO |
3248 | { /* sentinel */ }, |
3249 | }; | |
3250 | MODULE_DEVICE_TABLE(of, sja1105_dt_ids); | |
3251 | ||
3252 | static struct spi_driver sja1105_driver = { | |
3253 | .driver = { | |
3254 | .name = "sja1105", | |
3255 | .owner = THIS_MODULE, | |
3256 | .of_match_table = of_match_ptr(sja1105_dt_ids), | |
3257 | }, | |
3258 | .probe = sja1105_probe, | |
3259 | .remove = sja1105_remove, | |
3260 | }; | |
3261 | ||
3262 | module_spi_driver(sja1105_driver); | |
3263 | ||
3264 | MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>"); | |
3265 | MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>"); | |
3266 | MODULE_DESCRIPTION("SJA1105 Driver"); | |
3267 | MODULE_LICENSE("GPL v2"); |