]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
3 | ||
2648345f | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
1da177e4 LT |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 2 of the License, or (at your option) | |
9 | any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., 59 | |
18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in the | |
21 | file called LICENSE. | |
22 | ||
23 | Contact Information: | |
24 | Linux NICS <linux.nics@intel.com> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* e1000_hw.c | |
30 | * Shared functions for accessing and configuring the MAC | |
31 | */ | |
32 | ||
33 | #include "e1000_hw.h" | |
34 | ||
35 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); | |
36 | static void e1000_phy_init_script(struct e1000_hw *hw); | |
37 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); | |
38 | static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); | |
39 | static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); | |
40 | static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
41 | static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); | |
42 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
43 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
44 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, | |
45 | uint16_t count); | |
46 | static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); | |
47 | static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); | |
48 | static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, | |
49 | uint16_t words, uint16_t *data); | |
50 | static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, | |
51 | uint16_t offset, uint16_t words, | |
52 | uint16_t *data); | |
53 | static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); | |
54 | static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
55 | static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
56 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, | |
57 | uint16_t count); | |
58 | static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, | |
59 | uint16_t phy_data); | |
60 | static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, | |
61 | uint16_t *phy_data); | |
62 | static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); | |
63 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); | |
64 | static void e1000_release_eeprom(struct e1000_hw *hw); | |
65 | static void e1000_standby_eeprom(struct e1000_hw *hw); | |
1da177e4 LT |
66 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
67 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); | |
68 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); | |
2d7edb92 MC |
69 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
70 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); | |
1da177e4 LT |
71 | |
72 | /* IGP cable length table */ | |
73 | static const | |
74 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | |
75 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, | |
76 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, | |
77 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, | |
78 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, | |
79 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, | |
80 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, | |
81 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | |
82 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | |
83 | ||
2d7edb92 MC |
84 | static const |
85 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | |
868d5309 MC |
86 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
87 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
88 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
89 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
90 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
91 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
92 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
93 | 104, 109, 114, 118, 121, 124}; | |
2d7edb92 | 94 | |
1da177e4 LT |
95 | |
96 | /****************************************************************************** | |
97 | * Set the phy type member in the hw struct. | |
98 | * | |
99 | * hw - Struct containing variables accessed by shared code | |
100 | *****************************************************************************/ | |
101 | int32_t | |
102 | e1000_set_phy_type(struct e1000_hw *hw) | |
103 | { | |
104 | DEBUGFUNC("e1000_set_phy_type"); | |
105 | ||
2d7edb92 MC |
106 | if(hw->mac_type == e1000_undefined) |
107 | return -E1000_ERR_PHY_TYPE; | |
108 | ||
1da177e4 LT |
109 | switch(hw->phy_id) { |
110 | case M88E1000_E_PHY_ID: | |
111 | case M88E1000_I_PHY_ID: | |
112 | case M88E1011_I_PHY_ID: | |
2d7edb92 | 113 | case M88E1111_I_PHY_ID: |
1da177e4 LT |
114 | hw->phy_type = e1000_phy_m88; |
115 | break; | |
116 | case IGP01E1000_I_PHY_ID: | |
117 | if(hw->mac_type == e1000_82541 || | |
118 | hw->mac_type == e1000_82541_rev_2 || | |
119 | hw->mac_type == e1000_82547 || | |
120 | hw->mac_type == e1000_82547_rev_2) { | |
121 | hw->phy_type = e1000_phy_igp; | |
122 | break; | |
123 | } | |
124 | /* Fall Through */ | |
125 | default: | |
126 | /* Should never have loaded on this device */ | |
127 | hw->phy_type = e1000_phy_undefined; | |
128 | return -E1000_ERR_PHY_TYPE; | |
129 | } | |
130 | ||
131 | return E1000_SUCCESS; | |
132 | } | |
133 | ||
134 | /****************************************************************************** | |
135 | * IGP phy init script - initializes the GbE PHY | |
136 | * | |
137 | * hw - Struct containing variables accessed by shared code | |
138 | *****************************************************************************/ | |
139 | static void | |
140 | e1000_phy_init_script(struct e1000_hw *hw) | |
141 | { | |
142 | uint32_t ret_val; | |
143 | uint16_t phy_saved_data; | |
144 | ||
145 | DEBUGFUNC("e1000_phy_init_script"); | |
146 | ||
1da177e4 LT |
147 | if(hw->phy_init_script) { |
148 | msec_delay(20); | |
149 | ||
150 | /* Save off the current value of register 0x2F5B to be restored at | |
151 | * the end of this routine. */ | |
152 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
153 | ||
154 | /* Disabled the PHY transmitter */ | |
155 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
156 | ||
157 | msec_delay(20); | |
158 | ||
159 | e1000_write_phy_reg(hw,0x0000,0x0140); | |
160 | ||
161 | msec_delay(5); | |
162 | ||
163 | switch(hw->mac_type) { | |
164 | case e1000_82541: | |
165 | case e1000_82547: | |
166 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
167 | ||
168 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
169 | ||
170 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
171 | ||
172 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
173 | ||
174 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
175 | ||
176 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
177 | ||
178 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
179 | ||
180 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
181 | ||
182 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
183 | break; | |
184 | ||
185 | case e1000_82541_rev_2: | |
186 | case e1000_82547_rev_2: | |
187 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
188 | break; | |
189 | default: | |
190 | break; | |
191 | } | |
192 | ||
193 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
194 | ||
195 | msec_delay(20); | |
196 | ||
197 | /* Now enable the transmitter */ | |
198 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
199 | ||
200 | if(hw->mac_type == e1000_82547) { | |
201 | uint16_t fused, fine, coarse; | |
202 | ||
203 | /* Move to analog registers page */ | |
204 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
205 | ||
206 | if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | |
207 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); | |
208 | ||
209 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
210 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
211 | ||
212 | if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | |
213 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; | |
214 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
215 | } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | |
216 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | |
217 | ||
218 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
219 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
220 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
221 | ||
222 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
223 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, | |
224 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
225 | } | |
226 | } | |
227 | } | |
228 | } | |
229 | ||
230 | /****************************************************************************** | |
231 | * Set the mac type member in the hw struct. | |
232 | * | |
233 | * hw - Struct containing variables accessed by shared code | |
234 | *****************************************************************************/ | |
235 | int32_t | |
236 | e1000_set_mac_type(struct e1000_hw *hw) | |
237 | { | |
238 | DEBUGFUNC("e1000_set_mac_type"); | |
239 | ||
240 | switch (hw->device_id) { | |
241 | case E1000_DEV_ID_82542: | |
242 | switch (hw->revision_id) { | |
243 | case E1000_82542_2_0_REV_ID: | |
244 | hw->mac_type = e1000_82542_rev2_0; | |
245 | break; | |
246 | case E1000_82542_2_1_REV_ID: | |
247 | hw->mac_type = e1000_82542_rev2_1; | |
248 | break; | |
249 | default: | |
250 | /* Invalid 82542 revision ID */ | |
251 | return -E1000_ERR_MAC_TYPE; | |
252 | } | |
253 | break; | |
254 | case E1000_DEV_ID_82543GC_FIBER: | |
255 | case E1000_DEV_ID_82543GC_COPPER: | |
256 | hw->mac_type = e1000_82543; | |
257 | break; | |
258 | case E1000_DEV_ID_82544EI_COPPER: | |
259 | case E1000_DEV_ID_82544EI_FIBER: | |
260 | case E1000_DEV_ID_82544GC_COPPER: | |
261 | case E1000_DEV_ID_82544GC_LOM: | |
262 | hw->mac_type = e1000_82544; | |
263 | break; | |
264 | case E1000_DEV_ID_82540EM: | |
265 | case E1000_DEV_ID_82540EM_LOM: | |
266 | case E1000_DEV_ID_82540EP: | |
267 | case E1000_DEV_ID_82540EP_LOM: | |
268 | case E1000_DEV_ID_82540EP_LP: | |
269 | hw->mac_type = e1000_82540; | |
270 | break; | |
271 | case E1000_DEV_ID_82545EM_COPPER: | |
272 | case E1000_DEV_ID_82545EM_FIBER: | |
273 | hw->mac_type = e1000_82545; | |
274 | break; | |
275 | case E1000_DEV_ID_82545GM_COPPER: | |
276 | case E1000_DEV_ID_82545GM_FIBER: | |
277 | case E1000_DEV_ID_82545GM_SERDES: | |
278 | hw->mac_type = e1000_82545_rev_3; | |
279 | break; | |
280 | case E1000_DEV_ID_82546EB_COPPER: | |
281 | case E1000_DEV_ID_82546EB_FIBER: | |
282 | case E1000_DEV_ID_82546EB_QUAD_COPPER: | |
283 | hw->mac_type = e1000_82546; | |
284 | break; | |
285 | case E1000_DEV_ID_82546GB_COPPER: | |
286 | case E1000_DEV_ID_82546GB_FIBER: | |
287 | case E1000_DEV_ID_82546GB_SERDES: | |
288 | case E1000_DEV_ID_82546GB_PCIE: | |
289 | hw->mac_type = e1000_82546_rev_3; | |
290 | break; | |
291 | case E1000_DEV_ID_82541EI: | |
292 | case E1000_DEV_ID_82541EI_MOBILE: | |
293 | hw->mac_type = e1000_82541; | |
294 | break; | |
295 | case E1000_DEV_ID_82541ER: | |
296 | case E1000_DEV_ID_82541GI: | |
297 | case E1000_DEV_ID_82541GI_LF: | |
298 | case E1000_DEV_ID_82541GI_MOBILE: | |
299 | hw->mac_type = e1000_82541_rev_2; | |
300 | break; | |
301 | case E1000_DEV_ID_82547EI: | |
302 | hw->mac_type = e1000_82547; | |
303 | break; | |
304 | case E1000_DEV_ID_82547GI: | |
305 | hw->mac_type = e1000_82547_rev_2; | |
306 | break; | |
868d5309 MC |
307 | case E1000_DEV_ID_82571EB_COPPER: |
308 | case E1000_DEV_ID_82571EB_FIBER: | |
309 | case E1000_DEV_ID_82571EB_SERDES: | |
310 | hw->mac_type = e1000_82571; | |
311 | break; | |
312 | case E1000_DEV_ID_82572EI_COPPER: | |
313 | case E1000_DEV_ID_82572EI_FIBER: | |
314 | case E1000_DEV_ID_82572EI_SERDES: | |
315 | hw->mac_type = e1000_82572; | |
316 | break; | |
2d7edb92 MC |
317 | case E1000_DEV_ID_82573E: |
318 | case E1000_DEV_ID_82573E_IAMT: | |
868d5309 | 319 | case E1000_DEV_ID_82573L: |
2d7edb92 MC |
320 | hw->mac_type = e1000_82573; |
321 | break; | |
1da177e4 LT |
322 | default: |
323 | /* Should never have loaded on this device */ | |
324 | return -E1000_ERR_MAC_TYPE; | |
325 | } | |
326 | ||
327 | switch(hw->mac_type) { | |
868d5309 MC |
328 | case e1000_82571: |
329 | case e1000_82572: | |
2d7edb92 MC |
330 | case e1000_82573: |
331 | hw->eeprom_semaphore_present = TRUE; | |
332 | /* fall through */ | |
1da177e4 LT |
333 | case e1000_82541: |
334 | case e1000_82547: | |
335 | case e1000_82541_rev_2: | |
336 | case e1000_82547_rev_2: | |
337 | hw->asf_firmware_present = TRUE; | |
338 | break; | |
339 | default: | |
340 | break; | |
341 | } | |
342 | ||
343 | return E1000_SUCCESS; | |
344 | } | |
345 | ||
346 | /***************************************************************************** | |
347 | * Set media type and TBI compatibility. | |
348 | * | |
349 | * hw - Struct containing variables accessed by shared code | |
350 | * **************************************************************************/ | |
351 | void | |
352 | e1000_set_media_type(struct e1000_hw *hw) | |
353 | { | |
354 | uint32_t status; | |
355 | ||
356 | DEBUGFUNC("e1000_set_media_type"); | |
357 | ||
358 | if(hw->mac_type != e1000_82543) { | |
359 | /* tbi_compatibility is only valid on 82543 */ | |
360 | hw->tbi_compatibility_en = FALSE; | |
361 | } | |
362 | ||
363 | switch (hw->device_id) { | |
364 | case E1000_DEV_ID_82545GM_SERDES: | |
365 | case E1000_DEV_ID_82546GB_SERDES: | |
868d5309 MC |
366 | case E1000_DEV_ID_82571EB_SERDES: |
367 | case E1000_DEV_ID_82572EI_SERDES: | |
1da177e4 LT |
368 | hw->media_type = e1000_media_type_internal_serdes; |
369 | break; | |
370 | default: | |
3893d547 MC |
371 | switch (hw->mac_type) { |
372 | case e1000_82542_rev2_0: | |
373 | case e1000_82542_rev2_1: | |
374 | hw->media_type = e1000_media_type_fiber; | |
375 | break; | |
376 | case e1000_82573: | |
377 | /* The STATUS_TBIMODE bit is reserved or reused for the this | |
378 | * device. | |
379 | */ | |
380 | hw->media_type = e1000_media_type_copper; | |
381 | break; | |
382 | default: | |
1da177e4 | 383 | status = E1000_READ_REG(hw, STATUS); |
3893d547 | 384 | if (status & E1000_STATUS_TBIMODE) { |
1da177e4 LT |
385 | hw->media_type = e1000_media_type_fiber; |
386 | /* tbi_compatibility not valid on fiber */ | |
387 | hw->tbi_compatibility_en = FALSE; | |
388 | } else { | |
389 | hw->media_type = e1000_media_type_copper; | |
390 | } | |
3893d547 | 391 | break; |
1da177e4 LT |
392 | } |
393 | } | |
394 | } | |
395 | ||
396 | /****************************************************************************** | |
397 | * Reset the transmit and receive units; mask and clear all interrupts. | |
398 | * | |
399 | * hw - Struct containing variables accessed by shared code | |
400 | *****************************************************************************/ | |
401 | int32_t | |
402 | e1000_reset_hw(struct e1000_hw *hw) | |
403 | { | |
404 | uint32_t ctrl; | |
405 | uint32_t ctrl_ext; | |
406 | uint32_t icr; | |
407 | uint32_t manc; | |
408 | uint32_t led_ctrl; | |
2d7edb92 MC |
409 | uint32_t timeout; |
410 | uint32_t extcnf_ctrl; | |
411 | int32_t ret_val; | |
1da177e4 LT |
412 | |
413 | DEBUGFUNC("e1000_reset_hw"); | |
414 | ||
415 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ | |
416 | if(hw->mac_type == e1000_82542_rev2_0) { | |
417 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
418 | e1000_pci_clear_mwi(hw); | |
419 | } | |
420 | ||
2d7edb92 MC |
421 | if(hw->bus_type == e1000_bus_type_pci_express) { |
422 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | |
423 | * on the last TLP read/write transaction when MAC is reset. | |
424 | */ | |
425 | if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { | |
426 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); | |
427 | } | |
428 | } | |
429 | ||
1da177e4 LT |
430 | /* Clear interrupt mask to stop board from generating interrupts */ |
431 | DEBUGOUT("Masking off all interrupts\n"); | |
432 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
433 | ||
434 | /* Disable the Transmit and Receive units. Then delay to allow | |
435 | * any pending transactions to complete before we hit the MAC with | |
436 | * the global reset. | |
437 | */ | |
438 | E1000_WRITE_REG(hw, RCTL, 0); | |
439 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); | |
440 | E1000_WRITE_FLUSH(hw); | |
441 | ||
442 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
443 | hw->tbi_compatibility_on = FALSE; | |
444 | ||
445 | /* Delay to allow any outstanding PCI transactions to complete before | |
446 | * resetting the device | |
447 | */ | |
448 | msec_delay(10); | |
449 | ||
450 | ctrl = E1000_READ_REG(hw, CTRL); | |
451 | ||
452 | /* Must reset the PHY before resetting the MAC */ | |
453 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
2d7edb92 | 454 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
1da177e4 LT |
455 | msec_delay(5); |
456 | } | |
457 | ||
2d7edb92 MC |
458 | /* Must acquire the MDIO ownership before MAC reset. |
459 | * Ownership defaults to firmware after a reset. */ | |
460 | if(hw->mac_type == e1000_82573) { | |
461 | timeout = 10; | |
462 | ||
463 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
464 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
465 | ||
466 | do { | |
467 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | |
468 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
469 | ||
470 | if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
471 | break; | |
472 | else | |
473 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
474 | ||
475 | msec_delay(2); | |
476 | timeout--; | |
477 | } while(timeout); | |
478 | } | |
479 | ||
1da177e4 LT |
480 | /* Issue a global reset to the MAC. This will reset the chip's |
481 | * transmit, receive, DMA, and link units. It will not effect | |
482 | * the current PCI configuration. The global reset bit is self- | |
483 | * clearing, and should clear within a microsecond. | |
484 | */ | |
485 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
486 | ||
487 | switch(hw->mac_type) { | |
488 | case e1000_82544: | |
489 | case e1000_82540: | |
490 | case e1000_82545: | |
491 | case e1000_82546: | |
492 | case e1000_82541: | |
493 | case e1000_82541_rev_2: | |
494 | /* These controllers can't ack the 64-bit write when issuing the | |
495 | * reset, so use IO-mapping as a workaround to issue the reset */ | |
496 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
497 | break; | |
498 | case e1000_82545_rev_3: | |
499 | case e1000_82546_rev_3: | |
500 | /* Reset is performed on a shadow of the control register */ | |
501 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); | |
502 | break; | |
503 | default: | |
504 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
505 | break; | |
506 | } | |
507 | ||
508 | /* After MAC reset, force reload of EEPROM to restore power-on settings to | |
509 | * device. Later controllers reload the EEPROM automatically, so just wait | |
510 | * for reload to complete. | |
511 | */ | |
512 | switch(hw->mac_type) { | |
513 | case e1000_82542_rev2_0: | |
514 | case e1000_82542_rev2_1: | |
515 | case e1000_82543: | |
516 | case e1000_82544: | |
517 | /* Wait for reset to complete */ | |
518 | udelay(10); | |
519 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
520 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
521 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
522 | E1000_WRITE_FLUSH(hw); | |
523 | /* Wait for EEPROM reload */ | |
524 | msec_delay(2); | |
525 | break; | |
526 | case e1000_82541: | |
527 | case e1000_82541_rev_2: | |
528 | case e1000_82547: | |
529 | case e1000_82547_rev_2: | |
530 | /* Wait for EEPROM reload */ | |
531 | msec_delay(20); | |
532 | break; | |
2d7edb92 MC |
533 | case e1000_82573: |
534 | udelay(10); | |
535 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
536 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
537 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
538 | E1000_WRITE_FLUSH(hw); | |
539 | /* fall through */ | |
868d5309 MC |
540 | case e1000_82571: |
541 | case e1000_82572: | |
2d7edb92 MC |
542 | ret_val = e1000_get_auto_rd_done(hw); |
543 | if(ret_val) | |
544 | /* We don't want to continue accessing MAC registers. */ | |
545 | return ret_val; | |
546 | break; | |
1da177e4 LT |
547 | default: |
548 | /* Wait for EEPROM reload (it happens automatically) */ | |
549 | msec_delay(5); | |
550 | break; | |
551 | } | |
552 | ||
553 | /* Disable HW ARPs on ASF enabled adapters */ | |
2d7edb92 | 554 | if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
1da177e4 LT |
555 | manc = E1000_READ_REG(hw, MANC); |
556 | manc &= ~(E1000_MANC_ARP_EN); | |
557 | E1000_WRITE_REG(hw, MANC, manc); | |
558 | } | |
559 | ||
560 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
561 | e1000_phy_init_script(hw); | |
562 | ||
563 | /* Configure activity LED after PHY reset */ | |
564 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
565 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
566 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
567 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
568 | } | |
569 | ||
570 | /* Clear interrupt mask to stop board from generating interrupts */ | |
571 | DEBUGOUT("Masking off all interrupts\n"); | |
572 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
573 | ||
574 | /* Clear any pending interrupt events. */ | |
575 | icr = E1000_READ_REG(hw, ICR); | |
576 | ||
577 | /* If MWI was previously enabled, reenable it. */ | |
578 | if(hw->mac_type == e1000_82542_rev2_0) { | |
579 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | |
580 | e1000_pci_set_mwi(hw); | |
581 | } | |
582 | ||
583 | return E1000_SUCCESS; | |
584 | } | |
585 | ||
586 | /****************************************************************************** | |
587 | * Performs basic configuration of the adapter. | |
588 | * | |
589 | * hw - Struct containing variables accessed by shared code | |
590 | * | |
591 | * Assumes that the controller has previously been reset and is in a | |
592 | * post-reset uninitialized state. Initializes the receive address registers, | |
593 | * multicast table, and VLAN filter table. Calls routines to setup link | |
594 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
595 | * the transmit and receive units disabled and uninitialized. | |
596 | *****************************************************************************/ | |
597 | int32_t | |
598 | e1000_init_hw(struct e1000_hw *hw) | |
599 | { | |
600 | uint32_t ctrl; | |
601 | uint32_t i; | |
602 | int32_t ret_val; | |
603 | uint16_t pcix_cmd_word; | |
604 | uint16_t pcix_stat_hi_word; | |
605 | uint16_t cmd_mmrbc; | |
606 | uint16_t stat_mmrbc; | |
2d7edb92 MC |
607 | uint32_t mta_size; |
608 | ||
1da177e4 LT |
609 | DEBUGFUNC("e1000_init_hw"); |
610 | ||
611 | /* Initialize Identification LED */ | |
612 | ret_val = e1000_id_led_init(hw); | |
613 | if(ret_val) { | |
614 | DEBUGOUT("Error Initializing Identification LED\n"); | |
615 | return ret_val; | |
616 | } | |
617 | ||
618 | /* Set the media type and TBI compatibility */ | |
619 | e1000_set_media_type(hw); | |
620 | ||
621 | /* Disabling VLAN filtering. */ | |
622 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
2d7edb92 MC |
623 | if (hw->mac_type < e1000_82545_rev_3) |
624 | E1000_WRITE_REG(hw, VET, 0); | |
1da177e4 LT |
625 | e1000_clear_vfta(hw); |
626 | ||
627 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
628 | if(hw->mac_type == e1000_82542_rev2_0) { | |
629 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
630 | e1000_pci_clear_mwi(hw); | |
631 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); | |
632 | E1000_WRITE_FLUSH(hw); | |
633 | msec_delay(5); | |
634 | } | |
635 | ||
636 | /* Setup the receive address. This involves initializing all of the Receive | |
637 | * Address Registers (RARs 0 - 15). | |
638 | */ | |
639 | e1000_init_rx_addrs(hw); | |
640 | ||
641 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
642 | if(hw->mac_type == e1000_82542_rev2_0) { | |
643 | E1000_WRITE_REG(hw, RCTL, 0); | |
644 | E1000_WRITE_FLUSH(hw); | |
645 | msec_delay(1); | |
646 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | |
647 | e1000_pci_set_mwi(hw); | |
648 | } | |
649 | ||
650 | /* Zero out the Multicast HASH table */ | |
651 | DEBUGOUT("Zeroing the MTA\n"); | |
2d7edb92 MC |
652 | mta_size = E1000_MC_TBL_SIZE; |
653 | for(i = 0; i < mta_size; i++) | |
1da177e4 LT |
654 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
655 | ||
656 | /* Set the PCI priority bit correctly in the CTRL register. This | |
657 | * determines if the adapter gives priority to receives, or if it | |
2d7edb92 MC |
658 | * gives equal priority to transmits and receives. Valid only on |
659 | * 82542 and 82543 silicon. | |
1da177e4 | 660 | */ |
2d7edb92 | 661 | if(hw->dma_fairness && hw->mac_type <= e1000_82543) { |
1da177e4 LT |
662 | ctrl = E1000_READ_REG(hw, CTRL); |
663 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); | |
664 | } | |
665 | ||
666 | switch(hw->mac_type) { | |
667 | case e1000_82545_rev_3: | |
668 | case e1000_82546_rev_3: | |
669 | break; | |
670 | default: | |
671 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ | |
672 | if(hw->bus_type == e1000_bus_type_pcix) { | |
673 | e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); | |
674 | e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, | |
675 | &pcix_stat_hi_word); | |
676 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> | |
677 | PCIX_COMMAND_MMRBC_SHIFT; | |
678 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> | |
679 | PCIX_STATUS_HI_MMRBC_SHIFT; | |
680 | if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) | |
681 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; | |
682 | if(cmd_mmrbc > stat_mmrbc) { | |
683 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; | |
684 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; | |
685 | e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, | |
686 | &pcix_cmd_word); | |
687 | } | |
688 | } | |
689 | break; | |
690 | } | |
691 | ||
692 | /* Call a subroutine to configure the link and setup flow control. */ | |
693 | ret_val = e1000_setup_link(hw); | |
694 | ||
695 | /* Set the transmit descriptor write-back policy */ | |
696 | if(hw->mac_type > e1000_82544) { | |
697 | ctrl = E1000_READ_REG(hw, TXDCTL); | |
698 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2d7edb92 MC |
699 | switch (hw->mac_type) { |
700 | default: | |
701 | break; | |
868d5309 MC |
702 | case e1000_82571: |
703 | case e1000_82572: | |
704 | ctrl |= (1 << 22); | |
2d7edb92 MC |
705 | case e1000_82573: |
706 | ctrl |= E1000_TXDCTL_COUNT_DESC; | |
707 | break; | |
708 | } | |
1da177e4 LT |
709 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
710 | } | |
711 | ||
2d7edb92 MC |
712 | if (hw->mac_type == e1000_82573) { |
713 | e1000_enable_tx_pkt_filtering(hw); | |
714 | } | |
715 | ||
868d5309 MC |
716 | switch (hw->mac_type) { |
717 | default: | |
718 | break; | |
719 | case e1000_82571: | |
720 | ctrl = E1000_READ_REG(hw, TXDCTL1); | |
721 | ctrl &= ~E1000_TXDCTL_WTHRESH; | |
722 | ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB; | |
723 | ctrl |= (1 << 22); | |
724 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); | |
725 | break; | |
726 | } | |
727 | ||
728 | ||
729 | ||
730 | if (hw->mac_type == e1000_82573) { | |
731 | uint32_t gcr = E1000_READ_REG(hw, GCR); | |
732 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
733 | E1000_WRITE_REG(hw, GCR, gcr); | |
734 | } | |
2d7edb92 | 735 | |
1da177e4 LT |
736 | /* Clear all of the statistics registers (clear on read). It is |
737 | * important that we do this after we have tried to establish link | |
738 | * because the symbol error count will increment wildly if there | |
739 | * is no link. | |
740 | */ | |
741 | e1000_clear_hw_cntrs(hw); | |
742 | ||
743 | return ret_val; | |
744 | } | |
745 | ||
746 | /****************************************************************************** | |
747 | * Adjust SERDES output amplitude based on EEPROM setting. | |
748 | * | |
749 | * hw - Struct containing variables accessed by shared code. | |
750 | *****************************************************************************/ | |
751 | static int32_t | |
752 | e1000_adjust_serdes_amplitude(struct e1000_hw *hw) | |
753 | { | |
754 | uint16_t eeprom_data; | |
755 | int32_t ret_val; | |
756 | ||
757 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); | |
758 | ||
759 | if(hw->media_type != e1000_media_type_internal_serdes) | |
760 | return E1000_SUCCESS; | |
761 | ||
762 | switch(hw->mac_type) { | |
763 | case e1000_82545_rev_3: | |
764 | case e1000_82546_rev_3: | |
765 | break; | |
766 | default: | |
767 | return E1000_SUCCESS; | |
768 | } | |
769 | ||
770 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); | |
771 | if (ret_val) { | |
772 | return ret_val; | |
773 | } | |
774 | ||
775 | if(eeprom_data != EEPROM_RESERVED_WORD) { | |
776 | /* Adjust SERDES output amplitude only. */ | |
777 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; | |
778 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); | |
779 | if(ret_val) | |
780 | return ret_val; | |
781 | } | |
782 | ||
783 | return E1000_SUCCESS; | |
784 | } | |
785 | ||
786 | /****************************************************************************** | |
787 | * Configures flow control and link settings. | |
788 | * | |
789 | * hw - Struct containing variables accessed by shared code | |
790 | * | |
791 | * Determines which flow control settings to use. Calls the apropriate media- | |
792 | * specific link configuration function. Configures the flow control settings. | |
793 | * Assuming the adapter has a valid link partner, a valid link should be | |
794 | * established. Assumes the hardware has previously been reset and the | |
795 | * transmitter and receiver are not enabled. | |
796 | *****************************************************************************/ | |
797 | int32_t | |
798 | e1000_setup_link(struct e1000_hw *hw) | |
799 | { | |
800 | uint32_t ctrl_ext; | |
801 | int32_t ret_val; | |
802 | uint16_t eeprom_data; | |
803 | ||
804 | DEBUGFUNC("e1000_setup_link"); | |
805 | ||
806 | /* Read and store word 0x0F of the EEPROM. This word contains bits | |
807 | * that determine the hardware's default PAUSE (flow control) mode, | |
808 | * a bit that determines whether the HW defaults to enabling or | |
809 | * disabling auto-negotiation, and the direction of the | |
810 | * SW defined pins. If there is no SW over-ride of the flow | |
811 | * control setting, then the variable hw->fc will | |
812 | * be initialized based on a value in the EEPROM. | |
813 | */ | |
2d7edb92 | 814 | if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) { |
1da177e4 LT |
815 | DEBUGOUT("EEPROM Read Error\n"); |
816 | return -E1000_ERR_EEPROM; | |
817 | } | |
818 | ||
819 | if(hw->fc == e1000_fc_default) { | |
820 | if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) | |
821 | hw->fc = e1000_fc_none; | |
822 | else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == | |
823 | EEPROM_WORD0F_ASM_DIR) | |
824 | hw->fc = e1000_fc_tx_pause; | |
825 | else | |
826 | hw->fc = e1000_fc_full; | |
827 | } | |
828 | ||
829 | /* We want to save off the original Flow Control configuration just | |
830 | * in case we get disconnected and then reconnected into a different | |
831 | * hub or switch with different Flow Control capabilities. | |
832 | */ | |
833 | if(hw->mac_type == e1000_82542_rev2_0) | |
834 | hw->fc &= (~e1000_fc_tx_pause); | |
835 | ||
836 | if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) | |
837 | hw->fc &= (~e1000_fc_rx_pause); | |
838 | ||
839 | hw->original_fc = hw->fc; | |
840 | ||
841 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | |
842 | ||
843 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial | |
844 | * polarity value for the SW controlled pins, and setup the | |
845 | * Extended Device Control reg with that info. | |
846 | * This is needed because one of the SW controlled pins is used for | |
847 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
848 | * or e1000_phy_setup() is called. | |
849 | */ | |
850 | if(hw->mac_type == e1000_82543) { | |
851 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << | |
852 | SWDPIO__EXT_SHIFT); | |
853 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
854 | } | |
855 | ||
856 | /* Call the necessary subroutine to configure the link. */ | |
857 | ret_val = (hw->media_type == e1000_media_type_copper) ? | |
858 | e1000_setup_copper_link(hw) : | |
859 | e1000_setup_fiber_serdes_link(hw); | |
860 | ||
861 | /* Initialize the flow control address, type, and PAUSE timer | |
862 | * registers to their default values. This is done even if flow | |
863 | * control is disabled, because it does not hurt anything to | |
864 | * initialize these registers. | |
865 | */ | |
866 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | |
867 | ||
868 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
869 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
870 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | |
2d7edb92 | 871 | |
1da177e4 LT |
872 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
873 | ||
874 | /* Set the flow control receive threshold registers. Normally, | |
875 | * these registers will be set to a default threshold that may be | |
876 | * adjusted later by the driver's runtime code. However, if the | |
877 | * ability to transmit pause frames in not enabled, then these | |
878 | * registers will be set to 0. | |
879 | */ | |
880 | if(!(hw->fc & e1000_fc_tx_pause)) { | |
881 | E1000_WRITE_REG(hw, FCRTL, 0); | |
882 | E1000_WRITE_REG(hw, FCRTH, 0); | |
883 | } else { | |
884 | /* We need to set up the Receive Threshold high and low water marks | |
885 | * as well as (optionally) enabling the transmission of XON frames. | |
886 | */ | |
887 | if(hw->fc_send_xon) { | |
888 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); | |
889 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
890 | } else { | |
891 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); | |
892 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
893 | } | |
894 | } | |
895 | return ret_val; | |
896 | } | |
897 | ||
898 | /****************************************************************************** | |
899 | * Sets up link for a fiber based or serdes based adapter | |
900 | * | |
901 | * hw - Struct containing variables accessed by shared code | |
902 | * | |
903 | * Manipulates Physical Coding Sublayer functions in order to configure | |
904 | * link. Assumes the hardware has been previously reset and the transmitter | |
905 | * and receiver are not enabled. | |
906 | *****************************************************************************/ | |
907 | static int32_t | |
908 | e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |
909 | { | |
910 | uint32_t ctrl; | |
911 | uint32_t status; | |
912 | uint32_t txcw = 0; | |
913 | uint32_t i; | |
914 | uint32_t signal = 0; | |
915 | int32_t ret_val; | |
916 | ||
917 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); | |
918 | ||
868d5309 MC |
919 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
920 | * until explicitly turned off or a power cycle is performed. A read to | |
921 | * the register does not indicate its status. Therefore, we ensure | |
922 | * loopback mode is disabled during initialization. | |
923 | */ | |
924 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) | |
925 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); | |
926 | ||
1da177e4 LT |
927 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
928 | * set when the optics detect a signal. On older adapters, it will be | |
929 | * cleared when there is a signal. This applies to fiber media only. | |
930 | * If we're on serdes media, adjust the output amplitude to value set in | |
931 | * the EEPROM. | |
932 | */ | |
933 | ctrl = E1000_READ_REG(hw, CTRL); | |
934 | if(hw->media_type == e1000_media_type_fiber) | |
935 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | |
936 | ||
937 | ret_val = e1000_adjust_serdes_amplitude(hw); | |
938 | if(ret_val) | |
939 | return ret_val; | |
940 | ||
941 | /* Take the link out of reset */ | |
942 | ctrl &= ~(E1000_CTRL_LRST); | |
943 | ||
944 | /* Adjust VCO speed to improve BER performance */ | |
945 | ret_val = e1000_set_vco_speed(hw); | |
946 | if(ret_val) | |
947 | return ret_val; | |
948 | ||
949 | e1000_config_collision_dist(hw); | |
950 | ||
951 | /* Check for a software override of the flow control settings, and setup | |
952 | * the device accordingly. If auto-negotiation is enabled, then software | |
953 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
954 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
955 | * auto-negotiation is disabled, then software will have to manually | |
956 | * configure the two flow control enable bits in the CTRL register. | |
957 | * | |
958 | * The possible values of the "fc" parameter are: | |
959 | * 0: Flow control is completely disabled | |
960 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
961 | * not send pause frames). | |
962 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
963 | * not support receiving pause frames). | |
964 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
965 | */ | |
966 | switch (hw->fc) { | |
967 | case e1000_fc_none: | |
968 | /* Flow control is completely disabled by a software over-ride. */ | |
969 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
970 | break; | |
971 | case e1000_fc_rx_pause: | |
972 | /* RX Flow control is enabled and TX Flow control is disabled by a | |
973 | * software over-ride. Since there really isn't a way to advertise | |
974 | * that we are capable of RX Pause ONLY, we will advertise that we | |
975 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
976 | * disable the adapter's ability to send PAUSE frames. | |
977 | */ | |
978 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
979 | break; | |
980 | case e1000_fc_tx_pause: | |
981 | /* TX Flow control is enabled, and RX Flow control is disabled, by a | |
982 | * software over-ride. | |
983 | */ | |
984 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
985 | break; | |
986 | case e1000_fc_full: | |
987 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ | |
988 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
989 | break; | |
990 | default: | |
991 | DEBUGOUT("Flow control param set incorrectly\n"); | |
992 | return -E1000_ERR_CONFIG; | |
993 | break; | |
994 | } | |
995 | ||
996 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
997 | * will be in reset, because we previously reset the chip). This will | |
998 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
999 | * link-up status bit will be set and the flow control enable bits (RFCE | |
1000 | * and TFCE) will be set according to their negotiated value. | |
1001 | */ | |
1002 | DEBUGOUT("Auto-negotiation enabled\n"); | |
1003 | ||
1004 | E1000_WRITE_REG(hw, TXCW, txcw); | |
1005 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1006 | E1000_WRITE_FLUSH(hw); | |
1007 | ||
1008 | hw->txcw = txcw; | |
1009 | msec_delay(1); | |
1010 | ||
1011 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
1012 | * indication in the Device Status Register. Time-out if a link isn't | |
1013 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
1014 | * less than 500 milliseconds even if the other end is doing it in SW). | |
1015 | * For internal serdes, we just assume a signal is present, then poll. | |
1016 | */ | |
1017 | if(hw->media_type == e1000_media_type_internal_serdes || | |
1018 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { | |
1019 | DEBUGOUT("Looking for Link\n"); | |
1020 | for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | |
1021 | msec_delay(10); | |
1022 | status = E1000_READ_REG(hw, STATUS); | |
1023 | if(status & E1000_STATUS_LU) break; | |
1024 | } | |
1025 | if(i == (LINK_UP_TIMEOUT / 10)) { | |
1026 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | |
1027 | hw->autoneg_failed = 1; | |
1028 | /* AutoNeg failed to achieve a link, so we'll call | |
1029 | * e1000_check_for_link. This routine will force the link up if | |
1030 | * we detect a signal. This will allow us to communicate with | |
1031 | * non-autonegotiating link partners. | |
1032 | */ | |
1033 | ret_val = e1000_check_for_link(hw); | |
1034 | if(ret_val) { | |
1035 | DEBUGOUT("Error while checking for link\n"); | |
1036 | return ret_val; | |
1037 | } | |
1038 | hw->autoneg_failed = 0; | |
1039 | } else { | |
1040 | hw->autoneg_failed = 0; | |
1041 | DEBUGOUT("Valid Link Found\n"); | |
1042 | } | |
1043 | } else { | |
1044 | DEBUGOUT("No Signal Detected\n"); | |
1045 | } | |
1046 | return E1000_SUCCESS; | |
1047 | } | |
1048 | ||
1049 | /****************************************************************************** | |
2d7edb92 | 1050 | * Make sure we have a valid PHY and change PHY mode before link setup. |
1da177e4 LT |
1051 | * |
1052 | * hw - Struct containing variables accessed by shared code | |
1053 | ******************************************************************************/ | |
1054 | static int32_t | |
2d7edb92 | 1055 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
1da177e4 LT |
1056 | { |
1057 | uint32_t ctrl; | |
1da177e4 | 1058 | int32_t ret_val; |
1da177e4 LT |
1059 | uint16_t phy_data; |
1060 | ||
2d7edb92 | 1061 | DEBUGFUNC("e1000_copper_link_preconfig"); |
1da177e4 LT |
1062 | |
1063 | ctrl = E1000_READ_REG(hw, CTRL); | |
1064 | /* With 82543, we need to force speed and duplex on the MAC equal to what | |
1065 | * the PHY speed and duplex configuration is. In addition, we need to | |
1066 | * perform a hardware reset on the PHY to take it out of reset. | |
1067 | */ | |
1068 | if(hw->mac_type > e1000_82543) { | |
1069 | ctrl |= E1000_CTRL_SLU; | |
1070 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1071 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1072 | } else { | |
1073 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | |
1074 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2d7edb92 MC |
1075 | ret_val = e1000_phy_hw_reset(hw); |
1076 | if(ret_val) | |
1077 | return ret_val; | |
1da177e4 LT |
1078 | } |
1079 | ||
1080 | /* Make sure we have a valid PHY */ | |
1081 | ret_val = e1000_detect_gig_phy(hw); | |
1082 | if(ret_val) { | |
1083 | DEBUGOUT("Error, did not detect valid phy.\n"); | |
1084 | return ret_val; | |
1085 | } | |
1086 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); | |
1087 | ||
1088 | /* Set PHY to class A mode (if necessary) */ | |
1089 | ret_val = e1000_set_phy_mode(hw); | |
1090 | if(ret_val) | |
1091 | return ret_val; | |
1092 | ||
1093 | if((hw->mac_type == e1000_82545_rev_3) || | |
1094 | (hw->mac_type == e1000_82546_rev_3)) { | |
1095 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1096 | phy_data |= 0x00000008; | |
1097 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1098 | } | |
1099 | ||
1100 | if(hw->mac_type <= e1000_82543 || | |
1101 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
1102 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | |
1103 | hw->phy_reset_disable = FALSE; | |
1104 | ||
2d7edb92 MC |
1105 | return E1000_SUCCESS; |
1106 | } | |
1da177e4 | 1107 | |
1da177e4 | 1108 | |
2d7edb92 MC |
1109 | /******************************************************************** |
1110 | * Copper link setup for e1000_phy_igp series. | |
1111 | * | |
1112 | * hw - Struct containing variables accessed by shared code | |
1113 | *********************************************************************/ | |
1114 | static int32_t | |
1115 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | |
1116 | { | |
1117 | uint32_t led_ctrl; | |
1118 | int32_t ret_val; | |
1119 | uint16_t phy_data; | |
1da177e4 | 1120 | |
2d7edb92 | 1121 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
1da177e4 | 1122 | |
2d7edb92 MC |
1123 | if (hw->phy_reset_disable) |
1124 | return E1000_SUCCESS; | |
1125 | ||
1126 | ret_val = e1000_phy_reset(hw); | |
1127 | if (ret_val) { | |
1128 | DEBUGOUT("Error Resetting the PHY\n"); | |
1129 | return ret_val; | |
1130 | } | |
1da177e4 | 1131 | |
2d7edb92 MC |
1132 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
1133 | msec_delay(15); | |
1da177e4 | 1134 | |
2d7edb92 MC |
1135 | /* Configure activity LED after PHY reset */ |
1136 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
1137 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1138 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1139 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
1da177e4 | 1140 | |
2d7edb92 MC |
1141 | /* disable lplu d3 during driver init */ |
1142 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); | |
1143 | if (ret_val) { | |
1144 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
1145 | return ret_val; | |
1146 | } | |
1da177e4 | 1147 | |
2d7edb92 MC |
1148 | /* disable lplu d0 during driver init */ |
1149 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); | |
1150 | if (ret_val) { | |
1151 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
1152 | return ret_val; | |
1153 | } | |
1154 | /* Configure mdi-mdix settings */ | |
1155 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1156 | if (ret_val) | |
1157 | return ret_val; | |
1da177e4 | 1158 | |
2d7edb92 MC |
1159 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1160 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
1161 | /* Force MDI for earlier revs of the IGP PHY */ | |
1162 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
1163 | hw->mdix = 1; | |
1da177e4 | 1164 | |
2d7edb92 MC |
1165 | } else { |
1166 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1167 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1da177e4 | 1168 | |
2d7edb92 MC |
1169 | switch (hw->mdix) { |
1170 | case 1: | |
1171 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1172 | break; | |
1173 | case 2: | |
1174 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1175 | break; | |
1176 | case 0: | |
1177 | default: | |
1178 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
1179 | break; | |
1180 | } | |
1181 | } | |
1182 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1183 | if(ret_val) | |
1184 | return ret_val; | |
1da177e4 | 1185 | |
2d7edb92 MC |
1186 | /* set auto-master slave resolution settings */ |
1187 | if(hw->autoneg) { | |
1188 | e1000_ms_type phy_ms_setting = hw->master_slave; | |
1da177e4 | 1189 | |
2d7edb92 MC |
1190 | if(hw->ffe_config_state == e1000_ffe_config_active) |
1191 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
1da177e4 | 1192 | |
2d7edb92 MC |
1193 | if(hw->dsp_config_state == e1000_dsp_config_activated) |
1194 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1da177e4 | 1195 | |
2d7edb92 MC |
1196 | /* when autonegotiation advertisment is only 1000Mbps then we |
1197 | * should disable SmartSpeed and enable Auto MasterSlave | |
1198 | * resolution as hardware default. */ | |
1199 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { | |
1200 | /* Disable SmartSpeed */ | |
1201 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
1da177e4 LT |
1202 | if(ret_val) |
1203 | return ret_val; | |
2d7edb92 MC |
1204 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
1205 | ret_val = e1000_write_phy_reg(hw, | |
1206 | IGP01E1000_PHY_PORT_CONFIG, | |
1207 | phy_data); | |
1da177e4 LT |
1208 | if(ret_val) |
1209 | return ret_val; | |
2d7edb92 MC |
1210 | /* Set auto Master/Slave resolution process */ |
1211 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
1212 | if(ret_val) | |
1213 | return ret_val; | |
1214 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1215 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
1216 | if(ret_val) | |
1217 | return ret_val; | |
1218 | } | |
1da177e4 | 1219 | |
2d7edb92 MC |
1220 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1221 | if(ret_val) | |
1222 | return ret_val; | |
1da177e4 | 1223 | |
2d7edb92 MC |
1224 | /* load defaults for future use */ |
1225 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
1226 | ((phy_data & CR_1000T_MS_VALUE) ? | |
1227 | e1000_ms_force_master : | |
1228 | e1000_ms_force_slave) : | |
1229 | e1000_ms_auto; | |
1da177e4 | 1230 | |
2d7edb92 MC |
1231 | switch (phy_ms_setting) { |
1232 | case e1000_ms_force_master: | |
1233 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
1234 | break; | |
1235 | case e1000_ms_force_slave: | |
1236 | phy_data |= CR_1000T_MS_ENABLE; | |
1237 | phy_data &= ~(CR_1000T_MS_VALUE); | |
1238 | break; | |
1239 | case e1000_ms_auto: | |
1240 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1241 | default: | |
1242 | break; | |
1243 | } | |
1244 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
1245 | if(ret_val) | |
1246 | return ret_val; | |
2b02893e | 1247 | } |
1da177e4 | 1248 | |
2b02893e | 1249 | return E1000_SUCCESS; |
2d7edb92 | 1250 | } |
1da177e4 | 1251 | |
1da177e4 | 1252 | |
2d7edb92 MC |
1253 | /******************************************************************** |
1254 | * Copper link setup for e1000_phy_m88 series. | |
1255 | * | |
1256 | * hw - Struct containing variables accessed by shared code | |
1257 | *********************************************************************/ | |
1258 | static int32_t | |
1259 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | |
1260 | { | |
1261 | int32_t ret_val; | |
1262 | uint16_t phy_data; | |
1da177e4 | 1263 | |
2d7edb92 | 1264 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
1da177e4 | 1265 | |
2d7edb92 MC |
1266 | if(hw->phy_reset_disable) |
1267 | return E1000_SUCCESS; | |
1268 | ||
1269 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
1270 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1271 | if(ret_val) | |
1272 | return ret_val; | |
1da177e4 | 1273 | |
2d7edb92 | 1274 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
1da177e4 | 1275 | |
2d7edb92 MC |
1276 | /* Options: |
1277 | * MDI/MDI-X = 0 (default) | |
1278 | * 0 - Auto for all speeds | |
1279 | * 1 - MDI mode | |
1280 | * 2 - MDI-X mode | |
1281 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1282 | */ | |
1283 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1da177e4 | 1284 | |
2d7edb92 MC |
1285 | switch (hw->mdix) { |
1286 | case 1: | |
1287 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
1288 | break; | |
1289 | case 2: | |
1290 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
1291 | break; | |
1292 | case 3: | |
1293 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
1294 | break; | |
1295 | case 0: | |
1296 | default: | |
1297 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
1298 | break; | |
1299 | } | |
1300 | ||
1301 | /* Options: | |
1302 | * disable_polarity_correction = 0 (default) | |
1303 | * Automatic Correction for Reversed Cable Polarity | |
1304 | * 0 - Disabled | |
1305 | * 1 - Enabled | |
1da177e4 | 1306 | */ |
2d7edb92 MC |
1307 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
1308 | if(hw->disable_polarity_correction == 1) | |
1309 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
1310 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1da177e4 LT |
1311 | if(ret_val) |
1312 | return ret_val; | |
2d7edb92 MC |
1313 | |
1314 | /* Force TX_CLK in the Extended PHY Specific Control Register | |
1315 | * to 25MHz clock. | |
1316 | */ | |
1317 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1318 | if(ret_val) | |
1319 | return ret_val; | |
1320 | ||
1321 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1322 | ||
1323 | if (hw->phy_revision < M88E1011_I_REV_4) { | |
1324 | /* Configure Master and Slave downshift values */ | |
1325 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
1326 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
1327 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
1328 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
1329 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1da177e4 LT |
1330 | if(ret_val) |
1331 | return ret_val; | |
2d7edb92 | 1332 | } |
1da177e4 | 1333 | |
2d7edb92 MC |
1334 | /* SW Reset the PHY so all changes take effect */ |
1335 | ret_val = e1000_phy_reset(hw); | |
1336 | if(ret_val) { | |
1337 | DEBUGOUT("Error Resetting the PHY\n"); | |
1338 | return ret_val; | |
1da177e4 LT |
1339 | } |
1340 | ||
2d7edb92 | 1341 | return E1000_SUCCESS; |
1da177e4 LT |
1342 | } |
1343 | ||
2d7edb92 MC |
1344 | /******************************************************************** |
1345 | * Setup auto-negotiation and flow control advertisements, | |
1346 | * and then perform auto-negotiation. | |
1da177e4 LT |
1347 | * |
1348 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
1349 | *********************************************************************/ |
1350 | static int32_t | |
1351 | e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1da177e4 LT |
1352 | { |
1353 | int32_t ret_val; | |
2d7edb92 | 1354 | uint16_t phy_data; |
1da177e4 | 1355 | |
2d7edb92 | 1356 | DEBUGFUNC("e1000_copper_link_autoneg"); |
1da177e4 | 1357 | |
2d7edb92 MC |
1358 | /* Perform some bounds checking on the hw->autoneg_advertised |
1359 | * parameter. If this variable is zero, then set it to the default. | |
1360 | */ | |
1361 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1362 | ||
1363 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
1364 | * by the calling code so we set to advertise full capability. | |
1365 | */ | |
1366 | if(hw->autoneg_advertised == 0) | |
1367 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1368 | ||
1369 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); | |
1370 | ret_val = e1000_phy_setup_autoneg(hw); | |
1371 | if(ret_val) { | |
1372 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | |
1373 | return ret_val; | |
1374 | } | |
1375 | DEBUGOUT("Restarting Auto-Neg\n"); | |
1376 | ||
1377 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
1378 | * the Auto Neg Restart bit in the PHY control register. | |
1379 | */ | |
1380 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
1da177e4 LT |
1381 | if(ret_val) |
1382 | return ret_val; | |
1383 | ||
2d7edb92 MC |
1384 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
1385 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
1da177e4 LT |
1386 | if(ret_val) |
1387 | return ret_val; | |
1388 | ||
2d7edb92 MC |
1389 | /* Does the user want to wait for Auto-Neg to complete here, or |
1390 | * check at a later time (for example, callback routine). | |
1391 | */ | |
1392 | if(hw->wait_autoneg_complete) { | |
1393 | ret_val = e1000_wait_autoneg(hw); | |
1394 | if(ret_val) { | |
1395 | DEBUGOUT("Error while waiting for autoneg to complete\n"); | |
1396 | return ret_val; | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | hw->get_link_status = TRUE; | |
1401 | ||
1402 | return E1000_SUCCESS; | |
1403 | } | |
1404 | ||
1405 | ||
1406 | /****************************************************************************** | |
1407 | * Config the MAC and the PHY after link is up. | |
1408 | * 1) Set up the MAC to the current PHY speed/duplex | |
1409 | * if we are on 82543. If we | |
1410 | * are on newer silicon, we only need to configure | |
1411 | * collision distance in the Transmit Control Register. | |
1412 | * 2) Set up flow control on the MAC to that established with | |
1413 | * the link partner. | |
1414 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. | |
1415 | * | |
1416 | * hw - Struct containing variables accessed by shared code | |
1417 | ******************************************************************************/ | |
1418 | static int32_t | |
1419 | e1000_copper_link_postconfig(struct e1000_hw *hw) | |
1420 | { | |
1421 | int32_t ret_val; | |
1422 | DEBUGFUNC("e1000_copper_link_postconfig"); | |
1423 | ||
1424 | if(hw->mac_type >= e1000_82544) { | |
1425 | e1000_config_collision_dist(hw); | |
1426 | } else { | |
1427 | ret_val = e1000_config_mac_to_phy(hw); | |
1428 | if(ret_val) { | |
1429 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
1430 | return ret_val; | |
1431 | } | |
1432 | } | |
1433 | ret_val = e1000_config_fc_after_link_up(hw); | |
1434 | if(ret_val) { | |
1435 | DEBUGOUT("Error Configuring Flow Control\n"); | |
1436 | return ret_val; | |
1437 | } | |
1438 | ||
1439 | /* Config DSP to improve Giga link quality */ | |
1440 | if(hw->phy_type == e1000_phy_igp) { | |
1441 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); | |
1442 | if(ret_val) { | |
1443 | DEBUGOUT("Error Configuring DSP after link up\n"); | |
1444 | return ret_val; | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | return E1000_SUCCESS; | |
1449 | } | |
1450 | ||
1451 | /****************************************************************************** | |
1452 | * Detects which PHY is present and setup the speed and duplex | |
1453 | * | |
1454 | * hw - Struct containing variables accessed by shared code | |
1455 | ******************************************************************************/ | |
1456 | static int32_t | |
1457 | e1000_setup_copper_link(struct e1000_hw *hw) | |
1458 | { | |
1459 | int32_t ret_val; | |
1460 | uint16_t i; | |
1461 | uint16_t phy_data; | |
1462 | ||
1463 | DEBUGFUNC("e1000_setup_copper_link"); | |
1464 | ||
1465 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | |
1466 | ret_val = e1000_copper_link_preconfig(hw); | |
1467 | if(ret_val) | |
1468 | return ret_val; | |
1469 | ||
1470 | if (hw->phy_type == e1000_phy_igp || | |
1471 | hw->phy_type == e1000_phy_igp_2) { | |
1472 | ret_val = e1000_copper_link_igp_setup(hw); | |
1473 | if(ret_val) | |
1474 | return ret_val; | |
1475 | } else if (hw->phy_type == e1000_phy_m88) { | |
1476 | ret_val = e1000_copper_link_mgp_setup(hw); | |
1477 | if(ret_val) | |
1478 | return ret_val; | |
1479 | } | |
1480 | ||
1481 | if(hw->autoneg) { | |
1482 | /* Setup autoneg and flow control advertisement | |
1483 | * and perform autonegotiation */ | |
1484 | ret_val = e1000_copper_link_autoneg(hw); | |
1485 | if(ret_val) | |
1486 | return ret_val; | |
1487 | } else { | |
1488 | /* PHY will be set to 10H, 10F, 100H,or 100F | |
1489 | * depending on value from forced_speed_duplex. */ | |
1490 | DEBUGOUT("Forcing speed and duplex\n"); | |
1491 | ret_val = e1000_phy_force_speed_duplex(hw); | |
1492 | if(ret_val) { | |
1493 | DEBUGOUT("Error Forcing Speed and Duplex\n"); | |
1494 | return ret_val; | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | /* Check link status. Wait up to 100 microseconds for link to become | |
1499 | * valid. | |
1500 | */ | |
1501 | for(i = 0; i < 10; i++) { | |
1502 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
1503 | if(ret_val) | |
1504 | return ret_val; | |
1505 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
1506 | if(ret_val) | |
1507 | return ret_val; | |
1508 | ||
1509 | if(phy_data & MII_SR_LINK_STATUS) { | |
1510 | /* Config the MAC and PHY after link is up */ | |
1511 | ret_val = e1000_copper_link_postconfig(hw); | |
1512 | if(ret_val) | |
1513 | return ret_val; | |
1514 | ||
1515 | DEBUGOUT("Valid link established!!!\n"); | |
1516 | return E1000_SUCCESS; | |
1517 | } | |
1518 | udelay(10); | |
1519 | } | |
1520 | ||
1521 | DEBUGOUT("Unable to establish link!!!\n"); | |
1522 | return E1000_SUCCESS; | |
1523 | } | |
1524 | ||
1525 | /****************************************************************************** | |
1526 | * Configures PHY autoneg and flow control advertisement settings | |
1527 | * | |
1528 | * hw - Struct containing variables accessed by shared code | |
1529 | ******************************************************************************/ | |
1530 | int32_t | |
1531 | e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
1532 | { | |
1533 | int32_t ret_val; | |
1534 | uint16_t mii_autoneg_adv_reg; | |
1535 | uint16_t mii_1000t_ctrl_reg; | |
1536 | ||
1537 | DEBUGFUNC("e1000_phy_setup_autoneg"); | |
1538 | ||
1539 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
1540 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
1541 | if(ret_val) | |
1542 | return ret_val; | |
1543 | ||
1544 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
1545 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
1546 | if(ret_val) | |
1547 | return ret_val; | |
1548 | ||
1549 | /* Need to parse both autoneg_advertised and fc and set up | |
1550 | * the appropriate PHY registers. First we will parse for | |
1da177e4 LT |
1551 | * autoneg_advertised software override. Since we can advertise |
1552 | * a plethora of combinations, we need to check each bit | |
1553 | * individually. | |
1554 | */ | |
1555 | ||
1556 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
1557 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
1558 | * the 1000Base-T Control Register (Address 9). | |
1559 | */ | |
1560 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
1561 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
1562 | ||
1563 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); | |
1564 | ||
1565 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
1566 | if(hw->autoneg_advertised & ADVERTISE_10_HALF) { | |
1567 | DEBUGOUT("Advertise 10mb Half duplex\n"); | |
1568 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
1569 | } | |
1570 | ||
1571 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
1572 | if(hw->autoneg_advertised & ADVERTISE_10_FULL) { | |
1573 | DEBUGOUT("Advertise 10mb Full duplex\n"); | |
1574 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
1575 | } | |
1576 | ||
1577 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
1578 | if(hw->autoneg_advertised & ADVERTISE_100_HALF) { | |
1579 | DEBUGOUT("Advertise 100mb Half duplex\n"); | |
1580 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
1581 | } | |
1582 | ||
1583 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
1584 | if(hw->autoneg_advertised & ADVERTISE_100_FULL) { | |
1585 | DEBUGOUT("Advertise 100mb Full duplex\n"); | |
1586 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
1587 | } | |
1588 | ||
1589 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
1590 | if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { | |
1591 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); | |
1592 | } | |
1593 | ||
1594 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
1595 | if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { | |
1596 | DEBUGOUT("Advertise 1000mb Full duplex\n"); | |
1597 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
1598 | } | |
1599 | ||
1600 | /* Check for a software override of the flow control settings, and | |
1601 | * setup the PHY advertisement registers accordingly. If | |
1602 | * auto-negotiation is enabled, then software will have to set the | |
1603 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1604 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
1605 | * | |
1606 | * The possible values of the "fc" parameter are: | |
1607 | * 0: Flow control is completely disabled | |
1608 | * 1: Rx flow control is enabled (we can receive pause frames | |
1609 | * but not send pause frames). | |
1610 | * 2: Tx flow control is enabled (we can send pause frames | |
1611 | * but we do not support receiving pause frames). | |
1612 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1613 | * other: No software override. The flow control configuration | |
1614 | * in the EEPROM is used. | |
1615 | */ | |
1616 | switch (hw->fc) { | |
1617 | case e1000_fc_none: /* 0 */ | |
1618 | /* Flow control (RX & TX) is completely disabled by a | |
1619 | * software over-ride. | |
1620 | */ | |
1621 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1622 | break; | |
1623 | case e1000_fc_rx_pause: /* 1 */ | |
1624 | /* RX Flow control is enabled, and TX Flow control is | |
1625 | * disabled, by a software over-ride. | |
1626 | */ | |
1627 | /* Since there really isn't a way to advertise that we are | |
1628 | * capable of RX Pause ONLY, we will advertise that we | |
1629 | * support both symmetric and asymmetric RX PAUSE. Later | |
1630 | * (in e1000_config_fc_after_link_up) we will disable the | |
1631 | *hw's ability to send PAUSE frames. | |
1632 | */ | |
1633 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1634 | break; | |
1635 | case e1000_fc_tx_pause: /* 2 */ | |
1636 | /* TX Flow control is enabled, and RX Flow control is | |
1637 | * disabled, by a software over-ride. | |
1638 | */ | |
1639 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1640 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1641 | break; | |
1642 | case e1000_fc_full: /* 3 */ | |
1643 | /* Flow control (both RX and TX) is enabled by a software | |
1644 | * over-ride. | |
1645 | */ | |
1646 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1647 | break; | |
1648 | default: | |
1649 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1650 | return -E1000_ERR_CONFIG; | |
1651 | } | |
1652 | ||
1653 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1654 | if(ret_val) | |
1655 | return ret_val; | |
1656 | ||
1657 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
1658 | ||
2d7edb92 | 1659 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
1da177e4 LT |
1660 | if(ret_val) |
1661 | return ret_val; | |
1662 | ||
1663 | return E1000_SUCCESS; | |
1664 | } | |
1665 | ||
1666 | /****************************************************************************** | |
1667 | * Force PHY speed and duplex settings to hw->forced_speed_duplex | |
1668 | * | |
1669 | * hw - Struct containing variables accessed by shared code | |
1670 | ******************************************************************************/ | |
1671 | static int32_t | |
1672 | e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
1673 | { | |
1674 | uint32_t ctrl; | |
1675 | int32_t ret_val; | |
1676 | uint16_t mii_ctrl_reg; | |
1677 | uint16_t mii_status_reg; | |
1678 | uint16_t phy_data; | |
1679 | uint16_t i; | |
1680 | ||
1681 | DEBUGFUNC("e1000_phy_force_speed_duplex"); | |
1682 | ||
1683 | /* Turn off Flow control if we are forcing speed and duplex. */ | |
1684 | hw->fc = e1000_fc_none; | |
1685 | ||
1686 | DEBUGOUT1("hw->fc = %d\n", hw->fc); | |
1687 | ||
1688 | /* Read the Device Control Register. */ | |
1689 | ctrl = E1000_READ_REG(hw, CTRL); | |
1690 | ||
1691 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ | |
1692 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1693 | ctrl &= ~(DEVICE_SPEED_MASK); | |
1694 | ||
1695 | /* Clear the Auto Speed Detect Enable bit. */ | |
1696 | ctrl &= ~E1000_CTRL_ASDE; | |
1697 | ||
1698 | /* Read the MII Control Register. */ | |
1699 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); | |
1700 | if(ret_val) | |
1701 | return ret_val; | |
1702 | ||
1703 | /* We need to disable autoneg in order to force link and duplex. */ | |
1704 | ||
1705 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; | |
1706 | ||
1707 | /* Are we forcing Full or Half Duplex? */ | |
1708 | if(hw->forced_speed_duplex == e1000_100_full || | |
1709 | hw->forced_speed_duplex == e1000_10_full) { | |
1710 | /* We want to force full duplex so we SET the full duplex bits in the | |
1711 | * Device and MII Control Registers. | |
1712 | */ | |
1713 | ctrl |= E1000_CTRL_FD; | |
1714 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; | |
1715 | DEBUGOUT("Full Duplex\n"); | |
1716 | } else { | |
1717 | /* We want to force half duplex so we CLEAR the full duplex bits in | |
1718 | * the Device and MII Control Registers. | |
1719 | */ | |
1720 | ctrl &= ~E1000_CTRL_FD; | |
1721 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; | |
1722 | DEBUGOUT("Half Duplex\n"); | |
1723 | } | |
1724 | ||
1725 | /* Are we forcing 100Mbps??? */ | |
1726 | if(hw->forced_speed_duplex == e1000_100_full || | |
1727 | hw->forced_speed_duplex == e1000_100_half) { | |
1728 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ | |
1729 | ctrl |= E1000_CTRL_SPD_100; | |
1730 | mii_ctrl_reg |= MII_CR_SPEED_100; | |
1731 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
1732 | DEBUGOUT("Forcing 100mb "); | |
1733 | } else { | |
1734 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ | |
1735 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1736 | mii_ctrl_reg |= MII_CR_SPEED_10; | |
1737 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
1738 | DEBUGOUT("Forcing 10mb "); | |
1739 | } | |
1740 | ||
1741 | e1000_config_collision_dist(hw); | |
1742 | ||
1743 | /* Write the configured values back to the Device Control Reg. */ | |
1744 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1745 | ||
1746 | if (hw->phy_type == e1000_phy_m88) { | |
1747 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1748 | if(ret_val) | |
1749 | return ret_val; | |
1750 | ||
1751 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
1752 | * forced whenever speed are duplex are forced. | |
1753 | */ | |
1754 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1755 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1756 | if(ret_val) | |
1757 | return ret_val; | |
1758 | ||
1759 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | |
1760 | ||
1761 | /* Need to reset the PHY or these changes will be ignored */ | |
1762 | mii_ctrl_reg |= MII_CR_RESET; | |
1763 | } else { | |
1764 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
1765 | * forced whenever speed or duplex are forced. | |
1766 | */ | |
1767 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1768 | if(ret_val) | |
1769 | return ret_val; | |
1770 | ||
1771 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1772 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1773 | ||
1774 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1775 | if(ret_val) | |
1776 | return ret_val; | |
1777 | } | |
1778 | ||
1779 | /* Write back the modified PHY MII control register. */ | |
1780 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); | |
1781 | if(ret_val) | |
1782 | return ret_val; | |
1783 | ||
1784 | udelay(1); | |
1785 | ||
1786 | /* The wait_autoneg_complete flag may be a little misleading here. | |
1787 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | |
1788 | * But we do want to delay for a period while forcing only so we | |
1789 | * don't generate false No Link messages. So we will wait here | |
1790 | * only if the user has set wait_autoneg_complete to 1, which is | |
1791 | * the default. | |
1792 | */ | |
1793 | if(hw->wait_autoneg_complete) { | |
1794 | /* We will wait for autoneg to complete. */ | |
1795 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); | |
1796 | mii_status_reg = 0; | |
1797 | ||
1798 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
1799 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
1800 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | |
1801 | * to be set. | |
1802 | */ | |
1803 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
1804 | if(ret_val) | |
1805 | return ret_val; | |
1806 | ||
1807 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
1808 | if(ret_val) | |
1809 | return ret_val; | |
1810 | ||
1811 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
1812 | msec_delay(100); | |
1813 | } | |
1814 | if((i == 0) && | |
1815 | (hw->phy_type == e1000_phy_m88)) { | |
1816 | /* We didn't get link. Reset the DSP and wait again for link. */ | |
1817 | ret_val = e1000_phy_reset_dsp(hw); | |
1818 | if(ret_val) { | |
1819 | DEBUGOUT("Error Resetting PHY DSP\n"); | |
1820 | return ret_val; | |
1821 | } | |
1822 | } | |
1823 | /* This loop will early-out if the link condition has been met. */ | |
1824 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
1825 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
1826 | msec_delay(100); | |
1827 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | |
1828 | * to be set. | |
1829 | */ | |
1830 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
1831 | if(ret_val) | |
1832 | return ret_val; | |
1833 | ||
1834 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
1835 | if(ret_val) | |
1836 | return ret_val; | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | if (hw->phy_type == e1000_phy_m88) { | |
1841 | /* Because we reset the PHY above, we need to re-force TX_CLK in the | |
1842 | * Extended PHY Specific Control Register to 25MHz clock. This value | |
1843 | * defaults back to a 2.5MHz clock when the PHY is reset. | |
1844 | */ | |
1845 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1846 | if(ret_val) | |
1847 | return ret_val; | |
1848 | ||
1849 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1850 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1851 | if(ret_val) | |
1852 | return ret_val; | |
1853 | ||
1854 | /* In addition, because of the s/w reset above, we need to enable CRS on | |
1855 | * TX. This must be set for both full and half duplex operation. | |
1856 | */ | |
1857 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1858 | if(ret_val) | |
1859 | return ret_val; | |
1860 | ||
1861 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1862 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1863 | if(ret_val) | |
1864 | return ret_val; | |
1865 | ||
1866 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | |
1867 | (!hw->autoneg) && | |
1868 | (hw->forced_speed_duplex == e1000_10_full || | |
1869 | hw->forced_speed_duplex == e1000_10_half)) { | |
1870 | ret_val = e1000_polarity_reversal_workaround(hw); | |
1871 | if(ret_val) | |
1872 | return ret_val; | |
1873 | } | |
1874 | } | |
1875 | return E1000_SUCCESS; | |
1876 | } | |
1877 | ||
1878 | /****************************************************************************** | |
1879 | * Sets the collision distance in the Transmit Control register | |
1880 | * | |
1881 | * hw - Struct containing variables accessed by shared code | |
1882 | * | |
1883 | * Link should have been established previously. Reads the speed and duplex | |
1884 | * information from the Device Status register. | |
1885 | ******************************************************************************/ | |
1886 | void | |
1887 | e1000_config_collision_dist(struct e1000_hw *hw) | |
1888 | { | |
1889 | uint32_t tctl; | |
1890 | ||
1891 | DEBUGFUNC("e1000_config_collision_dist"); | |
1892 | ||
1893 | tctl = E1000_READ_REG(hw, TCTL); | |
1894 | ||
1895 | tctl &= ~E1000_TCTL_COLD; | |
1896 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; | |
1897 | ||
1898 | E1000_WRITE_REG(hw, TCTL, tctl); | |
1899 | E1000_WRITE_FLUSH(hw); | |
1900 | } | |
1901 | ||
1902 | /****************************************************************************** | |
1903 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
1904 | * | |
1905 | * hw - Struct containing variables accessed by shared code | |
1906 | * mii_reg - data to write to the MII control register | |
1907 | * | |
1908 | * The contents of the PHY register containing the needed information need to | |
1909 | * be passed in. | |
1910 | ******************************************************************************/ | |
1911 | static int32_t | |
1912 | e1000_config_mac_to_phy(struct e1000_hw *hw) | |
1913 | { | |
1914 | uint32_t ctrl; | |
1915 | int32_t ret_val; | |
1916 | uint16_t phy_data; | |
1917 | ||
1918 | DEBUGFUNC("e1000_config_mac_to_phy"); | |
1919 | ||
2d7edb92 MC |
1920 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
1921 | * MAC speed/duplex configuration.*/ | |
1922 | if (hw->mac_type >= e1000_82544) | |
1923 | return E1000_SUCCESS; | |
1924 | ||
1da177e4 LT |
1925 | /* Read the Device Control Register and set the bits to Force Speed |
1926 | * and Duplex. | |
1927 | */ | |
1928 | ctrl = E1000_READ_REG(hw, CTRL); | |
1929 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1930 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); | |
1931 | ||
1932 | /* Set up duplex in the Device Control and Transmit Control | |
1933 | * registers depending on negotiated values. | |
1934 | */ | |
2d7edb92 MC |
1935 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
1936 | if(ret_val) | |
1937 | return ret_val; | |
1da177e4 | 1938 | |
2d7edb92 MC |
1939 | if(phy_data & M88E1000_PSSR_DPLX) |
1940 | ctrl |= E1000_CTRL_FD; | |
1941 | else | |
1942 | ctrl &= ~E1000_CTRL_FD; | |
1da177e4 | 1943 | |
2d7edb92 | 1944 | e1000_config_collision_dist(hw); |
1da177e4 | 1945 | |
2d7edb92 MC |
1946 | /* Set up speed in the Device Control register depending on |
1947 | * negotiated values. | |
1948 | */ | |
1949 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | |
1950 | ctrl |= E1000_CTRL_SPD_1000; | |
1951 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | |
1952 | ctrl |= E1000_CTRL_SPD_100; | |
1da177e4 | 1953 | |
1da177e4 LT |
1954 | /* Write the configured values back to the Device Control Reg. */ |
1955 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1956 | return E1000_SUCCESS; | |
1957 | } | |
1958 | ||
1959 | /****************************************************************************** | |
1960 | * Forces the MAC's flow control settings. | |
1961 | * | |
1962 | * hw - Struct containing variables accessed by shared code | |
1963 | * | |
1964 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
1965 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
1966 | * software when a Copper PHY is used because autonegotiation is managed | |
1967 | * by the PHY rather than the MAC. Software must also configure these | |
1968 | * bits when link is forced on a fiber connection. | |
1969 | *****************************************************************************/ | |
1970 | int32_t | |
1971 | e1000_force_mac_fc(struct e1000_hw *hw) | |
1972 | { | |
1973 | uint32_t ctrl; | |
1974 | ||
1975 | DEBUGFUNC("e1000_force_mac_fc"); | |
1976 | ||
1977 | /* Get the current configuration of the Device Control Register */ | |
1978 | ctrl = E1000_READ_REG(hw, CTRL); | |
1979 | ||
1980 | /* Because we didn't get link via the internal auto-negotiation | |
1981 | * mechanism (we either forced link or we got link via PHY | |
1982 | * auto-neg), we have to manually enable/disable transmit an | |
1983 | * receive flow control. | |
1984 | * | |
1985 | * The "Case" statement below enables/disable flow control | |
1986 | * according to the "hw->fc" parameter. | |
1987 | * | |
1988 | * The possible values of the "fc" parameter are: | |
1989 | * 0: Flow control is completely disabled | |
1990 | * 1: Rx flow control is enabled (we can receive pause | |
1991 | * frames but not send pause frames). | |
1992 | * 2: Tx flow control is enabled (we can send pause frames | |
1993 | * frames but we do not receive pause frames). | |
1994 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
1995 | * other: No other values should be possible at this point. | |
1996 | */ | |
1997 | ||
1998 | switch (hw->fc) { | |
1999 | case e1000_fc_none: | |
2000 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
2001 | break; | |
2002 | case e1000_fc_rx_pause: | |
2003 | ctrl &= (~E1000_CTRL_TFCE); | |
2004 | ctrl |= E1000_CTRL_RFCE; | |
2005 | break; | |
2006 | case e1000_fc_tx_pause: | |
2007 | ctrl &= (~E1000_CTRL_RFCE); | |
2008 | ctrl |= E1000_CTRL_TFCE; | |
2009 | break; | |
2010 | case e1000_fc_full: | |
2011 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
2012 | break; | |
2013 | default: | |
2014 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2015 | return -E1000_ERR_CONFIG; | |
2016 | } | |
2017 | ||
2018 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
2019 | if(hw->mac_type == e1000_82542_rev2_0) | |
2020 | ctrl &= (~E1000_CTRL_TFCE); | |
2021 | ||
2022 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2023 | return E1000_SUCCESS; | |
2024 | } | |
2025 | ||
2026 | /****************************************************************************** | |
2027 | * Configures flow control settings after link is established | |
2028 | * | |
2029 | * hw - Struct containing variables accessed by shared code | |
2030 | * | |
2031 | * Should be called immediately after a valid link has been established. | |
2032 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
2033 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
2034 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
2035 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
2036 | *****************************************************************************/ | |
2037 | int32_t | |
2038 | e1000_config_fc_after_link_up(struct e1000_hw *hw) | |
2039 | { | |
2040 | int32_t ret_val; | |
2041 | uint16_t mii_status_reg; | |
2042 | uint16_t mii_nway_adv_reg; | |
2043 | uint16_t mii_nway_lp_ability_reg; | |
2044 | uint16_t speed; | |
2045 | uint16_t duplex; | |
2046 | ||
2047 | DEBUGFUNC("e1000_config_fc_after_link_up"); | |
2048 | ||
2049 | /* Check for the case where we have fiber media and auto-neg failed | |
2050 | * so we had to force link. In this case, we need to force the | |
2051 | * configuration of the MAC to match the "fc" parameter. | |
2052 | */ | |
2053 | if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || | |
2054 | ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || | |
2055 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { | |
2056 | ret_val = e1000_force_mac_fc(hw); | |
2057 | if(ret_val) { | |
2058 | DEBUGOUT("Error forcing flow control settings\n"); | |
2059 | return ret_val; | |
2060 | } | |
2061 | } | |
2062 | ||
2063 | /* Check for the case where we have copper media and auto-neg is | |
2064 | * enabled. In this case, we need to check and see if Auto-Neg | |
2065 | * has completed, and if so, how the PHY and link partner has | |
2066 | * flow control configured. | |
2067 | */ | |
2068 | if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { | |
2069 | /* Read the MII Status Register and check to see if AutoNeg | |
2070 | * has completed. We read this twice because this reg has | |
2071 | * some "sticky" (latched) bits. | |
2072 | */ | |
2073 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2074 | if(ret_val) | |
2075 | return ret_val; | |
2076 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2077 | if(ret_val) | |
2078 | return ret_val; | |
2079 | ||
2080 | if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { | |
2081 | /* The AutoNeg process has completed, so we now need to | |
2082 | * read both the Auto Negotiation Advertisement Register | |
2083 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
2084 | * Register (Address 5) to determine how flow control was | |
2085 | * negotiated. | |
2086 | */ | |
2087 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, | |
2088 | &mii_nway_adv_reg); | |
2089 | if(ret_val) | |
2090 | return ret_val; | |
2091 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, | |
2092 | &mii_nway_lp_ability_reg); | |
2093 | if(ret_val) | |
2094 | return ret_val; | |
2095 | ||
2096 | /* Two bits in the Auto Negotiation Advertisement Register | |
2097 | * (Address 4) and two bits in the Auto Negotiation Base | |
2098 | * Page Ability Register (Address 5) determine flow control | |
2099 | * for both the PHY and the link partner. The following | |
2100 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
2101 | * 1999, describes these PAUSE resolution bits and how flow | |
2102 | * control is determined based upon these settings. | |
2103 | * NOTE: DC = Don't Care | |
2104 | * | |
2105 | * LOCAL DEVICE | LINK PARTNER | |
2106 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
2107 | *-------|---------|-------|---------|-------------------- | |
2108 | * 0 | 0 | DC | DC | e1000_fc_none | |
2109 | * 0 | 1 | 0 | DC | e1000_fc_none | |
2110 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
2111 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
2112 | * 1 | 0 | 0 | DC | e1000_fc_none | |
2113 | * 1 | DC | 1 | DC | e1000_fc_full | |
2114 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
2115 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
2116 | * | |
2117 | */ | |
2118 | /* Are both PAUSE bits set to 1? If so, this implies | |
2119 | * Symmetric Flow Control is enabled at both ends. The | |
2120 | * ASM_DIR bits are irrelevant per the spec. | |
2121 | * | |
2122 | * For Symmetric Flow Control: | |
2123 | * | |
2124 | * LOCAL DEVICE | LINK PARTNER | |
2125 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2126 | *-------|---------|-------|---------|-------------------- | |
2127 | * 1 | DC | 1 | DC | e1000_fc_full | |
2128 | * | |
2129 | */ | |
2130 | if((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2131 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
2132 | /* Now we need to check if the user selected RX ONLY | |
2133 | * of pause frames. In this case, we had to advertise | |
2134 | * FULL flow control because we could not advertise RX | |
2135 | * ONLY. Hence, we must now check to see if we need to | |
2136 | * turn OFF the TRANSMISSION of PAUSE frames. | |
2137 | */ | |
2138 | if(hw->original_fc == e1000_fc_full) { | |
2139 | hw->fc = e1000_fc_full; | |
2140 | DEBUGOUT("Flow Control = FULL.\r\n"); | |
2141 | } else { | |
2142 | hw->fc = e1000_fc_rx_pause; | |
2143 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); | |
2144 | } | |
2145 | } | |
2146 | /* For receiving PAUSE frames ONLY. | |
2147 | * | |
2148 | * LOCAL DEVICE | LINK PARTNER | |
2149 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2150 | *-------|---------|-------|---------|-------------------- | |
2151 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
2152 | * | |
2153 | */ | |
2154 | else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2155 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2156 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2157 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
2158 | hw->fc = e1000_fc_tx_pause; | |
2159 | DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); | |
2160 | } | |
2161 | /* For transmitting PAUSE frames ONLY. | |
2162 | * | |
2163 | * LOCAL DEVICE | LINK PARTNER | |
2164 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2165 | *-------|---------|-------|---------|-------------------- | |
2166 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
2167 | * | |
2168 | */ | |
2169 | else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2170 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2171 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2172 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
2173 | hw->fc = e1000_fc_rx_pause; | |
2174 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); | |
2175 | } | |
2176 | /* Per the IEEE spec, at this point flow control should be | |
2177 | * disabled. However, we want to consider that we could | |
2178 | * be connected to a legacy switch that doesn't advertise | |
2179 | * desired flow control, but can be forced on the link | |
2180 | * partner. So if we advertised no flow control, that is | |
2181 | * what we will resolve to. If we advertised some kind of | |
2182 | * receive capability (Rx Pause Only or Full Flow Control) | |
2183 | * and the link partner advertised none, we will configure | |
2184 | * ourselves to enable Rx Flow Control only. We can do | |
2185 | * this safely for two reasons: If the link partner really | |
2186 | * didn't want flow control enabled, and we enable Rx, no | |
2187 | * harm done since we won't be receiving any PAUSE frames | |
2188 | * anyway. If the intent on the link partner was to have | |
2189 | * flow control enabled, then by us enabling RX only, we | |
2190 | * can at least receive pause frames and process them. | |
2191 | * This is a good idea because in most cases, since we are | |
2192 | * predominantly a server NIC, more times than not we will | |
2193 | * be asked to delay transmission of packets than asking | |
2194 | * our link partner to pause transmission of frames. | |
2195 | */ | |
2196 | else if((hw->original_fc == e1000_fc_none || | |
2197 | hw->original_fc == e1000_fc_tx_pause) || | |
2198 | hw->fc_strict_ieee) { | |
2199 | hw->fc = e1000_fc_none; | |
2200 | DEBUGOUT("Flow Control = NONE.\r\n"); | |
2201 | } else { | |
2202 | hw->fc = e1000_fc_rx_pause; | |
2203 | DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); | |
2204 | } | |
2205 | ||
2206 | /* Now we need to do one last check... If we auto- | |
2207 | * negotiated to HALF DUPLEX, flow control should not be | |
2208 | * enabled per IEEE 802.3 spec. | |
2209 | */ | |
2210 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
2211 | if(ret_val) { | |
2212 | DEBUGOUT("Error getting link speed and duplex\n"); | |
2213 | return ret_val; | |
2214 | } | |
2215 | ||
2216 | if(duplex == HALF_DUPLEX) | |
2217 | hw->fc = e1000_fc_none; | |
2218 | ||
2219 | /* Now we call a subroutine to actually force the MAC | |
2220 | * controller to use the correct flow control settings. | |
2221 | */ | |
2222 | ret_val = e1000_force_mac_fc(hw); | |
2223 | if(ret_val) { | |
2224 | DEBUGOUT("Error forcing flow control settings\n"); | |
2225 | return ret_val; | |
2226 | } | |
2227 | } else { | |
2228 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n"); | |
2229 | } | |
2230 | } | |
2231 | return E1000_SUCCESS; | |
2232 | } | |
2233 | ||
2234 | /****************************************************************************** | |
2235 | * Checks to see if the link status of the hardware has changed. | |
2236 | * | |
2237 | * hw - Struct containing variables accessed by shared code | |
2238 | * | |
2239 | * Called by any function that needs to check the link status of the adapter. | |
2240 | *****************************************************************************/ | |
2241 | int32_t | |
2242 | e1000_check_for_link(struct e1000_hw *hw) | |
2243 | { | |
2244 | uint32_t rxcw = 0; | |
2245 | uint32_t ctrl; | |
2246 | uint32_t status; | |
2247 | uint32_t rctl; | |
2248 | uint32_t icr; | |
2249 | uint32_t signal = 0; | |
2250 | int32_t ret_val; | |
2251 | uint16_t phy_data; | |
2252 | ||
2253 | DEBUGFUNC("e1000_check_for_link"); | |
2254 | ||
2255 | ctrl = E1000_READ_REG(hw, CTRL); | |
2256 | status = E1000_READ_REG(hw, STATUS); | |
2257 | ||
2258 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be | |
2259 | * set when the optics detect a signal. On older adapters, it will be | |
2260 | * cleared when there is a signal. This applies to fiber media only. | |
2261 | */ | |
2262 | if((hw->media_type == e1000_media_type_fiber) || | |
2263 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
2264 | rxcw = E1000_READ_REG(hw, RXCW); | |
2265 | ||
2266 | if(hw->media_type == e1000_media_type_fiber) { | |
2267 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | |
2268 | if(status & E1000_STATUS_LU) | |
2269 | hw->get_link_status = FALSE; | |
2270 | } | |
2271 | } | |
2272 | ||
2273 | /* If we have a copper PHY then we only want to go out to the PHY | |
2274 | * registers to see if Auto-Neg has completed and/or if our link | |
2275 | * status has changed. The get_link_status flag will be set if we | |
2276 | * receive a Link Status Change interrupt or we have Rx Sequence | |
2277 | * Errors. | |
2278 | */ | |
2279 | if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { | |
2280 | /* First we want to see if the MII Status Register reports | |
2281 | * link. If so, then we want to get the current speed/duplex | |
2282 | * of the PHY. | |
2283 | * Read the register twice since the link bit is sticky. | |
2284 | */ | |
2285 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2286 | if(ret_val) | |
2287 | return ret_val; | |
2288 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2289 | if(ret_val) | |
2290 | return ret_val; | |
2291 | ||
2292 | if(phy_data & MII_SR_LINK_STATUS) { | |
2293 | hw->get_link_status = FALSE; | |
2294 | /* Check if there was DownShift, must be checked immediately after | |
2295 | * link-up */ | |
2296 | e1000_check_downshift(hw); | |
2297 | ||
2298 | /* If we are on 82544 or 82543 silicon and speed/duplex | |
2299 | * are forced to 10H or 10F, then we will implement the polarity | |
2300 | * reversal workaround. We disable interrupts first, and upon | |
2301 | * returning, place the devices interrupt state to its previous | |
2302 | * value except for the link status change interrupt which will | |
2303 | * happen due to the execution of this workaround. | |
2304 | */ | |
2305 | ||
2306 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | |
2307 | (!hw->autoneg) && | |
2308 | (hw->forced_speed_duplex == e1000_10_full || | |
2309 | hw->forced_speed_duplex == e1000_10_half)) { | |
2310 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
2311 | ret_val = e1000_polarity_reversal_workaround(hw); | |
2312 | icr = E1000_READ_REG(hw, ICR); | |
2313 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); | |
2314 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); | |
2315 | } | |
2316 | ||
2317 | } else { | |
2318 | /* No link detected */ | |
2319 | e1000_config_dsp_after_link_change(hw, FALSE); | |
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | /* If we are forcing speed/duplex, then we simply return since | |
2324 | * we have already determined whether we have link or not. | |
2325 | */ | |
2326 | if(!hw->autoneg) return -E1000_ERR_CONFIG; | |
2327 | ||
2328 | /* optimize the dsp settings for the igp phy */ | |
2329 | e1000_config_dsp_after_link_change(hw, TRUE); | |
2330 | ||
2331 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
2332 | * have Si on board that is 82544 or newer, Auto | |
2333 | * Speed Detection takes care of MAC speed/duplex | |
2334 | * configuration. So we only need to configure Collision | |
2335 | * Distance in the MAC. Otherwise, we need to force | |
2336 | * speed/duplex on the MAC to the current PHY speed/duplex | |
2337 | * settings. | |
2338 | */ | |
2339 | if(hw->mac_type >= e1000_82544) | |
2340 | e1000_config_collision_dist(hw); | |
2341 | else { | |
2342 | ret_val = e1000_config_mac_to_phy(hw); | |
2343 | if(ret_val) { | |
2344 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
2345 | return ret_val; | |
2346 | } | |
2347 | } | |
2348 | ||
2349 | /* Configure Flow Control now that Auto-Neg has completed. First, we | |
2350 | * need to restore the desired flow control settings because we may | |
2351 | * have had to re-autoneg with a different link partner. | |
2352 | */ | |
2353 | ret_val = e1000_config_fc_after_link_up(hw); | |
2354 | if(ret_val) { | |
2355 | DEBUGOUT("Error configuring flow control\n"); | |
2356 | return ret_val; | |
2357 | } | |
2358 | ||
2359 | /* At this point we know that we are on copper and we have | |
2360 | * auto-negotiated link. These are conditions for checking the link | |
2361 | * partner capability register. We use the link speed to determine if | |
2362 | * TBI compatibility needs to be turned on or off. If the link is not | |
2363 | * at gigabit speed, then TBI compatibility is not needed. If we are | |
2364 | * at gigabit speed, we turn on TBI compatibility. | |
2365 | */ | |
2366 | if(hw->tbi_compatibility_en) { | |
2367 | uint16_t speed, duplex; | |
2368 | e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
2369 | if(speed != SPEED_1000) { | |
2370 | /* If link speed is not set to gigabit speed, we do not need | |
2371 | * to enable TBI compatibility. | |
2372 | */ | |
2373 | if(hw->tbi_compatibility_on) { | |
2374 | /* If we previously were in the mode, turn it off. */ | |
2375 | rctl = E1000_READ_REG(hw, RCTL); | |
2376 | rctl &= ~E1000_RCTL_SBP; | |
2377 | E1000_WRITE_REG(hw, RCTL, rctl); | |
2378 | hw->tbi_compatibility_on = FALSE; | |
2379 | } | |
2380 | } else { | |
2381 | /* If TBI compatibility is was previously off, turn it on. For | |
2382 | * compatibility with a TBI link partner, we will store bad | |
2383 | * packets. Some frames have an additional byte on the end and | |
2384 | * will look like CRC errors to to the hardware. | |
2385 | */ | |
2386 | if(!hw->tbi_compatibility_on) { | |
2387 | hw->tbi_compatibility_on = TRUE; | |
2388 | rctl = E1000_READ_REG(hw, RCTL); | |
2389 | rctl |= E1000_RCTL_SBP; | |
2390 | E1000_WRITE_REG(hw, RCTL, rctl); | |
2391 | } | |
2392 | } | |
2393 | } | |
2394 | } | |
2395 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
2396 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
2397 | * link partner is not trying to auto-negotiate with us (we are receiving | |
2398 | * idles or data), we need to force link up. We also need to give | |
2399 | * auto-negotiation time to complete, in case the cable was just plugged | |
2400 | * in. The autoneg_failed flag does this. | |
2401 | */ | |
2402 | else if((((hw->media_type == e1000_media_type_fiber) && | |
2403 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || | |
2404 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
2405 | (!(status & E1000_STATUS_LU)) && | |
2406 | (!(rxcw & E1000_RXCW_C))) { | |
2407 | if(hw->autoneg_failed == 0) { | |
2408 | hw->autoneg_failed = 1; | |
2409 | return 0; | |
2410 | } | |
2411 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); | |
2412 | ||
2413 | /* Disable auto-negotiation in the TXCW register */ | |
2414 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | |
2415 | ||
2416 | /* Force link-up and also force full-duplex. */ | |
2417 | ctrl = E1000_READ_REG(hw, CTRL); | |
2418 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
2419 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2420 | ||
2421 | /* Configure Flow Control after forcing link up. */ | |
2422 | ret_val = e1000_config_fc_after_link_up(hw); | |
2423 | if(ret_val) { | |
2424 | DEBUGOUT("Error configuring flow control\n"); | |
2425 | return ret_val; | |
2426 | } | |
2427 | } | |
2428 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
2429 | * auto-negotiation in the TXCW register and disable forced link in the | |
2430 | * Device Control register in an attempt to auto-negotiate with our link | |
2431 | * partner. | |
2432 | */ | |
2433 | else if(((hw->media_type == e1000_media_type_fiber) || | |
2434 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
2435 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
2436 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); | |
2437 | E1000_WRITE_REG(hw, TXCW, hw->txcw); | |
2438 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
2439 | ||
2440 | hw->serdes_link_down = FALSE; | |
2441 | } | |
2442 | /* If we force link for non-auto-negotiation switch, check link status | |
2443 | * based on MAC synchronization for internal serdes media type. | |
2444 | */ | |
2445 | else if((hw->media_type == e1000_media_type_internal_serdes) && | |
2446 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
2447 | /* SYNCH bit and IV bit are sticky. */ | |
2448 | udelay(10); | |
2449 | if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { | |
2450 | if(!(rxcw & E1000_RXCW_IV)) { | |
2451 | hw->serdes_link_down = FALSE; | |
2452 | DEBUGOUT("SERDES: Link is up.\n"); | |
2453 | } | |
2454 | } else { | |
2455 | hw->serdes_link_down = TRUE; | |
2456 | DEBUGOUT("SERDES: Link is down.\n"); | |
2457 | } | |
2458 | } | |
2459 | if((hw->media_type == e1000_media_type_internal_serdes) && | |
2460 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
2461 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); | |
2462 | } | |
2463 | return E1000_SUCCESS; | |
2464 | } | |
2465 | ||
2466 | /****************************************************************************** | |
2467 | * Detects the current speed and duplex settings of the hardware. | |
2468 | * | |
2469 | * hw - Struct containing variables accessed by shared code | |
2470 | * speed - Speed of the connection | |
2471 | * duplex - Duplex setting of the connection | |
2472 | *****************************************************************************/ | |
2473 | int32_t | |
2474 | e1000_get_speed_and_duplex(struct e1000_hw *hw, | |
2475 | uint16_t *speed, | |
2476 | uint16_t *duplex) | |
2477 | { | |
2478 | uint32_t status; | |
2479 | int32_t ret_val; | |
2480 | uint16_t phy_data; | |
2481 | ||
2482 | DEBUGFUNC("e1000_get_speed_and_duplex"); | |
2483 | ||
2484 | if(hw->mac_type >= e1000_82543) { | |
2485 | status = E1000_READ_REG(hw, STATUS); | |
2486 | if(status & E1000_STATUS_SPEED_1000) { | |
2487 | *speed = SPEED_1000; | |
2488 | DEBUGOUT("1000 Mbs, "); | |
2489 | } else if(status & E1000_STATUS_SPEED_100) { | |
2490 | *speed = SPEED_100; | |
2491 | DEBUGOUT("100 Mbs, "); | |
2492 | } else { | |
2493 | *speed = SPEED_10; | |
2494 | DEBUGOUT("10 Mbs, "); | |
2495 | } | |
2496 | ||
2497 | if(status & E1000_STATUS_FD) { | |
2498 | *duplex = FULL_DUPLEX; | |
2499 | DEBUGOUT("Full Duplex\r\n"); | |
2500 | } else { | |
2501 | *duplex = HALF_DUPLEX; | |
2502 | DEBUGOUT(" Half Duplex\r\n"); | |
2503 | } | |
2504 | } else { | |
2505 | DEBUGOUT("1000 Mbs, Full Duplex\r\n"); | |
2506 | *speed = SPEED_1000; | |
2507 | *duplex = FULL_DUPLEX; | |
2508 | } | |
2509 | ||
2510 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even | |
2511 | * if it is operating at half duplex. Here we set the duplex settings to | |
2512 | * match the duplex in the link partner's capabilities. | |
2513 | */ | |
2514 | if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { | |
2515 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); | |
2516 | if(ret_val) | |
2517 | return ret_val; | |
2518 | ||
2519 | if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) | |
2520 | *duplex = HALF_DUPLEX; | |
2521 | else { | |
2522 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); | |
2523 | if(ret_val) | |
2524 | return ret_val; | |
2525 | if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || | |
2526 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) | |
2527 | *duplex = HALF_DUPLEX; | |
2528 | } | |
2529 | } | |
2530 | ||
2531 | return E1000_SUCCESS; | |
2532 | } | |
2533 | ||
2534 | /****************************************************************************** | |
2535 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
2536 | * | |
2537 | * hw - Struct containing variables accessed by shared code | |
2538 | ******************************************************************************/ | |
2539 | int32_t | |
2540 | e1000_wait_autoneg(struct e1000_hw *hw) | |
2541 | { | |
2542 | int32_t ret_val; | |
2543 | uint16_t i; | |
2544 | uint16_t phy_data; | |
2545 | ||
2546 | DEBUGFUNC("e1000_wait_autoneg"); | |
2547 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
2548 | ||
2549 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
2550 | for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { | |
2551 | /* Read the MII Status Register and wait for Auto-Neg | |
2552 | * Complete bit to be set. | |
2553 | */ | |
2554 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2555 | if(ret_val) | |
2556 | return ret_val; | |
2557 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2558 | if(ret_val) | |
2559 | return ret_val; | |
2560 | if(phy_data & MII_SR_AUTONEG_COMPLETE) { | |
2561 | return E1000_SUCCESS; | |
2562 | } | |
2563 | msec_delay(100); | |
2564 | } | |
2565 | return E1000_SUCCESS; | |
2566 | } | |
2567 | ||
2568 | /****************************************************************************** | |
2569 | * Raises the Management Data Clock | |
2570 | * | |
2571 | * hw - Struct containing variables accessed by shared code | |
2572 | * ctrl - Device control register's current value | |
2573 | ******************************************************************************/ | |
2574 | static void | |
2575 | e1000_raise_mdi_clk(struct e1000_hw *hw, | |
2576 | uint32_t *ctrl) | |
2577 | { | |
2578 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
2579 | * bit), and then delay 10 microseconds. | |
2580 | */ | |
2581 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); | |
2582 | E1000_WRITE_FLUSH(hw); | |
2583 | udelay(10); | |
2584 | } | |
2585 | ||
2586 | /****************************************************************************** | |
2587 | * Lowers the Management Data Clock | |
2588 | * | |
2589 | * hw - Struct containing variables accessed by shared code | |
2590 | * ctrl - Device control register's current value | |
2591 | ******************************************************************************/ | |
2592 | static void | |
2593 | e1000_lower_mdi_clk(struct e1000_hw *hw, | |
2594 | uint32_t *ctrl) | |
2595 | { | |
2596 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
2597 | * bit), and then delay 10 microseconds. | |
2598 | */ | |
2599 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); | |
2600 | E1000_WRITE_FLUSH(hw); | |
2601 | udelay(10); | |
2602 | } | |
2603 | ||
2604 | /****************************************************************************** | |
2605 | * Shifts data bits out to the PHY | |
2606 | * | |
2607 | * hw - Struct containing variables accessed by shared code | |
2608 | * data - Data to send out to the PHY | |
2609 | * count - Number of bits to shift out | |
2610 | * | |
2611 | * Bits are shifted out in MSB to LSB order. | |
2612 | ******************************************************************************/ | |
2613 | static void | |
2614 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, | |
2615 | uint32_t data, | |
2616 | uint16_t count) | |
2617 | { | |
2618 | uint32_t ctrl; | |
2619 | uint32_t mask; | |
2620 | ||
2621 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
2622 | * in the "data" parameter will be shifted out to the PHY one bit at a | |
2623 | * time. In order to do this, "data" must be broken down into bits. | |
2624 | */ | |
2625 | mask = 0x01; | |
2626 | mask <<= (count - 1); | |
2627 | ||
2628 | ctrl = E1000_READ_REG(hw, CTRL); | |
2629 | ||
2630 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
2631 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
2632 | ||
2633 | while(mask) { | |
2634 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and | |
2635 | * then raising and lowering the Management Data Clock. A "0" is | |
2636 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
2637 | * raising and lowering the clock. | |
2638 | */ | |
2639 | if(data & mask) ctrl |= E1000_CTRL_MDIO; | |
2640 | else ctrl &= ~E1000_CTRL_MDIO; | |
2641 | ||
2642 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2643 | E1000_WRITE_FLUSH(hw); | |
2644 | ||
2645 | udelay(10); | |
2646 | ||
2647 | e1000_raise_mdi_clk(hw, &ctrl); | |
2648 | e1000_lower_mdi_clk(hw, &ctrl); | |
2649 | ||
2650 | mask = mask >> 1; | |
2651 | } | |
2652 | } | |
2653 | ||
2654 | /****************************************************************************** | |
2655 | * Shifts data bits in from the PHY | |
2656 | * | |
2657 | * hw - Struct containing variables accessed by shared code | |
2658 | * | |
2659 | * Bits are shifted in in MSB to LSB order. | |
2660 | ******************************************************************************/ | |
2661 | static uint16_t | |
2662 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) | |
2663 | { | |
2664 | uint32_t ctrl; | |
2665 | uint16_t data = 0; | |
2666 | uint8_t i; | |
2667 | ||
2668 | /* In order to read a register from the PHY, we need to shift in a total | |
2669 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
2670 | * to avoid contention on the MDIO pin when a read operation is performed. | |
2671 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
2672 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
2673 | * and then reading the value of the MDIO bit. | |
2674 | */ | |
2675 | ctrl = E1000_READ_REG(hw, CTRL); | |
2676 | ||
2677 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
2678 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
2679 | ctrl &= ~E1000_CTRL_MDIO; | |
2680 | ||
2681 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2682 | E1000_WRITE_FLUSH(hw); | |
2683 | ||
2684 | /* Raise and Lower the clock before reading in the data. This accounts for | |
2685 | * the turnaround bits. The first clock occurred when we clocked out the | |
2686 | * last bit of the Register Address. | |
2687 | */ | |
2688 | e1000_raise_mdi_clk(hw, &ctrl); | |
2689 | e1000_lower_mdi_clk(hw, &ctrl); | |
2690 | ||
2691 | for(data = 0, i = 0; i < 16; i++) { | |
2692 | data = data << 1; | |
2693 | e1000_raise_mdi_clk(hw, &ctrl); | |
2694 | ctrl = E1000_READ_REG(hw, CTRL); | |
2695 | /* Check to see if we shifted in a "1". */ | |
2696 | if(ctrl & E1000_CTRL_MDIO) data |= 1; | |
2697 | e1000_lower_mdi_clk(hw, &ctrl); | |
2698 | } | |
2699 | ||
2700 | e1000_raise_mdi_clk(hw, &ctrl); | |
2701 | e1000_lower_mdi_clk(hw, &ctrl); | |
2702 | ||
2703 | return data; | |
2704 | } | |
2705 | ||
2706 | /***************************************************************************** | |
2707 | * Reads the value from a PHY register, if the value is on a specific non zero | |
2708 | * page, sets the page first. | |
2709 | * hw - Struct containing variables accessed by shared code | |
2710 | * reg_addr - address of the PHY register to read | |
2711 | ******************************************************************************/ | |
2712 | int32_t | |
2713 | e1000_read_phy_reg(struct e1000_hw *hw, | |
2714 | uint32_t reg_addr, | |
2715 | uint16_t *phy_data) | |
2716 | { | |
2717 | uint32_t ret_val; | |
2718 | ||
2719 | DEBUGFUNC("e1000_read_phy_reg"); | |
2720 | ||
2d7edb92 MC |
2721 | if((hw->phy_type == e1000_phy_igp || |
2722 | hw->phy_type == e1000_phy_igp_2) && | |
1da177e4 LT |
2723 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
2724 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2725 | (uint16_t)reg_addr); | |
2726 | if(ret_val) { | |
2727 | return ret_val; | |
2728 | } | |
2729 | } | |
2730 | ||
2731 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
2732 | phy_data); | |
2733 | ||
2734 | return ret_val; | |
2735 | } | |
2736 | ||
2737 | int32_t | |
2738 | e1000_read_phy_reg_ex(struct e1000_hw *hw, | |
2739 | uint32_t reg_addr, | |
2740 | uint16_t *phy_data) | |
2741 | { | |
2742 | uint32_t i; | |
2743 | uint32_t mdic = 0; | |
2744 | const uint32_t phy_addr = 1; | |
2745 | ||
2746 | DEBUGFUNC("e1000_read_phy_reg_ex"); | |
2747 | ||
2748 | if(reg_addr > MAX_PHY_REG_ADDRESS) { | |
2749 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | |
2750 | return -E1000_ERR_PARAM; | |
2751 | } | |
2752 | ||
2753 | if(hw->mac_type > e1000_82543) { | |
2754 | /* Set up Op-code, Phy Address, and register address in the MDI | |
2755 | * Control register. The MAC will take care of interfacing with the | |
2756 | * PHY to retrieve the desired data. | |
2757 | */ | |
2758 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
2759 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
2760 | (E1000_MDIC_OP_READ)); | |
2761 | ||
2762 | E1000_WRITE_REG(hw, MDIC, mdic); | |
2763 | ||
2764 | /* Poll the ready bit to see if the MDI read completed */ | |
2765 | for(i = 0; i < 64; i++) { | |
2766 | udelay(50); | |
2767 | mdic = E1000_READ_REG(hw, MDIC); | |
2768 | if(mdic & E1000_MDIC_READY) break; | |
2769 | } | |
2770 | if(!(mdic & E1000_MDIC_READY)) { | |
2771 | DEBUGOUT("MDI Read did not complete\n"); | |
2772 | return -E1000_ERR_PHY; | |
2773 | } | |
2774 | if(mdic & E1000_MDIC_ERROR) { | |
2775 | DEBUGOUT("MDI Error\n"); | |
2776 | return -E1000_ERR_PHY; | |
2777 | } | |
2778 | *phy_data = (uint16_t) mdic; | |
2779 | } else { | |
2780 | /* We must first send a preamble through the MDIO pin to signal the | |
2781 | * beginning of an MII instruction. This is done by sending 32 | |
2782 | * consecutive "1" bits. | |
2783 | */ | |
2784 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
2785 | ||
2786 | /* Now combine the next few fields that are required for a read | |
2787 | * operation. We use this method instead of calling the | |
2788 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
2789 | * a MII read instruction consists of a shift out of 14 bits and is | |
2790 | * defined as follows: | |
2791 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
2792 | * followed by a shift in of 18 bits. This first two bits shifted in | |
2793 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
2794 | * READ operation is performed. These two bits are thrown away | |
2795 | * followed by a shift in of 16 bits which contains the desired data. | |
2796 | */ | |
2797 | mdic = ((reg_addr) | (phy_addr << 5) | | |
2798 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
2799 | ||
2800 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
2801 | ||
2802 | /* Now that we've shifted out the read command to the MII, we need to | |
2803 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
2804 | * register address. | |
2805 | */ | |
2806 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
2807 | } | |
2808 | return E1000_SUCCESS; | |
2809 | } | |
2810 | ||
2811 | /****************************************************************************** | |
2812 | * Writes a value to a PHY register | |
2813 | * | |
2814 | * hw - Struct containing variables accessed by shared code | |
2815 | * reg_addr - address of the PHY register to write | |
2816 | * data - data to write to the PHY | |
2817 | ******************************************************************************/ | |
2818 | int32_t | |
2819 | e1000_write_phy_reg(struct e1000_hw *hw, | |
2820 | uint32_t reg_addr, | |
2821 | uint16_t phy_data) | |
2822 | { | |
2823 | uint32_t ret_val; | |
2824 | ||
2825 | DEBUGFUNC("e1000_write_phy_reg"); | |
2826 | ||
2d7edb92 MC |
2827 | if((hw->phy_type == e1000_phy_igp || |
2828 | hw->phy_type == e1000_phy_igp_2) && | |
1da177e4 LT |
2829 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
2830 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2831 | (uint16_t)reg_addr); | |
2832 | if(ret_val) { | |
2833 | return ret_val; | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
2838 | phy_data); | |
2839 | ||
2840 | return ret_val; | |
2841 | } | |
2842 | ||
2843 | int32_t | |
2844 | e1000_write_phy_reg_ex(struct e1000_hw *hw, | |
2845 | uint32_t reg_addr, | |
2846 | uint16_t phy_data) | |
2847 | { | |
2848 | uint32_t i; | |
2849 | uint32_t mdic = 0; | |
2850 | const uint32_t phy_addr = 1; | |
2851 | ||
2852 | DEBUGFUNC("e1000_write_phy_reg_ex"); | |
2853 | ||
2854 | if(reg_addr > MAX_PHY_REG_ADDRESS) { | |
2855 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | |
2856 | return -E1000_ERR_PARAM; | |
2857 | } | |
2858 | ||
2859 | if(hw->mac_type > e1000_82543) { | |
2860 | /* Set up Op-code, Phy Address, register address, and data intended | |
2861 | * for the PHY register in the MDI Control register. The MAC will take | |
2862 | * care of interfacing with the PHY to send the desired data. | |
2863 | */ | |
2864 | mdic = (((uint32_t) phy_data) | | |
2865 | (reg_addr << E1000_MDIC_REG_SHIFT) | | |
2866 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
2867 | (E1000_MDIC_OP_WRITE)); | |
2868 | ||
2869 | E1000_WRITE_REG(hw, MDIC, mdic); | |
2870 | ||
2871 | /* Poll the ready bit to see if the MDI read completed */ | |
2872 | for(i = 0; i < 640; i++) { | |
2873 | udelay(5); | |
2874 | mdic = E1000_READ_REG(hw, MDIC); | |
2875 | if(mdic & E1000_MDIC_READY) break; | |
2876 | } | |
2877 | if(!(mdic & E1000_MDIC_READY)) { | |
2878 | DEBUGOUT("MDI Write did not complete\n"); | |
2879 | return -E1000_ERR_PHY; | |
2880 | } | |
2881 | } else { | |
2882 | /* We'll need to use the SW defined pins to shift the write command | |
2883 | * out to the PHY. We first send a preamble to the PHY to signal the | |
2884 | * beginning of the MII instruction. This is done by sending 32 | |
2885 | * consecutive "1" bits. | |
2886 | */ | |
2887 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
2888 | ||
2889 | /* Now combine the remaining required fields that will indicate a | |
2890 | * write operation. We use this method instead of calling the | |
2891 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
2892 | * format of a MII write instruction is as follows: | |
2893 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
2894 | */ | |
2895 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
2896 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
2897 | mdic <<= 16; | |
2898 | mdic |= (uint32_t) phy_data; | |
2899 | ||
2900 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
2901 | } | |
2902 | ||
2903 | return E1000_SUCCESS; | |
2904 | } | |
2905 | ||
2d7edb92 | 2906 | |
1da177e4 LT |
2907 | /****************************************************************************** |
2908 | * Returns the PHY to the power-on reset state | |
2909 | * | |
2910 | * hw - Struct containing variables accessed by shared code | |
2911 | ******************************************************************************/ | |
2d7edb92 | 2912 | int32_t |
1da177e4 LT |
2913 | e1000_phy_hw_reset(struct e1000_hw *hw) |
2914 | { | |
2915 | uint32_t ctrl, ctrl_ext; | |
2916 | uint32_t led_ctrl; | |
2d7edb92 | 2917 | int32_t ret_val; |
1da177e4 LT |
2918 | |
2919 | DEBUGFUNC("e1000_phy_hw_reset"); | |
2920 | ||
2d7edb92 MC |
2921 | /* In the case of the phy reset being blocked, it's not an error, we |
2922 | * simply return success without performing the reset. */ | |
2923 | ret_val = e1000_check_phy_reset_block(hw); | |
2924 | if (ret_val) | |
2925 | return E1000_SUCCESS; | |
2926 | ||
1da177e4 LT |
2927 | DEBUGOUT("Resetting Phy...\n"); |
2928 | ||
2929 | if(hw->mac_type > e1000_82543) { | |
2930 | /* Read the device control register and assert the E1000_CTRL_PHY_RST | |
2931 | * bit. Then, take it out of reset. | |
2932 | */ | |
2933 | ctrl = E1000_READ_REG(hw, CTRL); | |
2934 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2935 | E1000_WRITE_FLUSH(hw); | |
2936 | msec_delay(10); | |
2937 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2938 | E1000_WRITE_FLUSH(hw); | |
2939 | } else { | |
2940 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
2941 | * bit to put the PHY into reset. Then, take it out of reset. | |
2942 | */ | |
2943 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
2944 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | |
2945 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
2946 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
2947 | E1000_WRITE_FLUSH(hw); | |
2948 | msec_delay(10); | |
2949 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | |
2950 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
2951 | E1000_WRITE_FLUSH(hw); | |
2952 | } | |
2953 | udelay(150); | |
2954 | ||
2955 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
2956 | /* Configure activity LED after PHY reset */ | |
2957 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
2958 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
2959 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
2960 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
2961 | } | |
2d7edb92 MC |
2962 | |
2963 | /* Wait for FW to finish PHY configuration. */ | |
2964 | ret_val = e1000_get_phy_cfg_done(hw); | |
2965 | ||
2966 | return ret_val; | |
1da177e4 LT |
2967 | } |
2968 | ||
2969 | /****************************************************************************** | |
2970 | * Resets the PHY | |
2971 | * | |
2972 | * hw - Struct containing variables accessed by shared code | |
2973 | * | |
2974 | * Sets bit 15 of the MII Control regiser | |
2975 | ******************************************************************************/ | |
2976 | int32_t | |
2977 | e1000_phy_reset(struct e1000_hw *hw) | |
2978 | { | |
2979 | int32_t ret_val; | |
2980 | uint16_t phy_data; | |
2981 | ||
2982 | DEBUGFUNC("e1000_phy_reset"); | |
2983 | ||
2d7edb92 MC |
2984 | /* In the case of the phy reset being blocked, it's not an error, we |
2985 | * simply return success without performing the reset. */ | |
2986 | ret_val = e1000_check_phy_reset_block(hw); | |
2987 | if (ret_val) | |
2988 | return E1000_SUCCESS; | |
2989 | ||
2990 | switch (hw->mac_type) { | |
2991 | case e1000_82541_rev_2: | |
868d5309 MC |
2992 | case e1000_82571: |
2993 | case e1000_82572: | |
2d7edb92 MC |
2994 | ret_val = e1000_phy_hw_reset(hw); |
2995 | if(ret_val) | |
2996 | return ret_val; | |
2997 | break; | |
2998 | default: | |
1da177e4 LT |
2999 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
3000 | if(ret_val) | |
3001 | return ret_val; | |
3002 | ||
3003 | phy_data |= MII_CR_RESET; | |
3004 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
3005 | if(ret_val) | |
3006 | return ret_val; | |
3007 | ||
3008 | udelay(1); | |
2d7edb92 MC |
3009 | break; |
3010 | } | |
1da177e4 | 3011 | |
2d7edb92 | 3012 | if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
1da177e4 LT |
3013 | e1000_phy_init_script(hw); |
3014 | ||
3015 | return E1000_SUCCESS; | |
3016 | } | |
3017 | ||
3018 | /****************************************************************************** | |
3019 | * Probes the expected PHY address for known PHY IDs | |
3020 | * | |
3021 | * hw - Struct containing variables accessed by shared code | |
3022 | ******************************************************************************/ | |
3023 | int32_t | |
3024 | e1000_detect_gig_phy(struct e1000_hw *hw) | |
3025 | { | |
3026 | int32_t phy_init_status, ret_val; | |
3027 | uint16_t phy_id_high, phy_id_low; | |
3028 | boolean_t match = FALSE; | |
3029 | ||
3030 | DEBUGFUNC("e1000_detect_gig_phy"); | |
3031 | ||
868d5309 MC |
3032 | /* The 82571 firmware may still be configuring the PHY. In this |
3033 | * case, we cannot access the PHY until the configuration is done. So | |
3034 | * we explicitly set the PHY values. */ | |
3035 | if(hw->mac_type == e1000_82571 || | |
3036 | hw->mac_type == e1000_82572) { | |
3037 | hw->phy_id = IGP01E1000_I_PHY_ID; | |
3038 | hw->phy_type = e1000_phy_igp_2; | |
3039 | return E1000_SUCCESS; | |
3040 | } | |
3041 | ||
1da177e4 LT |
3042 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
3043 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
3044 | if(ret_val) | |
3045 | return ret_val; | |
3046 | ||
3047 | hw->phy_id = (uint32_t) (phy_id_high << 16); | |
3048 | udelay(20); | |
3049 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
3050 | if(ret_val) | |
3051 | return ret_val; | |
3052 | ||
3053 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); | |
3054 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; | |
3055 | ||
3056 | switch(hw->mac_type) { | |
3057 | case e1000_82543: | |
3058 | if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; | |
3059 | break; | |
3060 | case e1000_82544: | |
3061 | if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; | |
3062 | break; | |
3063 | case e1000_82540: | |
3064 | case e1000_82545: | |
3065 | case e1000_82545_rev_3: | |
3066 | case e1000_82546: | |
3067 | case e1000_82546_rev_3: | |
3068 | if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; | |
3069 | break; | |
3070 | case e1000_82541: | |
3071 | case e1000_82541_rev_2: | |
3072 | case e1000_82547: | |
3073 | case e1000_82547_rev_2: | |
3074 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; | |
3075 | break; | |
2d7edb92 MC |
3076 | case e1000_82573: |
3077 | if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; | |
3078 | break; | |
1da177e4 LT |
3079 | default: |
3080 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | |
3081 | return -E1000_ERR_CONFIG; | |
3082 | } | |
3083 | phy_init_status = e1000_set_phy_type(hw); | |
3084 | ||
3085 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
3086 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); | |
3087 | return E1000_SUCCESS; | |
3088 | } | |
3089 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); | |
3090 | return -E1000_ERR_PHY; | |
3091 | } | |
3092 | ||
3093 | /****************************************************************************** | |
3094 | * Resets the PHY's DSP | |
3095 | * | |
3096 | * hw - Struct containing variables accessed by shared code | |
3097 | ******************************************************************************/ | |
3098 | static int32_t | |
3099 | e1000_phy_reset_dsp(struct e1000_hw *hw) | |
3100 | { | |
3101 | int32_t ret_val; | |
3102 | DEBUGFUNC("e1000_phy_reset_dsp"); | |
3103 | ||
3104 | do { | |
3105 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); | |
3106 | if(ret_val) break; | |
3107 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); | |
3108 | if(ret_val) break; | |
3109 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); | |
3110 | if(ret_val) break; | |
3111 | ret_val = E1000_SUCCESS; | |
3112 | } while(0); | |
3113 | ||
3114 | return ret_val; | |
3115 | } | |
3116 | ||
3117 | /****************************************************************************** | |
3118 | * Get PHY information from various PHY registers for igp PHY only. | |
3119 | * | |
3120 | * hw - Struct containing variables accessed by shared code | |
3121 | * phy_info - PHY information structure | |
3122 | ******************************************************************************/ | |
3123 | int32_t | |
3124 | e1000_phy_igp_get_info(struct e1000_hw *hw, | |
3125 | struct e1000_phy_info *phy_info) | |
3126 | { | |
3127 | int32_t ret_val; | |
3128 | uint16_t phy_data, polarity, min_length, max_length, average; | |
3129 | ||
3130 | DEBUGFUNC("e1000_phy_igp_get_info"); | |
3131 | ||
3132 | /* The downshift status is checked only once, after link is established, | |
3133 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 3134 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
3135 | |
3136 | /* IGP01E1000 does not need to support it. */ | |
3137 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
3138 | ||
3139 | /* IGP01E1000 always correct polarity reversal */ | |
3140 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; | |
3141 | ||
3142 | /* Check polarity status */ | |
3143 | ret_val = e1000_check_polarity(hw, &polarity); | |
3144 | if(ret_val) | |
3145 | return ret_val; | |
3146 | ||
3147 | phy_info->cable_polarity = polarity; | |
3148 | ||
3149 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); | |
3150 | if(ret_val) | |
3151 | return ret_val; | |
3152 | ||
3153 | phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> | |
3154 | IGP01E1000_PSSR_MDIX_SHIFT; | |
3155 | ||
3156 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | |
3157 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
3158 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ | |
3159 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
3160 | if(ret_val) | |
3161 | return ret_val; | |
3162 | ||
3163 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> | |
3164 | SR_1000T_LOCAL_RX_STATUS_SHIFT; | |
3165 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
3166 | SR_1000T_REMOTE_RX_STATUS_SHIFT; | |
3167 | ||
3168 | /* Get cable length */ | |
3169 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | |
3170 | if(ret_val) | |
3171 | return ret_val; | |
3172 | ||
2d7edb92 | 3173 | /* Translate to old method */ |
1da177e4 LT |
3174 | average = (max_length + min_length) / 2; |
3175 | ||
3176 | if(average <= e1000_igp_cable_length_50) | |
3177 | phy_info->cable_length = e1000_cable_length_50; | |
3178 | else if(average <= e1000_igp_cable_length_80) | |
3179 | phy_info->cable_length = e1000_cable_length_50_80; | |
3180 | else if(average <= e1000_igp_cable_length_110) | |
3181 | phy_info->cable_length = e1000_cable_length_80_110; | |
3182 | else if(average <= e1000_igp_cable_length_140) | |
3183 | phy_info->cable_length = e1000_cable_length_110_140; | |
3184 | else | |
3185 | phy_info->cable_length = e1000_cable_length_140; | |
3186 | } | |
3187 | ||
3188 | return E1000_SUCCESS; | |
3189 | } | |
3190 | ||
3191 | /****************************************************************************** | |
3192 | * Get PHY information from various PHY registers fot m88 PHY only. | |
3193 | * | |
3194 | * hw - Struct containing variables accessed by shared code | |
3195 | * phy_info - PHY information structure | |
3196 | ******************************************************************************/ | |
3197 | int32_t | |
3198 | e1000_phy_m88_get_info(struct e1000_hw *hw, | |
3199 | struct e1000_phy_info *phy_info) | |
3200 | { | |
3201 | int32_t ret_val; | |
3202 | uint16_t phy_data, polarity; | |
3203 | ||
3204 | DEBUGFUNC("e1000_phy_m88_get_info"); | |
3205 | ||
3206 | /* The downshift status is checked only once, after link is established, | |
3207 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 3208 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
3209 | |
3210 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
3211 | if(ret_val) | |
3212 | return ret_val; | |
3213 | ||
3214 | phy_info->extended_10bt_distance = | |
3215 | (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> | |
3216 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; | |
3217 | phy_info->polarity_correction = | |
3218 | (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> | |
3219 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; | |
3220 | ||
3221 | /* Check polarity status */ | |
3222 | ret_val = e1000_check_polarity(hw, &polarity); | |
3223 | if(ret_val) | |
3224 | return ret_val; | |
3225 | phy_info->cable_polarity = polarity; | |
3226 | ||
3227 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
3228 | if(ret_val) | |
3229 | return ret_val; | |
3230 | ||
3231 | phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> | |
3232 | M88E1000_PSSR_MDIX_SHIFT; | |
3233 | ||
3234 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
3235 | /* Cable Length Estimation and Local/Remote Receiver Information | |
3236 | * are only valid at 1000 Mbps. | |
3237 | */ | |
3238 | phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
3239 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); | |
3240 | ||
3241 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
3242 | if(ret_val) | |
3243 | return ret_val; | |
3244 | ||
3245 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> | |
3246 | SR_1000T_LOCAL_RX_STATUS_SHIFT; | |
3247 | ||
3248 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
3249 | SR_1000T_REMOTE_RX_STATUS_SHIFT; | |
3250 | } | |
3251 | ||
3252 | return E1000_SUCCESS; | |
3253 | } | |
3254 | ||
3255 | /****************************************************************************** | |
3256 | * Get PHY information from various PHY registers | |
3257 | * | |
3258 | * hw - Struct containing variables accessed by shared code | |
3259 | * phy_info - PHY information structure | |
3260 | ******************************************************************************/ | |
3261 | int32_t | |
3262 | e1000_phy_get_info(struct e1000_hw *hw, | |
3263 | struct e1000_phy_info *phy_info) | |
3264 | { | |
3265 | int32_t ret_val; | |
3266 | uint16_t phy_data; | |
3267 | ||
3268 | DEBUGFUNC("e1000_phy_get_info"); | |
3269 | ||
3270 | phy_info->cable_length = e1000_cable_length_undefined; | |
3271 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; | |
3272 | phy_info->cable_polarity = e1000_rev_polarity_undefined; | |
3273 | phy_info->downshift = e1000_downshift_undefined; | |
3274 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; | |
3275 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; | |
3276 | phy_info->local_rx = e1000_1000t_rx_status_undefined; | |
3277 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; | |
3278 | ||
3279 | if(hw->media_type != e1000_media_type_copper) { | |
3280 | DEBUGOUT("PHY info is only valid for copper media\n"); | |
3281 | return -E1000_ERR_CONFIG; | |
3282 | } | |
3283 | ||
3284 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3285 | if(ret_val) | |
3286 | return ret_val; | |
3287 | ||
3288 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3289 | if(ret_val) | |
3290 | return ret_val; | |
3291 | ||
3292 | if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { | |
3293 | DEBUGOUT("PHY info is only valid if link is up\n"); | |
3294 | return -E1000_ERR_CONFIG; | |
3295 | } | |
3296 | ||
2d7edb92 MC |
3297 | if(hw->phy_type == e1000_phy_igp || |
3298 | hw->phy_type == e1000_phy_igp_2) | |
1da177e4 LT |
3299 | return e1000_phy_igp_get_info(hw, phy_info); |
3300 | else | |
3301 | return e1000_phy_m88_get_info(hw, phy_info); | |
3302 | } | |
3303 | ||
3304 | int32_t | |
3305 | e1000_validate_mdi_setting(struct e1000_hw *hw) | |
3306 | { | |
3307 | DEBUGFUNC("e1000_validate_mdi_settings"); | |
3308 | ||
3309 | if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { | |
3310 | DEBUGOUT("Invalid MDI setting detected\n"); | |
3311 | hw->mdix = 1; | |
3312 | return -E1000_ERR_CONFIG; | |
3313 | } | |
3314 | return E1000_SUCCESS; | |
3315 | } | |
3316 | ||
3317 | ||
3318 | /****************************************************************************** | |
3319 | * Sets up eeprom variables in the hw struct. Must be called after mac_type | |
3320 | * is configured. | |
3321 | * | |
3322 | * hw - Struct containing variables accessed by shared code | |
3323 | *****************************************************************************/ | |
2d7edb92 | 3324 | int32_t |
1da177e4 LT |
3325 | e1000_init_eeprom_params(struct e1000_hw *hw) |
3326 | { | |
3327 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3328 | uint32_t eecd = E1000_READ_REG(hw, EECD); | |
2d7edb92 | 3329 | int32_t ret_val = E1000_SUCCESS; |
1da177e4 LT |
3330 | uint16_t eeprom_size; |
3331 | ||
3332 | DEBUGFUNC("e1000_init_eeprom_params"); | |
3333 | ||
3334 | switch (hw->mac_type) { | |
3335 | case e1000_82542_rev2_0: | |
3336 | case e1000_82542_rev2_1: | |
3337 | case e1000_82543: | |
3338 | case e1000_82544: | |
3339 | eeprom->type = e1000_eeprom_microwire; | |
3340 | eeprom->word_size = 64; | |
3341 | eeprom->opcode_bits = 3; | |
3342 | eeprom->address_bits = 6; | |
3343 | eeprom->delay_usec = 50; | |
2d7edb92 MC |
3344 | eeprom->use_eerd = FALSE; |
3345 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
3346 | break; |
3347 | case e1000_82540: | |
3348 | case e1000_82545: | |
3349 | case e1000_82545_rev_3: | |
3350 | case e1000_82546: | |
3351 | case e1000_82546_rev_3: | |
3352 | eeprom->type = e1000_eeprom_microwire; | |
3353 | eeprom->opcode_bits = 3; | |
3354 | eeprom->delay_usec = 50; | |
3355 | if(eecd & E1000_EECD_SIZE) { | |
3356 | eeprom->word_size = 256; | |
3357 | eeprom->address_bits = 8; | |
3358 | } else { | |
3359 | eeprom->word_size = 64; | |
3360 | eeprom->address_bits = 6; | |
3361 | } | |
2d7edb92 MC |
3362 | eeprom->use_eerd = FALSE; |
3363 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
3364 | break; |
3365 | case e1000_82541: | |
3366 | case e1000_82541_rev_2: | |
3367 | case e1000_82547: | |
3368 | case e1000_82547_rev_2: | |
3369 | if (eecd & E1000_EECD_TYPE) { | |
3370 | eeprom->type = e1000_eeprom_spi; | |
3371 | eeprom->opcode_bits = 8; | |
3372 | eeprom->delay_usec = 1; | |
3373 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3374 | eeprom->page_size = 32; | |
3375 | eeprom->address_bits = 16; | |
3376 | } else { | |
3377 | eeprom->page_size = 8; | |
3378 | eeprom->address_bits = 8; | |
3379 | } | |
3380 | } else { | |
3381 | eeprom->type = e1000_eeprom_microwire; | |
3382 | eeprom->opcode_bits = 3; | |
3383 | eeprom->delay_usec = 50; | |
3384 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3385 | eeprom->word_size = 256; | |
3386 | eeprom->address_bits = 8; | |
3387 | } else { | |
3388 | eeprom->word_size = 64; | |
3389 | eeprom->address_bits = 6; | |
3390 | } | |
3391 | } | |
2d7edb92 MC |
3392 | eeprom->use_eerd = FALSE; |
3393 | eeprom->use_eewr = FALSE; | |
3394 | break; | |
868d5309 MC |
3395 | case e1000_82571: |
3396 | case e1000_82572: | |
3397 | eeprom->type = e1000_eeprom_spi; | |
3398 | eeprom->opcode_bits = 8; | |
3399 | eeprom->delay_usec = 1; | |
3400 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3401 | eeprom->page_size = 32; | |
3402 | eeprom->address_bits = 16; | |
3403 | } else { | |
3404 | eeprom->page_size = 8; | |
3405 | eeprom->address_bits = 8; | |
3406 | } | |
3407 | eeprom->use_eerd = FALSE; | |
3408 | eeprom->use_eewr = FALSE; | |
3409 | break; | |
2d7edb92 MC |
3410 | case e1000_82573: |
3411 | eeprom->type = e1000_eeprom_spi; | |
3412 | eeprom->opcode_bits = 8; | |
3413 | eeprom->delay_usec = 1; | |
3414 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3415 | eeprom->page_size = 32; | |
3416 | eeprom->address_bits = 16; | |
3417 | } else { | |
3418 | eeprom->page_size = 8; | |
3419 | eeprom->address_bits = 8; | |
3420 | } | |
3421 | eeprom->use_eerd = TRUE; | |
3422 | eeprom->use_eewr = TRUE; | |
3423 | if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { | |
3424 | eeprom->type = e1000_eeprom_flash; | |
3425 | eeprom->word_size = 2048; | |
3426 | ||
3427 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
3428 | * Flash update issue on parts which use a FLASH for NVM. */ | |
3429 | eecd &= ~E1000_EECD_AUPDEN; | |
3430 | E1000_WRITE_REG(hw, EECD, eecd); | |
3431 | } | |
1da177e4 LT |
3432 | break; |
3433 | default: | |
3434 | break; | |
3435 | } | |
3436 | ||
3437 | if (eeprom->type == e1000_eeprom_spi) { | |
2d7edb92 MC |
3438 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
3439 | * 32KB (incremented by powers of 2). | |
3440 | */ | |
3441 | if(hw->mac_type <= e1000_82547_rev_2) { | |
3442 | /* Set to default value for initial eeprom read. */ | |
3443 | eeprom->word_size = 64; | |
3444 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); | |
3445 | if(ret_val) | |
3446 | return ret_val; | |
3447 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; | |
3448 | /* 256B eeprom size was not supported in earlier hardware, so we | |
3449 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) | |
3450 | * is never the result used in the shifting logic below. */ | |
3451 | if(eeprom_size) | |
3452 | eeprom_size++; | |
3453 | } else { | |
3454 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
3455 | E1000_EECD_SIZE_EX_SHIFT); | |
1da177e4 | 3456 | } |
2d7edb92 MC |
3457 | |
3458 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
1da177e4 | 3459 | } |
2d7edb92 | 3460 | return ret_val; |
1da177e4 LT |
3461 | } |
3462 | ||
3463 | /****************************************************************************** | |
3464 | * Raises the EEPROM's clock input. | |
3465 | * | |
3466 | * hw - Struct containing variables accessed by shared code | |
3467 | * eecd - EECD's current value | |
3468 | *****************************************************************************/ | |
3469 | static void | |
3470 | e1000_raise_ee_clk(struct e1000_hw *hw, | |
3471 | uint32_t *eecd) | |
3472 | { | |
3473 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
3474 | * wait <delay> microseconds. | |
3475 | */ | |
3476 | *eecd = *eecd | E1000_EECD_SK; | |
3477 | E1000_WRITE_REG(hw, EECD, *eecd); | |
3478 | E1000_WRITE_FLUSH(hw); | |
3479 | udelay(hw->eeprom.delay_usec); | |
3480 | } | |
3481 | ||
3482 | /****************************************************************************** | |
3483 | * Lowers the EEPROM's clock input. | |
3484 | * | |
3485 | * hw - Struct containing variables accessed by shared code | |
3486 | * eecd - EECD's current value | |
3487 | *****************************************************************************/ | |
3488 | static void | |
3489 | e1000_lower_ee_clk(struct e1000_hw *hw, | |
3490 | uint32_t *eecd) | |
3491 | { | |
3492 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | |
3493 | * wait 50 microseconds. | |
3494 | */ | |
3495 | *eecd = *eecd & ~E1000_EECD_SK; | |
3496 | E1000_WRITE_REG(hw, EECD, *eecd); | |
3497 | E1000_WRITE_FLUSH(hw); | |
3498 | udelay(hw->eeprom.delay_usec); | |
3499 | } | |
3500 | ||
3501 | /****************************************************************************** | |
3502 | * Shift data bits out to the EEPROM. | |
3503 | * | |
3504 | * hw - Struct containing variables accessed by shared code | |
3505 | * data - data to send to the EEPROM | |
3506 | * count - number of bits to shift out | |
3507 | *****************************************************************************/ | |
3508 | static void | |
3509 | e1000_shift_out_ee_bits(struct e1000_hw *hw, | |
3510 | uint16_t data, | |
3511 | uint16_t count) | |
3512 | { | |
3513 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3514 | uint32_t eecd; | |
3515 | uint32_t mask; | |
3516 | ||
3517 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
3518 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
3519 | * In order to do this, "data" must be broken down into bits. | |
3520 | */ | |
3521 | mask = 0x01 << (count - 1); | |
3522 | eecd = E1000_READ_REG(hw, EECD); | |
3523 | if (eeprom->type == e1000_eeprom_microwire) { | |
3524 | eecd &= ~E1000_EECD_DO; | |
3525 | } else if (eeprom->type == e1000_eeprom_spi) { | |
3526 | eecd |= E1000_EECD_DO; | |
3527 | } | |
3528 | do { | |
3529 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
3530 | * and then raising and then lowering the clock (the SK bit controls | |
3531 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
3532 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
3533 | */ | |
3534 | eecd &= ~E1000_EECD_DI; | |
3535 | ||
3536 | if(data & mask) | |
3537 | eecd |= E1000_EECD_DI; | |
3538 | ||
3539 | E1000_WRITE_REG(hw, EECD, eecd); | |
3540 | E1000_WRITE_FLUSH(hw); | |
3541 | ||
3542 | udelay(eeprom->delay_usec); | |
3543 | ||
3544 | e1000_raise_ee_clk(hw, &eecd); | |
3545 | e1000_lower_ee_clk(hw, &eecd); | |
3546 | ||
3547 | mask = mask >> 1; | |
3548 | ||
3549 | } while(mask); | |
3550 | ||
3551 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
3552 | eecd &= ~E1000_EECD_DI; | |
3553 | E1000_WRITE_REG(hw, EECD, eecd); | |
3554 | } | |
3555 | ||
3556 | /****************************************************************************** | |
3557 | * Shift data bits in from the EEPROM | |
3558 | * | |
3559 | * hw - Struct containing variables accessed by shared code | |
3560 | *****************************************************************************/ | |
3561 | static uint16_t | |
3562 | e1000_shift_in_ee_bits(struct e1000_hw *hw, | |
3563 | uint16_t count) | |
3564 | { | |
3565 | uint32_t eecd; | |
3566 | uint32_t i; | |
3567 | uint16_t data; | |
3568 | ||
3569 | /* In order to read a register from the EEPROM, we need to shift 'count' | |
3570 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
3571 | * input to the EEPROM (setting the SK bit), and then reading the value of | |
3572 | * the "DO" bit. During this "shifting in" process the "DI" bit should | |
3573 | * always be clear. | |
3574 | */ | |
3575 | ||
3576 | eecd = E1000_READ_REG(hw, EECD); | |
3577 | ||
3578 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
3579 | data = 0; | |
3580 | ||
3581 | for(i = 0; i < count; i++) { | |
3582 | data = data << 1; | |
3583 | e1000_raise_ee_clk(hw, &eecd); | |
3584 | ||
3585 | eecd = E1000_READ_REG(hw, EECD); | |
3586 | ||
3587 | eecd &= ~(E1000_EECD_DI); | |
3588 | if(eecd & E1000_EECD_DO) | |
3589 | data |= 1; | |
3590 | ||
3591 | e1000_lower_ee_clk(hw, &eecd); | |
3592 | } | |
3593 | ||
3594 | return data; | |
3595 | } | |
3596 | ||
3597 | /****************************************************************************** | |
3598 | * Prepares EEPROM for access | |
3599 | * | |
3600 | * hw - Struct containing variables accessed by shared code | |
3601 | * | |
3602 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
3603 | * function should be called before issuing a command to the EEPROM. | |
3604 | *****************************************************************************/ | |
3605 | static int32_t | |
3606 | e1000_acquire_eeprom(struct e1000_hw *hw) | |
3607 | { | |
3608 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3609 | uint32_t eecd, i=0; | |
3610 | ||
3611 | DEBUGFUNC("e1000_acquire_eeprom"); | |
3612 | ||
2d7edb92 MC |
3613 | if(e1000_get_hw_eeprom_semaphore(hw)) |
3614 | return -E1000_ERR_EEPROM; | |
3615 | ||
1da177e4 LT |
3616 | eecd = E1000_READ_REG(hw, EECD); |
3617 | ||
2d7edb92 | 3618 | if (hw->mac_type != e1000_82573) { |
868d5309 MC |
3619 | /* Request EEPROM Access */ |
3620 | if(hw->mac_type > e1000_82544) { | |
3621 | eecd |= E1000_EECD_REQ; | |
1da177e4 | 3622 | E1000_WRITE_REG(hw, EECD, eecd); |
868d5309 MC |
3623 | eecd = E1000_READ_REG(hw, EECD); |
3624 | while((!(eecd & E1000_EECD_GNT)) && | |
3625 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { | |
3626 | i++; | |
3627 | udelay(5); | |
3628 | eecd = E1000_READ_REG(hw, EECD); | |
3629 | } | |
3630 | if(!(eecd & E1000_EECD_GNT)) { | |
3631 | eecd &= ~E1000_EECD_REQ; | |
3632 | E1000_WRITE_REG(hw, EECD, eecd); | |
3633 | DEBUGOUT("Could not acquire EEPROM grant\n"); | |
3634 | e1000_put_hw_eeprom_semaphore(hw); | |
3635 | return -E1000_ERR_EEPROM; | |
3636 | } | |
1da177e4 LT |
3637 | } |
3638 | } | |
3639 | ||
3640 | /* Setup EEPROM for Read/Write */ | |
3641 | ||
3642 | if (eeprom->type == e1000_eeprom_microwire) { | |
3643 | /* Clear SK and DI */ | |
3644 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
3645 | E1000_WRITE_REG(hw, EECD, eecd); | |
3646 | ||
3647 | /* Set CS */ | |
3648 | eecd |= E1000_EECD_CS; | |
3649 | E1000_WRITE_REG(hw, EECD, eecd); | |
3650 | } else if (eeprom->type == e1000_eeprom_spi) { | |
3651 | /* Clear SK and CS */ | |
3652 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
3653 | E1000_WRITE_REG(hw, EECD, eecd); | |
3654 | udelay(1); | |
3655 | } | |
3656 | ||
3657 | return E1000_SUCCESS; | |
3658 | } | |
3659 | ||
3660 | /****************************************************************************** | |
3661 | * Returns EEPROM to a "standby" state | |
3662 | * | |
3663 | * hw - Struct containing variables accessed by shared code | |
3664 | *****************************************************************************/ | |
3665 | static void | |
3666 | e1000_standby_eeprom(struct e1000_hw *hw) | |
3667 | { | |
3668 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3669 | uint32_t eecd; | |
3670 | ||
3671 | eecd = E1000_READ_REG(hw, EECD); | |
3672 | ||
3673 | if(eeprom->type == e1000_eeprom_microwire) { | |
3674 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
3675 | E1000_WRITE_REG(hw, EECD, eecd); | |
3676 | E1000_WRITE_FLUSH(hw); | |
3677 | udelay(eeprom->delay_usec); | |
3678 | ||
3679 | /* Clock high */ | |
3680 | eecd |= E1000_EECD_SK; | |
3681 | E1000_WRITE_REG(hw, EECD, eecd); | |
3682 | E1000_WRITE_FLUSH(hw); | |
3683 | udelay(eeprom->delay_usec); | |
3684 | ||
3685 | /* Select EEPROM */ | |
3686 | eecd |= E1000_EECD_CS; | |
3687 | E1000_WRITE_REG(hw, EECD, eecd); | |
3688 | E1000_WRITE_FLUSH(hw); | |
3689 | udelay(eeprom->delay_usec); | |
3690 | ||
3691 | /* Clock low */ | |
3692 | eecd &= ~E1000_EECD_SK; | |
3693 | E1000_WRITE_REG(hw, EECD, eecd); | |
3694 | E1000_WRITE_FLUSH(hw); | |
3695 | udelay(eeprom->delay_usec); | |
3696 | } else if(eeprom->type == e1000_eeprom_spi) { | |
3697 | /* Toggle CS to flush commands */ | |
3698 | eecd |= E1000_EECD_CS; | |
3699 | E1000_WRITE_REG(hw, EECD, eecd); | |
3700 | E1000_WRITE_FLUSH(hw); | |
3701 | udelay(eeprom->delay_usec); | |
3702 | eecd &= ~E1000_EECD_CS; | |
3703 | E1000_WRITE_REG(hw, EECD, eecd); | |
3704 | E1000_WRITE_FLUSH(hw); | |
3705 | udelay(eeprom->delay_usec); | |
3706 | } | |
3707 | } | |
3708 | ||
3709 | /****************************************************************************** | |
3710 | * Terminates a command by inverting the EEPROM's chip select pin | |
3711 | * | |
3712 | * hw - Struct containing variables accessed by shared code | |
3713 | *****************************************************************************/ | |
3714 | static void | |
3715 | e1000_release_eeprom(struct e1000_hw *hw) | |
3716 | { | |
3717 | uint32_t eecd; | |
3718 | ||
3719 | DEBUGFUNC("e1000_release_eeprom"); | |
3720 | ||
3721 | eecd = E1000_READ_REG(hw, EECD); | |
3722 | ||
3723 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
3724 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
3725 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
3726 | ||
3727 | E1000_WRITE_REG(hw, EECD, eecd); | |
3728 | ||
3729 | udelay(hw->eeprom.delay_usec); | |
3730 | } else if(hw->eeprom.type == e1000_eeprom_microwire) { | |
3731 | /* cleanup eeprom */ | |
3732 | ||
3733 | /* CS on Microwire is active-high */ | |
3734 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
3735 | ||
3736 | E1000_WRITE_REG(hw, EECD, eecd); | |
3737 | ||
3738 | /* Rising edge of clock */ | |
3739 | eecd |= E1000_EECD_SK; | |
3740 | E1000_WRITE_REG(hw, EECD, eecd); | |
3741 | E1000_WRITE_FLUSH(hw); | |
3742 | udelay(hw->eeprom.delay_usec); | |
3743 | ||
3744 | /* Falling edge of clock */ | |
3745 | eecd &= ~E1000_EECD_SK; | |
3746 | E1000_WRITE_REG(hw, EECD, eecd); | |
3747 | E1000_WRITE_FLUSH(hw); | |
3748 | udelay(hw->eeprom.delay_usec); | |
3749 | } | |
3750 | ||
3751 | /* Stop requesting EEPROM access */ | |
3752 | if(hw->mac_type > e1000_82544) { | |
3753 | eecd &= ~E1000_EECD_REQ; | |
3754 | E1000_WRITE_REG(hw, EECD, eecd); | |
3755 | } | |
2d7edb92 MC |
3756 | |
3757 | e1000_put_hw_eeprom_semaphore(hw); | |
1da177e4 LT |
3758 | } |
3759 | ||
3760 | /****************************************************************************** | |
3761 | * Reads a 16 bit word from the EEPROM. | |
3762 | * | |
3763 | * hw - Struct containing variables accessed by shared code | |
3764 | *****************************************************************************/ | |
3765 | int32_t | |
3766 | e1000_spi_eeprom_ready(struct e1000_hw *hw) | |
3767 | { | |
3768 | uint16_t retry_count = 0; | |
3769 | uint8_t spi_stat_reg; | |
3770 | ||
3771 | DEBUGFUNC("e1000_spi_eeprom_ready"); | |
3772 | ||
3773 | /* Read "Status Register" repeatedly until the LSB is cleared. The | |
3774 | * EEPROM will signal that the command has been completed by clearing | |
3775 | * bit 0 of the internal status register. If it's not cleared within | |
3776 | * 5 milliseconds, then error out. | |
3777 | */ | |
3778 | retry_count = 0; | |
3779 | do { | |
3780 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
3781 | hw->eeprom.opcode_bits); | |
3782 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); | |
3783 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | |
3784 | break; | |
3785 | ||
3786 | udelay(5); | |
3787 | retry_count += 5; | |
3788 | ||
3789 | e1000_standby_eeprom(hw); | |
3790 | } while(retry_count < EEPROM_MAX_RETRY_SPI); | |
3791 | ||
3792 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
3793 | * only 0-5mSec on 5V devices) | |
3794 | */ | |
3795 | if(retry_count >= EEPROM_MAX_RETRY_SPI) { | |
3796 | DEBUGOUT("SPI EEPROM Status error\n"); | |
3797 | return -E1000_ERR_EEPROM; | |
3798 | } | |
3799 | ||
3800 | return E1000_SUCCESS; | |
3801 | } | |
3802 | ||
3803 | /****************************************************************************** | |
3804 | * Reads a 16 bit word from the EEPROM. | |
3805 | * | |
3806 | * hw - Struct containing variables accessed by shared code | |
3807 | * offset - offset of word in the EEPROM to read | |
3808 | * data - word read from the EEPROM | |
3809 | * words - number of words to read | |
3810 | *****************************************************************************/ | |
3811 | int32_t | |
3812 | e1000_read_eeprom(struct e1000_hw *hw, | |
3813 | uint16_t offset, | |
3814 | uint16_t words, | |
3815 | uint16_t *data) | |
3816 | { | |
3817 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3818 | uint32_t i = 0; | |
2d7edb92 | 3819 | int32_t ret_val; |
1da177e4 LT |
3820 | |
3821 | DEBUGFUNC("e1000_read_eeprom"); | |
2d7edb92 | 3822 | |
1da177e4 LT |
3823 | /* A check for invalid values: offset too large, too many words, and not |
3824 | * enough words. | |
3825 | */ | |
3826 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | |
3827 | (words == 0)) { | |
3828 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
3829 | return -E1000_ERR_EEPROM; | |
3830 | } | |
3831 | ||
2d7edb92 MC |
3832 | /* FLASH reads without acquiring the semaphore are safe in 82573-based |
3833 | * controllers. | |
3834 | */ | |
3835 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | |
3836 | (hw->mac_type != e1000_82573)) { | |
3837 | /* Prepare the EEPROM for reading */ | |
3838 | if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
3839 | return -E1000_ERR_EEPROM; | |
3840 | } | |
3841 | ||
3842 | if(eeprom->use_eerd == TRUE) { | |
3843 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); | |
3844 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | |
3845 | (hw->mac_type != e1000_82573)) | |
3846 | e1000_release_eeprom(hw); | |
3847 | return ret_val; | |
3848 | } | |
1da177e4 LT |
3849 | |
3850 | if(eeprom->type == e1000_eeprom_spi) { | |
3851 | uint16_t word_in; | |
3852 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; | |
3853 | ||
3854 | if(e1000_spi_eeprom_ready(hw)) { | |
3855 | e1000_release_eeprom(hw); | |
3856 | return -E1000_ERR_EEPROM; | |
3857 | } | |
3858 | ||
3859 | e1000_standby_eeprom(hw); | |
3860 | ||
3861 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
3862 | if((eeprom->address_bits == 8) && (offset >= 128)) | |
3863 | read_opcode |= EEPROM_A8_OPCODE_SPI; | |
3864 | ||
3865 | /* Send the READ command (opcode + addr) */ | |
3866 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
3867 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); | |
3868 | ||
3869 | /* Read the data. The address of the eeprom internally increments with | |
3870 | * each byte (spi) being read, saving on the overhead of eeprom setup | |
3871 | * and tear-down. The address counter will roll over if reading beyond | |
3872 | * the size of the eeprom, thus allowing the entire memory to be read | |
3873 | * starting from any offset. */ | |
3874 | for (i = 0; i < words; i++) { | |
3875 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
3876 | data[i] = (word_in >> 8) | (word_in << 8); | |
3877 | } | |
3878 | } else if(eeprom->type == e1000_eeprom_microwire) { | |
3879 | for (i = 0; i < words; i++) { | |
3880 | /* Send the READ command (opcode + addr) */ | |
3881 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, | |
3882 | eeprom->opcode_bits); | |
3883 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), | |
3884 | eeprom->address_bits); | |
3885 | ||
3886 | /* Read the data. For microwire, each word requires the overhead | |
3887 | * of eeprom setup and tear-down. */ | |
3888 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
3889 | e1000_standby_eeprom(hw); | |
3890 | } | |
3891 | } | |
3892 | ||
3893 | /* End this read operation */ | |
3894 | e1000_release_eeprom(hw); | |
3895 | ||
3896 | return E1000_SUCCESS; | |
3897 | } | |
3898 | ||
3899 | /****************************************************************************** | |
2d7edb92 | 3900 | * Reads a 16 bit word from the EEPROM using the EERD register. |
1da177e4 LT |
3901 | * |
3902 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
3903 | * offset - offset of word in the EEPROM to read |
3904 | * data - word read from the EEPROM | |
3905 | * words - number of words to read | |
1da177e4 LT |
3906 | *****************************************************************************/ |
3907 | int32_t | |
2d7edb92 MC |
3908 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
3909 | uint16_t offset, | |
3910 | uint16_t words, | |
3911 | uint16_t *data) | |
1da177e4 | 3912 | { |
2d7edb92 MC |
3913 | uint32_t i, eerd = 0; |
3914 | int32_t error = 0; | |
1da177e4 | 3915 | |
2d7edb92 MC |
3916 | for (i = 0; i < words; i++) { |
3917 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
3918 | E1000_EEPROM_RW_REG_START; | |
1da177e4 | 3919 | |
2d7edb92 MC |
3920 | E1000_WRITE_REG(hw, EERD, eerd); |
3921 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); | |
3922 | ||
3923 | if(error) { | |
3924 | break; | |
1da177e4 | 3925 | } |
2d7edb92 MC |
3926 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
3927 | ||
1da177e4 | 3928 | } |
2d7edb92 MC |
3929 | |
3930 | return error; | |
1da177e4 LT |
3931 | } |
3932 | ||
3933 | /****************************************************************************** | |
2d7edb92 | 3934 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
1da177e4 LT |
3935 | * |
3936 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
3937 | * offset - offset of word in the EEPROM to read |
3938 | * data - word read from the EEPROM | |
3939 | * words - number of words to read | |
1da177e4 LT |
3940 | *****************************************************************************/ |
3941 | int32_t | |
2d7edb92 MC |
3942 | e1000_write_eeprom_eewr(struct e1000_hw *hw, |
3943 | uint16_t offset, | |
3944 | uint16_t words, | |
3945 | uint16_t *data) | |
1da177e4 | 3946 | { |
2d7edb92 MC |
3947 | uint32_t register_value = 0; |
3948 | uint32_t i = 0; | |
3949 | int32_t error = 0; | |
1da177e4 | 3950 | |
2d7edb92 MC |
3951 | for (i = 0; i < words; i++) { |
3952 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | | |
3953 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | |
3954 | E1000_EEPROM_RW_REG_START; | |
1da177e4 | 3955 | |
2d7edb92 MC |
3956 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
3957 | if(error) { | |
3958 | break; | |
3959 | } | |
3960 | ||
3961 | E1000_WRITE_REG(hw, EEWR, register_value); | |
3962 | ||
3963 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); | |
3964 | ||
3965 | if(error) { | |
3966 | break; | |
3967 | } | |
3968 | } | |
3969 | ||
3970 | return error; | |
3971 | } | |
3972 | ||
3973 | /****************************************************************************** | |
3974 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
3975 | * | |
3976 | * hw - Struct containing variables accessed by shared code | |
3977 | *****************************************************************************/ | |
3978 | int32_t | |
3979 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) | |
3980 | { | |
3981 | uint32_t attempts = 100000; | |
3982 | uint32_t i, reg = 0; | |
3983 | int32_t done = E1000_ERR_EEPROM; | |
3984 | ||
3985 | for(i = 0; i < attempts; i++) { | |
3986 | if(eerd == E1000_EEPROM_POLL_READ) | |
3987 | reg = E1000_READ_REG(hw, EERD); | |
3988 | else | |
3989 | reg = E1000_READ_REG(hw, EEWR); | |
3990 | ||
3991 | if(reg & E1000_EEPROM_RW_REG_DONE) { | |
3992 | done = E1000_SUCCESS; | |
3993 | break; | |
3994 | } | |
3995 | udelay(5); | |
3996 | } | |
3997 | ||
3998 | return done; | |
3999 | } | |
4000 | ||
4001 | /*************************************************************************** | |
4002 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
4003 | * | |
4004 | * hw - Struct containing variables accessed by shared code | |
4005 | ****************************************************************************/ | |
4006 | boolean_t | |
4007 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) | |
4008 | { | |
4009 | uint32_t eecd = 0; | |
4010 | ||
4011 | if(hw->mac_type == e1000_82573) { | |
4012 | eecd = E1000_READ_REG(hw, EECD); | |
4013 | ||
4014 | /* Isolate bits 15 & 16 */ | |
4015 | eecd = ((eecd >> 15) & 0x03); | |
4016 | ||
4017 | /* If both bits are set, device is Flash type */ | |
4018 | if(eecd == 0x03) { | |
4019 | return FALSE; | |
4020 | } | |
4021 | } | |
4022 | return TRUE; | |
4023 | } | |
4024 | ||
4025 | /****************************************************************************** | |
4026 | * Verifies that the EEPROM has a valid checksum | |
4027 | * | |
4028 | * hw - Struct containing variables accessed by shared code | |
4029 | * | |
4030 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
4031 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
4032 | * valid. | |
4033 | *****************************************************************************/ | |
4034 | int32_t | |
4035 | e1000_validate_eeprom_checksum(struct e1000_hw *hw) | |
4036 | { | |
4037 | uint16_t checksum = 0; | |
4038 | uint16_t i, eeprom_data; | |
4039 | ||
4040 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | |
4041 | ||
4042 | if ((hw->mac_type == e1000_82573) && | |
4043 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { | |
4044 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | |
4045 | * 10h-12h. Checksum may need to be fixed. */ | |
4046 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | |
4047 | if ((eeprom_data & 0x10) == 0) { | |
4048 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | |
4049 | * has already been fixed. If the checksum is still wrong and this | |
4050 | * bit is a 1, we need to return bad checksum. Otherwise, we need | |
4051 | * to set this bit to a 1 and update the checksum. */ | |
4052 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | |
4053 | if ((eeprom_data & 0x8000) == 0) { | |
4054 | eeprom_data |= 0x8000; | |
4055 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | |
4056 | e1000_update_eeprom_checksum(hw); | |
4057 | } | |
4058 | } | |
4059 | } | |
4060 | ||
4061 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | |
4062 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
4063 | DEBUGOUT("EEPROM Read Error\n"); | |
4064 | return -E1000_ERR_EEPROM; | |
4065 | } | |
4066 | checksum += eeprom_data; | |
4067 | } | |
4068 | ||
4069 | if(checksum == (uint16_t) EEPROM_SUM) | |
4070 | return E1000_SUCCESS; | |
4071 | else { | |
4072 | DEBUGOUT("EEPROM Checksum Invalid\n"); | |
4073 | return -E1000_ERR_EEPROM; | |
4074 | } | |
4075 | } | |
4076 | ||
4077 | /****************************************************************************** | |
4078 | * Calculates the EEPROM checksum and writes it to the EEPROM | |
4079 | * | |
4080 | * hw - Struct containing variables accessed by shared code | |
4081 | * | |
4082 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | |
4083 | * Writes the difference to word offset 63 of the EEPROM. | |
4084 | *****************************************************************************/ | |
4085 | int32_t | |
4086 | e1000_update_eeprom_checksum(struct e1000_hw *hw) | |
4087 | { | |
4088 | uint16_t checksum = 0; | |
4089 | uint16_t i, eeprom_data; | |
4090 | ||
4091 | DEBUGFUNC("e1000_update_eeprom_checksum"); | |
4092 | ||
4093 | for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { | |
4094 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
4095 | DEBUGOUT("EEPROM Read Error\n"); | |
4096 | return -E1000_ERR_EEPROM; | |
4097 | } | |
4098 | checksum += eeprom_data; | |
4099 | } | |
4100 | checksum = (uint16_t) EEPROM_SUM - checksum; | |
1da177e4 LT |
4101 | if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
4102 | DEBUGOUT("EEPROM Write Error\n"); | |
4103 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
4104 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
4105 | e1000_commit_shadow_ram(hw); | |
1da177e4 LT |
4106 | } |
4107 | return E1000_SUCCESS; | |
4108 | } | |
4109 | ||
4110 | /****************************************************************************** | |
4111 | * Parent function for writing words to the different EEPROM types. | |
4112 | * | |
4113 | * hw - Struct containing variables accessed by shared code | |
4114 | * offset - offset within the EEPROM to be written to | |
4115 | * words - number of words to write | |
4116 | * data - 16 bit word to be written to the EEPROM | |
4117 | * | |
4118 | * If e1000_update_eeprom_checksum is not called after this function, the | |
4119 | * EEPROM will most likely contain an invalid checksum. | |
4120 | *****************************************************************************/ | |
4121 | int32_t | |
4122 | e1000_write_eeprom(struct e1000_hw *hw, | |
4123 | uint16_t offset, | |
4124 | uint16_t words, | |
4125 | uint16_t *data) | |
4126 | { | |
4127 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4128 | int32_t status = 0; | |
4129 | ||
4130 | DEBUGFUNC("e1000_write_eeprom"); | |
4131 | ||
4132 | /* A check for invalid values: offset too large, too many words, and not | |
4133 | * enough words. | |
4134 | */ | |
4135 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | |
4136 | (words == 0)) { | |
4137 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
4138 | return -E1000_ERR_EEPROM; | |
4139 | } | |
4140 | ||
868d5309 | 4141 | /* 82573 writes only through eewr */ |
2d7edb92 MC |
4142 | if(eeprom->use_eewr == TRUE) |
4143 | return e1000_write_eeprom_eewr(hw, offset, words, data); | |
4144 | ||
1da177e4 LT |
4145 | /* Prepare the EEPROM for writing */ |
4146 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
4147 | return -E1000_ERR_EEPROM; | |
4148 | ||
4149 | if(eeprom->type == e1000_eeprom_microwire) { | |
4150 | status = e1000_write_eeprom_microwire(hw, offset, words, data); | |
4151 | } else { | |
4152 | status = e1000_write_eeprom_spi(hw, offset, words, data); | |
4153 | msec_delay(10); | |
4154 | } | |
4155 | ||
4156 | /* Done with writing */ | |
4157 | e1000_release_eeprom(hw); | |
4158 | ||
4159 | return status; | |
4160 | } | |
4161 | ||
4162 | /****************************************************************************** | |
4163 | * Writes a 16 bit word to a given offset in an SPI EEPROM. | |
4164 | * | |
4165 | * hw - Struct containing variables accessed by shared code | |
4166 | * offset - offset within the EEPROM to be written to | |
4167 | * words - number of words to write | |
4168 | * data - pointer to array of 8 bit words to be written to the EEPROM | |
4169 | * | |
4170 | *****************************************************************************/ | |
4171 | int32_t | |
4172 | e1000_write_eeprom_spi(struct e1000_hw *hw, | |
4173 | uint16_t offset, | |
4174 | uint16_t words, | |
4175 | uint16_t *data) | |
4176 | { | |
4177 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4178 | uint16_t widx = 0; | |
4179 | ||
4180 | DEBUGFUNC("e1000_write_eeprom_spi"); | |
4181 | ||
4182 | while (widx < words) { | |
4183 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; | |
4184 | ||
4185 | if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; | |
4186 | ||
4187 | e1000_standby_eeprom(hw); | |
4188 | ||
4189 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
4190 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, | |
4191 | eeprom->opcode_bits); | |
4192 | ||
4193 | e1000_standby_eeprom(hw); | |
4194 | ||
4195 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
4196 | if((eeprom->address_bits == 8) && (offset >= 128)) | |
4197 | write_opcode |= EEPROM_A8_OPCODE_SPI; | |
4198 | ||
4199 | /* Send the Write command (8-bit opcode + addr) */ | |
4200 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); | |
4201 | ||
4202 | e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), | |
4203 | eeprom->address_bits); | |
4204 | ||
4205 | /* Send the data */ | |
4206 | ||
4207 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ | |
4208 | while (widx < words) { | |
4209 | uint16_t word_out = data[widx]; | |
4210 | word_out = (word_out >> 8) | (word_out << 8); | |
4211 | e1000_shift_out_ee_bits(hw, word_out, 16); | |
4212 | widx++; | |
4213 | ||
4214 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE | |
4215 | * operation, while the smaller eeproms are capable of an 8-byte | |
4216 | * PAGE WRITE operation. Break the inner loop to pass new address | |
4217 | */ | |
4218 | if((((offset + widx)*2) % eeprom->page_size) == 0) { | |
4219 | e1000_standby_eeprom(hw); | |
4220 | break; | |
4221 | } | |
4222 | } | |
4223 | } | |
4224 | ||
4225 | return E1000_SUCCESS; | |
4226 | } | |
4227 | ||
4228 | /****************************************************************************** | |
4229 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. | |
4230 | * | |
4231 | * hw - Struct containing variables accessed by shared code | |
4232 | * offset - offset within the EEPROM to be written to | |
4233 | * words - number of words to write | |
4234 | * data - pointer to array of 16 bit words to be written to the EEPROM | |
4235 | * | |
4236 | *****************************************************************************/ | |
4237 | int32_t | |
4238 | e1000_write_eeprom_microwire(struct e1000_hw *hw, | |
4239 | uint16_t offset, | |
4240 | uint16_t words, | |
4241 | uint16_t *data) | |
4242 | { | |
4243 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4244 | uint32_t eecd; | |
4245 | uint16_t words_written = 0; | |
4246 | uint16_t i = 0; | |
4247 | ||
4248 | DEBUGFUNC("e1000_write_eeprom_microwire"); | |
4249 | ||
4250 | /* Send the write enable command to the EEPROM (3-bit opcode plus | |
4251 | * 6/8-bit dummy address beginning with 11). It's less work to include | |
4252 | * the 11 of the dummy address as part of the opcode than it is to shift | |
4253 | * it over the correct number of bits for the address. This puts the | |
4254 | * EEPROM into write/erase mode. | |
4255 | */ | |
4256 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, | |
4257 | (uint16_t)(eeprom->opcode_bits + 2)); | |
4258 | ||
4259 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
4260 | ||
4261 | /* Prepare the EEPROM */ | |
4262 | e1000_standby_eeprom(hw); | |
4263 | ||
4264 | while (words_written < words) { | |
4265 | /* Send the Write command (3-bit opcode + addr) */ | |
4266 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, | |
4267 | eeprom->opcode_bits); | |
4268 | ||
4269 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), | |
4270 | eeprom->address_bits); | |
4271 | ||
4272 | /* Send the data */ | |
4273 | e1000_shift_out_ee_bits(hw, data[words_written], 16); | |
4274 | ||
4275 | /* Toggle the CS line. This in effect tells the EEPROM to execute | |
4276 | * the previous command. | |
4277 | */ | |
4278 | e1000_standby_eeprom(hw); | |
4279 | ||
4280 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will | |
4281 | * signal that the command has been completed by raising the DO signal. | |
4282 | * If DO does not go high in 10 milliseconds, then error out. | |
4283 | */ | |
4284 | for(i = 0; i < 200; i++) { | |
4285 | eecd = E1000_READ_REG(hw, EECD); | |
4286 | if(eecd & E1000_EECD_DO) break; | |
4287 | udelay(50); | |
4288 | } | |
4289 | if(i == 200) { | |
4290 | DEBUGOUT("EEPROM Write did not complete\n"); | |
4291 | return -E1000_ERR_EEPROM; | |
4292 | } | |
4293 | ||
4294 | /* Recover from write */ | |
4295 | e1000_standby_eeprom(hw); | |
4296 | ||
4297 | words_written++; | |
4298 | } | |
4299 | ||
4300 | /* Send the write disable command to the EEPROM (3-bit opcode plus | |
4301 | * 6/8-bit dummy address beginning with 10). It's less work to include | |
4302 | * the 10 of the dummy address as part of the opcode than it is to shift | |
4303 | * it over the correct number of bits for the address. This takes the | |
4304 | * EEPROM out of write/erase mode. | |
4305 | */ | |
4306 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, | |
4307 | (uint16_t)(eeprom->opcode_bits + 2)); | |
4308 | ||
4309 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
4310 | ||
4311 | return E1000_SUCCESS; | |
4312 | } | |
4313 | ||
2d7edb92 MC |
4314 | /****************************************************************************** |
4315 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | |
4316 | * in the eeprom cache and the non modified values in the currently active bank | |
4317 | * to the new bank. | |
4318 | * | |
4319 | * hw - Struct containing variables accessed by shared code | |
4320 | * offset - offset of word in the EEPROM to read | |
4321 | * data - word read from the EEPROM | |
4322 | * words - number of words to read | |
4323 | *****************************************************************************/ | |
4324 | int32_t | |
4325 | e1000_commit_shadow_ram(struct e1000_hw *hw) | |
4326 | { | |
4327 | uint32_t attempts = 100000; | |
4328 | uint32_t eecd = 0; | |
4329 | uint32_t flop = 0; | |
4330 | uint32_t i = 0; | |
4331 | int32_t error = E1000_SUCCESS; | |
4332 | ||
4333 | /* The flop register will be used to determine if flash type is STM */ | |
4334 | flop = E1000_READ_REG(hw, FLOP); | |
4335 | ||
4336 | if (hw->mac_type == e1000_82573) { | |
4337 | for (i=0; i < attempts; i++) { | |
4338 | eecd = E1000_READ_REG(hw, EECD); | |
4339 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
4340 | break; | |
4341 | } | |
4342 | udelay(5); | |
4343 | } | |
4344 | ||
4345 | if (i == attempts) { | |
4346 | return -E1000_ERR_EEPROM; | |
4347 | } | |
4348 | ||
4349 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ | |
4350 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { | |
4351 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); | |
4352 | } | |
4353 | ||
4354 | /* Perform the flash update */ | |
4355 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); | |
4356 | ||
4357 | for (i=0; i < attempts; i++) { | |
4358 | eecd = E1000_READ_REG(hw, EECD); | |
4359 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
4360 | break; | |
4361 | } | |
4362 | udelay(5); | |
4363 | } | |
4364 | ||
4365 | if (i == attempts) { | |
4366 | return -E1000_ERR_EEPROM; | |
4367 | } | |
4368 | } | |
4369 | ||
4370 | return error; | |
4371 | } | |
4372 | ||
1da177e4 LT |
4373 | /****************************************************************************** |
4374 | * Reads the adapter's part number from the EEPROM | |
4375 | * | |
4376 | * hw - Struct containing variables accessed by shared code | |
4377 | * part_num - Adapter's part number | |
4378 | *****************************************************************************/ | |
4379 | int32_t | |
4380 | e1000_read_part_num(struct e1000_hw *hw, | |
4381 | uint32_t *part_num) | |
4382 | { | |
4383 | uint16_t offset = EEPROM_PBA_BYTE_1; | |
4384 | uint16_t eeprom_data; | |
4385 | ||
4386 | DEBUGFUNC("e1000_read_part_num"); | |
4387 | ||
4388 | /* Get word 0 from EEPROM */ | |
4389 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | |
4390 | DEBUGOUT("EEPROM Read Error\n"); | |
4391 | return -E1000_ERR_EEPROM; | |
4392 | } | |
4393 | /* Save word 0 in upper half of part_num */ | |
4394 | *part_num = (uint32_t) (eeprom_data << 16); | |
4395 | ||
4396 | /* Get word 1 from EEPROM */ | |
4397 | if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { | |
4398 | DEBUGOUT("EEPROM Read Error\n"); | |
4399 | return -E1000_ERR_EEPROM; | |
4400 | } | |
4401 | /* Save word 1 in lower half of part_num */ | |
4402 | *part_num |= eeprom_data; | |
4403 | ||
4404 | return E1000_SUCCESS; | |
4405 | } | |
4406 | ||
4407 | /****************************************************************************** | |
4408 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
4409 | * second function of dual function devices | |
4410 | * | |
4411 | * hw - Struct containing variables accessed by shared code | |
4412 | *****************************************************************************/ | |
4413 | int32_t | |
4414 | e1000_read_mac_addr(struct e1000_hw * hw) | |
4415 | { | |
4416 | uint16_t offset; | |
4417 | uint16_t eeprom_data, i; | |
4418 | ||
4419 | DEBUGFUNC("e1000_read_mac_addr"); | |
4420 | ||
4421 | for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { | |
4422 | offset = i >> 1; | |
4423 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | |
4424 | DEBUGOUT("EEPROM Read Error\n"); | |
4425 | return -E1000_ERR_EEPROM; | |
4426 | } | |
4427 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); | |
4428 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); | |
4429 | } | |
868d5309 MC |
4430 | switch (hw->mac_type) { |
4431 | default: | |
4432 | break; | |
4433 | case e1000_82546: | |
4434 | case e1000_82546_rev_3: | |
4435 | case e1000_82571: | |
4436 | if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) | |
1da177e4 | 4437 | hw->perm_mac_addr[5] ^= 0x01; |
868d5309 MC |
4438 | break; |
4439 | } | |
1da177e4 LT |
4440 | |
4441 | for(i = 0; i < NODE_ADDRESS_SIZE; i++) | |
4442 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
4443 | return E1000_SUCCESS; | |
4444 | } | |
4445 | ||
4446 | /****************************************************************************** | |
4447 | * Initializes receive address filters. | |
4448 | * | |
4449 | * hw - Struct containing variables accessed by shared code | |
4450 | * | |
4451 | * Places the MAC address in receive address register 0 and clears the rest | |
4452 | * of the receive addresss registers. Clears the multicast table. Assumes | |
4453 | * the receiver is in reset when the routine is called. | |
4454 | *****************************************************************************/ | |
4455 | void | |
4456 | e1000_init_rx_addrs(struct e1000_hw *hw) | |
4457 | { | |
4458 | uint32_t i; | |
2d7edb92 | 4459 | uint32_t rar_num; |
1da177e4 LT |
4460 | |
4461 | DEBUGFUNC("e1000_init_rx_addrs"); | |
4462 | ||
4463 | /* Setup the receive address. */ | |
4464 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
4465 | ||
4466 | e1000_rar_set(hw, hw->mac_addr, 0); | |
4467 | ||
2d7edb92 | 4468 | rar_num = E1000_RAR_ENTRIES; |
868d5309 MC |
4469 | |
4470 | /* Reserve a spot for the Locally Administered Address to work around | |
4471 | * an 82571 issue in which a reset on one port will reload the MAC on | |
4472 | * the other port. */ | |
4473 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | |
4474 | rar_num -= 1; | |
1da177e4 LT |
4475 | /* Zero out the other 15 receive addresses. */ |
4476 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
2d7edb92 | 4477 | for(i = 1; i < rar_num; i++) { |
1da177e4 LT |
4478 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
4479 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
4480 | } | |
4481 | } | |
4482 | ||
4483 | /****************************************************************************** | |
4484 | * Updates the MAC's list of multicast addresses. | |
4485 | * | |
4486 | * hw - Struct containing variables accessed by shared code | |
4487 | * mc_addr_list - the list of new multicast addresses | |
4488 | * mc_addr_count - number of addresses | |
4489 | * pad - number of bytes between addresses in the list | |
4490 | * rar_used_count - offset where to start adding mc addresses into the RAR's | |
4491 | * | |
4492 | * The given list replaces any existing list. Clears the last 15 receive | |
4493 | * address registers and the multicast table. Uses receive address registers | |
4494 | * for the first 15 multicast addresses, and hashes the rest into the | |
4495 | * multicast table. | |
4496 | *****************************************************************************/ | |
4497 | void | |
4498 | e1000_mc_addr_list_update(struct e1000_hw *hw, | |
4499 | uint8_t *mc_addr_list, | |
4500 | uint32_t mc_addr_count, | |
4501 | uint32_t pad, | |
4502 | uint32_t rar_used_count) | |
4503 | { | |
4504 | uint32_t hash_value; | |
4505 | uint32_t i; | |
2d7edb92 MC |
4506 | uint32_t num_rar_entry; |
4507 | uint32_t num_mta_entry; | |
4508 | ||
1da177e4 LT |
4509 | DEBUGFUNC("e1000_mc_addr_list_update"); |
4510 | ||
4511 | /* Set the new number of MC addresses that we are being requested to use. */ | |
4512 | hw->num_mc_addrs = mc_addr_count; | |
4513 | ||
4514 | /* Clear RAR[1-15] */ | |
4515 | DEBUGOUT(" Clearing RAR[1-15]\n"); | |
2d7edb92 | 4516 | num_rar_entry = E1000_RAR_ENTRIES; |
868d5309 MC |
4517 | /* Reserve a spot for the Locally Administered Address to work around |
4518 | * an 82571 issue in which a reset on one port will reload the MAC on | |
4519 | * the other port. */ | |
4520 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | |
4521 | num_rar_entry -= 1; | |
4522 | ||
2d7edb92 | 4523 | for(i = rar_used_count; i < num_rar_entry; i++) { |
1da177e4 LT |
4524 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
4525 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
4526 | } | |
4527 | ||
4528 | /* Clear the MTA */ | |
4529 | DEBUGOUT(" Clearing MTA\n"); | |
2d7edb92 MC |
4530 | num_mta_entry = E1000_NUM_MTA_REGISTERS; |
4531 | for(i = 0; i < num_mta_entry; i++) { | |
1da177e4 LT |
4532 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
4533 | } | |
4534 | ||
4535 | /* Add the new addresses */ | |
4536 | for(i = 0; i < mc_addr_count; i++) { | |
4537 | DEBUGOUT(" Adding the multicast addresses:\n"); | |
4538 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, | |
4539 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], | |
4540 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], | |
4541 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], | |
4542 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], | |
4543 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], | |
4544 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); | |
4545 | ||
4546 | hash_value = e1000_hash_mc_addr(hw, | |
4547 | mc_addr_list + | |
4548 | (i * (ETH_LENGTH_OF_ADDRESS + pad))); | |
4549 | ||
4550 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); | |
4551 | ||
4552 | /* Place this multicast address in the RAR if there is room, * | |
4553 | * else put it in the MTA | |
4554 | */ | |
2d7edb92 | 4555 | if (rar_used_count < num_rar_entry) { |
1da177e4 LT |
4556 | e1000_rar_set(hw, |
4557 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), | |
4558 | rar_used_count); | |
4559 | rar_used_count++; | |
4560 | } else { | |
4561 | e1000_mta_set(hw, hash_value); | |
4562 | } | |
4563 | } | |
4564 | DEBUGOUT("MC Update Complete\n"); | |
4565 | } | |
4566 | ||
4567 | /****************************************************************************** | |
4568 | * Hashes an address to determine its location in the multicast table | |
4569 | * | |
4570 | * hw - Struct containing variables accessed by shared code | |
4571 | * mc_addr - the multicast address to hash | |
4572 | *****************************************************************************/ | |
4573 | uint32_t | |
4574 | e1000_hash_mc_addr(struct e1000_hw *hw, | |
4575 | uint8_t *mc_addr) | |
4576 | { | |
4577 | uint32_t hash_value = 0; | |
4578 | ||
4579 | /* The portion of the address that is used for the hash table is | |
4580 | * determined by the mc_filter_type setting. | |
4581 | */ | |
4582 | switch (hw->mc_filter_type) { | |
4583 | /* [0] [1] [2] [3] [4] [5] | |
4584 | * 01 AA 00 12 34 56 | |
4585 | * LSB MSB | |
4586 | */ | |
4587 | case 0: | |
4588 | /* [47:36] i.e. 0x563 for above example address */ | |
4589 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); | |
4590 | break; | |
4591 | case 1: | |
4592 | /* [46:35] i.e. 0xAC6 for above example address */ | |
4593 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); | |
4594 | break; | |
4595 | case 2: | |
4596 | /* [45:34] i.e. 0x5D8 for above example address */ | |
4597 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); | |
4598 | break; | |
4599 | case 3: | |
4600 | /* [43:32] i.e. 0x634 for above example address */ | |
4601 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); | |
4602 | break; | |
4603 | } | |
4604 | ||
4605 | hash_value &= 0xFFF; | |
2d7edb92 | 4606 | |
1da177e4 LT |
4607 | return hash_value; |
4608 | } | |
4609 | ||
4610 | /****************************************************************************** | |
4611 | * Sets the bit in the multicast table corresponding to the hash value. | |
4612 | * | |
4613 | * hw - Struct containing variables accessed by shared code | |
4614 | * hash_value - Multicast address hash value | |
4615 | *****************************************************************************/ | |
4616 | void | |
4617 | e1000_mta_set(struct e1000_hw *hw, | |
4618 | uint32_t hash_value) | |
4619 | { | |
4620 | uint32_t hash_bit, hash_reg; | |
4621 | uint32_t mta; | |
4622 | uint32_t temp; | |
4623 | ||
4624 | /* The MTA is a register array of 128 32-bit registers. | |
4625 | * It is treated like an array of 4096 bits. We want to set | |
4626 | * bit BitArray[hash_value]. So we figure out what register | |
4627 | * the bit is in, read it, OR in the new bit, then write | |
4628 | * back the new value. The register is determined by the | |
4629 | * upper 7 bits of the hash value and the bit within that | |
4630 | * register are determined by the lower 5 bits of the value. | |
4631 | */ | |
4632 | hash_reg = (hash_value >> 5) & 0x7F; | |
4633 | hash_bit = hash_value & 0x1F; | |
4634 | ||
4635 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); | |
4636 | ||
4637 | mta |= (1 << hash_bit); | |
4638 | ||
4639 | /* If we are on an 82544 and we are trying to write an odd offset | |
4640 | * in the MTA, save off the previous entry before writing and | |
4641 | * restore the old value after writing. | |
4642 | */ | |
4643 | if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { | |
4644 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); | |
4645 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
4646 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); | |
4647 | } else { | |
4648 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
4649 | } | |
4650 | } | |
4651 | ||
4652 | /****************************************************************************** | |
4653 | * Puts an ethernet address into a receive address register. | |
4654 | * | |
4655 | * hw - Struct containing variables accessed by shared code | |
4656 | * addr - Address to put into receive address register | |
4657 | * index - Receive address register to write | |
4658 | *****************************************************************************/ | |
4659 | void | |
4660 | e1000_rar_set(struct e1000_hw *hw, | |
4661 | uint8_t *addr, | |
4662 | uint32_t index) | |
4663 | { | |
4664 | uint32_t rar_low, rar_high; | |
4665 | ||
4666 | /* HW expects these in little endian so we reverse the byte order | |
4667 | * from network order (big endian) to little endian | |
4668 | */ | |
4669 | rar_low = ((uint32_t) addr[0] | | |
4670 | ((uint32_t) addr[1] << 8) | | |
4671 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); | |
4672 | ||
4673 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV); | |
4674 | ||
4675 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); | |
4676 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); | |
4677 | } | |
4678 | ||
4679 | /****************************************************************************** | |
4680 | * Writes a value to the specified offset in the VLAN filter table. | |
4681 | * | |
4682 | * hw - Struct containing variables accessed by shared code | |
4683 | * offset - Offset in VLAN filer table to write | |
4684 | * value - Value to write into VLAN filter table | |
4685 | *****************************************************************************/ | |
4686 | void | |
4687 | e1000_write_vfta(struct e1000_hw *hw, | |
4688 | uint32_t offset, | |
4689 | uint32_t value) | |
4690 | { | |
4691 | uint32_t temp; | |
4692 | ||
4693 | if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { | |
4694 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); | |
4695 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
4696 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); | |
4697 | } else { | |
4698 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
4699 | } | |
4700 | } | |
4701 | ||
4702 | /****************************************************************************** | |
4703 | * Clears the VLAN filer table | |
4704 | * | |
4705 | * hw - Struct containing variables accessed by shared code | |
4706 | *****************************************************************************/ | |
4707 | void | |
4708 | e1000_clear_vfta(struct e1000_hw *hw) | |
4709 | { | |
4710 | uint32_t offset; | |
2d7edb92 MC |
4711 | uint32_t vfta_value = 0; |
4712 | uint32_t vfta_offset = 0; | |
4713 | uint32_t vfta_bit_in_reg = 0; | |
4714 | ||
4715 | if (hw->mac_type == e1000_82573) { | |
4716 | if (hw->mng_cookie.vlan_id != 0) { | |
4717 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | |
4718 | * ID. The following operations determine which 32b entry | |
4719 | * (i.e. offset) into the array we want to set the VLAN ID | |
4720 | * (i.e. bit) of the manageability unit. */ | |
4721 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
4722 | E1000_VFTA_ENTRY_SHIFT) & | |
4723 | E1000_VFTA_ENTRY_MASK; | |
4724 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
4725 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
4726 | } | |
4727 | } | |
4728 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
4729 | /* If the offset we want to clear is the same offset of the | |
4730 | * manageability VLAN ID, then clear all bits except that of the | |
4731 | * manageability unit */ | |
4732 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
4733 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | |
4734 | } | |
1da177e4 LT |
4735 | } |
4736 | ||
2d7edb92 | 4737 | int32_t |
1da177e4 LT |
4738 | e1000_id_led_init(struct e1000_hw * hw) |
4739 | { | |
4740 | uint32_t ledctl; | |
4741 | const uint32_t ledctl_mask = 0x000000FF; | |
4742 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
4743 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
4744 | uint16_t eeprom_data, i, temp; | |
4745 | const uint16_t led_mask = 0x0F; | |
4746 | ||
4747 | DEBUGFUNC("e1000_id_led_init"); | |
4748 | ||
4749 | if(hw->mac_type < e1000_82540) { | |
4750 | /* Nothing to do */ | |
4751 | return E1000_SUCCESS; | |
4752 | } | |
4753 | ||
4754 | ledctl = E1000_READ_REG(hw, LEDCTL); | |
4755 | hw->ledctl_default = ledctl; | |
4756 | hw->ledctl_mode1 = hw->ledctl_default; | |
4757 | hw->ledctl_mode2 = hw->ledctl_default; | |
4758 | ||
4759 | if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { | |
4760 | DEBUGOUT("EEPROM Read Error\n"); | |
4761 | return -E1000_ERR_EEPROM; | |
4762 | } | |
4763 | if((eeprom_data== ID_LED_RESERVED_0000) || | |
4764 | (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; | |
4765 | for(i = 0; i < 4; i++) { | |
4766 | temp = (eeprom_data >> (i << 2)) & led_mask; | |
4767 | switch(temp) { | |
4768 | case ID_LED_ON1_DEF2: | |
4769 | case ID_LED_ON1_ON2: | |
4770 | case ID_LED_ON1_OFF2: | |
4771 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
4772 | hw->ledctl_mode1 |= ledctl_on << (i << 3); | |
4773 | break; | |
4774 | case ID_LED_OFF1_DEF2: | |
4775 | case ID_LED_OFF1_ON2: | |
4776 | case ID_LED_OFF1_OFF2: | |
4777 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
4778 | hw->ledctl_mode1 |= ledctl_off << (i << 3); | |
4779 | break; | |
4780 | default: | |
4781 | /* Do nothing */ | |
4782 | break; | |
4783 | } | |
4784 | switch(temp) { | |
4785 | case ID_LED_DEF1_ON2: | |
4786 | case ID_LED_ON1_ON2: | |
4787 | case ID_LED_OFF1_ON2: | |
4788 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
4789 | hw->ledctl_mode2 |= ledctl_on << (i << 3); | |
4790 | break; | |
4791 | case ID_LED_DEF1_OFF2: | |
4792 | case ID_LED_ON1_OFF2: | |
4793 | case ID_LED_OFF1_OFF2: | |
4794 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
4795 | hw->ledctl_mode2 |= ledctl_off << (i << 3); | |
4796 | break; | |
4797 | default: | |
4798 | /* Do nothing */ | |
4799 | break; | |
4800 | } | |
4801 | } | |
4802 | return E1000_SUCCESS; | |
4803 | } | |
4804 | ||
4805 | /****************************************************************************** | |
4806 | * Prepares SW controlable LED for use and saves the current state of the LED. | |
4807 | * | |
4808 | * hw - Struct containing variables accessed by shared code | |
4809 | *****************************************************************************/ | |
4810 | int32_t | |
4811 | e1000_setup_led(struct e1000_hw *hw) | |
4812 | { | |
4813 | uint32_t ledctl; | |
4814 | int32_t ret_val = E1000_SUCCESS; | |
4815 | ||
4816 | DEBUGFUNC("e1000_setup_led"); | |
4817 | ||
4818 | switch(hw->mac_type) { | |
4819 | case e1000_82542_rev2_0: | |
4820 | case e1000_82542_rev2_1: | |
4821 | case e1000_82543: | |
4822 | case e1000_82544: | |
4823 | /* No setup necessary */ | |
4824 | break; | |
4825 | case e1000_82541: | |
4826 | case e1000_82547: | |
4827 | case e1000_82541_rev_2: | |
4828 | case e1000_82547_rev_2: | |
4829 | /* Turn off PHY Smart Power Down (if enabled) */ | |
4830 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
4831 | &hw->phy_spd_default); | |
4832 | if(ret_val) | |
4833 | return ret_val; | |
4834 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
4835 | (uint16_t)(hw->phy_spd_default & | |
4836 | ~IGP01E1000_GMII_SPD)); | |
4837 | if(ret_val) | |
4838 | return ret_val; | |
4839 | /* Fall Through */ | |
4840 | default: | |
4841 | if(hw->media_type == e1000_media_type_fiber) { | |
4842 | ledctl = E1000_READ_REG(hw, LEDCTL); | |
4843 | /* Save current LEDCTL settings */ | |
4844 | hw->ledctl_default = ledctl; | |
4845 | /* Turn off LED0 */ | |
4846 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | | |
4847 | E1000_LEDCTL_LED0_BLINK | | |
4848 | E1000_LEDCTL_LED0_MODE_MASK); | |
4849 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
4850 | E1000_LEDCTL_LED0_MODE_SHIFT); | |
4851 | E1000_WRITE_REG(hw, LEDCTL, ledctl); | |
4852 | } else if(hw->media_type == e1000_media_type_copper) | |
4853 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); | |
4854 | break; | |
4855 | } | |
4856 | ||
4857 | return E1000_SUCCESS; | |
4858 | } | |
4859 | ||
4860 | /****************************************************************************** | |
4861 | * Restores the saved state of the SW controlable LED. | |
4862 | * | |
4863 | * hw - Struct containing variables accessed by shared code | |
4864 | *****************************************************************************/ | |
4865 | int32_t | |
4866 | e1000_cleanup_led(struct e1000_hw *hw) | |
4867 | { | |
4868 | int32_t ret_val = E1000_SUCCESS; | |
4869 | ||
4870 | DEBUGFUNC("e1000_cleanup_led"); | |
4871 | ||
4872 | switch(hw->mac_type) { | |
4873 | case e1000_82542_rev2_0: | |
4874 | case e1000_82542_rev2_1: | |
4875 | case e1000_82543: | |
4876 | case e1000_82544: | |
4877 | /* No cleanup necessary */ | |
4878 | break; | |
4879 | case e1000_82541: | |
4880 | case e1000_82547: | |
4881 | case e1000_82541_rev_2: | |
4882 | case e1000_82547_rev_2: | |
4883 | /* Turn on PHY Smart Power Down (if previously enabled) */ | |
4884 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
4885 | hw->phy_spd_default); | |
4886 | if(ret_val) | |
4887 | return ret_val; | |
4888 | /* Fall Through */ | |
4889 | default: | |
4890 | /* Restore LEDCTL settings */ | |
4891 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); | |
4892 | break; | |
4893 | } | |
4894 | ||
4895 | return E1000_SUCCESS; | |
4896 | } | |
4897 | ||
4898 | /****************************************************************************** | |
4899 | * Turns on the software controllable LED | |
4900 | * | |
4901 | * hw - Struct containing variables accessed by shared code | |
4902 | *****************************************************************************/ | |
4903 | int32_t | |
4904 | e1000_led_on(struct e1000_hw *hw) | |
4905 | { | |
4906 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
4907 | ||
4908 | DEBUGFUNC("e1000_led_on"); | |
4909 | ||
4910 | switch(hw->mac_type) { | |
4911 | case e1000_82542_rev2_0: | |
4912 | case e1000_82542_rev2_1: | |
4913 | case e1000_82543: | |
4914 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
4915 | ctrl |= E1000_CTRL_SWDPIN0; | |
4916 | ctrl |= E1000_CTRL_SWDPIO0; | |
4917 | break; | |
4918 | case e1000_82544: | |
4919 | if(hw->media_type == e1000_media_type_fiber) { | |
4920 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
4921 | ctrl |= E1000_CTRL_SWDPIN0; | |
4922 | ctrl |= E1000_CTRL_SWDPIO0; | |
4923 | } else { | |
4924 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
4925 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
4926 | ctrl |= E1000_CTRL_SWDPIO0; | |
4927 | } | |
4928 | break; | |
4929 | default: | |
4930 | if(hw->media_type == e1000_media_type_fiber) { | |
4931 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
4932 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
4933 | ctrl |= E1000_CTRL_SWDPIO0; | |
4934 | } else if(hw->media_type == e1000_media_type_copper) { | |
4935 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); | |
4936 | return E1000_SUCCESS; | |
4937 | } | |
4938 | break; | |
4939 | } | |
4940 | ||
4941 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4942 | ||
4943 | return E1000_SUCCESS; | |
4944 | } | |
4945 | ||
4946 | /****************************************************************************** | |
4947 | * Turns off the software controllable LED | |
4948 | * | |
4949 | * hw - Struct containing variables accessed by shared code | |
4950 | *****************************************************************************/ | |
4951 | int32_t | |
4952 | e1000_led_off(struct e1000_hw *hw) | |
4953 | { | |
4954 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
4955 | ||
4956 | DEBUGFUNC("e1000_led_off"); | |
4957 | ||
4958 | switch(hw->mac_type) { | |
4959 | case e1000_82542_rev2_0: | |
4960 | case e1000_82542_rev2_1: | |
4961 | case e1000_82543: | |
4962 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
4963 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
4964 | ctrl |= E1000_CTRL_SWDPIO0; | |
4965 | break; | |
4966 | case e1000_82544: | |
4967 | if(hw->media_type == e1000_media_type_fiber) { | |
4968 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
4969 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
4970 | ctrl |= E1000_CTRL_SWDPIO0; | |
4971 | } else { | |
4972 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
4973 | ctrl |= E1000_CTRL_SWDPIN0; | |
4974 | ctrl |= E1000_CTRL_SWDPIO0; | |
4975 | } | |
4976 | break; | |
4977 | default: | |
4978 | if(hw->media_type == e1000_media_type_fiber) { | |
4979 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
4980 | ctrl |= E1000_CTRL_SWDPIN0; | |
4981 | ctrl |= E1000_CTRL_SWDPIO0; | |
4982 | } else if(hw->media_type == e1000_media_type_copper) { | |
4983 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); | |
4984 | return E1000_SUCCESS; | |
4985 | } | |
4986 | break; | |
4987 | } | |
4988 | ||
4989 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
4990 | ||
4991 | return E1000_SUCCESS; | |
4992 | } | |
4993 | ||
4994 | /****************************************************************************** | |
4995 | * Clears all hardware statistics counters. | |
4996 | * | |
4997 | * hw - Struct containing variables accessed by shared code | |
4998 | *****************************************************************************/ | |
4999 | void | |
5000 | e1000_clear_hw_cntrs(struct e1000_hw *hw) | |
5001 | { | |
5002 | volatile uint32_t temp; | |
5003 | ||
5004 | temp = E1000_READ_REG(hw, CRCERRS); | |
5005 | temp = E1000_READ_REG(hw, SYMERRS); | |
5006 | temp = E1000_READ_REG(hw, MPC); | |
5007 | temp = E1000_READ_REG(hw, SCC); | |
5008 | temp = E1000_READ_REG(hw, ECOL); | |
5009 | temp = E1000_READ_REG(hw, MCC); | |
5010 | temp = E1000_READ_REG(hw, LATECOL); | |
5011 | temp = E1000_READ_REG(hw, COLC); | |
5012 | temp = E1000_READ_REG(hw, DC); | |
5013 | temp = E1000_READ_REG(hw, SEC); | |
5014 | temp = E1000_READ_REG(hw, RLEC); | |
5015 | temp = E1000_READ_REG(hw, XONRXC); | |
5016 | temp = E1000_READ_REG(hw, XONTXC); | |
5017 | temp = E1000_READ_REG(hw, XOFFRXC); | |
5018 | temp = E1000_READ_REG(hw, XOFFTXC); | |
5019 | temp = E1000_READ_REG(hw, FCRUC); | |
5020 | temp = E1000_READ_REG(hw, PRC64); | |
5021 | temp = E1000_READ_REG(hw, PRC127); | |
5022 | temp = E1000_READ_REG(hw, PRC255); | |
5023 | temp = E1000_READ_REG(hw, PRC511); | |
5024 | temp = E1000_READ_REG(hw, PRC1023); | |
5025 | temp = E1000_READ_REG(hw, PRC1522); | |
5026 | temp = E1000_READ_REG(hw, GPRC); | |
5027 | temp = E1000_READ_REG(hw, BPRC); | |
5028 | temp = E1000_READ_REG(hw, MPRC); | |
5029 | temp = E1000_READ_REG(hw, GPTC); | |
5030 | temp = E1000_READ_REG(hw, GORCL); | |
5031 | temp = E1000_READ_REG(hw, GORCH); | |
5032 | temp = E1000_READ_REG(hw, GOTCL); | |
5033 | temp = E1000_READ_REG(hw, GOTCH); | |
5034 | temp = E1000_READ_REG(hw, RNBC); | |
5035 | temp = E1000_READ_REG(hw, RUC); | |
5036 | temp = E1000_READ_REG(hw, RFC); | |
5037 | temp = E1000_READ_REG(hw, ROC); | |
5038 | temp = E1000_READ_REG(hw, RJC); | |
5039 | temp = E1000_READ_REG(hw, TORL); | |
5040 | temp = E1000_READ_REG(hw, TORH); | |
5041 | temp = E1000_READ_REG(hw, TOTL); | |
5042 | temp = E1000_READ_REG(hw, TOTH); | |
5043 | temp = E1000_READ_REG(hw, TPR); | |
5044 | temp = E1000_READ_REG(hw, TPT); | |
5045 | temp = E1000_READ_REG(hw, PTC64); | |
5046 | temp = E1000_READ_REG(hw, PTC127); | |
5047 | temp = E1000_READ_REG(hw, PTC255); | |
5048 | temp = E1000_READ_REG(hw, PTC511); | |
5049 | temp = E1000_READ_REG(hw, PTC1023); | |
5050 | temp = E1000_READ_REG(hw, PTC1522); | |
5051 | temp = E1000_READ_REG(hw, MPTC); | |
5052 | temp = E1000_READ_REG(hw, BPTC); | |
5053 | ||
5054 | if(hw->mac_type < e1000_82543) return; | |
5055 | ||
5056 | temp = E1000_READ_REG(hw, ALGNERRC); | |
5057 | temp = E1000_READ_REG(hw, RXERRC); | |
5058 | temp = E1000_READ_REG(hw, TNCRS); | |
5059 | temp = E1000_READ_REG(hw, CEXTERR); | |
5060 | temp = E1000_READ_REG(hw, TSCTC); | |
5061 | temp = E1000_READ_REG(hw, TSCTFC); | |
5062 | ||
5063 | if(hw->mac_type <= e1000_82544) return; | |
5064 | ||
5065 | temp = E1000_READ_REG(hw, MGTPRC); | |
5066 | temp = E1000_READ_REG(hw, MGTPDC); | |
5067 | temp = E1000_READ_REG(hw, MGTPTC); | |
2d7edb92 MC |
5068 | |
5069 | if(hw->mac_type <= e1000_82547_rev_2) return; | |
5070 | ||
5071 | temp = E1000_READ_REG(hw, IAC); | |
5072 | temp = E1000_READ_REG(hw, ICRXOC); | |
5073 | temp = E1000_READ_REG(hw, ICRXPTC); | |
5074 | temp = E1000_READ_REG(hw, ICRXATC); | |
5075 | temp = E1000_READ_REG(hw, ICTXPTC); | |
5076 | temp = E1000_READ_REG(hw, ICTXATC); | |
5077 | temp = E1000_READ_REG(hw, ICTXQEC); | |
5078 | temp = E1000_READ_REG(hw, ICTXQMTC); | |
5079 | temp = E1000_READ_REG(hw, ICRXDMTC); | |
1da177e4 LT |
5080 | } |
5081 | ||
5082 | /****************************************************************************** | |
5083 | * Resets Adaptive IFS to its default state. | |
5084 | * | |
5085 | * hw - Struct containing variables accessed by shared code | |
5086 | * | |
5087 | * Call this after e1000_init_hw. You may override the IFS defaults by setting | |
5088 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> | |
5089 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio | |
5090 | * before calling this function. | |
5091 | *****************************************************************************/ | |
5092 | void | |
5093 | e1000_reset_adaptive(struct e1000_hw *hw) | |
5094 | { | |
5095 | DEBUGFUNC("e1000_reset_adaptive"); | |
5096 | ||
5097 | if(hw->adaptive_ifs) { | |
5098 | if(!hw->ifs_params_forced) { | |
5099 | hw->current_ifs_val = 0; | |
5100 | hw->ifs_min_val = IFS_MIN; | |
5101 | hw->ifs_max_val = IFS_MAX; | |
5102 | hw->ifs_step_size = IFS_STEP; | |
5103 | hw->ifs_ratio = IFS_RATIO; | |
5104 | } | |
5105 | hw->in_ifs_mode = FALSE; | |
5106 | E1000_WRITE_REG(hw, AIT, 0); | |
5107 | } else { | |
5108 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
5109 | } | |
5110 | } | |
5111 | ||
5112 | /****************************************************************************** | |
5113 | * Called during the callback/watchdog routine to update IFS value based on | |
5114 | * the ratio of transmits to collisions. | |
5115 | * | |
5116 | * hw - Struct containing variables accessed by shared code | |
5117 | * tx_packets - Number of transmits since last callback | |
5118 | * total_collisions - Number of collisions since last callback | |
5119 | *****************************************************************************/ | |
5120 | void | |
5121 | e1000_update_adaptive(struct e1000_hw *hw) | |
5122 | { | |
5123 | DEBUGFUNC("e1000_update_adaptive"); | |
5124 | ||
5125 | if(hw->adaptive_ifs) { | |
5126 | if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { | |
5127 | if(hw->tx_packet_delta > MIN_NUM_XMITS) { | |
5128 | hw->in_ifs_mode = TRUE; | |
5129 | if(hw->current_ifs_val < hw->ifs_max_val) { | |
5130 | if(hw->current_ifs_val == 0) | |
5131 | hw->current_ifs_val = hw->ifs_min_val; | |
5132 | else | |
5133 | hw->current_ifs_val += hw->ifs_step_size; | |
5134 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); | |
5135 | } | |
5136 | } | |
5137 | } else { | |
5138 | if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { | |
5139 | hw->current_ifs_val = 0; | |
5140 | hw->in_ifs_mode = FALSE; | |
5141 | E1000_WRITE_REG(hw, AIT, 0); | |
5142 | } | |
5143 | } | |
5144 | } else { | |
5145 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
5146 | } | |
5147 | } | |
5148 | ||
5149 | /****************************************************************************** | |
5150 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT | |
5151 | * | |
5152 | * hw - Struct containing variables accessed by shared code | |
5153 | * frame_len - The length of the frame in question | |
5154 | * mac_addr - The Ethernet destination address of the frame in question | |
5155 | *****************************************************************************/ | |
5156 | void | |
5157 | e1000_tbi_adjust_stats(struct e1000_hw *hw, | |
5158 | struct e1000_hw_stats *stats, | |
5159 | uint32_t frame_len, | |
5160 | uint8_t *mac_addr) | |
5161 | { | |
5162 | uint64_t carry_bit; | |
5163 | ||
5164 | /* First adjust the frame length. */ | |
5165 | frame_len--; | |
5166 | /* We need to adjust the statistics counters, since the hardware | |
5167 | * counters overcount this packet as a CRC error and undercount | |
5168 | * the packet as a good packet | |
5169 | */ | |
5170 | /* This packet should not be counted as a CRC error. */ | |
5171 | stats->crcerrs--; | |
5172 | /* This packet does count as a Good Packet Received. */ | |
5173 | stats->gprc++; | |
5174 | ||
5175 | /* Adjust the Good Octets received counters */ | |
5176 | carry_bit = 0x80000000 & stats->gorcl; | |
5177 | stats->gorcl += frame_len; | |
5178 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets | |
5179 | * Received Count) was one before the addition, | |
5180 | * AND it is zero after, then we lost the carry out, | |
5181 | * need to add one to Gorch (Good Octets Received Count High). | |
5182 | * This could be simplified if all environments supported | |
5183 | * 64-bit integers. | |
5184 | */ | |
5185 | if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) | |
5186 | stats->gorch++; | |
5187 | /* Is this a broadcast or multicast? Check broadcast first, | |
5188 | * since the test for a multicast frame will test positive on | |
5189 | * a broadcast frame. | |
5190 | */ | |
5191 | if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) | |
5192 | /* Broadcast packet */ | |
5193 | stats->bprc++; | |
5194 | else if(*mac_addr & 0x01) | |
5195 | /* Multicast packet */ | |
5196 | stats->mprc++; | |
5197 | ||
5198 | if(frame_len == hw->max_frame_size) { | |
5199 | /* In this case, the hardware has overcounted the number of | |
5200 | * oversize frames. | |
5201 | */ | |
5202 | if(stats->roc > 0) | |
5203 | stats->roc--; | |
5204 | } | |
5205 | ||
5206 | /* Adjust the bin counters when the extra byte put the frame in the | |
5207 | * wrong bin. Remember that the frame_len was adjusted above. | |
5208 | */ | |
5209 | if(frame_len == 64) { | |
5210 | stats->prc64++; | |
5211 | stats->prc127--; | |
5212 | } else if(frame_len == 127) { | |
5213 | stats->prc127++; | |
5214 | stats->prc255--; | |
5215 | } else if(frame_len == 255) { | |
5216 | stats->prc255++; | |
5217 | stats->prc511--; | |
5218 | } else if(frame_len == 511) { | |
5219 | stats->prc511++; | |
5220 | stats->prc1023--; | |
5221 | } else if(frame_len == 1023) { | |
5222 | stats->prc1023++; | |
5223 | stats->prc1522--; | |
5224 | } else if(frame_len == 1522) { | |
5225 | stats->prc1522++; | |
5226 | } | |
5227 | } | |
5228 | ||
5229 | /****************************************************************************** | |
5230 | * Gets the current PCI bus type, speed, and width of the hardware | |
5231 | * | |
5232 | * hw - Struct containing variables accessed by shared code | |
5233 | *****************************************************************************/ | |
5234 | void | |
5235 | e1000_get_bus_info(struct e1000_hw *hw) | |
5236 | { | |
5237 | uint32_t status; | |
5238 | ||
5239 | switch (hw->mac_type) { | |
5240 | case e1000_82542_rev2_0: | |
5241 | case e1000_82542_rev2_1: | |
5242 | hw->bus_type = e1000_bus_type_unknown; | |
5243 | hw->bus_speed = e1000_bus_speed_unknown; | |
5244 | hw->bus_width = e1000_bus_width_unknown; | |
5245 | break; | |
868d5309 MC |
5246 | case e1000_82571: |
5247 | case e1000_82572: | |
2d7edb92 MC |
5248 | case e1000_82573: |
5249 | hw->bus_type = e1000_bus_type_pci_express; | |
5250 | hw->bus_speed = e1000_bus_speed_2500; | |
5251 | hw->bus_width = e1000_bus_width_pciex_4; | |
5252 | break; | |
1da177e4 LT |
5253 | default: |
5254 | status = E1000_READ_REG(hw, STATUS); | |
5255 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | |
5256 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
5257 | ||
5258 | if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { | |
5259 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? | |
5260 | e1000_bus_speed_66 : e1000_bus_speed_120; | |
5261 | } else if(hw->bus_type == e1000_bus_type_pci) { | |
5262 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? | |
5263 | e1000_bus_speed_66 : e1000_bus_speed_33; | |
5264 | } else { | |
5265 | switch (status & E1000_STATUS_PCIX_SPEED) { | |
5266 | case E1000_STATUS_PCIX_SPEED_66: | |
5267 | hw->bus_speed = e1000_bus_speed_66; | |
5268 | break; | |
5269 | case E1000_STATUS_PCIX_SPEED_100: | |
5270 | hw->bus_speed = e1000_bus_speed_100; | |
5271 | break; | |
5272 | case E1000_STATUS_PCIX_SPEED_133: | |
5273 | hw->bus_speed = e1000_bus_speed_133; | |
5274 | break; | |
5275 | default: | |
5276 | hw->bus_speed = e1000_bus_speed_reserved; | |
5277 | break; | |
5278 | } | |
5279 | } | |
5280 | hw->bus_width = (status & E1000_STATUS_BUS64) ? | |
5281 | e1000_bus_width_64 : e1000_bus_width_32; | |
5282 | break; | |
5283 | } | |
5284 | } | |
5285 | /****************************************************************************** | |
5286 | * Reads a value from one of the devices registers using port I/O (as opposed | |
5287 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
5288 | * | |
5289 | * hw - Struct containing variables accessed by shared code | |
5290 | * offset - offset to read from | |
5291 | *****************************************************************************/ | |
5292 | uint32_t | |
5293 | e1000_read_reg_io(struct e1000_hw *hw, | |
5294 | uint32_t offset) | |
5295 | { | |
5296 | unsigned long io_addr = hw->io_base; | |
5297 | unsigned long io_data = hw->io_base + 4; | |
5298 | ||
5299 | e1000_io_write(hw, io_addr, offset); | |
5300 | return e1000_io_read(hw, io_data); | |
5301 | } | |
5302 | ||
5303 | /****************************************************************************** | |
5304 | * Writes a value to one of the devices registers using port I/O (as opposed to | |
5305 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
5306 | * | |
5307 | * hw - Struct containing variables accessed by shared code | |
5308 | * offset - offset to write to | |
5309 | * value - value to write | |
5310 | *****************************************************************************/ | |
5311 | void | |
5312 | e1000_write_reg_io(struct e1000_hw *hw, | |
5313 | uint32_t offset, | |
5314 | uint32_t value) | |
5315 | { | |
5316 | unsigned long io_addr = hw->io_base; | |
5317 | unsigned long io_data = hw->io_base + 4; | |
5318 | ||
5319 | e1000_io_write(hw, io_addr, offset); | |
5320 | e1000_io_write(hw, io_data, value); | |
5321 | } | |
5322 | ||
5323 | ||
5324 | /****************************************************************************** | |
5325 | * Estimates the cable length. | |
5326 | * | |
5327 | * hw - Struct containing variables accessed by shared code | |
5328 | * min_length - The estimated minimum length | |
5329 | * max_length - The estimated maximum length | |
5330 | * | |
5331 | * returns: - E1000_ERR_XXX | |
5332 | * E1000_SUCCESS | |
5333 | * | |
5334 | * This function always returns a ranged length (minimum & maximum). | |
5335 | * So for M88 phy's, this function interprets the one value returned from the | |
5336 | * register to the minimum and maximum range. | |
5337 | * For IGP phy's, the function calculates the range by the AGC registers. | |
5338 | *****************************************************************************/ | |
5339 | int32_t | |
5340 | e1000_get_cable_length(struct e1000_hw *hw, | |
5341 | uint16_t *min_length, | |
5342 | uint16_t *max_length) | |
5343 | { | |
5344 | int32_t ret_val; | |
5345 | uint16_t agc_value = 0; | |
5346 | uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | |
868d5309 | 5347 | uint16_t max_agc = 0; |
1da177e4 LT |
5348 | uint16_t i, phy_data; |
5349 | uint16_t cable_length; | |
5350 | ||
5351 | DEBUGFUNC("e1000_get_cable_length"); | |
5352 | ||
5353 | *min_length = *max_length = 0; | |
5354 | ||
5355 | /* Use old method for Phy older than IGP */ | |
5356 | if(hw->phy_type == e1000_phy_m88) { | |
2d7edb92 | 5357 | |
1da177e4 LT |
5358 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
5359 | &phy_data); | |
5360 | if(ret_val) | |
5361 | return ret_val; | |
5362 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
5363 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
5364 | ||
5365 | /* Convert the enum value to ranged values */ | |
5366 | switch (cable_length) { | |
5367 | case e1000_cable_length_50: | |
5368 | *min_length = 0; | |
5369 | *max_length = e1000_igp_cable_length_50; | |
5370 | break; | |
5371 | case e1000_cable_length_50_80: | |
5372 | *min_length = e1000_igp_cable_length_50; | |
5373 | *max_length = e1000_igp_cable_length_80; | |
5374 | break; | |
5375 | case e1000_cable_length_80_110: | |
5376 | *min_length = e1000_igp_cable_length_80; | |
5377 | *max_length = e1000_igp_cable_length_110; | |
5378 | break; | |
5379 | case e1000_cable_length_110_140: | |
5380 | *min_length = e1000_igp_cable_length_110; | |
5381 | *max_length = e1000_igp_cable_length_140; | |
5382 | break; | |
5383 | case e1000_cable_length_140: | |
5384 | *min_length = e1000_igp_cable_length_140; | |
5385 | *max_length = e1000_igp_cable_length_170; | |
5386 | break; | |
5387 | default: | |
5388 | return -E1000_ERR_PHY; | |
5389 | break; | |
5390 | } | |
5391 | } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ | |
5392 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
5393 | {IGP01E1000_PHY_AGC_A, | |
5394 | IGP01E1000_PHY_AGC_B, | |
5395 | IGP01E1000_PHY_AGC_C, | |
5396 | IGP01E1000_PHY_AGC_D}; | |
5397 | /* Read the AGC registers for all channels */ | |
5398 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
5399 | ||
5400 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
5401 | if(ret_val) | |
5402 | return ret_val; | |
5403 | ||
5404 | cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; | |
5405 | ||
5406 | /* Array bound check. */ | |
5407 | if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || | |
5408 | (cur_agc == 0)) | |
5409 | return -E1000_ERR_PHY; | |
5410 | ||
5411 | agc_value += cur_agc; | |
5412 | ||
5413 | /* Update minimal AGC value. */ | |
5414 | if(min_agc > cur_agc) | |
5415 | min_agc = cur_agc; | |
5416 | } | |
5417 | ||
5418 | /* Remove the minimal AGC result for length < 50m */ | |
5419 | if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { | |
5420 | agc_value -= min_agc; | |
5421 | ||
5422 | /* Get the average length of the remaining 3 channels */ | |
5423 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | |
5424 | } else { | |
5425 | /* Get the average length of all the 4 channels. */ | |
5426 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; | |
5427 | } | |
5428 | ||
5429 | /* Set the range of the calculated length. */ | |
5430 | *min_length = ((e1000_igp_cable_length_table[agc_value] - | |
5431 | IGP01E1000_AGC_RANGE) > 0) ? | |
5432 | (e1000_igp_cable_length_table[agc_value] - | |
5433 | IGP01E1000_AGC_RANGE) : 0; | |
5434 | *max_length = e1000_igp_cable_length_table[agc_value] + | |
5435 | IGP01E1000_AGC_RANGE; | |
868d5309 MC |
5436 | } else if (hw->phy_type == e1000_phy_igp_2) { |
5437 | uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
5438 | {IGP02E1000_PHY_AGC_A, | |
5439 | IGP02E1000_PHY_AGC_B, | |
5440 | IGP02E1000_PHY_AGC_C, | |
5441 | IGP02E1000_PHY_AGC_D}; | |
5442 | /* Read the AGC registers for all channels */ | |
5443 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
5444 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
5445 | if (ret_val) | |
5446 | return ret_val; | |
5447 | ||
5448 | /* Getting bits 15:9, which represent the combination of course and | |
5449 | * fine gain values. The result is a number that can be put into | |
5450 | * the lookup table to obtain the approximate cable length. */ | |
5451 | cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
5452 | IGP02E1000_AGC_LENGTH_MASK; | |
5453 | ||
5454 | /* Remove min & max AGC values from calculation. */ | |
5455 | if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) | |
5456 | min_agc = cur_agc; | |
5457 | if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) | |
5458 | max_agc = cur_agc; | |
5459 | ||
5460 | agc_value += e1000_igp_2_cable_length_table[cur_agc]; | |
5461 | } | |
5462 | ||
5463 | agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); | |
5464 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
5465 | ||
5466 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
5467 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
5468 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
5469 | *max_length = agc_value + IGP02E1000_AGC_RANGE; | |
1da177e4 LT |
5470 | } |
5471 | ||
5472 | return E1000_SUCCESS; | |
5473 | } | |
5474 | ||
5475 | /****************************************************************************** | |
5476 | * Check the cable polarity | |
5477 | * | |
5478 | * hw - Struct containing variables accessed by shared code | |
5479 | * polarity - output parameter : 0 - Polarity is not reversed | |
5480 | * 1 - Polarity is reversed. | |
5481 | * | |
5482 | * returns: - E1000_ERR_XXX | |
5483 | * E1000_SUCCESS | |
5484 | * | |
5485 | * For phy's older then IGP, this function simply reads the polarity bit in the | |
5486 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is | |
5487 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will | |
5488 | * return 0. If the link speed is 1000 Mbps the polarity status is in the | |
5489 | * IGP01E1000_PHY_PCS_INIT_REG. | |
5490 | *****************************************************************************/ | |
5491 | int32_t | |
5492 | e1000_check_polarity(struct e1000_hw *hw, | |
5493 | uint16_t *polarity) | |
5494 | { | |
5495 | int32_t ret_val; | |
5496 | uint16_t phy_data; | |
5497 | ||
5498 | DEBUGFUNC("e1000_check_polarity"); | |
5499 | ||
5500 | if(hw->phy_type == e1000_phy_m88) { | |
5501 | /* return the Polarity bit in the Status register. */ | |
5502 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | |
5503 | &phy_data); | |
5504 | if(ret_val) | |
5505 | return ret_val; | |
5506 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> | |
5507 | M88E1000_PSSR_REV_POLARITY_SHIFT; | |
2d7edb92 MC |
5508 | } else if(hw->phy_type == e1000_phy_igp || |
5509 | hw->phy_type == e1000_phy_igp_2) { | |
1da177e4 LT |
5510 | /* Read the Status register to check the speed */ |
5511 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | |
5512 | &phy_data); | |
5513 | if(ret_val) | |
5514 | return ret_val; | |
5515 | ||
5516 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to | |
5517 | * find the polarity status */ | |
5518 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | |
5519 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
5520 | ||
5521 | /* Read the GIG initialization PCS register (0x00B4) */ | |
5522 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | |
5523 | &phy_data); | |
5524 | if(ret_val) | |
5525 | return ret_val; | |
5526 | ||
5527 | /* Check the polarity bits */ | |
5528 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; | |
5529 | } else { | |
5530 | /* For 10 Mbps, read the polarity bit in the status register. (for | |
5531 | * 100 Mbps this bit is always 0) */ | |
5532 | *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; | |
5533 | } | |
5534 | } | |
5535 | return E1000_SUCCESS; | |
5536 | } | |
5537 | ||
5538 | /****************************************************************************** | |
5539 | * Check if Downshift occured | |
5540 | * | |
5541 | * hw - Struct containing variables accessed by shared code | |
5542 | * downshift - output parameter : 0 - No Downshift ocured. | |
5543 | * 1 - Downshift ocured. | |
5544 | * | |
5545 | * returns: - E1000_ERR_XXX | |
5546 | * E1000_SUCCESS | |
5547 | * | |
5548 | * For phy's older then IGP, this function reads the Downshift bit in the Phy | |
5549 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the | |
5550 | * Link Health register. In IGP this bit is latched high, so the driver must | |
5551 | * read it immediately after link is established. | |
5552 | *****************************************************************************/ | |
5553 | int32_t | |
5554 | e1000_check_downshift(struct e1000_hw *hw) | |
5555 | { | |
5556 | int32_t ret_val; | |
5557 | uint16_t phy_data; | |
5558 | ||
5559 | DEBUGFUNC("e1000_check_downshift"); | |
5560 | ||
2d7edb92 MC |
5561 | if(hw->phy_type == e1000_phy_igp || |
5562 | hw->phy_type == e1000_phy_igp_2) { | |
1da177e4 LT |
5563 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
5564 | &phy_data); | |
5565 | if(ret_val) | |
5566 | return ret_val; | |
5567 | ||
5568 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; | |
5569 | } else if(hw->phy_type == e1000_phy_m88) { | |
5570 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | |
5571 | &phy_data); | |
5572 | if(ret_val) | |
5573 | return ret_val; | |
5574 | ||
5575 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | |
5576 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | |
5577 | } | |
2d7edb92 | 5578 | |
1da177e4 LT |
5579 | return E1000_SUCCESS; |
5580 | } | |
5581 | ||
5582 | /***************************************************************************** | |
5583 | * | |
5584 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a | |
5585 | * gigabit link is achieved to improve link quality. | |
5586 | * | |
5587 | * hw: Struct containing variables accessed by shared code | |
5588 | * | |
5589 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
5590 | * E1000_SUCCESS at any other case. | |
5591 | * | |
5592 | ****************************************************************************/ | |
5593 | ||
5594 | int32_t | |
5595 | e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |
5596 | boolean_t link_up) | |
5597 | { | |
5598 | int32_t ret_val; | |
5599 | uint16_t phy_data, phy_saved_data, speed, duplex, i; | |
5600 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
5601 | {IGP01E1000_PHY_AGC_PARAM_A, | |
5602 | IGP01E1000_PHY_AGC_PARAM_B, | |
5603 | IGP01E1000_PHY_AGC_PARAM_C, | |
5604 | IGP01E1000_PHY_AGC_PARAM_D}; | |
5605 | uint16_t min_length, max_length; | |
5606 | ||
5607 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | |
5608 | ||
5609 | if(hw->phy_type != e1000_phy_igp) | |
5610 | return E1000_SUCCESS; | |
5611 | ||
5612 | if(link_up) { | |
5613 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
5614 | if(ret_val) { | |
5615 | DEBUGOUT("Error getting link speed and duplex\n"); | |
5616 | return ret_val; | |
5617 | } | |
5618 | ||
5619 | if(speed == SPEED_1000) { | |
5620 | ||
5621 | e1000_get_cable_length(hw, &min_length, &max_length); | |
5622 | ||
5623 | if((hw->dsp_config_state == e1000_dsp_config_enabled) && | |
5624 | min_length >= e1000_igp_cable_length_50) { | |
5625 | ||
5626 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
5627 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], | |
5628 | &phy_data); | |
5629 | if(ret_val) | |
5630 | return ret_val; | |
5631 | ||
5632 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
5633 | ||
5634 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], | |
5635 | phy_data); | |
5636 | if(ret_val) | |
5637 | return ret_val; | |
5638 | } | |
5639 | hw->dsp_config_state = e1000_dsp_config_activated; | |
5640 | } | |
5641 | ||
5642 | if((hw->ffe_config_state == e1000_ffe_config_enabled) && | |
5643 | (min_length < e1000_igp_cable_length_50)) { | |
5644 | ||
5645 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; | |
5646 | uint32_t idle_errs = 0; | |
5647 | ||
5648 | /* clear previous idle error counts */ | |
5649 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
5650 | &phy_data); | |
5651 | if(ret_val) | |
5652 | return ret_val; | |
5653 | ||
5654 | for(i = 0; i < ffe_idle_err_timeout; i++) { | |
5655 | udelay(1000); | |
5656 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
5657 | &phy_data); | |
5658 | if(ret_val) | |
5659 | return ret_val; | |
5660 | ||
5661 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); | |
5662 | if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { | |
5663 | hw->ffe_config_state = e1000_ffe_config_active; | |
5664 | ||
5665 | ret_val = e1000_write_phy_reg(hw, | |
5666 | IGP01E1000_PHY_DSP_FFE, | |
5667 | IGP01E1000_PHY_DSP_FFE_CM_CP); | |
5668 | if(ret_val) | |
5669 | return ret_val; | |
5670 | break; | |
5671 | } | |
5672 | ||
5673 | if(idle_errs) | |
5674 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; | |
5675 | } | |
5676 | } | |
5677 | } | |
5678 | } else { | |
5679 | if(hw->dsp_config_state == e1000_dsp_config_activated) { | |
5680 | /* Save off the current value of register 0x2F5B to be restored at | |
5681 | * the end of the routines. */ | |
5682 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
5683 | ||
5684 | if(ret_val) | |
5685 | return ret_val; | |
5686 | ||
5687 | /* Disable the PHY transmitter */ | |
5688 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
5689 | ||
5690 | if(ret_val) | |
5691 | return ret_val; | |
5692 | ||
2d7edb92 | 5693 | msec_delay_irq(20); |
1da177e4 LT |
5694 | |
5695 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
5696 | IGP01E1000_IEEE_FORCE_GIGA); | |
5697 | if(ret_val) | |
5698 | return ret_val; | |
5699 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
5700 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); | |
5701 | if(ret_val) | |
5702 | return ret_val; | |
5703 | ||
5704 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
5705 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | |
5706 | ||
5707 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); | |
5708 | if(ret_val) | |
5709 | return ret_val; | |
5710 | } | |
5711 | ||
5712 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
5713 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
5714 | if(ret_val) | |
5715 | return ret_val; | |
5716 | ||
2d7edb92 | 5717 | msec_delay_irq(20); |
1da177e4 LT |
5718 | |
5719 | /* Now enable the transmitter */ | |
5720 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
5721 | ||
5722 | if(ret_val) | |
5723 | return ret_val; | |
5724 | ||
5725 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
5726 | } | |
5727 | ||
5728 | if(hw->ffe_config_state == e1000_ffe_config_active) { | |
5729 | /* Save off the current value of register 0x2F5B to be restored at | |
5730 | * the end of the routines. */ | |
5731 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
5732 | ||
5733 | if(ret_val) | |
5734 | return ret_val; | |
5735 | ||
5736 | /* Disable the PHY transmitter */ | |
5737 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
5738 | ||
5739 | if(ret_val) | |
5740 | return ret_val; | |
5741 | ||
2d7edb92 | 5742 | msec_delay_irq(20); |
1da177e4 LT |
5743 | |
5744 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
5745 | IGP01E1000_IEEE_FORCE_GIGA); | |
5746 | if(ret_val) | |
5747 | return ret_val; | |
5748 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | |
5749 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | |
5750 | if(ret_val) | |
5751 | return ret_val; | |
5752 | ||
5753 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
5754 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
5755 | if(ret_val) | |
5756 | return ret_val; | |
5757 | ||
2d7edb92 | 5758 | msec_delay_irq(20); |
1da177e4 LT |
5759 | |
5760 | /* Now enable the transmitter */ | |
5761 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
5762 | ||
5763 | if(ret_val) | |
5764 | return ret_val; | |
5765 | ||
5766 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
5767 | } | |
5768 | } | |
5769 | return E1000_SUCCESS; | |
5770 | } | |
5771 | ||
5772 | /***************************************************************************** | |
5773 | * Set PHY to class A mode | |
5774 | * Assumes the following operations will follow to enable the new class mode. | |
5775 | * 1. Do a PHY soft reset | |
5776 | * 2. Restart auto-negotiation or force link. | |
5777 | * | |
5778 | * hw - Struct containing variables accessed by shared code | |
5779 | ****************************************************************************/ | |
5780 | static int32_t | |
5781 | e1000_set_phy_mode(struct e1000_hw *hw) | |
5782 | { | |
5783 | int32_t ret_val; | |
5784 | uint16_t eeprom_data; | |
5785 | ||
5786 | DEBUGFUNC("e1000_set_phy_mode"); | |
5787 | ||
5788 | if((hw->mac_type == e1000_82545_rev_3) && | |
5789 | (hw->media_type == e1000_media_type_copper)) { | |
5790 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); | |
5791 | if(ret_val) { | |
5792 | return ret_val; | |
5793 | } | |
5794 | ||
5795 | if((eeprom_data != EEPROM_RESERVED_WORD) && | |
5796 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
5797 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); | |
5798 | if(ret_val) | |
5799 | return ret_val; | |
5800 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); | |
5801 | if(ret_val) | |
5802 | return ret_val; | |
5803 | ||
5804 | hw->phy_reset_disable = FALSE; | |
5805 | } | |
5806 | } | |
5807 | ||
5808 | return E1000_SUCCESS; | |
5809 | } | |
5810 | ||
5811 | /***************************************************************************** | |
5812 | * | |
5813 | * This function sets the lplu state according to the active flag. When | |
5814 | * activating lplu this function also disables smart speed and vise versa. | |
5815 | * lplu will not be activated unless the device autonegotiation advertisment | |
5816 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
5817 | * hw: Struct containing variables accessed by shared code | |
5818 | * active - true to enable lplu false to disable lplu. | |
5819 | * | |
5820 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
5821 | * E1000_SUCCESS at any other case. | |
5822 | * | |
5823 | ****************************************************************************/ | |
5824 | ||
5825 | int32_t | |
5826 | e1000_set_d3_lplu_state(struct e1000_hw *hw, | |
5827 | boolean_t active) | |
5828 | { | |
5829 | int32_t ret_val; | |
5830 | uint16_t phy_data; | |
5831 | DEBUGFUNC("e1000_set_d3_lplu_state"); | |
5832 | ||
2d7edb92 | 5833 | if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) |
1da177e4 LT |
5834 | return E1000_SUCCESS; |
5835 | ||
5836 | /* During driver activity LPLU should not be used or it will attain link | |
5837 | * from the lowest speeds starting from 10Mbps. The capability is used for | |
5838 | * Dx transitions and states */ | |
2d7edb92 MC |
5839 | if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
5840 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); | |
5841 | if(ret_val) | |
5842 | return ret_val; | |
5843 | } else { | |
5844 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
1da177e4 LT |
5845 | if(ret_val) |
5846 | return ret_val; | |
2d7edb92 MC |
5847 | } |
5848 | ||
5849 | if(!active) { | |
5850 | if(hw->mac_type == e1000_82541_rev_2 || | |
5851 | hw->mac_type == e1000_82547_rev_2) { | |
5852 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | |
5853 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
5854 | if(ret_val) | |
5855 | return ret_val; | |
5856 | } else { | |
5857 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | |
5858 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
5859 | phy_data); | |
5860 | if (ret_val) | |
5861 | return ret_val; | |
5862 | } | |
1da177e4 LT |
5863 | |
5864 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
5865 | * Dx states where the power conservation is most important. During | |
5866 | * driver activity we should enable SmartSpeed, so performance is | |
5867 | * maintained. */ | |
5868 | if (hw->smart_speed == e1000_smart_speed_on) { | |
5869 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5870 | &phy_data); | |
5871 | if(ret_val) | |
5872 | return ret_val; | |
5873 | ||
5874 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
5875 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5876 | phy_data); | |
5877 | if(ret_val) | |
5878 | return ret_val; | |
5879 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
5880 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5881 | &phy_data); | |
5882 | if (ret_val) | |
5883 | return ret_val; | |
5884 | ||
5885 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
5886 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5887 | phy_data); | |
5888 | if(ret_val) | |
5889 | return ret_val; | |
5890 | } | |
5891 | ||
5892 | } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || | |
5893 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | |
5894 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
5895 | ||
2d7edb92 MC |
5896 | if(hw->mac_type == e1000_82541_rev_2 || |
5897 | hw->mac_type == e1000_82547_rev_2) { | |
5898 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | |
5899 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
5900 | if(ret_val) | |
5901 | return ret_val; | |
5902 | } else { | |
5903 | phy_data |= IGP02E1000_PM_D3_LPLU; | |
5904 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
5905 | phy_data); | |
5906 | if (ret_val) | |
5907 | return ret_val; | |
5908 | } | |
5909 | ||
5910 | /* When LPLU is enabled we should disable SmartSpeed */ | |
5911 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
5912 | if(ret_val) | |
5913 | return ret_val; | |
5914 | ||
5915 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
5916 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
5917 | if(ret_val) | |
5918 | return ret_val; | |
5919 | ||
5920 | } | |
5921 | return E1000_SUCCESS; | |
5922 | } | |
5923 | ||
5924 | /***************************************************************************** | |
5925 | * | |
5926 | * This function sets the lplu d0 state according to the active flag. When | |
5927 | * activating lplu this function also disables smart speed and vise versa. | |
5928 | * lplu will not be activated unless the device autonegotiation advertisment | |
5929 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
5930 | * hw: Struct containing variables accessed by shared code | |
5931 | * active - true to enable lplu false to disable lplu. | |
5932 | * | |
5933 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
5934 | * E1000_SUCCESS at any other case. | |
5935 | * | |
5936 | ****************************************************************************/ | |
5937 | ||
5938 | int32_t | |
5939 | e1000_set_d0_lplu_state(struct e1000_hw *hw, | |
5940 | boolean_t active) | |
5941 | { | |
5942 | int32_t ret_val; | |
5943 | uint16_t phy_data; | |
5944 | DEBUGFUNC("e1000_set_d0_lplu_state"); | |
5945 | ||
5946 | if(hw->mac_type <= e1000_82547_rev_2) | |
5947 | return E1000_SUCCESS; | |
5948 | ||
5949 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
1da177e4 LT |
5950 | if(ret_val) |
5951 | return ret_val; | |
5952 | ||
2d7edb92 MC |
5953 | if (!active) { |
5954 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | |
5955 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
5956 | if (ret_val) | |
5957 | return ret_val; | |
5958 | ||
5959 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
5960 | * Dx states where the power conservation is most important. During | |
5961 | * driver activity we should enable SmartSpeed, so performance is | |
5962 | * maintained. */ | |
5963 | if (hw->smart_speed == e1000_smart_speed_on) { | |
5964 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5965 | &phy_data); | |
5966 | if(ret_val) | |
5967 | return ret_val; | |
5968 | ||
5969 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
5970 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5971 | phy_data); | |
5972 | if(ret_val) | |
5973 | return ret_val; | |
5974 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
5975 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5976 | &phy_data); | |
5977 | if (ret_val) | |
5978 | return ret_val; | |
5979 | ||
5980 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
5981 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
5982 | phy_data); | |
5983 | if(ret_val) | |
5984 | return ret_val; | |
5985 | } | |
5986 | ||
5987 | ||
5988 | } else { | |
5989 | ||
5990 | phy_data |= IGP02E1000_PM_D0_LPLU; | |
5991 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
5992 | if (ret_val) | |
5993 | return ret_val; | |
5994 | ||
1da177e4 LT |
5995 | /* When LPLU is enabled we should disable SmartSpeed */ |
5996 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
5997 | if(ret_val) | |
5998 | return ret_val; | |
5999 | ||
6000 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
6001 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
6002 | if(ret_val) | |
6003 | return ret_val; | |
6004 | ||
6005 | } | |
6006 | return E1000_SUCCESS; | |
6007 | } | |
6008 | ||
6009 | /****************************************************************************** | |
6010 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. | |
6011 | * | |
6012 | * hw - Struct containing variables accessed by shared code | |
6013 | *****************************************************************************/ | |
6014 | static int32_t | |
6015 | e1000_set_vco_speed(struct e1000_hw *hw) | |
6016 | { | |
6017 | int32_t ret_val; | |
6018 | uint16_t default_page = 0; | |
6019 | uint16_t phy_data; | |
6020 | ||
6021 | DEBUGFUNC("e1000_set_vco_speed"); | |
6022 | ||
6023 | switch(hw->mac_type) { | |
6024 | case e1000_82545_rev_3: | |
6025 | case e1000_82546_rev_3: | |
6026 | break; | |
6027 | default: | |
6028 | return E1000_SUCCESS; | |
6029 | } | |
6030 | ||
6031 | /* Set PHY register 30, page 5, bit 8 to 0 */ | |
6032 | ||
6033 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); | |
6034 | if(ret_val) | |
6035 | return ret_val; | |
6036 | ||
6037 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); | |
6038 | if(ret_val) | |
6039 | return ret_val; | |
6040 | ||
6041 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
6042 | if(ret_val) | |
6043 | return ret_val; | |
6044 | ||
6045 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | |
6046 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
6047 | if(ret_val) | |
6048 | return ret_val; | |
6049 | ||
6050 | /* Set PHY register 30, page 4, bit 11 to 1 */ | |
6051 | ||
6052 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | |
6053 | if(ret_val) | |
6054 | return ret_val; | |
6055 | ||
6056 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
6057 | if(ret_val) | |
6058 | return ret_val; | |
6059 | ||
6060 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; | |
6061 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
6062 | if(ret_val) | |
6063 | return ret_val; | |
6064 | ||
6065 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); | |
6066 | if(ret_val) | |
6067 | return ret_val; | |
6068 | ||
6069 | return E1000_SUCCESS; | |
6070 | } | |
6071 | ||
1da177e4 | 6072 | |
2d7edb92 MC |
6073 | /***************************************************************************** |
6074 | * This function reads the cookie from ARC ram. | |
6075 | * | |
6076 | * returns: - E1000_SUCCESS . | |
6077 | ****************************************************************************/ | |
6078 | int32_t | |
6079 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) | |
6080 | { | |
6081 | uint8_t i; | |
6082 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; | |
6083 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; | |
1da177e4 | 6084 | |
2d7edb92 MC |
6085 | length = (length >> 2); |
6086 | offset = (offset >> 2); | |
1da177e4 | 6087 | |
2d7edb92 MC |
6088 | for (i = 0; i < length; i++) { |
6089 | *((uint32_t *) buffer + i) = | |
6090 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); | |
6091 | } | |
6092 | return E1000_SUCCESS; | |
6093 | } | |
6094 | ||
6095 | ||
6096 | /***************************************************************************** | |
6097 | * This function checks whether the HOST IF is enabled for command operaton | |
6098 | * and also checks whether the previous command is completed. | |
6099 | * It busy waits in case of previous command is not completed. | |
6100 | * | |
6101 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or | |
6102 | * timeout | |
6103 | * - E1000_SUCCESS for success. | |
6104 | ****************************************************************************/ | |
6105 | int32_t | |
6106 | e1000_mng_enable_host_if(struct e1000_hw * hw) | |
6107 | { | |
6108 | uint32_t hicr; | |
6109 | uint8_t i; | |
6110 | ||
6111 | /* Check that the host interface is enabled. */ | |
6112 | hicr = E1000_READ_REG(hw, HICR); | |
6113 | if ((hicr & E1000_HICR_EN) == 0) { | |
6114 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | |
6115 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
6116 | } | |
6117 | /* check the previous command is completed */ | |
6118 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | |
6119 | hicr = E1000_READ_REG(hw, HICR); | |
6120 | if (!(hicr & E1000_HICR_C)) | |
6121 | break; | |
6122 | msec_delay_irq(1); | |
6123 | } | |
6124 | ||
6125 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { | |
6126 | DEBUGOUT("Previous command timeout failed .\n"); | |
6127 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
6128 | } | |
6129 | return E1000_SUCCESS; | |
6130 | } | |
6131 | ||
6132 | /***************************************************************************** | |
6133 | * This function writes the buffer content at the offset given on the host if. | |
6134 | * It also does alignment considerations to do the writes in most efficient way. | |
6135 | * Also fills up the sum of the buffer in *buffer parameter. | |
6136 | * | |
6137 | * returns - E1000_SUCCESS for success. | |
6138 | ****************************************************************************/ | |
6139 | int32_t | |
6140 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, | |
6141 | uint16_t length, uint16_t offset, uint8_t *sum) | |
6142 | { | |
6143 | uint8_t *tmp; | |
6144 | uint8_t *bufptr = buffer; | |
6145 | uint32_t data; | |
6146 | uint16_t remaining, i, j, prev_bytes; | |
6147 | ||
6148 | /* sum = only sum of the data and it is not checksum */ | |
6149 | ||
6150 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | |
6151 | return -E1000_ERR_PARAM; | |
6152 | } | |
6153 | ||
6154 | tmp = (uint8_t *)&data; | |
6155 | prev_bytes = offset & 0x3; | |
6156 | offset &= 0xFFFC; | |
6157 | offset >>= 2; | |
6158 | ||
6159 | if (prev_bytes) { | |
6160 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | |
6161 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { | |
6162 | *(tmp + j) = *bufptr++; | |
6163 | *sum += *(tmp + j); | |
6164 | } | |
6165 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | |
6166 | length -= j - prev_bytes; | |
6167 | offset++; | |
6168 | } | |
6169 | ||
6170 | remaining = length & 0x3; | |
6171 | length -= remaining; | |
6172 | ||
6173 | /* Calculate length in DWORDs */ | |
6174 | length >>= 2; | |
6175 | ||
6176 | /* The device driver writes the relevant command block into the | |
6177 | * ram area. */ | |
6178 | for (i = 0; i < length; i++) { | |
6179 | for (j = 0; j < sizeof(uint32_t); j++) { | |
6180 | *(tmp + j) = *bufptr++; | |
6181 | *sum += *(tmp + j); | |
6182 | } | |
6183 | ||
6184 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
6185 | } | |
6186 | if (remaining) { | |
6187 | for (j = 0; j < sizeof(uint32_t); j++) { | |
6188 | if (j < remaining) | |
6189 | *(tmp + j) = *bufptr++; | |
6190 | else | |
6191 | *(tmp + j) = 0; | |
6192 | ||
6193 | *sum += *(tmp + j); | |
6194 | } | |
6195 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
6196 | } | |
6197 | ||
6198 | return E1000_SUCCESS; | |
6199 | } | |
6200 | ||
6201 | ||
6202 | /***************************************************************************** | |
6203 | * This function writes the command header after does the checksum calculation. | |
6204 | * | |
6205 | * returns - E1000_SUCCESS for success. | |
6206 | ****************************************************************************/ | |
6207 | int32_t | |
6208 | e1000_mng_write_cmd_header(struct e1000_hw * hw, | |
6209 | struct e1000_host_mng_command_header * hdr) | |
6210 | { | |
6211 | uint16_t i; | |
6212 | uint8_t sum; | |
6213 | uint8_t *buffer; | |
6214 | ||
6215 | /* Write the whole command header structure which includes sum of | |
6216 | * the buffer */ | |
6217 | ||
6218 | uint16_t length = sizeof(struct e1000_host_mng_command_header); | |
6219 | ||
6220 | sum = hdr->checksum; | |
6221 | hdr->checksum = 0; | |
6222 | ||
6223 | buffer = (uint8_t *) hdr; | |
6224 | i = length; | |
6225 | while(i--) | |
6226 | sum += buffer[i]; | |
6227 | ||
6228 | hdr->checksum = 0 - sum; | |
6229 | ||
6230 | length >>= 2; | |
6231 | /* The device driver writes the relevant command block into the ram area. */ | |
6232 | for (i = 0; i < length; i++) | |
6233 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); | |
6234 | ||
6235 | return E1000_SUCCESS; | |
6236 | } | |
6237 | ||
6238 | ||
6239 | /***************************************************************************** | |
6240 | * This function indicates to ARC that a new command is pending which completes | |
6241 | * one write operation by the driver. | |
6242 | * | |
6243 | * returns - E1000_SUCCESS for success. | |
6244 | ****************************************************************************/ | |
6245 | int32_t | |
6246 | e1000_mng_write_commit( | |
6247 | struct e1000_hw * hw) | |
6248 | { | |
6249 | uint32_t hicr; | |
6250 | ||
6251 | hicr = E1000_READ_REG(hw, HICR); | |
6252 | /* Setting this bit tells the ARC that a new command is pending. */ | |
6253 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); | |
6254 | ||
6255 | return E1000_SUCCESS; | |
6256 | } | |
6257 | ||
6258 | ||
6259 | /***************************************************************************** | |
6260 | * This function checks the mode of the firmware. | |
6261 | * | |
6262 | * returns - TRUE when the mode is IAMT or FALSE. | |
6263 | ****************************************************************************/ | |
6264 | boolean_t | |
6265 | e1000_check_mng_mode( | |
6266 | struct e1000_hw *hw) | |
6267 | { | |
6268 | uint32_t fwsm; | |
6269 | ||
6270 | fwsm = E1000_READ_REG(hw, FWSM); | |
6271 | ||
6272 | if((fwsm & E1000_FWSM_MODE_MASK) == | |
6273 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
6274 | return TRUE; | |
6275 | ||
6276 | return FALSE; | |
6277 | } | |
6278 | ||
6279 | ||
6280 | /***************************************************************************** | |
6281 | * This function writes the dhcp info . | |
6282 | ****************************************************************************/ | |
6283 | int32_t | |
6284 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | |
6285 | uint16_t length) | |
6286 | { | |
6287 | int32_t ret_val; | |
6288 | struct e1000_host_mng_command_header hdr; | |
6289 | ||
6290 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | |
6291 | hdr.command_length = length; | |
6292 | hdr.reserved1 = 0; | |
6293 | hdr.reserved2 = 0; | |
6294 | hdr.checksum = 0; | |
6295 | ||
6296 | ret_val = e1000_mng_enable_host_if(hw); | |
6297 | if (ret_val == E1000_SUCCESS) { | |
6298 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | |
6299 | &(hdr.checksum)); | |
6300 | if (ret_val == E1000_SUCCESS) { | |
6301 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | |
6302 | if (ret_val == E1000_SUCCESS) | |
6303 | ret_val = e1000_mng_write_commit(hw); | |
6304 | } | |
6305 | } | |
6306 | return ret_val; | |
6307 | } | |
6308 | ||
6309 | ||
6310 | /***************************************************************************** | |
6311 | * This function calculates the checksum. | |
6312 | * | |
6313 | * returns - checksum of buffer contents. | |
6314 | ****************************************************************************/ | |
6315 | uint8_t | |
6316 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) | |
6317 | { | |
6318 | uint8_t sum = 0; | |
6319 | uint32_t i; | |
6320 | ||
6321 | if (!buffer) | |
6322 | return 0; | |
6323 | ||
6324 | for (i=0; i < length; i++) | |
6325 | sum += buffer[i]; | |
6326 | ||
6327 | return (uint8_t) (0 - sum); | |
6328 | } | |
6329 | ||
6330 | /***************************************************************************** | |
6331 | * This function checks whether tx pkt filtering needs to be enabled or not. | |
6332 | * | |
6333 | * returns - TRUE for packet filtering or FALSE. | |
6334 | ****************************************************************************/ | |
6335 | boolean_t | |
6336 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) | |
6337 | { | |
6338 | /* called in init as well as watchdog timer functions */ | |
6339 | ||
6340 | int32_t ret_val, checksum; | |
6341 | boolean_t tx_filter = FALSE; | |
6342 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); | |
6343 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); | |
6344 | ||
6345 | if (e1000_check_mng_mode(hw)) { | |
6346 | ret_val = e1000_mng_enable_host_if(hw); | |
6347 | if (ret_val == E1000_SUCCESS) { | |
6348 | ret_val = e1000_host_if_read_cookie(hw, buffer); | |
6349 | if (ret_val == E1000_SUCCESS) { | |
6350 | checksum = hdr->checksum; | |
6351 | hdr->checksum = 0; | |
6352 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | |
6353 | checksum == e1000_calculate_mng_checksum((char *)buffer, | |
6354 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | |
6355 | if (hdr->status & | |
6356 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | |
6357 | tx_filter = TRUE; | |
6358 | } else | |
6359 | tx_filter = TRUE; | |
6360 | } else | |
6361 | tx_filter = TRUE; | |
6362 | } | |
6363 | } | |
6364 | ||
6365 | hw->tx_pkt_filtering = tx_filter; | |
6366 | return tx_filter; | |
6367 | } | |
6368 | ||
6369 | /****************************************************************************** | |
6370 | * Verifies the hardware needs to allow ARPs to be processed by the host | |
6371 | * | |
6372 | * hw - Struct containing variables accessed by shared code | |
6373 | * | |
6374 | * returns: - TRUE/FALSE | |
6375 | * | |
6376 | *****************************************************************************/ | |
6377 | uint32_t | |
6378 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) | |
6379 | { | |
6380 | uint32_t manc; | |
6381 | uint32_t fwsm, factps; | |
6382 | ||
6383 | if (hw->asf_firmware_present) { | |
6384 | manc = E1000_READ_REG(hw, MANC); | |
6385 | ||
6386 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | |
6387 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | |
6388 | return FALSE; | |
6389 | if (e1000_arc_subsystem_valid(hw) == TRUE) { | |
6390 | fwsm = E1000_READ_REG(hw, FWSM); | |
6391 | factps = E1000_READ_REG(hw, FACTPS); | |
6392 | ||
6393 | if (((fwsm & E1000_FWSM_MODE_MASK) == | |
6394 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && | |
6395 | (factps & E1000_FACTPS_MNGCG)) | |
6396 | return TRUE; | |
6397 | } else | |
6398 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | |
6399 | return TRUE; | |
6400 | } | |
6401 | return FALSE; | |
6402 | } | |
6403 | ||
6404 | static int32_t | |
6405 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |
6406 | { | |
6407 | int32_t ret_val; | |
6408 | uint16_t mii_status_reg; | |
6409 | uint16_t i; | |
6410 | ||
6411 | /* Polarity reversal workaround for forced 10F/10H links. */ | |
6412 | ||
6413 | /* Disable the transmitter on the PHY */ | |
6414 | ||
6415 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
1da177e4 LT |
6416 | if(ret_val) |
6417 | return ret_val; | |
6418 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); | |
6419 | if(ret_val) | |
6420 | return ret_val; | |
6421 | ||
6422 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
6423 | if(ret_val) | |
6424 | return ret_val; | |
6425 | ||
6426 | /* This loop will early-out if the NO link condition has been met. */ | |
6427 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
6428 | /* Read the MII Status Register and wait for Link Status bit | |
6429 | * to be clear. | |
6430 | */ | |
6431 | ||
6432 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
6433 | if(ret_val) | |
6434 | return ret_val; | |
6435 | ||
6436 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
6437 | if(ret_val) | |
6438 | return ret_val; | |
6439 | ||
6440 | if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; | |
6441 | msec_delay_irq(100); | |
6442 | } | |
6443 | ||
6444 | /* Recommended delay time after link has been lost */ | |
6445 | msec_delay_irq(1000); | |
6446 | ||
6447 | /* Now we will re-enable th transmitter on the PHY */ | |
6448 | ||
6449 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
6450 | if(ret_val) | |
6451 | return ret_val; | |
6452 | msec_delay_irq(50); | |
6453 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); | |
6454 | if(ret_val) | |
6455 | return ret_val; | |
6456 | msec_delay_irq(50); | |
6457 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); | |
6458 | if(ret_val) | |
6459 | return ret_val; | |
6460 | msec_delay_irq(50); | |
6461 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); | |
6462 | if(ret_val) | |
6463 | return ret_val; | |
6464 | ||
6465 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
6466 | if(ret_val) | |
6467 | return ret_val; | |
6468 | ||
6469 | /* This loop will early-out if the link condition has been met. */ | |
6470 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
6471 | /* Read the MII Status Register and wait for Link Status bit | |
6472 | * to be set. | |
6473 | */ | |
6474 | ||
6475 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
6476 | if(ret_val) | |
6477 | return ret_val; | |
6478 | ||
6479 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
6480 | if(ret_val) | |
6481 | return ret_val; | |
6482 | ||
6483 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
6484 | msec_delay_irq(100); | |
6485 | } | |
6486 | return E1000_SUCCESS; | |
6487 | } | |
6488 | ||
2d7edb92 MC |
6489 | /*************************************************************************** |
6490 | * | |
6491 | * Disables PCI-Express master access. | |
6492 | * | |
6493 | * hw: Struct containing variables accessed by shared code | |
6494 | * | |
6495 | * returns: - none. | |
6496 | * | |
6497 | ***************************************************************************/ | |
6498 | void | |
6499 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) | |
6500 | { | |
6501 | uint32_t ctrl; | |
6502 | ||
6503 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | |
6504 | ||
6505 | if (hw->bus_type != e1000_bus_type_pci_express) | |
6506 | return; | |
6507 | ||
6508 | ctrl = E1000_READ_REG(hw, CTRL); | |
6509 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | |
6510 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
6511 | } | |
6512 | ||
6513 | /*************************************************************************** | |
6514 | * | |
6515 | * Enables PCI-Express master access. | |
6516 | * | |
6517 | * hw: Struct containing variables accessed by shared code | |
6518 | * | |
6519 | * returns: - none. | |
6520 | * | |
6521 | ***************************************************************************/ | |
6522 | void | |
6523 | e1000_enable_pciex_master(struct e1000_hw *hw) | |
6524 | { | |
6525 | uint32_t ctrl; | |
6526 | ||
6527 | DEBUGFUNC("e1000_enable_pciex_master"); | |
6528 | ||
6529 | if (hw->bus_type != e1000_bus_type_pci_express) | |
6530 | return; | |
6531 | ||
6532 | ctrl = E1000_READ_REG(hw, CTRL); | |
6533 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; | |
6534 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
6535 | } | |
6536 | ||
6537 | /******************************************************************************* | |
6538 | * | |
6539 | * Disables PCI-Express master access and verifies there are no pending requests | |
6540 | * | |
6541 | * hw: Struct containing variables accessed by shared code | |
6542 | * | |
6543 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | |
6544 | * caused the master requests to be disabled. | |
6545 | * E1000_SUCCESS master requests disabled. | |
6546 | * | |
6547 | ******************************************************************************/ | |
6548 | int32_t | |
6549 | e1000_disable_pciex_master(struct e1000_hw *hw) | |
6550 | { | |
6551 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ | |
6552 | ||
6553 | DEBUGFUNC("e1000_disable_pciex_master"); | |
6554 | ||
6555 | if (hw->bus_type != e1000_bus_type_pci_express) | |
6556 | return E1000_SUCCESS; | |
6557 | ||
6558 | e1000_set_pci_express_master_disable(hw); | |
6559 | ||
6560 | while(timeout) { | |
6561 | if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) | |
6562 | break; | |
6563 | else | |
6564 | udelay(100); | |
6565 | timeout--; | |
6566 | } | |
6567 | ||
6568 | if(!timeout) { | |
6569 | DEBUGOUT("Master requests are pending.\n"); | |
6570 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | |
6571 | } | |
6572 | ||
6573 | return E1000_SUCCESS; | |
6574 | } | |
6575 | ||
6576 | /******************************************************************************* | |
6577 | * | |
6578 | * Check for EEPROM Auto Read bit done. | |
6579 | * | |
6580 | * hw: Struct containing variables accessed by shared code | |
6581 | * | |
6582 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
6583 | * E1000_SUCCESS at any other case. | |
6584 | * | |
6585 | ******************************************************************************/ | |
6586 | int32_t | |
6587 | e1000_get_auto_rd_done(struct e1000_hw *hw) | |
6588 | { | |
6589 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; | |
6590 | ||
6591 | DEBUGFUNC("e1000_get_auto_rd_done"); | |
6592 | ||
6593 | switch (hw->mac_type) { | |
6594 | default: | |
6595 | msec_delay(5); | |
6596 | break; | |
868d5309 MC |
6597 | case e1000_82571: |
6598 | case e1000_82572: | |
2d7edb92 MC |
6599 | case e1000_82573: |
6600 | while(timeout) { | |
6601 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; | |
6602 | else msec_delay(1); | |
6603 | timeout--; | |
6604 | } | |
6605 | ||
6606 | if(!timeout) { | |
6607 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); | |
6608 | return -E1000_ERR_RESET; | |
6609 | } | |
6610 | break; | |
6611 | } | |
6612 | ||
6613 | return E1000_SUCCESS; | |
6614 | } | |
6615 | ||
6616 | /*************************************************************************** | |
6617 | * Checks if the PHY configuration is done | |
6618 | * | |
6619 | * hw: Struct containing variables accessed by shared code | |
6620 | * | |
6621 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
6622 | * E1000_SUCCESS at any other case. | |
6623 | * | |
6624 | ***************************************************************************/ | |
6625 | int32_t | |
6626 | e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
6627 | { | |
868d5309 MC |
6628 | int32_t timeout = PHY_CFG_TIMEOUT; |
6629 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; | |
6630 | ||
2d7edb92 MC |
6631 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
6632 | ||
868d5309 MC |
6633 | switch (hw->mac_type) { |
6634 | default: | |
6635 | msec_delay(10); | |
6636 | break; | |
6637 | case e1000_82571: | |
6638 | case e1000_82572: | |
6639 | while (timeout) { | |
6640 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | |
6641 | break; | |
6642 | else | |
6643 | msec_delay(1); | |
6644 | timeout--; | |
6645 | } | |
6646 | ||
6647 | if (!timeout) { | |
6648 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | |
6649 | return -E1000_ERR_RESET; | |
6650 | } | |
6651 | break; | |
6652 | } | |
2d7edb92 MC |
6653 | |
6654 | return E1000_SUCCESS; | |
6655 | } | |
6656 | ||
6657 | /*************************************************************************** | |
6658 | * | |
6659 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
6660 | * adapter or Eeprom access. | |
6661 | * | |
6662 | * hw: Struct containing variables accessed by shared code | |
6663 | * | |
6664 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
6665 | * E1000_SUCCESS at any other case. | |
6666 | * | |
6667 | ***************************************************************************/ | |
6668 | int32_t | |
6669 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) | |
6670 | { | |
6671 | int32_t timeout; | |
6672 | uint32_t swsm; | |
6673 | ||
6674 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | |
6675 | ||
6676 | if(!hw->eeprom_semaphore_present) | |
6677 | return E1000_SUCCESS; | |
6678 | ||
6679 | ||
6680 | /* Get the FW semaphore. */ | |
6681 | timeout = hw->eeprom.word_size + 1; | |
6682 | while(timeout) { | |
6683 | swsm = E1000_READ_REG(hw, SWSM); | |
6684 | swsm |= E1000_SWSM_SWESMBI; | |
6685 | E1000_WRITE_REG(hw, SWSM, swsm); | |
6686 | /* if we managed to set the bit we got the semaphore. */ | |
6687 | swsm = E1000_READ_REG(hw, SWSM); | |
6688 | if(swsm & E1000_SWSM_SWESMBI) | |
6689 | break; | |
6690 | ||
6691 | udelay(50); | |
6692 | timeout--; | |
6693 | } | |
6694 | ||
6695 | if(!timeout) { | |
6696 | /* Release semaphores */ | |
6697 | e1000_put_hw_eeprom_semaphore(hw); | |
6698 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | |
6699 | return -E1000_ERR_EEPROM; | |
6700 | } | |
6701 | ||
6702 | return E1000_SUCCESS; | |
6703 | } | |
6704 | ||
6705 | /*************************************************************************** | |
6706 | * This function clears HW semaphore bits. | |
6707 | * | |
6708 | * hw: Struct containing variables accessed by shared code | |
6709 | * | |
6710 | * returns: - None. | |
6711 | * | |
6712 | ***************************************************************************/ | |
6713 | void | |
6714 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) | |
6715 | { | |
6716 | uint32_t swsm; | |
6717 | ||
6718 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | |
6719 | ||
6720 | if(!hw->eeprom_semaphore_present) | |
6721 | return; | |
6722 | ||
6723 | swsm = E1000_READ_REG(hw, SWSM); | |
868d5309 | 6724 | swsm &= ~(E1000_SWSM_SWESMBI); |
2d7edb92 MC |
6725 | E1000_WRITE_REG(hw, SWSM, swsm); |
6726 | } | |
6727 | ||
6728 | /****************************************************************************** | |
6729 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
6730 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
6731 | * the caller to figure out how to deal with it. | |
6732 | * | |
6733 | * hw - Struct containing variables accessed by shared code | |
6734 | * | |
6735 | * returns: - E1000_BLK_PHY_RESET | |
6736 | * E1000_SUCCESS | |
6737 | * | |
6738 | *****************************************************************************/ | |
6739 | int32_t | |
6740 | e1000_check_phy_reset_block(struct e1000_hw *hw) | |
6741 | { | |
6742 | uint32_t manc = 0; | |
6743 | if(hw->mac_type > e1000_82547_rev_2) | |
6744 | manc = E1000_READ_REG(hw, MANC); | |
6745 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
6746 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | |
6747 | } | |
6748 | ||
6749 | uint8_t | |
6750 | e1000_arc_subsystem_valid(struct e1000_hw *hw) | |
6751 | { | |
6752 | uint32_t fwsm; | |
6753 | ||
6754 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | |
6755 | * may not be provided a DMA clock when no manageability features are | |
6756 | * enabled. We do not want to perform any reads/writes to these registers | |
6757 | * if this is the case. We read FWSM to determine the manageability mode. | |
6758 | */ | |
6759 | switch (hw->mac_type) { | |
868d5309 MC |
6760 | case e1000_82571: |
6761 | case e1000_82572: | |
2d7edb92 MC |
6762 | case e1000_82573: |
6763 | fwsm = E1000_READ_REG(hw, FWSM); | |
6764 | if((fwsm & E1000_FWSM_MODE_MASK) != 0) | |
6765 | return TRUE; | |
6766 | break; | |
6767 | default: | |
6768 | break; | |
6769 | } | |
6770 | return FALSE; | |
6771 | } | |
6772 | ||
6773 | ||
6774 |