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e1000: ring buffers resources cleanup
[mirror_ubuntu-focal-kernel.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
3d41e30a 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#include "e1000.h"
31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
dc335d97 39#define DRV_VERSION "7.1.9-k6"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
1da177e4
LT		 51 INTEL_E1000_ETHERNET_DEVICE(0x1001),
52 INTEL_E1000_ETHERNET_DEVICE(0x1004),
53 INTEL_E1000_ETHERNET_DEVICE(0x1008),
54 INTEL_E1000_ETHERNET_DEVICE(0x1009),
55 INTEL_E1000_ETHERNET_DEVICE(0x100C),
56 INTEL_E1000_ETHERNET_DEVICE(0x100D),
57 INTEL_E1000_ETHERNET_DEVICE(0x100E),
58 INTEL_E1000_ETHERNET_DEVICE(0x100F),
59 INTEL_E1000_ETHERNET_DEVICE(0x1010),
60 INTEL_E1000_ETHERNET_DEVICE(0x1011),
61 INTEL_E1000_ETHERNET_DEVICE(0x1012),
62 INTEL_E1000_ETHERNET_DEVICE(0x1013),
63 INTEL_E1000_ETHERNET_DEVICE(0x1014),
64 INTEL_E1000_ETHERNET_DEVICE(0x1015),
65 INTEL_E1000_ETHERNET_DEVICE(0x1016),
66 INTEL_E1000_ETHERNET_DEVICE(0x1017),
67 INTEL_E1000_ETHERNET_DEVICE(0x1018),
68 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 69 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 70 INTEL_E1000_ETHERNET_DEVICE(0x101D),
71 INTEL_E1000_ETHERNET_DEVICE(0x101E),
72 INTEL_E1000_ETHERNET_DEVICE(0x1026),
73 INTEL_E1000_ETHERNET_DEVICE(0x1027),
74 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 75 INTEL_E1000_ETHERNET_DEVICE(0x1049),
76 INTEL_E1000_ETHERNET_DEVICE(0x104A),
77 INTEL_E1000_ETHERNET_DEVICE(0x104B),
78 INTEL_E1000_ETHERNET_DEVICE(0x104C),
79 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 80 INTEL_E1000_ETHERNET_DEVICE(0x105E),
81 INTEL_E1000_ETHERNET_DEVICE(0x105F),
82 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 91 INTEL_E1000_ETHERNET_DEVICE(0x107D),
92 INTEL_E1000_ETHERNET_DEVICE(0x107E),
93 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 94 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 95 INTEL_E1000_ETHERNET_DEVICE(0x108B),
96 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 97 INTEL_E1000_ETHERNET_DEVICE(0x1096),
98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 101 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 102 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 103 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
1da177e4
LT		 105 /* required last entry */
106 {0,}
107};
108
109MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
110
3ad2cc67 111static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 112 struct e1000_tx_ring *txdr);
3ad2cc67 113static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 114 struct e1000_rx_ring *rxdr);
3ad2cc67 115static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 116 struct e1000_tx_ring *tx_ring);
3ad2cc67 117static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 118 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 119
120/* Local Function Prototypes */
121
122static int e1000_init_module(void);
123static void e1000_exit_module(void);
124static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
125static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 126static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 127static int e1000_sw_init(struct e1000_adapter *adapter);
128static int e1000_open(struct net_device *netdev);
129static int e1000_close(struct net_device *netdev);
130static void e1000_configure_tx(struct e1000_adapter *adapter);
131static void e1000_configure_rx(struct e1000_adapter *adapter);
132static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 133static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
134static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
135static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
136 struct e1000_tx_ring *tx_ring);
137static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
138 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 139static void e1000_set_multi(struct net_device *netdev);
140static void e1000_update_phy_info(unsigned long data);
141static void e1000_watchdog(unsigned long data);
1da177e4
LT		 142static void e1000_82547_tx_fifo_stall(unsigned long data);
143static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
144static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
145static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
146static int e1000_set_mac(struct net_device *netdev, void *p);
147static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 148static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
149 struct e1000_tx_ring *tx_ring);
1da177e4 150#ifdef CONFIG_E1000_NAPI
581d708e 151static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 152static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 153 struct e1000_rx_ring *rx_ring,
1da177e4 154 int *work_done, int work_to_do);
2d7edb92 155static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 156 struct e1000_rx_ring *rx_ring,
2d7edb92 157 int *work_done, int work_to_do);
1da177e4 158#else
581d708e
MC		 159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
160 struct e1000_rx_ring *rx_ring);
161static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
162 struct e1000_rx_ring *rx_ring);
1da177e4 163#endif
581d708e 164static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 165 struct e1000_rx_ring *rx_ring,
166 int cleaned_count);
581d708e 167static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 168 struct e1000_rx_ring *rx_ring,
169 int cleaned_count);
1da177e4
LT		 170static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
171static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
172 int cmd);
1da177e4
LT		 173static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
174static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
175static void e1000_tx_timeout(struct net_device *dev);
87041639 176static void e1000_reset_task(struct net_device *dev);
1da177e4 177static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 178static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
179 struct sk_buff *skb);
1da177e4
LT		 180
181static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
182static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
183static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
184static void e1000_restore_vlan(struct e1000_adapter *adapter);
185
977e74b5 186static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 187#ifdef CONFIG_PM
1da177e4
LT		 188static int e1000_resume(struct pci_dev *pdev);
189#endif
c653e635 190static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 191
192#ifdef CONFIG_NET_POLL_CONTROLLER
193/* for netdump / net console */
194static void e1000_netpoll (struct net_device *netdev);
195#endif
196
9026729b
AK		 197static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
198 pci_channel_state_t state);
199static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
200static void e1000_io_resume(struct pci_dev *pdev);
201
202static struct pci_error_handlers e1000_err_handler = {
203 .error_detected = e1000_io_error_detected,
204 .slot_reset = e1000_io_slot_reset,
205 .resume = e1000_io_resume,
206};
24025e4e 207
1da177e4
LT		 208static struct pci_driver e1000_driver = {
209 .name = e1000_driver_name,
210 .id_table = e1000_pci_tbl,
211 .probe = e1000_probe,
212 .remove = __devexit_p(e1000_remove),
213 /* Power Managment Hooks */
1da177e4 214 .suspend = e1000_suspend,
6fdfef16 215#ifdef CONFIG_PM
c653e635 216 .resume = e1000_resume,
1da177e4 217#endif
9026729b
AK		 218 .shutdown = e1000_shutdown,
219 .err_handler = &e1000_err_handler
1da177e4
LT		 220};
221
222MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
223MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_VERSION);
226
227static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
228module_param(debug, int, 0);
229MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
230
231/**
232 * e1000_init_module - Driver Registration Routine
233 *
234 * e1000_init_module is the first routine called when the driver is
235 * loaded. All it does is register with the PCI subsystem.
236 **/
237
238static int __init
239e1000_init_module(void)
240{
241 int ret;
242 printk(KERN_INFO "%s - version %s\n",
243 e1000_driver_string, e1000_driver_version);
244
245 printk(KERN_INFO "%s\n", e1000_copyright);
246
29917620 247 ret = pci_register_driver(&e1000_driver);
8b378def 248
1da177e4
LT		 249 return ret;
250}
251
252module_init(e1000_init_module);
253
254/**
255 * e1000_exit_module - Driver Exit Cleanup Routine
256 *
257 * e1000_exit_module is called just before the driver is removed
258 * from memory.
259 **/
260
261static void __exit
262e1000_exit_module(void)
263{
1da177e4
LT		 264 pci_unregister_driver(&e1000_driver);
265}
266
267module_exit(e1000_exit_module);
268
2db10a08
AK		 269static int e1000_request_irq(struct e1000_adapter *adapter)
270{
271 struct net_device *netdev = adapter->netdev;
272 int flags, err = 0;
273
c0bc8721 274 flags = IRQF_SHARED;
2db10a08
AK		 275#ifdef CONFIG_PCI_MSI
276 if (adapter->hw.mac_type > e1000_82547_rev_2) {
277 adapter->have_msi = TRUE;
278 if ((err = pci_enable_msi(adapter->pdev))) {
279 DPRINTK(PROBE, ERR,
280 "Unable to allocate MSI interrupt Error: %d\n", err);
281 adapter->have_msi = FALSE;
282 }
283 }
284 if (adapter->have_msi)
61ef5c00 285 flags &= ~IRQF_SHARED;
2db10a08
AK		 286#endif
287 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
288 netdev->name, netdev)))
289 DPRINTK(PROBE, ERR,
290 "Unable to allocate interrupt Error: %d\n", err);
291
292 return err;
293}
294
295static void e1000_free_irq(struct e1000_adapter *adapter)
296{
297 struct net_device *netdev = adapter->netdev;
298
299 free_irq(adapter->pdev->irq, netdev);
300
301#ifdef CONFIG_PCI_MSI
302 if (adapter->have_msi)
303 pci_disable_msi(adapter->pdev);
304#endif
305}
306
1da177e4
LT		 307/**
308 * e1000_irq_disable - Mask off interrupt generation on the NIC
309 * @adapter: board private structure
310 **/
311
e619d523 312static void
1da177e4
LT		 313e1000_irq_disable(struct e1000_adapter *adapter)
314{
315 atomic_inc(&adapter->irq_sem);
316 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
317 E1000_WRITE_FLUSH(&adapter->hw);
318 synchronize_irq(adapter->pdev->irq);
319}
320
321/**
322 * e1000_irq_enable - Enable default interrupt generation settings
323 * @adapter: board private structure
324 **/
325
e619d523 326static void
1da177e4
LT		 327e1000_irq_enable(struct e1000_adapter *adapter)
328{
96838a40 329 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 330 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
331 E1000_WRITE_FLUSH(&adapter->hw);
332 }
333}
3ad2cc67
AB		 334
335static void
2d7edb92
MC		 336e1000_update_mng_vlan(struct e1000_adapter *adapter)
337{
338 struct net_device *netdev = adapter->netdev;
339 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
340 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 341 if (adapter->vlgrp) {
342 if (!adapter->vlgrp->vlan_devices[vid]) {
343 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 344 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
345 e1000_vlan_rx_add_vid(netdev, vid);
346 adapter->mng_vlan_id = vid;
347 } else
348 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 349
350 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
351 (vid != old_vid) &&
2d7edb92
MC		 352 !adapter->vlgrp->vlan_devices[old_vid])
353 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 354 } else
355 adapter->mng_vlan_id = vid;
2d7edb92
MC		 356 }
357}
b55ccb35
JK		 358
359/**
360 * e1000_release_hw_control - release control of the h/w to f/w
361 * @adapter: address of board private structure
362 *
363 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
364 * For ASF and Pass Through versions of f/w this means that the
365 * driver is no longer loaded. For AMT version (only with 82573) i
366 * of the f/w this means that the netowrk i/f is closed.
76c224bc 367 *
b55ccb35
JK		 368 **/
369
e619d523 370static void
b55ccb35
JK		 371e1000_release_hw_control(struct e1000_adapter *adapter)
372{
373 uint32_t ctrl_ext;
374 uint32_t swsm;
cd94dd0b 375 uint32_t extcnf;
b55ccb35
JK		 376
377 /* Let firmware taken over control of h/w */
378 switch (adapter->hw.mac_type) {
379 case e1000_82571:
380 case e1000_82572:
4cc15f54 381 case e1000_80003es2lan:
b55ccb35
JK		 382 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
383 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
384 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
385 break;
386 case e1000_82573:
387 swsm = E1000_READ_REG(&adapter->hw, SWSM);
388 E1000_WRITE_REG(&adapter->hw, SWSM,
389 swsm & ~E1000_SWSM_DRV_LOAD);
cd94dd0b
AK		 390 case e1000_ich8lan:
391 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
392 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
393 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
394 break;
b55ccb35
JK		 395 default:
396 break;
397 }
398}
399
400/**
401 * e1000_get_hw_control - get control of the h/w from f/w
402 * @adapter: address of board private structure
403 *
404 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 405 * For ASF and Pass Through versions of f/w this means that
406 * the driver is loaded. For AMT version (only with 82573)
b55ccb35 407 * of the f/w this means that the netowrk i/f is open.
76c224bc 408 *
b55ccb35
JK		 409 **/
410
e619d523 411static void
b55ccb35
JK		 412e1000_get_hw_control(struct e1000_adapter *adapter)
413{
414 uint32_t ctrl_ext;
415 uint32_t swsm;
cd94dd0b 416 uint32_t extcnf;
b55ccb35
JK		 417 /* Let firmware know the driver has taken over */
418 switch (adapter->hw.mac_type) {
419 case e1000_82571:
420 case e1000_82572:
4cc15f54 421 case e1000_80003es2lan:
b55ccb35
JK		 422 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
423 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
424 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
425 break;
426 case e1000_82573:
427 swsm = E1000_READ_REG(&adapter->hw, SWSM);
428 E1000_WRITE_REG(&adapter->hw, SWSM,
429 swsm | E1000_SWSM_DRV_LOAD);
430 break;
cd94dd0b
AK		 431 case e1000_ich8lan:
432 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
433 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
434 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
435 break;
b55ccb35
JK		 436 default:
437 break;
438 }
439}
440
1da177e4
LT		 441int
442e1000_up(struct e1000_adapter *adapter)
443{
444 struct net_device *netdev = adapter->netdev;
2db10a08 445 int i;
1da177e4
LT		 446
447 /* hardware has been reset, we need to reload some things */
448
1da177e4
LT		 449 e1000_set_multi(netdev);
450
451 e1000_restore_vlan(adapter);
452
453 e1000_configure_tx(adapter);
454 e1000_setup_rctl(adapter);
455 e1000_configure_rx(adapter);
72d64a43
JK		 456 /* call E1000_DESC_UNUSED which always leaves
457 * at least 1 descriptor unused to make sure
458 * next_to_use != next_to_clean */
f56799ea 459 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 460 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 461 adapter->alloc_rx_buf(adapter, ring,
462 E1000_DESC_UNUSED(ring));
f56799ea 463 }
1da177e4 464
7bfa4816
JK		 465 adapter->tx_queue_len = netdev->tx_queue_len;
466
1da177e4 467 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 468
469#ifdef CONFIG_E1000_NAPI
470 netif_poll_enable(netdev);
471#endif
5de55624
MC		 472 e1000_irq_enable(adapter);
473
1da177e4
LT		 474 return 0;
475}
476
79f05bf0
AK		 477/**
478 * e1000_power_up_phy - restore link in case the phy was powered down
479 * @adapter: address of board private structure
480 *
481 * The phy may be powered down to save power and turn off link when the
482 * driver is unloaded and wake on lan is not enabled (among others)
483 * *** this routine MUST be followed by a call to e1000_reset ***
484 *
485 **/
486
d658266e 487void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 488{
489 uint16_t mii_reg = 0;
490
491 /* Just clear the power down bit to wake the phy back up */
492 if (adapter->hw.media_type == e1000_media_type_copper) {
493 /* according to the manual, the phy will retain its
494 * settings across a power-down/up cycle */
495 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
496 mii_reg &= ~MII_CR_POWER_DOWN;
497 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
498 }
499}
500
501static void e1000_power_down_phy(struct e1000_adapter *adapter)
502{
503 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
504 e1000_check_mng_mode(&adapter->hw);
505 /* Power down the PHY so no link is implied when interface is down
506 * The PHY cannot be powered down if any of the following is TRUE
507 * (a) WoL is enabled
508 * (b) AMT is active
509 * (c) SoL/IDER session is active */
510 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 511 adapter->hw.mac_type != e1000_ich8lan &&
79f05bf0
AK		 512 adapter->hw.media_type == e1000_media_type_copper &&
513 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
514 !mng_mode_enabled &&
515 !e1000_check_phy_reset_block(&adapter->hw)) {
516 uint16_t mii_reg = 0;
517 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
518 mii_reg |= MII_CR_POWER_DOWN;
519 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
520 mdelay(1);
521 }
522}
523
1da177e4
LT		 524void
525e1000_down(struct e1000_adapter *adapter)
526{
527 struct net_device *netdev = adapter->netdev;
528
529 e1000_irq_disable(adapter);
c1605eb3 530
1da177e4
LT		 531 del_timer_sync(&adapter->tx_fifo_stall_timer);
532 del_timer_sync(&adapter->watchdog_timer);
533 del_timer_sync(&adapter->phy_info_timer);
534
535#ifdef CONFIG_E1000_NAPI
536 netif_poll_disable(netdev);
537#endif
7bfa4816 538 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 539 adapter->link_speed = 0;
540 adapter->link_duplex = 0;
541 netif_carrier_off(netdev);
542 netif_stop_queue(netdev);
543
544 e1000_reset(adapter);
581d708e
MC		 545 e1000_clean_all_tx_rings(adapter);
546 e1000_clean_all_rx_rings(adapter);
1da177e4 547}
1da177e4 548
2db10a08
AK		 549void
550e1000_reinit_locked(struct e1000_adapter *adapter)
551{
552 WARN_ON(in_interrupt());
553 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
554 msleep(1);
555 e1000_down(adapter);
556 e1000_up(adapter);
557 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 558}
559
560void
561e1000_reset(struct e1000_adapter *adapter)
562{
2d7edb92 563 uint32_t pba, manc;
1125ecbc 564 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 565
566 /* Repartition Pba for greater than 9k mtu
567 * To take effect CTRL.RST is required.
568 */
569
2d7edb92
MC		 570 switch (adapter->hw.mac_type) {
571 case e1000_82547:
0e6ef3e0 572 case e1000_82547_rev_2:
2d7edb92
MC		 573 pba = E1000_PBA_30K;
574 break;
868d5309
MC		 575 case e1000_82571:
576 case e1000_82572:
6418ecc6 577 case e1000_80003es2lan:
868d5309
MC		 578 pba = E1000_PBA_38K;
579 break;
2d7edb92
MC		 580 case e1000_82573:
581 pba = E1000_PBA_12K;
582 break;
cd94dd0b
AK		 583 case e1000_ich8lan:
584 pba = E1000_PBA_8K;
585 break;
2d7edb92
MC		 586 default:
587 pba = E1000_PBA_48K;
588 break;
589 }
590
96838a40 591 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 592 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 593 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 594
595
96838a40 596 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 597 adapter->tx_fifo_head = 0;
598 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
599 adapter->tx_fifo_size =
600 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
601 atomic_set(&adapter->tx_fifo_stall, 0);
602 }
2d7edb92 603
1da177e4
LT		 604 E1000_WRITE_REG(&adapter->hw, PBA, pba);
605
606 /* flow control settings */
f11b7f85
JK		 607 /* Set the FC high water mark to 90% of the FIFO size.
608 * Required to clear last 3 LSB */
609 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 610 /* We can't use 90% on small FIFOs because the remainder
611 * would be less than 1 full frame. In this case, we size
612 * it to allow at least a full frame above the high water
613 * mark. */
614 if (pba < E1000_PBA_16K)
615 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 616
617 adapter->hw.fc_high_water = fc_high_water_mark;
618 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 619 if (adapter->hw.mac_type == e1000_80003es2lan)
620 adapter->hw.fc_pause_time = 0xFFFF;
621 else
622 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 623 adapter->hw.fc_send_xon = 1;
624 adapter->hw.fc = adapter->hw.original_fc;
625
2d7edb92 626 /* Allow time for pending master requests to run */
1da177e4 627 e1000_reset_hw(&adapter->hw);
96838a40 628 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 629 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 630 if (e1000_init_hw(&adapter->hw))
1da177e4 631 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 632 e1000_update_mng_vlan(adapter);
1da177e4
LT		 633 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
634 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
635
636 e1000_reset_adaptive(&adapter->hw);
637 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 638
639 if (!adapter->smart_power_down &&
640 (adapter->hw.mac_type == e1000_82571 ||
641 adapter->hw.mac_type == e1000_82572)) {
642 uint16_t phy_data = 0;
643 /* speed up time to link by disabling smart power down, ignore
644 * the return value of this function because there is nothing
645 * different we would do if it failed */
646 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
647 &phy_data);
648 phy_data &= ~IGP02E1000_PM_SPD;
649 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
650 phy_data);
651 }
652
cd94dd0b
AK		 653 if (adapter->hw.mac_type < e1000_ich8lan)
654 /* FIXME: this code is duplicate and wrong for PCI Express */
2d7edb92
MC		 655 if (adapter->en_mng_pt) {
656 manc = E1000_READ_REG(&adapter->hw, MANC);
657 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
658 E1000_WRITE_REG(&adapter->hw, MANC, manc);
659 }
1da177e4
LT		 660}
661
662/**
663 * e1000_probe - Device Initialization Routine
664 * @pdev: PCI device information struct
665 * @ent: entry in e1000_pci_tbl
666 *
667 * Returns 0 on success, negative on failure
668 *
669 * e1000_probe initializes an adapter identified by a pci_dev structure.
670 * The OS initialization, configuring of the adapter private structure,
671 * and a hardware reset occur.
672 **/
673
674static int __devinit
675e1000_probe(struct pci_dev *pdev,
676 const struct pci_device_id *ent)
677{
678 struct net_device *netdev;
679 struct e1000_adapter *adapter;
2d7edb92 680 unsigned long mmio_start, mmio_len;
cd94dd0b 681 unsigned long flash_start, flash_len;
2d7edb92 682
1da177e4 683 static int cards_found = 0;
84916829 684 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 685 int i, err, pci_using_dac;
1da177e4
LT		 686 uint16_t eeprom_data;
687 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 688 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 689 return err;
690
cd94dd0b
AK		 691 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
692 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 693 pci_using_dac = 1;
694 } else {
cd94dd0b
AK		 695 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
696 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 697 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 698 goto err_dma;
1da177e4
LT		 699 }
700 pci_using_dac = 0;
701 }
702
96838a40 703 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 704 goto err_pci_reg;
1da177e4
LT		 705
706 pci_set_master(pdev);
707
6dd62ab0 708 err = -ENOMEM;
1da177e4 709 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 710 if (!netdev)
1da177e4 711 goto err_alloc_etherdev;
1da177e4
LT		 712
713 SET_MODULE_OWNER(netdev);
714 SET_NETDEV_DEV(netdev, &pdev->dev);
715
716 pci_set_drvdata(pdev, netdev);
60490fe0 717 adapter = netdev_priv(netdev);
1da177e4
LT		 718 adapter->netdev = netdev;
719 adapter->pdev = pdev;
720 adapter->hw.back = adapter;
721 adapter->msg_enable = (1 << debug) - 1;
722
723 mmio_start = pci_resource_start(pdev, BAR_0);
724 mmio_len = pci_resource_len(pdev, BAR_0);
725
6dd62ab0 726 err = -EIO;
1da177e4 727 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 728 if (!adapter->hw.hw_addr)
1da177e4 729 goto err_ioremap;
1da177e4 730
96838a40
JB		 731 for (i = BAR_1; i <= BAR_5; i++) {
732 if (pci_resource_len(pdev, i) == 0)
1da177e4 733 continue;
96838a40 734 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 735 adapter->hw.io_base = pci_resource_start(pdev, i);
736 break;
737 }
738 }
739
740 netdev->open = &e1000_open;
741 netdev->stop = &e1000_close;
742 netdev->hard_start_xmit = &e1000_xmit_frame;
743 netdev->get_stats = &e1000_get_stats;
744 netdev->set_multicast_list = &e1000_set_multi;
745 netdev->set_mac_address = &e1000_set_mac;
746 netdev->change_mtu = &e1000_change_mtu;
747 netdev->do_ioctl = &e1000_ioctl;
748 e1000_set_ethtool_ops(netdev);
749 netdev->tx_timeout = &e1000_tx_timeout;
750 netdev->watchdog_timeo = 5 * HZ;
751#ifdef CONFIG_E1000_NAPI
752 netdev->poll = &e1000_clean;
753 netdev->weight = 64;
754#endif
755 netdev->vlan_rx_register = e1000_vlan_rx_register;
756 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
757 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
758#ifdef CONFIG_NET_POLL_CONTROLLER
759 netdev->poll_controller = e1000_netpoll;
760#endif
761 strcpy(netdev->name, pci_name(pdev));
762
763 netdev->mem_start = mmio_start;
764 netdev->mem_end = mmio_start + mmio_len;
765 netdev->base_addr = adapter->hw.io_base;
766
767 adapter->bd_number = cards_found;
768
769 /* setup the private structure */
770
96838a40 771 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 772 goto err_sw_init;
773
6dd62ab0 774 err = -EIO;
cd94dd0b
AK		 775 /* Flash BAR mapping must happen after e1000_sw_init
776 * because it depends on mac_type */
777 if ((adapter->hw.mac_type == e1000_ich8lan) &&
778 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
779 flash_start = pci_resource_start(pdev, 1);
780 flash_len = pci_resource_len(pdev, 1);
781 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 782 if (!adapter->hw.flash_address)
cd94dd0b 783 goto err_flashmap;
cd94dd0b
AK		 784 }
785
6dd62ab0 786 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 787 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
788
84916829 789 /* if ksp3, indicate if it's port a being setup */
76c224bc
AK		 790 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
791 e1000_ksp3_port_a == 0)
84916829
JK		 792 adapter->ksp3_port_a = 1;
793 e1000_ksp3_port_a++;
794 /* Reset for multiple KP3 adapters */
795 if (e1000_ksp3_port_a == 4)
796 e1000_ksp3_port_a = 0;
797
96838a40 798 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 799 netdev->features = NETIF_F_SG |
800 NETIF_F_HW_CSUM |
801 NETIF_F_HW_VLAN_TX |
802 NETIF_F_HW_VLAN_RX |
803 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 804 if (adapter->hw.mac_type == e1000_ich8lan)
805 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 806 }
807
808#ifdef NETIF_F_TSO
96838a40 809 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 810 (adapter->hw.mac_type != e1000_82547))
811 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 812
813#ifdef NETIF_F_TSO_IPV6
96838a40 814 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 815 netdev->features |= NETIF_F_TSO_IPV6;
816#endif
1da177e4 817#endif
96838a40 818 if (pci_using_dac)
1da177e4
LT		 819 netdev->features |= NETIF_F_HIGHDMA;
820
76c224bc
AK		 821 netdev->features |= NETIF_F_LLTX;
822
2d7edb92
MC		 823 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
824
cd94dd0b
AK		 825 /* initialize eeprom parameters */
826
827 if (e1000_init_eeprom_params(&adapter->hw)) {
828 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 829 goto err_eeprom;
cd94dd0b
AK		 830 }
831
96838a40 832 /* before reading the EEPROM, reset the controller to
1da177e4 833 * put the device in a known good starting state */
96838a40 834
1da177e4
LT		 835 e1000_reset_hw(&adapter->hw);
836
837 /* make sure the EEPROM is good */
838
96838a40 839 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 840 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 841 goto err_eeprom;
842 }
843
844 /* copy the MAC address out of the EEPROM */
845
96838a40 846 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 847 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
848 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 849 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 850
96838a40 851 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 852 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 853 goto err_eeprom;
854 }
855
856 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
857
858 e1000_get_bus_info(&adapter->hw);
859
860 init_timer(&adapter->tx_fifo_stall_timer);
861 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
862 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
863
864 init_timer(&adapter->watchdog_timer);
865 adapter->watchdog_timer.function = &e1000_watchdog;
866 adapter->watchdog_timer.data = (unsigned long) adapter;
867
1da177e4
LT		 868 init_timer(&adapter->phy_info_timer);
869 adapter->phy_info_timer.function = &e1000_update_phy_info;
870 adapter->phy_info_timer.data = (unsigned long) adapter;
871
87041639
JK		 872 INIT_WORK(&adapter->reset_task,
873 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 874
875 /* we're going to reset, so assume we have no link for now */
876
877 netif_carrier_off(netdev);
878 netif_stop_queue(netdev);
879
880 e1000_check_options(adapter);
881
882 /* Initial Wake on LAN setting
883 * If APM wake is enabled in the EEPROM,
884 * enable the ACPI Magic Packet filter
885 */
886
96838a40 887 switch (adapter->hw.mac_type) {
1da177e4
LT		 888 case e1000_82542_rev2_0:
889 case e1000_82542_rev2_1:
890 case e1000_82543:
891 break;
892 case e1000_82544:
893 e1000_read_eeprom(&adapter->hw,
894 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
895 eeprom_apme_mask = E1000_EEPROM_82544_APM;
896 break;
cd94dd0b
AK		 897 case e1000_ich8lan:
898 e1000_read_eeprom(&adapter->hw,
899 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
900 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
901 break;
1da177e4
LT		 902 case e1000_82546:
903 case e1000_82546_rev_3:
fd803241 904 case e1000_82571:
6418ecc6 905 case e1000_80003es2lan:
96838a40 906 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 907 e1000_read_eeprom(&adapter->hw,
908 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
909 break;
910 }
911 /* Fall Through */
912 default:
913 e1000_read_eeprom(&adapter->hw,
914 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
915 break;
916 }
96838a40 917 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 918 adapter->wol |= E1000_WUFC_MAG;
919
fb3d47d4
JK		 920 /* print bus type/speed/width info */
921 {
922 struct e1000_hw *hw = &adapter->hw;
923 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
924 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
925 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
926 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
927 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
928 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
929 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
930 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
931 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
932 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
933 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
934 "32-bit"));
935 }
936
937 for (i = 0; i < 6; i++)
938 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
939
1da177e4
LT		 940 /* reset the hardware with the new settings */
941 e1000_reset(adapter);
942
b55ccb35
JK		 943 /* If the controller is 82573 and f/w is AMT, do not set
944 * DRV_LOAD until the interface is up. For all other cases,
945 * let the f/w know that the h/w is now under the control
946 * of the driver. */
947 if (adapter->hw.mac_type != e1000_82573 ||
948 !e1000_check_mng_mode(&adapter->hw))
949 e1000_get_hw_control(adapter);
2d7edb92 950
1da177e4 951 strcpy(netdev->name, "eth%d");
96838a40 952 if ((err = register_netdev(netdev)))
1da177e4
LT		 953 goto err_register;
954
955 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
956
957 cards_found++;
958 return 0;
959
960err_register:
6dd62ab0
VA		 961 e1000_release_hw_control(adapter);
962err_eeprom:
963 if (!e1000_check_phy_reset_block(&adapter->hw))
964 e1000_phy_hw_reset(&adapter->hw);
965
cd94dd0b
AK		 966 if (adapter->hw.flash_address)
967 iounmap(adapter->hw.flash_address);
968err_flashmap:
6dd62ab0
VA		 969#ifdef CONFIG_E1000_NAPI
970 for (i = 0; i < adapter->num_rx_queues; i++)
971 dev_put(&adapter->polling_netdev[i]);
972#endif
973
974 kfree(adapter->tx_ring);
975 kfree(adapter->rx_ring);
976#ifdef CONFIG_E1000_NAPI
977 kfree(adapter->polling_netdev);
978#endif
1da177e4 979err_sw_init:
1da177e4
LT		 980 iounmap(adapter->hw.hw_addr);
981err_ioremap:
982 free_netdev(netdev);
983err_alloc_etherdev:
984 pci_release_regions(pdev);
6dd62ab0
VA		 985err_pci_reg:
986err_dma:
987 pci_disable_device(pdev);
1da177e4
LT		 988 return err;
989}
990
991/**
992 * e1000_remove - Device Removal Routine
993 * @pdev: PCI device information struct
994 *
995 * e1000_remove is called by the PCI subsystem to alert the driver
996 * that it should release a PCI device. The could be caused by a
997 * Hot-Plug event, or because the driver is going to be removed from
998 * memory.
999 **/
1000
1001static void __devexit
1002e1000_remove(struct pci_dev *pdev)
1003{
1004 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1005 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 1006 uint32_t manc;
581d708e
MC		 1007#ifdef CONFIG_E1000_NAPI
1008 int i;
1009#endif
1da177e4 1010
be2b28ed
JG		 1011 flush_scheduled_work();
1012
96838a40 1013 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 1014 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 1015 adapter->hw.media_type == e1000_media_type_copper) {
1016 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 1017 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 1018 manc |= E1000_MANC_ARP_EN;
1019 E1000_WRITE_REG(&adapter->hw, MANC, manc);
1020 }
1021 }
1022
b55ccb35
JK		 1023 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1024 * would have already happened in close and is redundant. */
1025 e1000_release_hw_control(adapter);
2d7edb92 1026
1da177e4 1027 unregister_netdev(netdev);
581d708e 1028#ifdef CONFIG_E1000_NAPI
f56799ea 1029 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1030 dev_put(&adapter->polling_netdev[i]);
581d708e 1031#endif
1da177e4 1032
96838a40 1033 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1034 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1035
24025e4e
MC		 1036 kfree(adapter->tx_ring);
1037 kfree(adapter->rx_ring);
1038#ifdef CONFIG_E1000_NAPI
1039 kfree(adapter->polling_netdev);
1040#endif
1041
1da177e4 1042 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1043 if (adapter->hw.flash_address)
1044 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1045 pci_release_regions(pdev);
1046
1047 free_netdev(netdev);
1048
1049 pci_disable_device(pdev);
1050}
1051
1052/**
1053 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1054 * @adapter: board private structure to initialize
1055 *
1056 * e1000_sw_init initializes the Adapter private data structure.
1057 * Fields are initialized based on PCI device information and
1058 * OS network device settings (MTU size).
1059 **/
1060
1061static int __devinit
1062e1000_sw_init(struct e1000_adapter *adapter)
1063{
1064 struct e1000_hw *hw = &adapter->hw;
1065 struct net_device *netdev = adapter->netdev;
1066 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1067#ifdef CONFIG_E1000_NAPI
1068 int i;
1069#endif
1da177e4
LT		 1070
1071 /* PCI config space info */
1072
1073 hw->vendor_id = pdev->vendor;
1074 hw->device_id = pdev->device;
1075 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1076 hw->subsystem_id = pdev->subsystem_device;
1077
1078 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1079
1080 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1081
eb0f8054 1082 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1083 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1084 hw->max_frame_size = netdev->mtu +
1085 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1086 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1087
1088 /* identify the MAC */
1089
96838a40 1090 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1091 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1092 return -EIO;
1093 }
1094
96838a40 1095 switch (hw->mac_type) {
1da177e4
LT		 1096 default:
1097 break;
1098 case e1000_82541:
1099 case e1000_82547:
1100 case e1000_82541_rev_2:
1101 case e1000_82547_rev_2:
1102 hw->phy_init_script = 1;
1103 break;
1104 }
1105
1106 e1000_set_media_type(hw);
1107
1108 hw->wait_autoneg_complete = FALSE;
1109 hw->tbi_compatibility_en = TRUE;
1110 hw->adaptive_ifs = TRUE;
1111
1112 /* Copper options */
1113
96838a40 1114 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1115 hw->mdix = AUTO_ALL_MODES;
1116 hw->disable_polarity_correction = FALSE;
1117 hw->master_slave = E1000_MASTER_SLAVE;
1118 }
1119
f56799ea
JK		 1120 adapter->num_tx_queues = 1;
1121 adapter->num_rx_queues = 1;
581d708e
MC		 1122
1123 if (e1000_alloc_queues(adapter)) {
1124 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1125 return -ENOMEM;
1126 }
1127
1128#ifdef CONFIG_E1000_NAPI
f56799ea 1129 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1130 adapter->polling_netdev[i].priv = adapter;
1131 adapter->polling_netdev[i].poll = &e1000_clean;
1132 adapter->polling_netdev[i].weight = 64;
1133 dev_hold(&adapter->polling_netdev[i]);
1134 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1135 }
7bfa4816 1136 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1137#endif
1138
1da177e4
LT		 1139 atomic_set(&adapter->irq_sem, 1);
1140 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1141
1142 return 0;
1143}
1144
581d708e
MC		 1145/**
1146 * e1000_alloc_queues - Allocate memory for all rings
1147 * @adapter: board private structure to initialize
1148 *
1149 * We allocate one ring per queue at run-time since we don't know the
1150 * number of queues at compile-time. The polling_netdev array is
1151 * intended for Multiqueue, but should work fine with a single queue.
1152 **/
1153
1154static int __devinit
1155e1000_alloc_queues(struct e1000_adapter *adapter)
1156{
1157 int size;
1158
f56799ea 1159 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1160 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1161 if (!adapter->tx_ring)
1162 return -ENOMEM;
1163 memset(adapter->tx_ring, 0, size);
1164
f56799ea 1165 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1166 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1167 if (!adapter->rx_ring) {
1168 kfree(adapter->tx_ring);
1169 return -ENOMEM;
1170 }
1171 memset(adapter->rx_ring, 0, size);
1172
1173#ifdef CONFIG_E1000_NAPI
f56799ea 1174 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1175 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1176 if (!adapter->polling_netdev) {
1177 kfree(adapter->tx_ring);
1178 kfree(adapter->rx_ring);
1179 return -ENOMEM;
1180 }
1181 memset(adapter->polling_netdev, 0, size);
1182#endif
1183
1184 return E1000_SUCCESS;
1185}
1186
1da177e4
LT		 1187/**
1188 * e1000_open - Called when a network interface is made active
1189 * @netdev: network interface device structure
1190 *
1191 * Returns 0 on success, negative value on failure
1192 *
1193 * The open entry point is called when a network interface is made
1194 * active by the system (IFF_UP). At this point all resources needed
1195 * for transmit and receive operations are allocated, the interrupt
1196 * handler is registered with the OS, the watchdog timer is started,
1197 * and the stack is notified that the interface is ready.
1198 **/
1199
1200static int
1201e1000_open(struct net_device *netdev)
1202{
60490fe0 1203 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1204 int err;
1205
2db10a08
AK		 1206 /* disallow open during test */
1207 if (test_bit(__E1000_DRIVER_TESTING, &adapter->flags))
1208 return -EBUSY;
1209
1da177e4
LT		 1210 /* allocate transmit descriptors */
1211
581d708e 1212 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1213 goto err_setup_tx;
1214
1215 /* allocate receive descriptors */
1216
581d708e 1217 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1218 goto err_setup_rx;
1219
2db10a08
AK		 1220 err = e1000_request_irq(adapter);
1221 if (err)
401a552b 1222 goto err_req_irq;
2db10a08 1223
79f05bf0
AK		 1224 e1000_power_up_phy(adapter);
1225
96838a40 1226 if ((err = e1000_up(adapter)))
1da177e4 1227 goto err_up;
2d7edb92 1228 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1229 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1230 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1231 e1000_update_mng_vlan(adapter);
1232 }
1da177e4 1233
b55ccb35
JK		 1234 /* If AMT is enabled, let the firmware know that the network
1235 * interface is now open */
1236 if (adapter->hw.mac_type == e1000_82573 &&
1237 e1000_check_mng_mode(&adapter->hw))
1238 e1000_get_hw_control(adapter);
1239
1da177e4
LT		 1240 return E1000_SUCCESS;
1241
1242err_up:
401a552b
VA		 1243 e1000_power_down_phy(adapter);
1244 e1000_free_irq(adapter);
1245err_req_irq:
581d708e 1246 e1000_free_all_rx_resources(adapter);
1da177e4 1247err_setup_rx:
581d708e 1248 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1249err_setup_tx:
1250 e1000_reset(adapter);
1251
1252 return err;
1253}
1254
1255/**
1256 * e1000_close - Disables a network interface
1257 * @netdev: network interface device structure
1258 *
1259 * Returns 0, this is not allowed to fail
1260 *
1261 * The close entry point is called when an interface is de-activated
1262 * by the OS. The hardware is still under the drivers control, but
1263 * needs to be disabled. A global MAC reset is issued to stop the
1264 * hardware, and all transmit and receive resources are freed.
1265 **/
1266
1267static int
1268e1000_close(struct net_device *netdev)
1269{
60490fe0 1270 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1271
2db10a08 1272 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1273 e1000_down(adapter);
79f05bf0 1274 e1000_power_down_phy(adapter);
2db10a08 1275 e1000_free_irq(adapter);
1da177e4 1276
581d708e
MC		 1277 e1000_free_all_tx_resources(adapter);
1278 e1000_free_all_rx_resources(adapter);
1da177e4 1279
96838a40 1280 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1281 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1282 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1283 }
b55ccb35
JK		 1284
1285 /* If AMT is enabled, let the firmware know that the network
1286 * interface is now closed */
1287 if (adapter->hw.mac_type == e1000_82573 &&
1288 e1000_check_mng_mode(&adapter->hw))
1289 e1000_release_hw_control(adapter);
1290
1da177e4
LT		 1291 return 0;
1292}
1293
1294/**
1295 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1296 * @adapter: address of board private structure
2d7edb92
MC		 1297 * @start: address of beginning of memory
1298 * @len: length of memory
1da177e4 1299 **/
e619d523 1300static boolean_t
1da177e4
LT		 1301e1000_check_64k_bound(struct e1000_adapter *adapter,
1302 void *start, unsigned long len)
1303{
1304 unsigned long begin = (unsigned long) start;
1305 unsigned long end = begin + len;
1306
2648345f
MC		 1307 /* First rev 82545 and 82546 need to not allow any memory
1308 * write location to cross 64k boundary due to errata 23 */
1da177e4 1309 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1310 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1311 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1312 }
1313
1314 return TRUE;
1315}
1316
1317/**
1318 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1319 * @adapter: board private structure
581d708e 1320 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1321 *
1322 * Return 0 on success, negative on failure
1323 **/
1324
3ad2cc67 1325static int
581d708e
MC		 1326e1000_setup_tx_resources(struct e1000_adapter *adapter,
1327 struct e1000_tx_ring *txdr)
1da177e4 1328{
1da177e4
LT		 1329 struct pci_dev *pdev = adapter->pdev;
1330 int size;
1331
1332 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1333 txdr->buffer_info = vmalloc(size);
96838a40 1334 if (!txdr->buffer_info) {
2648345f
MC		 1335 DPRINTK(PROBE, ERR,
1336 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1337 return -ENOMEM;
1338 }
1339 memset(txdr->buffer_info, 0, size);
1340
1341 /* round up to nearest 4K */
1342
1343 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1344 E1000_ROUNDUP(txdr->size, 4096);
1345
1346 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1347 if (!txdr->desc) {
1da177e4 1348setup_tx_desc_die:
1da177e4 1349 vfree(txdr->buffer_info);
2648345f
MC		 1350 DPRINTK(PROBE, ERR,
1351 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1352 return -ENOMEM;
1353 }
1354
2648345f 1355 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1356 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1357 void *olddesc = txdr->desc;
1358 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1359 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1360 "at %p\n", txdr->size, txdr->desc);
1361 /* Try again, without freeing the previous */
1da177e4 1362 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1363 /* Failed allocation, critical failure */
96838a40 1364 if (!txdr->desc) {
1da177e4
LT		 1365 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1366 goto setup_tx_desc_die;
1367 }
1368
1369 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1370 /* give up */
2648345f
MC		 1371 pci_free_consistent(pdev, txdr->size, txdr->desc,
1372 txdr->dma);
1da177e4
LT		 1373 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1374 DPRINTK(PROBE, ERR,
2648345f
MC		 1375 "Unable to allocate aligned memory "
1376 "for the transmit descriptor ring\n");
1da177e4
LT		 1377 vfree(txdr->buffer_info);
1378 return -ENOMEM;
1379 } else {
2648345f 1380 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1381 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1382 }
1383 }
1384 memset(txdr->desc, 0, txdr->size);
1385
1386 txdr->next_to_use = 0;
1387 txdr->next_to_clean = 0;
2ae76d98 1388 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1389
1390 return 0;
1391}
1392
581d708e
MC		 1393/**
1394 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1395 * (Descriptors) for all queues
1396 * @adapter: board private structure
1397 *
581d708e
MC		 1398 * Return 0 on success, negative on failure
1399 **/
1400
1401int
1402e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1403{
1404 int i, err = 0;
1405
f56799ea 1406 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1407 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1408 if (err) {
1409 DPRINTK(PROBE, ERR,
1410 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1411 for (i-- ; i >= 0; i--)
1412 e1000_free_tx_resources(adapter,
1413 &adapter->tx_ring[i]);
581d708e
MC		 1414 break;
1415 }
1416 }
1417
1418 return err;
1419}
1420
1da177e4
LT		 1421/**
1422 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1423 * @adapter: board private structure
1424 *
1425 * Configure the Tx unit of the MAC after a reset.
1426 **/
1427
1428static void
1429e1000_configure_tx(struct e1000_adapter *adapter)
1430{
581d708e
MC		 1431 uint64_t tdba;
1432 struct e1000_hw *hw = &adapter->hw;
1433 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1434 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1435
1436 /* Setup the HW Tx Head and Tail descriptor pointers */
1437
f56799ea 1438 switch (adapter->num_tx_queues) {
24025e4e
MC		 1439 case 1:
1440 default:
581d708e
MC		 1441 tdba = adapter->tx_ring[0].dma;
1442 tdlen = adapter->tx_ring[0].count *
1443 sizeof(struct e1000_tx_desc);
581d708e 1444 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1445 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1446 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1447 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1448 E1000_WRITE_REG(hw, TDH, 0);
581d708e
MC		 1449 adapter->tx_ring[0].tdh = E1000_TDH;
1450 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1451 break;
1452 }
1da177e4
LT		 1453
1454 /* Set the default values for the Tx Inter Packet Gap timer */
1455
0fadb059
JK		 1456 if (hw->media_type == e1000_media_type_fiber ||
1457 hw->media_type == e1000_media_type_internal_serdes)
1458 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1459 else
1460 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1461
581d708e 1462 switch (hw->mac_type) {
1da177e4
LT		 1463 case e1000_82542_rev2_0:
1464 case e1000_82542_rev2_1:
1465 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1466 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1467 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1468 break;
87041639
JK		 1469 case e1000_80003es2lan:
1470 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1471 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1472 break;
1da177e4 1473 default:
0fadb059
JK		 1474 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1475 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1476 break;
1da177e4 1477 }
0fadb059
JK		 1478 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1479 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1480 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1481
1482 /* Set the Tx Interrupt Delay register */
1483
581d708e
MC		 1484 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1485 if (hw->mac_type >= e1000_82540)
1486 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1487
1488 /* Program the Transmit Control Register */
1489
581d708e 1490 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1491
1492 tctl &= ~E1000_TCTL_CT;
7e6c9861 1493 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1494 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1495
7e6c9861
JK		 1496#ifdef DISABLE_MULR
1497 /* disable Multiple Reads for debugging */
1498 tctl &= ~E1000_TCTL_MULR;
1499#endif
1da177e4 1500
2ae76d98
MC		 1501 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1502 tarc = E1000_READ_REG(hw, TARC0);
1503 tarc |= ((1 << 25) | (1 << 21));
1504 E1000_WRITE_REG(hw, TARC0, tarc);
1505 tarc = E1000_READ_REG(hw, TARC1);
1506 tarc |= (1 << 25);
1507 if (tctl & E1000_TCTL_MULR)
1508 tarc &= ~(1 << 28);
1509 else
1510 tarc |= (1 << 28);
1511 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1512 } else if (hw->mac_type == e1000_80003es2lan) {
1513 tarc = E1000_READ_REG(hw, TARC0);
1514 tarc |= 1;
87041639
JK		 1515 E1000_WRITE_REG(hw, TARC0, tarc);
1516 tarc = E1000_READ_REG(hw, TARC1);
1517 tarc |= 1;
1518 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1519 }
1520
581d708e 1521 e1000_config_collision_dist(hw);
1da177e4
LT		 1522
1523 /* Setup Transmit Descriptor Settings for eop descriptor */
1524 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1525 E1000_TXD_CMD_IFCS;
1526
581d708e 1527 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1528 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1529 else
1530 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1531
1532 /* Cache if we're 82544 running in PCI-X because we'll
1533 * need this to apply a workaround later in the send path. */
581d708e
MC		 1534 if (hw->mac_type == e1000_82544 &&
1535 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1536 adapter->pcix_82544 = 1;
7e6c9861
JK		 1537
1538 E1000_WRITE_REG(hw, TCTL, tctl);
1539
1da177e4
LT		 1540}
1541
1542/**
1543 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1544 * @adapter: board private structure
581d708e 1545 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1546 *
1547 * Returns 0 on success, negative on failure
1548 **/
1549
3ad2cc67 1550static int
581d708e
MC		 1551e1000_setup_rx_resources(struct e1000_adapter *adapter,
1552 struct e1000_rx_ring *rxdr)
1da177e4 1553{
1da177e4 1554 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1555 int size, desc_len;
1da177e4
LT		 1556
1557 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1558 rxdr->buffer_info = vmalloc(size);
581d708e 1559 if (!rxdr->buffer_info) {
2648345f
MC		 1560 DPRINTK(PROBE, ERR,
1561 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1562 return -ENOMEM;
1563 }
1564 memset(rxdr->buffer_info, 0, size);
1565
2d7edb92
MC		 1566 size = sizeof(struct e1000_ps_page) * rxdr->count;
1567 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1568 if (!rxdr->ps_page) {
2d7edb92
MC		 1569 vfree(rxdr->buffer_info);
1570 DPRINTK(PROBE, ERR,
1571 "Unable to allocate memory for the receive descriptor ring\n");
1572 return -ENOMEM;
1573 }
1574 memset(rxdr->ps_page, 0, size);
1575
1576 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1577 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1578 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1579 vfree(rxdr->buffer_info);
1580 kfree(rxdr->ps_page);
1581 DPRINTK(PROBE, ERR,
1582 "Unable to allocate memory for the receive descriptor ring\n");
1583 return -ENOMEM;
1584 }
1585 memset(rxdr->ps_page_dma, 0, size);
1586
96838a40 1587 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1588 desc_len = sizeof(struct e1000_rx_desc);
1589 else
1590 desc_len = sizeof(union e1000_rx_desc_packet_split);
1591
1da177e4
LT		 1592 /* Round up to nearest 4K */
1593
2d7edb92 1594 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1595 E1000_ROUNDUP(rxdr->size, 4096);
1596
1597 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1598
581d708e
MC		 1599 if (!rxdr->desc) {
1600 DPRINTK(PROBE, ERR,
1601 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1602setup_rx_desc_die:
1da177e4 1603 vfree(rxdr->buffer_info);
2d7edb92
MC		 1604 kfree(rxdr->ps_page);
1605 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1606 return -ENOMEM;
1607 }
1608
2648345f 1609 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1610 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1611 void *olddesc = rxdr->desc;
1612 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1613 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1614 "at %p\n", rxdr->size, rxdr->desc);
1615 /* Try again, without freeing the previous */
1da177e4 1616 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1617 /* Failed allocation, critical failure */
581d708e 1618 if (!rxdr->desc) {
1da177e4 1619 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1620 DPRINTK(PROBE, ERR,
1621 "Unable to allocate memory "
1622 "for the receive descriptor ring\n");
1da177e4
LT		 1623 goto setup_rx_desc_die;
1624 }
1625
1626 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1627 /* give up */
2648345f
MC		 1628 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1629 rxdr->dma);
1da177e4 1630 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1631 DPRINTK(PROBE, ERR,
1632 "Unable to allocate aligned memory "
1633 "for the receive descriptor ring\n");
581d708e 1634 goto setup_rx_desc_die;
1da177e4 1635 } else {
2648345f 1636 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1637 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1638 }
1639 }
1640 memset(rxdr->desc, 0, rxdr->size);
1641
1642 rxdr->next_to_clean = 0;
1643 rxdr->next_to_use = 0;
1644
1645 return 0;
1646}
1647
581d708e
MC		 1648/**
1649 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1650 * (Descriptors) for all queues
1651 * @adapter: board private structure
1652 *
581d708e
MC		 1653 * Return 0 on success, negative on failure
1654 **/
1655
1656int
1657e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1658{
1659 int i, err = 0;
1660
f56799ea 1661 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1662 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1663 if (err) {
1664 DPRINTK(PROBE, ERR,
1665 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1666 for (i-- ; i >= 0; i--)
1667 e1000_free_rx_resources(adapter,
1668 &adapter->rx_ring[i]);
581d708e
MC		 1669 break;
1670 }
1671 }
1672
1673 return err;
1674}
1675
1da177e4 1676/**
2648345f 1677 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1678 * @adapter: Board private structure
1679 **/
e4c811c9
MC		 1680#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1681 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1682static void
1683e1000_setup_rctl(struct e1000_adapter *adapter)
1684{
2d7edb92
MC		 1685 uint32_t rctl, rfctl;
1686 uint32_t psrctl = 0;
35ec56bb 1687#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1688 uint32_t pages = 0;
1689#endif
1da177e4
LT		 1690
1691 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1692
1693 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1694
1695 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1696 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1697 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1698
0fadb059 1699 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1700 rctl |= E1000_RCTL_SBP;
1701 else
1702 rctl &= ~E1000_RCTL_SBP;
1703
2d7edb92
MC		 1704 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1705 rctl &= ~E1000_RCTL_LPE;
1706 else
1707 rctl |= E1000_RCTL_LPE;
1708
1da177e4 1709 /* Setup buffer sizes */
9e2feace
AK		 1710 rctl &= ~E1000_RCTL_SZ_4096;
1711 rctl |= E1000_RCTL_BSEX;
1712 switch (adapter->rx_buffer_len) {
1713 case E1000_RXBUFFER_256:
1714 rctl |= E1000_RCTL_SZ_256;
1715 rctl &= ~E1000_RCTL_BSEX;
1716 break;
1717 case E1000_RXBUFFER_512:
1718 rctl |= E1000_RCTL_SZ_512;
1719 rctl &= ~E1000_RCTL_BSEX;
1720 break;
1721 case E1000_RXBUFFER_1024:
1722 rctl |= E1000_RCTL_SZ_1024;
1723 rctl &= ~E1000_RCTL_BSEX;
1724 break;
a1415ee6
JK		 1725 case E1000_RXBUFFER_2048:
1726 default:
1727 rctl |= E1000_RCTL_SZ_2048;
1728 rctl &= ~E1000_RCTL_BSEX;
1729 break;
1730 case E1000_RXBUFFER_4096:
1731 rctl |= E1000_RCTL_SZ_4096;
1732 break;
1733 case E1000_RXBUFFER_8192:
1734 rctl |= E1000_RCTL_SZ_8192;
1735 break;
1736 case E1000_RXBUFFER_16384:
1737 rctl |= E1000_RCTL_SZ_16384;
1738 break;
2d7edb92
MC		 1739 }
1740
35ec56bb 1741#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1742 /* 82571 and greater support packet-split where the protocol
1743 * header is placed in skb->data and the packet data is
1744 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1745 * In the case of a non-split, skb->data is linearly filled,
1746 * followed by the page buffers. Therefore, skb->data is
1747 * sized to hold the largest protocol header.
1748 */
e4c811c9
MC		 1749 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1750 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1751 PAGE_SIZE <= 16384)
1752 adapter->rx_ps_pages = pages;
1753 else
1754 adapter->rx_ps_pages = 0;
2d7edb92 1755#endif
e4c811c9 1756 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1757 /* Configure extra packet-split registers */
1758 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1759 rfctl |= E1000_RFCTL_EXTEN;
1760 /* disable IPv6 packet split support */
1761 rfctl |= E1000_RFCTL_IPV6_DIS;
1762 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1763
7dfee0cb 1764 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1765
2d7edb92
MC		 1766 psrctl |= adapter->rx_ps_bsize0 >>
1767 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1768
1769 switch (adapter->rx_ps_pages) {
1770 case 3:
1771 psrctl |= PAGE_SIZE <<
1772 E1000_PSRCTL_BSIZE3_SHIFT;
1773 case 2:
1774 psrctl |= PAGE_SIZE <<
1775 E1000_PSRCTL_BSIZE2_SHIFT;
1776 case 1:
1777 psrctl |= PAGE_SIZE >>
1778 E1000_PSRCTL_BSIZE1_SHIFT;
1779 break;
1780 }
2d7edb92
MC		 1781
1782 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1783 }
1784
1785 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1786}
1787
1788/**
1789 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1790 * @adapter: board private structure
1791 *
1792 * Configure the Rx unit of the MAC after a reset.
1793 **/
1794
1795static void
1796e1000_configure_rx(struct e1000_adapter *adapter)
1797{
581d708e
MC		 1798 uint64_t rdba;
1799 struct e1000_hw *hw = &adapter->hw;
1800 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1801
e4c811c9 1802 if (adapter->rx_ps_pages) {
0f15a8fa 1803 /* this is a 32 byte descriptor */
581d708e 1804 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1805 sizeof(union e1000_rx_desc_packet_split);
1806 adapter->clean_rx = e1000_clean_rx_irq_ps;
1807 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1808 } else {
581d708e
MC		 1809 rdlen = adapter->rx_ring[0].count *
1810 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1811 adapter->clean_rx = e1000_clean_rx_irq;
1812 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1813 }
1da177e4
LT		 1814
1815 /* disable receives while setting up the descriptors */
581d708e
MC		 1816 rctl = E1000_READ_REG(hw, RCTL);
1817 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1818
1819 /* set the Receive Delay Timer Register */
581d708e 1820 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1821
581d708e
MC		 1822 if (hw->mac_type >= e1000_82540) {
1823 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1824 if (adapter->itr > 1)
581d708e 1825 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1826 1000000000 / (adapter->itr * 256));
1827 }
1828
2ae76d98 1829 if (hw->mac_type >= e1000_82571) {
2ae76d98 1830 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1831 /* Reset delay timers after every interrupt */
6fc7a7ec 1832 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1833#ifdef CONFIG_E1000_NAPI
1834 /* Auto-Mask interrupts upon ICR read. */
1835 ctrl_ext |= E1000_CTRL_EXT_IAME;
1836#endif
2ae76d98 1837 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1838 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1839 E1000_WRITE_FLUSH(hw);
1840 }
1841
581d708e
MC		 1842 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1843 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1844 switch (adapter->num_rx_queues) {
24025e4e
MC		 1845 case 1:
1846 default:
581d708e 1847 rdba = adapter->rx_ring[0].dma;
581d708e 1848 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 1849 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1850 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 1851 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 1852 E1000_WRITE_REG(hw, RDH, 0);
581d708e
MC		 1853 adapter->rx_ring[0].rdh = E1000_RDH;
1854 adapter->rx_ring[0].rdt = E1000_RDT;
1855 break;
24025e4e
MC		 1856 }
1857
1da177e4 1858 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1859 if (hw->mac_type >= e1000_82543) {
1860 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1861 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1862 rxcsum |= E1000_RXCSUM_TUOFL;
1863
868d5309 1864 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1865 * Must be used in conjunction with packet-split. */
96838a40
JB		 1866 if ((hw->mac_type >= e1000_82571) &&
1867 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1868 rxcsum |= E1000_RXCSUM_IPPCSE;
1869 }
1870 } else {
1871 rxcsum &= ~E1000_RXCSUM_TUOFL;
1872 /* don't need to clear IPPCSE as it defaults to 0 */
1873 }
581d708e 1874 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1875 }
1876
1877 /* Enable Receives */
581d708e 1878 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1879}
1880
1881/**
581d708e 1882 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1883 * @adapter: board private structure
581d708e 1884 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1885 *
1886 * Free all transmit software resources
1887 **/
1888
3ad2cc67 1889static void
581d708e
MC		 1890e1000_free_tx_resources(struct e1000_adapter *adapter,
1891 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1892{
1893 struct pci_dev *pdev = adapter->pdev;
1894
581d708e 1895 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1896
581d708e
MC		 1897 vfree(tx_ring->buffer_info);
1898 tx_ring->buffer_info = NULL;
1da177e4 1899
581d708e 1900 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1901
581d708e
MC		 1902 tx_ring->desc = NULL;
1903}
1904
1905/**
1906 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1907 * @adapter: board private structure
1908 *
1909 * Free all transmit software resources
1910 **/
1911
1912void
1913e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1914{
1915 int i;
1916
f56799ea 1917 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1918 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1919}
1920
e619d523 1921static void
1da177e4
LT		 1922e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1923 struct e1000_buffer *buffer_info)
1924{
96838a40 1925 if (buffer_info->dma) {
2648345f
MC		 1926 pci_unmap_page(adapter->pdev,
1927 buffer_info->dma,
1928 buffer_info->length,
1929 PCI_DMA_TODEVICE);
1da177e4 1930 }
8241e35e 1931 if (buffer_info->skb)
1da177e4 1932 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1933 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1934}
1935
1936/**
1937 * e1000_clean_tx_ring - Free Tx Buffers
1938 * @adapter: board private structure
581d708e 1939 * @tx_ring: ring to be cleaned
1da177e4
LT		 1940 **/
1941
1942static void
581d708e
MC		 1943e1000_clean_tx_ring(struct e1000_adapter *adapter,
1944 struct e1000_tx_ring *tx_ring)
1da177e4 1945{
1da177e4
LT		 1946 struct e1000_buffer *buffer_info;
1947 unsigned long size;
1948 unsigned int i;
1949
1950 /* Free all the Tx ring sk_buffs */
1951
96838a40 1952 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1953 buffer_info = &tx_ring->buffer_info[i];
1954 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1955 }
1956
1957 size = sizeof(struct e1000_buffer) * tx_ring->count;
1958 memset(tx_ring->buffer_info, 0, size);
1959
1960 /* Zero out the descriptor ring */
1961
1962 memset(tx_ring->desc, 0, tx_ring->size);
1963
1964 tx_ring->next_to_use = 0;
1965 tx_ring->next_to_clean = 0;
fd803241 1966 tx_ring->last_tx_tso = 0;
1da177e4 1967
581d708e
MC		 1968 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1969 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1970}
1971
1972/**
1973 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1974 * @adapter: board private structure
1975 **/
1976
1977static void
1978e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1979{
1980 int i;
1981
f56799ea 1982 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1983 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1984}
1985
1986/**
1987 * e1000_free_rx_resources - Free Rx Resources
1988 * @adapter: board private structure
581d708e 1989 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1990 *
1991 * Free all receive software resources
1992 **/
1993
3ad2cc67 1994static void
581d708e
MC		 1995e1000_free_rx_resources(struct e1000_adapter *adapter,
1996 struct e1000_rx_ring *rx_ring)
1da177e4 1997{
1da177e4
LT		 1998 struct pci_dev *pdev = adapter->pdev;
1999
581d708e 2000 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2001
2002 vfree(rx_ring->buffer_info);
2003 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2004 kfree(rx_ring->ps_page);
2005 rx_ring->ps_page = NULL;
2006 kfree(rx_ring->ps_page_dma);
2007 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2008
2009 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2010
2011 rx_ring->desc = NULL;
2012}
2013
2014/**
581d708e 2015 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2016 * @adapter: board private structure
581d708e
MC		 2017 *
2018 * Free all receive software resources
2019 **/
2020
2021void
2022e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2023{
2024 int i;
2025
f56799ea 2026 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2027 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2028}
2029
2030/**
2031 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2032 * @adapter: board private structure
2033 * @rx_ring: ring to free buffers from
1da177e4
LT		 2034 **/
2035
2036static void
581d708e
MC		 2037e1000_clean_rx_ring(struct e1000_adapter *adapter,
2038 struct e1000_rx_ring *rx_ring)
1da177e4 2039{
1da177e4 2040 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2041 struct e1000_ps_page *ps_page;
2042 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2043 struct pci_dev *pdev = adapter->pdev;
2044 unsigned long size;
2d7edb92 2045 unsigned int i, j;
1da177e4
LT		 2046
2047 /* Free all the Rx ring sk_buffs */
96838a40 2048 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2049 buffer_info = &rx_ring->buffer_info[i];
96838a40 2050 if (buffer_info->skb) {
1da177e4
LT		 2051 pci_unmap_single(pdev,
2052 buffer_info->dma,
2053 buffer_info->length,
2054 PCI_DMA_FROMDEVICE);
2055
2056 dev_kfree_skb(buffer_info->skb);
2057 buffer_info->skb = NULL;
997f5cbd
JK		 2058 }
2059 ps_page = &rx_ring->ps_page[i];
2060 ps_page_dma = &rx_ring->ps_page_dma[i];
2061 for (j = 0; j < adapter->rx_ps_pages; j++) {
2062 if (!ps_page->ps_page[j]) break;
2063 pci_unmap_page(pdev,
2064 ps_page_dma->ps_page_dma[j],
2065 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2066 ps_page_dma->ps_page_dma[j] = 0;
2067 put_page(ps_page->ps_page[j]);
2068 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2069 }
2070 }
2071
2072 size = sizeof(struct e1000_buffer) * rx_ring->count;
2073 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2074 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2075 memset(rx_ring->ps_page, 0, size);
2076 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2077 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2078
2079 /* Zero out the descriptor ring */
2080
2081 memset(rx_ring->desc, 0, rx_ring->size);
2082
2083 rx_ring->next_to_clean = 0;
2084 rx_ring->next_to_use = 0;
2085
581d708e
MC		 2086 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2087 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2088}
2089
2090/**
2091 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2092 * @adapter: board private structure
2093 **/
2094
2095static void
2096e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2097{
2098 int i;
2099
f56799ea 2100 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2101 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2102}
2103
2104/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2105 * and memory write and invalidate disabled for certain operations
2106 */
2107static void
2108e1000_enter_82542_rst(struct e1000_adapter *adapter)
2109{
2110 struct net_device *netdev = adapter->netdev;
2111 uint32_t rctl;
2112
2113 e1000_pci_clear_mwi(&adapter->hw);
2114
2115 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2116 rctl |= E1000_RCTL_RST;
2117 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2118 E1000_WRITE_FLUSH(&adapter->hw);
2119 mdelay(5);
2120
96838a40 2121 if (netif_running(netdev))
581d708e 2122 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2123}
2124
2125static void
2126e1000_leave_82542_rst(struct e1000_adapter *adapter)
2127{
2128 struct net_device *netdev = adapter->netdev;
2129 uint32_t rctl;
2130
2131 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2132 rctl &= ~E1000_RCTL_RST;
2133 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2134 E1000_WRITE_FLUSH(&adapter->hw);
2135 mdelay(5);
2136
96838a40 2137 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2138 e1000_pci_set_mwi(&adapter->hw);
2139
96838a40 2140 if (netif_running(netdev)) {
72d64a43
JK		 2141 /* No need to loop, because 82542 supports only 1 queue */
2142 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2143 e1000_configure_rx(adapter);
72d64a43 2144 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2145 }
2146}
2147
2148/**
2149 * e1000_set_mac - Change the Ethernet Address of the NIC
2150 * @netdev: network interface device structure
2151 * @p: pointer to an address structure
2152 *
2153 * Returns 0 on success, negative on failure
2154 **/
2155
2156static int
2157e1000_set_mac(struct net_device *netdev, void *p)
2158{
60490fe0 2159 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2160 struct sockaddr *addr = p;
2161
96838a40 2162 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2163 return -EADDRNOTAVAIL;
2164
2165 /* 82542 2.0 needs to be in reset to write receive address registers */
2166
96838a40 2167 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2168 e1000_enter_82542_rst(adapter);
2169
2170 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2171 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2172
2173 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2174
868d5309
MC		 2175 /* With 82571 controllers, LAA may be overwritten (with the default)
2176 * due to controller reset from the other port. */
2177 if (adapter->hw.mac_type == e1000_82571) {
2178 /* activate the work around */
2179 adapter->hw.laa_is_present = 1;
2180
96838a40
JB		 2181 /* Hold a copy of the LAA in RAR[14] This is done so that
2182 * between the time RAR[0] gets clobbered and the time it
2183 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2184 * of the RARs and no incoming packets directed to this port
96838a40 2185 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2186 * RAR[14] */
96838a40 2187 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2188 E1000_RAR_ENTRIES - 1);
2189 }
2190
96838a40 2191 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2192 e1000_leave_82542_rst(adapter);
2193
2194 return 0;
2195}
2196
2197/**
2198 * e1000_set_multi - Multicast and Promiscuous mode set
2199 * @netdev: network interface device structure
2200 *
2201 * The set_multi entry point is called whenever the multicast address
2202 * list or the network interface flags are updated. This routine is
2203 * responsible for configuring the hardware for proper multicast,
2204 * promiscuous mode, and all-multi behavior.
2205 **/
2206
2207static void
2208e1000_set_multi(struct net_device *netdev)
2209{
60490fe0 2210 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2211 struct e1000_hw *hw = &adapter->hw;
2212 struct dev_mc_list *mc_ptr;
2213 uint32_t rctl;
2214 uint32_t hash_value;
868d5309 2215 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2216 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2217 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2218 E1000_NUM_MTA_REGISTERS;
2219
2220 if (adapter->hw.mac_type == e1000_ich8lan)
2221 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2222
868d5309
MC		 2223 /* reserve RAR[14] for LAA over-write work-around */
2224 if (adapter->hw.mac_type == e1000_82571)
2225 rar_entries--;
1da177e4 2226
2648345f
MC		 2227 /* Check for Promiscuous and All Multicast modes */
2228
1da177e4
LT		 2229 rctl = E1000_READ_REG(hw, RCTL);
2230
96838a40 2231 if (netdev->flags & IFF_PROMISC) {
1da177e4 2232 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2233 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2234 rctl |= E1000_RCTL_MPE;
2235 rctl &= ~E1000_RCTL_UPE;
2236 } else {
2237 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2238 }
2239
2240 E1000_WRITE_REG(hw, RCTL, rctl);
2241
2242 /* 82542 2.0 needs to be in reset to write receive address registers */
2243
96838a40 2244 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2245 e1000_enter_82542_rst(adapter);
2246
2247 /* load the first 14 multicast address into the exact filters 1-14
2248 * RAR 0 is used for the station MAC adddress
2249 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2250 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2251 */
2252 mc_ptr = netdev->mc_list;
2253
96838a40 2254 for (i = 1; i < rar_entries; i++) {
868d5309 2255 if (mc_ptr) {
1da177e4
LT		 2256 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2257 mc_ptr = mc_ptr->next;
2258 } else {
2259 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2260 E1000_WRITE_FLUSH(hw);
1da177e4 2261 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2262 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2263 }
2264 }
2265
2266 /* clear the old settings from the multicast hash table */
2267
cd94dd0b 2268 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2269 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2270 E1000_WRITE_FLUSH(hw);
2271 }
1da177e4
LT		 2272
2273 /* load any remaining addresses into the hash table */
2274
96838a40 2275 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2276 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2277 e1000_mta_set(hw, hash_value);
2278 }
2279
96838a40 2280 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2281 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2282}
2283
2284/* Need to wait a few seconds after link up to get diagnostic information from
2285 * the phy */
2286
2287static void
2288e1000_update_phy_info(unsigned long data)
2289{
2290 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2291 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2292}
2293
2294/**
2295 * e1000_82547_tx_fifo_stall - Timer Call-back
2296 * @data: pointer to adapter cast into an unsigned long
2297 **/
2298
2299static void
2300e1000_82547_tx_fifo_stall(unsigned long data)
2301{
2302 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2303 struct net_device *netdev = adapter->netdev;
2304 uint32_t tctl;
2305
96838a40
JB		 2306 if (atomic_read(&adapter->tx_fifo_stall)) {
2307 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2308 E1000_READ_REG(&adapter->hw, TDH)) &&
2309 (E1000_READ_REG(&adapter->hw, TDFT) ==
2310 E1000_READ_REG(&adapter->hw, TDFH)) &&
2311 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2312 E1000_READ_REG(&adapter->hw, TDFHS))) {
2313 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2314 E1000_WRITE_REG(&adapter->hw, TCTL,
2315 tctl & ~E1000_TCTL_EN);
2316 E1000_WRITE_REG(&adapter->hw, TDFT,
2317 adapter->tx_head_addr);
2318 E1000_WRITE_REG(&adapter->hw, TDFH,
2319 adapter->tx_head_addr);
2320 E1000_WRITE_REG(&adapter->hw, TDFTS,
2321 adapter->tx_head_addr);
2322 E1000_WRITE_REG(&adapter->hw, TDFHS,
2323 adapter->tx_head_addr);
2324 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2325 E1000_WRITE_FLUSH(&adapter->hw);
2326
2327 adapter->tx_fifo_head = 0;
2328 atomic_set(&adapter->tx_fifo_stall, 0);
2329 netif_wake_queue(netdev);
2330 } else {
2331 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2332 }
2333 }
2334}
2335
2336/**
2337 * e1000_watchdog - Timer Call-back
2338 * @data: pointer to adapter cast into an unsigned long
2339 **/
2340static void
2341e1000_watchdog(unsigned long data)
2342{
2343 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2344 struct net_device *netdev = adapter->netdev;
545c67c0 2345 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2346 uint32_t link, tctl;
cd94dd0b
AK		 2347 int32_t ret_val;
2348
2349 ret_val = e1000_check_for_link(&adapter->hw);
2350 if ((ret_val == E1000_ERR_PHY) &&
2351 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2352 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2353 /* See e1000_kumeran_lock_loss_workaround() */
2354 DPRINTK(LINK, INFO,
2355 "Gigabit has been disabled, downgrading speed\n");
2356 }
2d7edb92
MC		 2357 if (adapter->hw.mac_type == e1000_82573) {
2358 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2359 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2360 e1000_update_mng_vlan(adapter);
96838a40 2361 }
1da177e4 2362
96838a40 2363 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2364 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2365 link = !adapter->hw.serdes_link_down;
2366 else
2367 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2368
96838a40
JB		 2369 if (link) {
2370 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2371 boolean_t txb2b = 1;
1da177e4
LT		 2372 e1000_get_speed_and_duplex(&adapter->hw,
2373 &adapter->link_speed,
2374 &adapter->link_duplex);
2375
2376 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2377 adapter->link_speed,
2378 adapter->link_duplex == FULL_DUPLEX ?
2379 "Full Duplex" : "Half Duplex");
2380
7e6c9861
JK		 2381 /* tweak tx_queue_len according to speed/duplex
2382 * and adjust the timeout factor */
66a2b0a3
JK		 2383 netdev->tx_queue_len = adapter->tx_queue_len;
2384 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2385 switch (adapter->link_speed) {
2386 case SPEED_10:
fe7fe28e 2387 txb2b = 0;
7e6c9861
JK		 2388 netdev->tx_queue_len = 10;
2389 adapter->tx_timeout_factor = 8;
2390 break;
2391 case SPEED_100:
fe7fe28e 2392 txb2b = 0;
7e6c9861
JK		 2393 netdev->tx_queue_len = 100;
2394 /* maybe add some timeout factor ? */
2395 break;
2396 }
2397
fe7fe28e 2398 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2399 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2400 txb2b == 0) {
7e6c9861
JK		 2401#define SPEED_MODE_BIT (1 << 21)
2402 uint32_t tarc0;
2403 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2404 tarc0 &= ~SPEED_MODE_BIT;
2405 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2406 }
2407
2408#ifdef NETIF_F_TSO
2409 /* disable TSO for pcie and 10/100 speeds, to avoid
2410 * some hardware issues */
2411 if (!adapter->tso_force &&
2412 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2413 switch (adapter->link_speed) {
2414 case SPEED_10:
66a2b0a3 2415 case SPEED_100:
7e6c9861
JK		 2416 DPRINTK(PROBE,INFO,
2417 "10/100 speed: disabling TSO\n");
2418 netdev->features &= ~NETIF_F_TSO;
2419 break;
2420 case SPEED_1000:
2421 netdev->features |= NETIF_F_TSO;
2422 break;
2423 default:
2424 /* oops */
66a2b0a3
JK		 2425 break;
2426 }
2427 }
7e6c9861
JK		 2428#endif
2429
2430 /* enable transmits in the hardware, need to do this
2431 * after setting TARC0 */
2432 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2433 tctl |= E1000_TCTL_EN;
2434 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2435
1da177e4
LT		 2436 netif_carrier_on(netdev);
2437 netif_wake_queue(netdev);
2438 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2439 adapter->smartspeed = 0;
2440 }
2441 } else {
96838a40 2442 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2443 adapter->link_speed = 0;
2444 adapter->link_duplex = 0;
2445 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2446 netif_carrier_off(netdev);
2447 netif_stop_queue(netdev);
2448 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2449
2450 /* 80003ES2LAN workaround--
2451 * For packet buffer work-around on link down event;
2452 * disable receives in the ISR and
2453 * reset device here in the watchdog
2454 */
8fc897b0 2455 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2456 /* reset device */
2457 schedule_work(&adapter->reset_task);
1da177e4
LT		 2458 }
2459
2460 e1000_smartspeed(adapter);
2461 }
2462
2463 e1000_update_stats(adapter);
2464
2465 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2466 adapter->tpt_old = adapter->stats.tpt;
2467 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2468 adapter->colc_old = adapter->stats.colc;
2469
2470 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2471 adapter->gorcl_old = adapter->stats.gorcl;
2472 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2473 adapter->gotcl_old = adapter->stats.gotcl;
2474
2475 e1000_update_adaptive(&adapter->hw);
2476
f56799ea 2477 if (!netif_carrier_ok(netdev)) {
581d708e 2478 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2479 /* We've lost link, so the controller stops DMA,
2480 * but we've got queued Tx work that's never going
2481 * to get done, so reset controller to flush Tx.
2482 * (Do the reset outside of interrupt context). */
87041639
JK		 2483 adapter->tx_timeout_count++;
2484 schedule_work(&adapter->reset_task);
1da177e4
LT		 2485 }
2486 }
2487
2488 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2489 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2490 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2491 * asymmetrical Tx or Rx gets ITR=8000; everyone
2492 * else is between 2000-8000. */
2493 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2494 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2495 adapter->gotcl - adapter->gorcl :
2496 adapter->gorcl - adapter->gotcl) / 10000;
2497 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2498 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2499 }
2500
2501 /* Cause software interrupt to ensure rx ring is cleaned */
2502 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2503
2648345f 2504 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2505 adapter->detect_tx_hung = TRUE;
2506
96838a40 2507 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2508 * reset from the other port. Set the appropriate LAA in RAR[0] */
2509 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2510 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2511
1da177e4
LT		 2512 /* Reset the timer */
2513 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2514}
2515
2516#define E1000_TX_FLAGS_CSUM 0x00000001
2517#define E1000_TX_FLAGS_VLAN 0x00000002
2518#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2519#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2520#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2521#define E1000_TX_FLAGS_VLAN_SHIFT 16
2522
e619d523 2523static int
581d708e
MC		 2524e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2525 struct sk_buff *skb)
1da177e4
LT		 2526{
2527#ifdef NETIF_F_TSO
2528 struct e1000_context_desc *context_desc;
545c67c0 2529 struct e1000_buffer *buffer_info;
1da177e4
LT		 2530 unsigned int i;
2531 uint32_t cmd_length = 0;
2d7edb92 2532 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2533 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2534 int err;
2535
89114afd 2536 if (skb_is_gso(skb)) {
1da177e4
LT		 2537 if (skb_header_cloned(skb)) {
2538 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2539 if (err)
2540 return err;
2541 }
2542
2543 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
7967168c 2544 mss = skb_shinfo(skb)->gso_size;
60828236 2545 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2546 skb->nh.iph->tot_len = 0;
2547 skb->nh.iph->check = 0;
2548 skb->h.th->check =
2549 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2550 skb->nh.iph->daddr,
2551 0,
2552 IPPROTO_TCP,
2553 0);
2554 cmd_length = E1000_TXD_CMD_IP;
2555 ipcse = skb->h.raw - skb->data - 1;
2556#ifdef NETIF_F_TSO_IPV6
e15fdd03 2557 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2d7edb92
MC		 2558 skb->nh.ipv6h->payload_len = 0;
2559 skb->h.th->check =
2560 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2561 &skb->nh.ipv6h->daddr,
2562 0,
2563 IPPROTO_TCP,
2564 0);
2565 ipcse = 0;
2566#endif
2567 }
1da177e4
LT		 2568 ipcss = skb->nh.raw - skb->data;
2569 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2570 tucss = skb->h.raw - skb->data;
2571 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2572 tucse = 0;
2573
2574 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2575 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2576
581d708e
MC		 2577 i = tx_ring->next_to_use;
2578 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2579 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2580
2581 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2582 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2583 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2584 context_desc->upper_setup.tcp_fields.tucss = tucss;
2585 context_desc->upper_setup.tcp_fields.tucso = tucso;
2586 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2587 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2588 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2589 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2590
545c67c0
JK		 2591 buffer_info->time_stamp = jiffies;
2592
581d708e
MC		 2593 if (++i == tx_ring->count) i = 0;
2594 tx_ring->next_to_use = i;
1da177e4 2595
8241e35e 2596 return TRUE;
1da177e4
LT		 2597 }
2598#endif
2599
8241e35e 2600 return FALSE;
1da177e4
LT		 2601}
2602
e619d523 2603static boolean_t
581d708e
MC		 2604e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2605 struct sk_buff *skb)
1da177e4
LT		 2606{
2607 struct e1000_context_desc *context_desc;
545c67c0 2608 struct e1000_buffer *buffer_info;
1da177e4
LT		 2609 unsigned int i;
2610 uint8_t css;
2611
96838a40 2612 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2613 css = skb->h.raw - skb->data;
2614
581d708e 2615 i = tx_ring->next_to_use;
545c67c0 2616 buffer_info = &tx_ring->buffer_info[i];
581d708e 2617 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2618
2619 context_desc->upper_setup.tcp_fields.tucss = css;
2620 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2621 context_desc->upper_setup.tcp_fields.tucse = 0;
2622 context_desc->tcp_seg_setup.data = 0;
2623 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2624
545c67c0
JK		 2625 buffer_info->time_stamp = jiffies;
2626
581d708e
MC		 2627 if (unlikely(++i == tx_ring->count)) i = 0;
2628 tx_ring->next_to_use = i;
1da177e4
LT		 2629
2630 return TRUE;
2631 }
2632
2633 return FALSE;
2634}
2635
2636#define E1000_MAX_TXD_PWR 12
2637#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2638
e619d523 2639static int
581d708e
MC		 2640e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2641 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2642 unsigned int nr_frags, unsigned int mss)
1da177e4 2643{
1da177e4
LT		 2644 struct e1000_buffer *buffer_info;
2645 unsigned int len = skb->len;
2646 unsigned int offset = 0, size, count = 0, i;
2647 unsigned int f;
2648 len -= skb->data_len;
2649
2650 i = tx_ring->next_to_use;
2651
96838a40 2652 while (len) {
1da177e4
LT		 2653 buffer_info = &tx_ring->buffer_info[i];
2654 size = min(len, max_per_txd);
2655#ifdef NETIF_F_TSO
fd803241
JK		 2656 /* Workaround for Controller erratum --
2657 * descriptor for non-tso packet in a linear SKB that follows a
2658 * tso gets written back prematurely before the data is fully
0f15a8fa 2659 * DMA'd to the controller */
fd803241 2660 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 2661 !skb_is_gso(skb)) {
fd803241
JK		 2662 tx_ring->last_tx_tso = 0;
2663 size -= 4;
2664 }
2665
1da177e4
LT		 2666 /* Workaround for premature desc write-backs
2667 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2668 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2669 size -= 4;
2670#endif
97338bde
MC		 2671 /* work-around for errata 10 and it applies
2672 * to all controllers in PCI-X mode
2673 * The fix is to make sure that the first descriptor of a
2674 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2675 */
96838a40 2676 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2677 (size > 2015) && count == 0))
2678 size = 2015;
96838a40 2679
1da177e4
LT		 2680 /* Workaround for potential 82544 hang in PCI-X. Avoid
2681 * terminating buffers within evenly-aligned dwords. */
96838a40 2682 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2683 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2684 size > 4))
2685 size -= 4;
2686
2687 buffer_info->length = size;
2688 buffer_info->dma =
2689 pci_map_single(adapter->pdev,
2690 skb->data + offset,
2691 size,
2692 PCI_DMA_TODEVICE);
2693 buffer_info->time_stamp = jiffies;
2694
2695 len -= size;
2696 offset += size;
2697 count++;
96838a40 2698 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2699 }
2700
96838a40 2701 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2702 struct skb_frag_struct *frag;
2703
2704 frag = &skb_shinfo(skb)->frags[f];
2705 len = frag->size;
2706 offset = frag->page_offset;
2707
96838a40 2708 while (len) {
1da177e4
LT		 2709 buffer_info = &tx_ring->buffer_info[i];
2710 size = min(len, max_per_txd);
2711#ifdef NETIF_F_TSO
2712 /* Workaround for premature desc write-backs
2713 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2714 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2715 size -= 4;
2716#endif
2717 /* Workaround for potential 82544 hang in PCI-X.
2718 * Avoid terminating buffers within evenly-aligned
2719 * dwords. */
96838a40 2720 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2721 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2722 size > 4))
2723 size -= 4;
2724
2725 buffer_info->length = size;
2726 buffer_info->dma =
2727 pci_map_page(adapter->pdev,
2728 frag->page,
2729 offset,
2730 size,
2731 PCI_DMA_TODEVICE);
2732 buffer_info->time_stamp = jiffies;
2733
2734 len -= size;
2735 offset += size;
2736 count++;
96838a40 2737 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2738 }
2739 }
2740
2741 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2742 tx_ring->buffer_info[i].skb = skb;
2743 tx_ring->buffer_info[first].next_to_watch = i;
2744
2745 return count;
2746}
2747
e619d523 2748static void
581d708e
MC		 2749e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2750 int tx_flags, int count)
1da177e4 2751{
1da177e4
LT		 2752 struct e1000_tx_desc *tx_desc = NULL;
2753 struct e1000_buffer *buffer_info;
2754 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2755 unsigned int i;
2756
96838a40 2757 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2758 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2759 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2760 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2761
96838a40 2762 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2763 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2764 }
2765
96838a40 2766 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2767 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2768 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2769 }
2770
96838a40 2771 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2772 txd_lower |= E1000_TXD_CMD_VLE;
2773 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2774 }
2775
2776 i = tx_ring->next_to_use;
2777
96838a40 2778 while (count--) {
1da177e4
LT		 2779 buffer_info = &tx_ring->buffer_info[i];
2780 tx_desc = E1000_TX_DESC(*tx_ring, i);
2781 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2782 tx_desc->lower.data =
2783 cpu_to_le32(txd_lower | buffer_info->length);
2784 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2785 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2786 }
2787
2788 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2789
2790 /* Force memory writes to complete before letting h/w
2791 * know there are new descriptors to fetch. (Only
2792 * applicable for weak-ordered memory model archs,
2793 * such as IA-64). */
2794 wmb();
2795
2796 tx_ring->next_to_use = i;
581d708e 2797 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2798}
2799
2800/**
2801 * 82547 workaround to avoid controller hang in half-duplex environment.
2802 * The workaround is to avoid queuing a large packet that would span
2803 * the internal Tx FIFO ring boundary by notifying the stack to resend
2804 * the packet at a later time. This gives the Tx FIFO an opportunity to
2805 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2806 * to the beginning of the Tx FIFO.
2807 **/
2808
2809#define E1000_FIFO_HDR 0x10
2810#define E1000_82547_PAD_LEN 0x3E0
2811
e619d523 2812static int
1da177e4
LT		 2813e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2814{
2815 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2816 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2817
2818 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2819
96838a40 2820 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2821 goto no_fifo_stall_required;
2822
96838a40 2823 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2824 return 1;
2825
96838a40 2826 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2827 atomic_set(&adapter->tx_fifo_stall, 1);
2828 return 1;
2829 }
2830
2831no_fifo_stall_required:
2832 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2833 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2834 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2835 return 0;
2836}
2837
2d7edb92 2838#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2839static int
2d7edb92
MC		 2840e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2841{
2842 struct e1000_hw *hw = &adapter->hw;
2843 uint16_t length, offset;
96838a40
JB		 2844 if (vlan_tx_tag_present(skb)) {
2845 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2846 ( adapter->hw.mng_cookie.status &
2847 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2848 return 0;
2849 }
20a44028 2850 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2851 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2852 if ((htons(ETH_P_IP) == eth->h_proto)) {
2853 const struct iphdr *ip =
2d7edb92 2854 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2855 if (IPPROTO_UDP == ip->protocol) {
2856 struct udphdr *udp =
2857 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2858 (ip->ihl << 2));
96838a40 2859 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2860 offset = (uint8_t *)udp + 8 - skb->data;
2861 length = skb->len - offset;
2862
2863 return e1000_mng_write_dhcp_info(hw,
96838a40 2864 (uint8_t *)udp + 8,
2d7edb92
MC		 2865 length);
2866 }
2867 }
2868 }
2869 }
2870 return 0;
2871}
2872
1da177e4
LT		 2873#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2874static int
2875e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2876{
60490fe0 2877 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2878 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2879 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2880 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2881 unsigned int tx_flags = 0;
2882 unsigned int len = skb->len;
2883 unsigned long flags;
2884 unsigned int nr_frags = 0;
2885 unsigned int mss = 0;
2886 int count = 0;
76c224bc 2887 int tso;
1da177e4
LT		 2888 unsigned int f;
2889 len -= skb->data_len;
2890
581d708e 2891 tx_ring = adapter->tx_ring;
24025e4e 2892
581d708e 2893 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2894 dev_kfree_skb_any(skb);
2895 return NETDEV_TX_OK;
2896 }
2897
2898#ifdef NETIF_F_TSO
7967168c 2899 mss = skb_shinfo(skb)->gso_size;
76c224bc 2900 /* The controller does a simple calculation to
1da177e4
LT		 2901 * make sure there is enough room in the FIFO before
2902 * initiating the DMA for each buffer. The calc is:
2903 * 4 = ceil(buffer len/mss). To make sure we don't
2904 * overrun the FIFO, adjust the max buffer len if mss
2905 * drops. */
96838a40 2906 if (mss) {
9a3056da 2907 uint8_t hdr_len;
1da177e4
LT		 2908 max_per_txd = min(mss << 2, max_per_txd);
2909 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2910
9f687888 2911 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2912 * points to just header, pull a few bytes of payload from
2913 * frags into skb->data */
2914 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2915 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2916 switch (adapter->hw.mac_type) {
2917 unsigned int pull_size;
2918 case e1000_82571:
2919 case e1000_82572:
2920 case e1000_82573:
cd94dd0b 2921 case e1000_ich8lan:
9f687888
JK		 2922 pull_size = min((unsigned int)4, skb->data_len);
2923 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 2924 DPRINTK(DRV, ERR,
9f687888
JK		 2925 "__pskb_pull_tail failed.\n");
2926 dev_kfree_skb_any(skb);
749dfc70 2927 return NETDEV_TX_OK;
9f687888
JK		 2928 }
2929 len = skb->len - skb->data_len;
2930 break;
2931 default:
2932 /* do nothing */
2933 break;
d74bbd3b 2934 }
9a3056da 2935 }
1da177e4
LT		 2936 }
2937
9a3056da 2938 /* reserve a descriptor for the offload context */
96838a40 2939 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2940 count++;
2648345f 2941 count++;
1da177e4 2942#else
96838a40 2943 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2944 count++;
2945#endif
fd803241
JK		 2946
2947#ifdef NETIF_F_TSO
2948 /* Controller Erratum workaround */
89114afd 2949 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241
JK		 2950 count++;
2951#endif
2952
1da177e4
LT		 2953 count += TXD_USE_COUNT(len, max_txd_pwr);
2954
96838a40 2955 if (adapter->pcix_82544)
1da177e4
LT		 2956 count++;
2957
96838a40 2958 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2959 * in PCI-X mode, so add one more descriptor to the count
2960 */
96838a40 2961 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2962 (len > 2015)))
2963 count++;
2964
1da177e4 2965 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2966 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2967 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2968 max_txd_pwr);
96838a40 2969 if (adapter->pcix_82544)
1da177e4
LT		 2970 count += nr_frags;
2971
0f15a8fa
JK		 2972
2973 if (adapter->hw.tx_pkt_filtering &&
2974 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2975 e1000_transfer_dhcp_info(adapter, skb);
2976
581d708e
MC		 2977 local_irq_save(flags);
2978 if (!spin_trylock(&tx_ring->tx_lock)) {
2979 /* Collision - tell upper layer to requeue */
2980 local_irq_restore(flags);
2981 return NETDEV_TX_LOCKED;
2982 }
1da177e4
LT		 2983
2984 /* need: count + 2 desc gap to keep tail from touching
2985 * head, otherwise try next time */
581d708e 2986 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2987 netif_stop_queue(netdev);
581d708e 2988 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2989 return NETDEV_TX_BUSY;
2990 }
2991
96838a40
JB		 2992 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2993 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2994 netif_stop_queue(netdev);
2995 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2996 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2997 return NETDEV_TX_BUSY;
2998 }
2999 }
3000
96838a40 3001 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3002 tx_flags |= E1000_TX_FLAGS_VLAN;
3003 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3004 }
3005
581d708e 3006 first = tx_ring->next_to_use;
96838a40 3007
581d708e 3008 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3009 if (tso < 0) {
3010 dev_kfree_skb_any(skb);
581d708e 3011 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3012 return NETDEV_TX_OK;
3013 }
3014
fd803241
JK		 3015 if (likely(tso)) {
3016 tx_ring->last_tx_tso = 1;
1da177e4 3017 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3018 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3019 tx_flags |= E1000_TX_FLAGS_CSUM;
3020
2d7edb92 3021 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3022 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3023 * no longer assume, we must. */
60828236 3024 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3025 tx_flags |= E1000_TX_FLAGS_IPV4;
3026
581d708e
MC		 3027 e1000_tx_queue(adapter, tx_ring, tx_flags,
3028 e1000_tx_map(adapter, tx_ring, skb, first,
3029 max_per_txd, nr_frags, mss));
1da177e4
LT		 3030
3031 netdev->trans_start = jiffies;
3032
3033 /* Make sure there is space in the ring for the next send. */
581d708e 3034 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 3035 netif_stop_queue(netdev);
3036
581d708e 3037 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3038 return NETDEV_TX_OK;
3039}
3040
3041/**
3042 * e1000_tx_timeout - Respond to a Tx Hang
3043 * @netdev: network interface device structure
3044 **/
3045
3046static void
3047e1000_tx_timeout(struct net_device *netdev)
3048{
60490fe0 3049 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3050
3051 /* Do the reset outside of interrupt context */
87041639
JK		 3052 adapter->tx_timeout_count++;
3053 schedule_work(&adapter->reset_task);
1da177e4
LT		 3054}
3055
3056static void
87041639 3057e1000_reset_task(struct net_device *netdev)
1da177e4 3058{
60490fe0 3059 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3060
2db10a08 3061 e1000_reinit_locked(adapter);
1da177e4
LT		 3062}
3063
3064/**
3065 * e1000_get_stats - Get System Network Statistics
3066 * @netdev: network interface device structure
3067 *
3068 * Returns the address of the device statistics structure.
3069 * The statistics are actually updated from the timer callback.
3070 **/
3071
3072static struct net_device_stats *
3073e1000_get_stats(struct net_device *netdev)
3074{
60490fe0 3075 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3076
6b7660cd 3077 /* only return the current stats */
1da177e4
LT		 3078 return &adapter->net_stats;
3079}
3080
3081/**
3082 * e1000_change_mtu - Change the Maximum Transfer Unit
3083 * @netdev: network interface device structure
3084 * @new_mtu: new value for maximum frame size
3085 *
3086 * Returns 0 on success, negative on failure
3087 **/
3088
3089static int
3090e1000_change_mtu(struct net_device *netdev, int new_mtu)
3091{
60490fe0 3092 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3093 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3094 uint16_t eeprom_data = 0;
1da177e4 3095
96838a40
JB		 3096 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3097 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3098 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3099 return -EINVAL;
2d7edb92 3100 }
1da177e4 3101
997f5cbd
JK		 3102 /* Adapter-specific max frame size limits. */
3103 switch (adapter->hw.mac_type) {
9e2feace 3104 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3105 case e1000_ich8lan:
997f5cbd
JK		 3106 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3107 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3108 return -EINVAL;
2d7edb92 3109 }
997f5cbd 3110 break;
85b22eb6
JK		 3111 case e1000_82573:
3112 /* only enable jumbo frames if ASPM is disabled completely
3113 * this means both bits must be zero in 0x1A bits 3:2 */
3114 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3115 &eeprom_data);
3116 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
3117 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3118 DPRINTK(PROBE, ERR,
3119 "Jumbo Frames not supported.\n");
3120 return -EINVAL;
3121 }
3122 break;
3123 }
3124 /* fall through to get support */
997f5cbd
JK		 3125 case e1000_82571:
3126 case e1000_82572:
87041639 3127 case e1000_80003es2lan:
997f5cbd
JK		 3128#define MAX_STD_JUMBO_FRAME_SIZE 9234
3129 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3130 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3131 return -EINVAL;
3132 }
3133 break;
3134 default:
3135 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3136 break;
1da177e4
LT		 3137 }
3138
87f5032e 3139 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3140 * means we reserve 2 more, this pushes us to allocate from the next
3141 * larger slab size
3142 * i.e. RXBUFFER_2048 --> size-4096 slab */
3143
3144 if (max_frame <= E1000_RXBUFFER_256)
3145 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3146 else if (max_frame <= E1000_RXBUFFER_512)
3147 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3148 else if (max_frame <= E1000_RXBUFFER_1024)
3149 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3150 else if (max_frame <= E1000_RXBUFFER_2048)
3151 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3152 else if (max_frame <= E1000_RXBUFFER_4096)
3153 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3154 else if (max_frame <= E1000_RXBUFFER_8192)
3155 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3156 else if (max_frame <= E1000_RXBUFFER_16384)
3157 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3158
3159 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3160 if (!adapter->hw.tbi_compatibility_on &&
3161 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3162 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3163 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3164
2d7edb92
MC		 3165 netdev->mtu = new_mtu;
3166
2db10a08
AK		 3167 if (netif_running(netdev))
3168 e1000_reinit_locked(adapter);
1da177e4 3169
1da177e4
LT		 3170 adapter->hw.max_frame_size = max_frame;
3171
3172 return 0;
3173}
3174
3175/**
3176 * e1000_update_stats - Update the board statistics counters
3177 * @adapter: board private structure
3178 **/
3179
3180void
3181e1000_update_stats(struct e1000_adapter *adapter)
3182{
3183 struct e1000_hw *hw = &adapter->hw;
282f33c9 3184 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3185 unsigned long flags;
3186 uint16_t phy_tmp;
3187
3188#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3189
282f33c9
LV		 3190 /*
3191 * Prevent stats update while adapter is being reset, or if the pci
3192 * connection is down.
3193 */
9026729b 3194 if (adapter->link_speed == 0)
282f33c9
LV		 3195 return;
3196 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
9026729b
AK		 3197 return;
3198
1da177e4
LT		 3199 spin_lock_irqsave(&adapter->stats_lock, flags);
3200
3201 /* these counters are modified from e1000_adjust_tbi_stats,
3202 * called from the interrupt context, so they must only
3203 * be written while holding adapter->stats_lock
3204 */
3205
3206 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3207 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3208 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3209 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3210 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3211 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3212 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3213
3214 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3215 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3216 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3217 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3218 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3219 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3220 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3221 }
1da177e4
LT		 3222
3223 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3224 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3225 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3226 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3227 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3228 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3229 adapter->stats.dc += E1000_READ_REG(hw, DC);
3230 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3231 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3232 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3233 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3234 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3235 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3236 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3237 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3238 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3239 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3240 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3241 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3242 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3243 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3244 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3245 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3246 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3247 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3248 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3249
3250 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3251 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3252 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3253 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3254 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3255 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3256 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3257 }
3258
1da177e4
LT		 3259 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3260 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3261
3262 /* used for adaptive IFS */
3263
3264 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3265 adapter->stats.tpt += hw->tx_packet_delta;
3266 hw->collision_delta = E1000_READ_REG(hw, COLC);
3267 adapter->stats.colc += hw->collision_delta;
3268
96838a40 3269 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3270 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3271 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3272 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3273 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3274 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3275 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3276 }
96838a40 3277 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3278 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3279 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3280
3281 if (adapter->hw.mac_type != e1000_ich8lan) {
2d7edb92
MC		 3282 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3283 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3284 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3285 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3286 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3287 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3288 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3289 }
2d7edb92 3290 }
1da177e4
LT		 3291
3292 /* Fill out the OS statistics structure */
3293
3294 adapter->net_stats.rx_packets = adapter->stats.gprc;
3295 adapter->net_stats.tx_packets = adapter->stats.gptc;
3296 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3297 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3298 adapter->net_stats.multicast = adapter->stats.mprc;
3299 adapter->net_stats.collisions = adapter->stats.colc;
3300
3301 /* Rx Errors */
3302
87041639
JK		 3303 /* RLEC on some newer hardware can be incorrect so build
3304 * our own version based on RUC and ROC */
1da177e4
LT		 3305 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3306 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3307 adapter->stats.ruc + adapter->stats.roc +
3308 adapter->stats.cexterr;
87041639
JK		 3309 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3310 adapter->stats.roc;
1da177e4
LT		 3311 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3312 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3313 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3314
3315 /* Tx Errors */
3316
3317 adapter->net_stats.tx_errors = adapter->stats.ecol +
3318 adapter->stats.latecol;
3319 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3320 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3321 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3322
3323 /* Tx Dropped needs to be maintained elsewhere */
3324
3325 /* Phy Stats */
3326
96838a40
JB		 3327 if (hw->media_type == e1000_media_type_copper) {
3328 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3329 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3330 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3331 adapter->phy_stats.idle_errors += phy_tmp;
3332 }
3333
96838a40 3334 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3335 (hw->phy_type == e1000_phy_m88) &&
3336 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3337 adapter->phy_stats.receive_errors += phy_tmp;
3338 }
3339
3340 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3341}
3342
3343/**
3344 * e1000_intr - Interrupt Handler
3345 * @irq: interrupt number
3346 * @data: pointer to a network interface device structure
3347 * @pt_regs: CPU registers structure
3348 **/
3349
3350static irqreturn_t
3351e1000_intr(int irq, void *data, struct pt_regs *regs)
3352{
3353 struct net_device *netdev = data;
60490fe0 3354 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3355 struct e1000_hw *hw = &adapter->hw;
87041639 3356 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3357#ifndef CONFIG_E1000_NAPI
581d708e 3358 int i;
1e613fd9
JK		 3359#else
3360 /* Interrupt Auto-Mask...upon reading ICR,
3361 * interrupts are masked. No need for the
3362 * IMC write, but it does mean we should
3363 * account for it ASAP. */
3364 if (likely(hw->mac_type >= e1000_82571))
3365 atomic_inc(&adapter->irq_sem);
be2b28ed 3366#endif
1da177e4 3367
1e613fd9
JK		 3368 if (unlikely(!icr)) {
3369#ifdef CONFIG_E1000_NAPI
3370 if (hw->mac_type >= e1000_82571)
3371 e1000_irq_enable(adapter);
3372#endif
1da177e4 3373 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3374 }
1da177e4 3375
96838a40 3376 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3377 hw->get_link_status = 1;
87041639
JK		 3378 /* 80003ES2LAN workaround--
3379 * For packet buffer work-around on link down event;
3380 * disable receives here in the ISR and
3381 * reset adapter in watchdog
3382 */
3383 if (netif_carrier_ok(netdev) &&
3384 (adapter->hw.mac_type == e1000_80003es2lan)) {
3385 /* disable receives */
3386 rctl = E1000_READ_REG(hw, RCTL);
3387 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3388 }
1da177e4
LT		 3389 mod_timer(&adapter->watchdog_timer, jiffies);
3390 }
3391
3392#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3393 if (unlikely(hw->mac_type < e1000_82571)) {
3394 atomic_inc(&adapter->irq_sem);
3395 E1000_WRITE_REG(hw, IMC, ~0);
3396 E1000_WRITE_FLUSH(hw);
3397 }
d3d9e484
AK		 3398 if (likely(netif_rx_schedule_prep(netdev)))
3399 __netif_rx_schedule(netdev);
581d708e
MC		 3400 else
3401 e1000_irq_enable(adapter);
c1605eb3 3402#else
1da177e4 3403 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3404 * Due to Hub Link bus being occupied, an interrupt
3405 * de-assertion message is not able to be sent.
3406 * When an interrupt assertion message is generated later,
3407 * two messages are re-ordered and sent out.
3408 * That causes APIC to think 82547 is in de-assertion
3409 * state, while 82547 is in assertion state, resulting
3410 * in dead lock. Writing IMC forces 82547 into
3411 * de-assertion state.
3412 */
3413 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3414 atomic_inc(&adapter->irq_sem);
2648345f 3415 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3416 }
3417
96838a40
JB		 3418 for (i = 0; i < E1000_MAX_INTR; i++)
3419 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3420 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3421 break;
3422
96838a40 3423 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3424 e1000_irq_enable(adapter);
581d708e 3425
c1605eb3 3426#endif
1da177e4
LT		 3427
3428 return IRQ_HANDLED;
3429}
3430
3431#ifdef CONFIG_E1000_NAPI
3432/**
3433 * e1000_clean - NAPI Rx polling callback
3434 * @adapter: board private structure
3435 **/
3436
3437static int
581d708e 3438e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3439{
581d708e
MC		 3440 struct e1000_adapter *adapter;
3441 int work_to_do = min(*budget, poll_dev->quota);
d3d9e484 3442 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3443
3444 /* Must NOT use netdev_priv macro here. */
3445 adapter = poll_dev->priv;
3446
3447 /* Keep link state information with original netdev */
d3d9e484 3448 if (!netif_carrier_ok(poll_dev))
581d708e 3449 goto quit_polling;
2648345f 3450
d3d9e484
AK		 3451 /* e1000_clean is called per-cpu. This lock protects
3452 * tx_ring[0] from being cleaned by multiple cpus
3453 * simultaneously. A failure obtaining the lock means
3454 * tx_ring[0] is currently being cleaned anyway. */
3455 if (spin_trylock(&adapter->tx_queue_lock)) {
3456 tx_cleaned = e1000_clean_tx_irq(adapter,
3457 &adapter->tx_ring[0]);
3458 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3459 }
3460
d3d9e484 3461 adapter->clean_rx(adapter, &adapter->rx_ring[0],
581d708e 3462 &work_done, work_to_do);
1da177e4
LT		 3463
3464 *budget -= work_done;
581d708e 3465 poll_dev->quota -= work_done;
96838a40 3466
2b02893e 3467 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3468 if ((!tx_cleaned && (work_done == 0)) ||
d3d9e484 3469 !netif_running(poll_dev)) {
581d708e
MC		 3470quit_polling:
3471 netif_rx_complete(poll_dev);
1da177e4
LT		 3472 e1000_irq_enable(adapter);
3473 return 0;
3474 }
3475
3476 return 1;
3477}
3478
3479#endif
3480/**
3481 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3482 * @adapter: board private structure
3483 **/
3484
3485static boolean_t
581d708e
MC		 3486e1000_clean_tx_irq(struct e1000_adapter *adapter,
3487 struct e1000_tx_ring *tx_ring)
1da177e4 3488{
1da177e4
LT		 3489 struct net_device *netdev = adapter->netdev;
3490 struct e1000_tx_desc *tx_desc, *eop_desc;
3491 struct e1000_buffer *buffer_info;
3492 unsigned int i, eop;
2a1af5d7
JK		 3493#ifdef CONFIG_E1000_NAPI
3494 unsigned int count = 0;
3495#endif
1da177e4
LT		 3496 boolean_t cleaned = FALSE;
3497
3498 i = tx_ring->next_to_clean;
3499 eop = tx_ring->buffer_info[i].next_to_watch;
3500 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3501
581d708e 3502 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3503 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3504 tx_desc = E1000_TX_DESC(*tx_ring, i);
3505 buffer_info = &tx_ring->buffer_info[i];
3506 cleaned = (i == eop);
3507
fd803241 3508 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3509 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3510
96838a40 3511 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3512 }
581d708e 3513
7bfa4816 3514
1da177e4
LT		 3515 eop = tx_ring->buffer_info[i].next_to_watch;
3516 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3517#ifdef CONFIG_E1000_NAPI
3518#define E1000_TX_WEIGHT 64
3519 /* weight of a sort for tx, to avoid endless transmit cleanup */
3520 if (count++ == E1000_TX_WEIGHT) break;
3521#endif
1da177e4
LT		 3522 }
3523
3524 tx_ring->next_to_clean = i;
3525
77b2aad5 3526#define TX_WAKE_THRESHOLD 32
96838a40 3527 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
77b2aad5
AK		 3528 netif_carrier_ok(netdev))) {
3529 spin_lock(&tx_ring->tx_lock);
3530 if (netif_queue_stopped(netdev) &&
3531 (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
3532 netif_wake_queue(netdev);
3533 spin_unlock(&tx_ring->tx_lock);
3534 }
2648345f 3535
581d708e 3536 if (adapter->detect_tx_hung) {
2648345f 3537 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3538 * check with the clearing of time_stamp and movement of i */
3539 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3540 if (tx_ring->buffer_info[eop].dma &&
3541 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3542 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3543 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3544 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3545
3546 /* detected Tx unit hang */
c6963ef5 3547 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3548 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3549 " TDH <%x>\n"
3550 " TDT <%x>\n"
3551 " next_to_use <%x>\n"
3552 " next_to_clean <%x>\n"
3553 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3554 " time_stamp <%lx>\n"
3555 " next_to_watch <%x>\n"
3556 " jiffies <%lx>\n"
3557 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3558 (unsigned long)((tx_ring - adapter->tx_ring) /
3559 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3560 readl(adapter->hw.hw_addr + tx_ring->tdh),
3561 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3562 tx_ring->next_to_use,
392137fa
JK		 3563 tx_ring->next_to_clean,
3564 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3565 eop,
3566 jiffies,
3567 eop_desc->upper.fields.status);
1da177e4 3568 netif_stop_queue(netdev);
70b8f1e1 3569 }
1da177e4 3570 }
1da177e4
LT		 3571 return cleaned;
3572}
3573
3574/**
3575 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3576 * @adapter: board private structure
3577 * @status_err: receive descriptor status and error fields
3578 * @csum: receive descriptor csum field
3579 * @sk_buff: socket buffer with received data
1da177e4
LT		 3580 **/
3581
e619d523 3582static void
1da177e4 3583e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3584 uint32_t status_err, uint32_t csum,
3585 struct sk_buff *skb)
1da177e4 3586{
2d7edb92
MC		 3587 uint16_t status = (uint16_t)status_err;
3588 uint8_t errors = (uint8_t)(status_err >> 24);
3589 skb->ip_summed = CHECKSUM_NONE;
3590
1da177e4 3591 /* 82543 or newer only */
96838a40 3592 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3593 /* Ignore Checksum bit is set */
96838a40 3594 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3595 /* TCP/UDP checksum error bit is set */
96838a40 3596 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3597 /* let the stack verify checksum errors */
1da177e4 3598 adapter->hw_csum_err++;
2d7edb92
MC		 3599 return;
3600 }
3601 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3602 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3603 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3604 return;
1da177e4 3605 } else {
96838a40 3606 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3607 return;
3608 }
3609 /* It must be a TCP or UDP packet with a valid checksum */
3610 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3611 /* TCP checksum is good */
3612 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3613 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3614 /* IP fragment with UDP payload */
3615 /* Hardware complements the payload checksum, so we undo it
3616 * and then put the value in host order for further stack use.
3617 */
3618 csum = ntohl(csum ^ 0xFFFF);
3619 skb->csum = csum;
3620 skb->ip_summed = CHECKSUM_HW;
1da177e4 3621 }
2d7edb92 3622 adapter->hw_csum_good++;
1da177e4
LT		 3623}
3624
3625/**
2d7edb92 3626 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3627 * @adapter: board private structure
3628 **/
3629
3630static boolean_t
3631#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3632e1000_clean_rx_irq(struct e1000_adapter *adapter,
3633 struct e1000_rx_ring *rx_ring,
3634 int *work_done, int work_to_do)
1da177e4 3635#else
581d708e
MC		 3636e1000_clean_rx_irq(struct e1000_adapter *adapter,
3637 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3638#endif
3639{
1da177e4
LT		 3640 struct net_device *netdev = adapter->netdev;
3641 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3642 struct e1000_rx_desc *rx_desc, *next_rxd;
3643 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3644 unsigned long flags;
3645 uint32_t length;
3646 uint8_t last_byte;
3647 unsigned int i;
72d64a43 3648 int cleaned_count = 0;
a1415ee6 3649 boolean_t cleaned = FALSE;
1da177e4
LT		 3650
3651 i = rx_ring->next_to_clean;
3652 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3653 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3654
b92ff8ee 3655 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 3656 struct sk_buff *skb;
a292ca6e 3657 u8 status;
1da177e4 3658#ifdef CONFIG_E1000_NAPI
96838a40 3659 if (*work_done >= work_to_do)
1da177e4
LT		 3660 break;
3661 (*work_done)++;
3662#endif
a292ca6e 3663 status = rx_desc->status;
b92ff8ee 3664 skb = buffer_info->skb;
86c3d59f
JB		 3665 buffer_info->skb = NULL;
3666
30320be8
JK		 3667 prefetch(skb->data - NET_IP_ALIGN);
3668
86c3d59f
JB		 3669 if (++i == rx_ring->count) i = 0;
3670 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3671 prefetch(next_rxd);
3672
86c3d59f 3673 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3674
72d64a43
JK		 3675 cleaned = TRUE;
3676 cleaned_count++;
a292ca6e
JK		 3677 pci_unmap_single(pdev,
3678 buffer_info->dma,
3679 buffer_info->length,
1da177e4
LT		 3680 PCI_DMA_FROMDEVICE);
3681
1da177e4
LT		 3682 length = le16_to_cpu(rx_desc->length);
3683
f235a2ab
AK		 3684 /* adjust length to remove Ethernet CRC */
3685 length -= 4;
3686
a1415ee6
JK		 3687 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3688 /* All receives must fit into a single buffer */
3689 E1000_DBG("%s: Receive packet consumed multiple"
3690 " buffers\n", netdev->name);
864c4e45 3691 /* recycle */
8fc897b0 3692 buffer_info->skb = skb;
1da177e4
LT		 3693 goto next_desc;
3694 }
3695
96838a40 3696 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3697 last_byte = *(skb->data + length - 1);
b92ff8ee 3698 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3699 rx_desc->errors, length, last_byte)) {
3700 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3701 e1000_tbi_adjust_stats(&adapter->hw,
3702 &adapter->stats,
1da177e4
LT		 3703 length, skb->data);
3704 spin_unlock_irqrestore(&adapter->stats_lock,
3705 flags);
3706 length--;
3707 } else {
9e2feace
AK		 3708 /* recycle */
3709 buffer_info->skb = skb;
1da177e4
LT		 3710 goto next_desc;
3711 }
1cb5821f 3712 }
1da177e4 3713
a292ca6e
JK		 3714 /* code added for copybreak, this should improve
3715 * performance for small packets with large amounts
3716 * of reassembly being done in the stack */
3717#define E1000_CB_LENGTH 256
a1415ee6 3718 if (length < E1000_CB_LENGTH) {
a292ca6e 3719 struct sk_buff *new_skb =
87f5032e 3720 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 3721 if (new_skb) {
3722 skb_reserve(new_skb, NET_IP_ALIGN);
3723 new_skb->dev = netdev;
3724 memcpy(new_skb->data - NET_IP_ALIGN,
3725 skb->data - NET_IP_ALIGN,
3726 length + NET_IP_ALIGN);
3727 /* save the skb in buffer_info as good */
3728 buffer_info->skb = skb;
3729 skb = new_skb;
3730 skb_put(skb, length);
3731 }
a1415ee6
JK		 3732 } else
3733 skb_put(skb, length);
a292ca6e
JK		 3734
3735 /* end copybreak code */
1da177e4
LT		 3736
3737 /* Receive Checksum Offload */
a292ca6e
JK		 3738 e1000_rx_checksum(adapter,
3739 (uint32_t)(status) |
2d7edb92 3740 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3741 le16_to_cpu(rx_desc->csum), skb);
96838a40 3742
1da177e4
LT		 3743 skb->protocol = eth_type_trans(skb, netdev);
3744#ifdef CONFIG_E1000_NAPI
96838a40 3745 if (unlikely(adapter->vlgrp &&
a292ca6e 3746 (status & E1000_RXD_STAT_VP))) {
1da177e4 3747 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3748 le16_to_cpu(rx_desc->special) &
3749 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3750 } else {
3751 netif_receive_skb(skb);
3752 }
3753#else /* CONFIG_E1000_NAPI */
96838a40 3754 if (unlikely(adapter->vlgrp &&
b92ff8ee 3755 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3756 vlan_hwaccel_rx(skb, adapter->vlgrp,
3757 le16_to_cpu(rx_desc->special) &
3758 E1000_RXD_SPC_VLAN_MASK);
3759 } else {
3760 netif_rx(skb);
3761 }
3762#endif /* CONFIG_E1000_NAPI */
3763 netdev->last_rx = jiffies;
3764
3765next_desc:
3766 rx_desc->status = 0;
1da177e4 3767
72d64a43
JK		 3768 /* return some buffers to hardware, one at a time is too slow */
3769 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3770 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3771 cleaned_count = 0;
3772 }
3773
30320be8 3774 /* use prefetched values */
86c3d59f
JB		 3775 rx_desc = next_rxd;
3776 buffer_info = next_buffer;
1da177e4 3777 }
1da177e4 3778 rx_ring->next_to_clean = i;
72d64a43
JK		 3779
3780 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3781 if (cleaned_count)
3782 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3783
3784 return cleaned;
3785}
3786
3787/**
3788 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3789 * @adapter: board private structure
3790 **/
3791
3792static boolean_t
3793#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3794e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3795 struct e1000_rx_ring *rx_ring,
3796 int *work_done, int work_to_do)
2d7edb92 3797#else
581d708e
MC		 3798e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3799 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3800#endif
3801{
86c3d59f 3802 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3803 struct net_device *netdev = adapter->netdev;
3804 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3805 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3806 struct e1000_ps_page *ps_page;
3807 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 3808 struct sk_buff *skb;
2d7edb92
MC		 3809 unsigned int i, j;
3810 uint32_t length, staterr;
72d64a43 3811 int cleaned_count = 0;
2d7edb92
MC		 3812 boolean_t cleaned = FALSE;
3813
3814 i = rx_ring->next_to_clean;
3815 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3816 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3817 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3818
96838a40 3819 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3820 ps_page = &rx_ring->ps_page[i];
3821 ps_page_dma = &rx_ring->ps_page_dma[i];
3822#ifdef CONFIG_E1000_NAPI
96838a40 3823 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3824 break;
3825 (*work_done)++;
3826#endif
86c3d59f
JB		 3827 skb = buffer_info->skb;
3828
30320be8
JK		 3829 /* in the packet split case this is header only */
3830 prefetch(skb->data - NET_IP_ALIGN);
3831
86c3d59f
JB		 3832 if (++i == rx_ring->count) i = 0;
3833 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3834 prefetch(next_rxd);
3835
86c3d59f 3836 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3837
2d7edb92 3838 cleaned = TRUE;
72d64a43 3839 cleaned_count++;
2d7edb92
MC		 3840 pci_unmap_single(pdev, buffer_info->dma,
3841 buffer_info->length,
3842 PCI_DMA_FROMDEVICE);
3843
96838a40 3844 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3845 E1000_DBG("%s: Packet Split buffers didn't pick up"
3846 " the full packet\n", netdev->name);
3847 dev_kfree_skb_irq(skb);
3848 goto next_desc;
3849 }
1da177e4 3850
96838a40 3851 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3852 dev_kfree_skb_irq(skb);
3853 goto next_desc;
3854 }
3855
3856 length = le16_to_cpu(rx_desc->wb.middle.length0);
3857
96838a40 3858 if (unlikely(!length)) {
2d7edb92
MC		 3859 E1000_DBG("%s: Last part of the packet spanning"
3860 " multiple descriptors\n", netdev->name);
3861 dev_kfree_skb_irq(skb);
3862 goto next_desc;
3863 }
3864
3865 /* Good Receive */
3866 skb_put(skb, length);
3867
dc7c6add
JK		 3868 {
3869 /* this looks ugly, but it seems compiler issues make it
3870 more efficient than reusing j */
3871 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3872
3873 /* page alloc/put takes too long and effects small packet
3874 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 3875 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 3876 u8 *vaddr;
76c224bc 3877 /* there is no documentation about how to call
dc7c6add
JK		 3878 * kmap_atomic, so we can't hold the mapping
3879 * very long */
3880 pci_dma_sync_single_for_cpu(pdev,
3881 ps_page_dma->ps_page_dma[0],
3882 PAGE_SIZE,
3883 PCI_DMA_FROMDEVICE);
3884 vaddr = kmap_atomic(ps_page->ps_page[0],
3885 KM_SKB_DATA_SOFTIRQ);
3886 memcpy(skb->tail, vaddr, l1);
3887 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3888 pci_dma_sync_single_for_device(pdev,
3889 ps_page_dma->ps_page_dma[0],
3890 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 3891 /* remove the CRC */
3892 l1 -= 4;
dc7c6add 3893 skb_put(skb, l1);
dc7c6add
JK		 3894 goto copydone;
3895 } /* if */
3896 }
3897
96838a40 3898 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3899 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3900 break;
2d7edb92
MC		 3901 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3902 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3903 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3904 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3905 length);
2d7edb92 3906 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3907 skb->len += length;
3908 skb->data_len += length;
5d51b80f 3909 skb->truesize += length;
2d7edb92
MC		 3910 }
3911
f235a2ab
AK		 3912 /* strip the ethernet crc, problem is we're using pages now so
3913 * this whole operation can get a little cpu intensive */
3914 pskb_trim(skb, skb->len - 4);
3915
dc7c6add 3916copydone:
2d7edb92 3917 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3918 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3919 skb->protocol = eth_type_trans(skb, netdev);
3920
96838a40 3921 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3922 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3923 adapter->rx_hdr_split++;
2d7edb92 3924#ifdef CONFIG_E1000_NAPI
96838a40 3925 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3926 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3927 le16_to_cpu(rx_desc->wb.middle.vlan) &
3928 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3929 } else {
3930 netif_receive_skb(skb);
3931 }
3932#else /* CONFIG_E1000_NAPI */
96838a40 3933 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3934 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3935 le16_to_cpu(rx_desc->wb.middle.vlan) &
3936 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3937 } else {
3938 netif_rx(skb);
3939 }
3940#endif /* CONFIG_E1000_NAPI */
3941 netdev->last_rx = jiffies;
3942
3943next_desc:
c3d7a3a4 3944 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3945 buffer_info->skb = NULL;
2d7edb92 3946
72d64a43
JK		 3947 /* return some buffers to hardware, one at a time is too slow */
3948 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3949 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3950 cleaned_count = 0;
3951 }
3952
30320be8 3953 /* use prefetched values */
86c3d59f
JB		 3954 rx_desc = next_rxd;
3955 buffer_info = next_buffer;
3956
683a38f3 3957 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3958 }
3959 rx_ring->next_to_clean = i;
72d64a43
JK		 3960
3961 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3962 if (cleaned_count)
3963 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3964
3965 return cleaned;
3966}
3967
3968/**
2d7edb92 3969 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3970 * @adapter: address of board private structure
3971 **/
3972
3973static void
581d708e 3974e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3975 struct e1000_rx_ring *rx_ring,
a292ca6e 3976 int cleaned_count)
1da177e4 3977{
1da177e4
LT		 3978 struct net_device *netdev = adapter->netdev;
3979 struct pci_dev *pdev = adapter->pdev;
3980 struct e1000_rx_desc *rx_desc;
3981 struct e1000_buffer *buffer_info;
3982 struct sk_buff *skb;
2648345f
MC		 3983 unsigned int i;
3984 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3985
3986 i = rx_ring->next_to_use;
3987 buffer_info = &rx_ring->buffer_info[i];
3988
a292ca6e
JK		 3989 while (cleaned_count--) {
3990 if (!(skb = buffer_info->skb))
87f5032e 3991 skb = netdev_alloc_skb(netdev, bufsz);
a292ca6e
JK		 3992 else {
3993 skb_trim(skb, 0);
3994 goto map_skb;
3995 }
3996
96838a40 3997 if (unlikely(!skb)) {
1da177e4 3998 /* Better luck next round */
72d64a43 3999 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4000 break;
4001 }
4002
2648345f 4003 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4004 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4005 struct sk_buff *oldskb = skb;
2648345f
MC		 4006 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4007 "at %p\n", bufsz, skb->data);
4008 /* Try again, without freeing the previous */
87f5032e 4009 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4010 /* Failed allocation, critical failure */
1da177e4
LT		 4011 if (!skb) {
4012 dev_kfree_skb(oldskb);
4013 break;
4014 }
2648345f 4015
1da177e4
LT		 4016 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4017 /* give up */
4018 dev_kfree_skb(skb);
4019 dev_kfree_skb(oldskb);
4020 break; /* while !buffer_info->skb */
4021 } else {
2648345f 4022 /* Use new allocation */
1da177e4
LT		 4023 dev_kfree_skb(oldskb);
4024 }
4025 }
1da177e4
LT		 4026 /* Make buffer alignment 2 beyond a 16 byte boundary
4027 * this will result in a 16 byte aligned IP header after
4028 * the 14 byte MAC header is removed
4029 */
4030 skb_reserve(skb, NET_IP_ALIGN);
4031
4032 skb->dev = netdev;
4033
4034 buffer_info->skb = skb;
4035 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4036map_skb:
1da177e4
LT		 4037 buffer_info->dma = pci_map_single(pdev,
4038 skb->data,
4039 adapter->rx_buffer_len,
4040 PCI_DMA_FROMDEVICE);
4041
2648345f
MC		 4042 /* Fix for errata 23, can't cross 64kB boundary */
4043 if (!e1000_check_64k_bound(adapter,
4044 (void *)(unsigned long)buffer_info->dma,
4045 adapter->rx_buffer_len)) {
4046 DPRINTK(RX_ERR, ERR,
4047 "dma align check failed: %u bytes at %p\n",
4048 adapter->rx_buffer_len,
4049 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4050 dev_kfree_skb(skb);
4051 buffer_info->skb = NULL;
4052
2648345f 4053 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4054 adapter->rx_buffer_len,
4055 PCI_DMA_FROMDEVICE);
4056
4057 break; /* while !buffer_info->skb */
4058 }
1da177e4
LT		 4059 rx_desc = E1000_RX_DESC(*rx_ring, i);
4060 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4061
96838a40
JB		 4062 if (unlikely(++i == rx_ring->count))
4063 i = 0;
1da177e4
LT		 4064 buffer_info = &rx_ring->buffer_info[i];
4065 }
4066
b92ff8ee
JB		 4067 if (likely(rx_ring->next_to_use != i)) {
4068 rx_ring->next_to_use = i;
4069 if (unlikely(i-- == 0))
4070 i = (rx_ring->count - 1);
4071
4072 /* Force memory writes to complete before letting h/w
4073 * know there are new descriptors to fetch. (Only
4074 * applicable for weak-ordered memory model archs,
4075 * such as IA-64). */
4076 wmb();
4077 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4078 }
1da177e4
LT		 4079}
4080
2d7edb92
MC		 4081/**
4082 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4083 * @adapter: address of board private structure
4084 **/
4085
4086static void
581d708e 4087e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4088 struct e1000_rx_ring *rx_ring,
4089 int cleaned_count)
2d7edb92 4090{
2d7edb92
MC		 4091 struct net_device *netdev = adapter->netdev;
4092 struct pci_dev *pdev = adapter->pdev;
4093 union e1000_rx_desc_packet_split *rx_desc;
4094 struct e1000_buffer *buffer_info;
4095 struct e1000_ps_page *ps_page;
4096 struct e1000_ps_page_dma *ps_page_dma;
4097 struct sk_buff *skb;
4098 unsigned int i, j;
4099
4100 i = rx_ring->next_to_use;
4101 buffer_info = &rx_ring->buffer_info[i];
4102 ps_page = &rx_ring->ps_page[i];
4103 ps_page_dma = &rx_ring->ps_page_dma[i];
4104
72d64a43 4105 while (cleaned_count--) {
2d7edb92
MC		 4106 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4107
96838a40 4108 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4109 if (j < adapter->rx_ps_pages) {
4110 if (likely(!ps_page->ps_page[j])) {
4111 ps_page->ps_page[j] =
4112 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4113 if (unlikely(!ps_page->ps_page[j])) {
4114 adapter->alloc_rx_buff_failed++;
e4c811c9 4115 goto no_buffers;
b92ff8ee 4116 }
e4c811c9
MC		 4117 ps_page_dma->ps_page_dma[j] =
4118 pci_map_page(pdev,
4119 ps_page->ps_page[j],
4120 0, PAGE_SIZE,
4121 PCI_DMA_FROMDEVICE);
4122 }
4123 /* Refresh the desc even if buffer_addrs didn't
96838a40 4124 * change because each write-back erases
e4c811c9
MC		 4125 * this info.
4126 */
4127 rx_desc->read.buffer_addr[j+1] =
4128 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4129 } else
4130 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4131 }
4132
87f5032e
DM		 4133 skb = netdev_alloc_skb(netdev,
4134 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4135
b92ff8ee
JB		 4136 if (unlikely(!skb)) {
4137 adapter->alloc_rx_buff_failed++;
2d7edb92 4138 break;
b92ff8ee 4139 }
2d7edb92
MC		 4140
4141 /* Make buffer alignment 2 beyond a 16 byte boundary
4142 * this will result in a 16 byte aligned IP header after
4143 * the 14 byte MAC header is removed
4144 */
4145 skb_reserve(skb, NET_IP_ALIGN);
4146
4147 skb->dev = netdev;
4148
4149 buffer_info->skb = skb;
4150 buffer_info->length = adapter->rx_ps_bsize0;
4151 buffer_info->dma = pci_map_single(pdev, skb->data,
4152 adapter->rx_ps_bsize0,
4153 PCI_DMA_FROMDEVICE);
4154
4155 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4156
96838a40 4157 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4158 buffer_info = &rx_ring->buffer_info[i];
4159 ps_page = &rx_ring->ps_page[i];
4160 ps_page_dma = &rx_ring->ps_page_dma[i];
4161 }
4162
4163no_buffers:
b92ff8ee
JB		 4164 if (likely(rx_ring->next_to_use != i)) {
4165 rx_ring->next_to_use = i;
4166 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4167
4168 /* Force memory writes to complete before letting h/w
4169 * know there are new descriptors to fetch. (Only
4170 * applicable for weak-ordered memory model archs,
4171 * such as IA-64). */
4172 wmb();
4173 /* Hardware increments by 16 bytes, but packet split
4174 * descriptors are 32 bytes...so we increment tail
4175 * twice as much.
4176 */
4177 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4178 }
2d7edb92
MC		 4179}
4180
1da177e4
LT		 4181/**
4182 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4183 * @adapter:
4184 **/
4185
4186static void
4187e1000_smartspeed(struct e1000_adapter *adapter)
4188{
4189 uint16_t phy_status;
4190 uint16_t phy_ctrl;
4191
96838a40 4192 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4193 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4194 return;
4195
96838a40 4196 if (adapter->smartspeed == 0) {
1da177e4
LT		 4197 /* If Master/Slave config fault is asserted twice,
4198 * we assume back-to-back */
4199 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4200 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4201 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4202 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4203 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4204 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4205 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4206 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4207 phy_ctrl);
4208 adapter->smartspeed++;
96838a40 4209 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4210 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4211 &phy_ctrl)) {
4212 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4213 MII_CR_RESTART_AUTO_NEG);
4214 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4215 phy_ctrl);
4216 }
4217 }
4218 return;
96838a40 4219 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4220 /* If still no link, perhaps using 2/3 pair cable */
4221 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4222 phy_ctrl |= CR_1000T_MS_ENABLE;
4223 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4224 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4225 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4226 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4227 MII_CR_RESTART_AUTO_NEG);
4228 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4229 }
4230 }
4231 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4232 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4233 adapter->smartspeed = 0;
4234}
4235
4236/**
4237 * e1000_ioctl -
4238 * @netdev:
4239 * @ifreq:
4240 * @cmd:
4241 **/
4242
4243static int
4244e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4245{
4246 switch (cmd) {
4247 case SIOCGMIIPHY:
4248 case SIOCGMIIREG:
4249 case SIOCSMIIREG:
4250 return e1000_mii_ioctl(netdev, ifr, cmd);
4251 default:
4252 return -EOPNOTSUPP;
4253 }
4254}
4255
4256/**
4257 * e1000_mii_ioctl -
4258 * @netdev:
4259 * @ifreq:
4260 * @cmd:
4261 **/
4262
4263static int
4264e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4265{
60490fe0 4266 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4267 struct mii_ioctl_data *data = if_mii(ifr);
4268 int retval;
4269 uint16_t mii_reg;
4270 uint16_t spddplx;
97876fc6 4271 unsigned long flags;
1da177e4 4272
96838a40 4273 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4274 return -EOPNOTSUPP;
4275
4276 switch (cmd) {
4277 case SIOCGMIIPHY:
4278 data->phy_id = adapter->hw.phy_addr;
4279 break;
4280 case SIOCGMIIREG:
96838a40 4281 if (!capable(CAP_NET_ADMIN))
1da177e4 4282 return -EPERM;
97876fc6 4283 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4284 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4285 &data->val_out)) {
4286 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4287 return -EIO;
97876fc6
MC		 4288 }
4289 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4290 break;
4291 case SIOCSMIIREG:
96838a40 4292 if (!capable(CAP_NET_ADMIN))
1da177e4 4293 return -EPERM;
96838a40 4294 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4295 return -EFAULT;
4296 mii_reg = data->val_in;
97876fc6 4297 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4298 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4299 mii_reg)) {
4300 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4301 return -EIO;
97876fc6 4302 }
dc86d32a 4303 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4304 switch (data->reg_num) {
4305 case PHY_CTRL:
96838a40 4306 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4307 break;
96838a40 4308 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4309 adapter->hw.autoneg = 1;
4310 adapter->hw.autoneg_advertised = 0x2F;
4311 } else {
4312 if (mii_reg & 0x40)
4313 spddplx = SPEED_1000;
4314 else if (mii_reg & 0x2000)
4315 spddplx = SPEED_100;
4316 else
4317 spddplx = SPEED_10;
4318 spddplx += (mii_reg & 0x100)
cb764326
JK		 4319 ? DUPLEX_FULL :
4320 DUPLEX_HALF;
1da177e4
LT		 4321 retval = e1000_set_spd_dplx(adapter,
4322 spddplx);
96838a40 4323 if (retval) {
97876fc6 4324 spin_unlock_irqrestore(
96838a40 4325 &adapter->stats_lock,
97876fc6 4326 flags);
1da177e4 4327 return retval;
97876fc6 4328 }
1da177e4 4329 }
2db10a08
AK		 4330 if (netif_running(adapter->netdev))
4331 e1000_reinit_locked(adapter);
4332 else
1da177e4
LT		 4333 e1000_reset(adapter);
4334 break;
4335 case M88E1000_PHY_SPEC_CTRL:
4336 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4337 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4338 spin_unlock_irqrestore(
4339 &adapter->stats_lock, flags);
1da177e4 4340 return -EIO;
97876fc6 4341 }
1da177e4
LT		 4342 break;
4343 }
4344 } else {
4345 switch (data->reg_num) {
4346 case PHY_CTRL:
96838a40 4347 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4348 break;
2db10a08
AK		 4349 if (netif_running(adapter->netdev))
4350 e1000_reinit_locked(adapter);
4351 else
1da177e4
LT		 4352 e1000_reset(adapter);
4353 break;
4354 }
4355 }
97876fc6 4356 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4357 break;
4358 default:
4359 return -EOPNOTSUPP;
4360 }
4361 return E1000_SUCCESS;
4362}
4363
4364void
4365e1000_pci_set_mwi(struct e1000_hw *hw)
4366{
4367 struct e1000_adapter *adapter = hw->back;
2648345f 4368 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4369
96838a40 4370 if (ret_val)
2648345f 4371 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4372}
4373
4374void
4375e1000_pci_clear_mwi(struct e1000_hw *hw)
4376{
4377 struct e1000_adapter *adapter = hw->back;
4378
4379 pci_clear_mwi(adapter->pdev);
4380}
4381
4382void
4383e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4384{
4385 struct e1000_adapter *adapter = hw->back;
4386
4387 pci_read_config_word(adapter->pdev, reg, value);
4388}
4389
4390void
4391e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4392{
4393 struct e1000_adapter *adapter = hw->back;
4394
4395 pci_write_config_word(adapter->pdev, reg, *value);
4396}
4397
e4c780b1 4398#if 0
1da177e4
LT		 4399uint32_t
4400e1000_io_read(struct e1000_hw *hw, unsigned long port)
4401{
4402 return inl(port);
4403}
e4c780b1 4404#endif /* 0 */
1da177e4
LT		 4405
4406void
4407e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4408{
4409 outl(value, port);
4410}
4411
4412static void
4413e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4414{
60490fe0 4415 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4416 uint32_t ctrl, rctl;
4417
4418 e1000_irq_disable(adapter);
4419 adapter->vlgrp = grp;
4420
96838a40 4421 if (grp) {
1da177e4
LT		 4422 /* enable VLAN tag insert/strip */
4423 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4424 ctrl |= E1000_CTRL_VME;
4425 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4426
cd94dd0b 4427 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4428 /* enable VLAN receive filtering */
4429 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4430 rctl |= E1000_RCTL_VFE;
4431 rctl &= ~E1000_RCTL_CFIEN;
4432 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4433 e1000_update_mng_vlan(adapter);
cd94dd0b 4434 }
1da177e4
LT		 4435 } else {
4436 /* disable VLAN tag insert/strip */
4437 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4438 ctrl &= ~E1000_CTRL_VME;
4439 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4440
cd94dd0b 4441 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4442 /* disable VLAN filtering */
4443 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4444 rctl &= ~E1000_RCTL_VFE;
4445 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4446 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4447 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4448 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4449 }
cd94dd0b 4450 }
1da177e4
LT		 4451 }
4452
4453 e1000_irq_enable(adapter);
4454}
4455
4456static void
4457e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4458{
60490fe0 4459 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4460 uint32_t vfta, index;
96838a40
JB		 4461
4462 if ((adapter->hw.mng_cookie.status &
4463 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4464 (vid == adapter->mng_vlan_id))
2d7edb92 4465 return;
1da177e4
LT		 4466 /* add VID to filter table */
4467 index = (vid >> 5) & 0x7F;
4468 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4469 vfta |= (1 << (vid & 0x1F));
4470 e1000_write_vfta(&adapter->hw, index, vfta);
4471}
4472
4473static void
4474e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4475{
60490fe0 4476 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4477 uint32_t vfta, index;
4478
4479 e1000_irq_disable(adapter);
4480
96838a40 4481 if (adapter->vlgrp)
1da177e4
LT		 4482 adapter->vlgrp->vlan_devices[vid] = NULL;
4483
4484 e1000_irq_enable(adapter);
4485
96838a40
JB		 4486 if ((adapter->hw.mng_cookie.status &
4487 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4488 (vid == adapter->mng_vlan_id)) {
4489 /* release control to f/w */
4490 e1000_release_hw_control(adapter);
2d7edb92 4491 return;
ff147013
JK		 4492 }
4493
1da177e4
LT		 4494 /* remove VID from filter table */
4495 index = (vid >> 5) & 0x7F;
4496 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4497 vfta &= ~(1 << (vid & 0x1F));
4498 e1000_write_vfta(&adapter->hw, index, vfta);
4499}
4500
4501static void
4502e1000_restore_vlan(struct e1000_adapter *adapter)
4503{
4504 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4505
96838a40 4506 if (adapter->vlgrp) {
1da177e4 4507 uint16_t vid;
96838a40
JB		 4508 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4509 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4510 continue;
4511 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4512 }
4513 }
4514}
4515
4516int
4517e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4518{
4519 adapter->hw.autoneg = 0;
4520
6921368f 4521 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4522 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4523 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4524 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4525 return -EINVAL;
4526 }
4527
96838a40 4528 switch (spddplx) {
1da177e4
LT		 4529 case SPEED_10 + DUPLEX_HALF:
4530 adapter->hw.forced_speed_duplex = e1000_10_half;
4531 break;
4532 case SPEED_10 + DUPLEX_FULL:
4533 adapter->hw.forced_speed_duplex = e1000_10_full;
4534 break;
4535 case SPEED_100 + DUPLEX_HALF:
4536 adapter->hw.forced_speed_duplex = e1000_100_half;
4537 break;
4538 case SPEED_100 + DUPLEX_FULL:
4539 adapter->hw.forced_speed_duplex = e1000_100_full;
4540 break;
4541 case SPEED_1000 + DUPLEX_FULL:
4542 adapter->hw.autoneg = 1;
4543 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4544 break;
4545 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4546 default:
2648345f 4547 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4548 return -EINVAL;
4549 }
4550 return 0;
4551}
4552
b6a1d5f8 4553#ifdef CONFIG_PM
0f15a8fa
JK		 4554/* Save/restore 16 or 64 dwords of PCI config space depending on which
4555 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4556 */
4557#define PCIE_CONFIG_SPACE_LEN 256
4558#define PCI_CONFIG_SPACE_LEN 64
4559static int
4560e1000_pci_save_state(struct e1000_adapter *adapter)
4561{
4562 struct pci_dev *dev = adapter->pdev;
4563 int size;
4564 int i;
0f15a8fa 4565
2f82665f
JB		 4566 if (adapter->hw.mac_type >= e1000_82571)
4567 size = PCIE_CONFIG_SPACE_LEN;
4568 else
4569 size = PCI_CONFIG_SPACE_LEN;
4570
4571 WARN_ON(adapter->config_space != NULL);
4572
4573 adapter->config_space = kmalloc(size, GFP_KERNEL);
4574 if (!adapter->config_space) {
4575 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4576 return -ENOMEM;
4577 }
4578 for (i = 0; i < (size / 4); i++)
4579 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4580 return 0;
4581}
4582
4583static void
4584e1000_pci_restore_state(struct e1000_adapter *adapter)
4585{
4586 struct pci_dev *dev = adapter->pdev;
4587 int size;
4588 int i;
0f15a8fa 4589
2f82665f
JB		 4590 if (adapter->config_space == NULL)
4591 return;
0f15a8fa 4592
2f82665f
JB		 4593 if (adapter->hw.mac_type >= e1000_82571)
4594 size = PCIE_CONFIG_SPACE_LEN;
4595 else
4596 size = PCI_CONFIG_SPACE_LEN;
4597 for (i = 0; i < (size / 4); i++)
4598 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4599 kfree(adapter->config_space);
4600 adapter->config_space = NULL;
4601 return;
4602}
4603#endif /* CONFIG_PM */
4604
1da177e4 4605static int
829ca9a3 4606e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4607{
4608 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4609 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4610 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4611 uint32_t wufc = adapter->wol;
6fdfef16 4612#ifdef CONFIG_PM
240b1710 4613 int retval = 0;
6fdfef16 4614#endif
1da177e4
LT		 4615
4616 netif_device_detach(netdev);
4617
2db10a08
AK		 4618 if (netif_running(netdev)) {
4619 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 4620 e1000_down(adapter);
2db10a08 4621 }
1da177e4 4622
2f82665f 4623#ifdef CONFIG_PM
0f15a8fa
JK		 4624 /* Implement our own version of pci_save_state(pdev) because pci-
4625 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4626 retval = e1000_pci_save_state(adapter);
4627 if (retval)
4628 return retval;
4629#endif
4630
1da177e4 4631 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4632 if (status & E1000_STATUS_LU)
1da177e4
LT		 4633 wufc &= ~E1000_WUFC_LNKC;
4634
96838a40 4635 if (wufc) {
1da177e4
LT		 4636 e1000_setup_rctl(adapter);
4637 e1000_set_multi(netdev);
4638
4639 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4640 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4641 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4642 rctl |= E1000_RCTL_MPE;
4643 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4644 }
4645
96838a40 4646 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4647 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4648 /* advertise wake from D3Cold */
4649 #define E1000_CTRL_ADVD3WUC 0x00100000
4650 /* phy power management enable */
4651 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4652 ctrl |= E1000_CTRL_ADVD3WUC |
4653 E1000_CTRL_EN_PHY_PWR_MGMT;
4654 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4655 }
4656
96838a40 4657 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4658 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4659 /* keep the laser running in D3 */
4660 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4661 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4662 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4663 }
4664
2d7edb92
MC		 4665 /* Allow time for pending master requests to run */
4666 e1000_disable_pciex_master(&adapter->hw);
4667
1da177e4
LT		 4668 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4669 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4670 pci_enable_wake(pdev, PCI_D3hot, 1);
4671 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4672 } else {
4673 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4674 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4675 pci_enable_wake(pdev, PCI_D3hot, 0);
4676 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4677 }
4678
cd94dd0b 4679 /* FIXME: this code is incorrect for PCI Express */
96838a40 4680 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4681 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4682 adapter->hw.media_type == e1000_media_type_copper) {
4683 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4684 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4685 manc |= E1000_MANC_ARP_EN;
4686 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4687 pci_enable_wake(pdev, PCI_D3hot, 1);
4688 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4689 }
4690 }
4691
cd94dd0b
AK		 4692 if (adapter->hw.phy_type == e1000_phy_igp_3)
4693 e1000_phy_powerdown_workaround(&adapter->hw);
4694
b55ccb35
JK		 4695 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4696 * would have already happened in close and is redundant. */
4697 e1000_release_hw_control(adapter);
2d7edb92 4698
1da177e4 4699 pci_disable_device(pdev);
240b1710 4700
d0e027db 4701 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4702
4703 return 0;
4704}
4705
2f82665f 4706#ifdef CONFIG_PM
1da177e4
LT		 4707static int
4708e1000_resume(struct pci_dev *pdev)
4709{
4710 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4711 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4712 uint32_t manc, ret_val;
1da177e4 4713
d0e027db 4714 pci_set_power_state(pdev, PCI_D0);
2f82665f 4715 e1000_pci_restore_state(adapter);
2b02893e 4716 ret_val = pci_enable_device(pdev);
a4cb847d 4717 pci_set_master(pdev);
1da177e4 4718
d0e027db
AK		 4719 pci_enable_wake(pdev, PCI_D3hot, 0);
4720 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4721
4722 e1000_reset(adapter);
4723 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4724
96838a40 4725 if (netif_running(netdev))
1da177e4
LT		 4726 e1000_up(adapter);
4727
4728 netif_device_attach(netdev);
4729
cd94dd0b 4730 /* FIXME: this code is incorrect for PCI Express */
96838a40 4731 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4732 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4733 adapter->hw.media_type == e1000_media_type_copper) {
4734 manc = E1000_READ_REG(&adapter->hw, MANC);
4735 manc &= ~(E1000_MANC_ARP_EN);
4736 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4737 }
4738
b55ccb35
JK		 4739 /* If the controller is 82573 and f/w is AMT, do not set
4740 * DRV_LOAD until the interface is up. For all other cases,
4741 * let the f/w know that the h/w is now under the control
4742 * of the driver. */
4743 if (adapter->hw.mac_type != e1000_82573 ||
4744 !e1000_check_mng_mode(&adapter->hw))
4745 e1000_get_hw_control(adapter);
2d7edb92 4746
1da177e4
LT		 4747 return 0;
4748}
4749#endif
c653e635
AK		 4750
4751static void e1000_shutdown(struct pci_dev *pdev)
4752{
4753 e1000_suspend(pdev, PMSG_SUSPEND);
4754}
4755
1da177e4
LT		 4756#ifdef CONFIG_NET_POLL_CONTROLLER
4757/*
4758 * Polling 'interrupt' - used by things like netconsole to send skbs
4759 * without having to re-enable interrupts. It's not called while
4760 * the interrupt routine is executing.
4761 */
4762static void
2648345f 4763e1000_netpoll(struct net_device *netdev)
1da177e4 4764{
60490fe0 4765 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 4766
1da177e4
LT		 4767 disable_irq(adapter->pdev->irq);
4768 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4769 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4770#ifndef CONFIG_E1000_NAPI
4771 adapter->clean_rx(adapter, adapter->rx_ring);
4772#endif
1da177e4
LT		 4773 enable_irq(adapter->pdev->irq);
4774}
4775#endif
4776
9026729b
AK		 4777/**
4778 * e1000_io_error_detected - called when PCI error is detected
4779 * @pdev: Pointer to PCI device
4780 * @state: The current pci conneection state
4781 *
4782 * This function is called after a PCI bus error affecting
4783 * this device has been detected.
4784 */
4785static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4786{
4787 struct net_device *netdev = pci_get_drvdata(pdev);
4788 struct e1000_adapter *adapter = netdev->priv;
4789
4790 netif_device_detach(netdev);
4791
4792 if (netif_running(netdev))
4793 e1000_down(adapter);
4794
4795 /* Request a slot slot reset. */
4796 return PCI_ERS_RESULT_NEED_RESET;
4797}
4798
4799/**
4800 * e1000_io_slot_reset - called after the pci bus has been reset.
4801 * @pdev: Pointer to PCI device
4802 *
4803 * Restart the card from scratch, as if from a cold-boot. Implementation
4804 * resembles the first-half of the e1000_resume routine.
4805 */
4806static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4807{
4808 struct net_device *netdev = pci_get_drvdata(pdev);
4809 struct e1000_adapter *adapter = netdev->priv;
4810
4811 if (pci_enable_device(pdev)) {
4812 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
4813 return PCI_ERS_RESULT_DISCONNECT;
4814 }
4815 pci_set_master(pdev);
4816
4817 pci_enable_wake(pdev, 3, 0);
4818 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4819
4820 /* Perform card reset only on one instance of the card */
4821 if (PCI_FUNC (pdev->devfn) != 0)
4822 return PCI_ERS_RESULT_RECOVERED;
4823
4824 e1000_reset(adapter);
4825 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4826
4827 return PCI_ERS_RESULT_RECOVERED;
4828}
4829
4830/**
4831 * e1000_io_resume - called when traffic can start flowing again.
4832 * @pdev: Pointer to PCI device
4833 *
4834 * This callback is called when the error recovery driver tells us that
4835 * its OK to resume normal operation. Implementation resembles the
4836 * second-half of the e1000_resume routine.
4837 */
4838static void e1000_io_resume(struct pci_dev *pdev)
4839{
4840 struct net_device *netdev = pci_get_drvdata(pdev);
4841 struct e1000_adapter *adapter = netdev->priv;
4842 uint32_t manc, swsm;
4843
4844 if (netif_running(netdev)) {
4845 if (e1000_up(adapter)) {
4846 printk("e1000: can't bring device back up after reset\n");
4847 return;
4848 }
4849 }
4850
4851 netif_device_attach(netdev);
4852
4853 if (adapter->hw.mac_type >= e1000_82540 &&
4854 adapter->hw.media_type == e1000_media_type_copper) {
4855 manc = E1000_READ_REG(&adapter->hw, MANC);
4856 manc &= ~(E1000_MANC_ARP_EN);
4857 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4858 }
4859
4860 switch (adapter->hw.mac_type) {
4861 case e1000_82573:
4862 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4863 E1000_WRITE_REG(&adapter->hw, SWSM,
4864 swsm | E1000_SWSM_DRV_LOAD);
4865 break;
4866 default:
4867 break;
4868 }
4869
4870 if (netif_running(netdev))
4871 mod_timer(&adapter->watchdog_timer, jiffies);
4872}
4873
1da177e4 4874/* e1000_main.c */
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