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e1000: implement more efficient tx queue locking
[mirror_ubuntu-bionic-kernel.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
0f15a8fa
JK		 32 * 7.0.33 3-Feb-2006
33 * o Added another fix for the pass false carrier bit
34 * 7.0.32 24-Jan-2006
35 * o Need to rebuild with noew version number for the pass false carrier
36 * fix in e1000_hw.c
37 * 7.0.30 18-Jan-2006
38 * o fixup for tso workaround to disable it for pci-x
39 * o fix mem leak on 82542
40 * o fixes for 10 Mb/s connections and incorrect stats
41 * 7.0.28 01/06/2006
42 * o hardware workaround to only set "speed mode" bit for 1G link.
43 * 7.0.26 12/23/2005
44 * o wake on lan support modified for device ID 10B5
45 * o fix dhcp + vlan issue not making it to the iAMT firmware
46 * 7.0.24 12/9/2005
47 * o New hardware support for the Gigabit NIC embedded in the south bridge
48 * o Fixes to the recycling logic (skb->tail) from IBM LTC
73629bbc
JB		 49 * 6.3.9 12/16/2005
50 * o incorporate fix for recycled skbs from IBM LTC
51 * 6.3.7 11/18/2005
52 * o Honor eeprom setting for enabling/disabling Wake On Lan
53 * 6.3.5 11/17/2005
54 * o Fix memory leak in rx ring handling for PCI Express adapters
55 * 6.3.4 11/8/05
56 * o Patch from Jesper Juhl to remove redundant NULL checks for kfree
57 * 6.3.2 9/20/05
58 * o Render logic that sets/resets DRV_LOAD as inline functions to
59 * avoid code replication. If f/w is AMT then set DRV_LOAD only when
60 * network interface is open.
61 * o Handle DRV_LOAD set/reset in cases where AMT uses VLANs.
62 * o Adjust PBA partioning for Jumbo frames using MTU size and not
63 * rx_buffer_len
64 * 6.3.1 9/19/05
65 * o Use adapter->tx_timeout_factor in Tx Hung Detect logic
0f15a8fa 66 * (e1000_clean_tx_irq)
73629bbc 67 * o Support for 8086:10B5 device (Quad Port)
1da177e4
LT		 68 */
69
70char e1000_driver_name[] = "e1000";
3ad2cc67 71static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 72#ifndef CONFIG_E1000_NAPI
73#define DRIVERNAPI
74#else
75#define DRIVERNAPI "-NAPI"
76#endif
c1605eb3 77#define DRV_VERSION "7.0.33-k2"DRIVERNAPI
1da177e4 78char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 79static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 80
81/* e1000_pci_tbl - PCI Device ID Table
82 *
83 * Last entry must be all 0s
84 *
85 * Macro expands to...
86 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
87 */
88static struct pci_device_id e1000_pci_tbl[] = {
89 INTEL_E1000_ETHERNET_DEVICE(0x1000),
90 INTEL_E1000_ETHERNET_DEVICE(0x1001),
91 INTEL_E1000_ETHERNET_DEVICE(0x1004),
92 INTEL_E1000_ETHERNET_DEVICE(0x1008),
93 INTEL_E1000_ETHERNET_DEVICE(0x1009),
94 INTEL_E1000_ETHERNET_DEVICE(0x100C),
95 INTEL_E1000_ETHERNET_DEVICE(0x100D),
96 INTEL_E1000_ETHERNET_DEVICE(0x100E),
97 INTEL_E1000_ETHERNET_DEVICE(0x100F),
98 INTEL_E1000_ETHERNET_DEVICE(0x1010),
99 INTEL_E1000_ETHERNET_DEVICE(0x1011),
100 INTEL_E1000_ETHERNET_DEVICE(0x1012),
101 INTEL_E1000_ETHERNET_DEVICE(0x1013),
102 INTEL_E1000_ETHERNET_DEVICE(0x1014),
103 INTEL_E1000_ETHERNET_DEVICE(0x1015),
104 INTEL_E1000_ETHERNET_DEVICE(0x1016),
105 INTEL_E1000_ETHERNET_DEVICE(0x1017),
106 INTEL_E1000_ETHERNET_DEVICE(0x1018),
107 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 108 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 109 INTEL_E1000_ETHERNET_DEVICE(0x101D),
110 INTEL_E1000_ETHERNET_DEVICE(0x101E),
111 INTEL_E1000_ETHERNET_DEVICE(0x1026),
112 INTEL_E1000_ETHERNET_DEVICE(0x1027),
113 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 114 INTEL_E1000_ETHERNET_DEVICE(0x105E),
115 INTEL_E1000_ETHERNET_DEVICE(0x105F),
116 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 117 INTEL_E1000_ETHERNET_DEVICE(0x1075),
118 INTEL_E1000_ETHERNET_DEVICE(0x1076),
119 INTEL_E1000_ETHERNET_DEVICE(0x1077),
120 INTEL_E1000_ETHERNET_DEVICE(0x1078),
121 INTEL_E1000_ETHERNET_DEVICE(0x1079),
122 INTEL_E1000_ETHERNET_DEVICE(0x107A),
123 INTEL_E1000_ETHERNET_DEVICE(0x107B),
124 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 125 INTEL_E1000_ETHERNET_DEVICE(0x107D),
126 INTEL_E1000_ETHERNET_DEVICE(0x107E),
127 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 128 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 129 INTEL_E1000_ETHERNET_DEVICE(0x108B),
130 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 131 INTEL_E1000_ETHERNET_DEVICE(0x1096),
132 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 133 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 134 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 135 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 136 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
1da177e4
LT		 137 /* required last entry */
138 {0,}
139};
140
141MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
142
3ad2cc67 143static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 144 struct e1000_tx_ring *txdr);
3ad2cc67 145static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 146 struct e1000_rx_ring *rxdr);
3ad2cc67 147static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 148 struct e1000_tx_ring *tx_ring);
3ad2cc67 149static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 150 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 151
152/* Local Function Prototypes */
153
154static int e1000_init_module(void);
155static void e1000_exit_module(void);
156static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
157static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 158static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 159static int e1000_sw_init(struct e1000_adapter *adapter);
160static int e1000_open(struct net_device *netdev);
161static int e1000_close(struct net_device *netdev);
162static void e1000_configure_tx(struct e1000_adapter *adapter);
163static void e1000_configure_rx(struct e1000_adapter *adapter);
164static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 165static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
166static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
167static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
168 struct e1000_tx_ring *tx_ring);
169static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
170 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 171static void e1000_set_multi(struct net_device *netdev);
172static void e1000_update_phy_info(unsigned long data);
173static void e1000_watchdog(unsigned long data);
174static void e1000_watchdog_task(struct e1000_adapter *adapter);
175static void e1000_82547_tx_fifo_stall(unsigned long data);
176static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
177static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
178static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
179static int e1000_set_mac(struct net_device *netdev, void *p);
180static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 181static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
182 struct e1000_tx_ring *tx_ring);
1da177e4 183#ifdef CONFIG_E1000_NAPI
581d708e 184static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 185static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 186 struct e1000_rx_ring *rx_ring,
1da177e4 187 int *work_done, int work_to_do);
2d7edb92 188static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 189 struct e1000_rx_ring *rx_ring,
2d7edb92 190 int *work_done, int work_to_do);
1da177e4 191#else
581d708e
MC		 192static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
193 struct e1000_rx_ring *rx_ring);
194static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
195 struct e1000_rx_ring *rx_ring);
1da177e4 196#endif
581d708e 197static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 198 struct e1000_rx_ring *rx_ring,
199 int cleaned_count);
581d708e 200static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 201 struct e1000_rx_ring *rx_ring,
202 int cleaned_count);
1da177e4
LT		 203static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
204static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
205 int cmd);
1da177e4
LT		 206static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
207static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
208static void e1000_tx_timeout(struct net_device *dev);
87041639 209static void e1000_reset_task(struct net_device *dev);
1da177e4 210static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 211static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
212 struct sk_buff *skb);
1da177e4
LT		 213
214static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
215static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
216static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
217static void e1000_restore_vlan(struct e1000_adapter *adapter);
218
1da177e4 219#ifdef CONFIG_PM
977e74b5 220static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 221static int e1000_resume(struct pci_dev *pdev);
222#endif
223
224#ifdef CONFIG_NET_POLL_CONTROLLER
225/* for netdump / net console */
226static void e1000_netpoll (struct net_device *netdev);
227#endif
228
24025e4e 229
1da177e4
LT		 230static struct pci_driver e1000_driver = {
231 .name = e1000_driver_name,
232 .id_table = e1000_pci_tbl,
233 .probe = e1000_probe,
234 .remove = __devexit_p(e1000_remove),
235 /* Power Managment Hooks */
236#ifdef CONFIG_PM
237 .suspend = e1000_suspend,
238 .resume = e1000_resume
239#endif
240};
241
242MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
243MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
244MODULE_LICENSE("GPL");
245MODULE_VERSION(DRV_VERSION);
246
247static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
248module_param(debug, int, 0);
249MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
250
251/**
252 * e1000_init_module - Driver Registration Routine
253 *
254 * e1000_init_module is the first routine called when the driver is
255 * loaded. All it does is register with the PCI subsystem.
256 **/
257
258static int __init
259e1000_init_module(void)
260{
261 int ret;
262 printk(KERN_INFO "%s - version %s\n",
263 e1000_driver_string, e1000_driver_version);
264
265 printk(KERN_INFO "%s\n", e1000_copyright);
266
267 ret = pci_module_init(&e1000_driver);
8b378def 268
1da177e4
LT		 269 return ret;
270}
271
272module_init(e1000_init_module);
273
274/**
275 * e1000_exit_module - Driver Exit Cleanup Routine
276 *
277 * e1000_exit_module is called just before the driver is removed
278 * from memory.
279 **/
280
281static void __exit
282e1000_exit_module(void)
283{
1da177e4
LT		 284 pci_unregister_driver(&e1000_driver);
285}
286
287module_exit(e1000_exit_module);
288
289/**
290 * e1000_irq_disable - Mask off interrupt generation on the NIC
291 * @adapter: board private structure
292 **/
293
e619d523 294static void
1da177e4
LT		 295e1000_irq_disable(struct e1000_adapter *adapter)
296{
297 atomic_inc(&adapter->irq_sem);
298 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
299 E1000_WRITE_FLUSH(&adapter->hw);
300 synchronize_irq(adapter->pdev->irq);
301}
302
303/**
304 * e1000_irq_enable - Enable default interrupt generation settings
305 * @adapter: board private structure
306 **/
307
e619d523 308static void
1da177e4
LT		 309e1000_irq_enable(struct e1000_adapter *adapter)
310{
96838a40 311 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 312 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
313 E1000_WRITE_FLUSH(&adapter->hw);
314 }
315}
3ad2cc67
AB		 316
317static void
2d7edb92
MC		 318e1000_update_mng_vlan(struct e1000_adapter *adapter)
319{
320 struct net_device *netdev = adapter->netdev;
321 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
322 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 323 if (adapter->vlgrp) {
324 if (!adapter->vlgrp->vlan_devices[vid]) {
325 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 326 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
327 e1000_vlan_rx_add_vid(netdev, vid);
328 adapter->mng_vlan_id = vid;
329 } else
330 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 331
332 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
333 (vid != old_vid) &&
2d7edb92
MC		 334 !adapter->vlgrp->vlan_devices[old_vid])
335 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 336 } else
337 adapter->mng_vlan_id = vid;
2d7edb92
MC		 338 }
339}
b55ccb35
JK		 340
341/**
342 * e1000_release_hw_control - release control of the h/w to f/w
343 * @adapter: address of board private structure
344 *
345 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
346 * For ASF and Pass Through versions of f/w this means that the
347 * driver is no longer loaded. For AMT version (only with 82573) i
348 * of the f/w this means that the netowrk i/f is closed.
349 *
350 **/
351
e619d523 352static void
b55ccb35
JK		 353e1000_release_hw_control(struct e1000_adapter *adapter)
354{
355 uint32_t ctrl_ext;
356 uint32_t swsm;
357
358 /* Let firmware taken over control of h/w */
359 switch (adapter->hw.mac_type) {
360 case e1000_82571:
361 case e1000_82572:
4cc15f54 362 case e1000_80003es2lan:
b55ccb35
JK		 363 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
364 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
365 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
366 break;
367 case e1000_82573:
368 swsm = E1000_READ_REG(&adapter->hw, SWSM);
369 E1000_WRITE_REG(&adapter->hw, SWSM,
370 swsm & ~E1000_SWSM_DRV_LOAD);
371 default:
372 break;
373 }
374}
375
376/**
377 * e1000_get_hw_control - get control of the h/w from f/w
378 * @adapter: address of board private structure
379 *
380 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
381 * For ASF and Pass Through versions of f/w this means that
382 * the driver is loaded. For AMT version (only with 82573)
383 * of the f/w this means that the netowrk i/f is open.
384 *
385 **/
386
e619d523 387static void
b55ccb35
JK		 388e1000_get_hw_control(struct e1000_adapter *adapter)
389{
390 uint32_t ctrl_ext;
391 uint32_t swsm;
392 /* Let firmware know the driver has taken over */
393 switch (adapter->hw.mac_type) {
394 case e1000_82571:
395 case e1000_82572:
4cc15f54 396 case e1000_80003es2lan:
b55ccb35
JK		 397 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
398 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
399 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
400 break;
401 case e1000_82573:
402 swsm = E1000_READ_REG(&adapter->hw, SWSM);
403 E1000_WRITE_REG(&adapter->hw, SWSM,
404 swsm | E1000_SWSM_DRV_LOAD);
405 break;
406 default:
407 break;
408 }
409}
410
1da177e4
LT		 411int
412e1000_up(struct e1000_adapter *adapter)
413{
414 struct net_device *netdev = adapter->netdev;
581d708e 415 int i, err;
1da177e4
LT		 416
417 /* hardware has been reset, we need to reload some things */
418
419 /* Reset the PHY if it was previously powered down */
96838a40 420 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 421 uint16_t mii_reg;
422 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
96838a40 423 if (mii_reg & MII_CR_POWER_DOWN)
4cc15f54 424 e1000_phy_hw_reset(&adapter->hw);
1da177e4
LT		 425 }
426
427 e1000_set_multi(netdev);
428
429 e1000_restore_vlan(adapter);
430
431 e1000_configure_tx(adapter);
432 e1000_setup_rctl(adapter);
433 e1000_configure_rx(adapter);
72d64a43
JK		 434 /* call E1000_DESC_UNUSED which always leaves
435 * at least 1 descriptor unused to make sure
436 * next_to_use != next_to_clean */
f56799ea 437 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 438 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 439 adapter->alloc_rx_buf(adapter, ring,
440 E1000_DESC_UNUSED(ring));
f56799ea 441 }
1da177e4 442
fa4f7ef3 443#ifdef CONFIG_PCI_MSI
96838a40 444 if (adapter->hw.mac_type > e1000_82547_rev_2) {
fa4f7ef3 445 adapter->have_msi = TRUE;
96838a40 446 if ((err = pci_enable_msi(adapter->pdev))) {
fa4f7ef3
MC		 447 DPRINTK(PROBE, ERR,
448 "Unable to allocate MSI interrupt Error: %d\n", err);
449 adapter->have_msi = FALSE;
450 }
451 }
452#endif
96838a40 453 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
1da177e4 454 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 455 netdev->name, netdev))) {
456 DPRINTK(PROBE, ERR,
457 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 458 return err;
2648345f 459 }
1da177e4 460
7bfa4816
JK		 461 adapter->tx_queue_len = netdev->tx_queue_len;
462
1da177e4 463 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 464
465#ifdef CONFIG_E1000_NAPI
466 netif_poll_enable(netdev);
467#endif
5de55624
MC		 468 e1000_irq_enable(adapter);
469
1da177e4
LT		 470 return 0;
471}
472
473void
474e1000_down(struct e1000_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
57128197
JK		 477 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
478 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 479
480 e1000_irq_disable(adapter);
c1605eb3 481
1da177e4 482 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3 483#ifdef CONFIG_PCI_MSI
96838a40 484 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
fa4f7ef3
MC		 485 adapter->have_msi == TRUE)
486 pci_disable_msi(adapter->pdev);
487#endif
1da177e4
LT		 488 del_timer_sync(&adapter->tx_fifo_stall_timer);
489 del_timer_sync(&adapter->watchdog_timer);
490 del_timer_sync(&adapter->phy_info_timer);
491
492#ifdef CONFIG_E1000_NAPI
493 netif_poll_disable(netdev);
494#endif
7bfa4816 495 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 496 adapter->link_speed = 0;
497 adapter->link_duplex = 0;
498 netif_carrier_off(netdev);
499 netif_stop_queue(netdev);
500
501 e1000_reset(adapter);
581d708e
MC		 502 e1000_clean_all_tx_rings(adapter);
503 e1000_clean_all_rx_rings(adapter);
1da177e4 504
57128197
JK		 505 /* Power down the PHY so no link is implied when interface is down *
506 * The PHY cannot be powered down if any of the following is TRUE *
507 * (a) WoL is enabled
508 * (b) AMT is active
509 * (c) SoL/IDER session is active */
510 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 511 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 512 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
513 !mng_mode_enabled &&
514 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 515 uint16_t mii_reg;
516 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
517 mii_reg |= MII_CR_POWER_DOWN;
518 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 519 mdelay(1);
1da177e4
LT		 520 }
521}
522
523void
524e1000_reset(struct e1000_adapter *adapter)
525{
2d7edb92 526 uint32_t pba, manc;
1125ecbc 527 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 528
529 /* Repartition Pba for greater than 9k mtu
530 * To take effect CTRL.RST is required.
531 */
532
2d7edb92
MC		 533 switch (adapter->hw.mac_type) {
534 case e1000_82547:
0e6ef3e0 535 case e1000_82547_rev_2:
2d7edb92
MC		 536 pba = E1000_PBA_30K;
537 break;
868d5309
MC		 538 case e1000_82571:
539 case e1000_82572:
6418ecc6 540 case e1000_80003es2lan:
868d5309
MC		 541 pba = E1000_PBA_38K;
542 break;
2d7edb92
MC		 543 case e1000_82573:
544 pba = E1000_PBA_12K;
545 break;
546 default:
547 pba = E1000_PBA_48K;
548 break;
549 }
550
96838a40 551 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 552 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 553 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 554
555
96838a40 556 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 557 adapter->tx_fifo_head = 0;
558 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
559 adapter->tx_fifo_size =
560 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
561 atomic_set(&adapter->tx_fifo_stall, 0);
562 }
2d7edb92 563
1da177e4
LT		 564 E1000_WRITE_REG(&adapter->hw, PBA, pba);
565
566 /* flow control settings */
f11b7f85
JK		 567 /* Set the FC high water mark to 90% of the FIFO size.
568 * Required to clear last 3 LSB */
569 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
570
571 adapter->hw.fc_high_water = fc_high_water_mark;
572 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 573 if (adapter->hw.mac_type == e1000_80003es2lan)
574 adapter->hw.fc_pause_time = 0xFFFF;
575 else
576 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 577 adapter->hw.fc_send_xon = 1;
578 adapter->hw.fc = adapter->hw.original_fc;
579
2d7edb92 580 /* Allow time for pending master requests to run */
1da177e4 581 e1000_reset_hw(&adapter->hw);
96838a40 582 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 583 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 584 if (e1000_init_hw(&adapter->hw))
1da177e4 585 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 586 e1000_update_mng_vlan(adapter);
1da177e4
LT		 587 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
588 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
589
590 e1000_reset_adaptive(&adapter->hw);
591 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 592 if (adapter->en_mng_pt) {
593 manc = E1000_READ_REG(&adapter->hw, MANC);
594 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
595 E1000_WRITE_REG(&adapter->hw, MANC, manc);
596 }
1da177e4
LT		 597}
598
599/**
600 * e1000_probe - Device Initialization Routine
601 * @pdev: PCI device information struct
602 * @ent: entry in e1000_pci_tbl
603 *
604 * Returns 0 on success, negative on failure
605 *
606 * e1000_probe initializes an adapter identified by a pci_dev structure.
607 * The OS initialization, configuring of the adapter private structure,
608 * and a hardware reset occur.
609 **/
610
611static int __devinit
612e1000_probe(struct pci_dev *pdev,
613 const struct pci_device_id *ent)
614{
615 struct net_device *netdev;
616 struct e1000_adapter *adapter;
2d7edb92 617 unsigned long mmio_start, mmio_len;
2d7edb92 618
1da177e4 619 static int cards_found = 0;
84916829 620 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 621 int i, err, pci_using_dac;
1da177e4
LT		 622 uint16_t eeprom_data;
623 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 624 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 625 return err;
626
96838a40 627 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 628 pci_using_dac = 1;
629 } else {
96838a40 630 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 631 E1000_ERR("No usable DMA configuration, aborting\n");
632 return err;
633 }
634 pci_using_dac = 0;
635 }
636
96838a40 637 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 638 return err;
639
640 pci_set_master(pdev);
641
642 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 643 if (!netdev) {
1da177e4
LT		 644 err = -ENOMEM;
645 goto err_alloc_etherdev;
646 }
647
648 SET_MODULE_OWNER(netdev);
649 SET_NETDEV_DEV(netdev, &pdev->dev);
650
651 pci_set_drvdata(pdev, netdev);
60490fe0 652 adapter = netdev_priv(netdev);
1da177e4
LT		 653 adapter->netdev = netdev;
654 adapter->pdev = pdev;
655 adapter->hw.back = adapter;
656 adapter->msg_enable = (1 << debug) - 1;
657
658 mmio_start = pci_resource_start(pdev, BAR_0);
659 mmio_len = pci_resource_len(pdev, BAR_0);
660
661 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 662 if (!adapter->hw.hw_addr) {
1da177e4
LT		 663 err = -EIO;
664 goto err_ioremap;
665 }
666
96838a40
JB		 667 for (i = BAR_1; i <= BAR_5; i++) {
668 if (pci_resource_len(pdev, i) == 0)
1da177e4 669 continue;
96838a40 670 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 671 adapter->hw.io_base = pci_resource_start(pdev, i);
672 break;
673 }
674 }
675
676 netdev->open = &e1000_open;
677 netdev->stop = &e1000_close;
678 netdev->hard_start_xmit = &e1000_xmit_frame;
679 netdev->get_stats = &e1000_get_stats;
680 netdev->set_multicast_list = &e1000_set_multi;
681 netdev->set_mac_address = &e1000_set_mac;
682 netdev->change_mtu = &e1000_change_mtu;
683 netdev->do_ioctl = &e1000_ioctl;
684 e1000_set_ethtool_ops(netdev);
685 netdev->tx_timeout = &e1000_tx_timeout;
686 netdev->watchdog_timeo = 5 * HZ;
687#ifdef CONFIG_E1000_NAPI
688 netdev->poll = &e1000_clean;
689 netdev->weight = 64;
690#endif
691 netdev->vlan_rx_register = e1000_vlan_rx_register;
692 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
693 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
694#ifdef CONFIG_NET_POLL_CONTROLLER
695 netdev->poll_controller = e1000_netpoll;
696#endif
697 strcpy(netdev->name, pci_name(pdev));
698
699 netdev->mem_start = mmio_start;
700 netdev->mem_end = mmio_start + mmio_len;
701 netdev->base_addr = adapter->hw.io_base;
702
703 adapter->bd_number = cards_found;
704
705 /* setup the private structure */
706
96838a40 707 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 708 goto err_sw_init;
709
96838a40 710 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 711 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
712
84916829
JK		 713 /* if ksp3, indicate if it's port a being setup */
714 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
715 e1000_ksp3_port_a == 0)
716 adapter->ksp3_port_a = 1;
717 e1000_ksp3_port_a++;
718 /* Reset for multiple KP3 adapters */
719 if (e1000_ksp3_port_a == 4)
720 e1000_ksp3_port_a = 0;
721
96838a40 722 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 723 netdev->features = NETIF_F_SG |
724 NETIF_F_HW_CSUM |
725 NETIF_F_HW_VLAN_TX |
726 NETIF_F_HW_VLAN_RX |
727 NETIF_F_HW_VLAN_FILTER;
728 }
729
730#ifdef NETIF_F_TSO
96838a40 731 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 732 (adapter->hw.mac_type != e1000_82547))
733 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 734
735#ifdef NETIF_F_TSO_IPV6
96838a40 736 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 737 netdev->features |= NETIF_F_TSO_IPV6;
738#endif
1da177e4 739#endif
96838a40 740 if (pci_using_dac)
1da177e4
LT		 741 netdev->features |= NETIF_F_HIGHDMA;
742
743 /* hard_start_xmit is safe against parallel locking */
744 netdev->features |= NETIF_F_LLTX;
745
2d7edb92
MC		 746 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
747
96838a40 748 /* before reading the EEPROM, reset the controller to
1da177e4 749 * put the device in a known good starting state */
96838a40 750
1da177e4
LT		 751 e1000_reset_hw(&adapter->hw);
752
753 /* make sure the EEPROM is good */
754
96838a40 755 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 756 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
757 err = -EIO;
758 goto err_eeprom;
759 }
760
761 /* copy the MAC address out of the EEPROM */
762
96838a40 763 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 764 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
765 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 766 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 767
96838a40 768 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 769 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
770 err = -EIO;
771 goto err_eeprom;
772 }
773
774 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
775
776 e1000_get_bus_info(&adapter->hw);
777
778 init_timer(&adapter->tx_fifo_stall_timer);
779 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
780 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
781
782 init_timer(&adapter->watchdog_timer);
783 adapter->watchdog_timer.function = &e1000_watchdog;
784 adapter->watchdog_timer.data = (unsigned long) adapter;
785
786 INIT_WORK(&adapter->watchdog_task,
787 (void (*)(void *))e1000_watchdog_task, adapter);
788
789 init_timer(&adapter->phy_info_timer);
790 adapter->phy_info_timer.function = &e1000_update_phy_info;
791 adapter->phy_info_timer.data = (unsigned long) adapter;
792
87041639
JK		 793 INIT_WORK(&adapter->reset_task,
794 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 795
796 /* we're going to reset, so assume we have no link for now */
797
798 netif_carrier_off(netdev);
799 netif_stop_queue(netdev);
800
801 e1000_check_options(adapter);
802
803 /* Initial Wake on LAN setting
804 * If APM wake is enabled in the EEPROM,
805 * enable the ACPI Magic Packet filter
806 */
807
96838a40 808 switch (adapter->hw.mac_type) {
1da177e4
LT		 809 case e1000_82542_rev2_0:
810 case e1000_82542_rev2_1:
811 case e1000_82543:
812 break;
813 case e1000_82544:
814 e1000_read_eeprom(&adapter->hw,
815 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
816 eeprom_apme_mask = E1000_EEPROM_82544_APM;
817 break;
818 case e1000_82546:
819 case e1000_82546_rev_3:
fd803241 820 case e1000_82571:
6418ecc6 821 case e1000_80003es2lan:
96838a40 822 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 823 e1000_read_eeprom(&adapter->hw,
824 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
825 break;
826 }
827 /* Fall Through */
828 default:
829 e1000_read_eeprom(&adapter->hw,
830 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
831 break;
832 }
96838a40 833 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 834 adapter->wol |= E1000_WUFC_MAG;
835
fb3d47d4
JK		 836 /* print bus type/speed/width info */
837 {
838 struct e1000_hw *hw = &adapter->hw;
839 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
840 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
841 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
842 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
843 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
844 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
845 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
846 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
847 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
848 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
849 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
850 "32-bit"));
851 }
852
853 for (i = 0; i < 6; i++)
854 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
855
1da177e4
LT		 856 /* reset the hardware with the new settings */
857 e1000_reset(adapter);
858
b55ccb35
JK		 859 /* If the controller is 82573 and f/w is AMT, do not set
860 * DRV_LOAD until the interface is up. For all other cases,
861 * let the f/w know that the h/w is now under the control
862 * of the driver. */
863 if (adapter->hw.mac_type != e1000_82573 ||
864 !e1000_check_mng_mode(&adapter->hw))
865 e1000_get_hw_control(adapter);
2d7edb92 866
1da177e4 867 strcpy(netdev->name, "eth%d");
96838a40 868 if ((err = register_netdev(netdev)))
1da177e4
LT		 869 goto err_register;
870
871 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
872
873 cards_found++;
874 return 0;
875
876err_register:
877err_sw_init:
878err_eeprom:
879 iounmap(adapter->hw.hw_addr);
880err_ioremap:
881 free_netdev(netdev);
882err_alloc_etherdev:
883 pci_release_regions(pdev);
884 return err;
885}
886
887/**
888 * e1000_remove - Device Removal Routine
889 * @pdev: PCI device information struct
890 *
891 * e1000_remove is called by the PCI subsystem to alert the driver
892 * that it should release a PCI device. The could be caused by a
893 * Hot-Plug event, or because the driver is going to be removed from
894 * memory.
895 **/
896
897static void __devexit
898e1000_remove(struct pci_dev *pdev)
899{
900 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 901 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 902 uint32_t manc;
581d708e
MC		 903#ifdef CONFIG_E1000_NAPI
904 int i;
905#endif
1da177e4 906
be2b28ed
JG		 907 flush_scheduled_work();
908
96838a40 909 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 910 adapter->hw.media_type == e1000_media_type_copper) {
911 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 912 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 913 manc |= E1000_MANC_ARP_EN;
914 E1000_WRITE_REG(&adapter->hw, MANC, manc);
915 }
916 }
917
b55ccb35
JK		 918 /* Release control of h/w to f/w. If f/w is AMT enabled, this
919 * would have already happened in close and is redundant. */
920 e1000_release_hw_control(adapter);
2d7edb92 921
1da177e4 922 unregister_netdev(netdev);
581d708e 923#ifdef CONFIG_E1000_NAPI
f56799ea 924 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 925 dev_put(&adapter->polling_netdev[i]);
581d708e 926#endif
1da177e4 927
96838a40 928 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 929 e1000_phy_hw_reset(&adapter->hw);
1da177e4 930
24025e4e
MC		 931 kfree(adapter->tx_ring);
932 kfree(adapter->rx_ring);
933#ifdef CONFIG_E1000_NAPI
934 kfree(adapter->polling_netdev);
935#endif
936
1da177e4
LT		 937 iounmap(adapter->hw.hw_addr);
938 pci_release_regions(pdev);
939
940 free_netdev(netdev);
941
942 pci_disable_device(pdev);
943}
944
945/**
946 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
947 * @adapter: board private structure to initialize
948 *
949 * e1000_sw_init initializes the Adapter private data structure.
950 * Fields are initialized based on PCI device information and
951 * OS network device settings (MTU size).
952 **/
953
954static int __devinit
955e1000_sw_init(struct e1000_adapter *adapter)
956{
957 struct e1000_hw *hw = &adapter->hw;
958 struct net_device *netdev = adapter->netdev;
959 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 960#ifdef CONFIG_E1000_NAPI
961 int i;
962#endif
1da177e4
LT		 963
964 /* PCI config space info */
965
966 hw->vendor_id = pdev->vendor;
967 hw->device_id = pdev->device;
968 hw->subsystem_vendor_id = pdev->subsystem_vendor;
969 hw->subsystem_id = pdev->subsystem_device;
970
971 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
972
973 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
974
9e2feace
AK		 975 adapter->rx_buffer_len = MAXIMUM_ETHERNET_FRAME_SIZE;
976 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 977 hw->max_frame_size = netdev->mtu +
978 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
979 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
980
981 /* identify the MAC */
982
96838a40 983 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 984 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
985 return -EIO;
986 }
987
988 /* initialize eeprom parameters */
989
96838a40 990 if (e1000_init_eeprom_params(hw)) {
2d7edb92
MC		 991 E1000_ERR("EEPROM initialization failed\n");
992 return -EIO;
993 }
1da177e4 994
96838a40 995 switch (hw->mac_type) {
1da177e4
LT		 996 default:
997 break;
998 case e1000_82541:
999 case e1000_82547:
1000 case e1000_82541_rev_2:
1001 case e1000_82547_rev_2:
1002 hw->phy_init_script = 1;
1003 break;
1004 }
1005
1006 e1000_set_media_type(hw);
1007
1008 hw->wait_autoneg_complete = FALSE;
1009 hw->tbi_compatibility_en = TRUE;
1010 hw->adaptive_ifs = TRUE;
1011
1012 /* Copper options */
1013
96838a40 1014 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1015 hw->mdix = AUTO_ALL_MODES;
1016 hw->disable_polarity_correction = FALSE;
1017 hw->master_slave = E1000_MASTER_SLAVE;
1018 }
1019
f56799ea
JK		 1020 adapter->num_tx_queues = 1;
1021 adapter->num_rx_queues = 1;
581d708e
MC		 1022
1023 if (e1000_alloc_queues(adapter)) {
1024 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1025 return -ENOMEM;
1026 }
1027
1028#ifdef CONFIG_E1000_NAPI
f56799ea 1029 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1030 adapter->polling_netdev[i].priv = adapter;
1031 adapter->polling_netdev[i].poll = &e1000_clean;
1032 adapter->polling_netdev[i].weight = 64;
1033 dev_hold(&adapter->polling_netdev[i]);
1034 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1035 }
7bfa4816 1036 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1037#endif
1038
1da177e4
LT		 1039 atomic_set(&adapter->irq_sem, 1);
1040 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1041
1042 return 0;
1043}
1044
581d708e
MC		 1045/**
1046 * e1000_alloc_queues - Allocate memory for all rings
1047 * @adapter: board private structure to initialize
1048 *
1049 * We allocate one ring per queue at run-time since we don't know the
1050 * number of queues at compile-time. The polling_netdev array is
1051 * intended for Multiqueue, but should work fine with a single queue.
1052 **/
1053
1054static int __devinit
1055e1000_alloc_queues(struct e1000_adapter *adapter)
1056{
1057 int size;
1058
f56799ea 1059 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1060 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1061 if (!adapter->tx_ring)
1062 return -ENOMEM;
1063 memset(adapter->tx_ring, 0, size);
1064
f56799ea 1065 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1066 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1067 if (!adapter->rx_ring) {
1068 kfree(adapter->tx_ring);
1069 return -ENOMEM;
1070 }
1071 memset(adapter->rx_ring, 0, size);
1072
1073#ifdef CONFIG_E1000_NAPI
f56799ea 1074 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1075 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1076 if (!adapter->polling_netdev) {
1077 kfree(adapter->tx_ring);
1078 kfree(adapter->rx_ring);
1079 return -ENOMEM;
1080 }
1081 memset(adapter->polling_netdev, 0, size);
1082#endif
1083
1084 return E1000_SUCCESS;
1085}
1086
1da177e4
LT		 1087/**
1088 * e1000_open - Called when a network interface is made active
1089 * @netdev: network interface device structure
1090 *
1091 * Returns 0 on success, negative value on failure
1092 *
1093 * The open entry point is called when a network interface is made
1094 * active by the system (IFF_UP). At this point all resources needed
1095 * for transmit and receive operations are allocated, the interrupt
1096 * handler is registered with the OS, the watchdog timer is started,
1097 * and the stack is notified that the interface is ready.
1098 **/
1099
1100static int
1101e1000_open(struct net_device *netdev)
1102{
60490fe0 1103 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1104 int err;
1105
1106 /* allocate transmit descriptors */
1107
581d708e 1108 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1109 goto err_setup_tx;
1110
1111 /* allocate receive descriptors */
1112
581d708e 1113 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1114 goto err_setup_rx;
1115
96838a40 1116 if ((err = e1000_up(adapter)))
1da177e4 1117 goto err_up;
2d7edb92 1118 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1119 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1120 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1121 e1000_update_mng_vlan(adapter);
1122 }
1da177e4 1123
b55ccb35
JK		 1124 /* If AMT is enabled, let the firmware know that the network
1125 * interface is now open */
1126 if (adapter->hw.mac_type == e1000_82573 &&
1127 e1000_check_mng_mode(&adapter->hw))
1128 e1000_get_hw_control(adapter);
1129
1da177e4
LT		 1130 return E1000_SUCCESS;
1131
1132err_up:
581d708e 1133 e1000_free_all_rx_resources(adapter);
1da177e4 1134err_setup_rx:
581d708e 1135 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1136err_setup_tx:
1137 e1000_reset(adapter);
1138
1139 return err;
1140}
1141
1142/**
1143 * e1000_close - Disables a network interface
1144 * @netdev: network interface device structure
1145 *
1146 * Returns 0, this is not allowed to fail
1147 *
1148 * The close entry point is called when an interface is de-activated
1149 * by the OS. The hardware is still under the drivers control, but
1150 * needs to be disabled. A global MAC reset is issued to stop the
1151 * hardware, and all transmit and receive resources are freed.
1152 **/
1153
1154static int
1155e1000_close(struct net_device *netdev)
1156{
60490fe0 1157 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1158
1159 e1000_down(adapter);
1160
581d708e
MC		 1161 e1000_free_all_tx_resources(adapter);
1162 e1000_free_all_rx_resources(adapter);
1da177e4 1163
96838a40 1164 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1165 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1166 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1167 }
b55ccb35
JK		 1168
1169 /* If AMT is enabled, let the firmware know that the network
1170 * interface is now closed */
1171 if (adapter->hw.mac_type == e1000_82573 &&
1172 e1000_check_mng_mode(&adapter->hw))
1173 e1000_release_hw_control(adapter);
1174
1da177e4
LT		 1175 return 0;
1176}
1177
1178/**
1179 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1180 * @adapter: address of board private structure
2d7edb92
MC		 1181 * @start: address of beginning of memory
1182 * @len: length of memory
1da177e4 1183 **/
e619d523 1184static boolean_t
1da177e4
LT		 1185e1000_check_64k_bound(struct e1000_adapter *adapter,
1186 void *start, unsigned long len)
1187{
1188 unsigned long begin = (unsigned long) start;
1189 unsigned long end = begin + len;
1190
2648345f
MC		 1191 /* First rev 82545 and 82546 need to not allow any memory
1192 * write location to cross 64k boundary due to errata 23 */
1da177e4 1193 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1194 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1195 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1196 }
1197
1198 return TRUE;
1199}
1200
1201/**
1202 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1203 * @adapter: board private structure
581d708e 1204 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1205 *
1206 * Return 0 on success, negative on failure
1207 **/
1208
3ad2cc67 1209static int
581d708e
MC		 1210e1000_setup_tx_resources(struct e1000_adapter *adapter,
1211 struct e1000_tx_ring *txdr)
1da177e4 1212{
1da177e4
LT		 1213 struct pci_dev *pdev = adapter->pdev;
1214 int size;
1215
1216 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1217
1218 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
96838a40 1219 if (!txdr->buffer_info) {
2648345f
MC		 1220 DPRINTK(PROBE, ERR,
1221 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1222 return -ENOMEM;
1223 }
1224 memset(txdr->buffer_info, 0, size);
1225
1226 /* round up to nearest 4K */
1227
1228 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1229 E1000_ROUNDUP(txdr->size, 4096);
1230
1231 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1232 if (!txdr->desc) {
1da177e4 1233setup_tx_desc_die:
1da177e4 1234 vfree(txdr->buffer_info);
2648345f
MC		 1235 DPRINTK(PROBE, ERR,
1236 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1237 return -ENOMEM;
1238 }
1239
2648345f 1240 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1241 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1242 void *olddesc = txdr->desc;
1243 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1244 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1245 "at %p\n", txdr->size, txdr->desc);
1246 /* Try again, without freeing the previous */
1da177e4 1247 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1248 /* Failed allocation, critical failure */
96838a40 1249 if (!txdr->desc) {
1da177e4
LT		 1250 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1251 goto setup_tx_desc_die;
1252 }
1253
1254 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1255 /* give up */
2648345f
MC		 1256 pci_free_consistent(pdev, txdr->size, txdr->desc,
1257 txdr->dma);
1da177e4
LT		 1258 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1259 DPRINTK(PROBE, ERR,
2648345f
MC		 1260 "Unable to allocate aligned memory "
1261 "for the transmit descriptor ring\n");
1da177e4
LT		 1262 vfree(txdr->buffer_info);
1263 return -ENOMEM;
1264 } else {
2648345f 1265 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1266 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1267 }
1268 }
1269 memset(txdr->desc, 0, txdr->size);
1270
1271 txdr->next_to_use = 0;
1272 txdr->next_to_clean = 0;
2ae76d98 1273 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1274
1275 return 0;
1276}
1277
581d708e
MC		 1278/**
1279 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1280 * (Descriptors) for all queues
1281 * @adapter: board private structure
1282 *
1283 * If this function returns with an error, then it's possible one or
1284 * more of the rings is populated (while the rest are not). It is the
1285 * callers duty to clean those orphaned rings.
1286 *
1287 * Return 0 on success, negative on failure
1288 **/
1289
1290int
1291e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1292{
1293 int i, err = 0;
1294
f56799ea 1295 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1296 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1297 if (err) {
1298 DPRINTK(PROBE, ERR,
1299 "Allocation for Tx Queue %u failed\n", i);
1300 break;
1301 }
1302 }
1303
1304 return err;
1305}
1306
1da177e4
LT		 1307/**
1308 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1309 * @adapter: board private structure
1310 *
1311 * Configure the Tx unit of the MAC after a reset.
1312 **/
1313
1314static void
1315e1000_configure_tx(struct e1000_adapter *adapter)
1316{
581d708e
MC		 1317 uint64_t tdba;
1318 struct e1000_hw *hw = &adapter->hw;
1319 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1320 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1321
1322 /* Setup the HW Tx Head and Tail descriptor pointers */
1323
f56799ea 1324 switch (adapter->num_tx_queues) {
24025e4e
MC		 1325 case 1:
1326 default:
581d708e
MC		 1327 tdba = adapter->tx_ring[0].dma;
1328 tdlen = adapter->tx_ring[0].count *
1329 sizeof(struct e1000_tx_desc);
1330 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1331 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1332 E1000_WRITE_REG(hw, TDLEN, tdlen);
1333 E1000_WRITE_REG(hw, TDH, 0);
1334 E1000_WRITE_REG(hw, TDT, 0);
1335 adapter->tx_ring[0].tdh = E1000_TDH;
1336 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1337 break;
1338 }
1da177e4
LT		 1339
1340 /* Set the default values for the Tx Inter Packet Gap timer */
1341
0fadb059
JK		 1342 if (hw->media_type == e1000_media_type_fiber ||
1343 hw->media_type == e1000_media_type_internal_serdes)
1344 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1345 else
1346 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1347
581d708e 1348 switch (hw->mac_type) {
1da177e4
LT		 1349 case e1000_82542_rev2_0:
1350 case e1000_82542_rev2_1:
1351 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1352 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1353 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1354 break;
87041639
JK		 1355 case e1000_80003es2lan:
1356 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1357 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1358 break;
1da177e4 1359 default:
0fadb059
JK		 1360 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1361 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1362 break;
1da177e4 1363 }
0fadb059
JK		 1364 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1365 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1366 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1367
1368 /* Set the Tx Interrupt Delay register */
1369
581d708e
MC		 1370 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1371 if (hw->mac_type >= e1000_82540)
1372 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1373
1374 /* Program the Transmit Control Register */
1375
581d708e 1376 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1377
1378 tctl &= ~E1000_TCTL_CT;
7e6c9861 1379 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1380 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1381
7e6c9861
JK		 1382#ifdef DISABLE_MULR
1383 /* disable Multiple Reads for debugging */
1384 tctl &= ~E1000_TCTL_MULR;
1385#endif
1da177e4 1386
2ae76d98
MC		 1387 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1388 tarc = E1000_READ_REG(hw, TARC0);
1389 tarc |= ((1 << 25) | (1 << 21));
1390 E1000_WRITE_REG(hw, TARC0, tarc);
1391 tarc = E1000_READ_REG(hw, TARC1);
1392 tarc |= (1 << 25);
1393 if (tctl & E1000_TCTL_MULR)
1394 tarc &= ~(1 << 28);
1395 else
1396 tarc |= (1 << 28);
1397 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1398 } else if (hw->mac_type == e1000_80003es2lan) {
1399 tarc = E1000_READ_REG(hw, TARC0);
1400 tarc |= 1;
1401 if (hw->media_type == e1000_media_type_internal_serdes)
1402 tarc |= (1 << 20);
1403 E1000_WRITE_REG(hw, TARC0, tarc);
1404 tarc = E1000_READ_REG(hw, TARC1);
1405 tarc |= 1;
1406 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1407 }
1408
581d708e 1409 e1000_config_collision_dist(hw);
1da177e4
LT		 1410
1411 /* Setup Transmit Descriptor Settings for eop descriptor */
1412 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1413 E1000_TXD_CMD_IFCS;
1414
581d708e 1415 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1416 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1417 else
1418 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1419
1420 /* Cache if we're 82544 running in PCI-X because we'll
1421 * need this to apply a workaround later in the send path. */
581d708e
MC		 1422 if (hw->mac_type == e1000_82544 &&
1423 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1424 adapter->pcix_82544 = 1;
7e6c9861
JK		 1425
1426 E1000_WRITE_REG(hw, TCTL, tctl);
1427
1da177e4
LT		 1428}
1429
1430/**
1431 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1432 * @adapter: board private structure
581d708e 1433 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1434 *
1435 * Returns 0 on success, negative on failure
1436 **/
1437
3ad2cc67 1438static int
581d708e
MC		 1439e1000_setup_rx_resources(struct e1000_adapter *adapter,
1440 struct e1000_rx_ring *rxdr)
1da177e4 1441{
1da177e4 1442 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1443 int size, desc_len;
1da177e4
LT		 1444
1445 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1446 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1447 if (!rxdr->buffer_info) {
2648345f
MC		 1448 DPRINTK(PROBE, ERR,
1449 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1450 return -ENOMEM;
1451 }
1452 memset(rxdr->buffer_info, 0, size);
1453
2d7edb92
MC		 1454 size = sizeof(struct e1000_ps_page) * rxdr->count;
1455 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1456 if (!rxdr->ps_page) {
2d7edb92
MC		 1457 vfree(rxdr->buffer_info);
1458 DPRINTK(PROBE, ERR,
1459 "Unable to allocate memory for the receive descriptor ring\n");
1460 return -ENOMEM;
1461 }
1462 memset(rxdr->ps_page, 0, size);
1463
1464 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1465 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1466 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1467 vfree(rxdr->buffer_info);
1468 kfree(rxdr->ps_page);
1469 DPRINTK(PROBE, ERR,
1470 "Unable to allocate memory for the receive descriptor ring\n");
1471 return -ENOMEM;
1472 }
1473 memset(rxdr->ps_page_dma, 0, size);
1474
96838a40 1475 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1476 desc_len = sizeof(struct e1000_rx_desc);
1477 else
1478 desc_len = sizeof(union e1000_rx_desc_packet_split);
1479
1da177e4
LT		 1480 /* Round up to nearest 4K */
1481
2d7edb92 1482 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1483 E1000_ROUNDUP(rxdr->size, 4096);
1484
1485 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1486
581d708e
MC		 1487 if (!rxdr->desc) {
1488 DPRINTK(PROBE, ERR,
1489 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1490setup_rx_desc_die:
1da177e4 1491 vfree(rxdr->buffer_info);
2d7edb92
MC		 1492 kfree(rxdr->ps_page);
1493 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1494 return -ENOMEM;
1495 }
1496
2648345f 1497 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1498 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1499 void *olddesc = rxdr->desc;
1500 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1501 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1502 "at %p\n", rxdr->size, rxdr->desc);
1503 /* Try again, without freeing the previous */
1da177e4 1504 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1505 /* Failed allocation, critical failure */
581d708e 1506 if (!rxdr->desc) {
1da177e4 1507 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1508 DPRINTK(PROBE, ERR,
1509 "Unable to allocate memory "
1510 "for the receive descriptor ring\n");
1da177e4
LT		 1511 goto setup_rx_desc_die;
1512 }
1513
1514 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1515 /* give up */
2648345f
MC		 1516 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1517 rxdr->dma);
1da177e4 1518 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1519 DPRINTK(PROBE, ERR,
1520 "Unable to allocate aligned memory "
1521 "for the receive descriptor ring\n");
581d708e 1522 goto setup_rx_desc_die;
1da177e4 1523 } else {
2648345f 1524 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1525 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1526 }
1527 }
1528 memset(rxdr->desc, 0, rxdr->size);
1529
1530 rxdr->next_to_clean = 0;
1531 rxdr->next_to_use = 0;
1532
1533 return 0;
1534}
1535
581d708e
MC		 1536/**
1537 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1538 * (Descriptors) for all queues
1539 * @adapter: board private structure
1540 *
1541 * If this function returns with an error, then it's possible one or
1542 * more of the rings is populated (while the rest are not). It is the
1543 * callers duty to clean those orphaned rings.
1544 *
1545 * Return 0 on success, negative on failure
1546 **/
1547
1548int
1549e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1550{
1551 int i, err = 0;
1552
f56799ea 1553 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1554 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1555 if (err) {
1556 DPRINTK(PROBE, ERR,
1557 "Allocation for Rx Queue %u failed\n", i);
1558 break;
1559 }
1560 }
1561
1562 return err;
1563}
1564
1da177e4 1565/**
2648345f 1566 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1567 * @adapter: Board private structure
1568 **/
e4c811c9
MC		 1569#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1570 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1571static void
1572e1000_setup_rctl(struct e1000_adapter *adapter)
1573{
2d7edb92
MC		 1574 uint32_t rctl, rfctl;
1575 uint32_t psrctl = 0;
35ec56bb 1576#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1577 uint32_t pages = 0;
1578#endif
1da177e4
LT		 1579
1580 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1581
1582 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1583
1584 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1585 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1586 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1587
0fadb059
JK		 1588 if (adapter->hw.mac_type > e1000_82543)
1589 rctl |= E1000_RCTL_SECRC;
1590
1591 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1592 rctl |= E1000_RCTL_SBP;
1593 else
1594 rctl &= ~E1000_RCTL_SBP;
1595
2d7edb92
MC		 1596 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1597 rctl &= ~E1000_RCTL_LPE;
1598 else
1599 rctl |= E1000_RCTL_LPE;
1600
1da177e4 1601 /* Setup buffer sizes */
9e2feace
AK		 1602 rctl &= ~E1000_RCTL_SZ_4096;
1603 rctl |= E1000_RCTL_BSEX;
1604 switch (adapter->rx_buffer_len) {
1605 case E1000_RXBUFFER_256:
1606 rctl |= E1000_RCTL_SZ_256;
1607 rctl &= ~E1000_RCTL_BSEX;
1608 break;
1609 case E1000_RXBUFFER_512:
1610 rctl |= E1000_RCTL_SZ_512;
1611 rctl &= ~E1000_RCTL_BSEX;
1612 break;
1613 case E1000_RXBUFFER_1024:
1614 rctl |= E1000_RCTL_SZ_1024;
1615 rctl &= ~E1000_RCTL_BSEX;
1616 break;
a1415ee6
JK		 1617 case E1000_RXBUFFER_2048:
1618 default:
1619 rctl |= E1000_RCTL_SZ_2048;
1620 rctl &= ~E1000_RCTL_BSEX;
1621 break;
1622 case E1000_RXBUFFER_4096:
1623 rctl |= E1000_RCTL_SZ_4096;
1624 break;
1625 case E1000_RXBUFFER_8192:
1626 rctl |= E1000_RCTL_SZ_8192;
1627 break;
1628 case E1000_RXBUFFER_16384:
1629 rctl |= E1000_RCTL_SZ_16384;
1630 break;
2d7edb92
MC		 1631 }
1632
35ec56bb 1633#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1634 /* 82571 and greater support packet-split where the protocol
1635 * header is placed in skb->data and the packet data is
1636 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1637 * In the case of a non-split, skb->data is linearly filled,
1638 * followed by the page buffers. Therefore, skb->data is
1639 * sized to hold the largest protocol header.
1640 */
e4c811c9
MC		 1641 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1642 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1643 PAGE_SIZE <= 16384)
1644 adapter->rx_ps_pages = pages;
1645 else
1646 adapter->rx_ps_pages = 0;
2d7edb92 1647#endif
e4c811c9 1648 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1649 /* Configure extra packet-split registers */
1650 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1651 rfctl |= E1000_RFCTL_EXTEN;
1652 /* disable IPv6 packet split support */
1653 rfctl |= E1000_RFCTL_IPV6_DIS;
1654 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1655
1656 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
96838a40 1657
2d7edb92
MC		 1658 psrctl |= adapter->rx_ps_bsize0 >>
1659 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1660
1661 switch (adapter->rx_ps_pages) {
1662 case 3:
1663 psrctl |= PAGE_SIZE <<
1664 E1000_PSRCTL_BSIZE3_SHIFT;
1665 case 2:
1666 psrctl |= PAGE_SIZE <<
1667 E1000_PSRCTL_BSIZE2_SHIFT;
1668 case 1:
1669 psrctl |= PAGE_SIZE >>
1670 E1000_PSRCTL_BSIZE1_SHIFT;
1671 break;
1672 }
2d7edb92
MC		 1673
1674 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1675 }
1676
1677 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1678}
1679
1680/**
1681 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1682 * @adapter: board private structure
1683 *
1684 * Configure the Rx unit of the MAC after a reset.
1685 **/
1686
1687static void
1688e1000_configure_rx(struct e1000_adapter *adapter)
1689{
581d708e
MC		 1690 uint64_t rdba;
1691 struct e1000_hw *hw = &adapter->hw;
1692 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1693
e4c811c9 1694 if (adapter->rx_ps_pages) {
0f15a8fa 1695 /* this is a 32 byte descriptor */
581d708e 1696 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1697 sizeof(union e1000_rx_desc_packet_split);
1698 adapter->clean_rx = e1000_clean_rx_irq_ps;
1699 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1700 } else {
581d708e
MC		 1701 rdlen = adapter->rx_ring[0].count *
1702 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1703 adapter->clean_rx = e1000_clean_rx_irq;
1704 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1705 }
1da177e4
LT		 1706
1707 /* disable receives while setting up the descriptors */
581d708e
MC		 1708 rctl = E1000_READ_REG(hw, RCTL);
1709 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1710
1711 /* set the Receive Delay Timer Register */
581d708e 1712 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1713
581d708e
MC		 1714 if (hw->mac_type >= e1000_82540) {
1715 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1716 if (adapter->itr > 1)
581d708e 1717 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1718 1000000000 / (adapter->itr * 256));
1719 }
1720
2ae76d98 1721 if (hw->mac_type >= e1000_82571) {
2ae76d98 1722 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1723 /* Reset delay timers after every interrupt */
6fc7a7ec 1724 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1725#ifdef CONFIG_E1000_NAPI
1726 /* Auto-Mask interrupts upon ICR read. */
1727 ctrl_ext |= E1000_CTRL_EXT_IAME;
1728#endif
2ae76d98 1729 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1730 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1731 E1000_WRITE_FLUSH(hw);
1732 }
1733
581d708e
MC		 1734 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1735 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1736 switch (adapter->num_rx_queues) {
24025e4e
MC		 1737 case 1:
1738 default:
581d708e
MC		 1739 rdba = adapter->rx_ring[0].dma;
1740 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1741 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1742 E1000_WRITE_REG(hw, RDLEN, rdlen);
1743 E1000_WRITE_REG(hw, RDH, 0);
1744 E1000_WRITE_REG(hw, RDT, 0);
1745 adapter->rx_ring[0].rdh = E1000_RDH;
1746 adapter->rx_ring[0].rdt = E1000_RDT;
1747 break;
24025e4e
MC		 1748 }
1749
1da177e4 1750 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1751 if (hw->mac_type >= e1000_82543) {
1752 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1753 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1754 rxcsum |= E1000_RXCSUM_TUOFL;
1755
868d5309 1756 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1757 * Must be used in conjunction with packet-split. */
96838a40
JB		 1758 if ((hw->mac_type >= e1000_82571) &&
1759 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1760 rxcsum |= E1000_RXCSUM_IPPCSE;
1761 }
1762 } else {
1763 rxcsum &= ~E1000_RXCSUM_TUOFL;
1764 /* don't need to clear IPPCSE as it defaults to 0 */
1765 }
581d708e 1766 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1767 }
1768
581d708e
MC		 1769 if (hw->mac_type == e1000_82573)
1770 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1771
1da177e4 1772 /* Enable Receives */
581d708e 1773 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1774}
1775
1776/**
581d708e 1777 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1778 * @adapter: board private structure
581d708e 1779 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1780 *
1781 * Free all transmit software resources
1782 **/
1783
3ad2cc67 1784static void
581d708e
MC		 1785e1000_free_tx_resources(struct e1000_adapter *adapter,
1786 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1787{
1788 struct pci_dev *pdev = adapter->pdev;
1789
581d708e 1790 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1791
581d708e
MC		 1792 vfree(tx_ring->buffer_info);
1793 tx_ring->buffer_info = NULL;
1da177e4 1794
581d708e 1795 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1796
581d708e
MC		 1797 tx_ring->desc = NULL;
1798}
1799
1800/**
1801 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1802 * @adapter: board private structure
1803 *
1804 * Free all transmit software resources
1805 **/
1806
1807void
1808e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1809{
1810 int i;
1811
f56799ea 1812 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1813 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1814}
1815
e619d523 1816static void
1da177e4
LT		 1817e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1818 struct e1000_buffer *buffer_info)
1819{
96838a40 1820 if (buffer_info->dma) {
2648345f
MC		 1821 pci_unmap_page(adapter->pdev,
1822 buffer_info->dma,
1823 buffer_info->length,
1824 PCI_DMA_TODEVICE);
1da177e4 1825 }
8241e35e 1826 if (buffer_info->skb)
1da177e4 1827 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1828 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1829}
1830
1831/**
1832 * e1000_clean_tx_ring - Free Tx Buffers
1833 * @adapter: board private structure
581d708e 1834 * @tx_ring: ring to be cleaned
1da177e4
LT		 1835 **/
1836
1837static void
581d708e
MC		 1838e1000_clean_tx_ring(struct e1000_adapter *adapter,
1839 struct e1000_tx_ring *tx_ring)
1da177e4 1840{
1da177e4
LT		 1841 struct e1000_buffer *buffer_info;
1842 unsigned long size;
1843 unsigned int i;
1844
1845 /* Free all the Tx ring sk_buffs */
1846
96838a40 1847 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1848 buffer_info = &tx_ring->buffer_info[i];
1849 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1850 }
1851
1852 size = sizeof(struct e1000_buffer) * tx_ring->count;
1853 memset(tx_ring->buffer_info, 0, size);
1854
1855 /* Zero out the descriptor ring */
1856
1857 memset(tx_ring->desc, 0, tx_ring->size);
1858
1859 tx_ring->next_to_use = 0;
1860 tx_ring->next_to_clean = 0;
fd803241 1861 tx_ring->last_tx_tso = 0;
1da177e4 1862
581d708e
MC		 1863 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1864 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1865}
1866
1867/**
1868 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1869 * @adapter: board private structure
1870 **/
1871
1872static void
1873e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1874{
1875 int i;
1876
f56799ea 1877 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1878 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1879}
1880
1881/**
1882 * e1000_free_rx_resources - Free Rx Resources
1883 * @adapter: board private structure
581d708e 1884 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1885 *
1886 * Free all receive software resources
1887 **/
1888
3ad2cc67 1889static void
581d708e
MC		 1890e1000_free_rx_resources(struct e1000_adapter *adapter,
1891 struct e1000_rx_ring *rx_ring)
1da177e4 1892{
1da177e4
LT		 1893 struct pci_dev *pdev = adapter->pdev;
1894
581d708e 1895 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1896
1897 vfree(rx_ring->buffer_info);
1898 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1899 kfree(rx_ring->ps_page);
1900 rx_ring->ps_page = NULL;
1901 kfree(rx_ring->ps_page_dma);
1902 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1903
1904 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1905
1906 rx_ring->desc = NULL;
1907}
1908
1909/**
581d708e 1910 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1911 * @adapter: board private structure
581d708e
MC		 1912 *
1913 * Free all receive software resources
1914 **/
1915
1916void
1917e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1918{
1919 int i;
1920
f56799ea 1921 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 1922 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1923}
1924
1925/**
1926 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1927 * @adapter: board private structure
1928 * @rx_ring: ring to free buffers from
1da177e4
LT		 1929 **/
1930
1931static void
581d708e
MC		 1932e1000_clean_rx_ring(struct e1000_adapter *adapter,
1933 struct e1000_rx_ring *rx_ring)
1da177e4 1934{
1da177e4 1935 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1936 struct e1000_ps_page *ps_page;
1937 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1938 struct pci_dev *pdev = adapter->pdev;
1939 unsigned long size;
2d7edb92 1940 unsigned int i, j;
1da177e4
LT		 1941
1942 /* Free all the Rx ring sk_buffs */
96838a40 1943 for (i = 0; i < rx_ring->count; i++) {
1da177e4 1944 buffer_info = &rx_ring->buffer_info[i];
96838a40 1945 if (buffer_info->skb) {
1da177e4
LT		 1946 pci_unmap_single(pdev,
1947 buffer_info->dma,
1948 buffer_info->length,
1949 PCI_DMA_FROMDEVICE);
1950
1951 dev_kfree_skb(buffer_info->skb);
1952 buffer_info->skb = NULL;
997f5cbd
JK		 1953 }
1954 ps_page = &rx_ring->ps_page[i];
1955 ps_page_dma = &rx_ring->ps_page_dma[i];
1956 for (j = 0; j < adapter->rx_ps_pages; j++) {
1957 if (!ps_page->ps_page[j]) break;
1958 pci_unmap_page(pdev,
1959 ps_page_dma->ps_page_dma[j],
1960 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1961 ps_page_dma->ps_page_dma[j] = 0;
1962 put_page(ps_page->ps_page[j]);
1963 ps_page->ps_page[j] = NULL;
1da177e4
LT		 1964 }
1965 }
1966
1967 size = sizeof(struct e1000_buffer) * rx_ring->count;
1968 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1969 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1970 memset(rx_ring->ps_page, 0, size);
1971 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1972 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1973
1974 /* Zero out the descriptor ring */
1975
1976 memset(rx_ring->desc, 0, rx_ring->size);
1977
1978 rx_ring->next_to_clean = 0;
1979 rx_ring->next_to_use = 0;
1980
581d708e
MC		 1981 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
1982 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
1983}
1984
1985/**
1986 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
1987 * @adapter: board private structure
1988 **/
1989
1990static void
1991e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
1992{
1993 int i;
1994
f56799ea 1995 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 1996 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 1997}
1998
1999/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2000 * and memory write and invalidate disabled for certain operations
2001 */
2002static void
2003e1000_enter_82542_rst(struct e1000_adapter *adapter)
2004{
2005 struct net_device *netdev = adapter->netdev;
2006 uint32_t rctl;
2007
2008 e1000_pci_clear_mwi(&adapter->hw);
2009
2010 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2011 rctl |= E1000_RCTL_RST;
2012 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2013 E1000_WRITE_FLUSH(&adapter->hw);
2014 mdelay(5);
2015
96838a40 2016 if (netif_running(netdev))
581d708e 2017 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2018}
2019
2020static void
2021e1000_leave_82542_rst(struct e1000_adapter *adapter)
2022{
2023 struct net_device *netdev = adapter->netdev;
2024 uint32_t rctl;
2025
2026 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2027 rctl &= ~E1000_RCTL_RST;
2028 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2029 E1000_WRITE_FLUSH(&adapter->hw);
2030 mdelay(5);
2031
96838a40 2032 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2033 e1000_pci_set_mwi(&adapter->hw);
2034
96838a40 2035 if (netif_running(netdev)) {
72d64a43
JK		 2036 /* No need to loop, because 82542 supports only 1 queue */
2037 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2038 e1000_configure_rx(adapter);
72d64a43 2039 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2040 }
2041}
2042
2043/**
2044 * e1000_set_mac - Change the Ethernet Address of the NIC
2045 * @netdev: network interface device structure
2046 * @p: pointer to an address structure
2047 *
2048 * Returns 0 on success, negative on failure
2049 **/
2050
2051static int
2052e1000_set_mac(struct net_device *netdev, void *p)
2053{
60490fe0 2054 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2055 struct sockaddr *addr = p;
2056
96838a40 2057 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2058 return -EADDRNOTAVAIL;
2059
2060 /* 82542 2.0 needs to be in reset to write receive address registers */
2061
96838a40 2062 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2063 e1000_enter_82542_rst(adapter);
2064
2065 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2066 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2067
2068 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2069
868d5309
MC		 2070 /* With 82571 controllers, LAA may be overwritten (with the default)
2071 * due to controller reset from the other port. */
2072 if (adapter->hw.mac_type == e1000_82571) {
2073 /* activate the work around */
2074 adapter->hw.laa_is_present = 1;
2075
96838a40
JB		 2076 /* Hold a copy of the LAA in RAR[14] This is done so that
2077 * between the time RAR[0] gets clobbered and the time it
2078 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2079 * of the RARs and no incoming packets directed to this port
96838a40 2080 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2081 * RAR[14] */
96838a40 2082 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2083 E1000_RAR_ENTRIES - 1);
2084 }
2085
96838a40 2086 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2087 e1000_leave_82542_rst(adapter);
2088
2089 return 0;
2090}
2091
2092/**
2093 * e1000_set_multi - Multicast and Promiscuous mode set
2094 * @netdev: network interface device structure
2095 *
2096 * The set_multi entry point is called whenever the multicast address
2097 * list or the network interface flags are updated. This routine is
2098 * responsible for configuring the hardware for proper multicast,
2099 * promiscuous mode, and all-multi behavior.
2100 **/
2101
2102static void
2103e1000_set_multi(struct net_device *netdev)
2104{
60490fe0 2105 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2106 struct e1000_hw *hw = &adapter->hw;
2107 struct dev_mc_list *mc_ptr;
2108 uint32_t rctl;
2109 uint32_t hash_value;
868d5309 2110 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2111
868d5309
MC		 2112 /* reserve RAR[14] for LAA over-write work-around */
2113 if (adapter->hw.mac_type == e1000_82571)
2114 rar_entries--;
1da177e4 2115
2648345f
MC		 2116 /* Check for Promiscuous and All Multicast modes */
2117
1da177e4
LT		 2118 rctl = E1000_READ_REG(hw, RCTL);
2119
96838a40 2120 if (netdev->flags & IFF_PROMISC) {
1da177e4 2121 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2122 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2123 rctl |= E1000_RCTL_MPE;
2124 rctl &= ~E1000_RCTL_UPE;
2125 } else {
2126 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2127 }
2128
2129 E1000_WRITE_REG(hw, RCTL, rctl);
2130
2131 /* 82542 2.0 needs to be in reset to write receive address registers */
2132
96838a40 2133 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2134 e1000_enter_82542_rst(adapter);
2135
2136 /* load the first 14 multicast address into the exact filters 1-14
2137 * RAR 0 is used for the station MAC adddress
2138 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2139 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2140 */
2141 mc_ptr = netdev->mc_list;
2142
96838a40 2143 for (i = 1; i < rar_entries; i++) {
868d5309 2144 if (mc_ptr) {
1da177e4
LT		 2145 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2146 mc_ptr = mc_ptr->next;
2147 } else {
2148 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2149 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2150 }
2151 }
2152
2153 /* clear the old settings from the multicast hash table */
2154
96838a40 2155 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1da177e4
LT		 2156 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2157
2158 /* load any remaining addresses into the hash table */
2159
96838a40 2160 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2161 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2162 e1000_mta_set(hw, hash_value);
2163 }
2164
96838a40 2165 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2166 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2167}
2168
2169/* Need to wait a few seconds after link up to get diagnostic information from
2170 * the phy */
2171
2172static void
2173e1000_update_phy_info(unsigned long data)
2174{
2175 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2176 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2177}
2178
2179/**
2180 * e1000_82547_tx_fifo_stall - Timer Call-back
2181 * @data: pointer to adapter cast into an unsigned long
2182 **/
2183
2184static void
2185e1000_82547_tx_fifo_stall(unsigned long data)
2186{
2187 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2188 struct net_device *netdev = adapter->netdev;
2189 uint32_t tctl;
2190
96838a40
JB		 2191 if (atomic_read(&adapter->tx_fifo_stall)) {
2192 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2193 E1000_READ_REG(&adapter->hw, TDH)) &&
2194 (E1000_READ_REG(&adapter->hw, TDFT) ==
2195 E1000_READ_REG(&adapter->hw, TDFH)) &&
2196 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2197 E1000_READ_REG(&adapter->hw, TDFHS))) {
2198 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2199 E1000_WRITE_REG(&adapter->hw, TCTL,
2200 tctl & ~E1000_TCTL_EN);
2201 E1000_WRITE_REG(&adapter->hw, TDFT,
2202 adapter->tx_head_addr);
2203 E1000_WRITE_REG(&adapter->hw, TDFH,
2204 adapter->tx_head_addr);
2205 E1000_WRITE_REG(&adapter->hw, TDFTS,
2206 adapter->tx_head_addr);
2207 E1000_WRITE_REG(&adapter->hw, TDFHS,
2208 adapter->tx_head_addr);
2209 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2210 E1000_WRITE_FLUSH(&adapter->hw);
2211
2212 adapter->tx_fifo_head = 0;
2213 atomic_set(&adapter->tx_fifo_stall, 0);
2214 netif_wake_queue(netdev);
2215 } else {
2216 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2217 }
2218 }
2219}
2220
2221/**
2222 * e1000_watchdog - Timer Call-back
2223 * @data: pointer to adapter cast into an unsigned long
2224 **/
2225static void
2226e1000_watchdog(unsigned long data)
2227{
2228 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2229
2230 /* Do the rest outside of interrupt context */
2231 schedule_work(&adapter->watchdog_task);
2232}
2233
2234static void
2235e1000_watchdog_task(struct e1000_adapter *adapter)
2236{
2237 struct net_device *netdev = adapter->netdev;
545c67c0 2238 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2239 uint32_t link, tctl;
1da177e4
LT		 2240
2241 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2242 if (adapter->hw.mac_type == e1000_82573) {
2243 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2244 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2245 e1000_update_mng_vlan(adapter);
96838a40 2246 }
1da177e4 2247
96838a40 2248 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2249 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2250 link = !adapter->hw.serdes_link_down;
2251 else
2252 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2253
96838a40
JB		 2254 if (link) {
2255 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2256 boolean_t txb2b = 1;
1da177e4
LT		 2257 e1000_get_speed_and_duplex(&adapter->hw,
2258 &adapter->link_speed,
2259 &adapter->link_duplex);
2260
2261 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2262 adapter->link_speed,
2263 adapter->link_duplex == FULL_DUPLEX ?
2264 "Full Duplex" : "Half Duplex");
2265
7e6c9861
JK		 2266 /* tweak tx_queue_len according to speed/duplex
2267 * and adjust the timeout factor */
66a2b0a3
JK		 2268 netdev->tx_queue_len = adapter->tx_queue_len;
2269 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2270 switch (adapter->link_speed) {
2271 case SPEED_10:
fe7fe28e 2272 txb2b = 0;
7e6c9861
JK		 2273 netdev->tx_queue_len = 10;
2274 adapter->tx_timeout_factor = 8;
2275 break;
2276 case SPEED_100:
fe7fe28e 2277 txb2b = 0;
7e6c9861
JK		 2278 netdev->tx_queue_len = 100;
2279 /* maybe add some timeout factor ? */
2280 break;
2281 }
2282
fe7fe28e 2283 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2284 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2285 txb2b == 0) {
7e6c9861
JK		 2286#define SPEED_MODE_BIT (1 << 21)
2287 uint32_t tarc0;
2288 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2289 tarc0 &= ~SPEED_MODE_BIT;
2290 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2291 }
2292
2293#ifdef NETIF_F_TSO
2294 /* disable TSO for pcie and 10/100 speeds, to avoid
2295 * some hardware issues */
2296 if (!adapter->tso_force &&
2297 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2298 switch (adapter->link_speed) {
2299 case SPEED_10:
66a2b0a3 2300 case SPEED_100:
7e6c9861
JK		 2301 DPRINTK(PROBE,INFO,
2302 "10/100 speed: disabling TSO\n");
2303 netdev->features &= ~NETIF_F_TSO;
2304 break;
2305 case SPEED_1000:
2306 netdev->features |= NETIF_F_TSO;
2307 break;
2308 default:
2309 /* oops */
66a2b0a3
JK		 2310 break;
2311 }
2312 }
7e6c9861
JK		 2313#endif
2314
2315 /* enable transmits in the hardware, need to do this
2316 * after setting TARC0 */
2317 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2318 tctl |= E1000_TCTL_EN;
2319 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2320
1da177e4
LT		 2321 netif_carrier_on(netdev);
2322 netif_wake_queue(netdev);
2323 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2324 adapter->smartspeed = 0;
2325 }
2326 } else {
96838a40 2327 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2328 adapter->link_speed = 0;
2329 adapter->link_duplex = 0;
2330 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2331 netif_carrier_off(netdev);
2332 netif_stop_queue(netdev);
2333 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2334
2335 /* 80003ES2LAN workaround--
2336 * For packet buffer work-around on link down event;
2337 * disable receives in the ISR and
2338 * reset device here in the watchdog
2339 */
2340 if (adapter->hw.mac_type == e1000_80003es2lan) {
2341 /* reset device */
2342 schedule_work(&adapter->reset_task);
2343 }
1da177e4
LT		 2344 }
2345
2346 e1000_smartspeed(adapter);
2347 }
2348
2349 e1000_update_stats(adapter);
2350
2351 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2352 adapter->tpt_old = adapter->stats.tpt;
2353 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2354 adapter->colc_old = adapter->stats.colc;
2355
2356 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2357 adapter->gorcl_old = adapter->stats.gorcl;
2358 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2359 adapter->gotcl_old = adapter->stats.gotcl;
2360
2361 e1000_update_adaptive(&adapter->hw);
2362
f56799ea 2363 if (!netif_carrier_ok(netdev)) {
581d708e 2364 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2365 /* We've lost link, so the controller stops DMA,
2366 * but we've got queued Tx work that's never going
2367 * to get done, so reset controller to flush Tx.
2368 * (Do the reset outside of interrupt context). */
87041639
JK		 2369 adapter->tx_timeout_count++;
2370 schedule_work(&adapter->reset_task);
1da177e4
LT		 2371 }
2372 }
2373
2374 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2375 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2376 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2377 * asymmetrical Tx or Rx gets ITR=8000; everyone
2378 * else is between 2000-8000. */
2379 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2380 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2381 adapter->gotcl - adapter->gorcl :
2382 adapter->gorcl - adapter->gotcl) / 10000;
2383 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2384 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2385 }
2386
2387 /* Cause software interrupt to ensure rx ring is cleaned */
2388 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2389
2648345f 2390 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2391 adapter->detect_tx_hung = TRUE;
2392
96838a40 2393 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2394 * reset from the other port. Set the appropriate LAA in RAR[0] */
2395 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2396 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2397
1da177e4
LT		 2398 /* Reset the timer */
2399 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2400}
2401
2402#define E1000_TX_FLAGS_CSUM 0x00000001
2403#define E1000_TX_FLAGS_VLAN 0x00000002
2404#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2405#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2406#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2407#define E1000_TX_FLAGS_VLAN_SHIFT 16
2408
e619d523 2409static int
581d708e
MC		 2410e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2411 struct sk_buff *skb)
1da177e4
LT		 2412{
2413#ifdef NETIF_F_TSO
2414 struct e1000_context_desc *context_desc;
545c67c0 2415 struct e1000_buffer *buffer_info;
1da177e4
LT		 2416 unsigned int i;
2417 uint32_t cmd_length = 0;
2d7edb92 2418 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2419 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2420 int err;
2421
96838a40 2422 if (skb_shinfo(skb)->tso_size) {
1da177e4
LT		 2423 if (skb_header_cloned(skb)) {
2424 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2425 if (err)
2426 return err;
2427 }
2428
2429 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2430 mss = skb_shinfo(skb)->tso_size;
96838a40 2431 if (skb->protocol == ntohs(ETH_P_IP)) {
2d7edb92
MC		 2432 skb->nh.iph->tot_len = 0;
2433 skb->nh.iph->check = 0;
2434 skb->h.th->check =
2435 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2436 skb->nh.iph->daddr,
2437 0,
2438 IPPROTO_TCP,
2439 0);
2440 cmd_length = E1000_TXD_CMD_IP;
2441 ipcse = skb->h.raw - skb->data - 1;
2442#ifdef NETIF_F_TSO_IPV6
96838a40 2443 } else if (skb->protocol == ntohs(ETH_P_IPV6)) {
2d7edb92
MC		 2444 skb->nh.ipv6h->payload_len = 0;
2445 skb->h.th->check =
2446 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2447 &skb->nh.ipv6h->daddr,
2448 0,
2449 IPPROTO_TCP,
2450 0);
2451 ipcse = 0;
2452#endif
2453 }
1da177e4
LT		 2454 ipcss = skb->nh.raw - skb->data;
2455 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2456 tucss = skb->h.raw - skb->data;
2457 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2458 tucse = 0;
2459
2460 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2461 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2462
581d708e
MC		 2463 i = tx_ring->next_to_use;
2464 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2465 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2466
2467 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2468 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2469 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2470 context_desc->upper_setup.tcp_fields.tucss = tucss;
2471 context_desc->upper_setup.tcp_fields.tucso = tucso;
2472 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2473 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2474 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2475 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2476
545c67c0
JK		 2477 buffer_info->time_stamp = jiffies;
2478
581d708e
MC		 2479 if (++i == tx_ring->count) i = 0;
2480 tx_ring->next_to_use = i;
1da177e4 2481
8241e35e 2482 return TRUE;
1da177e4
LT		 2483 }
2484#endif
2485
8241e35e 2486 return FALSE;
1da177e4
LT		 2487}
2488
e619d523 2489static boolean_t
581d708e
MC		 2490e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2491 struct sk_buff *skb)
1da177e4
LT		 2492{
2493 struct e1000_context_desc *context_desc;
545c67c0 2494 struct e1000_buffer *buffer_info;
1da177e4
LT		 2495 unsigned int i;
2496 uint8_t css;
2497
96838a40 2498 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2499 css = skb->h.raw - skb->data;
2500
581d708e 2501 i = tx_ring->next_to_use;
545c67c0 2502 buffer_info = &tx_ring->buffer_info[i];
581d708e 2503 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2504
2505 context_desc->upper_setup.tcp_fields.tucss = css;
2506 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2507 context_desc->upper_setup.tcp_fields.tucse = 0;
2508 context_desc->tcp_seg_setup.data = 0;
2509 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2510
545c67c0
JK		 2511 buffer_info->time_stamp = jiffies;
2512
581d708e
MC		 2513 if (unlikely(++i == tx_ring->count)) i = 0;
2514 tx_ring->next_to_use = i;
1da177e4
LT		 2515
2516 return TRUE;
2517 }
2518
2519 return FALSE;
2520}
2521
2522#define E1000_MAX_TXD_PWR 12
2523#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2524
e619d523 2525static int
581d708e
MC		 2526e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2527 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2528 unsigned int nr_frags, unsigned int mss)
1da177e4 2529{
1da177e4
LT		 2530 struct e1000_buffer *buffer_info;
2531 unsigned int len = skb->len;
2532 unsigned int offset = 0, size, count = 0, i;
2533 unsigned int f;
2534 len -= skb->data_len;
2535
2536 i = tx_ring->next_to_use;
2537
96838a40 2538 while (len) {
1da177e4
LT		 2539 buffer_info = &tx_ring->buffer_info[i];
2540 size = min(len, max_per_txd);
2541#ifdef NETIF_F_TSO
fd803241
JK		 2542 /* Workaround for Controller erratum --
2543 * descriptor for non-tso packet in a linear SKB that follows a
2544 * tso gets written back prematurely before the data is fully
0f15a8fa 2545 * DMA'd to the controller */
fd803241 2546 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2547 !skb_shinfo(skb)->tso_size) {
fd803241
JK		 2548 tx_ring->last_tx_tso = 0;
2549 size -= 4;
2550 }
2551
1da177e4
LT		 2552 /* Workaround for premature desc write-backs
2553 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2554 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2555 size -= 4;
2556#endif
97338bde
MC		 2557 /* work-around for errata 10 and it applies
2558 * to all controllers in PCI-X mode
2559 * The fix is to make sure that the first descriptor of a
2560 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2561 */
96838a40 2562 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2563 (size > 2015) && count == 0))
2564 size = 2015;
96838a40 2565
1da177e4
LT		 2566 /* Workaround for potential 82544 hang in PCI-X. Avoid
2567 * terminating buffers within evenly-aligned dwords. */
96838a40 2568 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2569 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2570 size > 4))
2571 size -= 4;
2572
2573 buffer_info->length = size;
2574 buffer_info->dma =
2575 pci_map_single(adapter->pdev,
2576 skb->data + offset,
2577 size,
2578 PCI_DMA_TODEVICE);
2579 buffer_info->time_stamp = jiffies;
2580
2581 len -= size;
2582 offset += size;
2583 count++;
96838a40 2584 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2585 }
2586
96838a40 2587 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2588 struct skb_frag_struct *frag;
2589
2590 frag = &skb_shinfo(skb)->frags[f];
2591 len = frag->size;
2592 offset = frag->page_offset;
2593
96838a40 2594 while (len) {
1da177e4
LT		 2595 buffer_info = &tx_ring->buffer_info[i];
2596 size = min(len, max_per_txd);
2597#ifdef NETIF_F_TSO
2598 /* Workaround for premature desc write-backs
2599 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2600 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2601 size -= 4;
2602#endif
2603 /* Workaround for potential 82544 hang in PCI-X.
2604 * Avoid terminating buffers within evenly-aligned
2605 * dwords. */
96838a40 2606 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2607 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2608 size > 4))
2609 size -= 4;
2610
2611 buffer_info->length = size;
2612 buffer_info->dma =
2613 pci_map_page(adapter->pdev,
2614 frag->page,
2615 offset,
2616 size,
2617 PCI_DMA_TODEVICE);
2618 buffer_info->time_stamp = jiffies;
2619
2620 len -= size;
2621 offset += size;
2622 count++;
96838a40 2623 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2624 }
2625 }
2626
2627 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2628 tx_ring->buffer_info[i].skb = skb;
2629 tx_ring->buffer_info[first].next_to_watch = i;
2630
2631 return count;
2632}
2633
e619d523 2634static void
581d708e
MC		 2635e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2636 int tx_flags, int count)
1da177e4 2637{
1da177e4
LT		 2638 struct e1000_tx_desc *tx_desc = NULL;
2639 struct e1000_buffer *buffer_info;
2640 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2641 unsigned int i;
2642
96838a40 2643 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2644 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2645 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2646 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2647
96838a40 2648 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2649 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2650 }
2651
96838a40 2652 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2653 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2654 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2655 }
2656
96838a40 2657 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2658 txd_lower |= E1000_TXD_CMD_VLE;
2659 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2660 }
2661
2662 i = tx_ring->next_to_use;
2663
96838a40 2664 while (count--) {
1da177e4
LT		 2665 buffer_info = &tx_ring->buffer_info[i];
2666 tx_desc = E1000_TX_DESC(*tx_ring, i);
2667 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2668 tx_desc->lower.data =
2669 cpu_to_le32(txd_lower | buffer_info->length);
2670 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2671 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2672 }
2673
2674 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2675
2676 /* Force memory writes to complete before letting h/w
2677 * know there are new descriptors to fetch. (Only
2678 * applicable for weak-ordered memory model archs,
2679 * such as IA-64). */
2680 wmb();
2681
2682 tx_ring->next_to_use = i;
581d708e 2683 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2684}
2685
2686/**
2687 * 82547 workaround to avoid controller hang in half-duplex environment.
2688 * The workaround is to avoid queuing a large packet that would span
2689 * the internal Tx FIFO ring boundary by notifying the stack to resend
2690 * the packet at a later time. This gives the Tx FIFO an opportunity to
2691 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2692 * to the beginning of the Tx FIFO.
2693 **/
2694
2695#define E1000_FIFO_HDR 0x10
2696#define E1000_82547_PAD_LEN 0x3E0
2697
e619d523 2698static int
1da177e4
LT		 2699e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2700{
2701 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2702 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2703
2704 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2705
96838a40 2706 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2707 goto no_fifo_stall_required;
2708
96838a40 2709 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2710 return 1;
2711
96838a40 2712 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2713 atomic_set(&adapter->tx_fifo_stall, 1);
2714 return 1;
2715 }
2716
2717no_fifo_stall_required:
2718 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2719 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2720 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2721 return 0;
2722}
2723
2d7edb92 2724#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2725static int
2d7edb92
MC		 2726e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2727{
2728 struct e1000_hw *hw = &adapter->hw;
2729 uint16_t length, offset;
96838a40
JB		 2730 if (vlan_tx_tag_present(skb)) {
2731 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2732 ( adapter->hw.mng_cookie.status &
2733 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2734 return 0;
2735 }
20a44028 2736 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2737 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2738 if ((htons(ETH_P_IP) == eth->h_proto)) {
2739 const struct iphdr *ip =
2d7edb92 2740 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2741 if (IPPROTO_UDP == ip->protocol) {
2742 struct udphdr *udp =
2743 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2744 (ip->ihl << 2));
96838a40 2745 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2746 offset = (uint8_t *)udp + 8 - skb->data;
2747 length = skb->len - offset;
2748
2749 return e1000_mng_write_dhcp_info(hw,
96838a40 2750 (uint8_t *)udp + 8,
2d7edb92
MC		 2751 length);
2752 }
2753 }
2754 }
2755 }
2756 return 0;
2757}
2758
1da177e4
LT		 2759#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2760static int
2761e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2762{
60490fe0 2763 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2764 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2765 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2766 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2767 unsigned int tx_flags = 0;
2768 unsigned int len = skb->len;
2769 unsigned long flags;
2770 unsigned int nr_frags = 0;
2771 unsigned int mss = 0;
2772 int count = 0;
96838a40 2773 int tso;
1da177e4
LT		 2774 unsigned int f;
2775 len -= skb->data_len;
2776
581d708e 2777 tx_ring = adapter->tx_ring;
24025e4e 2778
581d708e 2779 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2780 dev_kfree_skb_any(skb);
2781 return NETDEV_TX_OK;
2782 }
2783
2784#ifdef NETIF_F_TSO
2785 mss = skb_shinfo(skb)->tso_size;
2648345f 2786 /* The controller does a simple calculation to
1da177e4
LT		 2787 * make sure there is enough room in the FIFO before
2788 * initiating the DMA for each buffer. The calc is:
2789 * 4 = ceil(buffer len/mss). To make sure we don't
2790 * overrun the FIFO, adjust the max buffer len if mss
2791 * drops. */
96838a40 2792 if (mss) {
9a3056da 2793 uint8_t hdr_len;
1da177e4
LT		 2794 max_per_txd = min(mss << 2, max_per_txd);
2795 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2796
9f687888 2797 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2798 * points to just header, pull a few bytes of payload from
2799 * frags into skb->data */
2800 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2801 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2802 switch (adapter->hw.mac_type) {
2803 unsigned int pull_size;
2804 case e1000_82571:
2805 case e1000_82572:
2806 case e1000_82573:
2807 pull_size = min((unsigned int)4, skb->data_len);
2808 if (!__pskb_pull_tail(skb, pull_size)) {
2809 printk(KERN_ERR
2810 "__pskb_pull_tail failed.\n");
2811 dev_kfree_skb_any(skb);
749dfc70 2812 return NETDEV_TX_OK;
9f687888
JK		 2813 }
2814 len = skb->len - skb->data_len;
2815 break;
2816 default:
2817 /* do nothing */
2818 break;
d74bbd3b 2819 }
9a3056da 2820 }
1da177e4
LT		 2821 }
2822
9a3056da 2823 /* reserve a descriptor for the offload context */
96838a40 2824 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2825 count++;
2648345f 2826 count++;
1da177e4 2827#else
96838a40 2828 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2829 count++;
2830#endif
fd803241
JK		 2831
2832#ifdef NETIF_F_TSO
2833 /* Controller Erratum workaround */
2834 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2835 !skb_shinfo(skb)->tso_size)
fd803241
JK		 2836 count++;
2837#endif
2838
1da177e4
LT		 2839 count += TXD_USE_COUNT(len, max_txd_pwr);
2840
96838a40 2841 if (adapter->pcix_82544)
1da177e4
LT		 2842 count++;
2843
96838a40 2844 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2845 * in PCI-X mode, so add one more descriptor to the count
2846 */
96838a40 2847 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2848 (len > 2015)))
2849 count++;
2850
1da177e4 2851 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2852 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2853 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2854 max_txd_pwr);
96838a40 2855 if (adapter->pcix_82544)
1da177e4
LT		 2856 count += nr_frags;
2857
0f15a8fa
JK		 2858
2859 if (adapter->hw.tx_pkt_filtering &&
2860 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2861 e1000_transfer_dhcp_info(adapter, skb);
2862
581d708e
MC		 2863 local_irq_save(flags);
2864 if (!spin_trylock(&tx_ring->tx_lock)) {
2865 /* Collision - tell upper layer to requeue */
2866 local_irq_restore(flags);
2867 return NETDEV_TX_LOCKED;
2868 }
1da177e4
LT		 2869
2870 /* need: count + 2 desc gap to keep tail from touching
2871 * head, otherwise try next time */
581d708e 2872 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2873 netif_stop_queue(netdev);
581d708e 2874 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2875 return NETDEV_TX_BUSY;
2876 }
2877
96838a40
JB		 2878 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2879 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2880 netif_stop_queue(netdev);
2881 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2882 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2883 return NETDEV_TX_BUSY;
2884 }
2885 }
2886
96838a40 2887 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2888 tx_flags |= E1000_TX_FLAGS_VLAN;
2889 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2890 }
2891
581d708e 2892 first = tx_ring->next_to_use;
96838a40 2893
581d708e 2894 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2895 if (tso < 0) {
2896 dev_kfree_skb_any(skb);
581d708e 2897 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2898 return NETDEV_TX_OK;
2899 }
2900
fd803241
JK		 2901 if (likely(tso)) {
2902 tx_ring->last_tx_tso = 1;
1da177e4 2903 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2904 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2905 tx_flags |= E1000_TX_FLAGS_CSUM;
2906
2d7edb92 2907 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2908 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2909 * no longer assume, we must. */
581d708e 2910 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2911 tx_flags |= E1000_TX_FLAGS_IPV4;
2912
581d708e
MC		 2913 e1000_tx_queue(adapter, tx_ring, tx_flags,
2914 e1000_tx_map(adapter, tx_ring, skb, first,
2915 max_per_txd, nr_frags, mss));
1da177e4
LT		 2916
2917 netdev->trans_start = jiffies;
2918
2919 /* Make sure there is space in the ring for the next send. */
581d708e 2920 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2921 netif_stop_queue(netdev);
2922
581d708e 2923 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2924 return NETDEV_TX_OK;
2925}
2926
2927/**
2928 * e1000_tx_timeout - Respond to a Tx Hang
2929 * @netdev: network interface device structure
2930 **/
2931
2932static void
2933e1000_tx_timeout(struct net_device *netdev)
2934{
60490fe0 2935 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2936
2937 /* Do the reset outside of interrupt context */
87041639
JK		 2938 adapter->tx_timeout_count++;
2939 schedule_work(&adapter->reset_task);
1da177e4
LT		 2940}
2941
2942static void
87041639 2943e1000_reset_task(struct net_device *netdev)
1da177e4 2944{
60490fe0 2945 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2946
2947 e1000_down(adapter);
2948 e1000_up(adapter);
2949}
2950
2951/**
2952 * e1000_get_stats - Get System Network Statistics
2953 * @netdev: network interface device structure
2954 *
2955 * Returns the address of the device statistics structure.
2956 * The statistics are actually updated from the timer callback.
2957 **/
2958
2959static struct net_device_stats *
2960e1000_get_stats(struct net_device *netdev)
2961{
60490fe0 2962 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2963
6b7660cd 2964 /* only return the current stats */
1da177e4
LT		 2965 return &adapter->net_stats;
2966}
2967
2968/**
2969 * e1000_change_mtu - Change the Maximum Transfer Unit
2970 * @netdev: network interface device structure
2971 * @new_mtu: new value for maximum frame size
2972 *
2973 * Returns 0 on success, negative on failure
2974 **/
2975
2976static int
2977e1000_change_mtu(struct net_device *netdev, int new_mtu)
2978{
60490fe0 2979 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2980 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 2981 uint16_t eeprom_data = 0;
1da177e4 2982
96838a40
JB		 2983 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2984 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2985 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 2986 return -EINVAL;
2d7edb92 2987 }
1da177e4 2988
997f5cbd
JK		 2989 /* Adapter-specific max frame size limits. */
2990 switch (adapter->hw.mac_type) {
9e2feace 2991 case e1000_undefined ... e1000_82542_rev2_1:
997f5cbd
JK		 2992 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2993 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 2994 return -EINVAL;
2d7edb92 2995 }
997f5cbd 2996 break;
85b22eb6
JK		 2997 case e1000_82573:
2998 /* only enable jumbo frames if ASPM is disabled completely
2999 * this means both bits must be zero in 0x1A bits 3:2 */
3000 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3001 &eeprom_data);
3002 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
3003 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3004 DPRINTK(PROBE, ERR,
3005 "Jumbo Frames not supported.\n");
3006 return -EINVAL;
3007 }
3008 break;
3009 }
3010 /* fall through to get support */
997f5cbd
JK		 3011 case e1000_82571:
3012 case e1000_82572:
87041639 3013 case e1000_80003es2lan:
997f5cbd
JK		 3014#define MAX_STD_JUMBO_FRAME_SIZE 9234
3015 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3016 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3017 return -EINVAL;
3018 }
3019 break;
3020 default:
3021 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3022 break;
1da177e4
LT		 3023 }
3024
9e2feace
AK		 3025 /* NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3026 * means we reserve 2 more, this pushes us to allocate from the next
3027 * larger slab size
3028 * i.e. RXBUFFER_2048 --> size-4096 slab */
3029
3030 if (max_frame <= E1000_RXBUFFER_256)
3031 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3032 else if (max_frame <= E1000_RXBUFFER_512)
3033 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3034 else if (max_frame <= E1000_RXBUFFER_1024)
3035 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3036 else if (max_frame <= E1000_RXBUFFER_2048)
3037 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3038 else if (max_frame <= E1000_RXBUFFER_4096)
3039 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3040 else if (max_frame <= E1000_RXBUFFER_8192)
3041 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3042 else if (max_frame <= E1000_RXBUFFER_16384)
3043 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3044
3045 /* adjust allocation if LPE protects us, and we aren't using SBP */
3046#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
3047 if (!adapter->hw.tbi_compatibility_on &&
3048 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3049 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3050 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3051
2d7edb92
MC		 3052 netdev->mtu = new_mtu;
3053
96838a40 3054 if (netif_running(netdev)) {
1da177e4
LT		 3055 e1000_down(adapter);
3056 e1000_up(adapter);
3057 }
3058
1da177e4
LT		 3059 adapter->hw.max_frame_size = max_frame;
3060
3061 return 0;
3062}
3063
3064/**
3065 * e1000_update_stats - Update the board statistics counters
3066 * @adapter: board private structure
3067 **/
3068
3069void
3070e1000_update_stats(struct e1000_adapter *adapter)
3071{
3072 struct e1000_hw *hw = &adapter->hw;
3073 unsigned long flags;
3074 uint16_t phy_tmp;
3075
3076#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3077
3078 spin_lock_irqsave(&adapter->stats_lock, flags);
3079
3080 /* these counters are modified from e1000_adjust_tbi_stats,
3081 * called from the interrupt context, so they must only
3082 * be written while holding adapter->stats_lock
3083 */
3084
3085 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3086 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3087 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3088 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3089 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3090 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3091 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3092 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3093 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3094 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3095 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3096 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3097 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3098
3099 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3100 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3101 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3102 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3103 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3104 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3105 adapter->stats.dc += E1000_READ_REG(hw, DC);
3106 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3107 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3108 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3109 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3110 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3111 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3112 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3113 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3114 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3115 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3116 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3117 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3118 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3119 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3120 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3121 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3122 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3123 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3124 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3125 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3126 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3127 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3128 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3129 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3130 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3131 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3132 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3133
3134 /* used for adaptive IFS */
3135
3136 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3137 adapter->stats.tpt += hw->tx_packet_delta;
3138 hw->collision_delta = E1000_READ_REG(hw, COLC);
3139 adapter->stats.colc += hw->collision_delta;
3140
96838a40 3141 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3142 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3143 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3144 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3145 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3146 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3147 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3148 }
96838a40 3149 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3150 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3151 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3152 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3153 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3154 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3155 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3156 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3157 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3158 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3159 }
1da177e4
LT		 3160
3161 /* Fill out the OS statistics structure */
3162
3163 adapter->net_stats.rx_packets = adapter->stats.gprc;
3164 adapter->net_stats.tx_packets = adapter->stats.gptc;
3165 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3166 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3167 adapter->net_stats.multicast = adapter->stats.mprc;
3168 adapter->net_stats.collisions = adapter->stats.colc;
3169
3170 /* Rx Errors */
3171
87041639
JK		 3172 /* RLEC on some newer hardware can be incorrect so build
3173 * our own version based on RUC and ROC */
1da177e4
LT		 3174 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3175 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3176 adapter->stats.ruc + adapter->stats.roc +
3177 adapter->stats.cexterr;
87041639
JK		 3178 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3179 adapter->stats.roc;
1da177e4
LT		 3180 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3181 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3182 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3183
3184 /* Tx Errors */
3185
3186 adapter->net_stats.tx_errors = adapter->stats.ecol +
3187 adapter->stats.latecol;
3188 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3189 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3190 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3191
3192 /* Tx Dropped needs to be maintained elsewhere */
3193
3194 /* Phy Stats */
3195
96838a40
JB		 3196 if (hw->media_type == e1000_media_type_copper) {
3197 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3198 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3199 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3200 adapter->phy_stats.idle_errors += phy_tmp;
3201 }
3202
96838a40 3203 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3204 (hw->phy_type == e1000_phy_m88) &&
3205 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3206 adapter->phy_stats.receive_errors += phy_tmp;
3207 }
3208
3209 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3210}
3211
3212/**
3213 * e1000_intr - Interrupt Handler
3214 * @irq: interrupt number
3215 * @data: pointer to a network interface device structure
3216 * @pt_regs: CPU registers structure
3217 **/
3218
3219static irqreturn_t
3220e1000_intr(int irq, void *data, struct pt_regs *regs)
3221{
3222 struct net_device *netdev = data;
60490fe0 3223 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3224 struct e1000_hw *hw = &adapter->hw;
87041639 3225 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3226#ifndef CONFIG_E1000_NAPI
581d708e 3227 int i;
1e613fd9
JK		 3228#else
3229 /* Interrupt Auto-Mask...upon reading ICR,
3230 * interrupts are masked. No need for the
3231 * IMC write, but it does mean we should
3232 * account for it ASAP. */
3233 if (likely(hw->mac_type >= e1000_82571))
3234 atomic_inc(&adapter->irq_sem);
be2b28ed 3235#endif
1da177e4 3236
1e613fd9
JK		 3237 if (unlikely(!icr)) {
3238#ifdef CONFIG_E1000_NAPI
3239 if (hw->mac_type >= e1000_82571)
3240 e1000_irq_enable(adapter);
3241#endif
1da177e4 3242 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3243 }
1da177e4 3244
96838a40 3245 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3246 hw->get_link_status = 1;
87041639
JK		 3247 /* 80003ES2LAN workaround--
3248 * For packet buffer work-around on link down event;
3249 * disable receives here in the ISR and
3250 * reset adapter in watchdog
3251 */
3252 if (netif_carrier_ok(netdev) &&
3253 (adapter->hw.mac_type == e1000_80003es2lan)) {
3254 /* disable receives */
3255 rctl = E1000_READ_REG(hw, RCTL);
3256 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3257 }
1da177e4
LT		 3258 mod_timer(&adapter->watchdog_timer, jiffies);
3259 }
3260
3261#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3262 if (unlikely(hw->mac_type < e1000_82571)) {
3263 atomic_inc(&adapter->irq_sem);
3264 E1000_WRITE_REG(hw, IMC, ~0);
3265 E1000_WRITE_FLUSH(hw);
3266 }
581d708e
MC		 3267 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3268 __netif_rx_schedule(&adapter->polling_netdev[0]);
3269 else
3270 e1000_irq_enable(adapter);
c1605eb3 3271#else
1da177e4 3272 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3273 * Due to Hub Link bus being occupied, an interrupt
3274 * de-assertion message is not able to be sent.
3275 * When an interrupt assertion message is generated later,
3276 * two messages are re-ordered and sent out.
3277 * That causes APIC to think 82547 is in de-assertion
3278 * state, while 82547 is in assertion state, resulting
3279 * in dead lock. Writing IMC forces 82547 into
3280 * de-assertion state.
3281 */
3282 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3283 atomic_inc(&adapter->irq_sem);
2648345f 3284 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3285 }
3286
96838a40
JB		 3287 for (i = 0; i < E1000_MAX_INTR; i++)
3288 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3289 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3290 break;
3291
96838a40 3292 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3293 e1000_irq_enable(adapter);
581d708e 3294
c1605eb3 3295#endif
1da177e4
LT		 3296
3297 return IRQ_HANDLED;
3298}
3299
3300#ifdef CONFIG_E1000_NAPI
3301/**
3302 * e1000_clean - NAPI Rx polling callback
3303 * @adapter: board private structure
3304 **/
3305
3306static int
581d708e 3307e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3308{
581d708e
MC		 3309 struct e1000_adapter *adapter;
3310 int work_to_do = min(*budget, poll_dev->quota);
38bd3b26 3311 int tx_cleaned = 0, i = 0, work_done = 0;
581d708e
MC		 3312
3313 /* Must NOT use netdev_priv macro here. */
3314 adapter = poll_dev->priv;
3315
3316 /* Keep link state information with original netdev */
3317 if (!netif_carrier_ok(adapter->netdev))
3318 goto quit_polling;
2648345f 3319
581d708e
MC		 3320 while (poll_dev != &adapter->polling_netdev[i]) {
3321 i++;
5d9428de 3322 BUG_ON(i == adapter->num_rx_queues);
581d708e
MC		 3323 }
3324
8241e35e
JK		 3325 if (likely(adapter->num_tx_queues == 1)) {
3326 /* e1000_clean is called per-cpu. This lock protects
3327 * tx_ring[0] from being cleaned by multiple cpus
3328 * simultaneously. A failure obtaining the lock means
3329 * tx_ring[0] is currently being cleaned anyway. */
3330 if (spin_trylock(&adapter->tx_queue_lock)) {
3331 tx_cleaned = e1000_clean_tx_irq(adapter,
3332 &adapter->tx_ring[0]);
3333 spin_unlock(&adapter->tx_queue_lock);
3334 }
3335 } else
3336 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3337
581d708e
MC		 3338 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3339 &work_done, work_to_do);
1da177e4
LT		 3340
3341 *budget -= work_done;
581d708e 3342 poll_dev->quota -= work_done;
96838a40 3343
2b02893e 3344 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3345 if ((!tx_cleaned && (work_done == 0)) ||
581d708e
MC		 3346 !netif_running(adapter->netdev)) {
3347quit_polling:
3348 netif_rx_complete(poll_dev);
1da177e4
LT		 3349 e1000_irq_enable(adapter);
3350 return 0;
3351 }
3352
3353 return 1;
3354}
3355
3356#endif
3357/**
3358 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3359 * @adapter: board private structure
3360 **/
3361
3362static boolean_t
581d708e
MC		 3363e1000_clean_tx_irq(struct e1000_adapter *adapter,
3364 struct e1000_tx_ring *tx_ring)
1da177e4 3365{
1da177e4
LT		 3366 struct net_device *netdev = adapter->netdev;
3367 struct e1000_tx_desc *tx_desc, *eop_desc;
3368 struct e1000_buffer *buffer_info;
3369 unsigned int i, eop;
2a1af5d7
JK		 3370#ifdef CONFIG_E1000_NAPI
3371 unsigned int count = 0;
3372#endif
1da177e4
LT		 3373 boolean_t cleaned = FALSE;
3374
3375 i = tx_ring->next_to_clean;
3376 eop = tx_ring->buffer_info[i].next_to_watch;
3377 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3378
581d708e 3379 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3380 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3381 tx_desc = E1000_TX_DESC(*tx_ring, i);
3382 buffer_info = &tx_ring->buffer_info[i];
3383 cleaned = (i == eop);
3384
fd803241 3385 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3386 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3387
96838a40 3388 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3389 }
581d708e 3390
7bfa4816 3391
1da177e4
LT		 3392 eop = tx_ring->buffer_info[i].next_to_watch;
3393 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3394#ifdef CONFIG_E1000_NAPI
3395#define E1000_TX_WEIGHT 64
3396 /* weight of a sort for tx, to avoid endless transmit cleanup */
3397 if (count++ == E1000_TX_WEIGHT) break;
3398#endif
1da177e4
LT		 3399 }
3400
3401 tx_ring->next_to_clean = i;
3402
77b2aad5 3403#define TX_WAKE_THRESHOLD 32
96838a40 3404 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
77b2aad5
AK		 3405 netif_carrier_ok(netdev))) {
3406 spin_lock(&tx_ring->tx_lock);
3407 if (netif_queue_stopped(netdev) &&
3408 (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
3409 netif_wake_queue(netdev);
3410 spin_unlock(&tx_ring->tx_lock);
3411 }
2648345f 3412
581d708e 3413 if (adapter->detect_tx_hung) {
2648345f 3414 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3415 * check with the clearing of time_stamp and movement of i */
3416 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3417 if (tx_ring->buffer_info[eop].dma &&
3418 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3419 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3420 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3421 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3422
3423 /* detected Tx unit hang */
c6963ef5 3424 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3425 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3426 " TDH <%x>\n"
3427 " TDT <%x>\n"
3428 " next_to_use <%x>\n"
3429 " next_to_clean <%x>\n"
3430 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3431 " time_stamp <%lx>\n"
3432 " next_to_watch <%x>\n"
3433 " jiffies <%lx>\n"
3434 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3435 (unsigned long)((tx_ring - adapter->tx_ring) /
3436 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3437 readl(adapter->hw.hw_addr + tx_ring->tdh),
3438 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3439 tx_ring->next_to_use,
392137fa
JK		 3440 tx_ring->next_to_clean,
3441 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3442 eop,
3443 jiffies,
3444 eop_desc->upper.fields.status);
1da177e4 3445 netif_stop_queue(netdev);
70b8f1e1 3446 }
1da177e4 3447 }
1da177e4
LT		 3448 return cleaned;
3449}
3450
3451/**
3452 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3453 * @adapter: board private structure
3454 * @status_err: receive descriptor status and error fields
3455 * @csum: receive descriptor csum field
3456 * @sk_buff: socket buffer with received data
1da177e4
LT		 3457 **/
3458
e619d523 3459static void
1da177e4 3460e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3461 uint32_t status_err, uint32_t csum,
3462 struct sk_buff *skb)
1da177e4 3463{
2d7edb92
MC		 3464 uint16_t status = (uint16_t)status_err;
3465 uint8_t errors = (uint8_t)(status_err >> 24);
3466 skb->ip_summed = CHECKSUM_NONE;
3467
1da177e4 3468 /* 82543 or newer only */
96838a40 3469 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3470 /* Ignore Checksum bit is set */
96838a40 3471 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3472 /* TCP/UDP checksum error bit is set */
96838a40 3473 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3474 /* let the stack verify checksum errors */
1da177e4 3475 adapter->hw_csum_err++;
2d7edb92
MC		 3476 return;
3477 }
3478 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3479 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3480 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3481 return;
1da177e4 3482 } else {
96838a40 3483 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3484 return;
3485 }
3486 /* It must be a TCP or UDP packet with a valid checksum */
3487 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3488 /* TCP checksum is good */
3489 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3490 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3491 /* IP fragment with UDP payload */
3492 /* Hardware complements the payload checksum, so we undo it
3493 * and then put the value in host order for further stack use.
3494 */
3495 csum = ntohl(csum ^ 0xFFFF);
3496 skb->csum = csum;
3497 skb->ip_summed = CHECKSUM_HW;
1da177e4 3498 }
2d7edb92 3499 adapter->hw_csum_good++;
1da177e4
LT		 3500}
3501
3502/**
2d7edb92 3503 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3504 * @adapter: board private structure
3505 **/
3506
3507static boolean_t
3508#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3509e1000_clean_rx_irq(struct e1000_adapter *adapter,
3510 struct e1000_rx_ring *rx_ring,
3511 int *work_done, int work_to_do)
1da177e4 3512#else
581d708e
MC		 3513e1000_clean_rx_irq(struct e1000_adapter *adapter,
3514 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3515#endif
3516{
1da177e4
LT		 3517 struct net_device *netdev = adapter->netdev;
3518 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3519 struct e1000_rx_desc *rx_desc, *next_rxd;
3520 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3521 unsigned long flags;
3522 uint32_t length;
3523 uint8_t last_byte;
3524 unsigned int i;
72d64a43 3525 int cleaned_count = 0;
a1415ee6 3526 boolean_t cleaned = FALSE;
1da177e4
LT		 3527
3528 i = rx_ring->next_to_clean;
3529 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3530 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3531
b92ff8ee 3532 while (rx_desc->status & E1000_RXD_STAT_DD) {
86c3d59f 3533 struct sk_buff *skb, *next_skb;
a292ca6e 3534 u8 status;
1da177e4 3535#ifdef CONFIG_E1000_NAPI
96838a40 3536 if (*work_done >= work_to_do)
1da177e4
LT		 3537 break;
3538 (*work_done)++;
3539#endif
a292ca6e 3540 status = rx_desc->status;
b92ff8ee 3541 skb = buffer_info->skb;
86c3d59f
JB		 3542 buffer_info->skb = NULL;
3543
30320be8
JK		 3544 prefetch(skb->data - NET_IP_ALIGN);
3545
86c3d59f
JB		 3546 if (++i == rx_ring->count) i = 0;
3547 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3548 prefetch(next_rxd);
3549
86c3d59f
JB		 3550 next_buffer = &rx_ring->buffer_info[i];
3551 next_skb = next_buffer->skb;
30320be8 3552 prefetch(next_skb->data - NET_IP_ALIGN);
86c3d59f 3553
72d64a43
JK		 3554 cleaned = TRUE;
3555 cleaned_count++;
a292ca6e
JK		 3556 pci_unmap_single(pdev,
3557 buffer_info->dma,
3558 buffer_info->length,
1da177e4
LT		 3559 PCI_DMA_FROMDEVICE);
3560
1da177e4
LT		 3561 length = le16_to_cpu(rx_desc->length);
3562
a1415ee6
JK		 3563 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3564 /* All receives must fit into a single buffer */
3565 E1000_DBG("%s: Receive packet consumed multiple"
3566 " buffers\n", netdev->name);
3567 dev_kfree_skb_irq(skb);
1da177e4
LT		 3568 goto next_desc;
3569 }
3570
96838a40 3571 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3572 last_byte = *(skb->data + length - 1);
b92ff8ee 3573 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3574 rx_desc->errors, length, last_byte)) {
3575 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3576 e1000_tbi_adjust_stats(&adapter->hw,
3577 &adapter->stats,
1da177e4
LT		 3578 length, skb->data);
3579 spin_unlock_irqrestore(&adapter->stats_lock,
3580 flags);
3581 length--;
3582 } else {
9e2feace
AK		 3583 /* recycle */
3584 buffer_info->skb = skb;
1da177e4
LT		 3585 goto next_desc;
3586 }
9e2feace
AK		 3587 } else
3588 skb_put(skb, length);
1da177e4 3589
a292ca6e
JK		 3590 /* code added for copybreak, this should improve
3591 * performance for small packets with large amounts
3592 * of reassembly being done in the stack */
3593#define E1000_CB_LENGTH 256
a1415ee6 3594 if (length < E1000_CB_LENGTH) {
a292ca6e
JK		 3595 struct sk_buff *new_skb =
3596 dev_alloc_skb(length + NET_IP_ALIGN);
3597 if (new_skb) {
3598 skb_reserve(new_skb, NET_IP_ALIGN);
3599 new_skb->dev = netdev;
3600 memcpy(new_skb->data - NET_IP_ALIGN,
3601 skb->data - NET_IP_ALIGN,
3602 length + NET_IP_ALIGN);
3603 /* save the skb in buffer_info as good */
3604 buffer_info->skb = skb;
3605 skb = new_skb;
3606 skb_put(skb, length);
3607 }
a1415ee6
JK		 3608 } else
3609 skb_put(skb, length);
a292ca6e
JK		 3610
3611 /* end copybreak code */
1da177e4
LT		 3612
3613 /* Receive Checksum Offload */
a292ca6e
JK		 3614 e1000_rx_checksum(adapter,
3615 (uint32_t)(status) |
2d7edb92 3616 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3617 le16_to_cpu(rx_desc->csum), skb);
96838a40 3618
1da177e4
LT		 3619 skb->protocol = eth_type_trans(skb, netdev);
3620#ifdef CONFIG_E1000_NAPI
96838a40 3621 if (unlikely(adapter->vlgrp &&
a292ca6e 3622 (status & E1000_RXD_STAT_VP))) {
1da177e4 3623 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3624 le16_to_cpu(rx_desc->special) &
3625 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3626 } else {
3627 netif_receive_skb(skb);
3628 }
3629#else /* CONFIG_E1000_NAPI */
96838a40 3630 if (unlikely(adapter->vlgrp &&
b92ff8ee 3631 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3632 vlan_hwaccel_rx(skb, adapter->vlgrp,
3633 le16_to_cpu(rx_desc->special) &
3634 E1000_RXD_SPC_VLAN_MASK);
3635 } else {
3636 netif_rx(skb);
3637 }
3638#endif /* CONFIG_E1000_NAPI */
3639 netdev->last_rx = jiffies;
3640
3641next_desc:
3642 rx_desc->status = 0;
1da177e4 3643
72d64a43
JK		 3644 /* return some buffers to hardware, one at a time is too slow */
3645 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3646 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3647 cleaned_count = 0;
3648 }
3649
30320be8 3650 /* use prefetched values */
86c3d59f
JB		 3651 rx_desc = next_rxd;
3652 buffer_info = next_buffer;
1da177e4 3653 }
1da177e4 3654 rx_ring->next_to_clean = i;
72d64a43
JK		 3655
3656 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3657 if (cleaned_count)
3658 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3659
3660 return cleaned;
3661}
3662
3663/**
3664 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3665 * @adapter: board private structure
3666 **/
3667
3668static boolean_t
3669#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3670e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3671 struct e1000_rx_ring *rx_ring,
3672 int *work_done, int work_to_do)
2d7edb92 3673#else
581d708e
MC		 3674e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3675 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3676#endif
3677{
86c3d59f 3678 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3679 struct net_device *netdev = adapter->netdev;
3680 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3681 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3682 struct e1000_ps_page *ps_page;
3683 struct e1000_ps_page_dma *ps_page_dma;
86c3d59f 3684 struct sk_buff *skb, *next_skb;
2d7edb92
MC		 3685 unsigned int i, j;
3686 uint32_t length, staterr;
72d64a43 3687 int cleaned_count = 0;
2d7edb92
MC		 3688 boolean_t cleaned = FALSE;
3689
3690 i = rx_ring->next_to_clean;
3691 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3692 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3693 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3694
96838a40 3695 while (staterr & E1000_RXD_STAT_DD) {
30320be8 3696 buffer_info = &rx_ring->buffer_info[i];
2d7edb92
MC		 3697 ps_page = &rx_ring->ps_page[i];
3698 ps_page_dma = &rx_ring->ps_page_dma[i];
3699#ifdef CONFIG_E1000_NAPI
96838a40 3700 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3701 break;
3702 (*work_done)++;
3703#endif
86c3d59f
JB		 3704 skb = buffer_info->skb;
3705
30320be8
JK		 3706 /* in the packet split case this is header only */
3707 prefetch(skb->data - NET_IP_ALIGN);
3708
86c3d59f
JB		 3709 if (++i == rx_ring->count) i = 0;
3710 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3711 prefetch(next_rxd);
3712
86c3d59f
JB		 3713 next_buffer = &rx_ring->buffer_info[i];
3714 next_skb = next_buffer->skb;
30320be8 3715 prefetch(next_skb->data - NET_IP_ALIGN);
86c3d59f 3716
2d7edb92 3717 cleaned = TRUE;
72d64a43 3718 cleaned_count++;
2d7edb92
MC		 3719 pci_unmap_single(pdev, buffer_info->dma,
3720 buffer_info->length,
3721 PCI_DMA_FROMDEVICE);
3722
96838a40 3723 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3724 E1000_DBG("%s: Packet Split buffers didn't pick up"
3725 " the full packet\n", netdev->name);
3726 dev_kfree_skb_irq(skb);
3727 goto next_desc;
3728 }
1da177e4 3729
96838a40 3730 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3731 dev_kfree_skb_irq(skb);
3732 goto next_desc;
3733 }
3734
3735 length = le16_to_cpu(rx_desc->wb.middle.length0);
3736
96838a40 3737 if (unlikely(!length)) {
2d7edb92
MC		 3738 E1000_DBG("%s: Last part of the packet spanning"
3739 " multiple descriptors\n", netdev->name);
3740 dev_kfree_skb_irq(skb);
3741 goto next_desc;
3742 }
3743
3744 /* Good Receive */
3745 skb_put(skb, length);
3746
dc7c6add
JK		 3747 {
3748 /* this looks ugly, but it seems compiler issues make it
3749 more efficient than reusing j */
3750 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3751
3752 /* page alloc/put takes too long and effects small packet
3753 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 3754 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add
JK		 3755 u8 *vaddr;
3756 /* there is no documentation about how to call
3757 * kmap_atomic, so we can't hold the mapping
3758 * very long */
3759 pci_dma_sync_single_for_cpu(pdev,
3760 ps_page_dma->ps_page_dma[0],
3761 PAGE_SIZE,
3762 PCI_DMA_FROMDEVICE);
3763 vaddr = kmap_atomic(ps_page->ps_page[0],
3764 KM_SKB_DATA_SOFTIRQ);
3765 memcpy(skb->tail, vaddr, l1);
3766 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3767 pci_dma_sync_single_for_device(pdev,
3768 ps_page_dma->ps_page_dma[0],
3769 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3770 skb_put(skb, l1);
3771 length += l1;
3772 goto copydone;
3773 } /* if */
3774 }
3775
96838a40 3776 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3777 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3778 break;
2d7edb92
MC		 3779 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3780 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3781 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3782 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3783 length);
2d7edb92 3784 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3785 skb->len += length;
3786 skb->data_len += length;
5d51b80f 3787 skb->truesize += length;
2d7edb92
MC		 3788 }
3789
dc7c6add 3790copydone:
2d7edb92 3791 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3792 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3793 skb->protocol = eth_type_trans(skb, netdev);
3794
96838a40 3795 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3796 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3797 adapter->rx_hdr_split++;
2d7edb92 3798#ifdef CONFIG_E1000_NAPI
96838a40 3799 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3800 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3801 le16_to_cpu(rx_desc->wb.middle.vlan) &
3802 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3803 } else {
3804 netif_receive_skb(skb);
3805 }
3806#else /* CONFIG_E1000_NAPI */
96838a40 3807 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3808 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3809 le16_to_cpu(rx_desc->wb.middle.vlan) &
3810 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3811 } else {
3812 netif_rx(skb);
3813 }
3814#endif /* CONFIG_E1000_NAPI */
3815 netdev->last_rx = jiffies;
3816
3817next_desc:
c3d7a3a4 3818 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3819 buffer_info->skb = NULL;
2d7edb92 3820
72d64a43
JK		 3821 /* return some buffers to hardware, one at a time is too slow */
3822 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3823 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3824 cleaned_count = 0;
3825 }
3826
30320be8 3827 /* use prefetched values */
86c3d59f
JB		 3828 rx_desc = next_rxd;
3829 buffer_info = next_buffer;
3830
683a38f3 3831 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3832 }
3833 rx_ring->next_to_clean = i;
72d64a43
JK		 3834
3835 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3836 if (cleaned_count)
3837 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3838
3839 return cleaned;
3840}
3841
3842/**
2d7edb92 3843 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3844 * @adapter: address of board private structure
3845 **/
3846
3847static void
581d708e 3848e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3849 struct e1000_rx_ring *rx_ring,
a292ca6e 3850 int cleaned_count)
1da177e4 3851{
1da177e4
LT		 3852 struct net_device *netdev = adapter->netdev;
3853 struct pci_dev *pdev = adapter->pdev;
3854 struct e1000_rx_desc *rx_desc;
3855 struct e1000_buffer *buffer_info;
3856 struct sk_buff *skb;
2648345f
MC		 3857 unsigned int i;
3858 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3859
3860 i = rx_ring->next_to_use;
3861 buffer_info = &rx_ring->buffer_info[i];
3862
a292ca6e
JK		 3863 while (cleaned_count--) {
3864 if (!(skb = buffer_info->skb))
3865 skb = dev_alloc_skb(bufsz);
3866 else {
3867 skb_trim(skb, 0);
3868 goto map_skb;
3869 }
3870
96838a40 3871 if (unlikely(!skb)) {
1da177e4 3872 /* Better luck next round */
72d64a43 3873 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3874 break;
3875 }
3876
2648345f 3877 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3878 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3879 struct sk_buff *oldskb = skb;
2648345f
MC		 3880 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3881 "at %p\n", bufsz, skb->data);
3882 /* Try again, without freeing the previous */
1da177e4 3883 skb = dev_alloc_skb(bufsz);
2648345f 3884 /* Failed allocation, critical failure */
1da177e4
LT		 3885 if (!skb) {
3886 dev_kfree_skb(oldskb);
3887 break;
3888 }
2648345f 3889
1da177e4
LT		 3890 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3891 /* give up */
3892 dev_kfree_skb(skb);
3893 dev_kfree_skb(oldskb);
3894 break; /* while !buffer_info->skb */
3895 } else {
2648345f 3896 /* Use new allocation */
1da177e4
LT		 3897 dev_kfree_skb(oldskb);
3898 }
3899 }
1da177e4
LT		 3900 /* Make buffer alignment 2 beyond a 16 byte boundary
3901 * this will result in a 16 byte aligned IP header after
3902 * the 14 byte MAC header is removed
3903 */
3904 skb_reserve(skb, NET_IP_ALIGN);
3905
3906 skb->dev = netdev;
3907
3908 buffer_info->skb = skb;
3909 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 3910map_skb:
1da177e4
LT		 3911 buffer_info->dma = pci_map_single(pdev,
3912 skb->data,
3913 adapter->rx_buffer_len,
3914 PCI_DMA_FROMDEVICE);
3915
2648345f
MC		 3916 /* Fix for errata 23, can't cross 64kB boundary */
3917 if (!e1000_check_64k_bound(adapter,
3918 (void *)(unsigned long)buffer_info->dma,
3919 adapter->rx_buffer_len)) {
3920 DPRINTK(RX_ERR, ERR,
3921 "dma align check failed: %u bytes at %p\n",
3922 adapter->rx_buffer_len,
3923 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3924 dev_kfree_skb(skb);
3925 buffer_info->skb = NULL;
3926
2648345f 3927 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3928 adapter->rx_buffer_len,
3929 PCI_DMA_FROMDEVICE);
3930
3931 break; /* while !buffer_info->skb */
3932 }
1da177e4
LT		 3933 rx_desc = E1000_RX_DESC(*rx_ring, i);
3934 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3935
96838a40
JB		 3936 if (unlikely(++i == rx_ring->count))
3937 i = 0;
1da177e4
LT		 3938 buffer_info = &rx_ring->buffer_info[i];
3939 }
3940
b92ff8ee
JB		 3941 if (likely(rx_ring->next_to_use != i)) {
3942 rx_ring->next_to_use = i;
3943 if (unlikely(i-- == 0))
3944 i = (rx_ring->count - 1);
3945
3946 /* Force memory writes to complete before letting h/w
3947 * know there are new descriptors to fetch. (Only
3948 * applicable for weak-ordered memory model archs,
3949 * such as IA-64). */
3950 wmb();
3951 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
3952 }
1da177e4
LT		 3953}
3954
2d7edb92
MC		 3955/**
3956 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3957 * @adapter: address of board private structure
3958 **/
3959
3960static void
581d708e 3961e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 3962 struct e1000_rx_ring *rx_ring,
3963 int cleaned_count)
2d7edb92 3964{
2d7edb92
MC		 3965 struct net_device *netdev = adapter->netdev;
3966 struct pci_dev *pdev = adapter->pdev;
3967 union e1000_rx_desc_packet_split *rx_desc;
3968 struct e1000_buffer *buffer_info;
3969 struct e1000_ps_page *ps_page;
3970 struct e1000_ps_page_dma *ps_page_dma;
3971 struct sk_buff *skb;
3972 unsigned int i, j;
3973
3974 i = rx_ring->next_to_use;
3975 buffer_info = &rx_ring->buffer_info[i];
3976 ps_page = &rx_ring->ps_page[i];
3977 ps_page_dma = &rx_ring->ps_page_dma[i];
3978
72d64a43 3979 while (cleaned_count--) {
2d7edb92
MC		 3980 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3981
96838a40 3982 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3983 if (j < adapter->rx_ps_pages) {
3984 if (likely(!ps_page->ps_page[j])) {
3985 ps_page->ps_page[j] =
3986 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 3987 if (unlikely(!ps_page->ps_page[j])) {
3988 adapter->alloc_rx_buff_failed++;
e4c811c9 3989 goto no_buffers;
b92ff8ee 3990 }
e4c811c9
MC		 3991 ps_page_dma->ps_page_dma[j] =
3992 pci_map_page(pdev,
3993 ps_page->ps_page[j],
3994 0, PAGE_SIZE,
3995 PCI_DMA_FROMDEVICE);
3996 }
3997 /* Refresh the desc even if buffer_addrs didn't
96838a40 3998 * change because each write-back erases
e4c811c9
MC		 3999 * this info.
4000 */
4001 rx_desc->read.buffer_addr[j+1] =
4002 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4003 } else
4004 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4005 }
4006
4007 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4008
b92ff8ee
JB		 4009 if (unlikely(!skb)) {
4010 adapter->alloc_rx_buff_failed++;
2d7edb92 4011 break;
b92ff8ee 4012 }
2d7edb92
MC		 4013
4014 /* Make buffer alignment 2 beyond a 16 byte boundary
4015 * this will result in a 16 byte aligned IP header after
4016 * the 14 byte MAC header is removed
4017 */
4018 skb_reserve(skb, NET_IP_ALIGN);
4019
4020 skb->dev = netdev;
4021
4022 buffer_info->skb = skb;
4023 buffer_info->length = adapter->rx_ps_bsize0;
4024 buffer_info->dma = pci_map_single(pdev, skb->data,
4025 adapter->rx_ps_bsize0,
4026 PCI_DMA_FROMDEVICE);
4027
4028 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4029
96838a40 4030 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4031 buffer_info = &rx_ring->buffer_info[i];
4032 ps_page = &rx_ring->ps_page[i];
4033 ps_page_dma = &rx_ring->ps_page_dma[i];
4034 }
4035
4036no_buffers:
b92ff8ee
JB		 4037 if (likely(rx_ring->next_to_use != i)) {
4038 rx_ring->next_to_use = i;
4039 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4040
4041 /* Force memory writes to complete before letting h/w
4042 * know there are new descriptors to fetch. (Only
4043 * applicable for weak-ordered memory model archs,
4044 * such as IA-64). */
4045 wmb();
4046 /* Hardware increments by 16 bytes, but packet split
4047 * descriptors are 32 bytes...so we increment tail
4048 * twice as much.
4049 */
4050 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4051 }
2d7edb92
MC		 4052}
4053
1da177e4
LT		 4054/**
4055 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4056 * @adapter:
4057 **/
4058
4059static void
4060e1000_smartspeed(struct e1000_adapter *adapter)
4061{
4062 uint16_t phy_status;
4063 uint16_t phy_ctrl;
4064
96838a40 4065 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4066 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4067 return;
4068
96838a40 4069 if (adapter->smartspeed == 0) {
1da177e4
LT		 4070 /* If Master/Slave config fault is asserted twice,
4071 * we assume back-to-back */
4072 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4073 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4074 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4075 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4076 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4077 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4078 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4079 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4080 phy_ctrl);
4081 adapter->smartspeed++;
96838a40 4082 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4083 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4084 &phy_ctrl)) {
4085 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4086 MII_CR_RESTART_AUTO_NEG);
4087 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4088 phy_ctrl);
4089 }
4090 }
4091 return;
96838a40 4092 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4093 /* If still no link, perhaps using 2/3 pair cable */
4094 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4095 phy_ctrl |= CR_1000T_MS_ENABLE;
4096 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4097 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4098 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4099 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4100 MII_CR_RESTART_AUTO_NEG);
4101 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4102 }
4103 }
4104 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4105 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4106 adapter->smartspeed = 0;
4107}
4108
4109/**
4110 * e1000_ioctl -
4111 * @netdev:
4112 * @ifreq:
4113 * @cmd:
4114 **/
4115
4116static int
4117e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4118{
4119 switch (cmd) {
4120 case SIOCGMIIPHY:
4121 case SIOCGMIIREG:
4122 case SIOCSMIIREG:
4123 return e1000_mii_ioctl(netdev, ifr, cmd);
4124 default:
4125 return -EOPNOTSUPP;
4126 }
4127}
4128
4129/**
4130 * e1000_mii_ioctl -
4131 * @netdev:
4132 * @ifreq:
4133 * @cmd:
4134 **/
4135
4136static int
4137e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4138{
60490fe0 4139 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4140 struct mii_ioctl_data *data = if_mii(ifr);
4141 int retval;
4142 uint16_t mii_reg;
4143 uint16_t spddplx;
97876fc6 4144 unsigned long flags;
1da177e4 4145
96838a40 4146 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4147 return -EOPNOTSUPP;
4148
4149 switch (cmd) {
4150 case SIOCGMIIPHY:
4151 data->phy_id = adapter->hw.phy_addr;
4152 break;
4153 case SIOCGMIIREG:
96838a40 4154 if (!capable(CAP_NET_ADMIN))
1da177e4 4155 return -EPERM;
97876fc6 4156 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4157 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4158 &data->val_out)) {
4159 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4160 return -EIO;
97876fc6
MC		 4161 }
4162 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4163 break;
4164 case SIOCSMIIREG:
96838a40 4165 if (!capable(CAP_NET_ADMIN))
1da177e4 4166 return -EPERM;
96838a40 4167 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4168 return -EFAULT;
4169 mii_reg = data->val_in;
97876fc6 4170 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4171 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4172 mii_reg)) {
4173 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4174 return -EIO;
97876fc6 4175 }
cb764326 4176 if (adapter->hw.phy_type == e1000_media_type_copper) {
1da177e4
LT		 4177 switch (data->reg_num) {
4178 case PHY_CTRL:
96838a40 4179 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4180 break;
96838a40 4181 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4182 adapter->hw.autoneg = 1;
4183 adapter->hw.autoneg_advertised = 0x2F;
4184 } else {
4185 if (mii_reg & 0x40)
4186 spddplx = SPEED_1000;
4187 else if (mii_reg & 0x2000)
4188 spddplx = SPEED_100;
4189 else
4190 spddplx = SPEED_10;
4191 spddplx += (mii_reg & 0x100)
cb764326
JK		 4192 ? DUPLEX_FULL :
4193 DUPLEX_HALF;
1da177e4
LT		 4194 retval = e1000_set_spd_dplx(adapter,
4195 spddplx);
96838a40 4196 if (retval) {
97876fc6 4197 spin_unlock_irqrestore(
96838a40 4198 &adapter->stats_lock,
97876fc6 4199 flags);
1da177e4 4200 return retval;
97876fc6 4201 }
1da177e4 4202 }
96838a40 4203 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4204 e1000_down(adapter);
4205 e1000_up(adapter);
4206 } else
4207 e1000_reset(adapter);
4208 break;
4209 case M88E1000_PHY_SPEC_CTRL:
4210 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4211 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4212 spin_unlock_irqrestore(
4213 &adapter->stats_lock, flags);
1da177e4 4214 return -EIO;
97876fc6 4215 }
1da177e4
LT		 4216 break;
4217 }
4218 } else {
4219 switch (data->reg_num) {
4220 case PHY_CTRL:
96838a40 4221 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4222 break;
96838a40 4223 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4224 e1000_down(adapter);
4225 e1000_up(adapter);
4226 } else
4227 e1000_reset(adapter);
4228 break;
4229 }
4230 }
97876fc6 4231 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4232 break;
4233 default:
4234 return -EOPNOTSUPP;
4235 }
4236 return E1000_SUCCESS;
4237}
4238
4239void
4240e1000_pci_set_mwi(struct e1000_hw *hw)
4241{
4242 struct e1000_adapter *adapter = hw->back;
2648345f 4243 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4244
96838a40 4245 if (ret_val)
2648345f 4246 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4247}
4248
4249void
4250e1000_pci_clear_mwi(struct e1000_hw *hw)
4251{
4252 struct e1000_adapter *adapter = hw->back;
4253
4254 pci_clear_mwi(adapter->pdev);
4255}
4256
4257void
4258e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4259{
4260 struct e1000_adapter *adapter = hw->back;
4261
4262 pci_read_config_word(adapter->pdev, reg, value);
4263}
4264
4265void
4266e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4267{
4268 struct e1000_adapter *adapter = hw->back;
4269
4270 pci_write_config_word(adapter->pdev, reg, *value);
4271}
4272
4273uint32_t
4274e1000_io_read(struct e1000_hw *hw, unsigned long port)
4275{
4276 return inl(port);
4277}
4278
4279void
4280e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4281{
4282 outl(value, port);
4283}
4284
4285static void
4286e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4287{
60490fe0 4288 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4289 uint32_t ctrl, rctl;
4290
4291 e1000_irq_disable(adapter);
4292 adapter->vlgrp = grp;
4293
96838a40 4294 if (grp) {
1da177e4
LT		 4295 /* enable VLAN tag insert/strip */
4296 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4297 ctrl |= E1000_CTRL_VME;
4298 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4299
4300 /* enable VLAN receive filtering */
4301 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4302 rctl |= E1000_RCTL_VFE;
4303 rctl &= ~E1000_RCTL_CFIEN;
4304 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4305 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4306 } else {
4307 /* disable VLAN tag insert/strip */
4308 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4309 ctrl &= ~E1000_CTRL_VME;
4310 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4311
4312 /* disable VLAN filtering */
4313 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4314 rctl &= ~E1000_RCTL_VFE;
4315 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4316 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4317 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4318 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4319 }
1da177e4
LT		 4320 }
4321
4322 e1000_irq_enable(adapter);
4323}
4324
4325static void
4326e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4327{
60490fe0 4328 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4329 uint32_t vfta, index;
96838a40
JB		 4330
4331 if ((adapter->hw.mng_cookie.status &
4332 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4333 (vid == adapter->mng_vlan_id))
2d7edb92 4334 return;
1da177e4
LT		 4335 /* add VID to filter table */
4336 index = (vid >> 5) & 0x7F;
4337 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4338 vfta |= (1 << (vid & 0x1F));
4339 e1000_write_vfta(&adapter->hw, index, vfta);
4340}
4341
4342static void
4343e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4344{
60490fe0 4345 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4346 uint32_t vfta, index;
4347
4348 e1000_irq_disable(adapter);
4349
96838a40 4350 if (adapter->vlgrp)
1da177e4
LT		 4351 adapter->vlgrp->vlan_devices[vid] = NULL;
4352
4353 e1000_irq_enable(adapter);
4354
96838a40
JB		 4355 if ((adapter->hw.mng_cookie.status &
4356 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4357 (vid == adapter->mng_vlan_id)) {
4358 /* release control to f/w */
4359 e1000_release_hw_control(adapter);
2d7edb92 4360 return;
ff147013
JK		 4361 }
4362
1da177e4
LT		 4363 /* remove VID from filter table */
4364 index = (vid >> 5) & 0x7F;
4365 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4366 vfta &= ~(1 << (vid & 0x1F));
4367 e1000_write_vfta(&adapter->hw, index, vfta);
4368}
4369
4370static void
4371e1000_restore_vlan(struct e1000_adapter *adapter)
4372{
4373 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4374
96838a40 4375 if (adapter->vlgrp) {
1da177e4 4376 uint16_t vid;
96838a40
JB		 4377 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4378 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4379 continue;
4380 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4381 }
4382 }
4383}
4384
4385int
4386e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4387{
4388 adapter->hw.autoneg = 0;
4389
6921368f 4390 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4391 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4392 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4393 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4394 return -EINVAL;
4395 }
4396
96838a40 4397 switch (spddplx) {
1da177e4
LT		 4398 case SPEED_10 + DUPLEX_HALF:
4399 adapter->hw.forced_speed_duplex = e1000_10_half;
4400 break;
4401 case SPEED_10 + DUPLEX_FULL:
4402 adapter->hw.forced_speed_duplex = e1000_10_full;
4403 break;
4404 case SPEED_100 + DUPLEX_HALF:
4405 adapter->hw.forced_speed_duplex = e1000_100_half;
4406 break;
4407 case SPEED_100 + DUPLEX_FULL:
4408 adapter->hw.forced_speed_duplex = e1000_100_full;
4409 break;
4410 case SPEED_1000 + DUPLEX_FULL:
4411 adapter->hw.autoneg = 1;
4412 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4413 break;
4414 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4415 default:
2648345f 4416 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4417 return -EINVAL;
4418 }
4419 return 0;
4420}
4421
b6a1d5f8 4422#ifdef CONFIG_PM
0f15a8fa
JK		 4423/* Save/restore 16 or 64 dwords of PCI config space depending on which
4424 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4425 */
4426#define PCIE_CONFIG_SPACE_LEN 256
4427#define PCI_CONFIG_SPACE_LEN 64
4428static int
4429e1000_pci_save_state(struct e1000_adapter *adapter)
4430{
4431 struct pci_dev *dev = adapter->pdev;
4432 int size;
4433 int i;
0f15a8fa 4434
2f82665f
JB		 4435 if (adapter->hw.mac_type >= e1000_82571)
4436 size = PCIE_CONFIG_SPACE_LEN;
4437 else
4438 size = PCI_CONFIG_SPACE_LEN;
4439
4440 WARN_ON(adapter->config_space != NULL);
4441
4442 adapter->config_space = kmalloc(size, GFP_KERNEL);
4443 if (!adapter->config_space) {
4444 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4445 return -ENOMEM;
4446 }
4447 for (i = 0; i < (size / 4); i++)
4448 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4449 return 0;
4450}
4451
4452static void
4453e1000_pci_restore_state(struct e1000_adapter *adapter)
4454{
4455 struct pci_dev *dev = adapter->pdev;
4456 int size;
4457 int i;
0f15a8fa 4458
2f82665f
JB		 4459 if (adapter->config_space == NULL)
4460 return;
0f15a8fa 4461
2f82665f
JB		 4462 if (adapter->hw.mac_type >= e1000_82571)
4463 size = PCIE_CONFIG_SPACE_LEN;
4464 else
4465 size = PCI_CONFIG_SPACE_LEN;
4466 for (i = 0; i < (size / 4); i++)
4467 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4468 kfree(adapter->config_space);
4469 adapter->config_space = NULL;
4470 return;
4471}
4472#endif /* CONFIG_PM */
4473
1da177e4 4474static int
829ca9a3 4475e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4476{
4477 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4478 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4479 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4480 uint32_t wufc = adapter->wol;
240b1710 4481 int retval = 0;
1da177e4
LT		 4482
4483 netif_device_detach(netdev);
4484
96838a40 4485 if (netif_running(netdev))
1da177e4
LT		 4486 e1000_down(adapter);
4487
2f82665f 4488#ifdef CONFIG_PM
0f15a8fa
JK		 4489 /* Implement our own version of pci_save_state(pdev) because pci-
4490 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4491 retval = e1000_pci_save_state(adapter);
4492 if (retval)
4493 return retval;
4494#endif
4495
1da177e4 4496 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4497 if (status & E1000_STATUS_LU)
1da177e4
LT		 4498 wufc &= ~E1000_WUFC_LNKC;
4499
96838a40 4500 if (wufc) {
1da177e4
LT		 4501 e1000_setup_rctl(adapter);
4502 e1000_set_multi(netdev);
4503
4504 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4505 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4506 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4507 rctl |= E1000_RCTL_MPE;
4508 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4509 }
4510
96838a40 4511 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4512 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4513 /* advertise wake from D3Cold */
4514 #define E1000_CTRL_ADVD3WUC 0x00100000
4515 /* phy power management enable */
4516 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4517 ctrl |= E1000_CTRL_ADVD3WUC |
4518 E1000_CTRL_EN_PHY_PWR_MGMT;
4519 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4520 }
4521
96838a40 4522 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4523 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4524 /* keep the laser running in D3 */
4525 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4526 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4527 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4528 }
4529
2d7edb92
MC		 4530 /* Allow time for pending master requests to run */
4531 e1000_disable_pciex_master(&adapter->hw);
4532
1da177e4
LT		 4533 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4534 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4535 pci_enable_wake(pdev, PCI_D3hot, 1);
4536 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4537 } else {
4538 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4539 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4540 pci_enable_wake(pdev, PCI_D3hot, 0);
4541 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4542 }
4543
96838a40 4544 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4545 adapter->hw.media_type == e1000_media_type_copper) {
4546 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4547 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4548 manc |= E1000_MANC_ARP_EN;
4549 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4550 pci_enable_wake(pdev, PCI_D3hot, 1);
4551 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4552 }
4553 }
4554
b55ccb35
JK		 4555 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4556 * would have already happened in close and is redundant. */
4557 e1000_release_hw_control(adapter);
2d7edb92 4558
1da177e4 4559 pci_disable_device(pdev);
240b1710 4560
d0e027db 4561 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4562
4563 return 0;
4564}
4565
2f82665f 4566#ifdef CONFIG_PM
1da177e4
LT		 4567static int
4568e1000_resume(struct pci_dev *pdev)
4569{
4570 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4571 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4572 uint32_t manc, ret_val;
1da177e4 4573
d0e027db 4574 pci_set_power_state(pdev, PCI_D0);
2f82665f 4575 e1000_pci_restore_state(adapter);
2b02893e 4576 ret_val = pci_enable_device(pdev);
a4cb847d 4577 pci_set_master(pdev);
1da177e4 4578
d0e027db
AK		 4579 pci_enable_wake(pdev, PCI_D3hot, 0);
4580 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4581
4582 e1000_reset(adapter);
4583 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4584
96838a40 4585 if (netif_running(netdev))
1da177e4
LT		 4586 e1000_up(adapter);
4587
4588 netif_device_attach(netdev);
4589
96838a40 4590 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4591 adapter->hw.media_type == e1000_media_type_copper) {
4592 manc = E1000_READ_REG(&adapter->hw, MANC);
4593 manc &= ~(E1000_MANC_ARP_EN);
4594 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4595 }
4596
b55ccb35
JK		 4597 /* If the controller is 82573 and f/w is AMT, do not set
4598 * DRV_LOAD until the interface is up. For all other cases,
4599 * let the f/w know that the h/w is now under the control
4600 * of the driver. */
4601 if (adapter->hw.mac_type != e1000_82573 ||
4602 !e1000_check_mng_mode(&adapter->hw))
4603 e1000_get_hw_control(adapter);
2d7edb92 4604
1da177e4
LT		 4605 return 0;
4606}
4607#endif
1da177e4
LT		 4608#ifdef CONFIG_NET_POLL_CONTROLLER
4609/*
4610 * Polling 'interrupt' - used by things like netconsole to send skbs
4611 * without having to re-enable interrupts. It's not called while
4612 * the interrupt routine is executing.
4613 */
4614static void
2648345f 4615e1000_netpoll(struct net_device *netdev)
1da177e4 4616{
60490fe0 4617 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4618 disable_irq(adapter->pdev->irq);
4619 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4620 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4621#ifndef CONFIG_E1000_NAPI
4622 adapter->clean_rx(adapter, adapter->rx_ring);
4623#endif
1da177e4
LT		 4624 enable_irq(adapter->pdev->irq);
4625}
4626#endif
4627
4628/* e1000_main.c */
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