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[PATCH] e1000: fix receive breakage
[mirror_ubuntu-focal-kernel.git] / drivers / net / e1000 / e1000_main.c
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1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
73629bbc
JB		 32 * 6.3.9 12/16/2005
33 * o incorporate fix for recycled skbs from IBM LTC
34 * 6.3.7 11/18/2005
35 * o Honor eeprom setting for enabling/disabling Wake On Lan
36 * 6.3.5 11/17/2005
37 * o Fix memory leak in rx ring handling for PCI Express adapters
38 * 6.3.4 11/8/05
39 * o Patch from Jesper Juhl to remove redundant NULL checks for kfree
40 * 6.3.2 9/20/05
41 * o Render logic that sets/resets DRV_LOAD as inline functions to
42 * avoid code replication. If f/w is AMT then set DRV_LOAD only when
43 * network interface is open.
44 * o Handle DRV_LOAD set/reset in cases where AMT uses VLANs.
45 * o Adjust PBA partioning for Jumbo frames using MTU size and not
46 * rx_buffer_len
47 * 6.3.1 9/19/05
48 * o Use adapter->tx_timeout_factor in Tx Hung Detect logic
49 (e1000_clean_tx_irq)
50 * o Support for 8086:10B5 device (Quad Port)
51 * 6.2.14 9/15/05
52 * o In AMT enabled configurations, set/reset DRV_LOAD bit on interface
53 * open/close
54 * 6.2.13 9/14/05
55 * o Invoke e1000_check_mng_mode only for 8257x controllers since it
56 * accesses the FWSM that is not supported in other controllers
57 * 6.2.12 9/9/05
58 * o Add support for device id E1000_DEV_ID_82546GB_QUAD_COPPER
59 * o set RCTL:SECRC only for controllers newer than 82543.
60 * o When the n/w interface comes down reset DRV_LOAD bit to notify f/w.
61 * This code was moved from e1000_remove to e1000_close
62 * 6.2.10 9/6/05
63 * o Fix error in updating RDT in el1000_alloc_rx_buffers[_ps] -- one off.
64 * o Enable fc by default on 82573 controllers (do not read eeprom)
65 * o Fix rx_errors statistic not to include missed_packet_count
66 * o Fix rx_dropped statistic not to include missed_packet_count
67 (Padraig Brady)
68 * 6.2.9 8/30/05
69 * o Remove call to update statistics from the controller ib e1000_get_stats
70 * 6.2.8 8/30/05
71 * o Improved algorithm for rx buffer allocation/rdt update
72 * o Flow control watermarks relative to rx PBA size
73 * o Simplified 'Tx Hung' detect logic
74 * 6.2.7 8/17/05
75 * o Report rx buffer allocation failures and tx timeout counts in stats
76 * 6.2.6 8/16/05
77 * o Implement workaround for controller erratum -- linear non-tso packet
78 * following a TSO gets written back prematurely
79 * 6.2.5 8/15/05
80 * o Set netdev->tx_queue_len based on link speed/duplex settings.
81 * o Fix net_stats.rx_fifo_errors <p@draigBrady.com>
82 * o Do not power off PHY if SoL/IDER session is active
83 * 6.2.4 8/10/05
84 * o Fix loopback test setup/cleanup for 82571/3 controllers
85 * o Fix parsing of outgoing packets (e1000_transfer_dhcp_info) to treat
86 * all packets as raw
87 * o Prevent operations that will cause the PHY to be reset if SoL/IDER
88 * sessions are active and log a message
89 * 6.2.2 7/21/05
90 * o used fixed size descriptors for all MTU sizes, reduces memory load
73629bbc
JB		 91 * 6.1.2 4/13/05
92 * o Fixed ethtool diagnostics
93 * o Enabled flow control to take default eeprom settings
94 * o Added stats_lock around e1000_read_phy_reg commands to avoid concurrent
95 * calls, one from mii_ioctl and other from within update_stats while
96 * processing MIIREG ioctl.
1da177e4
LT		 97 */
98
99char e1000_driver_name[] = "e1000";
3ad2cc67 100static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 101#ifndef CONFIG_E1000_NAPI
102#define DRIVERNAPI
103#else
104#define DRIVERNAPI "-NAPI"
105#endif
4ee9c020 106#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 107char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 108static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 109
110/* e1000_pci_tbl - PCI Device ID Table
111 *
112 * Last entry must be all 0s
113 *
114 * Macro expands to...
115 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
116 */
117static struct pci_device_id e1000_pci_tbl[] = {
118 INTEL_E1000_ETHERNET_DEVICE(0x1000),
119 INTEL_E1000_ETHERNET_DEVICE(0x1001),
120 INTEL_E1000_ETHERNET_DEVICE(0x1004),
121 INTEL_E1000_ETHERNET_DEVICE(0x1008),
122 INTEL_E1000_ETHERNET_DEVICE(0x1009),
123 INTEL_E1000_ETHERNET_DEVICE(0x100C),
124 INTEL_E1000_ETHERNET_DEVICE(0x100D),
125 INTEL_E1000_ETHERNET_DEVICE(0x100E),
126 INTEL_E1000_ETHERNET_DEVICE(0x100F),
127 INTEL_E1000_ETHERNET_DEVICE(0x1010),
128 INTEL_E1000_ETHERNET_DEVICE(0x1011),
129 INTEL_E1000_ETHERNET_DEVICE(0x1012),
130 INTEL_E1000_ETHERNET_DEVICE(0x1013),
131 INTEL_E1000_ETHERNET_DEVICE(0x1014),
132 INTEL_E1000_ETHERNET_DEVICE(0x1015),
133 INTEL_E1000_ETHERNET_DEVICE(0x1016),
134 INTEL_E1000_ETHERNET_DEVICE(0x1017),
135 INTEL_E1000_ETHERNET_DEVICE(0x1018),
136 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 137 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 138 INTEL_E1000_ETHERNET_DEVICE(0x101D),
139 INTEL_E1000_ETHERNET_DEVICE(0x101E),
140 INTEL_E1000_ETHERNET_DEVICE(0x1026),
141 INTEL_E1000_ETHERNET_DEVICE(0x1027),
142 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 143 INTEL_E1000_ETHERNET_DEVICE(0x105E),
144 INTEL_E1000_ETHERNET_DEVICE(0x105F),
145 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 146 INTEL_E1000_ETHERNET_DEVICE(0x1075),
147 INTEL_E1000_ETHERNET_DEVICE(0x1076),
148 INTEL_E1000_ETHERNET_DEVICE(0x1077),
149 INTEL_E1000_ETHERNET_DEVICE(0x1078),
150 INTEL_E1000_ETHERNET_DEVICE(0x1079),
151 INTEL_E1000_ETHERNET_DEVICE(0x107A),
152 INTEL_E1000_ETHERNET_DEVICE(0x107B),
153 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 154 INTEL_E1000_ETHERNET_DEVICE(0x107D),
155 INTEL_E1000_ETHERNET_DEVICE(0x107E),
156 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 157 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 158 INTEL_E1000_ETHERNET_DEVICE(0x108B),
159 INTEL_E1000_ETHERNET_DEVICE(0x108C),
b7ee49db 160 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 161 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 162 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
1da177e4
LT		 163 /* required last entry */
164 {0,}
165};
166
167MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
168
169int e1000_up(struct e1000_adapter *adapter);
170void e1000_down(struct e1000_adapter *adapter);
171void e1000_reset(struct e1000_adapter *adapter);
172int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 173int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
174int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
175void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
176void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 177static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
178 struct e1000_tx_ring *txdr);
179static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
180 struct e1000_rx_ring *rxdr);
181static void e1000_free_tx_resources(struct e1000_adapter *adapter,
182 struct e1000_tx_ring *tx_ring);
183static void e1000_free_rx_resources(struct e1000_adapter *adapter,
184 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 185void e1000_update_stats(struct e1000_adapter *adapter);
186
187/* Local Function Prototypes */
188
189static int e1000_init_module(void);
190static void e1000_exit_module(void);
191static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
192static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 193static int e1000_alloc_queues(struct e1000_adapter *adapter);
194#ifdef CONFIG_E1000_MQ
195static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
196#endif
1da177e4
LT		 197static int e1000_sw_init(struct e1000_adapter *adapter);
198static int e1000_open(struct net_device *netdev);
199static int e1000_close(struct net_device *netdev);
200static void e1000_configure_tx(struct e1000_adapter *adapter);
201static void e1000_configure_rx(struct e1000_adapter *adapter);
202static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 203static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
204static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
205static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
206 struct e1000_tx_ring *tx_ring);
207static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
208 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 209static void e1000_set_multi(struct net_device *netdev);
210static void e1000_update_phy_info(unsigned long data);
211static void e1000_watchdog(unsigned long data);
212static void e1000_watchdog_task(struct e1000_adapter *adapter);
213static void e1000_82547_tx_fifo_stall(unsigned long data);
214static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
215static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
216static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
217static int e1000_set_mac(struct net_device *netdev, void *p);
218static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 219static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
220 struct e1000_tx_ring *tx_ring);
1da177e4 221#ifdef CONFIG_E1000_NAPI
581d708e 222static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 223static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 224 struct e1000_rx_ring *rx_ring,
1da177e4 225 int *work_done, int work_to_do);
2d7edb92 226static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 227 struct e1000_rx_ring *rx_ring,
2d7edb92 228 int *work_done, int work_to_do);
1da177e4 229#else
581d708e
MC		 230static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
231 struct e1000_rx_ring *rx_ring);
232static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
233 struct e1000_rx_ring *rx_ring);
1da177e4 234#endif
581d708e 235static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 236 struct e1000_rx_ring *rx_ring,
237 int cleaned_count);
581d708e 238static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 239 struct e1000_rx_ring *rx_ring,
240 int cleaned_count);
1da177e4
LT		 241static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
242static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
243 int cmd);
244void e1000_set_ethtool_ops(struct net_device *netdev);
245static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
246static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
247static void e1000_tx_timeout(struct net_device *dev);
248static void e1000_tx_timeout_task(struct net_device *dev);
249static void e1000_smartspeed(struct e1000_adapter *adapter);
250static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
251 struct sk_buff *skb);
252
253static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
254static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
255static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
256static void e1000_restore_vlan(struct e1000_adapter *adapter);
257
1da177e4 258#ifdef CONFIG_PM
977e74b5 259static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 260static int e1000_resume(struct pci_dev *pdev);
261#endif
262
263#ifdef CONFIG_NET_POLL_CONTROLLER
264/* for netdump / net console */
265static void e1000_netpoll (struct net_device *netdev);
266#endif
267
24025e4e
MC		 268#ifdef CONFIG_E1000_MQ
269/* for multiple Rx queues */
270void e1000_rx_schedule(void *data);
271#endif
272
1da177e4
LT		 273/* Exported from other modules */
274
275extern void e1000_check_options(struct e1000_adapter *adapter);
276
277static struct pci_driver e1000_driver = {
278 .name = e1000_driver_name,
279 .id_table = e1000_pci_tbl,
280 .probe = e1000_probe,
281 .remove = __devexit_p(e1000_remove),
282 /* Power Managment Hooks */
283#ifdef CONFIG_PM
284 .suspend = e1000_suspend,
285 .resume = e1000_resume
286#endif
287};
288
289MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
290MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
291MODULE_LICENSE("GPL");
292MODULE_VERSION(DRV_VERSION);
293
294static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
295module_param(debug, int, 0);
296MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
297
298/**
299 * e1000_init_module - Driver Registration Routine
300 *
301 * e1000_init_module is the first routine called when the driver is
302 * loaded. All it does is register with the PCI subsystem.
303 **/
304
305static int __init
306e1000_init_module(void)
307{
308 int ret;
309 printk(KERN_INFO "%s - version %s\n",
310 e1000_driver_string, e1000_driver_version);
311
312 printk(KERN_INFO "%s\n", e1000_copyright);
313
314 ret = pci_module_init(&e1000_driver);
8b378def 315
1da177e4
LT		 316 return ret;
317}
318
319module_init(e1000_init_module);
320
321/**
322 * e1000_exit_module - Driver Exit Cleanup Routine
323 *
324 * e1000_exit_module is called just before the driver is removed
325 * from memory.
326 **/
327
328static void __exit
329e1000_exit_module(void)
330{
1da177e4
LT		 331 pci_unregister_driver(&e1000_driver);
332}
333
334module_exit(e1000_exit_module);
335
336/**
337 * e1000_irq_disable - Mask off interrupt generation on the NIC
338 * @adapter: board private structure
339 **/
340
341static inline void
342e1000_irq_disable(struct e1000_adapter *adapter)
343{
344 atomic_inc(&adapter->irq_sem);
345 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
346 E1000_WRITE_FLUSH(&adapter->hw);
347 synchronize_irq(adapter->pdev->irq);
348}
349
350/**
351 * e1000_irq_enable - Enable default interrupt generation settings
352 * @adapter: board private structure
353 **/
354
355static inline void
356e1000_irq_enable(struct e1000_adapter *adapter)
357{
96838a40 358 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 359 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
360 E1000_WRITE_FLUSH(&adapter->hw);
361 }
362}
3ad2cc67
AB		 363
364static void
2d7edb92
MC		 365e1000_update_mng_vlan(struct e1000_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
369 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 370 if (adapter->vlgrp) {
371 if (!adapter->vlgrp->vlan_devices[vid]) {
372 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 373 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
374 e1000_vlan_rx_add_vid(netdev, vid);
375 adapter->mng_vlan_id = vid;
376 } else
377 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 378
379 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
380 (vid != old_vid) &&
2d7edb92
MC		 381 !adapter->vlgrp->vlan_devices[old_vid])
382 e1000_vlan_rx_kill_vid(netdev, old_vid);
383 }
384 }
385}
b55ccb35
JK		 386
387/**
388 * e1000_release_hw_control - release control of the h/w to f/w
389 * @adapter: address of board private structure
390 *
391 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
392 * For ASF and Pass Through versions of f/w this means that the
393 * driver is no longer loaded. For AMT version (only with 82573) i
394 * of the f/w this means that the netowrk i/f is closed.
395 *
396 **/
397
398static inline void
399e1000_release_hw_control(struct e1000_adapter *adapter)
400{
401 uint32_t ctrl_ext;
402 uint32_t swsm;
403
404 /* Let firmware taken over control of h/w */
405 switch (adapter->hw.mac_type) {
406 case e1000_82571:
407 case e1000_82572:
408 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
409 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
410 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
411 break;
412 case e1000_82573:
413 swsm = E1000_READ_REG(&adapter->hw, SWSM);
414 E1000_WRITE_REG(&adapter->hw, SWSM,
415 swsm & ~E1000_SWSM_DRV_LOAD);
416 default:
417 break;
418 }
419}
420
421/**
422 * e1000_get_hw_control - get control of the h/w from f/w
423 * @adapter: address of board private structure
424 *
425 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
426 * For ASF and Pass Through versions of f/w this means that
427 * the driver is loaded. For AMT version (only with 82573)
428 * of the f/w this means that the netowrk i/f is open.
429 *
430 **/
431
432static inline void
433e1000_get_hw_control(struct e1000_adapter *adapter)
434{
435 uint32_t ctrl_ext;
436 uint32_t swsm;
437 /* Let firmware know the driver has taken over */
438 switch (adapter->hw.mac_type) {
439 case e1000_82571:
440 case e1000_82572:
441 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
442 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
443 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
444 break;
445 case e1000_82573:
446 swsm = E1000_READ_REG(&adapter->hw, SWSM);
447 E1000_WRITE_REG(&adapter->hw, SWSM,
448 swsm | E1000_SWSM_DRV_LOAD);
449 break;
450 default:
451 break;
452 }
453}
454
1da177e4
LT		 455int
456e1000_up(struct e1000_adapter *adapter)
457{
458 struct net_device *netdev = adapter->netdev;
581d708e 459 int i, err;
1da177e4
LT		 460
461 /* hardware has been reset, we need to reload some things */
462
463 /* Reset the PHY if it was previously powered down */
96838a40 464 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 465 uint16_t mii_reg;
466 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
96838a40 467 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4
LT		 468 e1000_phy_reset(&adapter->hw);
469 }
470
471 e1000_set_multi(netdev);
472
473 e1000_restore_vlan(adapter);
474
475 e1000_configure_tx(adapter);
476 e1000_setup_rctl(adapter);
477 e1000_configure_rx(adapter);
72d64a43
JK		 478 /* call E1000_DESC_UNUSED which always leaves
479 * at least 1 descriptor unused to make sure
480 * next_to_use != next_to_clean */
f56799ea 481 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 482 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 483 adapter->alloc_rx_buf(adapter, ring,
484 E1000_DESC_UNUSED(ring));
f56799ea 485 }
1da177e4 486
fa4f7ef3 487#ifdef CONFIG_PCI_MSI
96838a40 488 if (adapter->hw.mac_type > e1000_82547_rev_2) {
fa4f7ef3 489 adapter->have_msi = TRUE;
96838a40 490 if ((err = pci_enable_msi(adapter->pdev))) {
fa4f7ef3
MC		 491 DPRINTK(PROBE, ERR,
492 "Unable to allocate MSI interrupt Error: %d\n", err);
493 adapter->have_msi = FALSE;
494 }
495 }
496#endif
96838a40 497 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
1da177e4 498 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 499 netdev->name, netdev))) {
500 DPRINTK(PROBE, ERR,
501 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 502 return err;
2648345f 503 }
1da177e4 504
7bfa4816
JK		 505#ifdef CONFIG_E1000_MQ
506 e1000_setup_queue_mapping(adapter);
507#endif
508
509 adapter->tx_queue_len = netdev->tx_queue_len;
510
1da177e4 511 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 512
513#ifdef CONFIG_E1000_NAPI
514 netif_poll_enable(netdev);
515#endif
5de55624
MC		 516 e1000_irq_enable(adapter);
517
1da177e4
LT		 518 return 0;
519}
520
521void
522e1000_down(struct e1000_adapter *adapter)
523{
524 struct net_device *netdev = adapter->netdev;
57128197
JK		 525 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
526 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 527
528 e1000_irq_disable(adapter);
24025e4e
MC		 529#ifdef CONFIG_E1000_MQ
530 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
531#endif
1da177e4 532 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3 533#ifdef CONFIG_PCI_MSI
96838a40 534 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
fa4f7ef3
MC		 535 adapter->have_msi == TRUE)
536 pci_disable_msi(adapter->pdev);
537#endif
1da177e4
LT		 538 del_timer_sync(&adapter->tx_fifo_stall_timer);
539 del_timer_sync(&adapter->watchdog_timer);
540 del_timer_sync(&adapter->phy_info_timer);
541
542#ifdef CONFIG_E1000_NAPI
543 netif_poll_disable(netdev);
544#endif
7bfa4816 545 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 546 adapter->link_speed = 0;
547 adapter->link_duplex = 0;
548 netif_carrier_off(netdev);
549 netif_stop_queue(netdev);
550
551 e1000_reset(adapter);
581d708e
MC		 552 e1000_clean_all_tx_rings(adapter);
553 e1000_clean_all_rx_rings(adapter);
1da177e4 554
57128197
JK		 555 /* Power down the PHY so no link is implied when interface is down *
556 * The PHY cannot be powered down if any of the following is TRUE *
557 * (a) WoL is enabled
558 * (b) AMT is active
559 * (c) SoL/IDER session is active */
560 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 561 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 562 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
563 !mng_mode_enabled &&
564 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 565 uint16_t mii_reg;
566 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
567 mii_reg |= MII_CR_POWER_DOWN;
568 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 569 mdelay(1);
1da177e4
LT		 570 }
571}
572
573void
574e1000_reset(struct e1000_adapter *adapter)
575{
2d7edb92 576 uint32_t pba, manc;
1125ecbc 577 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 578
579 /* Repartition Pba for greater than 9k mtu
580 * To take effect CTRL.RST is required.
581 */
582
2d7edb92
MC		 583 switch (adapter->hw.mac_type) {
584 case e1000_82547:
0e6ef3e0 585 case e1000_82547_rev_2:
2d7edb92
MC		 586 pba = E1000_PBA_30K;
587 break;
868d5309
MC		 588 case e1000_82571:
589 case e1000_82572:
590 pba = E1000_PBA_38K;
591 break;
2d7edb92
MC		 592 case e1000_82573:
593 pba = E1000_PBA_12K;
594 break;
595 default:
596 pba = E1000_PBA_48K;
597 break;
598 }
599
96838a40 600 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 601 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 602 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 603
604
96838a40 605 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 606 adapter->tx_fifo_head = 0;
607 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
608 adapter->tx_fifo_size =
609 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
610 atomic_set(&adapter->tx_fifo_stall, 0);
611 }
2d7edb92 612
1da177e4
LT		 613 E1000_WRITE_REG(&adapter->hw, PBA, pba);
614
615 /* flow control settings */
f11b7f85
JK		 616 /* Set the FC high water mark to 90% of the FIFO size.
617 * Required to clear last 3 LSB */
618 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
619
620 adapter->hw.fc_high_water = fc_high_water_mark;
621 adapter->hw.fc_low_water = fc_high_water_mark - 8;
1da177e4
LT		 622 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
623 adapter->hw.fc_send_xon = 1;
624 adapter->hw.fc = adapter->hw.original_fc;
625
2d7edb92 626 /* Allow time for pending master requests to run */
1da177e4 627 e1000_reset_hw(&adapter->hw);
96838a40 628 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 629 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 630 if (e1000_init_hw(&adapter->hw))
1da177e4 631 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 632 e1000_update_mng_vlan(adapter);
1da177e4
LT		 633 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
634 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
635
636 e1000_reset_adaptive(&adapter->hw);
637 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 638 if (adapter->en_mng_pt) {
639 manc = E1000_READ_REG(&adapter->hw, MANC);
640 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
641 E1000_WRITE_REG(&adapter->hw, MANC, manc);
642 }
1da177e4
LT		 643}
644
645/**
646 * e1000_probe - Device Initialization Routine
647 * @pdev: PCI device information struct
648 * @ent: entry in e1000_pci_tbl
649 *
650 * Returns 0 on success, negative on failure
651 *
652 * e1000_probe initializes an adapter identified by a pci_dev structure.
653 * The OS initialization, configuring of the adapter private structure,
654 * and a hardware reset occur.
655 **/
656
657static int __devinit
658e1000_probe(struct pci_dev *pdev,
659 const struct pci_device_id *ent)
660{
661 struct net_device *netdev;
662 struct e1000_adapter *adapter;
2d7edb92 663 unsigned long mmio_start, mmio_len;
2d7edb92 664
1da177e4 665 static int cards_found = 0;
2d7edb92 666 int i, err, pci_using_dac;
1da177e4
LT		 667 uint16_t eeprom_data;
668 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 669 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 670 return err;
671
96838a40 672 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 673 pci_using_dac = 1;
674 } else {
96838a40 675 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 676 E1000_ERR("No usable DMA configuration, aborting\n");
677 return err;
678 }
679 pci_using_dac = 0;
680 }
681
96838a40 682 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 683 return err;
684
685 pci_set_master(pdev);
686
687 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 688 if (!netdev) {
1da177e4
LT		 689 err = -ENOMEM;
690 goto err_alloc_etherdev;
691 }
692
693 SET_MODULE_OWNER(netdev);
694 SET_NETDEV_DEV(netdev, &pdev->dev);
695
696 pci_set_drvdata(pdev, netdev);
60490fe0 697 adapter = netdev_priv(netdev);
1da177e4
LT		 698 adapter->netdev = netdev;
699 adapter->pdev = pdev;
700 adapter->hw.back = adapter;
701 adapter->msg_enable = (1 << debug) - 1;
702
703 mmio_start = pci_resource_start(pdev, BAR_0);
704 mmio_len = pci_resource_len(pdev, BAR_0);
705
706 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 707 if (!adapter->hw.hw_addr) {
1da177e4
LT		 708 err = -EIO;
709 goto err_ioremap;
710 }
711
96838a40
JB		 712 for (i = BAR_1; i <= BAR_5; i++) {
713 if (pci_resource_len(pdev, i) == 0)
1da177e4 714 continue;
96838a40 715 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 716 adapter->hw.io_base = pci_resource_start(pdev, i);
717 break;
718 }
719 }
720
721 netdev->open = &e1000_open;
722 netdev->stop = &e1000_close;
723 netdev->hard_start_xmit = &e1000_xmit_frame;
724 netdev->get_stats = &e1000_get_stats;
725 netdev->set_multicast_list = &e1000_set_multi;
726 netdev->set_mac_address = &e1000_set_mac;
727 netdev->change_mtu = &e1000_change_mtu;
728 netdev->do_ioctl = &e1000_ioctl;
729 e1000_set_ethtool_ops(netdev);
730 netdev->tx_timeout = &e1000_tx_timeout;
731 netdev->watchdog_timeo = 5 * HZ;
732#ifdef CONFIG_E1000_NAPI
733 netdev->poll = &e1000_clean;
734 netdev->weight = 64;
735#endif
736 netdev->vlan_rx_register = e1000_vlan_rx_register;
737 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
738 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
739#ifdef CONFIG_NET_POLL_CONTROLLER
740 netdev->poll_controller = e1000_netpoll;
741#endif
742 strcpy(netdev->name, pci_name(pdev));
743
744 netdev->mem_start = mmio_start;
745 netdev->mem_end = mmio_start + mmio_len;
746 netdev->base_addr = adapter->hw.io_base;
747
748 adapter->bd_number = cards_found;
749
750 /* setup the private structure */
751
96838a40 752 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 753 goto err_sw_init;
754
96838a40 755 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 756 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
757
96838a40 758 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 759 netdev->features = NETIF_F_SG |
760 NETIF_F_HW_CSUM |
761 NETIF_F_HW_VLAN_TX |
762 NETIF_F_HW_VLAN_RX |
763 NETIF_F_HW_VLAN_FILTER;
764 }
765
766#ifdef NETIF_F_TSO
96838a40 767 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 768 (adapter->hw.mac_type != e1000_82547))
769 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 770
771#ifdef NETIF_F_TSO_IPV6
96838a40 772 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 773 netdev->features |= NETIF_F_TSO_IPV6;
774#endif
1da177e4 775#endif
96838a40 776 if (pci_using_dac)
1da177e4
LT		 777 netdev->features |= NETIF_F_HIGHDMA;
778
779 /* hard_start_xmit is safe against parallel locking */
780 netdev->features |= NETIF_F_LLTX;
781
2d7edb92
MC		 782 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
783
96838a40 784 /* before reading the EEPROM, reset the controller to
1da177e4 785 * put the device in a known good starting state */
96838a40 786
1da177e4
LT		 787 e1000_reset_hw(&adapter->hw);
788
789 /* make sure the EEPROM is good */
790
96838a40 791 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 792 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
793 err = -EIO;
794 goto err_eeprom;
795 }
796
797 /* copy the MAC address out of the EEPROM */
798
96838a40 799 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 800 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
801 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 802 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 803
96838a40 804 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 805 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
806 err = -EIO;
807 goto err_eeprom;
808 }
809
810 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
811
812 e1000_get_bus_info(&adapter->hw);
813
814 init_timer(&adapter->tx_fifo_stall_timer);
815 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
816 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
817
818 init_timer(&adapter->watchdog_timer);
819 adapter->watchdog_timer.function = &e1000_watchdog;
820 adapter->watchdog_timer.data = (unsigned long) adapter;
821
822 INIT_WORK(&adapter->watchdog_task,
823 (void (*)(void *))e1000_watchdog_task, adapter);
824
825 init_timer(&adapter->phy_info_timer);
826 adapter->phy_info_timer.function = &e1000_update_phy_info;
827 adapter->phy_info_timer.data = (unsigned long) adapter;
828
829 INIT_WORK(&adapter->tx_timeout_task,
830 (void (*)(void *))e1000_tx_timeout_task, netdev);
831
832 /* we're going to reset, so assume we have no link for now */
833
834 netif_carrier_off(netdev);
835 netif_stop_queue(netdev);
836
837 e1000_check_options(adapter);
838
839 /* Initial Wake on LAN setting
840 * If APM wake is enabled in the EEPROM,
841 * enable the ACPI Magic Packet filter
842 */
843
96838a40 844 switch (adapter->hw.mac_type) {
1da177e4
LT		 845 case e1000_82542_rev2_0:
846 case e1000_82542_rev2_1:
847 case e1000_82543:
848 break;
849 case e1000_82544:
850 e1000_read_eeprom(&adapter->hw,
851 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
852 eeprom_apme_mask = E1000_EEPROM_82544_APM;
853 break;
854 case e1000_82546:
855 case e1000_82546_rev_3:
fd803241 856 case e1000_82571:
96838a40 857 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 858 e1000_read_eeprom(&adapter->hw,
859 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
860 break;
861 }
862 /* Fall Through */
863 default:
864 e1000_read_eeprom(&adapter->hw,
865 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
866 break;
867 }
96838a40 868 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 869 adapter->wol |= E1000_WUFC_MAG;
870
fb3d47d4
JK		 871 /* print bus type/speed/width info */
872 {
873 struct e1000_hw *hw = &adapter->hw;
874 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
875 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
876 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
877 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
878 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
879 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
880 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
881 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
882 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
883 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
884 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
885 "32-bit"));
886 }
887
888 for (i = 0; i < 6; i++)
889 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
890
1da177e4
LT		 891 /* reset the hardware with the new settings */
892 e1000_reset(adapter);
893
b55ccb35
JK		 894 /* If the controller is 82573 and f/w is AMT, do not set
895 * DRV_LOAD until the interface is up. For all other cases,
896 * let the f/w know that the h/w is now under the control
897 * of the driver. */
898 if (adapter->hw.mac_type != e1000_82573 ||
899 !e1000_check_mng_mode(&adapter->hw))
900 e1000_get_hw_control(adapter);
2d7edb92 901
1da177e4 902 strcpy(netdev->name, "eth%d");
96838a40 903 if ((err = register_netdev(netdev)))
1da177e4
LT		 904 goto err_register;
905
906 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
907
908 cards_found++;
909 return 0;
910
911err_register:
912err_sw_init:
913err_eeprom:
914 iounmap(adapter->hw.hw_addr);
915err_ioremap:
916 free_netdev(netdev);
917err_alloc_etherdev:
918 pci_release_regions(pdev);
919 return err;
920}
921
922/**
923 * e1000_remove - Device Removal Routine
924 * @pdev: PCI device information struct
925 *
926 * e1000_remove is called by the PCI subsystem to alert the driver
927 * that it should release a PCI device. The could be caused by a
928 * Hot-Plug event, or because the driver is going to be removed from
929 * memory.
930 **/
931
932static void __devexit
933e1000_remove(struct pci_dev *pdev)
934{
935 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 936 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 937 uint32_t manc;
581d708e
MC		 938#ifdef CONFIG_E1000_NAPI
939 int i;
940#endif
1da177e4 941
be2b28ed
JG		 942 flush_scheduled_work();
943
96838a40 944 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 945 adapter->hw.media_type == e1000_media_type_copper) {
946 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 947 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 948 manc |= E1000_MANC_ARP_EN;
949 E1000_WRITE_REG(&adapter->hw, MANC, manc);
950 }
951 }
952
b55ccb35
JK		 953 /* Release control of h/w to f/w. If f/w is AMT enabled, this
954 * would have already happened in close and is redundant. */
955 e1000_release_hw_control(adapter);
2d7edb92 956
1da177e4 957 unregister_netdev(netdev);
581d708e 958#ifdef CONFIG_E1000_NAPI
f56799ea 959 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 960 __dev_put(&adapter->polling_netdev[i]);
961#endif
1da177e4 962
96838a40 963 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 964 e1000_phy_hw_reset(&adapter->hw);
1da177e4 965
24025e4e
MC		 966 kfree(adapter->tx_ring);
967 kfree(adapter->rx_ring);
968#ifdef CONFIG_E1000_NAPI
969 kfree(adapter->polling_netdev);
970#endif
971
1da177e4
LT		 972 iounmap(adapter->hw.hw_addr);
973 pci_release_regions(pdev);
974
24025e4e
MC		 975#ifdef CONFIG_E1000_MQ
976 free_percpu(adapter->cpu_netdev);
977 free_percpu(adapter->cpu_tx_ring);
978#endif
1da177e4
LT		 979 free_netdev(netdev);
980
981 pci_disable_device(pdev);
982}
983
984/**
985 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
986 * @adapter: board private structure to initialize
987 *
988 * e1000_sw_init initializes the Adapter private data structure.
989 * Fields are initialized based on PCI device information and
990 * OS network device settings (MTU size).
991 **/
992
993static int __devinit
994e1000_sw_init(struct e1000_adapter *adapter)
995{
996 struct e1000_hw *hw = &adapter->hw;
997 struct net_device *netdev = adapter->netdev;
998 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 999#ifdef CONFIG_E1000_NAPI
1000 int i;
1001#endif
1da177e4
LT		 1002
1003 /* PCI config space info */
1004
1005 hw->vendor_id = pdev->vendor;
1006 hw->device_id = pdev->device;
1007 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1008 hw->subsystem_id = pdev->subsystem_device;
1009
1010 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1011
1012 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1013
1014 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 1015 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 1016 hw->max_frame_size = netdev->mtu +
1017 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1018 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1019
1020 /* identify the MAC */
1021
96838a40 1022 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1023 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1024 return -EIO;
1025 }
1026
1027 /* initialize eeprom parameters */
1028
96838a40 1029 if (e1000_init_eeprom_params(hw)) {
2d7edb92
MC		 1030 E1000_ERR("EEPROM initialization failed\n");
1031 return -EIO;
1032 }
1da177e4 1033
96838a40 1034 switch (hw->mac_type) {
1da177e4
LT		 1035 default:
1036 break;
1037 case e1000_82541:
1038 case e1000_82547:
1039 case e1000_82541_rev_2:
1040 case e1000_82547_rev_2:
1041 hw->phy_init_script = 1;
1042 break;
1043 }
1044
1045 e1000_set_media_type(hw);
1046
1047 hw->wait_autoneg_complete = FALSE;
1048 hw->tbi_compatibility_en = TRUE;
1049 hw->adaptive_ifs = TRUE;
1050
1051 /* Copper options */
1052
96838a40 1053 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1054 hw->mdix = AUTO_ALL_MODES;
1055 hw->disable_polarity_correction = FALSE;
1056 hw->master_slave = E1000_MASTER_SLAVE;
1057 }
1058
24025e4e
MC		 1059#ifdef CONFIG_E1000_MQ
1060 /* Number of supported queues */
1061 switch (hw->mac_type) {
1062 case e1000_82571:
1063 case e1000_82572:
f56799ea
JK		 1064 /* These controllers support 2 tx queues, but with a single
1065 * qdisc implementation, multiple tx queues aren't quite as
1066 * interesting. If we can find a logical way of mapping
1067 * flows to a queue, then perhaps we can up the num_tx_queue
1068 * count back to its default. Until then, we run the risk of
1069 * terrible performance due to SACK overload. */
1070 adapter->num_tx_queues = 1;
1071 adapter->num_rx_queues = 2;
24025e4e
MC		 1072 break;
1073 default:
f56799ea
JK		 1074 adapter->num_tx_queues = 1;
1075 adapter->num_rx_queues = 1;
24025e4e
MC		 1076 break;
1077 }
f56799ea
JK		 1078 adapter->num_rx_queues = min(adapter->num_rx_queues, num_online_cpus());
1079 adapter->num_tx_queues = min(adapter->num_tx_queues, num_online_cpus());
7bfa4816
JK		 1080 DPRINTK(DRV, INFO, "Multiqueue Enabled: Rx Queue count = %u %s\n",
1081 adapter->num_rx_queues,
1082 ((adapter->num_rx_queues == 1)
1083 ? ((num_online_cpus() > 1)
1084 ? "(due to unsupported feature in current adapter)"
1085 : "(due to unsupported system configuration)")
1086 : ""));
1087 DPRINTK(DRV, INFO, "Multiqueue Enabled: Tx Queue count = %u\n",
1088 adapter->num_tx_queues);
24025e4e 1089#else
f56799ea
JK		 1090 adapter->num_tx_queues = 1;
1091 adapter->num_rx_queues = 1;
24025e4e 1092#endif
581d708e
MC		 1093
1094 if (e1000_alloc_queues(adapter)) {
1095 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1096 return -ENOMEM;
1097 }
1098
1099#ifdef CONFIG_E1000_NAPI
f56799ea 1100 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1101 adapter->polling_netdev[i].priv = adapter;
1102 adapter->polling_netdev[i].poll = &e1000_clean;
1103 adapter->polling_netdev[i].weight = 64;
1104 dev_hold(&adapter->polling_netdev[i]);
1105 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1106 }
7bfa4816 1107 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1108#endif
1109
1da177e4
LT		 1110 atomic_set(&adapter->irq_sem, 1);
1111 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1112
1113 return 0;
1114}
1115
581d708e
MC		 1116/**
1117 * e1000_alloc_queues - Allocate memory for all rings
1118 * @adapter: board private structure to initialize
1119 *
1120 * We allocate one ring per queue at run-time since we don't know the
1121 * number of queues at compile-time. The polling_netdev array is
1122 * intended for Multiqueue, but should work fine with a single queue.
1123 **/
1124
1125static int __devinit
1126e1000_alloc_queues(struct e1000_adapter *adapter)
1127{
1128 int size;
1129
f56799ea 1130 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1131 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1132 if (!adapter->tx_ring)
1133 return -ENOMEM;
1134 memset(adapter->tx_ring, 0, size);
1135
f56799ea 1136 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1137 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1138 if (!adapter->rx_ring) {
1139 kfree(adapter->tx_ring);
1140 return -ENOMEM;
1141 }
1142 memset(adapter->rx_ring, 0, size);
1143
1144#ifdef CONFIG_E1000_NAPI
f56799ea 1145 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1146 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1147 if (!adapter->polling_netdev) {
1148 kfree(adapter->tx_ring);
1149 kfree(adapter->rx_ring);
1150 return -ENOMEM;
1151 }
1152 memset(adapter->polling_netdev, 0, size);
1153#endif
1154
7bfa4816
JK		 1155#ifdef CONFIG_E1000_MQ
1156 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1157 adapter->rx_sched_call_data.info = adapter->netdev;
1158
1159 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1160 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1161#endif
1162
581d708e
MC		 1163 return E1000_SUCCESS;
1164}
1165
24025e4e
MC		 1166#ifdef CONFIG_E1000_MQ
1167static void __devinit
1168e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1169{
1170 int i, cpu;
1171
1172 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1173 adapter->rx_sched_call_data.info = adapter->netdev;
1174 cpus_clear(adapter->rx_sched_call_data.cpumask);
1175
1176 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1177 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1178
1179 lock_cpu_hotplug();
1180 i = 0;
1181 for_each_online_cpu(cpu) {
f56799ea 1182 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_tx_queues];
24025e4e
MC		 1183 /* This is incomplete because we'd like to assign separate
1184 * physical cpus to these netdev polling structures and
1185 * avoid saturating a subset of cpus.
1186 */
f56799ea 1187 if (i < adapter->num_rx_queues) {
24025e4e 1188 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
7bfa4816
JK		 1189 adapter->rx_ring[i].cpu = cpu;
1190 cpu_set(cpu, adapter->cpumask);
24025e4e
MC		 1191 } else
1192 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1193
1194 i++;
1195 }
1196 unlock_cpu_hotplug();
1197}
1198#endif
1199
1da177e4
LT		 1200/**
1201 * e1000_open - Called when a network interface is made active
1202 * @netdev: network interface device structure
1203 *
1204 * Returns 0 on success, negative value on failure
1205 *
1206 * The open entry point is called when a network interface is made
1207 * active by the system (IFF_UP). At this point all resources needed
1208 * for transmit and receive operations are allocated, the interrupt
1209 * handler is registered with the OS, the watchdog timer is started,
1210 * and the stack is notified that the interface is ready.
1211 **/
1212
1213static int
1214e1000_open(struct net_device *netdev)
1215{
60490fe0 1216 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1217 int err;
1218
1219 /* allocate transmit descriptors */
1220
581d708e 1221 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1222 goto err_setup_tx;
1223
1224 /* allocate receive descriptors */
1225
581d708e 1226 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1227 goto err_setup_rx;
1228
96838a40 1229 if ((err = e1000_up(adapter)))
1da177e4 1230 goto err_up;
2d7edb92 1231 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1232 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1233 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1234 e1000_update_mng_vlan(adapter);
1235 }
1da177e4 1236
b55ccb35
JK		 1237 /* If AMT is enabled, let the firmware know that the network
1238 * interface is now open */
1239 if (adapter->hw.mac_type == e1000_82573 &&
1240 e1000_check_mng_mode(&adapter->hw))
1241 e1000_get_hw_control(adapter);
1242
1da177e4
LT		 1243 return E1000_SUCCESS;
1244
1245err_up:
581d708e 1246 e1000_free_all_rx_resources(adapter);
1da177e4 1247err_setup_rx:
581d708e 1248 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1249err_setup_tx:
1250 e1000_reset(adapter);
1251
1252 return err;
1253}
1254
1255/**
1256 * e1000_close - Disables a network interface
1257 * @netdev: network interface device structure
1258 *
1259 * Returns 0, this is not allowed to fail
1260 *
1261 * The close entry point is called when an interface is de-activated
1262 * by the OS. The hardware is still under the drivers control, but
1263 * needs to be disabled. A global MAC reset is issued to stop the
1264 * hardware, and all transmit and receive resources are freed.
1265 **/
1266
1267static int
1268e1000_close(struct net_device *netdev)
1269{
60490fe0 1270 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1271
1272 e1000_down(adapter);
1273
581d708e
MC		 1274 e1000_free_all_tx_resources(adapter);
1275 e1000_free_all_rx_resources(adapter);
1da177e4 1276
96838a40 1277 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1278 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1279 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1280 }
b55ccb35
JK		 1281
1282 /* If AMT is enabled, let the firmware know that the network
1283 * interface is now closed */
1284 if (adapter->hw.mac_type == e1000_82573 &&
1285 e1000_check_mng_mode(&adapter->hw))
1286 e1000_release_hw_control(adapter);
1287
1da177e4
LT		 1288 return 0;
1289}
1290
1291/**
1292 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1293 * @adapter: address of board private structure
2d7edb92
MC		 1294 * @start: address of beginning of memory
1295 * @len: length of memory
1da177e4
LT		 1296 **/
1297static inline boolean_t
1298e1000_check_64k_bound(struct e1000_adapter *adapter,
1299 void *start, unsigned long len)
1300{
1301 unsigned long begin = (unsigned long) start;
1302 unsigned long end = begin + len;
1303
2648345f
MC		 1304 /* First rev 82545 and 82546 need to not allow any memory
1305 * write location to cross 64k boundary due to errata 23 */
1da177e4 1306 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1307 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1308 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1309 }
1310
1311 return TRUE;
1312}
1313
1314/**
1315 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1316 * @adapter: board private structure
581d708e 1317 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1318 *
1319 * Return 0 on success, negative on failure
1320 **/
1321
3ad2cc67 1322static int
581d708e
MC		 1323e1000_setup_tx_resources(struct e1000_adapter *adapter,
1324 struct e1000_tx_ring *txdr)
1da177e4 1325{
1da177e4
LT		 1326 struct pci_dev *pdev = adapter->pdev;
1327 int size;
1328
1329 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1330
1331 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
96838a40 1332 if (!txdr->buffer_info) {
2648345f
MC		 1333 DPRINTK(PROBE, ERR,
1334 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1335 return -ENOMEM;
1336 }
1337 memset(txdr->buffer_info, 0, size);
1338
1339 /* round up to nearest 4K */
1340
1341 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1342 E1000_ROUNDUP(txdr->size, 4096);
1343
1344 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1345 if (!txdr->desc) {
1da177e4 1346setup_tx_desc_die:
1da177e4 1347 vfree(txdr->buffer_info);
2648345f
MC		 1348 DPRINTK(PROBE, ERR,
1349 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1350 return -ENOMEM;
1351 }
1352
2648345f 1353 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1354 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1355 void *olddesc = txdr->desc;
1356 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1357 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1358 "at %p\n", txdr->size, txdr->desc);
1359 /* Try again, without freeing the previous */
1da177e4 1360 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1361 /* Failed allocation, critical failure */
96838a40 1362 if (!txdr->desc) {
1da177e4
LT		 1363 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1364 goto setup_tx_desc_die;
1365 }
1366
1367 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1368 /* give up */
2648345f
MC		 1369 pci_free_consistent(pdev, txdr->size, txdr->desc,
1370 txdr->dma);
1da177e4
LT		 1371 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1372 DPRINTK(PROBE, ERR,
2648345f
MC		 1373 "Unable to allocate aligned memory "
1374 "for the transmit descriptor ring\n");
1da177e4
LT		 1375 vfree(txdr->buffer_info);
1376 return -ENOMEM;
1377 } else {
2648345f 1378 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1379 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1380 }
1381 }
1382 memset(txdr->desc, 0, txdr->size);
1383
1384 txdr->next_to_use = 0;
1385 txdr->next_to_clean = 0;
2ae76d98 1386 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1387
1388 return 0;
1389}
1390
581d708e
MC		 1391/**
1392 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1393 * (Descriptors) for all queues
1394 * @adapter: board private structure
1395 *
1396 * If this function returns with an error, then it's possible one or
1397 * more of the rings is populated (while the rest are not). It is the
1398 * callers duty to clean those orphaned rings.
1399 *
1400 * Return 0 on success, negative on failure
1401 **/
1402
1403int
1404e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1405{
1406 int i, err = 0;
1407
f56799ea 1408 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1409 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1410 if (err) {
1411 DPRINTK(PROBE, ERR,
1412 "Allocation for Tx Queue %u failed\n", i);
1413 break;
1414 }
1415 }
1416
1417 return err;
1418}
1419
1da177e4
LT		 1420/**
1421 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1422 * @adapter: board private structure
1423 *
1424 * Configure the Tx unit of the MAC after a reset.
1425 **/
1426
1427static void
1428e1000_configure_tx(struct e1000_adapter *adapter)
1429{
581d708e
MC		 1430 uint64_t tdba;
1431 struct e1000_hw *hw = &adapter->hw;
1432 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1433 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1434
1435 /* Setup the HW Tx Head and Tail descriptor pointers */
1436
f56799ea 1437 switch (adapter->num_tx_queues) {
24025e4e
MC		 1438 case 2:
1439 tdba = adapter->tx_ring[1].dma;
1440 tdlen = adapter->tx_ring[1].count *
1441 sizeof(struct e1000_tx_desc);
1442 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1443 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1444 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1445 E1000_WRITE_REG(hw, TDH1, 0);
1446 E1000_WRITE_REG(hw, TDT1, 0);
1447 adapter->tx_ring[1].tdh = E1000_TDH1;
1448 adapter->tx_ring[1].tdt = E1000_TDT1;
1449 /* Fall Through */
1450 case 1:
1451 default:
581d708e
MC		 1452 tdba = adapter->tx_ring[0].dma;
1453 tdlen = adapter->tx_ring[0].count *
1454 sizeof(struct e1000_tx_desc);
1455 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1456 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1457 E1000_WRITE_REG(hw, TDLEN, tdlen);
1458 E1000_WRITE_REG(hw, TDH, 0);
1459 E1000_WRITE_REG(hw, TDT, 0);
1460 adapter->tx_ring[0].tdh = E1000_TDH;
1461 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1462 break;
1463 }
1da177e4
LT		 1464
1465 /* Set the default values for the Tx Inter Packet Gap timer */
1466
0fadb059
JK		 1467 if (hw->media_type == e1000_media_type_fiber ||
1468 hw->media_type == e1000_media_type_internal_serdes)
1469 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1470 else
1471 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1472
581d708e 1473 switch (hw->mac_type) {
1da177e4
LT		 1474 case e1000_82542_rev2_0:
1475 case e1000_82542_rev2_1:
1476 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1477 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1478 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4
LT		 1479 break;
1480 default:
0fadb059
JK		 1481 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1482 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1483 break;
1da177e4 1484 }
0fadb059
JK		 1485 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1486 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1487 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1488
1489 /* Set the Tx Interrupt Delay register */
1490
581d708e
MC		 1491 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1492 if (hw->mac_type >= e1000_82540)
1493 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1494
1495 /* Program the Transmit Control Register */
1496
581d708e 1497 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1498
1499 tctl &= ~E1000_TCTL_CT;
24025e4e 1500 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1501 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1502
581d708e 1503 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1504
2ae76d98
MC		 1505 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1506 tarc = E1000_READ_REG(hw, TARC0);
1507 tarc |= ((1 << 25) | (1 << 21));
1508 E1000_WRITE_REG(hw, TARC0, tarc);
1509 tarc = E1000_READ_REG(hw, TARC1);
1510 tarc |= (1 << 25);
1511 if (tctl & E1000_TCTL_MULR)
1512 tarc &= ~(1 << 28);
1513 else
1514 tarc |= (1 << 28);
1515 E1000_WRITE_REG(hw, TARC1, tarc);
1516 }
1517
581d708e 1518 e1000_config_collision_dist(hw);
1da177e4
LT		 1519
1520 /* Setup Transmit Descriptor Settings for eop descriptor */
1521 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1522 E1000_TXD_CMD_IFCS;
1523
581d708e 1524 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1525 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1526 else
1527 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1528
1529 /* Cache if we're 82544 running in PCI-X because we'll
1530 * need this to apply a workaround later in the send path. */
581d708e
MC		 1531 if (hw->mac_type == e1000_82544 &&
1532 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1533 adapter->pcix_82544 = 1;
1534}
1535
1536/**
1537 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1538 * @adapter: board private structure
581d708e 1539 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1540 *
1541 * Returns 0 on success, negative on failure
1542 **/
1543
3ad2cc67 1544static int
581d708e
MC		 1545e1000_setup_rx_resources(struct e1000_adapter *adapter,
1546 struct e1000_rx_ring *rxdr)
1da177e4 1547{
1da177e4 1548 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1549 int size, desc_len;
1da177e4
LT		 1550
1551 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1552 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1553 if (!rxdr->buffer_info) {
2648345f
MC		 1554 DPRINTK(PROBE, ERR,
1555 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1556 return -ENOMEM;
1557 }
1558 memset(rxdr->buffer_info, 0, size);
1559
2d7edb92
MC		 1560 size = sizeof(struct e1000_ps_page) * rxdr->count;
1561 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1562 if (!rxdr->ps_page) {
2d7edb92
MC		 1563 vfree(rxdr->buffer_info);
1564 DPRINTK(PROBE, ERR,
1565 "Unable to allocate memory for the receive descriptor ring\n");
1566 return -ENOMEM;
1567 }
1568 memset(rxdr->ps_page, 0, size);
1569
1570 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1571 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1572 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1573 vfree(rxdr->buffer_info);
1574 kfree(rxdr->ps_page);
1575 DPRINTK(PROBE, ERR,
1576 "Unable to allocate memory for the receive descriptor ring\n");
1577 return -ENOMEM;
1578 }
1579 memset(rxdr->ps_page_dma, 0, size);
1580
96838a40 1581 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1582 desc_len = sizeof(struct e1000_rx_desc);
1583 else
1584 desc_len = sizeof(union e1000_rx_desc_packet_split);
1585
1da177e4
LT		 1586 /* Round up to nearest 4K */
1587
2d7edb92 1588 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1589 E1000_ROUNDUP(rxdr->size, 4096);
1590
1591 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1592
581d708e
MC		 1593 if (!rxdr->desc) {
1594 DPRINTK(PROBE, ERR,
1595 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1596setup_rx_desc_die:
1da177e4 1597 vfree(rxdr->buffer_info);
2d7edb92
MC		 1598 kfree(rxdr->ps_page);
1599 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1600 return -ENOMEM;
1601 }
1602
2648345f 1603 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1604 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1605 void *olddesc = rxdr->desc;
1606 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1607 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1608 "at %p\n", rxdr->size, rxdr->desc);
1609 /* Try again, without freeing the previous */
1da177e4 1610 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1611 /* Failed allocation, critical failure */
581d708e 1612 if (!rxdr->desc) {
1da177e4 1613 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1614 DPRINTK(PROBE, ERR,
1615 "Unable to allocate memory "
1616 "for the receive descriptor ring\n");
1da177e4
LT		 1617 goto setup_rx_desc_die;
1618 }
1619
1620 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1621 /* give up */
2648345f
MC		 1622 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1623 rxdr->dma);
1da177e4 1624 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1625 DPRINTK(PROBE, ERR,
1626 "Unable to allocate aligned memory "
1627 "for the receive descriptor ring\n");
581d708e 1628 goto setup_rx_desc_die;
1da177e4 1629 } else {
2648345f 1630 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1631 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1632 }
1633 }
1634 memset(rxdr->desc, 0, rxdr->size);
1635
1636 rxdr->next_to_clean = 0;
1637 rxdr->next_to_use = 0;
997f5cbd
JK		 1638 rxdr->rx_skb_top = NULL;
1639 rxdr->rx_skb_prev = NULL;
1da177e4
LT		 1640
1641 return 0;
1642}
1643
581d708e
MC		 1644/**
1645 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1646 * (Descriptors) for all queues
1647 * @adapter: board private structure
1648 *
1649 * If this function returns with an error, then it's possible one or
1650 * more of the rings is populated (while the rest are not). It is the
1651 * callers duty to clean those orphaned rings.
1652 *
1653 * Return 0 on success, negative on failure
1654 **/
1655
1656int
1657e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1658{
1659 int i, err = 0;
1660
f56799ea 1661 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1662 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1663 if (err) {
1664 DPRINTK(PROBE, ERR,
1665 "Allocation for Rx Queue %u failed\n", i);
1666 break;
1667 }
1668 }
1669
1670 return err;
1671}
1672
1da177e4 1673/**
2648345f 1674 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1675 * @adapter: Board private structure
1676 **/
e4c811c9
MC		 1677#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1678 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1679static void
1680e1000_setup_rctl(struct e1000_adapter *adapter)
1681{
2d7edb92
MC		 1682 uint32_t rctl, rfctl;
1683 uint32_t psrctl = 0;
35ec56bb 1684#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1685 uint32_t pages = 0;
1686#endif
1da177e4
LT		 1687
1688 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1689
1690 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1691
1692 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1693 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1694 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1695
0fadb059
JK		 1696 if (adapter->hw.mac_type > e1000_82543)
1697 rctl |= E1000_RCTL_SECRC;
1698
1699 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1700 rctl |= E1000_RCTL_SBP;
1701 else
1702 rctl &= ~E1000_RCTL_SBP;
1703
2d7edb92
MC		 1704 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1705 rctl &= ~E1000_RCTL_LPE;
1706 else
1707 rctl |= E1000_RCTL_LPE;
1708
1da177e4 1709 /* Setup buffer sizes */
96838a40 1710 if (adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1711 /* We can now specify buffers in 1K increments.
1712 * BSIZE and BSEX are ignored in this case. */
1713 rctl |= adapter->rx_buffer_len << 0x11;
1714 } else {
1715 rctl &= ~E1000_RCTL_SZ_4096;
b92ff8ee
JB		 1716 rctl &= ~E1000_RCTL_BSEX;
1717 rctl |= E1000_RCTL_SZ_2048;
2d7edb92
MC		 1718 }
1719
35ec56bb 1720#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1721 /* 82571 and greater support packet-split where the protocol
1722 * header is placed in skb->data and the packet data is
1723 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1724 * In the case of a non-split, skb->data is linearly filled,
1725 * followed by the page buffers. Therefore, skb->data is
1726 * sized to hold the largest protocol header.
1727 */
e4c811c9
MC		 1728 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1729 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1730 PAGE_SIZE <= 16384)
1731 adapter->rx_ps_pages = pages;
1732 else
1733 adapter->rx_ps_pages = 0;
2d7edb92 1734#endif
e4c811c9 1735 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1736 /* Configure extra packet-split registers */
1737 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1738 rfctl |= E1000_RFCTL_EXTEN;
1739 /* disable IPv6 packet split support */
1740 rfctl |= E1000_RFCTL_IPV6_DIS;
1741 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1742
1743 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
96838a40 1744
2d7edb92
MC		 1745 psrctl |= adapter->rx_ps_bsize0 >>
1746 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1747
1748 switch (adapter->rx_ps_pages) {
1749 case 3:
1750 psrctl |= PAGE_SIZE <<
1751 E1000_PSRCTL_BSIZE3_SHIFT;
1752 case 2:
1753 psrctl |= PAGE_SIZE <<
1754 E1000_PSRCTL_BSIZE2_SHIFT;
1755 case 1:
1756 psrctl |= PAGE_SIZE >>
1757 E1000_PSRCTL_BSIZE1_SHIFT;
1758 break;
1759 }
2d7edb92
MC		 1760
1761 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1762 }
1763
1764 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1765}
1766
1767/**
1768 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1769 * @adapter: board private structure
1770 *
1771 * Configure the Rx unit of the MAC after a reset.
1772 **/
1773
1774static void
1775e1000_configure_rx(struct e1000_adapter *adapter)
1776{
581d708e
MC		 1777 uint64_t rdba;
1778 struct e1000_hw *hw = &adapter->hw;
1779 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1780#ifdef CONFIG_E1000_MQ
1781 uint32_t reta, mrqc;
1782 int i;
1783#endif
2d7edb92 1784
e4c811c9 1785 if (adapter->rx_ps_pages) {
581d708e 1786 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1787 sizeof(union e1000_rx_desc_packet_split);
1788 adapter->clean_rx = e1000_clean_rx_irq_ps;
1789 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1790 } else {
581d708e
MC		 1791 rdlen = adapter->rx_ring[0].count *
1792 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1793 adapter->clean_rx = e1000_clean_rx_irq;
1794 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1795 }
1da177e4
LT		 1796
1797 /* disable receives while setting up the descriptors */
581d708e
MC		 1798 rctl = E1000_READ_REG(hw, RCTL);
1799 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1800
1801 /* set the Receive Delay Timer Register */
581d708e 1802 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1803
581d708e
MC		 1804 if (hw->mac_type >= e1000_82540) {
1805 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1806 if (adapter->itr > 1)
581d708e 1807 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1808 1000000000 / (adapter->itr * 256));
1809 }
1810
2ae76d98 1811 if (hw->mac_type >= e1000_82571) {
2ae76d98 1812 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1813 /* Reset delay timers after every interrupt */
2ae76d98 1814 ctrl_ext |= E1000_CTRL_EXT_CANC;
1e613fd9
JK		 1815#ifdef CONFIG_E1000_NAPI
1816 /* Auto-Mask interrupts upon ICR read. */
1817 ctrl_ext |= E1000_CTRL_EXT_IAME;
1818#endif
2ae76d98 1819 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1820 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1821 E1000_WRITE_FLUSH(hw);
1822 }
1823
581d708e
MC		 1824 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1825 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1826 switch (adapter->num_rx_queues) {
24025e4e
MC		 1827#ifdef CONFIG_E1000_MQ
1828 case 2:
1829 rdba = adapter->rx_ring[1].dma;
1830 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1831 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1832 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1833 E1000_WRITE_REG(hw, RDH1, 0);
1834 E1000_WRITE_REG(hw, RDT1, 0);
1835 adapter->rx_ring[1].rdh = E1000_RDH1;
1836 adapter->rx_ring[1].rdt = E1000_RDT1;
1837 /* Fall Through */
1838#endif
1839 case 1:
1840 default:
581d708e
MC		 1841 rdba = adapter->rx_ring[0].dma;
1842 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1843 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1844 E1000_WRITE_REG(hw, RDLEN, rdlen);
1845 E1000_WRITE_REG(hw, RDH, 0);
1846 E1000_WRITE_REG(hw, RDT, 0);
1847 adapter->rx_ring[0].rdh = E1000_RDH;
1848 adapter->rx_ring[0].rdt = E1000_RDT;
1849 break;
24025e4e
MC		 1850 }
1851
1852#ifdef CONFIG_E1000_MQ
f56799ea 1853 if (adapter->num_rx_queues > 1) {
24025e4e
MC		 1854 uint32_t random[10];
1855
1856 get_random_bytes(&random[0], 40);
1857
1858 if (hw->mac_type <= e1000_82572) {
1859 E1000_WRITE_REG(hw, RSSIR, 0);
1860 E1000_WRITE_REG(hw, RSSIM, 0);
1861 }
1862
f56799ea 1863 switch (adapter->num_rx_queues) {
24025e4e
MC		 1864 case 2:
1865 default:
1866 reta = 0x00800080;
1867 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1868 break;
1869 }
1870
1871 /* Fill out redirection table */
1872 for (i = 0; i < 32; i++)
1873 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1874 /* Fill out hash function seeds */
1875 for (i = 0; i < 10; i++)
1876 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1877
1878 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1879 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1880 E1000_WRITE_REG(hw, MRQC, mrqc);
1881 }
1882
1883 /* Multiqueue and packet checksumming are mutually exclusive. */
1884 if (hw->mac_type >= e1000_82571) {
1885 rxcsum = E1000_READ_REG(hw, RXCSUM);
1886 rxcsum |= E1000_RXCSUM_PCSD;
1887 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1888 }
1889
1890#else
1da177e4
LT		 1891
1892 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1893 if (hw->mac_type >= e1000_82543) {
1894 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1895 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1896 rxcsum |= E1000_RXCSUM_TUOFL;
1897
868d5309 1898 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1899 * Must be used in conjunction with packet-split. */
96838a40
JB		 1900 if ((hw->mac_type >= e1000_82571) &&
1901 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1902 rxcsum |= E1000_RXCSUM_IPPCSE;
1903 }
1904 } else {
1905 rxcsum &= ~E1000_RXCSUM_TUOFL;
1906 /* don't need to clear IPPCSE as it defaults to 0 */
1907 }
581d708e 1908 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1909 }
24025e4e 1910#endif /* CONFIG_E1000_MQ */
1da177e4 1911
581d708e
MC		 1912 if (hw->mac_type == e1000_82573)
1913 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1914
1da177e4 1915 /* Enable Receives */
581d708e 1916 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1917}
1918
1919/**
581d708e 1920 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1921 * @adapter: board private structure
581d708e 1922 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1923 *
1924 * Free all transmit software resources
1925 **/
1926
3ad2cc67 1927static void
581d708e
MC		 1928e1000_free_tx_resources(struct e1000_adapter *adapter,
1929 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1930{
1931 struct pci_dev *pdev = adapter->pdev;
1932
581d708e 1933 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1934
581d708e
MC		 1935 vfree(tx_ring->buffer_info);
1936 tx_ring->buffer_info = NULL;
1da177e4 1937
581d708e 1938 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1939
581d708e
MC		 1940 tx_ring->desc = NULL;
1941}
1942
1943/**
1944 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1945 * @adapter: board private structure
1946 *
1947 * Free all transmit software resources
1948 **/
1949
1950void
1951e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1952{
1953 int i;
1954
f56799ea 1955 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1956 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1957}
1958
1959static inline void
1960e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1961 struct e1000_buffer *buffer_info)
1962{
96838a40 1963 if (buffer_info->dma) {
2648345f
MC		 1964 pci_unmap_page(adapter->pdev,
1965 buffer_info->dma,
1966 buffer_info->length,
1967 PCI_DMA_TODEVICE);
1da177e4 1968 }
8241e35e 1969 if (buffer_info->skb)
1da177e4 1970 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1971 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1972}
1973
1974/**
1975 * e1000_clean_tx_ring - Free Tx Buffers
1976 * @adapter: board private structure
581d708e 1977 * @tx_ring: ring to be cleaned
1da177e4
LT		 1978 **/
1979
1980static void
581d708e
MC		 1981e1000_clean_tx_ring(struct e1000_adapter *adapter,
1982 struct e1000_tx_ring *tx_ring)
1da177e4 1983{
1da177e4
LT		 1984 struct e1000_buffer *buffer_info;
1985 unsigned long size;
1986 unsigned int i;
1987
1988 /* Free all the Tx ring sk_buffs */
1989
96838a40 1990 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1991 buffer_info = &tx_ring->buffer_info[i];
1992 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1993 }
1994
1995 size = sizeof(struct e1000_buffer) * tx_ring->count;
1996 memset(tx_ring->buffer_info, 0, size);
1997
1998 /* Zero out the descriptor ring */
1999
2000 memset(tx_ring->desc, 0, tx_ring->size);
2001
2002 tx_ring->next_to_use = 0;
2003 tx_ring->next_to_clean = 0;
fd803241 2004 tx_ring->last_tx_tso = 0;
1da177e4 2005
581d708e
MC		 2006 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2007 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2008}
2009
2010/**
2011 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2012 * @adapter: board private structure
2013 **/
2014
2015static void
2016e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2017{
2018 int i;
2019
f56799ea 2020 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2021 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2022}
2023
2024/**
2025 * e1000_free_rx_resources - Free Rx Resources
2026 * @adapter: board private structure
581d708e 2027 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2028 *
2029 * Free all receive software resources
2030 **/
2031
3ad2cc67 2032static void
581d708e
MC		 2033e1000_free_rx_resources(struct e1000_adapter *adapter,
2034 struct e1000_rx_ring *rx_ring)
1da177e4 2035{
1da177e4
LT		 2036 struct pci_dev *pdev = adapter->pdev;
2037
581d708e 2038 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2039
2040 vfree(rx_ring->buffer_info);
2041 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2042 kfree(rx_ring->ps_page);
2043 rx_ring->ps_page = NULL;
2044 kfree(rx_ring->ps_page_dma);
2045 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2046
2047 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2048
2049 rx_ring->desc = NULL;
2050}
2051
2052/**
581d708e 2053 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2054 * @adapter: board private structure
581d708e
MC		 2055 *
2056 * Free all receive software resources
2057 **/
2058
2059void
2060e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2061{
2062 int i;
2063
f56799ea 2064 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2065 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2066}
2067
2068/**
2069 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2070 * @adapter: board private structure
2071 * @rx_ring: ring to free buffers from
1da177e4
LT		 2072 **/
2073
2074static void
581d708e
MC		 2075e1000_clean_rx_ring(struct e1000_adapter *adapter,
2076 struct e1000_rx_ring *rx_ring)
1da177e4 2077{
1da177e4 2078 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2079 struct e1000_ps_page *ps_page;
2080 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2081 struct pci_dev *pdev = adapter->pdev;
2082 unsigned long size;
2d7edb92 2083 unsigned int i, j;
1da177e4
LT		 2084
2085 /* Free all the Rx ring sk_buffs */
96838a40 2086 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2087 buffer_info = &rx_ring->buffer_info[i];
96838a40 2088 if (buffer_info->skb) {
1da177e4
LT		 2089 pci_unmap_single(pdev,
2090 buffer_info->dma,
2091 buffer_info->length,
2092 PCI_DMA_FROMDEVICE);
2093
2094 dev_kfree_skb(buffer_info->skb);
2095 buffer_info->skb = NULL;
997f5cbd
JK		 2096 }
2097 ps_page = &rx_ring->ps_page[i];
2098 ps_page_dma = &rx_ring->ps_page_dma[i];
2099 for (j = 0; j < adapter->rx_ps_pages; j++) {
2100 if (!ps_page->ps_page[j]) break;
2101 pci_unmap_page(pdev,
2102 ps_page_dma->ps_page_dma[j],
2103 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2104 ps_page_dma->ps_page_dma[j] = 0;
2105 put_page(ps_page->ps_page[j]);
2106 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2107 }
2108 }
2109
997f5cbd
JK		 2110 /* there also may be some cached data in our adapter */
2111 if (rx_ring->rx_skb_top) {
2112 dev_kfree_skb(rx_ring->rx_skb_top);
2113
2114 /* rx_skb_prev will be wiped out by rx_skb_top */
2115 rx_ring->rx_skb_top = NULL;
2116 rx_ring->rx_skb_prev = NULL;
2117 }
2118
2119
1da177e4
LT		 2120 size = sizeof(struct e1000_buffer) * rx_ring->count;
2121 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2122 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2123 memset(rx_ring->ps_page, 0, size);
2124 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2125 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2126
2127 /* Zero out the descriptor ring */
2128
2129 memset(rx_ring->desc, 0, rx_ring->size);
2130
2131 rx_ring->next_to_clean = 0;
2132 rx_ring->next_to_use = 0;
2133
581d708e
MC		 2134 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2135 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2136}
2137
2138/**
2139 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2140 * @adapter: board private structure
2141 **/
2142
2143static void
2144e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2145{
2146 int i;
2147
f56799ea 2148 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2149 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2150}
2151
2152/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2153 * and memory write and invalidate disabled for certain operations
2154 */
2155static void
2156e1000_enter_82542_rst(struct e1000_adapter *adapter)
2157{
2158 struct net_device *netdev = adapter->netdev;
2159 uint32_t rctl;
2160
2161 e1000_pci_clear_mwi(&adapter->hw);
2162
2163 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2164 rctl |= E1000_RCTL_RST;
2165 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2166 E1000_WRITE_FLUSH(&adapter->hw);
2167 mdelay(5);
2168
96838a40 2169 if (netif_running(netdev))
581d708e 2170 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2171}
2172
2173static void
2174e1000_leave_82542_rst(struct e1000_adapter *adapter)
2175{
2176 struct net_device *netdev = adapter->netdev;
2177 uint32_t rctl;
2178
2179 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2180 rctl &= ~E1000_RCTL_RST;
2181 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2182 E1000_WRITE_FLUSH(&adapter->hw);
2183 mdelay(5);
2184
96838a40 2185 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2186 e1000_pci_set_mwi(&adapter->hw);
2187
96838a40 2188 if (netif_running(netdev)) {
1da177e4 2189 e1000_configure_rx(adapter);
72d64a43
JK		 2190 /* No need to loop, because 82542 supports only 1 queue */
2191 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
2192 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2193 }
2194}
2195
2196/**
2197 * e1000_set_mac - Change the Ethernet Address of the NIC
2198 * @netdev: network interface device structure
2199 * @p: pointer to an address structure
2200 *
2201 * Returns 0 on success, negative on failure
2202 **/
2203
2204static int
2205e1000_set_mac(struct net_device *netdev, void *p)
2206{
60490fe0 2207 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2208 struct sockaddr *addr = p;
2209
96838a40 2210 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2211 return -EADDRNOTAVAIL;
2212
2213 /* 82542 2.0 needs to be in reset to write receive address registers */
2214
96838a40 2215 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2216 e1000_enter_82542_rst(adapter);
2217
2218 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2219 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2220
2221 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2222
868d5309
MC		 2223 /* With 82571 controllers, LAA may be overwritten (with the default)
2224 * due to controller reset from the other port. */
2225 if (adapter->hw.mac_type == e1000_82571) {
2226 /* activate the work around */
2227 adapter->hw.laa_is_present = 1;
2228
96838a40
JB		 2229 /* Hold a copy of the LAA in RAR[14] This is done so that
2230 * between the time RAR[0] gets clobbered and the time it
2231 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2232 * of the RARs and no incoming packets directed to this port
96838a40 2233 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2234 * RAR[14] */
96838a40 2235 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2236 E1000_RAR_ENTRIES - 1);
2237 }
2238
96838a40 2239 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2240 e1000_leave_82542_rst(adapter);
2241
2242 return 0;
2243}
2244
2245/**
2246 * e1000_set_multi - Multicast and Promiscuous mode set
2247 * @netdev: network interface device structure
2248 *
2249 * The set_multi entry point is called whenever the multicast address
2250 * list or the network interface flags are updated. This routine is
2251 * responsible for configuring the hardware for proper multicast,
2252 * promiscuous mode, and all-multi behavior.
2253 **/
2254
2255static void
2256e1000_set_multi(struct net_device *netdev)
2257{
60490fe0 2258 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2259 struct e1000_hw *hw = &adapter->hw;
2260 struct dev_mc_list *mc_ptr;
2261 uint32_t rctl;
2262 uint32_t hash_value;
868d5309 2263 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2264
868d5309
MC		 2265 /* reserve RAR[14] for LAA over-write work-around */
2266 if (adapter->hw.mac_type == e1000_82571)
2267 rar_entries--;
1da177e4 2268
2648345f
MC		 2269 /* Check for Promiscuous and All Multicast modes */
2270
1da177e4
LT		 2271 rctl = E1000_READ_REG(hw, RCTL);
2272
96838a40 2273 if (netdev->flags & IFF_PROMISC) {
1da177e4 2274 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2275 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2276 rctl |= E1000_RCTL_MPE;
2277 rctl &= ~E1000_RCTL_UPE;
2278 } else {
2279 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2280 }
2281
2282 E1000_WRITE_REG(hw, RCTL, rctl);
2283
2284 /* 82542 2.0 needs to be in reset to write receive address registers */
2285
96838a40 2286 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2287 e1000_enter_82542_rst(adapter);
2288
2289 /* load the first 14 multicast address into the exact filters 1-14
2290 * RAR 0 is used for the station MAC adddress
2291 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2292 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2293 */
2294 mc_ptr = netdev->mc_list;
2295
96838a40 2296 for (i = 1; i < rar_entries; i++) {
868d5309 2297 if (mc_ptr) {
1da177e4
LT		 2298 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2299 mc_ptr = mc_ptr->next;
2300 } else {
2301 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2302 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2303 }
2304 }
2305
2306 /* clear the old settings from the multicast hash table */
2307
96838a40 2308 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1da177e4
LT		 2309 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2310
2311 /* load any remaining addresses into the hash table */
2312
96838a40 2313 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2314 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2315 e1000_mta_set(hw, hash_value);
2316 }
2317
96838a40 2318 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2319 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2320}
2321
2322/* Need to wait a few seconds after link up to get diagnostic information from
2323 * the phy */
2324
2325static void
2326e1000_update_phy_info(unsigned long data)
2327{
2328 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2329 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2330}
2331
2332/**
2333 * e1000_82547_tx_fifo_stall - Timer Call-back
2334 * @data: pointer to adapter cast into an unsigned long
2335 **/
2336
2337static void
2338e1000_82547_tx_fifo_stall(unsigned long data)
2339{
2340 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2341 struct net_device *netdev = adapter->netdev;
2342 uint32_t tctl;
2343
96838a40
JB		 2344 if (atomic_read(&adapter->tx_fifo_stall)) {
2345 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2346 E1000_READ_REG(&adapter->hw, TDH)) &&
2347 (E1000_READ_REG(&adapter->hw, TDFT) ==
2348 E1000_READ_REG(&adapter->hw, TDFH)) &&
2349 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2350 E1000_READ_REG(&adapter->hw, TDFHS))) {
2351 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2352 E1000_WRITE_REG(&adapter->hw, TCTL,
2353 tctl & ~E1000_TCTL_EN);
2354 E1000_WRITE_REG(&adapter->hw, TDFT,
2355 adapter->tx_head_addr);
2356 E1000_WRITE_REG(&adapter->hw, TDFH,
2357 adapter->tx_head_addr);
2358 E1000_WRITE_REG(&adapter->hw, TDFTS,
2359 adapter->tx_head_addr);
2360 E1000_WRITE_REG(&adapter->hw, TDFHS,
2361 adapter->tx_head_addr);
2362 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2363 E1000_WRITE_FLUSH(&adapter->hw);
2364
2365 adapter->tx_fifo_head = 0;
2366 atomic_set(&adapter->tx_fifo_stall, 0);
2367 netif_wake_queue(netdev);
2368 } else {
2369 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2370 }
2371 }
2372}
2373
2374/**
2375 * e1000_watchdog - Timer Call-back
2376 * @data: pointer to adapter cast into an unsigned long
2377 **/
2378static void
2379e1000_watchdog(unsigned long data)
2380{
2381 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2382
2383 /* Do the rest outside of interrupt context */
2384 schedule_work(&adapter->watchdog_task);
2385}
2386
2387static void
2388e1000_watchdog_task(struct e1000_adapter *adapter)
2389{
2390 struct net_device *netdev = adapter->netdev;
545c67c0 2391 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2392 uint32_t link;
2393
2394 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2395 if (adapter->hw.mac_type == e1000_82573) {
2396 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2397 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2398 e1000_update_mng_vlan(adapter);
96838a40 2399 }
1da177e4 2400
96838a40 2401 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2402 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2403 link = !adapter->hw.serdes_link_down;
2404 else
2405 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2406
96838a40
JB		 2407 if (link) {
2408 if (!netif_carrier_ok(netdev)) {
1da177e4
LT		 2409 e1000_get_speed_and_duplex(&adapter->hw,
2410 &adapter->link_speed,
2411 &adapter->link_duplex);
2412
2413 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2414 adapter->link_speed,
2415 adapter->link_duplex == FULL_DUPLEX ?
2416 "Full Duplex" : "Half Duplex");
2417
66a2b0a3
JK		 2418 /* tweak tx_queue_len according to speed/duplex */
2419 netdev->tx_queue_len = adapter->tx_queue_len;
2420 adapter->tx_timeout_factor = 1;
2421 if (adapter->link_duplex == HALF_DUPLEX) {
2422 switch (adapter->link_speed) {
2423 case SPEED_10:
2424 netdev->tx_queue_len = 10;
2425 adapter->tx_timeout_factor = 8;
2426 break;
2427 case SPEED_100:
2428 netdev->tx_queue_len = 100;
2429 break;
2430 }
2431 }
2432
1da177e4
LT		 2433 netif_carrier_on(netdev);
2434 netif_wake_queue(netdev);
2435 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2436 adapter->smartspeed = 0;
2437 }
2438 } else {
96838a40 2439 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2440 adapter->link_speed = 0;
2441 adapter->link_duplex = 0;
2442 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2443 netif_carrier_off(netdev);
2444 netif_stop_queue(netdev);
2445 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2446 }
2447
2448 e1000_smartspeed(adapter);
2449 }
2450
2451 e1000_update_stats(adapter);
2452
2453 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2454 adapter->tpt_old = adapter->stats.tpt;
2455 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2456 adapter->colc_old = adapter->stats.colc;
2457
2458 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2459 adapter->gorcl_old = adapter->stats.gorcl;
2460 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2461 adapter->gotcl_old = adapter->stats.gotcl;
2462
2463 e1000_update_adaptive(&adapter->hw);
2464
f56799ea
JK		 2465#ifdef CONFIG_E1000_MQ
2466 txdr = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2467#endif
2468 if (!netif_carrier_ok(netdev)) {
581d708e 2469 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2470 /* We've lost link, so the controller stops DMA,
2471 * but we've got queued Tx work that's never going
2472 * to get done, so reset controller to flush Tx.
2473 * (Do the reset outside of interrupt context). */
2474 schedule_work(&adapter->tx_timeout_task);
2475 }
2476 }
2477
2478 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2479 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2480 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2481 * asymmetrical Tx or Rx gets ITR=8000; everyone
2482 * else is between 2000-8000. */
2483 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2484 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2485 adapter->gotcl - adapter->gorcl :
2486 adapter->gorcl - adapter->gotcl) / 10000;
2487 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2488 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2489 }
2490
2491 /* Cause software interrupt to ensure rx ring is cleaned */
2492 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2493
2648345f 2494 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2495 adapter->detect_tx_hung = TRUE;
2496
96838a40 2497 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2498 * reset from the other port. Set the appropriate LAA in RAR[0] */
2499 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2500 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2501
1da177e4
LT		 2502 /* Reset the timer */
2503 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2504}
2505
2506#define E1000_TX_FLAGS_CSUM 0x00000001
2507#define E1000_TX_FLAGS_VLAN 0x00000002
2508#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2509#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2510#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2511#define E1000_TX_FLAGS_VLAN_SHIFT 16
2512
2513static inline int
581d708e
MC		 2514e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2515 struct sk_buff *skb)
1da177e4
LT		 2516{
2517#ifdef NETIF_F_TSO
2518 struct e1000_context_desc *context_desc;
545c67c0 2519 struct e1000_buffer *buffer_info;
1da177e4
LT		 2520 unsigned int i;
2521 uint32_t cmd_length = 0;
2d7edb92 2522 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2523 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2524 int err;
2525
96838a40 2526 if (skb_shinfo(skb)->tso_size) {
1da177e4
LT		 2527 if (skb_header_cloned(skb)) {
2528 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2529 if (err)
2530 return err;
2531 }
2532
2533 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2534 mss = skb_shinfo(skb)->tso_size;
96838a40 2535 if (skb->protocol == ntohs(ETH_P_IP)) {
2d7edb92
MC		 2536 skb->nh.iph->tot_len = 0;
2537 skb->nh.iph->check = 0;
2538 skb->h.th->check =
2539 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2540 skb->nh.iph->daddr,
2541 0,
2542 IPPROTO_TCP,
2543 0);
2544 cmd_length = E1000_TXD_CMD_IP;
2545 ipcse = skb->h.raw - skb->data - 1;
2546#ifdef NETIF_F_TSO_IPV6
96838a40 2547 } else if (skb->protocol == ntohs(ETH_P_IPV6)) {
2d7edb92
MC		 2548 skb->nh.ipv6h->payload_len = 0;
2549 skb->h.th->check =
2550 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2551 &skb->nh.ipv6h->daddr,
2552 0,
2553 IPPROTO_TCP,
2554 0);
2555 ipcse = 0;
2556#endif
2557 }
1da177e4
LT		 2558 ipcss = skb->nh.raw - skb->data;
2559 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2560 tucss = skb->h.raw - skb->data;
2561 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2562 tucse = 0;
2563
2564 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2565 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2566
581d708e
MC		 2567 i = tx_ring->next_to_use;
2568 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2569 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2570
2571 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2572 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2573 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2574 context_desc->upper_setup.tcp_fields.tucss = tucss;
2575 context_desc->upper_setup.tcp_fields.tucso = tucso;
2576 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2577 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2578 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2579 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2580
545c67c0
JK		 2581 buffer_info->time_stamp = jiffies;
2582
581d708e
MC		 2583 if (++i == tx_ring->count) i = 0;
2584 tx_ring->next_to_use = i;
1da177e4 2585
8241e35e 2586 return TRUE;
1da177e4
LT		 2587 }
2588#endif
2589
8241e35e 2590 return FALSE;
1da177e4
LT		 2591}
2592
2593static inline boolean_t
581d708e
MC		 2594e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2595 struct sk_buff *skb)
1da177e4
LT		 2596{
2597 struct e1000_context_desc *context_desc;
545c67c0 2598 struct e1000_buffer *buffer_info;
1da177e4
LT		 2599 unsigned int i;
2600 uint8_t css;
2601
96838a40 2602 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2603 css = skb->h.raw - skb->data;
2604
581d708e 2605 i = tx_ring->next_to_use;
545c67c0 2606 buffer_info = &tx_ring->buffer_info[i];
581d708e 2607 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2608
2609 context_desc->upper_setup.tcp_fields.tucss = css;
2610 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2611 context_desc->upper_setup.tcp_fields.tucse = 0;
2612 context_desc->tcp_seg_setup.data = 0;
2613 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2614
545c67c0
JK		 2615 buffer_info->time_stamp = jiffies;
2616
581d708e
MC		 2617 if (unlikely(++i == tx_ring->count)) i = 0;
2618 tx_ring->next_to_use = i;
1da177e4
LT		 2619
2620 return TRUE;
2621 }
2622
2623 return FALSE;
2624}
2625
2626#define E1000_MAX_TXD_PWR 12
2627#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2628
2629static inline int
581d708e
MC		 2630e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2631 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2632 unsigned int nr_frags, unsigned int mss)
1da177e4 2633{
1da177e4
LT		 2634 struct e1000_buffer *buffer_info;
2635 unsigned int len = skb->len;
2636 unsigned int offset = 0, size, count = 0, i;
2637 unsigned int f;
2638 len -= skb->data_len;
2639
2640 i = tx_ring->next_to_use;
2641
96838a40 2642 while (len) {
1da177e4
LT		 2643 buffer_info = &tx_ring->buffer_info[i];
2644 size = min(len, max_per_txd);
2645#ifdef NETIF_F_TSO
fd803241
JK		 2646 /* Workaround for Controller erratum --
2647 * descriptor for non-tso packet in a linear SKB that follows a
2648 * tso gets written back prematurely before the data is fully
2649 * DMAd to the controller */
2650 if (!skb->data_len && tx_ring->last_tx_tso &&
2651 !skb_shinfo(skb)->tso_size) {
2652 tx_ring->last_tx_tso = 0;
2653 size -= 4;
2654 }
2655
1da177e4
LT		 2656 /* Workaround for premature desc write-backs
2657 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2658 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2659 size -= 4;
2660#endif
97338bde
MC		 2661 /* work-around for errata 10 and it applies
2662 * to all controllers in PCI-X mode
2663 * The fix is to make sure that the first descriptor of a
2664 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2665 */
96838a40 2666 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2667 (size > 2015) && count == 0))
2668 size = 2015;
96838a40 2669
1da177e4
LT		 2670 /* Workaround for potential 82544 hang in PCI-X. Avoid
2671 * terminating buffers within evenly-aligned dwords. */
96838a40 2672 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2673 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2674 size > 4))
2675 size -= 4;
2676
2677 buffer_info->length = size;
2678 buffer_info->dma =
2679 pci_map_single(adapter->pdev,
2680 skb->data + offset,
2681 size,
2682 PCI_DMA_TODEVICE);
2683 buffer_info->time_stamp = jiffies;
2684
2685 len -= size;
2686 offset += size;
2687 count++;
96838a40 2688 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2689 }
2690
96838a40 2691 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2692 struct skb_frag_struct *frag;
2693
2694 frag = &skb_shinfo(skb)->frags[f];
2695 len = frag->size;
2696 offset = frag->page_offset;
2697
96838a40 2698 while (len) {
1da177e4
LT		 2699 buffer_info = &tx_ring->buffer_info[i];
2700 size = min(len, max_per_txd);
2701#ifdef NETIF_F_TSO
2702 /* Workaround for premature desc write-backs
2703 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2704 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2705 size -= 4;
2706#endif
2707 /* Workaround for potential 82544 hang in PCI-X.
2708 * Avoid terminating buffers within evenly-aligned
2709 * dwords. */
96838a40 2710 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2711 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2712 size > 4))
2713 size -= 4;
2714
2715 buffer_info->length = size;
2716 buffer_info->dma =
2717 pci_map_page(adapter->pdev,
2718 frag->page,
2719 offset,
2720 size,
2721 PCI_DMA_TODEVICE);
2722 buffer_info->time_stamp = jiffies;
2723
2724 len -= size;
2725 offset += size;
2726 count++;
96838a40 2727 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2728 }
2729 }
2730
2731 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2732 tx_ring->buffer_info[i].skb = skb;
2733 tx_ring->buffer_info[first].next_to_watch = i;
2734
2735 return count;
2736}
2737
2738static inline void
581d708e
MC		 2739e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2740 int tx_flags, int count)
1da177e4 2741{
1da177e4
LT		 2742 struct e1000_tx_desc *tx_desc = NULL;
2743 struct e1000_buffer *buffer_info;
2744 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2745 unsigned int i;
2746
96838a40 2747 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2748 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2749 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2750 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2751
96838a40 2752 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2753 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2754 }
2755
96838a40 2756 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2757 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2758 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2759 }
2760
96838a40 2761 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2762 txd_lower |= E1000_TXD_CMD_VLE;
2763 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2764 }
2765
2766 i = tx_ring->next_to_use;
2767
96838a40 2768 while (count--) {
1da177e4
LT		 2769 buffer_info = &tx_ring->buffer_info[i];
2770 tx_desc = E1000_TX_DESC(*tx_ring, i);
2771 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2772 tx_desc->lower.data =
2773 cpu_to_le32(txd_lower | buffer_info->length);
2774 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2775 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2776 }
2777
2778 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2779
2780 /* Force memory writes to complete before letting h/w
2781 * know there are new descriptors to fetch. (Only
2782 * applicable for weak-ordered memory model archs,
2783 * such as IA-64). */
2784 wmb();
2785
2786 tx_ring->next_to_use = i;
581d708e 2787 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2788}
2789
2790/**
2791 * 82547 workaround to avoid controller hang in half-duplex environment.
2792 * The workaround is to avoid queuing a large packet that would span
2793 * the internal Tx FIFO ring boundary by notifying the stack to resend
2794 * the packet at a later time. This gives the Tx FIFO an opportunity to
2795 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2796 * to the beginning of the Tx FIFO.
2797 **/
2798
2799#define E1000_FIFO_HDR 0x10
2800#define E1000_82547_PAD_LEN 0x3E0
2801
2802static inline int
2803e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2804{
2805 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2806 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2807
2808 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2809
96838a40 2810 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2811 goto no_fifo_stall_required;
2812
96838a40 2813 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2814 return 1;
2815
96838a40 2816 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2817 atomic_set(&adapter->tx_fifo_stall, 1);
2818 return 1;
2819 }
2820
2821no_fifo_stall_required:
2822 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2823 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2824 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2825 return 0;
2826}
2827
2d7edb92
MC		 2828#define MINIMUM_DHCP_PACKET_SIZE 282
2829static inline int
2830e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2831{
2832 struct e1000_hw *hw = &adapter->hw;
2833 uint16_t length, offset;
96838a40
JB		 2834 if (vlan_tx_tag_present(skb)) {
2835 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2836 ( adapter->hw.mng_cookie.status &
2837 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2838 return 0;
2839 }
96838a40 2840 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92 2841 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2842 if ((htons(ETH_P_IP) == eth->h_proto)) {
2843 const struct iphdr *ip =
2d7edb92 2844 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2845 if (IPPROTO_UDP == ip->protocol) {
2846 struct udphdr *udp =
2847 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2848 (ip->ihl << 2));
96838a40 2849 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2850 offset = (uint8_t *)udp + 8 - skb->data;
2851 length = skb->len - offset;
2852
2853 return e1000_mng_write_dhcp_info(hw,
96838a40 2854 (uint8_t *)udp + 8,
2d7edb92
MC		 2855 length);
2856 }
2857 }
2858 }
2859 }
2860 return 0;
2861}
2862
1da177e4
LT		 2863#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2864static int
2865e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2866{
60490fe0 2867 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2868 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2869 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2870 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2871 unsigned int tx_flags = 0;
2872 unsigned int len = skb->len;
2873 unsigned long flags;
2874 unsigned int nr_frags = 0;
2875 unsigned int mss = 0;
2876 int count = 0;
96838a40 2877 int tso;
1da177e4
LT		 2878 unsigned int f;
2879 len -= skb->data_len;
2880
24025e4e
MC		 2881#ifdef CONFIG_E1000_MQ
2882 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2883#else
581d708e 2884 tx_ring = adapter->tx_ring;
24025e4e
MC		 2885#endif
2886
581d708e 2887 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2888 dev_kfree_skb_any(skb);
2889 return NETDEV_TX_OK;
2890 }
2891
2892#ifdef NETIF_F_TSO
2893 mss = skb_shinfo(skb)->tso_size;
2648345f 2894 /* The controller does a simple calculation to
1da177e4
LT		 2895 * make sure there is enough room in the FIFO before
2896 * initiating the DMA for each buffer. The calc is:
2897 * 4 = ceil(buffer len/mss). To make sure we don't
2898 * overrun the FIFO, adjust the max buffer len if mss
2899 * drops. */
96838a40 2900 if (mss) {
9a3056da 2901 uint8_t hdr_len;
1da177e4
LT		 2902 max_per_txd = min(mss << 2, max_per_txd);
2903 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2904
2905 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2906 * points to just header, pull a few bytes of payload from
2907 * frags into skb->data */
2908 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2909 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2910 (adapter->hw.mac_type == e1000_82571 ||
2911 adapter->hw.mac_type == e1000_82572)) {
d74bbd3b
JK		 2912 unsigned int pull_size;
2913 pull_size = min((unsigned int)4, skb->data_len);
2914 if (!__pskb_pull_tail(skb, pull_size)) {
2915 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2916 dev_kfree_skb_any(skb);
2917 return -EFAULT;
2918 }
9a3056da
JK		 2919 len = skb->len - skb->data_len;
2920 }
1da177e4
LT		 2921 }
2922
9a3056da 2923 /* reserve a descriptor for the offload context */
96838a40 2924 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2925 count++;
2648345f 2926 count++;
1da177e4 2927#else
96838a40 2928 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2929 count++;
2930#endif
fd803241
JK		 2931
2932#ifdef NETIF_F_TSO
2933 /* Controller Erratum workaround */
2934 if (!skb->data_len && tx_ring->last_tx_tso &&
2935 !skb_shinfo(skb)->tso_size)
2936 count++;
2937#endif
2938
1da177e4
LT		 2939 count += TXD_USE_COUNT(len, max_txd_pwr);
2940
96838a40 2941 if (adapter->pcix_82544)
1da177e4
LT		 2942 count++;
2943
96838a40 2944 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2945 * in PCI-X mode, so add one more descriptor to the count
2946 */
96838a40 2947 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2948 (len > 2015)))
2949 count++;
2950
1da177e4 2951 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2952 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2953 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2954 max_txd_pwr);
96838a40 2955 if (adapter->pcix_82544)
1da177e4
LT		 2956 count += nr_frags;
2957
96838a40 2958 if (adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2d7edb92
MC		 2959 e1000_transfer_dhcp_info(adapter, skb);
2960
581d708e
MC		 2961 local_irq_save(flags);
2962 if (!spin_trylock(&tx_ring->tx_lock)) {
2963 /* Collision - tell upper layer to requeue */
2964 local_irq_restore(flags);
2965 return NETDEV_TX_LOCKED;
2966 }
1da177e4
LT		 2967
2968 /* need: count + 2 desc gap to keep tail from touching
2969 * head, otherwise try next time */
581d708e 2970 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2971 netif_stop_queue(netdev);
581d708e 2972 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2973 return NETDEV_TX_BUSY;
2974 }
2975
96838a40
JB		 2976 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2977 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2978 netif_stop_queue(netdev);
2979 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2980 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2981 return NETDEV_TX_BUSY;
2982 }
2983 }
2984
96838a40 2985 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2986 tx_flags |= E1000_TX_FLAGS_VLAN;
2987 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2988 }
2989
581d708e 2990 first = tx_ring->next_to_use;
96838a40 2991
581d708e 2992 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2993 if (tso < 0) {
2994 dev_kfree_skb_any(skb);
581d708e 2995 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2996 return NETDEV_TX_OK;
2997 }
2998
fd803241
JK		 2999 if (likely(tso)) {
3000 tx_ring->last_tx_tso = 1;
1da177e4 3001 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3002 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3003 tx_flags |= E1000_TX_FLAGS_CSUM;
3004
2d7edb92 3005 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3006 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3007 * no longer assume, we must. */
581d708e 3008 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 3009 tx_flags |= E1000_TX_FLAGS_IPV4;
3010
581d708e
MC		 3011 e1000_tx_queue(adapter, tx_ring, tx_flags,
3012 e1000_tx_map(adapter, tx_ring, skb, first,
3013 max_per_txd, nr_frags, mss));
1da177e4
LT		 3014
3015 netdev->trans_start = jiffies;
3016
3017 /* Make sure there is space in the ring for the next send. */
581d708e 3018 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 3019 netif_stop_queue(netdev);
3020
581d708e 3021 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3022 return NETDEV_TX_OK;
3023}
3024
3025/**
3026 * e1000_tx_timeout - Respond to a Tx Hang
3027 * @netdev: network interface device structure
3028 **/
3029
3030static void
3031e1000_tx_timeout(struct net_device *netdev)
3032{
60490fe0 3033 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3034
3035 /* Do the reset outside of interrupt context */
3036 schedule_work(&adapter->tx_timeout_task);
3037}
3038
3039static void
3040e1000_tx_timeout_task(struct net_device *netdev)
3041{
60490fe0 3042 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3043
6b7660cd 3044 adapter->tx_timeout_count++;
1da177e4
LT		 3045 e1000_down(adapter);
3046 e1000_up(adapter);
3047}
3048
3049/**
3050 * e1000_get_stats - Get System Network Statistics
3051 * @netdev: network interface device structure
3052 *
3053 * Returns the address of the device statistics structure.
3054 * The statistics are actually updated from the timer callback.
3055 **/
3056
3057static struct net_device_stats *
3058e1000_get_stats(struct net_device *netdev)
3059{
60490fe0 3060 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3061
6b7660cd 3062 /* only return the current stats */
1da177e4
LT		 3063 return &adapter->net_stats;
3064}
3065
3066/**
3067 * e1000_change_mtu - Change the Maximum Transfer Unit
3068 * @netdev: network interface device structure
3069 * @new_mtu: new value for maximum frame size
3070 *
3071 * Returns 0 on success, negative on failure
3072 **/
3073
3074static int
3075e1000_change_mtu(struct net_device *netdev, int new_mtu)
3076{
60490fe0 3077 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3078 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3079
96838a40
JB		 3080 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3081 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3082 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3083 return -EINVAL;
2d7edb92 3084 }
1da177e4 3085
997f5cbd
JK		 3086 /* Adapter-specific max frame size limits. */
3087 switch (adapter->hw.mac_type) {
3088 case e1000_82542_rev2_0:
3089 case e1000_82542_rev2_1:
3090 case e1000_82573:
3091 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3092 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3093 return -EINVAL;
2d7edb92 3094 }
997f5cbd
JK		 3095 break;
3096 case e1000_82571:
3097 case e1000_82572:
3098#define MAX_STD_JUMBO_FRAME_SIZE 9234
3099 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3100 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3101 return -EINVAL;
3102 }
3103 break;
3104 default:
3105 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3106 break;
1da177e4
LT		 3107 }
3108
997f5cbd
JK		 3109 /* since the driver code now supports splitting a packet across
3110 * multiple descriptors, most of the fifo related limitations on
3111 * jumbo frame traffic have gone away.
3112 * simply use 2k descriptors for everything.
3113 *
3114 * NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3115 * means we reserve 2 more, this pushes us to allocate from the next
3116 * larger slab size
3117 * i.e. RXBUFFER_2048 --> size-4096 slab */
3118
3119 /* recent hardware supports 1KB granularity */
3120 if (adapter->hw.mac_type > e1000_82547_rev_2) {
3121 adapter->rx_buffer_len =
3122 ((max_frame < E1000_RXBUFFER_2048) ?
3123 max_frame : E1000_RXBUFFER_2048);
3124 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
3125 } else
3126 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3127
2d7edb92
MC		 3128 netdev->mtu = new_mtu;
3129
96838a40 3130 if (netif_running(netdev)) {
1da177e4
LT		 3131 e1000_down(adapter);
3132 e1000_up(adapter);
3133 }
3134
1da177e4
LT		 3135 adapter->hw.max_frame_size = max_frame;
3136
3137 return 0;
3138}
3139
3140/**
3141 * e1000_update_stats - Update the board statistics counters
3142 * @adapter: board private structure
3143 **/
3144
3145void
3146e1000_update_stats(struct e1000_adapter *adapter)
3147{
3148 struct e1000_hw *hw = &adapter->hw;
3149 unsigned long flags;
3150 uint16_t phy_tmp;
3151
3152#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3153
3154 spin_lock_irqsave(&adapter->stats_lock, flags);
3155
3156 /* these counters are modified from e1000_adjust_tbi_stats,
3157 * called from the interrupt context, so they must only
3158 * be written while holding adapter->stats_lock
3159 */
3160
3161 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3162 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3163 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3164 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3165 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3166 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3167 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3168 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3169 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3170 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3171 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3172 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3173 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3174
3175 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3176 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3177 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3178 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3179 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3180 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3181 adapter->stats.dc += E1000_READ_REG(hw, DC);
3182 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3183 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3184 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3185 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3186 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3187 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3188 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3189 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3190 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3191 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3192 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3193 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3194 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3195 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3196 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3197 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3198 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3199 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3200 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3201 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3202 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3203 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3204 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3205 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3206 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3207 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3208 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3209
3210 /* used for adaptive IFS */
3211
3212 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3213 adapter->stats.tpt += hw->tx_packet_delta;
3214 hw->collision_delta = E1000_READ_REG(hw, COLC);
3215 adapter->stats.colc += hw->collision_delta;
3216
96838a40 3217 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3218 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3219 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3220 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3221 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3222 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3223 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3224 }
96838a40 3225 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3226 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3227 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3228 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3229 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3230 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3231 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3232 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3233 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3234 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3235 }
1da177e4
LT		 3236
3237 /* Fill out the OS statistics structure */
3238
3239 adapter->net_stats.rx_packets = adapter->stats.gprc;
3240 adapter->net_stats.tx_packets = adapter->stats.gptc;
3241 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3242 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3243 adapter->net_stats.multicast = adapter->stats.mprc;
3244 adapter->net_stats.collisions = adapter->stats.colc;
3245
3246 /* Rx Errors */
3247
3248 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3249 adapter->stats.crcerrs + adapter->stats.algnerrc +
6b7660cd
JK		 3250 adapter->stats.rlec + adapter->stats.cexterr;
3251 adapter->net_stats.rx_dropped = 0;
1da177e4
LT		 3252 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3253 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3254 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3255 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3256
3257 /* Tx Errors */
3258
3259 adapter->net_stats.tx_errors = adapter->stats.ecol +
3260 adapter->stats.latecol;
3261 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3262 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3263 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3264
3265 /* Tx Dropped needs to be maintained elsewhere */
3266
3267 /* Phy Stats */
3268
96838a40
JB		 3269 if (hw->media_type == e1000_media_type_copper) {
3270 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3271 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3272 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3273 adapter->phy_stats.idle_errors += phy_tmp;
3274 }
3275
96838a40 3276 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3277 (hw->phy_type == e1000_phy_m88) &&
3278 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3279 adapter->phy_stats.receive_errors += phy_tmp;
3280 }
3281
3282 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3283}
3284
24025e4e
MC		 3285#ifdef CONFIG_E1000_MQ
3286void
3287e1000_rx_schedule(void *data)
3288{
3289 struct net_device *poll_dev, *netdev = data;
3290 struct e1000_adapter *adapter = netdev->priv;
3291 int this_cpu = get_cpu();
3292
3293 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3294 if (poll_dev == NULL) {
3295 put_cpu();
3296 return;
3297 }
3298
3299 if (likely(netif_rx_schedule_prep(poll_dev)))
3300 __netif_rx_schedule(poll_dev);
3301 else
3302 e1000_irq_enable(adapter);
3303
3304 put_cpu();
3305}
3306#endif
3307
1da177e4
LT		 3308/**
3309 * e1000_intr - Interrupt Handler
3310 * @irq: interrupt number
3311 * @data: pointer to a network interface device structure
3312 * @pt_regs: CPU registers structure
3313 **/
3314
3315static irqreturn_t
3316e1000_intr(int irq, void *data, struct pt_regs *regs)
3317{
3318 struct net_device *netdev = data;
60490fe0 3319 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3320 struct e1000_hw *hw = &adapter->hw;
3321 uint32_t icr = E1000_READ_REG(hw, ICR);
1e613fd9 3322#ifndef CONFIG_E1000_NAPI
581d708e 3323 int i;
1e613fd9
JK		 3324#else
3325 /* Interrupt Auto-Mask...upon reading ICR,
3326 * interrupts are masked. No need for the
3327 * IMC write, but it does mean we should
3328 * account for it ASAP. */
3329 if (likely(hw->mac_type >= e1000_82571))
3330 atomic_inc(&adapter->irq_sem);
be2b28ed 3331#endif
1da177e4 3332
1e613fd9
JK		 3333 if (unlikely(!icr)) {
3334#ifdef CONFIG_E1000_NAPI
3335 if (hw->mac_type >= e1000_82571)
3336 e1000_irq_enable(adapter);
3337#endif
1da177e4 3338 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3339 }
1da177e4 3340
96838a40 3341 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4
LT		 3342 hw->get_link_status = 1;
3343 mod_timer(&adapter->watchdog_timer, jiffies);
3344 }
3345
3346#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3347 if (unlikely(hw->mac_type < e1000_82571)) {
3348 atomic_inc(&adapter->irq_sem);
3349 E1000_WRITE_REG(hw, IMC, ~0);
3350 E1000_WRITE_FLUSH(hw);
3351 }
24025e4e
MC		 3352#ifdef CONFIG_E1000_MQ
3353 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
f56799ea
JK		 3354 /* We must setup the cpumask once count == 0 since
3355 * each cpu bit is cleared when the work is done. */
3356 adapter->rx_sched_call_data.cpumask = adapter->cpumask;
3357 atomic_add(adapter->num_rx_queues - 1, &adapter->irq_sem);
3358 atomic_set(&adapter->rx_sched_call_data.count,
3359 adapter->num_rx_queues);
24025e4e
MC		 3360 smp_call_async_mask(&adapter->rx_sched_call_data);
3361 } else {
3362 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3363 }
be2b28ed 3364#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3365 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3366 __netif_rx_schedule(&adapter->polling_netdev[0]);
3367 else
3368 e1000_irq_enable(adapter);
be2b28ed
JG		 3369#endif /* CONFIG_E1000_MQ */
3370
3371#else /* if !CONFIG_E1000_NAPI */
1da177e4 3372 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3373 * Due to Hub Link bus being occupied, an interrupt
3374 * de-assertion message is not able to be sent.
3375 * When an interrupt assertion message is generated later,
3376 * two messages are re-ordered and sent out.
3377 * That causes APIC to think 82547 is in de-assertion
3378 * state, while 82547 is in assertion state, resulting
3379 * in dead lock. Writing IMC forces 82547 into
3380 * de-assertion state.
3381 */
3382 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3383 atomic_inc(&adapter->irq_sem);
2648345f 3384 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3385 }
3386
96838a40
JB		 3387 for (i = 0; i < E1000_MAX_INTR; i++)
3388 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3389 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3390 break;
3391
96838a40 3392 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3393 e1000_irq_enable(adapter);
581d708e 3394
be2b28ed 3395#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3396
3397 return IRQ_HANDLED;
3398}
3399
3400#ifdef CONFIG_E1000_NAPI
3401/**
3402 * e1000_clean - NAPI Rx polling callback
3403 * @adapter: board private structure
3404 **/
3405
3406static int
581d708e 3407e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3408{
581d708e
MC		 3409 struct e1000_adapter *adapter;
3410 int work_to_do = min(*budget, poll_dev->quota);
38bd3b26 3411 int tx_cleaned = 0, i = 0, work_done = 0;
581d708e
MC		 3412
3413 /* Must NOT use netdev_priv macro here. */
3414 adapter = poll_dev->priv;
3415
3416 /* Keep link state information with original netdev */
3417 if (!netif_carrier_ok(adapter->netdev))
3418 goto quit_polling;
2648345f 3419
581d708e
MC		 3420 while (poll_dev != &adapter->polling_netdev[i]) {
3421 i++;
f56799ea 3422 if (unlikely(i == adapter->num_rx_queues))
581d708e
MC		 3423 BUG();
3424 }
3425
8241e35e
JK		 3426 if (likely(adapter->num_tx_queues == 1)) {
3427 /* e1000_clean is called per-cpu. This lock protects
3428 * tx_ring[0] from being cleaned by multiple cpus
3429 * simultaneously. A failure obtaining the lock means
3430 * tx_ring[0] is currently being cleaned anyway. */
3431 if (spin_trylock(&adapter->tx_queue_lock)) {
3432 tx_cleaned = e1000_clean_tx_irq(adapter,
3433 &adapter->tx_ring[0]);
3434 spin_unlock(&adapter->tx_queue_lock);
3435 }
3436 } else
3437 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3438
581d708e
MC		 3439 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3440 &work_done, work_to_do);
1da177e4
LT		 3441
3442 *budget -= work_done;
581d708e 3443 poll_dev->quota -= work_done;
96838a40 3444
2b02893e 3445 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3446 if ((!tx_cleaned && (work_done == 0)) ||
581d708e
MC		 3447 !netif_running(adapter->netdev)) {
3448quit_polling:
3449 netif_rx_complete(poll_dev);
1da177e4
LT		 3450 e1000_irq_enable(adapter);
3451 return 0;
3452 }
3453
3454 return 1;
3455}
3456
3457#endif
3458/**
3459 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3460 * @adapter: board private structure
3461 **/
3462
3463static boolean_t
581d708e
MC		 3464e1000_clean_tx_irq(struct e1000_adapter *adapter,
3465 struct e1000_tx_ring *tx_ring)
1da177e4 3466{
1da177e4
LT		 3467 struct net_device *netdev = adapter->netdev;
3468 struct e1000_tx_desc *tx_desc, *eop_desc;
3469 struct e1000_buffer *buffer_info;
3470 unsigned int i, eop;
3471 boolean_t cleaned = FALSE;
3472
3473 i = tx_ring->next_to_clean;
3474 eop = tx_ring->buffer_info[i].next_to_watch;
3475 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3476
581d708e 3477 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3478 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3479 tx_desc = E1000_TX_DESC(*tx_ring, i);
3480 buffer_info = &tx_ring->buffer_info[i];
3481 cleaned = (i == eop);
3482
8241e35e
JK		 3483#ifdef CONFIG_E1000_MQ
3484 tx_ring->tx_stats.bytes += buffer_info->length;
3485#endif
fd803241 3486 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3487 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3488
96838a40 3489 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3490 }
581d708e 3491
7bfa4816
JK		 3492#ifdef CONFIG_E1000_MQ
3493 tx_ring->tx_stats.packets++;
3494#endif
3495
1da177e4
LT		 3496 eop = tx_ring->buffer_info[i].next_to_watch;
3497 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3498 }
3499
3500 tx_ring->next_to_clean = i;
3501
581d708e 3502 spin_lock(&tx_ring->tx_lock);
1da177e4 3503
96838a40 3504 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
1da177e4
LT		 3505 netif_carrier_ok(netdev)))
3506 netif_wake_queue(netdev);
3507
581d708e 3508 spin_unlock(&tx_ring->tx_lock);
2648345f 3509
581d708e 3510 if (adapter->detect_tx_hung) {
2648345f 3511 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3512 * check with the clearing of time_stamp and movement of i */
3513 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3514 if (tx_ring->buffer_info[eop].dma &&
3515 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
3516 adapter->tx_timeout_factor * HZ)
70b8f1e1 3517 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3518 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3519
3520 /* detected Tx unit hang */
c6963ef5 3521 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3522 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3523 " TDH <%x>\n"
3524 " TDT <%x>\n"
3525 " next_to_use <%x>\n"
3526 " next_to_clean <%x>\n"
3527 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3528 " time_stamp <%lx>\n"
3529 " next_to_watch <%x>\n"
3530 " jiffies <%lx>\n"
3531 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3532 (unsigned long)((tx_ring - adapter->tx_ring) /
3533 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3534 readl(adapter->hw.hw_addr + tx_ring->tdh),
3535 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3536 tx_ring->next_to_use,
392137fa
JK		 3537 tx_ring->next_to_clean,
3538 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3539 eop,
3540 jiffies,
3541 eop_desc->upper.fields.status);
1da177e4 3542 netif_stop_queue(netdev);
70b8f1e1 3543 }
1da177e4 3544 }
1da177e4
LT		 3545 return cleaned;
3546}
3547
3548/**
3549 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3550 * @adapter: board private structure
3551 * @status_err: receive descriptor status and error fields
3552 * @csum: receive descriptor csum field
3553 * @sk_buff: socket buffer with received data
1da177e4
LT		 3554 **/
3555
3556static inline void
3557e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3558 uint32_t status_err, uint32_t csum,
3559 struct sk_buff *skb)
1da177e4 3560{
2d7edb92
MC		 3561 uint16_t status = (uint16_t)status_err;
3562 uint8_t errors = (uint8_t)(status_err >> 24);
3563 skb->ip_summed = CHECKSUM_NONE;
3564
1da177e4 3565 /* 82543 or newer only */
96838a40 3566 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3567 /* Ignore Checksum bit is set */
96838a40 3568 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3569 /* TCP/UDP checksum error bit is set */
96838a40 3570 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3571 /* let the stack verify checksum errors */
1da177e4 3572 adapter->hw_csum_err++;
2d7edb92
MC		 3573 return;
3574 }
3575 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3576 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3577 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3578 return;
1da177e4 3579 } else {
96838a40 3580 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3581 return;
3582 }
3583 /* It must be a TCP or UDP packet with a valid checksum */
3584 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3585 /* TCP checksum is good */
3586 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3587 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3588 /* IP fragment with UDP payload */
3589 /* Hardware complements the payload checksum, so we undo it
3590 * and then put the value in host order for further stack use.
3591 */
3592 csum = ntohl(csum ^ 0xFFFF);
3593 skb->csum = csum;
3594 skb->ip_summed = CHECKSUM_HW;
1da177e4 3595 }
2d7edb92 3596 adapter->hw_csum_good++;
1da177e4
LT		 3597}
3598
3599/**
2d7edb92 3600 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3601 * @adapter: board private structure
3602 **/
3603
3604static boolean_t
3605#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3606e1000_clean_rx_irq(struct e1000_adapter *adapter,
3607 struct e1000_rx_ring *rx_ring,
3608 int *work_done, int work_to_do)
1da177e4 3609#else
581d708e
MC		 3610e1000_clean_rx_irq(struct e1000_adapter *adapter,
3611 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3612#endif
3613{
1da177e4
LT		 3614 struct net_device *netdev = adapter->netdev;
3615 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3616 struct e1000_rx_desc *rx_desc, *next_rxd;
3617 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3618 unsigned long flags;
3619 uint32_t length;
3620 uint8_t last_byte;
3621 unsigned int i;
72d64a43 3622 int cleaned_count = 0;
a292ca6e 3623 boolean_t cleaned = FALSE, multi_descriptor = FALSE;
1da177e4
LT		 3624
3625 i = rx_ring->next_to_clean;
3626 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3627 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3628
b92ff8ee 3629 while (rx_desc->status & E1000_RXD_STAT_DD) {
86c3d59f 3630 struct sk_buff *skb, *next_skb;
a292ca6e 3631 u8 status;
1da177e4 3632#ifdef CONFIG_E1000_NAPI
96838a40 3633 if (*work_done >= work_to_do)
1da177e4
LT		 3634 break;
3635 (*work_done)++;
3636#endif
a292ca6e 3637 status = rx_desc->status;
b92ff8ee 3638 skb = buffer_info->skb;
86c3d59f
JB		 3639 buffer_info->skb = NULL;
3640
3641 if (++i == rx_ring->count) i = 0;
3642 next_rxd = E1000_RX_DESC(*rx_ring, i);
3643 next_buffer = &rx_ring->buffer_info[i];
3644 next_skb = next_buffer->skb;
3645
72d64a43
JK		 3646 cleaned = TRUE;
3647 cleaned_count++;
a292ca6e
JK		 3648 pci_unmap_single(pdev,
3649 buffer_info->dma,
3650 buffer_info->length,
1da177e4
LT		 3651 PCI_DMA_FROMDEVICE);
3652
1da177e4
LT		 3653 length = le16_to_cpu(rx_desc->length);
3654
b92ff8ee
JB		 3655 skb_put(skb, length);
3656
3657 if (!(status & E1000_RXD_STAT_EOP)) {
3658 if (!rx_ring->rx_skb_top) {
3659 rx_ring->rx_skb_top = skb;
3660 rx_ring->rx_skb_top->len = length;
3661 rx_ring->rx_skb_prev = skb;
3662 } else {
3663 if (skb_shinfo(rx_ring->rx_skb_top)->frag_list) {
3664 rx_ring->rx_skb_prev->next = skb;
3665 skb->prev = rx_ring->rx_skb_prev;
3666 } else {
3667 skb_shinfo(rx_ring->rx_skb_top)->frag_list = skb;
3668 }
3669 rx_ring->rx_skb_prev = skb;
3670 rx_ring->rx_skb_top->data_len += length;
3671 }
1da177e4 3672 goto next_desc;
b92ff8ee
JB		 3673 } else {
3674 if (rx_ring->rx_skb_top) {
3675 if (skb_shinfo(rx_ring->rx_skb_top)
3676 ->frag_list) {
3677 rx_ring->rx_skb_prev->next = skb;
3678 skb->prev = rx_ring->rx_skb_prev;
3679 } else
3680 skb_shinfo(rx_ring->rx_skb_top)
3681 ->frag_list = skb;
3682
3683 rx_ring->rx_skb_top->data_len += length;
3684 rx_ring->rx_skb_top->len +=
3685 rx_ring->rx_skb_top->data_len;
3686
3687 skb = rx_ring->rx_skb_top;
3688 multi_descriptor = TRUE;
3689 rx_ring->rx_skb_top = NULL;
3690 rx_ring->rx_skb_prev = NULL;
3691 }
1da177e4
LT		 3692 }
3693
96838a40 3694 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3695 last_byte = *(skb->data + length - 1);
b92ff8ee 3696 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3697 rx_desc->errors, length, last_byte)) {
3698 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3699 e1000_tbi_adjust_stats(&adapter->hw,
3700 &adapter->stats,
1da177e4
LT		 3701 length, skb->data);
3702 spin_unlock_irqrestore(&adapter->stats_lock,
3703 flags);
3704 length--;
3705 } else {
3706 dev_kfree_skb_irq(skb);
3707 goto next_desc;
3708 }
3709 }
3710
a292ca6e
JK		 3711 /* code added for copybreak, this should improve
3712 * performance for small packets with large amounts
3713 * of reassembly being done in the stack */
3714#define E1000_CB_LENGTH 256
3715 if ((length < E1000_CB_LENGTH) &&
3716 !rx_ring->rx_skb_top &&
3717 /* or maybe (status & E1000_RXD_STAT_EOP) && */
3718 !multi_descriptor) {
3719 struct sk_buff *new_skb =
3720 dev_alloc_skb(length + NET_IP_ALIGN);
3721 if (new_skb) {
3722 skb_reserve(new_skb, NET_IP_ALIGN);
3723 new_skb->dev = netdev;
3724 memcpy(new_skb->data - NET_IP_ALIGN,
3725 skb->data - NET_IP_ALIGN,
3726 length + NET_IP_ALIGN);
3727 /* save the skb in buffer_info as good */
3728 buffer_info->skb = skb;
3729 skb = new_skb;
3730 skb_put(skb, length);
3731 }
3732 }
3733
3734 /* end copybreak code */
1da177e4
LT		 3735
3736 /* Receive Checksum Offload */
a292ca6e
JK		 3737 e1000_rx_checksum(adapter,
3738 (uint32_t)(status) |
2d7edb92
MC		 3739 ((uint32_t)(rx_desc->errors) << 24),
3740 rx_desc->csum, skb);
96838a40 3741
1da177e4
LT		 3742 skb->protocol = eth_type_trans(skb, netdev);
3743#ifdef CONFIG_E1000_NAPI
96838a40 3744 if (unlikely(adapter->vlgrp &&
a292ca6e 3745 (status & E1000_RXD_STAT_VP))) {
1da177e4 3746 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3747 le16_to_cpu(rx_desc->special) &
3748 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3749 } else {
3750 netif_receive_skb(skb);
3751 }
3752#else /* CONFIG_E1000_NAPI */
96838a40 3753 if (unlikely(adapter->vlgrp &&
b92ff8ee 3754 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3755 vlan_hwaccel_rx(skb, adapter->vlgrp,
3756 le16_to_cpu(rx_desc->special) &
3757 E1000_RXD_SPC_VLAN_MASK);
3758 } else {
3759 netif_rx(skb);
3760 }
3761#endif /* CONFIG_E1000_NAPI */
3762 netdev->last_rx = jiffies;
7bfa4816
JK		 3763#ifdef CONFIG_E1000_MQ
3764 rx_ring->rx_stats.packets++;
3765 rx_ring->rx_stats.bytes += length;
3766#endif
1da177e4
LT		 3767
3768next_desc:
3769 rx_desc->status = 0;
1da177e4 3770
72d64a43
JK		 3771 /* return some buffers to hardware, one at a time is too slow */
3772 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3773 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3774 cleaned_count = 0;
3775 }
3776
86c3d59f
JB		 3777 rx_desc = next_rxd;
3778 buffer_info = next_buffer;
1da177e4 3779 }
1da177e4 3780 rx_ring->next_to_clean = i;
72d64a43
JK		 3781
3782 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3783 if (cleaned_count)
3784 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3785
3786 return cleaned;
3787}
3788
3789/**
3790 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3791 * @adapter: board private structure
3792 **/
3793
3794static boolean_t
3795#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3796e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3797 struct e1000_rx_ring *rx_ring,
3798 int *work_done, int work_to_do)
2d7edb92 3799#else
581d708e
MC		 3800e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3801 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3802#endif
3803{
86c3d59f 3804 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3805 struct net_device *netdev = adapter->netdev;
3806 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3807 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3808 struct e1000_ps_page *ps_page;
3809 struct e1000_ps_page_dma *ps_page_dma;
86c3d59f 3810 struct sk_buff *skb, *next_skb;
2d7edb92
MC		 3811 unsigned int i, j;
3812 uint32_t length, staterr;
72d64a43 3813 int cleaned_count = 0;
2d7edb92
MC		 3814 boolean_t cleaned = FALSE;
3815
3816 i = rx_ring->next_to_clean;
3817 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3818 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
86c3d59f 3819 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3820
96838a40 3821 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3822 ps_page = &rx_ring->ps_page[i];
3823 ps_page_dma = &rx_ring->ps_page_dma[i];
3824#ifdef CONFIG_E1000_NAPI
96838a40 3825 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3826 break;
3827 (*work_done)++;
3828#endif
86c3d59f
JB		 3829 skb = buffer_info->skb;
3830
3831 if (++i == rx_ring->count) i = 0;
3832 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
3833 next_buffer = &rx_ring->buffer_info[i];
3834 next_skb = next_buffer->skb;
3835
2d7edb92 3836 cleaned = TRUE;
72d64a43 3837 cleaned_count++;
2d7edb92
MC		 3838 pci_unmap_single(pdev, buffer_info->dma,
3839 buffer_info->length,
3840 PCI_DMA_FROMDEVICE);
3841
96838a40 3842 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3843 E1000_DBG("%s: Packet Split buffers didn't pick up"
3844 " the full packet\n", netdev->name);
3845 dev_kfree_skb_irq(skb);
3846 goto next_desc;
3847 }
1da177e4 3848
96838a40 3849 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3850 dev_kfree_skb_irq(skb);
3851 goto next_desc;
3852 }
3853
3854 length = le16_to_cpu(rx_desc->wb.middle.length0);
3855
96838a40 3856 if (unlikely(!length)) {
2d7edb92
MC		 3857 E1000_DBG("%s: Last part of the packet spanning"
3858 " multiple descriptors\n", netdev->name);
3859 dev_kfree_skb_irq(skb);
3860 goto next_desc;
3861 }
3862
3863 /* Good Receive */
3864 skb_put(skb, length);
3865
96838a40
JB		 3866 for (j = 0; j < adapter->rx_ps_pages; j++) {
3867 if (!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92
MC		 3868 break;
3869
3870 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3871 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3872 ps_page_dma->ps_page_dma[j] = 0;
3873 skb_shinfo(skb)->frags[j].page =
3874 ps_page->ps_page[j];
3875 ps_page->ps_page[j] = NULL;
3876 skb_shinfo(skb)->frags[j].page_offset = 0;
3877 skb_shinfo(skb)->frags[j].size = length;
3878 skb_shinfo(skb)->nr_frags++;
3879 skb->len += length;
3880 skb->data_len += length;
3881 }
3882
3883 e1000_rx_checksum(adapter, staterr,
3884 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3885 skb->protocol = eth_type_trans(skb, netdev);
3886
96838a40 3887 if (likely(rx_desc->wb.upper.header_status &
b92ff8ee 3888 E1000_RXDPS_HDRSTAT_HDRSP))
e4c811c9 3889 adapter->rx_hdr_split++;
2d7edb92 3890#ifdef CONFIG_E1000_NAPI
96838a40 3891 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3892 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3893 le16_to_cpu(rx_desc->wb.middle.vlan) &
3894 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3895 } else {
3896 netif_receive_skb(skb);
3897 }
3898#else /* CONFIG_E1000_NAPI */
96838a40 3899 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3900 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3901 le16_to_cpu(rx_desc->wb.middle.vlan) &
3902 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3903 } else {
3904 netif_rx(skb);
3905 }
3906#endif /* CONFIG_E1000_NAPI */
3907 netdev->last_rx = jiffies;
7bfa4816
JK		 3908#ifdef CONFIG_E1000_MQ
3909 rx_ring->rx_stats.packets++;
3910 rx_ring->rx_stats.bytes += length;
3911#endif
2d7edb92
MC		 3912
3913next_desc:
3914 rx_desc->wb.middle.status_error &= ~0xFF;
3915 buffer_info->skb = NULL;
2d7edb92 3916
72d64a43
JK		 3917 /* return some buffers to hardware, one at a time is too slow */
3918 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3919 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3920 cleaned_count = 0;
3921 }
3922
86c3d59f
JB		 3923 rx_desc = next_rxd;
3924 buffer_info = next_buffer;
3925
683a38f3 3926 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3927 }
3928 rx_ring->next_to_clean = i;
72d64a43
JK		 3929
3930 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3931 if (cleaned_count)
3932 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3933
3934 return cleaned;
3935}
3936
3937/**
2d7edb92 3938 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3939 * @adapter: address of board private structure
3940 **/
3941
3942static void
581d708e 3943e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3944 struct e1000_rx_ring *rx_ring,
a292ca6e 3945 int cleaned_count)
1da177e4 3946{
1da177e4
LT		 3947 struct net_device *netdev = adapter->netdev;
3948 struct pci_dev *pdev = adapter->pdev;
3949 struct e1000_rx_desc *rx_desc;
3950 struct e1000_buffer *buffer_info;
3951 struct sk_buff *skb;
2648345f
MC		 3952 unsigned int i;
3953 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3954
3955 i = rx_ring->next_to_use;
3956 buffer_info = &rx_ring->buffer_info[i];
3957
a292ca6e
JK		 3958 while (cleaned_count--) {
3959 if (!(skb = buffer_info->skb))
3960 skb = dev_alloc_skb(bufsz);
3961 else {
3962 skb_trim(skb, 0);
3963 goto map_skb;
3964 }
3965
2648345f 3966
96838a40 3967 if (unlikely(!skb)) {
1da177e4 3968 /* Better luck next round */
72d64a43 3969 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3970 break;
3971 }
3972
2648345f 3973 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3974 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3975 struct sk_buff *oldskb = skb;
2648345f
MC		 3976 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3977 "at %p\n", bufsz, skb->data);
3978 /* Try again, without freeing the previous */
1da177e4 3979 skb = dev_alloc_skb(bufsz);
2648345f 3980 /* Failed allocation, critical failure */
1da177e4
LT		 3981 if (!skb) {
3982 dev_kfree_skb(oldskb);
3983 break;
3984 }
2648345f 3985
1da177e4
LT		 3986 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3987 /* give up */
3988 dev_kfree_skb(skb);
3989 dev_kfree_skb(oldskb);
3990 break; /* while !buffer_info->skb */
3991 } else {
2648345f 3992 /* Use new allocation */
1da177e4
LT		 3993 dev_kfree_skb(oldskb);
3994 }
3995 }
1da177e4
LT		 3996 /* Make buffer alignment 2 beyond a 16 byte boundary
3997 * this will result in a 16 byte aligned IP header after
3998 * the 14 byte MAC header is removed
3999 */
4000 skb_reserve(skb, NET_IP_ALIGN);
4001
4002 skb->dev = netdev;
4003
4004 buffer_info->skb = skb;
4005 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4006map_skb:
1da177e4
LT		 4007 buffer_info->dma = pci_map_single(pdev,
4008 skb->data,
4009 adapter->rx_buffer_len,
4010 PCI_DMA_FROMDEVICE);
4011
2648345f
MC		 4012 /* Fix for errata 23, can't cross 64kB boundary */
4013 if (!e1000_check_64k_bound(adapter,
4014 (void *)(unsigned long)buffer_info->dma,
4015 adapter->rx_buffer_len)) {
4016 DPRINTK(RX_ERR, ERR,
4017 "dma align check failed: %u bytes at %p\n",
4018 adapter->rx_buffer_len,
4019 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4020 dev_kfree_skb(skb);
4021 buffer_info->skb = NULL;
4022
2648345f 4023 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4024 adapter->rx_buffer_len,
4025 PCI_DMA_FROMDEVICE);
4026
4027 break; /* while !buffer_info->skb */
4028 }
1da177e4
LT		 4029 rx_desc = E1000_RX_DESC(*rx_ring, i);
4030 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4031
96838a40
JB		 4032 if (unlikely(++i == rx_ring->count))
4033 i = 0;
1da177e4
LT		 4034 buffer_info = &rx_ring->buffer_info[i];
4035 }
4036
b92ff8ee
JB		 4037 if (likely(rx_ring->next_to_use != i)) {
4038 rx_ring->next_to_use = i;
4039 if (unlikely(i-- == 0))
4040 i = (rx_ring->count - 1);
4041
4042 /* Force memory writes to complete before letting h/w
4043 * know there are new descriptors to fetch. (Only
4044 * applicable for weak-ordered memory model archs,
4045 * such as IA-64). */
4046 wmb();
4047 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4048 }
1da177e4
LT		 4049}
4050
2d7edb92
MC		 4051/**
4052 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4053 * @adapter: address of board private structure
4054 **/
4055
4056static void
581d708e 4057e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4058 struct e1000_rx_ring *rx_ring,
4059 int cleaned_count)
2d7edb92 4060{
2d7edb92
MC		 4061 struct net_device *netdev = adapter->netdev;
4062 struct pci_dev *pdev = adapter->pdev;
4063 union e1000_rx_desc_packet_split *rx_desc;
4064 struct e1000_buffer *buffer_info;
4065 struct e1000_ps_page *ps_page;
4066 struct e1000_ps_page_dma *ps_page_dma;
4067 struct sk_buff *skb;
4068 unsigned int i, j;
4069
4070 i = rx_ring->next_to_use;
4071 buffer_info = &rx_ring->buffer_info[i];
4072 ps_page = &rx_ring->ps_page[i];
4073 ps_page_dma = &rx_ring->ps_page_dma[i];
4074
72d64a43 4075 while (cleaned_count--) {
2d7edb92
MC		 4076 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4077
96838a40 4078 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4079 if (j < adapter->rx_ps_pages) {
4080 if (likely(!ps_page->ps_page[j])) {
4081 ps_page->ps_page[j] =
4082 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4083 if (unlikely(!ps_page->ps_page[j])) {
4084 adapter->alloc_rx_buff_failed++;
e4c811c9 4085 goto no_buffers;
b92ff8ee 4086 }
e4c811c9
MC		 4087 ps_page_dma->ps_page_dma[j] =
4088 pci_map_page(pdev,
4089 ps_page->ps_page[j],
4090 0, PAGE_SIZE,
4091 PCI_DMA_FROMDEVICE);
4092 }
4093 /* Refresh the desc even if buffer_addrs didn't
96838a40 4094 * change because each write-back erases
e4c811c9
MC		 4095 * this info.
4096 */
4097 rx_desc->read.buffer_addr[j+1] =
4098 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4099 } else
4100 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4101 }
4102
4103 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4104
b92ff8ee
JB		 4105 if (unlikely(!skb)) {
4106 adapter->alloc_rx_buff_failed++;
2d7edb92 4107 break;
b92ff8ee 4108 }
2d7edb92
MC		 4109
4110 /* Make buffer alignment 2 beyond a 16 byte boundary
4111 * this will result in a 16 byte aligned IP header after
4112 * the 14 byte MAC header is removed
4113 */
4114 skb_reserve(skb, NET_IP_ALIGN);
4115
4116 skb->dev = netdev;
4117
4118 buffer_info->skb = skb;
4119 buffer_info->length = adapter->rx_ps_bsize0;
4120 buffer_info->dma = pci_map_single(pdev, skb->data,
4121 adapter->rx_ps_bsize0,
4122 PCI_DMA_FROMDEVICE);
4123
4124 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4125
96838a40 4126 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4127 buffer_info = &rx_ring->buffer_info[i];
4128 ps_page = &rx_ring->ps_page[i];
4129 ps_page_dma = &rx_ring->ps_page_dma[i];
4130 }
4131
4132no_buffers:
b92ff8ee
JB		 4133 if (likely(rx_ring->next_to_use != i)) {
4134 rx_ring->next_to_use = i;
4135 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4136
4137 /* Force memory writes to complete before letting h/w
4138 * know there are new descriptors to fetch. (Only
4139 * applicable for weak-ordered memory model archs,
4140 * such as IA-64). */
4141 wmb();
4142 /* Hardware increments by 16 bytes, but packet split
4143 * descriptors are 32 bytes...so we increment tail
4144 * twice as much.
4145 */
4146 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4147 }
2d7edb92
MC		 4148}
4149
1da177e4
LT		 4150/**
4151 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4152 * @adapter:
4153 **/
4154
4155static void
4156e1000_smartspeed(struct e1000_adapter *adapter)
4157{
4158 uint16_t phy_status;
4159 uint16_t phy_ctrl;
4160
96838a40 4161 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4162 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4163 return;
4164
96838a40 4165 if (adapter->smartspeed == 0) {
1da177e4
LT		 4166 /* If Master/Slave config fault is asserted twice,
4167 * we assume back-to-back */
4168 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4169 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4170 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4171 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4172 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4173 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4174 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4175 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4176 phy_ctrl);
4177 adapter->smartspeed++;
96838a40 4178 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4179 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4180 &phy_ctrl)) {
4181 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4182 MII_CR_RESTART_AUTO_NEG);
4183 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4184 phy_ctrl);
4185 }
4186 }
4187 return;
96838a40 4188 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4189 /* If still no link, perhaps using 2/3 pair cable */
4190 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4191 phy_ctrl |= CR_1000T_MS_ENABLE;
4192 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4193 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4194 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4195 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4196 MII_CR_RESTART_AUTO_NEG);
4197 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4198 }
4199 }
4200 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4201 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4202 adapter->smartspeed = 0;
4203}
4204
4205/**
4206 * e1000_ioctl -
4207 * @netdev:
4208 * @ifreq:
4209 * @cmd:
4210 **/
4211
4212static int
4213e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4214{
4215 switch (cmd) {
4216 case SIOCGMIIPHY:
4217 case SIOCGMIIREG:
4218 case SIOCSMIIREG:
4219 return e1000_mii_ioctl(netdev, ifr, cmd);
4220 default:
4221 return -EOPNOTSUPP;
4222 }
4223}
4224
4225/**
4226 * e1000_mii_ioctl -
4227 * @netdev:
4228 * @ifreq:
4229 * @cmd:
4230 **/
4231
4232static int
4233e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4234{
60490fe0 4235 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4236 struct mii_ioctl_data *data = if_mii(ifr);
4237 int retval;
4238 uint16_t mii_reg;
4239 uint16_t spddplx;
97876fc6 4240 unsigned long flags;
1da177e4 4241
96838a40 4242 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4243 return -EOPNOTSUPP;
4244
4245 switch (cmd) {
4246 case SIOCGMIIPHY:
4247 data->phy_id = adapter->hw.phy_addr;
4248 break;
4249 case SIOCGMIIREG:
96838a40 4250 if (!capable(CAP_NET_ADMIN))
1da177e4 4251 return -EPERM;
97876fc6 4252 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4253 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4254 &data->val_out)) {
4255 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4256 return -EIO;
97876fc6
MC		 4257 }
4258 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4259 break;
4260 case SIOCSMIIREG:
96838a40 4261 if (!capable(CAP_NET_ADMIN))
1da177e4 4262 return -EPERM;
96838a40 4263 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4264 return -EFAULT;
4265 mii_reg = data->val_in;
97876fc6 4266 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4267 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4268 mii_reg)) {
4269 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4270 return -EIO;
97876fc6 4271 }
96838a40 4272 if (adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 4273 switch (data->reg_num) {
4274 case PHY_CTRL:
96838a40 4275 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4276 break;
96838a40 4277 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4278 adapter->hw.autoneg = 1;
4279 adapter->hw.autoneg_advertised = 0x2F;
4280 } else {
4281 if (mii_reg & 0x40)
4282 spddplx = SPEED_1000;
4283 else if (mii_reg & 0x2000)
4284 spddplx = SPEED_100;
4285 else
4286 spddplx = SPEED_10;
4287 spddplx += (mii_reg & 0x100)
4288 ? FULL_DUPLEX :
4289 HALF_DUPLEX;
4290 retval = e1000_set_spd_dplx(adapter,
4291 spddplx);
96838a40 4292 if (retval) {
97876fc6 4293 spin_unlock_irqrestore(
96838a40 4294 &adapter->stats_lock,
97876fc6 4295 flags);
1da177e4 4296 return retval;
97876fc6 4297 }
1da177e4 4298 }
96838a40 4299 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4300 e1000_down(adapter);
4301 e1000_up(adapter);
4302 } else
4303 e1000_reset(adapter);
4304 break;
4305 case M88E1000_PHY_SPEC_CTRL:
4306 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4307 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4308 spin_unlock_irqrestore(
4309 &adapter->stats_lock, flags);
1da177e4 4310 return -EIO;
97876fc6 4311 }
1da177e4
LT		 4312 break;
4313 }
4314 } else {
4315 switch (data->reg_num) {
4316 case PHY_CTRL:
96838a40 4317 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4318 break;
96838a40 4319 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4320 e1000_down(adapter);
4321 e1000_up(adapter);
4322 } else
4323 e1000_reset(adapter);
4324 break;
4325 }
4326 }
97876fc6 4327 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4328 break;
4329 default:
4330 return -EOPNOTSUPP;
4331 }
4332 return E1000_SUCCESS;
4333}
4334
4335void
4336e1000_pci_set_mwi(struct e1000_hw *hw)
4337{
4338 struct e1000_adapter *adapter = hw->back;
2648345f 4339 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4340
96838a40 4341 if (ret_val)
2648345f 4342 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4343}
4344
4345void
4346e1000_pci_clear_mwi(struct e1000_hw *hw)
4347{
4348 struct e1000_adapter *adapter = hw->back;
4349
4350 pci_clear_mwi(adapter->pdev);
4351}
4352
4353void
4354e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4355{
4356 struct e1000_adapter *adapter = hw->back;
4357
4358 pci_read_config_word(adapter->pdev, reg, value);
4359}
4360
4361void
4362e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4363{
4364 struct e1000_adapter *adapter = hw->back;
4365
4366 pci_write_config_word(adapter->pdev, reg, *value);
4367}
4368
4369uint32_t
4370e1000_io_read(struct e1000_hw *hw, unsigned long port)
4371{
4372 return inl(port);
4373}
4374
4375void
4376e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4377{
4378 outl(value, port);
4379}
4380
4381static void
4382e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4383{
60490fe0 4384 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4385 uint32_t ctrl, rctl;
4386
4387 e1000_irq_disable(adapter);
4388 adapter->vlgrp = grp;
4389
96838a40 4390 if (grp) {
1da177e4
LT		 4391 /* enable VLAN tag insert/strip */
4392 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4393 ctrl |= E1000_CTRL_VME;
4394 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4395
4396 /* enable VLAN receive filtering */
4397 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4398 rctl |= E1000_RCTL_VFE;
4399 rctl &= ~E1000_RCTL_CFIEN;
4400 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4401 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4402 } else {
4403 /* disable VLAN tag insert/strip */
4404 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4405 ctrl &= ~E1000_CTRL_VME;
4406 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4407
4408 /* disable VLAN filtering */
4409 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4410 rctl &= ~E1000_RCTL_VFE;
4411 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4412 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4413 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4414 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4415 }
1da177e4
LT		 4416 }
4417
4418 e1000_irq_enable(adapter);
4419}
4420
4421static void
4422e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4423{
60490fe0 4424 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4425 uint32_t vfta, index;
96838a40
JB		 4426
4427 if ((adapter->hw.mng_cookie.status &
4428 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4429 (vid == adapter->mng_vlan_id))
2d7edb92 4430 return;
1da177e4
LT		 4431 /* add VID to filter table */
4432 index = (vid >> 5) & 0x7F;
4433 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4434 vfta |= (1 << (vid & 0x1F));
4435 e1000_write_vfta(&adapter->hw, index, vfta);
4436}
4437
4438static void
4439e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4440{
60490fe0 4441 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4442 uint32_t vfta, index;
4443
4444 e1000_irq_disable(adapter);
4445
96838a40 4446 if (adapter->vlgrp)
1da177e4
LT		 4447 adapter->vlgrp->vlan_devices[vid] = NULL;
4448
4449 e1000_irq_enable(adapter);
4450
96838a40
JB		 4451 if ((adapter->hw.mng_cookie.status &
4452 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4453 (vid == adapter->mng_vlan_id)) {
4454 /* release control to f/w */
4455 e1000_release_hw_control(adapter);
2d7edb92 4456 return;
ff147013
JK		 4457 }
4458
1da177e4
LT		 4459 /* remove VID from filter table */
4460 index = (vid >> 5) & 0x7F;
4461 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4462 vfta &= ~(1 << (vid & 0x1F));
4463 e1000_write_vfta(&adapter->hw, index, vfta);
4464}
4465
4466static void
4467e1000_restore_vlan(struct e1000_adapter *adapter)
4468{
4469 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4470
96838a40 4471 if (adapter->vlgrp) {
1da177e4 4472 uint16_t vid;
96838a40
JB		 4473 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4474 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4475 continue;
4476 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4477 }
4478 }
4479}
4480
4481int
4482e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4483{
4484 adapter->hw.autoneg = 0;
4485
6921368f 4486 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4487 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4488 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4489 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4490 return -EINVAL;
4491 }
4492
96838a40 4493 switch (spddplx) {
1da177e4
LT		 4494 case SPEED_10 + DUPLEX_HALF:
4495 adapter->hw.forced_speed_duplex = e1000_10_half;
4496 break;
4497 case SPEED_10 + DUPLEX_FULL:
4498 adapter->hw.forced_speed_duplex = e1000_10_full;
4499 break;
4500 case SPEED_100 + DUPLEX_HALF:
4501 adapter->hw.forced_speed_duplex = e1000_100_half;
4502 break;
4503 case SPEED_100 + DUPLEX_FULL:
4504 adapter->hw.forced_speed_duplex = e1000_100_full;
4505 break;
4506 case SPEED_1000 + DUPLEX_FULL:
4507 adapter->hw.autoneg = 1;
4508 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4509 break;
4510 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4511 default:
2648345f 4512 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4513 return -EINVAL;
4514 }
4515 return 0;
4516}
4517
b6a1d5f8 4518#ifdef CONFIG_PM
2f82665f
JB		 4519/* these functions save and restore 16 or 64 dwords (64-256 bytes) of config
4520 * space versus the 64 bytes that pci_[save|restore]_state handle
4521 */
4522#define PCIE_CONFIG_SPACE_LEN 256
4523#define PCI_CONFIG_SPACE_LEN 64
4524static int
4525e1000_pci_save_state(struct e1000_adapter *adapter)
4526{
4527 struct pci_dev *dev = adapter->pdev;
4528 int size;
4529 int i;
4530 if (adapter->hw.mac_type >= e1000_82571)
4531 size = PCIE_CONFIG_SPACE_LEN;
4532 else
4533 size = PCI_CONFIG_SPACE_LEN;
4534
4535 WARN_ON(adapter->config_space != NULL);
4536
4537 adapter->config_space = kmalloc(size, GFP_KERNEL);
4538 if (!adapter->config_space) {
4539 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4540 return -ENOMEM;
4541 }
4542 for (i = 0; i < (size / 4); i++)
4543 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4544 return 0;
4545}
4546
4547static void
4548e1000_pci_restore_state(struct e1000_adapter *adapter)
4549{
4550 struct pci_dev *dev = adapter->pdev;
4551 int size;
4552 int i;
4553 if (adapter->config_space == NULL)
4554 return;
4555 if (adapter->hw.mac_type >= e1000_82571)
4556 size = PCIE_CONFIG_SPACE_LEN;
4557 else
4558 size = PCI_CONFIG_SPACE_LEN;
4559 for (i = 0; i < (size / 4); i++)
4560 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4561 kfree(adapter->config_space);
4562 adapter->config_space = NULL;
4563 return;
4564}
4565#endif /* CONFIG_PM */
4566
1da177e4 4567static int
829ca9a3 4568e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4569{
4570 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4571 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4572 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4573 uint32_t wufc = adapter->wol;
240b1710 4574 int retval = 0;
1da177e4
LT		 4575
4576 netif_device_detach(netdev);
4577
96838a40 4578 if (netif_running(netdev))
1da177e4
LT		 4579 e1000_down(adapter);
4580
2f82665f
JB		 4581#ifdef CONFIG_PM
4582 /* implement our own version of pci_save_state(pdev) because pci
4583 * express adapters have larger 256 byte config spaces */
4584 retval = e1000_pci_save_state(adapter);
4585 if (retval)
4586 return retval;
4587#endif
4588
1da177e4 4589 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4590 if (status & E1000_STATUS_LU)
1da177e4
LT		 4591 wufc &= ~E1000_WUFC_LNKC;
4592
96838a40 4593 if (wufc) {
1da177e4
LT		 4594 e1000_setup_rctl(adapter);
4595 e1000_set_multi(netdev);
4596
4597 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4598 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4599 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4600 rctl |= E1000_RCTL_MPE;
4601 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4602 }
4603
96838a40 4604 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4605 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4606 /* advertise wake from D3Cold */
4607 #define E1000_CTRL_ADVD3WUC 0x00100000
4608 /* phy power management enable */
4609 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4610 ctrl |= E1000_CTRL_ADVD3WUC |
4611 E1000_CTRL_EN_PHY_PWR_MGMT;
4612 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4613 }
4614
96838a40 4615 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4616 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4617 /* keep the laser running in D3 */
4618 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4619 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4620 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4621 }
4622
2d7edb92
MC		 4623 /* Allow time for pending master requests to run */
4624 e1000_disable_pciex_master(&adapter->hw);
4625
1da177e4
LT		 4626 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4627 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
240b1710
JK		 4628 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4629 if (retval)
4630 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4631 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4632 if (retval)
4633 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4634 } else {
4635 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4636 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
240b1710
JK		 4637 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4638 if (retval)
4639 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4640 retval = pci_enable_wake(pdev, PCI_D3cold, 0); /* 4 == D3 cold */
4641 if (retval)
4642 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4643 }
4644
96838a40 4645 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4646 adapter->hw.media_type == e1000_media_type_copper) {
4647 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4648 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4649 manc |= E1000_MANC_ARP_EN;
4650 E1000_WRITE_REG(&adapter->hw, MANC, manc);
240b1710
JK		 4651 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4652 if (retval)
4653 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4654 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4655 if (retval)
4656 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4657 }
4658 }
4659
b55ccb35
JK		 4660 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4661 * would have already happened in close and is redundant. */
4662 e1000_release_hw_control(adapter);
2d7edb92 4663
1da177e4 4664 pci_disable_device(pdev);
240b1710
JK		 4665
4666 retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
4667 if (retval)
4668 DPRINTK(PROBE, ERR, "Error in setting power state\n");
1da177e4
LT		 4669
4670 return 0;
4671}
4672
2f82665f 4673#ifdef CONFIG_PM
1da177e4
LT		 4674static int
4675e1000_resume(struct pci_dev *pdev)
4676{
4677 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4678 struct e1000_adapter *adapter = netdev_priv(netdev);
240b1710 4679 int retval;
b55ccb35 4680 uint32_t manc, ret_val;
1da177e4 4681
240b1710
JK		 4682 retval = pci_set_power_state(pdev, PCI_D0);
4683 if (retval)
4684 DPRINTK(PROBE, ERR, "Error in setting power state\n");
2f82665f 4685 e1000_pci_restore_state(adapter);
2b02893e 4686 ret_val = pci_enable_device(pdev);
a4cb847d 4687 pci_set_master(pdev);
1da177e4 4688
240b1710
JK		 4689 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4690 if (retval)
4691 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4692 retval = pci_enable_wake(pdev, PCI_D3cold, 0);
4693 if (retval)
4694 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4695
4696 e1000_reset(adapter);
4697 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4698
96838a40 4699 if (netif_running(netdev))
1da177e4
LT		 4700 e1000_up(adapter);
4701
4702 netif_device_attach(netdev);
4703
96838a40 4704 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4705 adapter->hw.media_type == e1000_media_type_copper) {
4706 manc = E1000_READ_REG(&adapter->hw, MANC);
4707 manc &= ~(E1000_MANC_ARP_EN);
4708 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4709 }
4710
b55ccb35
JK		 4711 /* If the controller is 82573 and f/w is AMT, do not set
4712 * DRV_LOAD until the interface is up. For all other cases,
4713 * let the f/w know that the h/w is now under the control
4714 * of the driver. */
4715 if (adapter->hw.mac_type != e1000_82573 ||
4716 !e1000_check_mng_mode(&adapter->hw))
4717 e1000_get_hw_control(adapter);
2d7edb92 4718
1da177e4
LT		 4719 return 0;
4720}
4721#endif
1da177e4
LT		 4722#ifdef CONFIG_NET_POLL_CONTROLLER
4723/*
4724 * Polling 'interrupt' - used by things like netconsole to send skbs
4725 * without having to re-enable interrupts. It's not called while
4726 * the interrupt routine is executing.
4727 */
4728static void
2648345f 4729e1000_netpoll(struct net_device *netdev)
1da177e4 4730{
60490fe0 4731 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4732 disable_irq(adapter->pdev->irq);
4733 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4734 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4735#ifndef CONFIG_E1000_NAPI
4736 adapter->clean_rx(adapter, adapter->rx_ring);
4737#endif
1da177e4
LT		 4738 enable_irq(adapter->pdev->irq);
4739}
4740#endif
4741
4742/* e1000_main.c */
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