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1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
3ad2cc67 40static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
4ee9c020 46#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 48static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 83 INTEL_E1000_ETHERNET_DEVICE(0x105E),
84 INTEL_E1000_ETHERNET_DEVICE(0x105F),
85 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 86 INTEL_E1000_ETHERNET_DEVICE(0x1075),
87 INTEL_E1000_ETHERNET_DEVICE(0x1076),
88 INTEL_E1000_ETHERNET_DEVICE(0x1077),
89 INTEL_E1000_ETHERNET_DEVICE(0x1078),
90 INTEL_E1000_ETHERNET_DEVICE(0x1079),
91 INTEL_E1000_ETHERNET_DEVICE(0x107A),
92 INTEL_E1000_ETHERNET_DEVICE(0x107B),
93 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 94 INTEL_E1000_ETHERNET_DEVICE(0x107D),
95 INTEL_E1000_ETHERNET_DEVICE(0x107E),
96 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 97 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 98 INTEL_E1000_ETHERNET_DEVICE(0x108B),
99 INTEL_E1000_ETHERNET_DEVICE(0x108C),
b7ee49db 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
1da177e4
LT		 103 /* required last entry */
104 {0,}
105};
106
107MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
108
109int e1000_up(struct e1000_adapter *adapter);
110void e1000_down(struct e1000_adapter *adapter);
111void e1000_reset(struct e1000_adapter *adapter);
112int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 113int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
114int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
115void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
116void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 117static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
118 struct e1000_tx_ring *txdr);
119static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
120 struct e1000_rx_ring *rxdr);
121static void e1000_free_tx_resources(struct e1000_adapter *adapter,
122 struct e1000_tx_ring *tx_ring);
123static void e1000_free_rx_resources(struct e1000_adapter *adapter,
124 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 125void e1000_update_stats(struct e1000_adapter *adapter);
126
127/* Local Function Prototypes */
128
129static int e1000_init_module(void);
130static void e1000_exit_module(void);
131static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
132static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 133static int e1000_alloc_queues(struct e1000_adapter *adapter);
134#ifdef CONFIG_E1000_MQ
135static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
136#endif
1da177e4
LT		 137static int e1000_sw_init(struct e1000_adapter *adapter);
138static int e1000_open(struct net_device *netdev);
139static int e1000_close(struct net_device *netdev);
140static void e1000_configure_tx(struct e1000_adapter *adapter);
141static void e1000_configure_rx(struct e1000_adapter *adapter);
142static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 143static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
144static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
145static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
146 struct e1000_tx_ring *tx_ring);
147static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
148 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 149static void e1000_set_multi(struct net_device *netdev);
150static void e1000_update_phy_info(unsigned long data);
151static void e1000_watchdog(unsigned long data);
152static void e1000_watchdog_task(struct e1000_adapter *adapter);
153static void e1000_82547_tx_fifo_stall(unsigned long data);
154static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
155static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
156static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
157static int e1000_set_mac(struct net_device *netdev, void *p);
158static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 159static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
160 struct e1000_tx_ring *tx_ring);
1da177e4 161#ifdef CONFIG_E1000_NAPI
581d708e 162static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 163static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 164 struct e1000_rx_ring *rx_ring,
1da177e4 165 int *work_done, int work_to_do);
2d7edb92 166static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 167 struct e1000_rx_ring *rx_ring,
2d7edb92 168 int *work_done, int work_to_do);
1da177e4 169#else
581d708e
MC		 170static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
171 struct e1000_rx_ring *rx_ring);
172static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
173 struct e1000_rx_ring *rx_ring);
1da177e4 174#endif
581d708e 175static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 176 struct e1000_rx_ring *rx_ring,
177 int cleaned_count);
581d708e 178static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 179 struct e1000_rx_ring *rx_ring,
180 int cleaned_count);
1da177e4
LT		 181static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
182static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
183 int cmd);
184void e1000_set_ethtool_ops(struct net_device *netdev);
185static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
186static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
187static void e1000_tx_timeout(struct net_device *dev);
188static void e1000_tx_timeout_task(struct net_device *dev);
189static void e1000_smartspeed(struct e1000_adapter *adapter);
190static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
191 struct sk_buff *skb);
192
193static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
194static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
195static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
196static void e1000_restore_vlan(struct e1000_adapter *adapter);
197
1da177e4 198#ifdef CONFIG_PM
977e74b5 199static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 200static int e1000_resume(struct pci_dev *pdev);
201#endif
202
203#ifdef CONFIG_NET_POLL_CONTROLLER
204/* for netdump / net console */
205static void e1000_netpoll (struct net_device *netdev);
206#endif
207
24025e4e
MC		 208#ifdef CONFIG_E1000_MQ
209/* for multiple Rx queues */
210void e1000_rx_schedule(void *data);
211#endif
212
1da177e4
LT		 213/* Exported from other modules */
214
215extern void e1000_check_options(struct e1000_adapter *adapter);
216
217static struct pci_driver e1000_driver = {
218 .name = e1000_driver_name,
219 .id_table = e1000_pci_tbl,
220 .probe = e1000_probe,
221 .remove = __devexit_p(e1000_remove),
222 /* Power Managment Hooks */
223#ifdef CONFIG_PM
224 .suspend = e1000_suspend,
225 .resume = e1000_resume
226#endif
227};
228
229MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
230MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
231MODULE_LICENSE("GPL");
232MODULE_VERSION(DRV_VERSION);
233
234static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
235module_param(debug, int, 0);
236MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
237
238/**
239 * e1000_init_module - Driver Registration Routine
240 *
241 * e1000_init_module is the first routine called when the driver is
242 * loaded. All it does is register with the PCI subsystem.
243 **/
244
245static int __init
246e1000_init_module(void)
247{
248 int ret;
249 printk(KERN_INFO "%s - version %s\n",
250 e1000_driver_string, e1000_driver_version);
251
252 printk(KERN_INFO "%s\n", e1000_copyright);
253
254 ret = pci_module_init(&e1000_driver);
8b378def 255
1da177e4
LT		 256 return ret;
257}
258
259module_init(e1000_init_module);
260
261/**
262 * e1000_exit_module - Driver Exit Cleanup Routine
263 *
264 * e1000_exit_module is called just before the driver is removed
265 * from memory.
266 **/
267
268static void __exit
269e1000_exit_module(void)
270{
1da177e4
LT		 271 pci_unregister_driver(&e1000_driver);
272}
273
274module_exit(e1000_exit_module);
275
276/**
277 * e1000_irq_disable - Mask off interrupt generation on the NIC
278 * @adapter: board private structure
279 **/
280
281static inline void
282e1000_irq_disable(struct e1000_adapter *adapter)
283{
284 atomic_inc(&adapter->irq_sem);
285 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
286 E1000_WRITE_FLUSH(&adapter->hw);
287 synchronize_irq(adapter->pdev->irq);
288}
289
290/**
291 * e1000_irq_enable - Enable default interrupt generation settings
292 * @adapter: board private structure
293 **/
294
295static inline void
296e1000_irq_enable(struct e1000_adapter *adapter)
297{
96838a40 298 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 299 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
300 E1000_WRITE_FLUSH(&adapter->hw);
301 }
302}
3ad2cc67
AB		 303
304static void
2d7edb92
MC		 305e1000_update_mng_vlan(struct e1000_adapter *adapter)
306{
307 struct net_device *netdev = adapter->netdev;
308 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
309 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 310 if (adapter->vlgrp) {
311 if (!adapter->vlgrp->vlan_devices[vid]) {
312 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 313 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
314 e1000_vlan_rx_add_vid(netdev, vid);
315 adapter->mng_vlan_id = vid;
316 } else
317 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 318
319 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
320 (vid != old_vid) &&
2d7edb92
MC		 321 !adapter->vlgrp->vlan_devices[old_vid])
322 e1000_vlan_rx_kill_vid(netdev, old_vid);
323 }
324 }
325}
b55ccb35
JK		 326
327/**
328 * e1000_release_hw_control - release control of the h/w to f/w
329 * @adapter: address of board private structure
330 *
331 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
332 * For ASF and Pass Through versions of f/w this means that the
333 * driver is no longer loaded. For AMT version (only with 82573) i
334 * of the f/w this means that the netowrk i/f is closed.
335 *
336 **/
337
338static inline void
339e1000_release_hw_control(struct e1000_adapter *adapter)
340{
341 uint32_t ctrl_ext;
342 uint32_t swsm;
343
344 /* Let firmware taken over control of h/w */
345 switch (adapter->hw.mac_type) {
346 case e1000_82571:
347 case e1000_82572:
348 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
349 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
350 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
351 break;
352 case e1000_82573:
353 swsm = E1000_READ_REG(&adapter->hw, SWSM);
354 E1000_WRITE_REG(&adapter->hw, SWSM,
355 swsm & ~E1000_SWSM_DRV_LOAD);
356 default:
357 break;
358 }
359}
360
361/**
362 * e1000_get_hw_control - get control of the h/w from f/w
363 * @adapter: address of board private structure
364 *
365 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
366 * For ASF and Pass Through versions of f/w this means that
367 * the driver is loaded. For AMT version (only with 82573)
368 * of the f/w this means that the netowrk i/f is open.
369 *
370 **/
371
372static inline void
373e1000_get_hw_control(struct e1000_adapter *adapter)
374{
375 uint32_t ctrl_ext;
376 uint32_t swsm;
377 /* Let firmware know the driver has taken over */
378 switch (adapter->hw.mac_type) {
379 case e1000_82571:
380 case e1000_82572:
381 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
382 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
383 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
384 break;
385 case e1000_82573:
386 swsm = E1000_READ_REG(&adapter->hw, SWSM);
387 E1000_WRITE_REG(&adapter->hw, SWSM,
388 swsm | E1000_SWSM_DRV_LOAD);
389 break;
390 default:
391 break;
392 }
393}
394
1da177e4
LT		 395int
396e1000_up(struct e1000_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
581d708e 399 int i, err;
1da177e4
LT		 400
401 /* hardware has been reset, we need to reload some things */
402
403 /* Reset the PHY if it was previously powered down */
96838a40 404 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 405 uint16_t mii_reg;
406 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
96838a40 407 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4
LT		 408 e1000_phy_reset(&adapter->hw);
409 }
410
411 e1000_set_multi(netdev);
412
413 e1000_restore_vlan(adapter);
414
415 e1000_configure_tx(adapter);
416 e1000_setup_rctl(adapter);
417 e1000_configure_rx(adapter);
72d64a43
JK		 418 /* call E1000_DESC_UNUSED which always leaves
419 * at least 1 descriptor unused to make sure
420 * next_to_use != next_to_clean */
f56799ea 421 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 422 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 423 adapter->alloc_rx_buf(adapter, ring,
424 E1000_DESC_UNUSED(ring));
f56799ea 425 }
1da177e4 426
fa4f7ef3 427#ifdef CONFIG_PCI_MSI
96838a40 428 if (adapter->hw.mac_type > e1000_82547_rev_2) {
fa4f7ef3 429 adapter->have_msi = TRUE;
96838a40 430 if ((err = pci_enable_msi(adapter->pdev))) {
fa4f7ef3
MC		 431 DPRINTK(PROBE, ERR,
432 "Unable to allocate MSI interrupt Error: %d\n", err);
433 adapter->have_msi = FALSE;
434 }
435 }
436#endif
96838a40 437 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
1da177e4 438 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 439 netdev->name, netdev))) {
440 DPRINTK(PROBE, ERR,
441 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 442 return err;
2648345f 443 }
1da177e4 444
7bfa4816
JK		 445#ifdef CONFIG_E1000_MQ
446 e1000_setup_queue_mapping(adapter);
447#endif
448
449 adapter->tx_queue_len = netdev->tx_queue_len;
450
1da177e4 451 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 452
453#ifdef CONFIG_E1000_NAPI
454 netif_poll_enable(netdev);
455#endif
5de55624
MC		 456 e1000_irq_enable(adapter);
457
1da177e4
LT		 458 return 0;
459}
460
461void
462e1000_down(struct e1000_adapter *adapter)
463{
464 struct net_device *netdev = adapter->netdev;
57128197
JK		 465 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
466 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 467
468 e1000_irq_disable(adapter);
24025e4e
MC		 469#ifdef CONFIG_E1000_MQ
470 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
471#endif
1da177e4 472 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3 473#ifdef CONFIG_PCI_MSI
96838a40 474 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
fa4f7ef3
MC		 475 adapter->have_msi == TRUE)
476 pci_disable_msi(adapter->pdev);
477#endif
1da177e4
LT		 478 del_timer_sync(&adapter->tx_fifo_stall_timer);
479 del_timer_sync(&adapter->watchdog_timer);
480 del_timer_sync(&adapter->phy_info_timer);
481
482#ifdef CONFIG_E1000_NAPI
483 netif_poll_disable(netdev);
484#endif
7bfa4816 485 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 486 adapter->link_speed = 0;
487 adapter->link_duplex = 0;
488 netif_carrier_off(netdev);
489 netif_stop_queue(netdev);
490
491 e1000_reset(adapter);
581d708e
MC		 492 e1000_clean_all_tx_rings(adapter);
493 e1000_clean_all_rx_rings(adapter);
1da177e4 494
57128197
JK		 495 /* Power down the PHY so no link is implied when interface is down *
496 * The PHY cannot be powered down if any of the following is TRUE *
497 * (a) WoL is enabled
498 * (b) AMT is active
499 * (c) SoL/IDER session is active */
500 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 501 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 502 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
503 !mng_mode_enabled &&
504 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 505 uint16_t mii_reg;
506 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
507 mii_reg |= MII_CR_POWER_DOWN;
508 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 509 mdelay(1);
1da177e4
LT		 510 }
511}
512
513void
514e1000_reset(struct e1000_adapter *adapter)
515{
2d7edb92 516 uint32_t pba, manc;
1125ecbc 517 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 518
519 /* Repartition Pba for greater than 9k mtu
520 * To take effect CTRL.RST is required.
521 */
522
2d7edb92
MC		 523 switch (adapter->hw.mac_type) {
524 case e1000_82547:
0e6ef3e0 525 case e1000_82547_rev_2:
2d7edb92
MC		 526 pba = E1000_PBA_30K;
527 break;
868d5309
MC		 528 case e1000_82571:
529 case e1000_82572:
530 pba = E1000_PBA_38K;
531 break;
2d7edb92
MC		 532 case e1000_82573:
533 pba = E1000_PBA_12K;
534 break;
535 default:
536 pba = E1000_PBA_48K;
537 break;
538 }
539
96838a40 540 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 541 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 542 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 543
544
96838a40 545 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 546 adapter->tx_fifo_head = 0;
547 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
548 adapter->tx_fifo_size =
549 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
550 atomic_set(&adapter->tx_fifo_stall, 0);
551 }
2d7edb92 552
1da177e4
LT		 553 E1000_WRITE_REG(&adapter->hw, PBA, pba);
554
555 /* flow control settings */
f11b7f85
JK		 556 /* Set the FC high water mark to 90% of the FIFO size.
557 * Required to clear last 3 LSB */
558 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
559
560 adapter->hw.fc_high_water = fc_high_water_mark;
561 adapter->hw.fc_low_water = fc_high_water_mark - 8;
1da177e4
LT		 562 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
563 adapter->hw.fc_send_xon = 1;
564 adapter->hw.fc = adapter->hw.original_fc;
565
2d7edb92 566 /* Allow time for pending master requests to run */
1da177e4 567 e1000_reset_hw(&adapter->hw);
96838a40 568 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 569 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 570 if (e1000_init_hw(&adapter->hw))
1da177e4 571 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 572 e1000_update_mng_vlan(adapter);
1da177e4
LT		 573 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
574 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
575
576 e1000_reset_adaptive(&adapter->hw);
577 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 578 if (adapter->en_mng_pt) {
579 manc = E1000_READ_REG(&adapter->hw, MANC);
580 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
581 E1000_WRITE_REG(&adapter->hw, MANC, manc);
582 }
1da177e4
LT		 583}
584
585/**
586 * e1000_probe - Device Initialization Routine
587 * @pdev: PCI device information struct
588 * @ent: entry in e1000_pci_tbl
589 *
590 * Returns 0 on success, negative on failure
591 *
592 * e1000_probe initializes an adapter identified by a pci_dev structure.
593 * The OS initialization, configuring of the adapter private structure,
594 * and a hardware reset occur.
595 **/
596
597static int __devinit
598e1000_probe(struct pci_dev *pdev,
599 const struct pci_device_id *ent)
600{
601 struct net_device *netdev;
602 struct e1000_adapter *adapter;
2d7edb92 603 unsigned long mmio_start, mmio_len;
2d7edb92 604
1da177e4 605 static int cards_found = 0;
2d7edb92 606 int i, err, pci_using_dac;
1da177e4
LT		 607 uint16_t eeprom_data;
608 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 609 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 610 return err;
611
96838a40 612 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 613 pci_using_dac = 1;
614 } else {
96838a40 615 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 616 E1000_ERR("No usable DMA configuration, aborting\n");
617 return err;
618 }
619 pci_using_dac = 0;
620 }
621
96838a40 622 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 623 return err;
624
625 pci_set_master(pdev);
626
627 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 628 if (!netdev) {
1da177e4
LT		 629 err = -ENOMEM;
630 goto err_alloc_etherdev;
631 }
632
633 SET_MODULE_OWNER(netdev);
634 SET_NETDEV_DEV(netdev, &pdev->dev);
635
636 pci_set_drvdata(pdev, netdev);
60490fe0 637 adapter = netdev_priv(netdev);
1da177e4
LT		 638 adapter->netdev = netdev;
639 adapter->pdev = pdev;
640 adapter->hw.back = adapter;
641 adapter->msg_enable = (1 << debug) - 1;
642
643 mmio_start = pci_resource_start(pdev, BAR_0);
644 mmio_len = pci_resource_len(pdev, BAR_0);
645
646 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 647 if (!adapter->hw.hw_addr) {
1da177e4
LT		 648 err = -EIO;
649 goto err_ioremap;
650 }
651
96838a40
JB		 652 for (i = BAR_1; i <= BAR_5; i++) {
653 if (pci_resource_len(pdev, i) == 0)
1da177e4 654 continue;
96838a40 655 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 656 adapter->hw.io_base = pci_resource_start(pdev, i);
657 break;
658 }
659 }
660
661 netdev->open = &e1000_open;
662 netdev->stop = &e1000_close;
663 netdev->hard_start_xmit = &e1000_xmit_frame;
664 netdev->get_stats = &e1000_get_stats;
665 netdev->set_multicast_list = &e1000_set_multi;
666 netdev->set_mac_address = &e1000_set_mac;
667 netdev->change_mtu = &e1000_change_mtu;
668 netdev->do_ioctl = &e1000_ioctl;
669 e1000_set_ethtool_ops(netdev);
670 netdev->tx_timeout = &e1000_tx_timeout;
671 netdev->watchdog_timeo = 5 * HZ;
672#ifdef CONFIG_E1000_NAPI
673 netdev->poll = &e1000_clean;
674 netdev->weight = 64;
675#endif
676 netdev->vlan_rx_register = e1000_vlan_rx_register;
677 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
678 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
679#ifdef CONFIG_NET_POLL_CONTROLLER
680 netdev->poll_controller = e1000_netpoll;
681#endif
682 strcpy(netdev->name, pci_name(pdev));
683
684 netdev->mem_start = mmio_start;
685 netdev->mem_end = mmio_start + mmio_len;
686 netdev->base_addr = adapter->hw.io_base;
687
688 adapter->bd_number = cards_found;
689
690 /* setup the private structure */
691
96838a40 692 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 693 goto err_sw_init;
694
96838a40 695 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 696 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
697
96838a40 698 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 699 netdev->features = NETIF_F_SG |
700 NETIF_F_HW_CSUM |
701 NETIF_F_HW_VLAN_TX |
702 NETIF_F_HW_VLAN_RX |
703 NETIF_F_HW_VLAN_FILTER;
704 }
705
706#ifdef NETIF_F_TSO
96838a40 707 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 708 (adapter->hw.mac_type != e1000_82547))
709 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 710
711#ifdef NETIF_F_TSO_IPV6
96838a40 712 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 713 netdev->features |= NETIF_F_TSO_IPV6;
714#endif
1da177e4 715#endif
96838a40 716 if (pci_using_dac)
1da177e4
LT		 717 netdev->features |= NETIF_F_HIGHDMA;
718
719 /* hard_start_xmit is safe against parallel locking */
720 netdev->features |= NETIF_F_LLTX;
721
2d7edb92
MC		 722 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
723
96838a40 724 /* before reading the EEPROM, reset the controller to
1da177e4 725 * put the device in a known good starting state */
96838a40 726
1da177e4
LT		 727 e1000_reset_hw(&adapter->hw);
728
729 /* make sure the EEPROM is good */
730
96838a40 731 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 732 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
733 err = -EIO;
734 goto err_eeprom;
735 }
736
737 /* copy the MAC address out of the EEPROM */
738
96838a40 739 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 740 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
741 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 742 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 743
96838a40 744 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 745 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
746 err = -EIO;
747 goto err_eeprom;
748 }
749
750 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
751
752 e1000_get_bus_info(&adapter->hw);
753
754 init_timer(&adapter->tx_fifo_stall_timer);
755 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
756 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
757
758 init_timer(&adapter->watchdog_timer);
759 adapter->watchdog_timer.function = &e1000_watchdog;
760 adapter->watchdog_timer.data = (unsigned long) adapter;
761
762 INIT_WORK(&adapter->watchdog_task,
763 (void (*)(void *))e1000_watchdog_task, adapter);
764
765 init_timer(&adapter->phy_info_timer);
766 adapter->phy_info_timer.function = &e1000_update_phy_info;
767 adapter->phy_info_timer.data = (unsigned long) adapter;
768
769 INIT_WORK(&adapter->tx_timeout_task,
770 (void (*)(void *))e1000_tx_timeout_task, netdev);
771
772 /* we're going to reset, so assume we have no link for now */
773
774 netif_carrier_off(netdev);
775 netif_stop_queue(netdev);
776
777 e1000_check_options(adapter);
778
779 /* Initial Wake on LAN setting
780 * If APM wake is enabled in the EEPROM,
781 * enable the ACPI Magic Packet filter
782 */
783
96838a40 784 switch (adapter->hw.mac_type) {
1da177e4
LT		 785 case e1000_82542_rev2_0:
786 case e1000_82542_rev2_1:
787 case e1000_82543:
788 break;
789 case e1000_82544:
790 e1000_read_eeprom(&adapter->hw,
791 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
792 eeprom_apme_mask = E1000_EEPROM_82544_APM;
793 break;
794 case e1000_82546:
795 case e1000_82546_rev_3:
fd803241 796 case e1000_82571:
96838a40 797 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 798 e1000_read_eeprom(&adapter->hw,
799 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
800 break;
801 }
802 /* Fall Through */
803 default:
804 e1000_read_eeprom(&adapter->hw,
805 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
806 break;
807 }
96838a40 808 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 809 adapter->wol |= E1000_WUFC_MAG;
810
fb3d47d4
JK		 811 /* print bus type/speed/width info */
812 {
813 struct e1000_hw *hw = &adapter->hw;
814 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
815 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
816 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
817 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
818 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
819 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
820 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
821 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
822 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
823 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
824 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
825 "32-bit"));
826 }
827
828 for (i = 0; i < 6; i++)
829 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
830
1da177e4
LT		 831 /* reset the hardware with the new settings */
832 e1000_reset(adapter);
833
b55ccb35
JK		 834 /* If the controller is 82573 and f/w is AMT, do not set
835 * DRV_LOAD until the interface is up. For all other cases,
836 * let the f/w know that the h/w is now under the control
837 * of the driver. */
838 if (adapter->hw.mac_type != e1000_82573 ||
839 !e1000_check_mng_mode(&adapter->hw))
840 e1000_get_hw_control(adapter);
2d7edb92 841
1da177e4 842 strcpy(netdev->name, "eth%d");
96838a40 843 if ((err = register_netdev(netdev)))
1da177e4
LT		 844 goto err_register;
845
846 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
847
848 cards_found++;
849 return 0;
850
851err_register:
852err_sw_init:
853err_eeprom:
854 iounmap(adapter->hw.hw_addr);
855err_ioremap:
856 free_netdev(netdev);
857err_alloc_etherdev:
858 pci_release_regions(pdev);
859 return err;
860}
861
862/**
863 * e1000_remove - Device Removal Routine
864 * @pdev: PCI device information struct
865 *
866 * e1000_remove is called by the PCI subsystem to alert the driver
867 * that it should release a PCI device. The could be caused by a
868 * Hot-Plug event, or because the driver is going to be removed from
869 * memory.
870 **/
871
872static void __devexit
873e1000_remove(struct pci_dev *pdev)
874{
875 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 876 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 877 uint32_t manc;
581d708e
MC		 878#ifdef CONFIG_E1000_NAPI
879 int i;
880#endif
1da177e4 881
be2b28ed
JG		 882 flush_scheduled_work();
883
96838a40 884 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 885 adapter->hw.media_type == e1000_media_type_copper) {
886 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 887 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 888 manc |= E1000_MANC_ARP_EN;
889 E1000_WRITE_REG(&adapter->hw, MANC, manc);
890 }
891 }
892
b55ccb35
JK		 893 /* Release control of h/w to f/w. If f/w is AMT enabled, this
894 * would have already happened in close and is redundant. */
895 e1000_release_hw_control(adapter);
2d7edb92 896
1da177e4 897 unregister_netdev(netdev);
581d708e 898#ifdef CONFIG_E1000_NAPI
f56799ea 899 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 900 __dev_put(&adapter->polling_netdev[i]);
901#endif
1da177e4 902
96838a40 903 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 904 e1000_phy_hw_reset(&adapter->hw);
1da177e4 905
24025e4e
MC		 906 kfree(adapter->tx_ring);
907 kfree(adapter->rx_ring);
908#ifdef CONFIG_E1000_NAPI
909 kfree(adapter->polling_netdev);
910#endif
911
1da177e4
LT		 912 iounmap(adapter->hw.hw_addr);
913 pci_release_regions(pdev);
914
24025e4e
MC		 915#ifdef CONFIG_E1000_MQ
916 free_percpu(adapter->cpu_netdev);
917 free_percpu(adapter->cpu_tx_ring);
918#endif
1da177e4
LT		 919 free_netdev(netdev);
920
921 pci_disable_device(pdev);
922}
923
924/**
925 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
926 * @adapter: board private structure to initialize
927 *
928 * e1000_sw_init initializes the Adapter private data structure.
929 * Fields are initialized based on PCI device information and
930 * OS network device settings (MTU size).
931 **/
932
933static int __devinit
934e1000_sw_init(struct e1000_adapter *adapter)
935{
936 struct e1000_hw *hw = &adapter->hw;
937 struct net_device *netdev = adapter->netdev;
938 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 939#ifdef CONFIG_E1000_NAPI
940 int i;
941#endif
1da177e4
LT		 942
943 /* PCI config space info */
944
945 hw->vendor_id = pdev->vendor;
946 hw->device_id = pdev->device;
947 hw->subsystem_vendor_id = pdev->subsystem_vendor;
948 hw->subsystem_id = pdev->subsystem_device;
949
950 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
951
952 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
953
954 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 955 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 956 hw->max_frame_size = netdev->mtu +
957 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
958 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
959
960 /* identify the MAC */
961
96838a40 962 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 963 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
964 return -EIO;
965 }
966
967 /* initialize eeprom parameters */
968
96838a40 969 if (e1000_init_eeprom_params(hw)) {
2d7edb92
MC		 970 E1000_ERR("EEPROM initialization failed\n");
971 return -EIO;
972 }
1da177e4 973
96838a40 974 switch (hw->mac_type) {
1da177e4
LT		 975 default:
976 break;
977 case e1000_82541:
978 case e1000_82547:
979 case e1000_82541_rev_2:
980 case e1000_82547_rev_2:
981 hw->phy_init_script = 1;
982 break;
983 }
984
985 e1000_set_media_type(hw);
986
987 hw->wait_autoneg_complete = FALSE;
988 hw->tbi_compatibility_en = TRUE;
989 hw->adaptive_ifs = TRUE;
990
991 /* Copper options */
992
96838a40 993 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 994 hw->mdix = AUTO_ALL_MODES;
995 hw->disable_polarity_correction = FALSE;
996 hw->master_slave = E1000_MASTER_SLAVE;
997 }
998
24025e4e
MC		 999#ifdef CONFIG_E1000_MQ
1000 /* Number of supported queues */
1001 switch (hw->mac_type) {
1002 case e1000_82571:
1003 case e1000_82572:
f56799ea
JK		 1004 /* These controllers support 2 tx queues, but with a single
1005 * qdisc implementation, multiple tx queues aren't quite as
1006 * interesting. If we can find a logical way of mapping
1007 * flows to a queue, then perhaps we can up the num_tx_queue
1008 * count back to its default. Until then, we run the risk of
1009 * terrible performance due to SACK overload. */
1010 adapter->num_tx_queues = 1;
1011 adapter->num_rx_queues = 2;
24025e4e
MC		 1012 break;
1013 default:
f56799ea
JK		 1014 adapter->num_tx_queues = 1;
1015 adapter->num_rx_queues = 1;
24025e4e
MC		 1016 break;
1017 }
f56799ea
JK		 1018 adapter->num_rx_queues = min(adapter->num_rx_queues, num_online_cpus());
1019 adapter->num_tx_queues = min(adapter->num_tx_queues, num_online_cpus());
7bfa4816
JK		 1020 DPRINTK(DRV, INFO, "Multiqueue Enabled: Rx Queue count = %u %s\n",
1021 adapter->num_rx_queues,
1022 ((adapter->num_rx_queues == 1)
1023 ? ((num_online_cpus() > 1)
1024 ? "(due to unsupported feature in current adapter)"
1025 : "(due to unsupported system configuration)")
1026 : ""));
1027 DPRINTK(DRV, INFO, "Multiqueue Enabled: Tx Queue count = %u\n",
1028 adapter->num_tx_queues);
24025e4e 1029#else
f56799ea
JK		 1030 adapter->num_tx_queues = 1;
1031 adapter->num_rx_queues = 1;
24025e4e 1032#endif
581d708e
MC		 1033
1034 if (e1000_alloc_queues(adapter)) {
1035 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1036 return -ENOMEM;
1037 }
1038
1039#ifdef CONFIG_E1000_NAPI
f56799ea 1040 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1041 adapter->polling_netdev[i].priv = adapter;
1042 adapter->polling_netdev[i].poll = &e1000_clean;
1043 adapter->polling_netdev[i].weight = 64;
1044 dev_hold(&adapter->polling_netdev[i]);
1045 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1046 }
7bfa4816 1047 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1048#endif
1049
1da177e4
LT		 1050 atomic_set(&adapter->irq_sem, 1);
1051 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1052
1053 return 0;
1054}
1055
581d708e
MC		 1056/**
1057 * e1000_alloc_queues - Allocate memory for all rings
1058 * @adapter: board private structure to initialize
1059 *
1060 * We allocate one ring per queue at run-time since we don't know the
1061 * number of queues at compile-time. The polling_netdev array is
1062 * intended for Multiqueue, but should work fine with a single queue.
1063 **/
1064
1065static int __devinit
1066e1000_alloc_queues(struct e1000_adapter *adapter)
1067{
1068 int size;
1069
f56799ea 1070 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1071 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1072 if (!adapter->tx_ring)
1073 return -ENOMEM;
1074 memset(adapter->tx_ring, 0, size);
1075
f56799ea 1076 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1077 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1078 if (!adapter->rx_ring) {
1079 kfree(adapter->tx_ring);
1080 return -ENOMEM;
1081 }
1082 memset(adapter->rx_ring, 0, size);
1083
1084#ifdef CONFIG_E1000_NAPI
f56799ea 1085 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1086 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1087 if (!adapter->polling_netdev) {
1088 kfree(adapter->tx_ring);
1089 kfree(adapter->rx_ring);
1090 return -ENOMEM;
1091 }
1092 memset(adapter->polling_netdev, 0, size);
1093#endif
1094
7bfa4816
JK		 1095#ifdef CONFIG_E1000_MQ
1096 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1097 adapter->rx_sched_call_data.info = adapter->netdev;
1098
1099 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1100 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1101#endif
1102
581d708e
MC		 1103 return E1000_SUCCESS;
1104}
1105
24025e4e
MC		 1106#ifdef CONFIG_E1000_MQ
1107static void __devinit
1108e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1109{
1110 int i, cpu;
1111
1112 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1113 adapter->rx_sched_call_data.info = adapter->netdev;
1114 cpus_clear(adapter->rx_sched_call_data.cpumask);
1115
1116 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1117 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1118
1119 lock_cpu_hotplug();
1120 i = 0;
1121 for_each_online_cpu(cpu) {
f56799ea 1122 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_tx_queues];
24025e4e
MC		 1123 /* This is incomplete because we'd like to assign separate
1124 * physical cpus to these netdev polling structures and
1125 * avoid saturating a subset of cpus.
1126 */
f56799ea 1127 if (i < adapter->num_rx_queues) {
24025e4e 1128 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
7bfa4816
JK		 1129 adapter->rx_ring[i].cpu = cpu;
1130 cpu_set(cpu, adapter->cpumask);
24025e4e
MC		 1131 } else
1132 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1133
1134 i++;
1135 }
1136 unlock_cpu_hotplug();
1137}
1138#endif
1139
1da177e4
LT		 1140/**
1141 * e1000_open - Called when a network interface is made active
1142 * @netdev: network interface device structure
1143 *
1144 * Returns 0 on success, negative value on failure
1145 *
1146 * The open entry point is called when a network interface is made
1147 * active by the system (IFF_UP). At this point all resources needed
1148 * for transmit and receive operations are allocated, the interrupt
1149 * handler is registered with the OS, the watchdog timer is started,
1150 * and the stack is notified that the interface is ready.
1151 **/
1152
1153static int
1154e1000_open(struct net_device *netdev)
1155{
60490fe0 1156 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1157 int err;
1158
1159 /* allocate transmit descriptors */
1160
581d708e 1161 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1162 goto err_setup_tx;
1163
1164 /* allocate receive descriptors */
1165
581d708e 1166 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1167 goto err_setup_rx;
1168
96838a40 1169 if ((err = e1000_up(adapter)))
1da177e4 1170 goto err_up;
2d7edb92 1171 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1172 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1173 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1174 e1000_update_mng_vlan(adapter);
1175 }
1da177e4 1176
b55ccb35
JK		 1177 /* If AMT is enabled, let the firmware know that the network
1178 * interface is now open */
1179 if (adapter->hw.mac_type == e1000_82573 &&
1180 e1000_check_mng_mode(&adapter->hw))
1181 e1000_get_hw_control(adapter);
1182
1da177e4
LT		 1183 return E1000_SUCCESS;
1184
1185err_up:
581d708e 1186 e1000_free_all_rx_resources(adapter);
1da177e4 1187err_setup_rx:
581d708e 1188 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1189err_setup_tx:
1190 e1000_reset(adapter);
1191
1192 return err;
1193}
1194
1195/**
1196 * e1000_close - Disables a network interface
1197 * @netdev: network interface device structure
1198 *
1199 * Returns 0, this is not allowed to fail
1200 *
1201 * The close entry point is called when an interface is de-activated
1202 * by the OS. The hardware is still under the drivers control, but
1203 * needs to be disabled. A global MAC reset is issued to stop the
1204 * hardware, and all transmit and receive resources are freed.
1205 **/
1206
1207static int
1208e1000_close(struct net_device *netdev)
1209{
60490fe0 1210 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1211
1212 e1000_down(adapter);
1213
581d708e
MC		 1214 e1000_free_all_tx_resources(adapter);
1215 e1000_free_all_rx_resources(adapter);
1da177e4 1216
96838a40 1217 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1218 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1219 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1220 }
b55ccb35
JK		 1221
1222 /* If AMT is enabled, let the firmware know that the network
1223 * interface is now closed */
1224 if (adapter->hw.mac_type == e1000_82573 &&
1225 e1000_check_mng_mode(&adapter->hw))
1226 e1000_release_hw_control(adapter);
1227
1da177e4
LT		 1228 return 0;
1229}
1230
1231/**
1232 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1233 * @adapter: address of board private structure
2d7edb92
MC		 1234 * @start: address of beginning of memory
1235 * @len: length of memory
1da177e4
LT		 1236 **/
1237static inline boolean_t
1238e1000_check_64k_bound(struct e1000_adapter *adapter,
1239 void *start, unsigned long len)
1240{
1241 unsigned long begin = (unsigned long) start;
1242 unsigned long end = begin + len;
1243
2648345f
MC		 1244 /* First rev 82545 and 82546 need to not allow any memory
1245 * write location to cross 64k boundary due to errata 23 */
1da177e4 1246 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1247 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1248 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1249 }
1250
1251 return TRUE;
1252}
1253
1254/**
1255 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1256 * @adapter: board private structure
581d708e 1257 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1258 *
1259 * Return 0 on success, negative on failure
1260 **/
1261
3ad2cc67 1262static int
581d708e
MC		 1263e1000_setup_tx_resources(struct e1000_adapter *adapter,
1264 struct e1000_tx_ring *txdr)
1da177e4 1265{
1da177e4
LT		 1266 struct pci_dev *pdev = adapter->pdev;
1267 int size;
1268
1269 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1270
1271 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
96838a40 1272 if (!txdr->buffer_info) {
2648345f
MC		 1273 DPRINTK(PROBE, ERR,
1274 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1275 return -ENOMEM;
1276 }
1277 memset(txdr->buffer_info, 0, size);
1278
1279 /* round up to nearest 4K */
1280
1281 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1282 E1000_ROUNDUP(txdr->size, 4096);
1283
1284 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1285 if (!txdr->desc) {
1da177e4 1286setup_tx_desc_die:
1da177e4 1287 vfree(txdr->buffer_info);
2648345f
MC		 1288 DPRINTK(PROBE, ERR,
1289 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1290 return -ENOMEM;
1291 }
1292
2648345f 1293 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1294 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1295 void *olddesc = txdr->desc;
1296 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1297 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1298 "at %p\n", txdr->size, txdr->desc);
1299 /* Try again, without freeing the previous */
1da177e4 1300 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1301 /* Failed allocation, critical failure */
96838a40 1302 if (!txdr->desc) {
1da177e4
LT		 1303 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1304 goto setup_tx_desc_die;
1305 }
1306
1307 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1308 /* give up */
2648345f
MC		 1309 pci_free_consistent(pdev, txdr->size, txdr->desc,
1310 txdr->dma);
1da177e4
LT		 1311 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1312 DPRINTK(PROBE, ERR,
2648345f
MC		 1313 "Unable to allocate aligned memory "
1314 "for the transmit descriptor ring\n");
1da177e4
LT		 1315 vfree(txdr->buffer_info);
1316 return -ENOMEM;
1317 } else {
2648345f 1318 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1319 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1320 }
1321 }
1322 memset(txdr->desc, 0, txdr->size);
1323
1324 txdr->next_to_use = 0;
1325 txdr->next_to_clean = 0;
2ae76d98 1326 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1327
1328 return 0;
1329}
1330
581d708e
MC		 1331/**
1332 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1333 * (Descriptors) for all queues
1334 * @adapter: board private structure
1335 *
1336 * If this function returns with an error, then it's possible one or
1337 * more of the rings is populated (while the rest are not). It is the
1338 * callers duty to clean those orphaned rings.
1339 *
1340 * Return 0 on success, negative on failure
1341 **/
1342
1343int
1344e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1345{
1346 int i, err = 0;
1347
f56799ea 1348 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1349 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1350 if (err) {
1351 DPRINTK(PROBE, ERR,
1352 "Allocation for Tx Queue %u failed\n", i);
1353 break;
1354 }
1355 }
1356
1357 return err;
1358}
1359
1da177e4
LT		 1360/**
1361 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1362 * @adapter: board private structure
1363 *
1364 * Configure the Tx unit of the MAC after a reset.
1365 **/
1366
1367static void
1368e1000_configure_tx(struct e1000_adapter *adapter)
1369{
581d708e
MC		 1370 uint64_t tdba;
1371 struct e1000_hw *hw = &adapter->hw;
1372 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1373 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1374
1375 /* Setup the HW Tx Head and Tail descriptor pointers */
1376
f56799ea 1377 switch (adapter->num_tx_queues) {
24025e4e
MC		 1378 case 2:
1379 tdba = adapter->tx_ring[1].dma;
1380 tdlen = adapter->tx_ring[1].count *
1381 sizeof(struct e1000_tx_desc);
1382 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1383 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1384 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1385 E1000_WRITE_REG(hw, TDH1, 0);
1386 E1000_WRITE_REG(hw, TDT1, 0);
1387 adapter->tx_ring[1].tdh = E1000_TDH1;
1388 adapter->tx_ring[1].tdt = E1000_TDT1;
1389 /* Fall Through */
1390 case 1:
1391 default:
581d708e
MC		 1392 tdba = adapter->tx_ring[0].dma;
1393 tdlen = adapter->tx_ring[0].count *
1394 sizeof(struct e1000_tx_desc);
1395 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1396 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1397 E1000_WRITE_REG(hw, TDLEN, tdlen);
1398 E1000_WRITE_REG(hw, TDH, 0);
1399 E1000_WRITE_REG(hw, TDT, 0);
1400 adapter->tx_ring[0].tdh = E1000_TDH;
1401 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1402 break;
1403 }
1da177e4
LT		 1404
1405 /* Set the default values for the Tx Inter Packet Gap timer */
1406
0fadb059
JK		 1407 if (hw->media_type == e1000_media_type_fiber ||
1408 hw->media_type == e1000_media_type_internal_serdes)
1409 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1410 else
1411 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1412
581d708e 1413 switch (hw->mac_type) {
1da177e4
LT		 1414 case e1000_82542_rev2_0:
1415 case e1000_82542_rev2_1:
1416 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1417 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1418 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4
LT		 1419 break;
1420 default:
0fadb059
JK		 1421 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1422 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1423 break;
1da177e4 1424 }
0fadb059
JK		 1425 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1426 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1427 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1428
1429 /* Set the Tx Interrupt Delay register */
1430
581d708e
MC		 1431 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1432 if (hw->mac_type >= e1000_82540)
1433 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1434
1435 /* Program the Transmit Control Register */
1436
581d708e 1437 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1438
1439 tctl &= ~E1000_TCTL_CT;
24025e4e 1440 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1441 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1442
581d708e 1443 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1444
2ae76d98
MC		 1445 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1446 tarc = E1000_READ_REG(hw, TARC0);
1447 tarc |= ((1 << 25) | (1 << 21));
1448 E1000_WRITE_REG(hw, TARC0, tarc);
1449 tarc = E1000_READ_REG(hw, TARC1);
1450 tarc |= (1 << 25);
1451 if (tctl & E1000_TCTL_MULR)
1452 tarc &= ~(1 << 28);
1453 else
1454 tarc |= (1 << 28);
1455 E1000_WRITE_REG(hw, TARC1, tarc);
1456 }
1457
581d708e 1458 e1000_config_collision_dist(hw);
1da177e4
LT		 1459
1460 /* Setup Transmit Descriptor Settings for eop descriptor */
1461 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1462 E1000_TXD_CMD_IFCS;
1463
581d708e 1464 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1465 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1466 else
1467 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1468
1469 /* Cache if we're 82544 running in PCI-X because we'll
1470 * need this to apply a workaround later in the send path. */
581d708e
MC		 1471 if (hw->mac_type == e1000_82544 &&
1472 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1473 adapter->pcix_82544 = 1;
1474}
1475
1476/**
1477 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1478 * @adapter: board private structure
581d708e 1479 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1480 *
1481 * Returns 0 on success, negative on failure
1482 **/
1483
3ad2cc67 1484static int
581d708e
MC		 1485e1000_setup_rx_resources(struct e1000_adapter *adapter,
1486 struct e1000_rx_ring *rxdr)
1da177e4 1487{
1da177e4 1488 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1489 int size, desc_len;
1da177e4
LT		 1490
1491 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1492 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1493 if (!rxdr->buffer_info) {
2648345f
MC		 1494 DPRINTK(PROBE, ERR,
1495 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1496 return -ENOMEM;
1497 }
1498 memset(rxdr->buffer_info, 0, size);
1499
2d7edb92
MC		 1500 size = sizeof(struct e1000_ps_page) * rxdr->count;
1501 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1502 if (!rxdr->ps_page) {
2d7edb92
MC		 1503 vfree(rxdr->buffer_info);
1504 DPRINTK(PROBE, ERR,
1505 "Unable to allocate memory for the receive descriptor ring\n");
1506 return -ENOMEM;
1507 }
1508 memset(rxdr->ps_page, 0, size);
1509
1510 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1511 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1512 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1513 vfree(rxdr->buffer_info);
1514 kfree(rxdr->ps_page);
1515 DPRINTK(PROBE, ERR,
1516 "Unable to allocate memory for the receive descriptor ring\n");
1517 return -ENOMEM;
1518 }
1519 memset(rxdr->ps_page_dma, 0, size);
1520
96838a40 1521 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1522 desc_len = sizeof(struct e1000_rx_desc);
1523 else
1524 desc_len = sizeof(union e1000_rx_desc_packet_split);
1525
1da177e4
LT		 1526 /* Round up to nearest 4K */
1527
2d7edb92 1528 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1529 E1000_ROUNDUP(rxdr->size, 4096);
1530
1531 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1532
581d708e
MC		 1533 if (!rxdr->desc) {
1534 DPRINTK(PROBE, ERR,
1535 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1536setup_rx_desc_die:
1da177e4 1537 vfree(rxdr->buffer_info);
2d7edb92
MC		 1538 kfree(rxdr->ps_page);
1539 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1540 return -ENOMEM;
1541 }
1542
2648345f 1543 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1544 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1545 void *olddesc = rxdr->desc;
1546 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1547 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1548 "at %p\n", rxdr->size, rxdr->desc);
1549 /* Try again, without freeing the previous */
1da177e4 1550 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1551 /* Failed allocation, critical failure */
581d708e 1552 if (!rxdr->desc) {
1da177e4 1553 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1554 DPRINTK(PROBE, ERR,
1555 "Unable to allocate memory "
1556 "for the receive descriptor ring\n");
1da177e4
LT		 1557 goto setup_rx_desc_die;
1558 }
1559
1560 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1561 /* give up */
2648345f
MC		 1562 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1563 rxdr->dma);
1da177e4 1564 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1565 DPRINTK(PROBE, ERR,
1566 "Unable to allocate aligned memory "
1567 "for the receive descriptor ring\n");
581d708e 1568 goto setup_rx_desc_die;
1da177e4 1569 } else {
2648345f 1570 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1571 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1572 }
1573 }
1574 memset(rxdr->desc, 0, rxdr->size);
1575
1576 rxdr->next_to_clean = 0;
1577 rxdr->next_to_use = 0;
997f5cbd
JK		 1578 rxdr->rx_skb_top = NULL;
1579 rxdr->rx_skb_prev = NULL;
1da177e4
LT		 1580
1581 return 0;
1582}
1583
581d708e
MC		 1584/**
1585 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1586 * (Descriptors) for all queues
1587 * @adapter: board private structure
1588 *
1589 * If this function returns with an error, then it's possible one or
1590 * more of the rings is populated (while the rest are not). It is the
1591 * callers duty to clean those orphaned rings.
1592 *
1593 * Return 0 on success, negative on failure
1594 **/
1595
1596int
1597e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1598{
1599 int i, err = 0;
1600
f56799ea 1601 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1602 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1603 if (err) {
1604 DPRINTK(PROBE, ERR,
1605 "Allocation for Rx Queue %u failed\n", i);
1606 break;
1607 }
1608 }
1609
1610 return err;
1611}
1612
1da177e4 1613/**
2648345f 1614 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1615 * @adapter: Board private structure
1616 **/
e4c811c9
MC		 1617#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1618 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1619static void
1620e1000_setup_rctl(struct e1000_adapter *adapter)
1621{
2d7edb92
MC		 1622 uint32_t rctl, rfctl;
1623 uint32_t psrctl = 0;
35ec56bb 1624#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1625 uint32_t pages = 0;
1626#endif
1da177e4
LT		 1627
1628 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1629
1630 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1631
1632 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1633 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1634 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1635
0fadb059
JK		 1636 if (adapter->hw.mac_type > e1000_82543)
1637 rctl |= E1000_RCTL_SECRC;
1638
1639 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1640 rctl |= E1000_RCTL_SBP;
1641 else
1642 rctl &= ~E1000_RCTL_SBP;
1643
2d7edb92
MC		 1644 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1645 rctl &= ~E1000_RCTL_LPE;
1646 else
1647 rctl |= E1000_RCTL_LPE;
1648
1da177e4 1649 /* Setup buffer sizes */
96838a40 1650 if (adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1651 /* We can now specify buffers in 1K increments.
1652 * BSIZE and BSEX are ignored in this case. */
1653 rctl |= adapter->rx_buffer_len << 0x11;
1654 } else {
1655 rctl &= ~E1000_RCTL_SZ_4096;
b92ff8ee
JB		 1656 rctl &= ~E1000_RCTL_BSEX;
1657 rctl |= E1000_RCTL_SZ_2048;
2d7edb92
MC		 1658 }
1659
35ec56bb 1660#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1661 /* 82571 and greater support packet-split where the protocol
1662 * header is placed in skb->data and the packet data is
1663 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1664 * In the case of a non-split, skb->data is linearly filled,
1665 * followed by the page buffers. Therefore, skb->data is
1666 * sized to hold the largest protocol header.
1667 */
e4c811c9
MC		 1668 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1669 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1670 PAGE_SIZE <= 16384)
1671 adapter->rx_ps_pages = pages;
1672 else
1673 adapter->rx_ps_pages = 0;
2d7edb92 1674#endif
e4c811c9 1675 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1676 /* Configure extra packet-split registers */
1677 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1678 rfctl |= E1000_RFCTL_EXTEN;
1679 /* disable IPv6 packet split support */
1680 rfctl |= E1000_RFCTL_IPV6_DIS;
1681 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1682
1683 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
96838a40 1684
2d7edb92
MC		 1685 psrctl |= adapter->rx_ps_bsize0 >>
1686 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1687
1688 switch (adapter->rx_ps_pages) {
1689 case 3:
1690 psrctl |= PAGE_SIZE <<
1691 E1000_PSRCTL_BSIZE3_SHIFT;
1692 case 2:
1693 psrctl |= PAGE_SIZE <<
1694 E1000_PSRCTL_BSIZE2_SHIFT;
1695 case 1:
1696 psrctl |= PAGE_SIZE >>
1697 E1000_PSRCTL_BSIZE1_SHIFT;
1698 break;
1699 }
2d7edb92
MC		 1700
1701 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1702 }
1703
1704 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1705}
1706
1707/**
1708 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1709 * @adapter: board private structure
1710 *
1711 * Configure the Rx unit of the MAC after a reset.
1712 **/
1713
1714static void
1715e1000_configure_rx(struct e1000_adapter *adapter)
1716{
581d708e
MC		 1717 uint64_t rdba;
1718 struct e1000_hw *hw = &adapter->hw;
1719 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1720#ifdef CONFIG_E1000_MQ
1721 uint32_t reta, mrqc;
1722 int i;
1723#endif
2d7edb92 1724
e4c811c9 1725 if (adapter->rx_ps_pages) {
581d708e 1726 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1727 sizeof(union e1000_rx_desc_packet_split);
1728 adapter->clean_rx = e1000_clean_rx_irq_ps;
1729 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1730 } else {
581d708e
MC		 1731 rdlen = adapter->rx_ring[0].count *
1732 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1733 adapter->clean_rx = e1000_clean_rx_irq;
1734 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1735 }
1da177e4
LT		 1736
1737 /* disable receives while setting up the descriptors */
581d708e
MC		 1738 rctl = E1000_READ_REG(hw, RCTL);
1739 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1740
1741 /* set the Receive Delay Timer Register */
581d708e 1742 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1743
581d708e
MC		 1744 if (hw->mac_type >= e1000_82540) {
1745 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1746 if (adapter->itr > 1)
581d708e 1747 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1748 1000000000 / (adapter->itr * 256));
1749 }
1750
2ae76d98 1751 if (hw->mac_type >= e1000_82571) {
2ae76d98 1752 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1753 /* Reset delay timers after every interrupt */
2ae76d98 1754 ctrl_ext |= E1000_CTRL_EXT_CANC;
1e613fd9
JK		 1755#ifdef CONFIG_E1000_NAPI
1756 /* Auto-Mask interrupts upon ICR read. */
1757 ctrl_ext |= E1000_CTRL_EXT_IAME;
1758#endif
2ae76d98 1759 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1760 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1761 E1000_WRITE_FLUSH(hw);
1762 }
1763
581d708e
MC		 1764 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1765 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1766 switch (adapter->num_rx_queues) {
24025e4e
MC		 1767#ifdef CONFIG_E1000_MQ
1768 case 2:
1769 rdba = adapter->rx_ring[1].dma;
1770 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1771 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1772 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1773 E1000_WRITE_REG(hw, RDH1, 0);
1774 E1000_WRITE_REG(hw, RDT1, 0);
1775 adapter->rx_ring[1].rdh = E1000_RDH1;
1776 adapter->rx_ring[1].rdt = E1000_RDT1;
1777 /* Fall Through */
1778#endif
1779 case 1:
1780 default:
581d708e
MC		 1781 rdba = adapter->rx_ring[0].dma;
1782 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1783 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1784 E1000_WRITE_REG(hw, RDLEN, rdlen);
1785 E1000_WRITE_REG(hw, RDH, 0);
1786 E1000_WRITE_REG(hw, RDT, 0);
1787 adapter->rx_ring[0].rdh = E1000_RDH;
1788 adapter->rx_ring[0].rdt = E1000_RDT;
1789 break;
24025e4e
MC		 1790 }
1791
1792#ifdef CONFIG_E1000_MQ
f56799ea 1793 if (adapter->num_rx_queues > 1) {
24025e4e
MC		 1794 uint32_t random[10];
1795
1796 get_random_bytes(&random[0], 40);
1797
1798 if (hw->mac_type <= e1000_82572) {
1799 E1000_WRITE_REG(hw, RSSIR, 0);
1800 E1000_WRITE_REG(hw, RSSIM, 0);
1801 }
1802
f56799ea 1803 switch (adapter->num_rx_queues) {
24025e4e
MC		 1804 case 2:
1805 default:
1806 reta = 0x00800080;
1807 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1808 break;
1809 }
1810
1811 /* Fill out redirection table */
1812 for (i = 0; i < 32; i++)
1813 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1814 /* Fill out hash function seeds */
1815 for (i = 0; i < 10; i++)
1816 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1817
1818 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1819 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1820 E1000_WRITE_REG(hw, MRQC, mrqc);
1821 }
1822
1823 /* Multiqueue and packet checksumming are mutually exclusive. */
1824 if (hw->mac_type >= e1000_82571) {
1825 rxcsum = E1000_READ_REG(hw, RXCSUM);
1826 rxcsum |= E1000_RXCSUM_PCSD;
1827 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1828 }
1829
1830#else
1da177e4
LT		 1831
1832 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1833 if (hw->mac_type >= e1000_82543) {
1834 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1835 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1836 rxcsum |= E1000_RXCSUM_TUOFL;
1837
868d5309 1838 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1839 * Must be used in conjunction with packet-split. */
96838a40
JB		 1840 if ((hw->mac_type >= e1000_82571) &&
1841 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1842 rxcsum |= E1000_RXCSUM_IPPCSE;
1843 }
1844 } else {
1845 rxcsum &= ~E1000_RXCSUM_TUOFL;
1846 /* don't need to clear IPPCSE as it defaults to 0 */
1847 }
581d708e 1848 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1849 }
24025e4e 1850#endif /* CONFIG_E1000_MQ */
1da177e4 1851
581d708e
MC		 1852 if (hw->mac_type == e1000_82573)
1853 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1854
1da177e4 1855 /* Enable Receives */
581d708e 1856 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1857}
1858
1859/**
581d708e 1860 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1861 * @adapter: board private structure
581d708e 1862 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1863 *
1864 * Free all transmit software resources
1865 **/
1866
3ad2cc67 1867static void
581d708e
MC		 1868e1000_free_tx_resources(struct e1000_adapter *adapter,
1869 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1870{
1871 struct pci_dev *pdev = adapter->pdev;
1872
581d708e 1873 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1874
581d708e
MC		 1875 vfree(tx_ring->buffer_info);
1876 tx_ring->buffer_info = NULL;
1da177e4 1877
581d708e 1878 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1879
581d708e
MC		 1880 tx_ring->desc = NULL;
1881}
1882
1883/**
1884 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1885 * @adapter: board private structure
1886 *
1887 * Free all transmit software resources
1888 **/
1889
1890void
1891e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1892{
1893 int i;
1894
f56799ea 1895 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1896 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1897}
1898
1899static inline void
1900e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1901 struct e1000_buffer *buffer_info)
1902{
96838a40 1903 if (buffer_info->dma) {
2648345f
MC		 1904 pci_unmap_page(adapter->pdev,
1905 buffer_info->dma,
1906 buffer_info->length,
1907 PCI_DMA_TODEVICE);
1da177e4 1908 }
8241e35e 1909 if (buffer_info->skb)
1da177e4 1910 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1911 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1912}
1913
1914/**
1915 * e1000_clean_tx_ring - Free Tx Buffers
1916 * @adapter: board private structure
581d708e 1917 * @tx_ring: ring to be cleaned
1da177e4
LT		 1918 **/
1919
1920static void
581d708e
MC		 1921e1000_clean_tx_ring(struct e1000_adapter *adapter,
1922 struct e1000_tx_ring *tx_ring)
1da177e4 1923{
1da177e4
LT		 1924 struct e1000_buffer *buffer_info;
1925 unsigned long size;
1926 unsigned int i;
1927
1928 /* Free all the Tx ring sk_buffs */
1929
96838a40 1930 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1931 buffer_info = &tx_ring->buffer_info[i];
1932 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1933 }
1934
1935 size = sizeof(struct e1000_buffer) * tx_ring->count;
1936 memset(tx_ring->buffer_info, 0, size);
1937
1938 /* Zero out the descriptor ring */
1939
1940 memset(tx_ring->desc, 0, tx_ring->size);
1941
1942 tx_ring->next_to_use = 0;
1943 tx_ring->next_to_clean = 0;
fd803241 1944 tx_ring->last_tx_tso = 0;
1da177e4 1945
581d708e
MC		 1946 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1947 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1948}
1949
1950/**
1951 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1952 * @adapter: board private structure
1953 **/
1954
1955static void
1956e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1957{
1958 int i;
1959
f56799ea 1960 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1961 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1962}
1963
1964/**
1965 * e1000_free_rx_resources - Free Rx Resources
1966 * @adapter: board private structure
581d708e 1967 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1968 *
1969 * Free all receive software resources
1970 **/
1971
3ad2cc67 1972static void
581d708e
MC		 1973e1000_free_rx_resources(struct e1000_adapter *adapter,
1974 struct e1000_rx_ring *rx_ring)
1da177e4 1975{
1da177e4
LT		 1976 struct pci_dev *pdev = adapter->pdev;
1977
581d708e 1978 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1979
1980 vfree(rx_ring->buffer_info);
1981 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1982 kfree(rx_ring->ps_page);
1983 rx_ring->ps_page = NULL;
1984 kfree(rx_ring->ps_page_dma);
1985 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1986
1987 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1988
1989 rx_ring->desc = NULL;
1990}
1991
1992/**
581d708e 1993 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1994 * @adapter: board private structure
581d708e
MC		 1995 *
1996 * Free all receive software resources
1997 **/
1998
1999void
2000e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2001{
2002 int i;
2003
f56799ea 2004 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2005 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2006}
2007
2008/**
2009 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2010 * @adapter: board private structure
2011 * @rx_ring: ring to free buffers from
1da177e4
LT		 2012 **/
2013
2014static void
581d708e
MC		 2015e1000_clean_rx_ring(struct e1000_adapter *adapter,
2016 struct e1000_rx_ring *rx_ring)
1da177e4 2017{
1da177e4 2018 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2019 struct e1000_ps_page *ps_page;
2020 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2021 struct pci_dev *pdev = adapter->pdev;
2022 unsigned long size;
2d7edb92 2023 unsigned int i, j;
1da177e4
LT		 2024
2025 /* Free all the Rx ring sk_buffs */
96838a40 2026 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2027 buffer_info = &rx_ring->buffer_info[i];
96838a40 2028 if (buffer_info->skb) {
1da177e4
LT		 2029 pci_unmap_single(pdev,
2030 buffer_info->dma,
2031 buffer_info->length,
2032 PCI_DMA_FROMDEVICE);
2033
2034 dev_kfree_skb(buffer_info->skb);
2035 buffer_info->skb = NULL;
997f5cbd
JK		 2036 }
2037 ps_page = &rx_ring->ps_page[i];
2038 ps_page_dma = &rx_ring->ps_page_dma[i];
2039 for (j = 0; j < adapter->rx_ps_pages; j++) {
2040 if (!ps_page->ps_page[j]) break;
2041 pci_unmap_page(pdev,
2042 ps_page_dma->ps_page_dma[j],
2043 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2044 ps_page_dma->ps_page_dma[j] = 0;
2045 put_page(ps_page->ps_page[j]);
2046 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2047 }
2048 }
2049
997f5cbd
JK		 2050 /* there also may be some cached data in our adapter */
2051 if (rx_ring->rx_skb_top) {
2052 dev_kfree_skb(rx_ring->rx_skb_top);
2053
2054 /* rx_skb_prev will be wiped out by rx_skb_top */
2055 rx_ring->rx_skb_top = NULL;
2056 rx_ring->rx_skb_prev = NULL;
2057 }
2058
2059
1da177e4
LT		 2060 size = sizeof(struct e1000_buffer) * rx_ring->count;
2061 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2062 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2063 memset(rx_ring->ps_page, 0, size);
2064 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2065 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2066
2067 /* Zero out the descriptor ring */
2068
2069 memset(rx_ring->desc, 0, rx_ring->size);
2070
2071 rx_ring->next_to_clean = 0;
2072 rx_ring->next_to_use = 0;
2073
581d708e
MC		 2074 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2075 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2076}
2077
2078/**
2079 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2080 * @adapter: board private structure
2081 **/
2082
2083static void
2084e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2085{
2086 int i;
2087
f56799ea 2088 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2089 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2090}
2091
2092/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2093 * and memory write and invalidate disabled for certain operations
2094 */
2095static void
2096e1000_enter_82542_rst(struct e1000_adapter *adapter)
2097{
2098 struct net_device *netdev = adapter->netdev;
2099 uint32_t rctl;
2100
2101 e1000_pci_clear_mwi(&adapter->hw);
2102
2103 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2104 rctl |= E1000_RCTL_RST;
2105 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2106 E1000_WRITE_FLUSH(&adapter->hw);
2107 mdelay(5);
2108
96838a40 2109 if (netif_running(netdev))
581d708e 2110 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2111}
2112
2113static void
2114e1000_leave_82542_rst(struct e1000_adapter *adapter)
2115{
2116 struct net_device *netdev = adapter->netdev;
2117 uint32_t rctl;
2118
2119 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2120 rctl &= ~E1000_RCTL_RST;
2121 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2122 E1000_WRITE_FLUSH(&adapter->hw);
2123 mdelay(5);
2124
96838a40 2125 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2126 e1000_pci_set_mwi(&adapter->hw);
2127
96838a40 2128 if (netif_running(netdev)) {
1da177e4 2129 e1000_configure_rx(adapter);
72d64a43
JK		 2130 /* No need to loop, because 82542 supports only 1 queue */
2131 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
2132 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2133 }
2134}
2135
2136/**
2137 * e1000_set_mac - Change the Ethernet Address of the NIC
2138 * @netdev: network interface device structure
2139 * @p: pointer to an address structure
2140 *
2141 * Returns 0 on success, negative on failure
2142 **/
2143
2144static int
2145e1000_set_mac(struct net_device *netdev, void *p)
2146{
60490fe0 2147 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2148 struct sockaddr *addr = p;
2149
96838a40 2150 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2151 return -EADDRNOTAVAIL;
2152
2153 /* 82542 2.0 needs to be in reset to write receive address registers */
2154
96838a40 2155 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2156 e1000_enter_82542_rst(adapter);
2157
2158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2159 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2160
2161 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2162
868d5309
MC		 2163 /* With 82571 controllers, LAA may be overwritten (with the default)
2164 * due to controller reset from the other port. */
2165 if (adapter->hw.mac_type == e1000_82571) {
2166 /* activate the work around */
2167 adapter->hw.laa_is_present = 1;
2168
96838a40
JB		 2169 /* Hold a copy of the LAA in RAR[14] This is done so that
2170 * between the time RAR[0] gets clobbered and the time it
2171 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2172 * of the RARs and no incoming packets directed to this port
96838a40 2173 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2174 * RAR[14] */
96838a40 2175 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2176 E1000_RAR_ENTRIES - 1);
2177 }
2178
96838a40 2179 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2180 e1000_leave_82542_rst(adapter);
2181
2182 return 0;
2183}
2184
2185/**
2186 * e1000_set_multi - Multicast and Promiscuous mode set
2187 * @netdev: network interface device structure
2188 *
2189 * The set_multi entry point is called whenever the multicast address
2190 * list or the network interface flags are updated. This routine is
2191 * responsible for configuring the hardware for proper multicast,
2192 * promiscuous mode, and all-multi behavior.
2193 **/
2194
2195static void
2196e1000_set_multi(struct net_device *netdev)
2197{
60490fe0 2198 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2199 struct e1000_hw *hw = &adapter->hw;
2200 struct dev_mc_list *mc_ptr;
2201 uint32_t rctl;
2202 uint32_t hash_value;
868d5309 2203 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2204
868d5309
MC		 2205 /* reserve RAR[14] for LAA over-write work-around */
2206 if (adapter->hw.mac_type == e1000_82571)
2207 rar_entries--;
1da177e4 2208
2648345f
MC		 2209 /* Check for Promiscuous and All Multicast modes */
2210
1da177e4
LT		 2211 rctl = E1000_READ_REG(hw, RCTL);
2212
96838a40 2213 if (netdev->flags & IFF_PROMISC) {
1da177e4 2214 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2215 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2216 rctl |= E1000_RCTL_MPE;
2217 rctl &= ~E1000_RCTL_UPE;
2218 } else {
2219 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2220 }
2221
2222 E1000_WRITE_REG(hw, RCTL, rctl);
2223
2224 /* 82542 2.0 needs to be in reset to write receive address registers */
2225
96838a40 2226 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2227 e1000_enter_82542_rst(adapter);
2228
2229 /* load the first 14 multicast address into the exact filters 1-14
2230 * RAR 0 is used for the station MAC adddress
2231 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2232 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2233 */
2234 mc_ptr = netdev->mc_list;
2235
96838a40 2236 for (i = 1; i < rar_entries; i++) {
868d5309 2237 if (mc_ptr) {
1da177e4
LT		 2238 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2239 mc_ptr = mc_ptr->next;
2240 } else {
2241 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2242 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2243 }
2244 }
2245
2246 /* clear the old settings from the multicast hash table */
2247
96838a40 2248 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1da177e4
LT		 2249 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2250
2251 /* load any remaining addresses into the hash table */
2252
96838a40 2253 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2254 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2255 e1000_mta_set(hw, hash_value);
2256 }
2257
96838a40 2258 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2259 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2260}
2261
2262/* Need to wait a few seconds after link up to get diagnostic information from
2263 * the phy */
2264
2265static void
2266e1000_update_phy_info(unsigned long data)
2267{
2268 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2269 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2270}
2271
2272/**
2273 * e1000_82547_tx_fifo_stall - Timer Call-back
2274 * @data: pointer to adapter cast into an unsigned long
2275 **/
2276
2277static void
2278e1000_82547_tx_fifo_stall(unsigned long data)
2279{
2280 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2281 struct net_device *netdev = adapter->netdev;
2282 uint32_t tctl;
2283
96838a40
JB		 2284 if (atomic_read(&adapter->tx_fifo_stall)) {
2285 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2286 E1000_READ_REG(&adapter->hw, TDH)) &&
2287 (E1000_READ_REG(&adapter->hw, TDFT) ==
2288 E1000_READ_REG(&adapter->hw, TDFH)) &&
2289 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2290 E1000_READ_REG(&adapter->hw, TDFHS))) {
2291 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2292 E1000_WRITE_REG(&adapter->hw, TCTL,
2293 tctl & ~E1000_TCTL_EN);
2294 E1000_WRITE_REG(&adapter->hw, TDFT,
2295 adapter->tx_head_addr);
2296 E1000_WRITE_REG(&adapter->hw, TDFH,
2297 adapter->tx_head_addr);
2298 E1000_WRITE_REG(&adapter->hw, TDFTS,
2299 adapter->tx_head_addr);
2300 E1000_WRITE_REG(&adapter->hw, TDFHS,
2301 adapter->tx_head_addr);
2302 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2303 E1000_WRITE_FLUSH(&adapter->hw);
2304
2305 adapter->tx_fifo_head = 0;
2306 atomic_set(&adapter->tx_fifo_stall, 0);
2307 netif_wake_queue(netdev);
2308 } else {
2309 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2310 }
2311 }
2312}
2313
2314/**
2315 * e1000_watchdog - Timer Call-back
2316 * @data: pointer to adapter cast into an unsigned long
2317 **/
2318static void
2319e1000_watchdog(unsigned long data)
2320{
2321 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2322
2323 /* Do the rest outside of interrupt context */
2324 schedule_work(&adapter->watchdog_task);
2325}
2326
2327static void
2328e1000_watchdog_task(struct e1000_adapter *adapter)
2329{
2330 struct net_device *netdev = adapter->netdev;
545c67c0 2331 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2332 uint32_t link;
2333
2334 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2335 if (adapter->hw.mac_type == e1000_82573) {
2336 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2337 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2338 e1000_update_mng_vlan(adapter);
96838a40 2339 }
1da177e4 2340
96838a40 2341 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2342 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2343 link = !adapter->hw.serdes_link_down;
2344 else
2345 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2346
96838a40
JB		 2347 if (link) {
2348 if (!netif_carrier_ok(netdev)) {
1da177e4
LT		 2349 e1000_get_speed_and_duplex(&adapter->hw,
2350 &adapter->link_speed,
2351 &adapter->link_duplex);
2352
2353 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2354 adapter->link_speed,
2355 adapter->link_duplex == FULL_DUPLEX ?
2356 "Full Duplex" : "Half Duplex");
2357
66a2b0a3
JK		 2358 /* tweak tx_queue_len according to speed/duplex */
2359 netdev->tx_queue_len = adapter->tx_queue_len;
2360 adapter->tx_timeout_factor = 1;
2361 if (adapter->link_duplex == HALF_DUPLEX) {
2362 switch (adapter->link_speed) {
2363 case SPEED_10:
2364 netdev->tx_queue_len = 10;
2365 adapter->tx_timeout_factor = 8;
2366 break;
2367 case SPEED_100:
2368 netdev->tx_queue_len = 100;
2369 break;
2370 }
2371 }
2372
1da177e4
LT		 2373 netif_carrier_on(netdev);
2374 netif_wake_queue(netdev);
2375 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2376 adapter->smartspeed = 0;
2377 }
2378 } else {
96838a40 2379 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2380 adapter->link_speed = 0;
2381 adapter->link_duplex = 0;
2382 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2383 netif_carrier_off(netdev);
2384 netif_stop_queue(netdev);
2385 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2386 }
2387
2388 e1000_smartspeed(adapter);
2389 }
2390
2391 e1000_update_stats(adapter);
2392
2393 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2394 adapter->tpt_old = adapter->stats.tpt;
2395 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2396 adapter->colc_old = adapter->stats.colc;
2397
2398 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2399 adapter->gorcl_old = adapter->stats.gorcl;
2400 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2401 adapter->gotcl_old = adapter->stats.gotcl;
2402
2403 e1000_update_adaptive(&adapter->hw);
2404
f56799ea
JK		 2405#ifdef CONFIG_E1000_MQ
2406 txdr = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2407#endif
2408 if (!netif_carrier_ok(netdev)) {
581d708e 2409 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2410 /* We've lost link, so the controller stops DMA,
2411 * but we've got queued Tx work that's never going
2412 * to get done, so reset controller to flush Tx.
2413 * (Do the reset outside of interrupt context). */
2414 schedule_work(&adapter->tx_timeout_task);
2415 }
2416 }
2417
2418 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2419 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2420 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2421 * asymmetrical Tx or Rx gets ITR=8000; everyone
2422 * else is between 2000-8000. */
2423 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2424 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2425 adapter->gotcl - adapter->gorcl :
2426 adapter->gorcl - adapter->gotcl) / 10000;
2427 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2428 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2429 }
2430
2431 /* Cause software interrupt to ensure rx ring is cleaned */
2432 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2433
2648345f 2434 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2435 adapter->detect_tx_hung = TRUE;
2436
96838a40 2437 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2438 * reset from the other port. Set the appropriate LAA in RAR[0] */
2439 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2440 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2441
1da177e4
LT		 2442 /* Reset the timer */
2443 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2444}
2445
2446#define E1000_TX_FLAGS_CSUM 0x00000001
2447#define E1000_TX_FLAGS_VLAN 0x00000002
2448#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2449#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2450#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2451#define E1000_TX_FLAGS_VLAN_SHIFT 16
2452
2453static inline int
581d708e
MC		 2454e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2455 struct sk_buff *skb)
1da177e4
LT		 2456{
2457#ifdef NETIF_F_TSO
2458 struct e1000_context_desc *context_desc;
545c67c0 2459 struct e1000_buffer *buffer_info;
1da177e4
LT		 2460 unsigned int i;
2461 uint32_t cmd_length = 0;
2d7edb92 2462 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2463 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2464 int err;
2465
96838a40 2466 if (skb_shinfo(skb)->tso_size) {
1da177e4
LT		 2467 if (skb_header_cloned(skb)) {
2468 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2469 if (err)
2470 return err;
2471 }
2472
2473 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2474 mss = skb_shinfo(skb)->tso_size;
96838a40 2475 if (skb->protocol == ntohs(ETH_P_IP)) {
2d7edb92
MC		 2476 skb->nh.iph->tot_len = 0;
2477 skb->nh.iph->check = 0;
2478 skb->h.th->check =
2479 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2480 skb->nh.iph->daddr,
2481 0,
2482 IPPROTO_TCP,
2483 0);
2484 cmd_length = E1000_TXD_CMD_IP;
2485 ipcse = skb->h.raw - skb->data - 1;
2486#ifdef NETIF_F_TSO_IPV6
96838a40 2487 } else if (skb->protocol == ntohs(ETH_P_IPV6)) {
2d7edb92
MC		 2488 skb->nh.ipv6h->payload_len = 0;
2489 skb->h.th->check =
2490 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2491 &skb->nh.ipv6h->daddr,
2492 0,
2493 IPPROTO_TCP,
2494 0);
2495 ipcse = 0;
2496#endif
2497 }
1da177e4
LT		 2498 ipcss = skb->nh.raw - skb->data;
2499 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2500 tucss = skb->h.raw - skb->data;
2501 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2502 tucse = 0;
2503
2504 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2505 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2506
581d708e
MC		 2507 i = tx_ring->next_to_use;
2508 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2509 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2510
2511 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2512 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2513 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2514 context_desc->upper_setup.tcp_fields.tucss = tucss;
2515 context_desc->upper_setup.tcp_fields.tucso = tucso;
2516 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2517 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2518 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2519 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2520
545c67c0
JK		 2521 buffer_info->time_stamp = jiffies;
2522
581d708e
MC		 2523 if (++i == tx_ring->count) i = 0;
2524 tx_ring->next_to_use = i;
1da177e4 2525
8241e35e 2526 return TRUE;
1da177e4
LT		 2527 }
2528#endif
2529
8241e35e 2530 return FALSE;
1da177e4
LT		 2531}
2532
2533static inline boolean_t
581d708e
MC		 2534e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2535 struct sk_buff *skb)
1da177e4
LT		 2536{
2537 struct e1000_context_desc *context_desc;
545c67c0 2538 struct e1000_buffer *buffer_info;
1da177e4
LT		 2539 unsigned int i;
2540 uint8_t css;
2541
96838a40 2542 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2543 css = skb->h.raw - skb->data;
2544
581d708e 2545 i = tx_ring->next_to_use;
545c67c0 2546 buffer_info = &tx_ring->buffer_info[i];
581d708e 2547 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2548
2549 context_desc->upper_setup.tcp_fields.tucss = css;
2550 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2551 context_desc->upper_setup.tcp_fields.tucse = 0;
2552 context_desc->tcp_seg_setup.data = 0;
2553 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2554
545c67c0
JK		 2555 buffer_info->time_stamp = jiffies;
2556
581d708e
MC		 2557 if (unlikely(++i == tx_ring->count)) i = 0;
2558 tx_ring->next_to_use = i;
1da177e4
LT		 2559
2560 return TRUE;
2561 }
2562
2563 return FALSE;
2564}
2565
2566#define E1000_MAX_TXD_PWR 12
2567#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2568
2569static inline int
581d708e
MC		 2570e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2571 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2572 unsigned int nr_frags, unsigned int mss)
1da177e4 2573{
1da177e4
LT		 2574 struct e1000_buffer *buffer_info;
2575 unsigned int len = skb->len;
2576 unsigned int offset = 0, size, count = 0, i;
2577 unsigned int f;
2578 len -= skb->data_len;
2579
2580 i = tx_ring->next_to_use;
2581
96838a40 2582 while (len) {
1da177e4
LT		 2583 buffer_info = &tx_ring->buffer_info[i];
2584 size = min(len, max_per_txd);
2585#ifdef NETIF_F_TSO
fd803241
JK		 2586 /* Workaround for Controller erratum --
2587 * descriptor for non-tso packet in a linear SKB that follows a
2588 * tso gets written back prematurely before the data is fully
2589 * DMAd to the controller */
2590 if (!skb->data_len && tx_ring->last_tx_tso &&
2591 !skb_shinfo(skb)->tso_size) {
2592 tx_ring->last_tx_tso = 0;
2593 size -= 4;
2594 }
2595
1da177e4
LT		 2596 /* Workaround for premature desc write-backs
2597 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2598 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2599 size -= 4;
2600#endif
97338bde
MC		 2601 /* work-around for errata 10 and it applies
2602 * to all controllers in PCI-X mode
2603 * The fix is to make sure that the first descriptor of a
2604 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2605 */
96838a40 2606 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2607 (size > 2015) && count == 0))
2608 size = 2015;
96838a40 2609
1da177e4
LT		 2610 /* Workaround for potential 82544 hang in PCI-X. Avoid
2611 * terminating buffers within evenly-aligned dwords. */
96838a40 2612 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2613 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2614 size > 4))
2615 size -= 4;
2616
2617 buffer_info->length = size;
2618 buffer_info->dma =
2619 pci_map_single(adapter->pdev,
2620 skb->data + offset,
2621 size,
2622 PCI_DMA_TODEVICE);
2623 buffer_info->time_stamp = jiffies;
2624
2625 len -= size;
2626 offset += size;
2627 count++;
96838a40 2628 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2629 }
2630
96838a40 2631 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2632 struct skb_frag_struct *frag;
2633
2634 frag = &skb_shinfo(skb)->frags[f];
2635 len = frag->size;
2636 offset = frag->page_offset;
2637
96838a40 2638 while (len) {
1da177e4
LT		 2639 buffer_info = &tx_ring->buffer_info[i];
2640 size = min(len, max_per_txd);
2641#ifdef NETIF_F_TSO
2642 /* Workaround for premature desc write-backs
2643 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2644 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2645 size -= 4;
2646#endif
2647 /* Workaround for potential 82544 hang in PCI-X.
2648 * Avoid terminating buffers within evenly-aligned
2649 * dwords. */
96838a40 2650 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2651 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2652 size > 4))
2653 size -= 4;
2654
2655 buffer_info->length = size;
2656 buffer_info->dma =
2657 pci_map_page(adapter->pdev,
2658 frag->page,
2659 offset,
2660 size,
2661 PCI_DMA_TODEVICE);
2662 buffer_info->time_stamp = jiffies;
2663
2664 len -= size;
2665 offset += size;
2666 count++;
96838a40 2667 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2668 }
2669 }
2670
2671 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2672 tx_ring->buffer_info[i].skb = skb;
2673 tx_ring->buffer_info[first].next_to_watch = i;
2674
2675 return count;
2676}
2677
2678static inline void
581d708e
MC		 2679e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2680 int tx_flags, int count)
1da177e4 2681{
1da177e4
LT		 2682 struct e1000_tx_desc *tx_desc = NULL;
2683 struct e1000_buffer *buffer_info;
2684 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2685 unsigned int i;
2686
96838a40 2687 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2688 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2689 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2690 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2691
96838a40 2692 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2693 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2694 }
2695
96838a40 2696 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2697 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2698 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2699 }
2700
96838a40 2701 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2702 txd_lower |= E1000_TXD_CMD_VLE;
2703 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2704 }
2705
2706 i = tx_ring->next_to_use;
2707
96838a40 2708 while (count--) {
1da177e4
LT		 2709 buffer_info = &tx_ring->buffer_info[i];
2710 tx_desc = E1000_TX_DESC(*tx_ring, i);
2711 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2712 tx_desc->lower.data =
2713 cpu_to_le32(txd_lower | buffer_info->length);
2714 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2715 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2716 }
2717
2718 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2719
2720 /* Force memory writes to complete before letting h/w
2721 * know there are new descriptors to fetch. (Only
2722 * applicable for weak-ordered memory model archs,
2723 * such as IA-64). */
2724 wmb();
2725
2726 tx_ring->next_to_use = i;
581d708e 2727 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2728}
2729
2730/**
2731 * 82547 workaround to avoid controller hang in half-duplex environment.
2732 * The workaround is to avoid queuing a large packet that would span
2733 * the internal Tx FIFO ring boundary by notifying the stack to resend
2734 * the packet at a later time. This gives the Tx FIFO an opportunity to
2735 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2736 * to the beginning of the Tx FIFO.
2737 **/
2738
2739#define E1000_FIFO_HDR 0x10
2740#define E1000_82547_PAD_LEN 0x3E0
2741
2742static inline int
2743e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2744{
2745 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2746 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2747
2748 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2749
96838a40 2750 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2751 goto no_fifo_stall_required;
2752
96838a40 2753 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2754 return 1;
2755
96838a40 2756 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2757 atomic_set(&adapter->tx_fifo_stall, 1);
2758 return 1;
2759 }
2760
2761no_fifo_stall_required:
2762 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2763 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2764 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2765 return 0;
2766}
2767
2d7edb92
MC		 2768#define MINIMUM_DHCP_PACKET_SIZE 282
2769static inline int
2770e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2771{
2772 struct e1000_hw *hw = &adapter->hw;
2773 uint16_t length, offset;
96838a40
JB		 2774 if (vlan_tx_tag_present(skb)) {
2775 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2776 ( adapter->hw.mng_cookie.status &
2777 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2778 return 0;
2779 }
96838a40 2780 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92 2781 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2782 if ((htons(ETH_P_IP) == eth->h_proto)) {
2783 const struct iphdr *ip =
2d7edb92 2784 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2785 if (IPPROTO_UDP == ip->protocol) {
2786 struct udphdr *udp =
2787 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2788 (ip->ihl << 2));
96838a40 2789 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2790 offset = (uint8_t *)udp + 8 - skb->data;
2791 length = skb->len - offset;
2792
2793 return e1000_mng_write_dhcp_info(hw,
96838a40 2794 (uint8_t *)udp + 8,
2d7edb92
MC		 2795 length);
2796 }
2797 }
2798 }
2799 }
2800 return 0;
2801}
2802
1da177e4
LT		 2803#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2804static int
2805e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2806{
60490fe0 2807 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2808 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2809 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2810 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2811 unsigned int tx_flags = 0;
2812 unsigned int len = skb->len;
2813 unsigned long flags;
2814 unsigned int nr_frags = 0;
2815 unsigned int mss = 0;
2816 int count = 0;
96838a40 2817 int tso;
1da177e4
LT		 2818 unsigned int f;
2819 len -= skb->data_len;
2820
24025e4e
MC		 2821#ifdef CONFIG_E1000_MQ
2822 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2823#else
581d708e 2824 tx_ring = adapter->tx_ring;
24025e4e
MC		 2825#endif
2826
581d708e 2827 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2828 dev_kfree_skb_any(skb);
2829 return NETDEV_TX_OK;
2830 }
2831
2832#ifdef NETIF_F_TSO
2833 mss = skb_shinfo(skb)->tso_size;
2648345f 2834 /* The controller does a simple calculation to
1da177e4
LT		 2835 * make sure there is enough room in the FIFO before
2836 * initiating the DMA for each buffer. The calc is:
2837 * 4 = ceil(buffer len/mss). To make sure we don't
2838 * overrun the FIFO, adjust the max buffer len if mss
2839 * drops. */
96838a40 2840 if (mss) {
9a3056da 2841 uint8_t hdr_len;
1da177e4
LT		 2842 max_per_txd = min(mss << 2, max_per_txd);
2843 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2844
2845 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2846 * points to just header, pull a few bytes of payload from
2847 * frags into skb->data */
2848 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2849 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2850 (adapter->hw.mac_type == e1000_82571 ||
2851 adapter->hw.mac_type == e1000_82572)) {
d74bbd3b
JK		 2852 unsigned int pull_size;
2853 pull_size = min((unsigned int)4, skb->data_len);
2854 if (!__pskb_pull_tail(skb, pull_size)) {
2855 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2856 dev_kfree_skb_any(skb);
2857 return -EFAULT;
2858 }
9a3056da
JK		 2859 len = skb->len - skb->data_len;
2860 }
1da177e4
LT		 2861 }
2862
9a3056da 2863 /* reserve a descriptor for the offload context */
96838a40 2864 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2865 count++;
2648345f 2866 count++;
1da177e4 2867#else
96838a40 2868 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2869 count++;
2870#endif
fd803241
JK		 2871
2872#ifdef NETIF_F_TSO
2873 /* Controller Erratum workaround */
2874 if (!skb->data_len && tx_ring->last_tx_tso &&
2875 !skb_shinfo(skb)->tso_size)
2876 count++;
2877#endif
2878
1da177e4
LT		 2879 count += TXD_USE_COUNT(len, max_txd_pwr);
2880
96838a40 2881 if (adapter->pcix_82544)
1da177e4
LT		 2882 count++;
2883
96838a40 2884 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2885 * in PCI-X mode, so add one more descriptor to the count
2886 */
96838a40 2887 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2888 (len > 2015)))
2889 count++;
2890
1da177e4 2891 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2892 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2893 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2894 max_txd_pwr);
96838a40 2895 if (adapter->pcix_82544)
1da177e4
LT		 2896 count += nr_frags;
2897
96838a40 2898 if (adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2d7edb92
MC		 2899 e1000_transfer_dhcp_info(adapter, skb);
2900
581d708e
MC		 2901 local_irq_save(flags);
2902 if (!spin_trylock(&tx_ring->tx_lock)) {
2903 /* Collision - tell upper layer to requeue */
2904 local_irq_restore(flags);
2905 return NETDEV_TX_LOCKED;
2906 }
1da177e4
LT		 2907
2908 /* need: count + 2 desc gap to keep tail from touching
2909 * head, otherwise try next time */
581d708e 2910 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2911 netif_stop_queue(netdev);
581d708e 2912 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2913 return NETDEV_TX_BUSY;
2914 }
2915
96838a40
JB		 2916 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2917 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2918 netif_stop_queue(netdev);
2919 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2920 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2921 return NETDEV_TX_BUSY;
2922 }
2923 }
2924
96838a40 2925 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2926 tx_flags |= E1000_TX_FLAGS_VLAN;
2927 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2928 }
2929
581d708e 2930 first = tx_ring->next_to_use;
96838a40 2931
581d708e 2932 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2933 if (tso < 0) {
2934 dev_kfree_skb_any(skb);
581d708e 2935 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2936 return NETDEV_TX_OK;
2937 }
2938
fd803241
JK		 2939 if (likely(tso)) {
2940 tx_ring->last_tx_tso = 1;
1da177e4 2941 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2942 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2943 tx_flags |= E1000_TX_FLAGS_CSUM;
2944
2d7edb92 2945 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2946 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2947 * no longer assume, we must. */
581d708e 2948 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2949 tx_flags |= E1000_TX_FLAGS_IPV4;
2950
581d708e
MC		 2951 e1000_tx_queue(adapter, tx_ring, tx_flags,
2952 e1000_tx_map(adapter, tx_ring, skb, first,
2953 max_per_txd, nr_frags, mss));
1da177e4
LT		 2954
2955 netdev->trans_start = jiffies;
2956
2957 /* Make sure there is space in the ring for the next send. */
581d708e 2958 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2959 netif_stop_queue(netdev);
2960
581d708e 2961 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2962 return NETDEV_TX_OK;
2963}
2964
2965/**
2966 * e1000_tx_timeout - Respond to a Tx Hang
2967 * @netdev: network interface device structure
2968 **/
2969
2970static void
2971e1000_tx_timeout(struct net_device *netdev)
2972{
60490fe0 2973 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2974
2975 /* Do the reset outside of interrupt context */
2976 schedule_work(&adapter->tx_timeout_task);
2977}
2978
2979static void
2980e1000_tx_timeout_task(struct net_device *netdev)
2981{
60490fe0 2982 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2983
6b7660cd 2984 adapter->tx_timeout_count++;
1da177e4
LT		 2985 e1000_down(adapter);
2986 e1000_up(adapter);
2987}
2988
2989/**
2990 * e1000_get_stats - Get System Network Statistics
2991 * @netdev: network interface device structure
2992 *
2993 * Returns the address of the device statistics structure.
2994 * The statistics are actually updated from the timer callback.
2995 **/
2996
2997static struct net_device_stats *
2998e1000_get_stats(struct net_device *netdev)
2999{
60490fe0 3000 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3001
6b7660cd 3002 /* only return the current stats */
1da177e4
LT		 3003 return &adapter->net_stats;
3004}
3005
3006/**
3007 * e1000_change_mtu - Change the Maximum Transfer Unit
3008 * @netdev: network interface device structure
3009 * @new_mtu: new value for maximum frame size
3010 *
3011 * Returns 0 on success, negative on failure
3012 **/
3013
3014static int
3015e1000_change_mtu(struct net_device *netdev, int new_mtu)
3016{
60490fe0 3017 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3018 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3019
96838a40
JB		 3020 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3021 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3022 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3023 return -EINVAL;
2d7edb92 3024 }
1da177e4 3025
997f5cbd
JK		 3026 /* Adapter-specific max frame size limits. */
3027 switch (adapter->hw.mac_type) {
3028 case e1000_82542_rev2_0:
3029 case e1000_82542_rev2_1:
3030 case e1000_82573:
3031 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3032 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3033 return -EINVAL;
2d7edb92 3034 }
997f5cbd
JK		 3035 break;
3036 case e1000_82571:
3037 case e1000_82572:
3038#define MAX_STD_JUMBO_FRAME_SIZE 9234
3039 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3040 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3041 return -EINVAL;
3042 }
3043 break;
3044 default:
3045 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3046 break;
1da177e4
LT		 3047 }
3048
997f5cbd
JK		 3049 /* since the driver code now supports splitting a packet across
3050 * multiple descriptors, most of the fifo related limitations on
3051 * jumbo frame traffic have gone away.
3052 * simply use 2k descriptors for everything.
3053 *
3054 * NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3055 * means we reserve 2 more, this pushes us to allocate from the next
3056 * larger slab size
3057 * i.e. RXBUFFER_2048 --> size-4096 slab */
3058
3059 /* recent hardware supports 1KB granularity */
3060 if (adapter->hw.mac_type > e1000_82547_rev_2) {
3061 adapter->rx_buffer_len =
3062 ((max_frame < E1000_RXBUFFER_2048) ?
3063 max_frame : E1000_RXBUFFER_2048);
3064 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
3065 } else
3066 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3067
2d7edb92
MC		 3068 netdev->mtu = new_mtu;
3069
96838a40 3070 if (netif_running(netdev)) {
1da177e4
LT		 3071 e1000_down(adapter);
3072 e1000_up(adapter);
3073 }
3074
1da177e4
LT		 3075 adapter->hw.max_frame_size = max_frame;
3076
3077 return 0;
3078}
3079
3080/**
3081 * e1000_update_stats - Update the board statistics counters
3082 * @adapter: board private structure
3083 **/
3084
3085void
3086e1000_update_stats(struct e1000_adapter *adapter)
3087{
3088 struct e1000_hw *hw = &adapter->hw;
3089 unsigned long flags;
3090 uint16_t phy_tmp;
3091
3092#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3093
3094 spin_lock_irqsave(&adapter->stats_lock, flags);
3095
3096 /* these counters are modified from e1000_adjust_tbi_stats,
3097 * called from the interrupt context, so they must only
3098 * be written while holding adapter->stats_lock
3099 */
3100
3101 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3102 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3103 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3104 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3105 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3106 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3107 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3108 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3109 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3110 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3111 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3112 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3113 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3114
3115 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3116 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3117 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3118 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3119 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3120 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3121 adapter->stats.dc += E1000_READ_REG(hw, DC);
3122 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3123 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3124 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3125 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3126 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3127 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3128 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3129 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3130 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3131 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3132 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3133 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3134 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3135 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3136 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3137 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3138 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3139 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3140 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3141 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3142 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3143 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3144 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3145 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3146 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3147 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3148 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3149
3150 /* used for adaptive IFS */
3151
3152 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3153 adapter->stats.tpt += hw->tx_packet_delta;
3154 hw->collision_delta = E1000_READ_REG(hw, COLC);
3155 adapter->stats.colc += hw->collision_delta;
3156
96838a40 3157 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3158 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3159 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3160 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3161 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3162 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3163 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3164 }
96838a40 3165 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3166 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3167 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3168 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3169 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3170 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3171 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3172 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3173 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3174 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3175 }
1da177e4
LT		 3176
3177 /* Fill out the OS statistics structure */
3178
3179 adapter->net_stats.rx_packets = adapter->stats.gprc;
3180 adapter->net_stats.tx_packets = adapter->stats.gptc;
3181 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3182 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3183 adapter->net_stats.multicast = adapter->stats.mprc;
3184 adapter->net_stats.collisions = adapter->stats.colc;
3185
3186 /* Rx Errors */
3187
3188 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3189 adapter->stats.crcerrs + adapter->stats.algnerrc +
6b7660cd
JK		 3190 adapter->stats.rlec + adapter->stats.cexterr;
3191 adapter->net_stats.rx_dropped = 0;
1da177e4
LT		 3192 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3193 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3194 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3195 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3196
3197 /* Tx Errors */
3198
3199 adapter->net_stats.tx_errors = adapter->stats.ecol +
3200 adapter->stats.latecol;
3201 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3202 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3203 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3204
3205 /* Tx Dropped needs to be maintained elsewhere */
3206
3207 /* Phy Stats */
3208
96838a40
JB		 3209 if (hw->media_type == e1000_media_type_copper) {
3210 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3211 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3212 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3213 adapter->phy_stats.idle_errors += phy_tmp;
3214 }
3215
96838a40 3216 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3217 (hw->phy_type == e1000_phy_m88) &&
3218 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3219 adapter->phy_stats.receive_errors += phy_tmp;
3220 }
3221
3222 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3223}
3224
24025e4e
MC		 3225#ifdef CONFIG_E1000_MQ
3226void
3227e1000_rx_schedule(void *data)
3228{
3229 struct net_device *poll_dev, *netdev = data;
3230 struct e1000_adapter *adapter = netdev->priv;
3231 int this_cpu = get_cpu();
3232
3233 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3234 if (poll_dev == NULL) {
3235 put_cpu();
3236 return;
3237 }
3238
3239 if (likely(netif_rx_schedule_prep(poll_dev)))
3240 __netif_rx_schedule(poll_dev);
3241 else
3242 e1000_irq_enable(adapter);
3243
3244 put_cpu();
3245}
3246#endif
3247
1da177e4
LT		 3248/**
3249 * e1000_intr - Interrupt Handler
3250 * @irq: interrupt number
3251 * @data: pointer to a network interface device structure
3252 * @pt_regs: CPU registers structure
3253 **/
3254
3255static irqreturn_t
3256e1000_intr(int irq, void *data, struct pt_regs *regs)
3257{
3258 struct net_device *netdev = data;
60490fe0 3259 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3260 struct e1000_hw *hw = &adapter->hw;
3261 uint32_t icr = E1000_READ_REG(hw, ICR);
1e613fd9 3262#ifndef CONFIG_E1000_NAPI
581d708e 3263 int i;
1e613fd9
JK		 3264#else
3265 /* Interrupt Auto-Mask...upon reading ICR,
3266 * interrupts are masked. No need for the
3267 * IMC write, but it does mean we should
3268 * account for it ASAP. */
3269 if (likely(hw->mac_type >= e1000_82571))
3270 atomic_inc(&adapter->irq_sem);
be2b28ed 3271#endif
1da177e4 3272
1e613fd9
JK		 3273 if (unlikely(!icr)) {
3274#ifdef CONFIG_E1000_NAPI
3275 if (hw->mac_type >= e1000_82571)
3276 e1000_irq_enable(adapter);
3277#endif
1da177e4 3278 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3279 }
1da177e4 3280
96838a40 3281 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4
LT		 3282 hw->get_link_status = 1;
3283 mod_timer(&adapter->watchdog_timer, jiffies);
3284 }
3285
3286#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3287 if (unlikely(hw->mac_type < e1000_82571)) {
3288 atomic_inc(&adapter->irq_sem);
3289 E1000_WRITE_REG(hw, IMC, ~0);
3290 E1000_WRITE_FLUSH(hw);
3291 }
24025e4e
MC		 3292#ifdef CONFIG_E1000_MQ
3293 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
f56799ea
JK		 3294 /* We must setup the cpumask once count == 0 since
3295 * each cpu bit is cleared when the work is done. */
3296 adapter->rx_sched_call_data.cpumask = adapter->cpumask;
3297 atomic_add(adapter->num_rx_queues - 1, &adapter->irq_sem);
3298 atomic_set(&adapter->rx_sched_call_data.count,
3299 adapter->num_rx_queues);
24025e4e
MC		 3300 smp_call_async_mask(&adapter->rx_sched_call_data);
3301 } else {
3302 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3303 }
be2b28ed 3304#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3305 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3306 __netif_rx_schedule(&adapter->polling_netdev[0]);
3307 else
3308 e1000_irq_enable(adapter);
be2b28ed
JG		 3309#endif /* CONFIG_E1000_MQ */
3310
3311#else /* if !CONFIG_E1000_NAPI */
1da177e4 3312 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3313 * Due to Hub Link bus being occupied, an interrupt
3314 * de-assertion message is not able to be sent.
3315 * When an interrupt assertion message is generated later,
3316 * two messages are re-ordered and sent out.
3317 * That causes APIC to think 82547 is in de-assertion
3318 * state, while 82547 is in assertion state, resulting
3319 * in dead lock. Writing IMC forces 82547 into
3320 * de-assertion state.
3321 */
3322 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3323 atomic_inc(&adapter->irq_sem);
2648345f 3324 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3325 }
3326
96838a40
JB		 3327 for (i = 0; i < E1000_MAX_INTR; i++)
3328 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3329 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3330 break;
3331
96838a40 3332 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3333 e1000_irq_enable(adapter);
581d708e 3334
be2b28ed 3335#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3336
3337 return IRQ_HANDLED;
3338}
3339
3340#ifdef CONFIG_E1000_NAPI
3341/**
3342 * e1000_clean - NAPI Rx polling callback
3343 * @adapter: board private structure
3344 **/
3345
3346static int
581d708e 3347e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3348{
581d708e
MC		 3349 struct e1000_adapter *adapter;
3350 int work_to_do = min(*budget, poll_dev->quota);
38bd3b26 3351 int tx_cleaned = 0, i = 0, work_done = 0;
581d708e
MC		 3352
3353 /* Must NOT use netdev_priv macro here. */
3354 adapter = poll_dev->priv;
3355
3356 /* Keep link state information with original netdev */
3357 if (!netif_carrier_ok(adapter->netdev))
3358 goto quit_polling;
2648345f 3359
581d708e
MC		 3360 while (poll_dev != &adapter->polling_netdev[i]) {
3361 i++;
f56799ea 3362 if (unlikely(i == adapter->num_rx_queues))
581d708e
MC		 3363 BUG();
3364 }
3365
8241e35e
JK		 3366 if (likely(adapter->num_tx_queues == 1)) {
3367 /* e1000_clean is called per-cpu. This lock protects
3368 * tx_ring[0] from being cleaned by multiple cpus
3369 * simultaneously. A failure obtaining the lock means
3370 * tx_ring[0] is currently being cleaned anyway. */
3371 if (spin_trylock(&adapter->tx_queue_lock)) {
3372 tx_cleaned = e1000_clean_tx_irq(adapter,
3373 &adapter->tx_ring[0]);
3374 spin_unlock(&adapter->tx_queue_lock);
3375 }
3376 } else
3377 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3378
581d708e
MC		 3379 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3380 &work_done, work_to_do);
1da177e4
LT		 3381
3382 *budget -= work_done;
581d708e 3383 poll_dev->quota -= work_done;
96838a40 3384
2b02893e 3385 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3386 if ((!tx_cleaned && (work_done == 0)) ||
581d708e
MC		 3387 !netif_running(adapter->netdev)) {
3388quit_polling:
3389 netif_rx_complete(poll_dev);
1da177e4
LT		 3390 e1000_irq_enable(adapter);
3391 return 0;
3392 }
3393
3394 return 1;
3395}
3396
3397#endif
3398/**
3399 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3400 * @adapter: board private structure
3401 **/
3402
3403static boolean_t
581d708e
MC		 3404e1000_clean_tx_irq(struct e1000_adapter *adapter,
3405 struct e1000_tx_ring *tx_ring)
1da177e4 3406{
1da177e4
LT		 3407 struct net_device *netdev = adapter->netdev;
3408 struct e1000_tx_desc *tx_desc, *eop_desc;
3409 struct e1000_buffer *buffer_info;
3410 unsigned int i, eop;
3411 boolean_t cleaned = FALSE;
3412
3413 i = tx_ring->next_to_clean;
3414 eop = tx_ring->buffer_info[i].next_to_watch;
3415 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3416
581d708e 3417 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3418 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3419 tx_desc = E1000_TX_DESC(*tx_ring, i);
3420 buffer_info = &tx_ring->buffer_info[i];
3421 cleaned = (i == eop);
3422
8241e35e
JK		 3423#ifdef CONFIG_E1000_MQ
3424 tx_ring->tx_stats.bytes += buffer_info->length;
3425#endif
fd803241 3426 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3427 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3428
96838a40 3429 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3430 }
581d708e 3431
7bfa4816
JK		 3432#ifdef CONFIG_E1000_MQ
3433 tx_ring->tx_stats.packets++;
3434#endif
3435
1da177e4
LT		 3436 eop = tx_ring->buffer_info[i].next_to_watch;
3437 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3438 }
3439
3440 tx_ring->next_to_clean = i;
3441
581d708e 3442 spin_lock(&tx_ring->tx_lock);
1da177e4 3443
96838a40 3444 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
1da177e4
LT		 3445 netif_carrier_ok(netdev)))
3446 netif_wake_queue(netdev);
3447
581d708e 3448 spin_unlock(&tx_ring->tx_lock);
2648345f 3449
581d708e 3450 if (adapter->detect_tx_hung) {
2648345f 3451 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3452 * check with the clearing of time_stamp and movement of i */
3453 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3454 if (tx_ring->buffer_info[eop].dma &&
3455 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
3456 adapter->tx_timeout_factor * HZ)
70b8f1e1 3457 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3458 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3459
3460 /* detected Tx unit hang */
c6963ef5 3461 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3462 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3463 " TDH <%x>\n"
3464 " TDT <%x>\n"
3465 " next_to_use <%x>\n"
3466 " next_to_clean <%x>\n"
3467 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3468 " time_stamp <%lx>\n"
3469 " next_to_watch <%x>\n"
3470 " jiffies <%lx>\n"
3471 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3472 (unsigned long)((tx_ring - adapter->tx_ring) /
3473 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3474 readl(adapter->hw.hw_addr + tx_ring->tdh),
3475 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3476 tx_ring->next_to_use,
392137fa
JK		 3477 tx_ring->next_to_clean,
3478 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3479 eop,
3480 jiffies,
3481 eop_desc->upper.fields.status);
1da177e4 3482 netif_stop_queue(netdev);
70b8f1e1 3483 }
1da177e4 3484 }
1da177e4
LT		 3485 return cleaned;
3486}
3487
3488/**
3489 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3490 * @adapter: board private structure
3491 * @status_err: receive descriptor status and error fields
3492 * @csum: receive descriptor csum field
3493 * @sk_buff: socket buffer with received data
1da177e4
LT		 3494 **/
3495
3496static inline void
3497e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3498 uint32_t status_err, uint32_t csum,
3499 struct sk_buff *skb)
1da177e4 3500{
2d7edb92
MC		 3501 uint16_t status = (uint16_t)status_err;
3502 uint8_t errors = (uint8_t)(status_err >> 24);
3503 skb->ip_summed = CHECKSUM_NONE;
3504
1da177e4 3505 /* 82543 or newer only */
96838a40 3506 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3507 /* Ignore Checksum bit is set */
96838a40 3508 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3509 /* TCP/UDP checksum error bit is set */
96838a40 3510 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3511 /* let the stack verify checksum errors */
1da177e4 3512 adapter->hw_csum_err++;
2d7edb92
MC		 3513 return;
3514 }
3515 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3516 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3517 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3518 return;
1da177e4 3519 } else {
96838a40 3520 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3521 return;
3522 }
3523 /* It must be a TCP or UDP packet with a valid checksum */
3524 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3525 /* TCP checksum is good */
3526 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3527 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3528 /* IP fragment with UDP payload */
3529 /* Hardware complements the payload checksum, so we undo it
3530 * and then put the value in host order for further stack use.
3531 */
3532 csum = ntohl(csum ^ 0xFFFF);
3533 skb->csum = csum;
3534 skb->ip_summed = CHECKSUM_HW;
1da177e4 3535 }
2d7edb92 3536 adapter->hw_csum_good++;
1da177e4
LT		 3537}
3538
3539/**
2d7edb92 3540 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3541 * @adapter: board private structure
3542 **/
3543
3544static boolean_t
3545#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3546e1000_clean_rx_irq(struct e1000_adapter *adapter,
3547 struct e1000_rx_ring *rx_ring,
3548 int *work_done, int work_to_do)
1da177e4 3549#else
581d708e
MC		 3550e1000_clean_rx_irq(struct e1000_adapter *adapter,
3551 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3552#endif
3553{
1da177e4
LT		 3554 struct net_device *netdev = adapter->netdev;
3555 struct pci_dev *pdev = adapter->pdev;
3556 struct e1000_rx_desc *rx_desc;
3557 struct e1000_buffer *buffer_info;
1da177e4
LT		 3558 unsigned long flags;
3559 uint32_t length;
3560 uint8_t last_byte;
3561 unsigned int i;
72d64a43 3562 int cleaned_count = 0;
a292ca6e 3563 boolean_t cleaned = FALSE, multi_descriptor = FALSE;
1da177e4
LT		 3564
3565 i = rx_ring->next_to_clean;
3566 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3567 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3568
b92ff8ee
JB		 3569 while (rx_desc->status & E1000_RXD_STAT_DD) {
3570 struct sk_buff *skb;
a292ca6e 3571 u8 status;
1da177e4 3572#ifdef CONFIG_E1000_NAPI
96838a40 3573 if (*work_done >= work_to_do)
1da177e4
LT		 3574 break;
3575 (*work_done)++;
3576#endif
a292ca6e 3577 status = rx_desc->status;
b92ff8ee 3578 skb = buffer_info->skb;
72d64a43
JK		 3579 cleaned = TRUE;
3580 cleaned_count++;
a292ca6e
JK		 3581 pci_unmap_single(pdev,
3582 buffer_info->dma,
3583 buffer_info->length,
1da177e4
LT		 3584 PCI_DMA_FROMDEVICE);
3585
1da177e4
LT		 3586 length = le16_to_cpu(rx_desc->length);
3587
b92ff8ee
JB		 3588 skb_put(skb, length);
3589
3590 if (!(status & E1000_RXD_STAT_EOP)) {
3591 if (!rx_ring->rx_skb_top) {
3592 rx_ring->rx_skb_top = skb;
3593 rx_ring->rx_skb_top->len = length;
3594 rx_ring->rx_skb_prev = skb;
3595 } else {
3596 if (skb_shinfo(rx_ring->rx_skb_top)->frag_list) {
3597 rx_ring->rx_skb_prev->next = skb;
3598 skb->prev = rx_ring->rx_skb_prev;
3599 } else {
3600 skb_shinfo(rx_ring->rx_skb_top)->frag_list = skb;
3601 }
3602 rx_ring->rx_skb_prev = skb;
3603 rx_ring->rx_skb_top->data_len += length;
3604 }
1da177e4 3605 goto next_desc;
b92ff8ee
JB		 3606 } else {
3607 if (rx_ring->rx_skb_top) {
3608 if (skb_shinfo(rx_ring->rx_skb_top)
3609 ->frag_list) {
3610 rx_ring->rx_skb_prev->next = skb;
3611 skb->prev = rx_ring->rx_skb_prev;
3612 } else
3613 skb_shinfo(rx_ring->rx_skb_top)
3614 ->frag_list = skb;
3615
3616 rx_ring->rx_skb_top->data_len += length;
3617 rx_ring->rx_skb_top->len +=
3618 rx_ring->rx_skb_top->data_len;
3619
3620 skb = rx_ring->rx_skb_top;
3621 multi_descriptor = TRUE;
3622 rx_ring->rx_skb_top = NULL;
3623 rx_ring->rx_skb_prev = NULL;
3624 }
1da177e4
LT		 3625 }
3626
96838a40 3627 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3628 last_byte = *(skb->data + length - 1);
b92ff8ee 3629 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3630 rx_desc->errors, length, last_byte)) {
3631 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3632 e1000_tbi_adjust_stats(&adapter->hw,
3633 &adapter->stats,
1da177e4
LT		 3634 length, skb->data);
3635 spin_unlock_irqrestore(&adapter->stats_lock,
3636 flags);
3637 length--;
3638 } else {
3639 dev_kfree_skb_irq(skb);
3640 goto next_desc;
3641 }
3642 }
3643
a292ca6e
JK		 3644 /* code added for copybreak, this should improve
3645 * performance for small packets with large amounts
3646 * of reassembly being done in the stack */
3647#define E1000_CB_LENGTH 256
3648 if ((length < E1000_CB_LENGTH) &&
3649 !rx_ring->rx_skb_top &&
3650 /* or maybe (status & E1000_RXD_STAT_EOP) && */
3651 !multi_descriptor) {
3652 struct sk_buff *new_skb =
3653 dev_alloc_skb(length + NET_IP_ALIGN);
3654 if (new_skb) {
3655 skb_reserve(new_skb, NET_IP_ALIGN);
3656 new_skb->dev = netdev;
3657 memcpy(new_skb->data - NET_IP_ALIGN,
3658 skb->data - NET_IP_ALIGN,
3659 length + NET_IP_ALIGN);
3660 /* save the skb in buffer_info as good */
3661 buffer_info->skb = skb;
3662 skb = new_skb;
3663 skb_put(skb, length);
3664 }
3665 }
3666
3667 /* end copybreak code */
1da177e4
LT		 3668
3669 /* Receive Checksum Offload */
a292ca6e
JK		 3670 e1000_rx_checksum(adapter,
3671 (uint32_t)(status) |
2d7edb92
MC		 3672 ((uint32_t)(rx_desc->errors) << 24),
3673 rx_desc->csum, skb);
96838a40 3674
1da177e4
LT		 3675 skb->protocol = eth_type_trans(skb, netdev);
3676#ifdef CONFIG_E1000_NAPI
96838a40 3677 if (unlikely(adapter->vlgrp &&
a292ca6e 3678 (status & E1000_RXD_STAT_VP))) {
1da177e4 3679 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3680 le16_to_cpu(rx_desc->special) &
3681 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3682 } else {
3683 netif_receive_skb(skb);
3684 }
3685#else /* CONFIG_E1000_NAPI */
96838a40 3686 if (unlikely(adapter->vlgrp &&
b92ff8ee 3687 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3688 vlan_hwaccel_rx(skb, adapter->vlgrp,
3689 le16_to_cpu(rx_desc->special) &
3690 E1000_RXD_SPC_VLAN_MASK);
3691 } else {
3692 netif_rx(skb);
3693 }
3694#endif /* CONFIG_E1000_NAPI */
3695 netdev->last_rx = jiffies;
7bfa4816
JK		 3696#ifdef CONFIG_E1000_MQ
3697 rx_ring->rx_stats.packets++;
3698 rx_ring->rx_stats.bytes += length;
3699#endif
1da177e4
LT		 3700
3701next_desc:
3702 rx_desc->status = 0;
1da177e4 3703
72d64a43
JK		 3704 /* return some buffers to hardware, one at a time is too slow */
3705 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3706 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3707 cleaned_count = 0;
3708 }
3709
1da177e4 3710 }
1da177e4 3711 rx_ring->next_to_clean = i;
72d64a43
JK		 3712
3713 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3714 if (cleaned_count)
3715 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3716
3717 return cleaned;
3718}
3719
3720/**
3721 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3722 * @adapter: board private structure
3723 **/
3724
3725static boolean_t
3726#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3727e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3728 struct e1000_rx_ring *rx_ring,
3729 int *work_done, int work_to_do)
2d7edb92 3730#else
581d708e
MC		 3731e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3732 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3733#endif
3734{
2d7edb92
MC		 3735 union e1000_rx_desc_packet_split *rx_desc;
3736 struct net_device *netdev = adapter->netdev;
3737 struct pci_dev *pdev = adapter->pdev;
3738 struct e1000_buffer *buffer_info;
3739 struct e1000_ps_page *ps_page;
3740 struct e1000_ps_page_dma *ps_page_dma;
3741 struct sk_buff *skb;
3742 unsigned int i, j;
3743 uint32_t length, staterr;
72d64a43 3744 int cleaned_count = 0;
2d7edb92
MC		 3745 boolean_t cleaned = FALSE;
3746
3747 i = rx_ring->next_to_clean;
3748 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3749 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92 3750
96838a40 3751 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3752 buffer_info = &rx_ring->buffer_info[i];
3753 ps_page = &rx_ring->ps_page[i];
3754 ps_page_dma = &rx_ring->ps_page_dma[i];
3755#ifdef CONFIG_E1000_NAPI
96838a40 3756 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3757 break;
3758 (*work_done)++;
3759#endif
3760 cleaned = TRUE;
72d64a43 3761 cleaned_count++;
2d7edb92
MC		 3762 pci_unmap_single(pdev, buffer_info->dma,
3763 buffer_info->length,
3764 PCI_DMA_FROMDEVICE);
3765
3766 skb = buffer_info->skb;
3767
96838a40 3768 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3769 E1000_DBG("%s: Packet Split buffers didn't pick up"
3770 " the full packet\n", netdev->name);
3771 dev_kfree_skb_irq(skb);
3772 goto next_desc;
3773 }
1da177e4 3774
96838a40 3775 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3776 dev_kfree_skb_irq(skb);
3777 goto next_desc;
3778 }
3779
3780 length = le16_to_cpu(rx_desc->wb.middle.length0);
3781
96838a40 3782 if (unlikely(!length)) {
2d7edb92
MC		 3783 E1000_DBG("%s: Last part of the packet spanning"
3784 " multiple descriptors\n", netdev->name);
3785 dev_kfree_skb_irq(skb);
3786 goto next_desc;
3787 }
3788
3789 /* Good Receive */
3790 skb_put(skb, length);
3791
96838a40
JB		 3792 for (j = 0; j < adapter->rx_ps_pages; j++) {
3793 if (!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92
MC		 3794 break;
3795
3796 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3797 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3798 ps_page_dma->ps_page_dma[j] = 0;
3799 skb_shinfo(skb)->frags[j].page =
3800 ps_page->ps_page[j];
3801 ps_page->ps_page[j] = NULL;
3802 skb_shinfo(skb)->frags[j].page_offset = 0;
3803 skb_shinfo(skb)->frags[j].size = length;
3804 skb_shinfo(skb)->nr_frags++;
3805 skb->len += length;
3806 skb->data_len += length;
3807 }
3808
3809 e1000_rx_checksum(adapter, staterr,
3810 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3811 skb->protocol = eth_type_trans(skb, netdev);
3812
96838a40 3813 if (likely(rx_desc->wb.upper.header_status &
b92ff8ee 3814 E1000_RXDPS_HDRSTAT_HDRSP))
e4c811c9 3815 adapter->rx_hdr_split++;
2d7edb92 3816#ifdef CONFIG_E1000_NAPI
96838a40 3817 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3818 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3819 le16_to_cpu(rx_desc->wb.middle.vlan) &
3820 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3821 } else {
3822 netif_receive_skb(skb);
3823 }
3824#else /* CONFIG_E1000_NAPI */
96838a40 3825 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3826 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3827 le16_to_cpu(rx_desc->wb.middle.vlan) &
3828 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3829 } else {
3830 netif_rx(skb);
3831 }
3832#endif /* CONFIG_E1000_NAPI */
3833 netdev->last_rx = jiffies;
7bfa4816
JK		 3834#ifdef CONFIG_E1000_MQ
3835 rx_ring->rx_stats.packets++;
3836 rx_ring->rx_stats.bytes += length;
3837#endif
2d7edb92
MC		 3838
3839next_desc:
3840 rx_desc->wb.middle.status_error &= ~0xFF;
3841 buffer_info->skb = NULL;
2d7edb92 3842
72d64a43
JK		 3843 /* return some buffers to hardware, one at a time is too slow */
3844 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3845 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3846 cleaned_count = 0;
3847 }
3848
683a38f3 3849 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3850 }
3851 rx_ring->next_to_clean = i;
72d64a43
JK		 3852
3853 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3854 if (cleaned_count)
3855 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3856
3857 return cleaned;
3858}
3859
3860/**
2d7edb92 3861 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3862 * @adapter: address of board private structure
3863 **/
3864
3865static void
581d708e 3866e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3867 struct e1000_rx_ring *rx_ring,
a292ca6e 3868 int cleaned_count)
1da177e4 3869{
1da177e4
LT		 3870 struct net_device *netdev = adapter->netdev;
3871 struct pci_dev *pdev = adapter->pdev;
3872 struct e1000_rx_desc *rx_desc;
3873 struct e1000_buffer *buffer_info;
3874 struct sk_buff *skb;
2648345f
MC		 3875 unsigned int i;
3876 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3877
3878 i = rx_ring->next_to_use;
3879 buffer_info = &rx_ring->buffer_info[i];
3880
a292ca6e
JK		 3881 while (cleaned_count--) {
3882 if (!(skb = buffer_info->skb))
3883 skb = dev_alloc_skb(bufsz);
3884 else {
3885 skb_trim(skb, 0);
3886 goto map_skb;
3887 }
3888
2648345f 3889
96838a40 3890 if (unlikely(!skb)) {
1da177e4 3891 /* Better luck next round */
72d64a43 3892 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3893 break;
3894 }
3895
2648345f 3896 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3897 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3898 struct sk_buff *oldskb = skb;
2648345f
MC		 3899 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3900 "at %p\n", bufsz, skb->data);
3901 /* Try again, without freeing the previous */
1da177e4 3902 skb = dev_alloc_skb(bufsz);
2648345f 3903 /* Failed allocation, critical failure */
1da177e4
LT		 3904 if (!skb) {
3905 dev_kfree_skb(oldskb);
3906 break;
3907 }
2648345f 3908
1da177e4
LT		 3909 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3910 /* give up */
3911 dev_kfree_skb(skb);
3912 dev_kfree_skb(oldskb);
3913 break; /* while !buffer_info->skb */
3914 } else {
2648345f 3915 /* Use new allocation */
1da177e4
LT		 3916 dev_kfree_skb(oldskb);
3917 }
3918 }
1da177e4
LT		 3919 /* Make buffer alignment 2 beyond a 16 byte boundary
3920 * this will result in a 16 byte aligned IP header after
3921 * the 14 byte MAC header is removed
3922 */
3923 skb_reserve(skb, NET_IP_ALIGN);
3924
3925 skb->dev = netdev;
3926
3927 buffer_info->skb = skb;
3928 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 3929map_skb:
1da177e4
LT		 3930 buffer_info->dma = pci_map_single(pdev,
3931 skb->data,
3932 adapter->rx_buffer_len,
3933 PCI_DMA_FROMDEVICE);
3934
2648345f
MC		 3935 /* Fix for errata 23, can't cross 64kB boundary */
3936 if (!e1000_check_64k_bound(adapter,
3937 (void *)(unsigned long)buffer_info->dma,
3938 adapter->rx_buffer_len)) {
3939 DPRINTK(RX_ERR, ERR,
3940 "dma align check failed: %u bytes at %p\n",
3941 adapter->rx_buffer_len,
3942 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3943 dev_kfree_skb(skb);
3944 buffer_info->skb = NULL;
3945
2648345f 3946 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3947 adapter->rx_buffer_len,
3948 PCI_DMA_FROMDEVICE);
3949
3950 break; /* while !buffer_info->skb */
3951 }
1da177e4
LT		 3952 rx_desc = E1000_RX_DESC(*rx_ring, i);
3953 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3954
96838a40
JB		 3955 if (unlikely(++i == rx_ring->count))
3956 i = 0;
1da177e4
LT		 3957 buffer_info = &rx_ring->buffer_info[i];
3958 }
3959
b92ff8ee
JB		 3960 if (likely(rx_ring->next_to_use != i)) {
3961 rx_ring->next_to_use = i;
3962 if (unlikely(i-- == 0))
3963 i = (rx_ring->count - 1);
3964
3965 /* Force memory writes to complete before letting h/w
3966 * know there are new descriptors to fetch. (Only
3967 * applicable for weak-ordered memory model archs,
3968 * such as IA-64). */
3969 wmb();
3970 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
3971 }
1da177e4
LT		 3972}
3973
2d7edb92
MC		 3974/**
3975 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3976 * @adapter: address of board private structure
3977 **/
3978
3979static void
581d708e 3980e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 3981 struct e1000_rx_ring *rx_ring,
3982 int cleaned_count)
2d7edb92 3983{
2d7edb92
MC		 3984 struct net_device *netdev = adapter->netdev;
3985 struct pci_dev *pdev = adapter->pdev;
3986 union e1000_rx_desc_packet_split *rx_desc;
3987 struct e1000_buffer *buffer_info;
3988 struct e1000_ps_page *ps_page;
3989 struct e1000_ps_page_dma *ps_page_dma;
3990 struct sk_buff *skb;
3991 unsigned int i, j;
3992
3993 i = rx_ring->next_to_use;
3994 buffer_info = &rx_ring->buffer_info[i];
3995 ps_page = &rx_ring->ps_page[i];
3996 ps_page_dma = &rx_ring->ps_page_dma[i];
3997
72d64a43 3998 while (cleaned_count--) {
2d7edb92
MC		 3999 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4000
96838a40 4001 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4002 if (j < adapter->rx_ps_pages) {
4003 if (likely(!ps_page->ps_page[j])) {
4004 ps_page->ps_page[j] =
4005 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4006 if (unlikely(!ps_page->ps_page[j])) {
4007 adapter->alloc_rx_buff_failed++;
e4c811c9 4008 goto no_buffers;
b92ff8ee 4009 }
e4c811c9
MC		 4010 ps_page_dma->ps_page_dma[j] =
4011 pci_map_page(pdev,
4012 ps_page->ps_page[j],
4013 0, PAGE_SIZE,
4014 PCI_DMA_FROMDEVICE);
4015 }
4016 /* Refresh the desc even if buffer_addrs didn't
96838a40 4017 * change because each write-back erases
e4c811c9
MC		 4018 * this info.
4019 */
4020 rx_desc->read.buffer_addr[j+1] =
4021 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4022 } else
4023 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4024 }
4025
4026 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4027
b92ff8ee
JB		 4028 if (unlikely(!skb)) {
4029 adapter->alloc_rx_buff_failed++;
2d7edb92 4030 break;
b92ff8ee 4031 }
2d7edb92
MC		 4032
4033 /* Make buffer alignment 2 beyond a 16 byte boundary
4034 * this will result in a 16 byte aligned IP header after
4035 * the 14 byte MAC header is removed
4036 */
4037 skb_reserve(skb, NET_IP_ALIGN);
4038
4039 skb->dev = netdev;
4040
4041 buffer_info->skb = skb;
4042 buffer_info->length = adapter->rx_ps_bsize0;
4043 buffer_info->dma = pci_map_single(pdev, skb->data,
4044 adapter->rx_ps_bsize0,
4045 PCI_DMA_FROMDEVICE);
4046
4047 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4048
96838a40 4049 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4050 buffer_info = &rx_ring->buffer_info[i];
4051 ps_page = &rx_ring->ps_page[i];
4052 ps_page_dma = &rx_ring->ps_page_dma[i];
4053 }
4054
4055no_buffers:
b92ff8ee
JB		 4056 if (likely(rx_ring->next_to_use != i)) {
4057 rx_ring->next_to_use = i;
4058 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4059
4060 /* Force memory writes to complete before letting h/w
4061 * know there are new descriptors to fetch. (Only
4062 * applicable for weak-ordered memory model archs,
4063 * such as IA-64). */
4064 wmb();
4065 /* Hardware increments by 16 bytes, but packet split
4066 * descriptors are 32 bytes...so we increment tail
4067 * twice as much.
4068 */
4069 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4070 }
2d7edb92
MC		 4071}
4072
1da177e4
LT		 4073/**
4074 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4075 * @adapter:
4076 **/
4077
4078static void
4079e1000_smartspeed(struct e1000_adapter *adapter)
4080{
4081 uint16_t phy_status;
4082 uint16_t phy_ctrl;
4083
96838a40 4084 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4085 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4086 return;
4087
96838a40 4088 if (adapter->smartspeed == 0) {
1da177e4
LT		 4089 /* If Master/Slave config fault is asserted twice,
4090 * we assume back-to-back */
4091 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4092 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4093 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4094 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4095 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4096 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4097 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4098 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4099 phy_ctrl);
4100 adapter->smartspeed++;
96838a40 4101 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4102 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4103 &phy_ctrl)) {
4104 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4105 MII_CR_RESTART_AUTO_NEG);
4106 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4107 phy_ctrl);
4108 }
4109 }
4110 return;
96838a40 4111 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4112 /* If still no link, perhaps using 2/3 pair cable */
4113 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4114 phy_ctrl |= CR_1000T_MS_ENABLE;
4115 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4116 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4117 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4118 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4119 MII_CR_RESTART_AUTO_NEG);
4120 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4121 }
4122 }
4123 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4124 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4125 adapter->smartspeed = 0;
4126}
4127
4128/**
4129 * e1000_ioctl -
4130 * @netdev:
4131 * @ifreq:
4132 * @cmd:
4133 **/
4134
4135static int
4136e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4137{
4138 switch (cmd) {
4139 case SIOCGMIIPHY:
4140 case SIOCGMIIREG:
4141 case SIOCSMIIREG:
4142 return e1000_mii_ioctl(netdev, ifr, cmd);
4143 default:
4144 return -EOPNOTSUPP;
4145 }
4146}
4147
4148/**
4149 * e1000_mii_ioctl -
4150 * @netdev:
4151 * @ifreq:
4152 * @cmd:
4153 **/
4154
4155static int
4156e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4157{
60490fe0 4158 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4159 struct mii_ioctl_data *data = if_mii(ifr);
4160 int retval;
4161 uint16_t mii_reg;
4162 uint16_t spddplx;
97876fc6 4163 unsigned long flags;
1da177e4 4164
96838a40 4165 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4166 return -EOPNOTSUPP;
4167
4168 switch (cmd) {
4169 case SIOCGMIIPHY:
4170 data->phy_id = adapter->hw.phy_addr;
4171 break;
4172 case SIOCGMIIREG:
96838a40 4173 if (!capable(CAP_NET_ADMIN))
1da177e4 4174 return -EPERM;
97876fc6 4175 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4176 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4177 &data->val_out)) {
4178 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4179 return -EIO;
97876fc6
MC		 4180 }
4181 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4182 break;
4183 case SIOCSMIIREG:
96838a40 4184 if (!capable(CAP_NET_ADMIN))
1da177e4 4185 return -EPERM;
96838a40 4186 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4187 return -EFAULT;
4188 mii_reg = data->val_in;
97876fc6 4189 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4190 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4191 mii_reg)) {
4192 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4193 return -EIO;
97876fc6 4194 }
96838a40 4195 if (adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 4196 switch (data->reg_num) {
4197 case PHY_CTRL:
96838a40 4198 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4199 break;
96838a40 4200 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4201 adapter->hw.autoneg = 1;
4202 adapter->hw.autoneg_advertised = 0x2F;
4203 } else {
4204 if (mii_reg & 0x40)
4205 spddplx = SPEED_1000;
4206 else if (mii_reg & 0x2000)
4207 spddplx = SPEED_100;
4208 else
4209 spddplx = SPEED_10;
4210 spddplx += (mii_reg & 0x100)
4211 ? FULL_DUPLEX :
4212 HALF_DUPLEX;
4213 retval = e1000_set_spd_dplx(adapter,
4214 spddplx);
96838a40 4215 if (retval) {
97876fc6 4216 spin_unlock_irqrestore(
96838a40 4217 &adapter->stats_lock,
97876fc6 4218 flags);
1da177e4 4219 return retval;
97876fc6 4220 }
1da177e4 4221 }
96838a40 4222 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4223 e1000_down(adapter);
4224 e1000_up(adapter);
4225 } else
4226 e1000_reset(adapter);
4227 break;
4228 case M88E1000_PHY_SPEC_CTRL:
4229 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4230 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4231 spin_unlock_irqrestore(
4232 &adapter->stats_lock, flags);
1da177e4 4233 return -EIO;
97876fc6 4234 }
1da177e4
LT		 4235 break;
4236 }
4237 } else {
4238 switch (data->reg_num) {
4239 case PHY_CTRL:
96838a40 4240 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4241 break;
96838a40 4242 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4243 e1000_down(adapter);
4244 e1000_up(adapter);
4245 } else
4246 e1000_reset(adapter);
4247 break;
4248 }
4249 }
97876fc6 4250 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4251 break;
4252 default:
4253 return -EOPNOTSUPP;
4254 }
4255 return E1000_SUCCESS;
4256}
4257
4258void
4259e1000_pci_set_mwi(struct e1000_hw *hw)
4260{
4261 struct e1000_adapter *adapter = hw->back;
2648345f 4262 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4263
96838a40 4264 if (ret_val)
2648345f 4265 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4266}
4267
4268void
4269e1000_pci_clear_mwi(struct e1000_hw *hw)
4270{
4271 struct e1000_adapter *adapter = hw->back;
4272
4273 pci_clear_mwi(adapter->pdev);
4274}
4275
4276void
4277e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4278{
4279 struct e1000_adapter *adapter = hw->back;
4280
4281 pci_read_config_word(adapter->pdev, reg, value);
4282}
4283
4284void
4285e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4286{
4287 struct e1000_adapter *adapter = hw->back;
4288
4289 pci_write_config_word(adapter->pdev, reg, *value);
4290}
4291
4292uint32_t
4293e1000_io_read(struct e1000_hw *hw, unsigned long port)
4294{
4295 return inl(port);
4296}
4297
4298void
4299e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4300{
4301 outl(value, port);
4302}
4303
4304static void
4305e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4306{
60490fe0 4307 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4308 uint32_t ctrl, rctl;
4309
4310 e1000_irq_disable(adapter);
4311 adapter->vlgrp = grp;
4312
96838a40 4313 if (grp) {
1da177e4
LT		 4314 /* enable VLAN tag insert/strip */
4315 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4316 ctrl |= E1000_CTRL_VME;
4317 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4318
4319 /* enable VLAN receive filtering */
4320 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4321 rctl |= E1000_RCTL_VFE;
4322 rctl &= ~E1000_RCTL_CFIEN;
4323 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4324 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4325 } else {
4326 /* disable VLAN tag insert/strip */
4327 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4328 ctrl &= ~E1000_CTRL_VME;
4329 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4330
4331 /* disable VLAN filtering */
4332 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4333 rctl &= ~E1000_RCTL_VFE;
4334 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4335 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4336 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4337 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4338 }
1da177e4
LT		 4339 }
4340
4341 e1000_irq_enable(adapter);
4342}
4343
4344static void
4345e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4346{
60490fe0 4347 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4348 uint32_t vfta, index;
96838a40
JB		 4349
4350 if ((adapter->hw.mng_cookie.status &
4351 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4352 (vid == adapter->mng_vlan_id))
2d7edb92 4353 return;
1da177e4
LT		 4354 /* add VID to filter table */
4355 index = (vid >> 5) & 0x7F;
4356 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4357 vfta |= (1 << (vid & 0x1F));
4358 e1000_write_vfta(&adapter->hw, index, vfta);
4359}
4360
4361static void
4362e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4363{
60490fe0 4364 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4365 uint32_t vfta, index;
4366
4367 e1000_irq_disable(adapter);
4368
96838a40 4369 if (adapter->vlgrp)
1da177e4
LT		 4370 adapter->vlgrp->vlan_devices[vid] = NULL;
4371
4372 e1000_irq_enable(adapter);
4373
96838a40
JB		 4374 if ((adapter->hw.mng_cookie.status &
4375 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4376 (vid == adapter->mng_vlan_id)) {
4377 /* release control to f/w */
4378 e1000_release_hw_control(adapter);
2d7edb92 4379 return;
ff147013
JK		 4380 }
4381
1da177e4
LT		 4382 /* remove VID from filter table */
4383 index = (vid >> 5) & 0x7F;
4384 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4385 vfta &= ~(1 << (vid & 0x1F));
4386 e1000_write_vfta(&adapter->hw, index, vfta);
4387}
4388
4389static void
4390e1000_restore_vlan(struct e1000_adapter *adapter)
4391{
4392 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4393
96838a40 4394 if (adapter->vlgrp) {
1da177e4 4395 uint16_t vid;
96838a40
JB		 4396 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4397 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4398 continue;
4399 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4400 }
4401 }
4402}
4403
4404int
4405e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4406{
4407 adapter->hw.autoneg = 0;
4408
6921368f 4409 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4410 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4411 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4412 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4413 return -EINVAL;
4414 }
4415
96838a40 4416 switch (spddplx) {
1da177e4
LT		 4417 case SPEED_10 + DUPLEX_HALF:
4418 adapter->hw.forced_speed_duplex = e1000_10_half;
4419 break;
4420 case SPEED_10 + DUPLEX_FULL:
4421 adapter->hw.forced_speed_duplex = e1000_10_full;
4422 break;
4423 case SPEED_100 + DUPLEX_HALF:
4424 adapter->hw.forced_speed_duplex = e1000_100_half;
4425 break;
4426 case SPEED_100 + DUPLEX_FULL:
4427 adapter->hw.forced_speed_duplex = e1000_100_full;
4428 break;
4429 case SPEED_1000 + DUPLEX_FULL:
4430 adapter->hw.autoneg = 1;
4431 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4432 break;
4433 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4434 default:
2648345f 4435 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4436 return -EINVAL;
4437 }
4438 return 0;
4439}
4440
b6a1d5f8 4441#ifdef CONFIG_PM
2f82665f
JB		 4442/* these functions save and restore 16 or 64 dwords (64-256 bytes) of config
4443 * space versus the 64 bytes that pci_[save|restore]_state handle
4444 */
4445#define PCIE_CONFIG_SPACE_LEN 256
4446#define PCI_CONFIG_SPACE_LEN 64
4447static int
4448e1000_pci_save_state(struct e1000_adapter *adapter)
4449{
4450 struct pci_dev *dev = adapter->pdev;
4451 int size;
4452 int i;
4453 if (adapter->hw.mac_type >= e1000_82571)
4454 size = PCIE_CONFIG_SPACE_LEN;
4455 else
4456 size = PCI_CONFIG_SPACE_LEN;
4457
4458 WARN_ON(adapter->config_space != NULL);
4459
4460 adapter->config_space = kmalloc(size, GFP_KERNEL);
4461 if (!adapter->config_space) {
4462 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4463 return -ENOMEM;
4464 }
4465 for (i = 0; i < (size / 4); i++)
4466 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4467 return 0;
4468}
4469
4470static void
4471e1000_pci_restore_state(struct e1000_adapter *adapter)
4472{
4473 struct pci_dev *dev = adapter->pdev;
4474 int size;
4475 int i;
4476 if (adapter->config_space == NULL)
4477 return;
4478 if (adapter->hw.mac_type >= e1000_82571)
4479 size = PCIE_CONFIG_SPACE_LEN;
4480 else
4481 size = PCI_CONFIG_SPACE_LEN;
4482 for (i = 0; i < (size / 4); i++)
4483 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4484 kfree(adapter->config_space);
4485 adapter->config_space = NULL;
4486 return;
4487}
4488#endif /* CONFIG_PM */
4489
1da177e4 4490static int
829ca9a3 4491e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4492{
4493 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4494 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4495 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4496 uint32_t wufc = adapter->wol;
240b1710 4497 int retval = 0;
1da177e4
LT		 4498
4499 netif_device_detach(netdev);
4500
96838a40 4501 if (netif_running(netdev))
1da177e4
LT		 4502 e1000_down(adapter);
4503
2f82665f
JB		 4504#ifdef CONFIG_PM
4505 /* implement our own version of pci_save_state(pdev) because pci
4506 * express adapters have larger 256 byte config spaces */
4507 retval = e1000_pci_save_state(adapter);
4508 if (retval)
4509 return retval;
4510#endif
4511
1da177e4 4512 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4513 if (status & E1000_STATUS_LU)
1da177e4
LT		 4514 wufc &= ~E1000_WUFC_LNKC;
4515
96838a40 4516 if (wufc) {
1da177e4
LT		 4517 e1000_setup_rctl(adapter);
4518 e1000_set_multi(netdev);
4519
4520 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4521 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4522 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4523 rctl |= E1000_RCTL_MPE;
4524 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4525 }
4526
96838a40 4527 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4528 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4529 /* advertise wake from D3Cold */
4530 #define E1000_CTRL_ADVD3WUC 0x00100000
4531 /* phy power management enable */
4532 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4533 ctrl |= E1000_CTRL_ADVD3WUC |
4534 E1000_CTRL_EN_PHY_PWR_MGMT;
4535 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4536 }
4537
96838a40 4538 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4539 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4540 /* keep the laser running in D3 */
4541 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4542 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4543 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4544 }
4545
2d7edb92
MC		 4546 /* Allow time for pending master requests to run */
4547 e1000_disable_pciex_master(&adapter->hw);
4548
1da177e4
LT		 4549 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4550 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
240b1710
JK		 4551 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4552 if (retval)
4553 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4554 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4555 if (retval)
4556 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4557 } else {
4558 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4559 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
240b1710
JK		 4560 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4561 if (retval)
4562 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4563 retval = pci_enable_wake(pdev, PCI_D3cold, 0); /* 4 == D3 cold */
4564 if (retval)
4565 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4566 }
4567
96838a40 4568 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4569 adapter->hw.media_type == e1000_media_type_copper) {
4570 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4571 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4572 manc |= E1000_MANC_ARP_EN;
4573 E1000_WRITE_REG(&adapter->hw, MANC, manc);
240b1710
JK		 4574 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4575 if (retval)
4576 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4577 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4578 if (retval)
4579 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4580 }
4581 }
4582
b55ccb35
JK		 4583 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4584 * would have already happened in close and is redundant. */
4585 e1000_release_hw_control(adapter);
2d7edb92 4586
1da177e4 4587 pci_disable_device(pdev);
240b1710
JK		 4588
4589 retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
4590 if (retval)
4591 DPRINTK(PROBE, ERR, "Error in setting power state\n");
1da177e4
LT		 4592
4593 return 0;
4594}
4595
2f82665f 4596#ifdef CONFIG_PM
1da177e4
LT		 4597static int
4598e1000_resume(struct pci_dev *pdev)
4599{
4600 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4601 struct e1000_adapter *adapter = netdev_priv(netdev);
240b1710 4602 int retval;
b55ccb35 4603 uint32_t manc, ret_val;
1da177e4 4604
240b1710
JK		 4605 retval = pci_set_power_state(pdev, PCI_D0);
4606 if (retval)
4607 DPRINTK(PROBE, ERR, "Error in setting power state\n");
2f82665f 4608 e1000_pci_restore_state(adapter);
2b02893e 4609 ret_val = pci_enable_device(pdev);
a4cb847d 4610 pci_set_master(pdev);
1da177e4 4611
240b1710
JK		 4612 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4613 if (retval)
4614 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4615 retval = pci_enable_wake(pdev, PCI_D3cold, 0);
4616 if (retval)
4617 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4618
4619 e1000_reset(adapter);
4620 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4621
96838a40 4622 if (netif_running(netdev))
1da177e4
LT		 4623 e1000_up(adapter);
4624
4625 netif_device_attach(netdev);
4626
96838a40 4627 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4628 adapter->hw.media_type == e1000_media_type_copper) {
4629 manc = E1000_READ_REG(&adapter->hw, MANC);
4630 manc &= ~(E1000_MANC_ARP_EN);
4631 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4632 }
4633
b55ccb35
JK		 4634 /* If the controller is 82573 and f/w is AMT, do not set
4635 * DRV_LOAD until the interface is up. For all other cases,
4636 * let the f/w know that the h/w is now under the control
4637 * of the driver. */
4638 if (adapter->hw.mac_type != e1000_82573 ||
4639 !e1000_check_mng_mode(&adapter->hw))
4640 e1000_get_hw_control(adapter);
2d7edb92 4641
1da177e4
LT		 4642 return 0;
4643}
4644#endif
1da177e4
LT		 4645#ifdef CONFIG_NET_POLL_CONTROLLER
4646/*
4647 * Polling 'interrupt' - used by things like netconsole to send skbs
4648 * without having to re-enable interrupts. It's not called while
4649 * the interrupt routine is executing.
4650 */
4651static void
2648345f 4652e1000_netpoll(struct net_device *netdev)
1da177e4 4653{
60490fe0 4654 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4655 disable_irq(adapter->pdev->irq);
4656 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4657 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4658#ifndef CONFIG_E1000_NAPI
4659 adapter->clean_rx(adapter, adapter->rx_ring);
4660#endif
1da177e4
LT		 4661 enable_irq(adapter->pdev->irq);
4662}
4663#endif
4664
4665/* e1000_main.c */
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