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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
55 | ||
4662e82b BA |
56 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
57 | ||
bc7f75fa AK |
58 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
59 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
60 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 61 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
62 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
63 | u16 words, u16 *data); | |
64 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
65 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
66 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
67 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
4662e82b BA |
68 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
69 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 70 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
bc7f75fa AK |
71 | |
72 | /** | |
73 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
74 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
75 | **/ |
76 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
77 | { | |
78 | struct e1000_phy_info *phy = &hw->phy; | |
79 | s32 ret_val; | |
80 | ||
318a94d6 | 81 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
82 | phy->type = e1000_phy_none; |
83 | return 0; | |
84 | } | |
85 | ||
86 | phy->addr = 1; | |
87 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
88 | phy->reset_delay_us = 100; | |
89 | ||
90 | switch (hw->mac.type) { | |
91 | case e1000_82571: | |
92 | case e1000_82572: | |
93 | phy->type = e1000_phy_igp_2; | |
94 | break; | |
95 | case e1000_82573: | |
96 | phy->type = e1000_phy_m88; | |
97 | break; | |
4662e82b | 98 | case e1000_82574: |
8c81c9c3 | 99 | case e1000_82583: |
4662e82b BA |
100 | phy->type = e1000_phy_bm; |
101 | break; | |
bc7f75fa AK |
102 | default: |
103 | return -E1000_ERR_PHY; | |
104 | break; | |
105 | } | |
106 | ||
107 | /* This can only be done after all function pointers are setup. */ | |
108 | ret_val = e1000_get_phy_id_82571(hw); | |
109 | ||
110 | /* Verify phy id */ | |
111 | switch (hw->mac.type) { | |
112 | case e1000_82571: | |
113 | case e1000_82572: | |
114 | if (phy->id != IGP01E1000_I_PHY_ID) | |
115 | return -E1000_ERR_PHY; | |
116 | break; | |
117 | case e1000_82573: | |
118 | if (phy->id != M88E1111_I_PHY_ID) | |
119 | return -E1000_ERR_PHY; | |
120 | break; | |
4662e82b | 121 | case e1000_82574: |
8c81c9c3 | 122 | case e1000_82583: |
4662e82b BA |
123 | if (phy->id != BME1000_E_PHY_ID_R2) |
124 | return -E1000_ERR_PHY; | |
125 | break; | |
bc7f75fa AK |
126 | default: |
127 | return -E1000_ERR_PHY; | |
128 | break; | |
129 | } | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /** | |
135 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
136 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
137 | **/ |
138 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
139 | { | |
140 | struct e1000_nvm_info *nvm = &hw->nvm; | |
141 | u32 eecd = er32(EECD); | |
142 | u16 size; | |
143 | ||
144 | nvm->opcode_bits = 8; | |
145 | nvm->delay_usec = 1; | |
146 | switch (nvm->override) { | |
147 | case e1000_nvm_override_spi_large: | |
148 | nvm->page_size = 32; | |
149 | nvm->address_bits = 16; | |
150 | break; | |
151 | case e1000_nvm_override_spi_small: | |
152 | nvm->page_size = 8; | |
153 | nvm->address_bits = 8; | |
154 | break; | |
155 | default: | |
156 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
157 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
158 | break; | |
159 | } | |
160 | ||
161 | switch (hw->mac.type) { | |
162 | case e1000_82573: | |
4662e82b | 163 | case e1000_82574: |
8c81c9c3 | 164 | case e1000_82583: |
bc7f75fa AK |
165 | if (((eecd >> 15) & 0x3) == 0x3) { |
166 | nvm->type = e1000_nvm_flash_hw; | |
167 | nvm->word_size = 2048; | |
ad68076e BA |
168 | /* |
169 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
170 | * to Flash update issue. |
171 | */ | |
172 | eecd &= ~E1000_EECD_AUPDEN; | |
173 | ew32(EECD, eecd); | |
174 | break; | |
175 | } | |
176 | /* Fall Through */ | |
177 | default: | |
ad68076e | 178 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
179 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
180 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
181 | /* |
182 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
183 | * for setting word_size. |
184 | */ | |
185 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
186 | |
187 | /* EEPROM access above 16k is unsupported */ | |
188 | if (size > 14) | |
189 | size = 14; | |
bc7f75fa AK |
190 | nvm->word_size = 1 << size; |
191 | break; | |
192 | } | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
199 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
200 | **/ |
201 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
202 | { | |
203 | struct e1000_hw *hw = &adapter->hw; | |
204 | struct e1000_mac_info *mac = &hw->mac; | |
205 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
206 | u32 swsm = 0; |
207 | u32 swsm2 = 0; | |
208 | bool force_clear_smbi = false; | |
bc7f75fa AK |
209 | |
210 | /* Set media type */ | |
211 | switch (adapter->pdev->device) { | |
212 | case E1000_DEV_ID_82571EB_FIBER: | |
213 | case E1000_DEV_ID_82572EI_FIBER: | |
214 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 215 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
216 | break; |
217 | case E1000_DEV_ID_82571EB_SERDES: | |
218 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
219 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
220 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 221 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
222 | break; |
223 | default: | |
318a94d6 | 224 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
225 | break; |
226 | } | |
227 | ||
228 | /* Set mta register count */ | |
229 | mac->mta_reg_count = 128; | |
230 | /* Set rar entry count */ | |
231 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
232 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
233 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
234 | ? true : false; | |
bc7f75fa AK |
235 | |
236 | /* check for link */ | |
318a94d6 | 237 | switch (hw->phy.media_type) { |
bc7f75fa AK |
238 | case e1000_media_type_copper: |
239 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
240 | func->check_for_link = e1000e_check_for_copper_link; | |
241 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
242 | break; | |
243 | case e1000_media_type_fiber: | |
ad68076e BA |
244 | func->setup_physical_interface = |
245 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 246 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
247 | func->get_link_up_info = |
248 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
249 | break; |
250 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
251 | func->setup_physical_interface = |
252 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 253 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
254 | func->get_link_up_info = |
255 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
256 | break; |
257 | default: | |
258 | return -E1000_ERR_CONFIG; | |
259 | break; | |
260 | } | |
261 | ||
4662e82b BA |
262 | switch (hw->mac.type) { |
263 | case e1000_82574: | |
8c81c9c3 | 264 | case e1000_82583: |
4662e82b BA |
265 | func->check_mng_mode = e1000_check_mng_mode_82574; |
266 | func->led_on = e1000_led_on_82574; | |
267 | break; | |
268 | default: | |
269 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
270 | func->led_on = e1000e_led_on_generic; | |
271 | break; | |
272 | } | |
273 | ||
23a2d1b2 DG |
274 | /* |
275 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
276 | * first NVM or PHY acess. This should be done for single-port | |
277 | * devices, and for one port only on dual-port devices so that | |
278 | * for those devices we can still use the SMBI lock to synchronize | |
279 | * inter-port accesses to the PHY & NVM. | |
280 | */ | |
281 | switch (hw->mac.type) { | |
282 | case e1000_82571: | |
283 | case e1000_82572: | |
284 | swsm2 = er32(SWSM2); | |
285 | ||
286 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
287 | /* Only do this for the first interface on this card */ | |
288 | ew32(SWSM2, | |
289 | swsm2 | E1000_SWSM2_LOCK); | |
290 | force_clear_smbi = true; | |
291 | } else | |
292 | force_clear_smbi = false; | |
293 | break; | |
294 | default: | |
295 | force_clear_smbi = true; | |
296 | break; | |
297 | } | |
298 | ||
299 | if (force_clear_smbi) { | |
300 | /* Make sure SWSM.SMBI is clear */ | |
301 | swsm = er32(SWSM); | |
302 | if (swsm & E1000_SWSM_SMBI) { | |
303 | /* This bit should not be set on a first interface, and | |
304 | * indicates that the bootagent or EFI code has | |
305 | * improperly left this bit enabled | |
306 | */ | |
3bb99fe2 | 307 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
308 | } |
309 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
310 | } | |
311 | ||
312 | /* | |
313 | * Initialze device specific counter of SMBI acquisition | |
314 | * timeouts. | |
315 | */ | |
316 | hw->dev_spec.e82571.smb_counter = 0; | |
317 | ||
bc7f75fa AK |
318 | return 0; |
319 | } | |
320 | ||
69e3fd8c | 321 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
322 | { |
323 | struct e1000_hw *hw = &adapter->hw; | |
324 | static int global_quad_port_a; /* global port a indication */ | |
325 | struct pci_dev *pdev = adapter->pdev; | |
326 | u16 eeprom_data = 0; | |
327 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
328 | s32 rc; | |
329 | ||
330 | rc = e1000_init_mac_params_82571(adapter); | |
331 | if (rc) | |
332 | return rc; | |
333 | ||
334 | rc = e1000_init_nvm_params_82571(hw); | |
335 | if (rc) | |
336 | return rc; | |
337 | ||
338 | rc = e1000_init_phy_params_82571(hw); | |
339 | if (rc) | |
340 | return rc; | |
341 | ||
342 | /* tag quad port adapters first, it's used below */ | |
343 | switch (pdev->device) { | |
344 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
345 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
346 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 347 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
348 | adapter->flags |= FLAG_IS_QUAD_PORT; |
349 | /* mark the first port */ | |
350 | if (global_quad_port_a == 0) | |
351 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
352 | /* Reset for multiple quad port adapters */ | |
353 | global_quad_port_a++; | |
354 | if (global_quad_port_a == 4) | |
355 | global_quad_port_a = 0; | |
356 | break; | |
357 | default: | |
358 | break; | |
359 | } | |
360 | ||
361 | switch (adapter->hw.mac.type) { | |
362 | case e1000_82571: | |
363 | /* these dual ports don't have WoL on port B at all */ | |
364 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
365 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
366 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
367 | (is_port_b)) | |
368 | adapter->flags &= ~FLAG_HAS_WOL; | |
369 | /* quad ports only support WoL on port A */ | |
370 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 371 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 372 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
373 | /* Does not support WoL on any port */ |
374 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
375 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
376 | break; |
377 | ||
378 | case e1000_82573: | |
379 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
380 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
381 | &eeprom_data) < 0) | |
382 | break; | |
2adc55c9 BA |
383 | if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { |
384 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; | |
385 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
386 | } | |
bc7f75fa AK |
387 | } |
388 | break; | |
389 | default: | |
390 | break; | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /** | |
397 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
398 | * @hw: pointer to the HW structure | |
399 | * | |
400 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
401 | * revision in the hardware structure. | |
402 | **/ | |
403 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
404 | { | |
405 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
406 | s32 ret_val; |
407 | u16 phy_id = 0; | |
bc7f75fa AK |
408 | |
409 | switch (hw->mac.type) { | |
410 | case e1000_82571: | |
411 | case e1000_82572: | |
ad68076e BA |
412 | /* |
413 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
414 | * In this case, we cannot access the PHY until the |
415 | * configuration is done. So we explicitly set the | |
ad68076e BA |
416 | * PHY ID. |
417 | */ | |
bc7f75fa AK |
418 | phy->id = IGP01E1000_I_PHY_ID; |
419 | break; | |
420 | case e1000_82573: | |
421 | return e1000e_get_phy_id(hw); | |
422 | break; | |
4662e82b | 423 | case e1000_82574: |
8c81c9c3 | 424 | case e1000_82583: |
4662e82b BA |
425 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
426 | if (ret_val) | |
427 | return ret_val; | |
428 | ||
429 | phy->id = (u32)(phy_id << 16); | |
430 | udelay(20); | |
431 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
432 | if (ret_val) | |
433 | return ret_val; | |
434 | ||
435 | phy->id |= (u32)(phy_id); | |
436 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
437 | break; | |
bc7f75fa AK |
438 | default: |
439 | return -E1000_ERR_PHY; | |
440 | break; | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | /** | |
447 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
448 | * @hw: pointer to the HW structure | |
449 | * | |
450 | * Acquire the HW semaphore to access the PHY or NVM | |
451 | **/ | |
452 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
453 | { | |
454 | u32 swsm; | |
23a2d1b2 DG |
455 | s32 sw_timeout = hw->nvm.word_size + 1; |
456 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
457 | s32 i = 0; |
458 | ||
23a2d1b2 DG |
459 | /* |
460 | * If we have timedout 3 times on trying to acquire | |
461 | * the inter-port SMBI semaphore, there is old code | |
462 | * operating on the other port, and it is not | |
463 | * releasing SMBI. Modify the number of times that | |
464 | * we try for the semaphore to interwork with this | |
465 | * older code. | |
466 | */ | |
467 | if (hw->dev_spec.e82571.smb_counter > 2) | |
468 | sw_timeout = 1; | |
469 | ||
470 | /* Get the SW semaphore */ | |
471 | while (i < sw_timeout) { | |
472 | swsm = er32(SWSM); | |
473 | if (!(swsm & E1000_SWSM_SMBI)) | |
474 | break; | |
475 | ||
476 | udelay(50); | |
477 | i++; | |
478 | } | |
479 | ||
480 | if (i == sw_timeout) { | |
3bb99fe2 | 481 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
482 | hw->dev_spec.e82571.smb_counter++; |
483 | } | |
bc7f75fa | 484 | /* Get the FW semaphore. */ |
23a2d1b2 | 485 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
486 | swsm = er32(SWSM); |
487 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
488 | ||
489 | /* Semaphore acquired if bit latched */ | |
490 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
491 | break; | |
492 | ||
493 | udelay(50); | |
494 | } | |
495 | ||
23a2d1b2 | 496 | if (i == fw_timeout) { |
bc7f75fa | 497 | /* Release semaphores */ |
23a2d1b2 | 498 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 499 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
500 | return -E1000_ERR_NVM; |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | /** | |
507 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
508 | * @hw: pointer to the HW structure | |
509 | * | |
510 | * Release hardware semaphore used to access the PHY or NVM | |
511 | **/ | |
512 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
513 | { | |
514 | u32 swsm; | |
515 | ||
516 | swsm = er32(SWSM); | |
23a2d1b2 | 517 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
518 | ew32(SWSM, swsm); |
519 | } | |
520 | ||
521 | /** | |
522 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
523 | * @hw: pointer to the HW structure | |
524 | * | |
525 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
526 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
527 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
528 | * hardware semaphore. | |
529 | **/ | |
530 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
531 | { | |
532 | s32 ret_val; | |
533 | ||
534 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
535 | if (ret_val) | |
536 | return ret_val; | |
537 | ||
8c81c9c3 AD |
538 | switch (hw->mac.type) { |
539 | case e1000_82573: | |
540 | case e1000_82574: | |
541 | case e1000_82583: | |
542 | break; | |
543 | default: | |
bc7f75fa | 544 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
545 | break; |
546 | } | |
bc7f75fa AK |
547 | |
548 | if (ret_val) | |
549 | e1000_put_hw_semaphore_82571(hw); | |
550 | ||
551 | return ret_val; | |
552 | } | |
553 | ||
554 | /** | |
555 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
556 | * @hw: pointer to the HW structure | |
557 | * | |
558 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
559 | **/ | |
560 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
561 | { | |
562 | e1000e_release_nvm(hw); | |
563 | e1000_put_hw_semaphore_82571(hw); | |
564 | } | |
565 | ||
566 | /** | |
567 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
568 | * @hw: pointer to the HW structure | |
569 | * @offset: offset within the EEPROM to be written to | |
570 | * @words: number of words to write | |
571 | * @data: 16 bit word(s) to be written to the EEPROM | |
572 | * | |
573 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
574 | * | |
575 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 576 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
577 | **/ |
578 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
579 | u16 *data) | |
580 | { | |
581 | s32 ret_val; | |
582 | ||
583 | switch (hw->mac.type) { | |
584 | case e1000_82573: | |
4662e82b | 585 | case e1000_82574: |
8c81c9c3 | 586 | case e1000_82583: |
bc7f75fa AK |
587 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
588 | break; | |
589 | case e1000_82571: | |
590 | case e1000_82572: | |
591 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
592 | break; | |
593 | default: | |
594 | ret_val = -E1000_ERR_NVM; | |
595 | break; | |
596 | } | |
597 | ||
598 | return ret_val; | |
599 | } | |
600 | ||
601 | /** | |
602 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
603 | * @hw: pointer to the HW structure | |
604 | * | |
605 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
606 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
607 | * value to the EEPROM. | |
608 | **/ | |
609 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
610 | { | |
611 | u32 eecd; | |
612 | s32 ret_val; | |
613 | u16 i; | |
614 | ||
615 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
616 | if (ret_val) | |
617 | return ret_val; | |
618 | ||
ad68076e BA |
619 | /* |
620 | * If our nvm is an EEPROM, then we're done | |
621 | * otherwise, commit the checksum to the flash NVM. | |
622 | */ | |
bc7f75fa AK |
623 | if (hw->nvm.type != e1000_nvm_flash_hw) |
624 | return ret_val; | |
625 | ||
626 | /* Check for pending operations. */ | |
627 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
628 | msleep(1); | |
629 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
630 | break; | |
631 | } | |
632 | ||
633 | if (i == E1000_FLASH_UPDATES) | |
634 | return -E1000_ERR_NVM; | |
635 | ||
636 | /* Reset the firmware if using STM opcode. */ | |
637 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
638 | /* |
639 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
640 | * in two write cycles. |
641 | */ | |
642 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
643 | e1e_flush(); | |
644 | ew32(HICR, E1000_HICR_FW_RESET); | |
645 | } | |
646 | ||
647 | /* Commit the write to flash */ | |
648 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
649 | ew32(EECD, eecd); | |
650 | ||
651 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
652 | msleep(1); | |
653 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
654 | break; | |
655 | } | |
656 | ||
657 | if (i == E1000_FLASH_UPDATES) | |
658 | return -E1000_ERR_NVM; | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | /** | |
664 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
665 | * @hw: pointer to the HW structure | |
666 | * | |
667 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
668 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
669 | **/ | |
670 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
671 | { | |
672 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
673 | e1000_fix_nvm_checksum_82571(hw); | |
674 | ||
675 | return e1000e_validate_nvm_checksum_generic(hw); | |
676 | } | |
677 | ||
678 | /** | |
679 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
680 | * @hw: pointer to the HW structure | |
681 | * @offset: offset within the EEPROM to be written to | |
682 | * @words: number of words to write | |
683 | * @data: 16 bit word(s) to be written to the EEPROM | |
684 | * | |
685 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
686 | * command has completed before trying to write the next word. After write | |
687 | * poll for completion. | |
688 | * | |
689 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 690 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
691 | **/ |
692 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
693 | u16 words, u16 *data) | |
694 | { | |
695 | struct e1000_nvm_info *nvm = &hw->nvm; | |
696 | u32 i; | |
697 | u32 eewr = 0; | |
698 | s32 ret_val = 0; | |
699 | ||
ad68076e BA |
700 | /* |
701 | * A check for invalid values: offset too large, too many words, | |
702 | * and not enough words. | |
703 | */ | |
bc7f75fa AK |
704 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
705 | (words == 0)) { | |
3bb99fe2 | 706 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
707 | return -E1000_ERR_NVM; |
708 | } | |
709 | ||
710 | for (i = 0; i < words; i++) { | |
711 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
712 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
713 | E1000_NVM_RW_REG_START; | |
714 | ||
715 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
716 | if (ret_val) | |
717 | break; | |
718 | ||
719 | ew32(EEWR, eewr); | |
720 | ||
721 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
722 | if (ret_val) | |
723 | break; | |
724 | } | |
725 | ||
726 | return ret_val; | |
727 | } | |
728 | ||
729 | /** | |
730 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
731 | * @hw: pointer to the HW structure | |
732 | * | |
733 | * Reads the management control register for the config done bit to be set. | |
734 | **/ | |
735 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
736 | { | |
737 | s32 timeout = PHY_CFG_TIMEOUT; | |
738 | ||
739 | while (timeout) { | |
740 | if (er32(EEMNGCTL) & | |
741 | E1000_NVM_CFG_DONE_PORT_0) | |
742 | break; | |
743 | msleep(1); | |
744 | timeout--; | |
745 | } | |
746 | if (!timeout) { | |
3bb99fe2 | 747 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
748 | return -E1000_ERR_RESET; |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
754 | /** | |
755 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
756 | * @hw: pointer to the HW structure | |
564ea9bb | 757 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
758 | * |
759 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
760 | * this function also disables smart speed and vice versa. LPLU will not be | |
761 | * activated unless the device autonegotiation advertisement meets standards | |
762 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
763 | * pointer entry point only called by PHY setup routines. | |
764 | **/ | |
765 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
766 | { | |
767 | struct e1000_phy_info *phy = &hw->phy; | |
768 | s32 ret_val; | |
769 | u16 data; | |
770 | ||
771 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
772 | if (ret_val) | |
773 | return ret_val; | |
774 | ||
775 | if (active) { | |
776 | data |= IGP02E1000_PM_D0_LPLU; | |
777 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
778 | if (ret_val) | |
779 | return ret_val; | |
780 | ||
781 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
782 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
783 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
784 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
785 | if (ret_val) | |
786 | return ret_val; | |
787 | } else { | |
788 | data &= ~IGP02E1000_PM_D0_LPLU; | |
789 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
790 | /* |
791 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
792 | * during Dx states where the power conservation is most |
793 | * important. During driver activity we should enable | |
ad68076e BA |
794 | * SmartSpeed, so performance is maintained. |
795 | */ | |
bc7f75fa AK |
796 | if (phy->smart_speed == e1000_smart_speed_on) { |
797 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 798 | &data); |
bc7f75fa AK |
799 | if (ret_val) |
800 | return ret_val; | |
801 | ||
802 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
803 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 804 | data); |
bc7f75fa AK |
805 | if (ret_val) |
806 | return ret_val; | |
807 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
808 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 809 | &data); |
bc7f75fa AK |
810 | if (ret_val) |
811 | return ret_val; | |
812 | ||
813 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
814 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 815 | data); |
bc7f75fa AK |
816 | if (ret_val) |
817 | return ret_val; | |
818 | } | |
819 | } | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | /** | |
825 | * e1000_reset_hw_82571 - Reset hardware | |
826 | * @hw: pointer to the HW structure | |
827 | * | |
fe401674 | 828 | * This resets the hardware into a known state. |
bc7f75fa AK |
829 | **/ |
830 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
831 | { | |
832 | u32 ctrl; | |
833 | u32 extcnf_ctrl; | |
834 | u32 ctrl_ext; | |
835 | u32 icr; | |
836 | s32 ret_val; | |
837 | u16 i = 0; | |
838 | ||
ad68076e BA |
839 | /* |
840 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
841 | * on the last TLP read/write transaction when MAC is reset. |
842 | */ | |
843 | ret_val = e1000e_disable_pcie_master(hw); | |
844 | if (ret_val) | |
3bb99fe2 | 845 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 846 | |
3bb99fe2 | 847 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
848 | ew32(IMC, 0xffffffff); |
849 | ||
850 | ew32(RCTL, 0); | |
851 | ew32(TCTL, E1000_TCTL_PSP); | |
852 | e1e_flush(); | |
853 | ||
854 | msleep(10); | |
855 | ||
ad68076e BA |
856 | /* |
857 | * Must acquire the MDIO ownership before MAC reset. | |
858 | * Ownership defaults to firmware after a reset. | |
859 | */ | |
8c81c9c3 AD |
860 | switch (hw->mac.type) { |
861 | case e1000_82573: | |
862 | case e1000_82574: | |
863 | case e1000_82583: | |
bc7f75fa AK |
864 | extcnf_ctrl = er32(EXTCNF_CTRL); |
865 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
866 | ||
867 | do { | |
868 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
869 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
870 | ||
871 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
872 | break; | |
873 | ||
874 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
875 | ||
876 | msleep(2); | |
877 | i++; | |
878 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
879 | break; |
880 | default: | |
881 | break; | |
bc7f75fa AK |
882 | } |
883 | ||
884 | ctrl = er32(CTRL); | |
885 | ||
3bb99fe2 | 886 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
887 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
888 | ||
889 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
890 | udelay(10); | |
891 | ctrl_ext = er32(CTRL_EXT); | |
892 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
893 | ew32(CTRL_EXT, ctrl_ext); | |
894 | e1e_flush(); | |
895 | } | |
896 | ||
897 | ret_val = e1000e_get_auto_rd_done(hw); | |
898 | if (ret_val) | |
899 | /* We don't want to continue accessing MAC registers. */ | |
900 | return ret_val; | |
901 | ||
ad68076e BA |
902 | /* |
903 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
904 | * Need to wait for Phy configuration completion before accessing |
905 | * NVM and Phy. | |
906 | */ | |
8c81c9c3 AD |
907 | |
908 | switch (hw->mac.type) { | |
909 | case e1000_82573: | |
910 | case e1000_82574: | |
911 | case e1000_82583: | |
bc7f75fa | 912 | msleep(25); |
8c81c9c3 AD |
913 | break; |
914 | default: | |
915 | break; | |
916 | } | |
bc7f75fa AK |
917 | |
918 | /* Clear any pending interrupt events. */ | |
919 | ew32(IMC, 0xffffffff); | |
920 | icr = er32(ICR); | |
921 | ||
93ca1610 BH |
922 | if (hw->mac.type == e1000_82571 && |
923 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
924 | e1000e_set_laa_state_82571(hw, true); | |
925 | ||
c9523379 | 926 | /* Reinitialize the 82571 serdes link state machine */ |
927 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
928 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
929 | ||
bc7f75fa AK |
930 | return 0; |
931 | } | |
932 | ||
933 | /** | |
934 | * e1000_init_hw_82571 - Initialize hardware | |
935 | * @hw: pointer to the HW structure | |
936 | * | |
937 | * This inits the hardware readying it for operation. | |
938 | **/ | |
939 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
940 | { | |
941 | struct e1000_mac_info *mac = &hw->mac; | |
942 | u32 reg_data; | |
943 | s32 ret_val; | |
944 | u16 i; | |
945 | u16 rar_count = mac->rar_entry_count; | |
946 | ||
947 | e1000_initialize_hw_bits_82571(hw); | |
948 | ||
949 | /* Initialize identification LED */ | |
950 | ret_val = e1000e_id_led_init(hw); | |
951 | if (ret_val) { | |
3bb99fe2 | 952 | e_dbg("Error initializing identification LED\n"); |
bc7f75fa AK |
953 | return ret_val; |
954 | } | |
955 | ||
956 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 957 | e_dbg("Initializing the IEEE VLAN\n"); |
bc7f75fa AK |
958 | e1000e_clear_vfta(hw); |
959 | ||
960 | /* Setup the receive address. */ | |
ad68076e BA |
961 | /* |
962 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
963 | * 82571, we must reserve a RAR for it to work around an issue where |
964 | * resetting one port will reload the MAC on the other port. | |
965 | */ | |
966 | if (e1000e_get_laa_state_82571(hw)) | |
967 | rar_count--; | |
968 | e1000e_init_rx_addrs(hw, rar_count); | |
969 | ||
970 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 971 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
972 | for (i = 0; i < mac->mta_reg_count; i++) |
973 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
974 | ||
975 | /* Setup link and flow control */ | |
976 | ret_val = e1000_setup_link_82571(hw); | |
977 | ||
978 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 979 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
980 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
981 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
982 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 983 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
984 | |
985 | /* ...for both queues. */ | |
8c81c9c3 AD |
986 | switch (mac->type) { |
987 | case e1000_82573: | |
988 | case e1000_82574: | |
989 | case e1000_82583: | |
990 | e1000e_enable_tx_pkt_filtering(hw); | |
991 | reg_data = er32(GCR); | |
992 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
993 | ew32(GCR, reg_data); | |
994 | break; | |
995 | default: | |
e9ec2c0f | 996 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
997 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
998 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
999 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1000 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1001 | break; |
bc7f75fa AK |
1002 | } |
1003 | ||
ad68076e BA |
1004 | /* |
1005 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1006 | * important that we do this after we have tried to establish link |
1007 | * because the symbol error count will increment wildly if there | |
1008 | * is no link. | |
1009 | */ | |
1010 | e1000_clear_hw_cntrs_82571(hw); | |
1011 | ||
1012 | return ret_val; | |
1013 | } | |
1014 | ||
1015 | /** | |
1016 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1017 | * @hw: pointer to the HW structure | |
1018 | * | |
1019 | * Initializes required hardware-dependent bits needed for normal operation. | |
1020 | **/ | |
1021 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1022 | { | |
1023 | u32 reg; | |
1024 | ||
1025 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1026 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1027 | reg |= (1 << 22); |
e9ec2c0f | 1028 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1029 | |
1030 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1031 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1032 | reg |= (1 << 22); |
e9ec2c0f | 1033 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1034 | |
1035 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1036 | reg = er32(TARC(0)); |
bc7f75fa AK |
1037 | reg &= ~(0xF << 27); /* 30:27 */ |
1038 | switch (hw->mac.type) { | |
1039 | case e1000_82571: | |
1040 | case e1000_82572: | |
1041 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1042 | break; | |
1043 | default: | |
1044 | break; | |
1045 | } | |
e9ec2c0f | 1046 | ew32(TARC(0), reg); |
bc7f75fa AK |
1047 | |
1048 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1049 | reg = er32(TARC(1)); |
bc7f75fa AK |
1050 | switch (hw->mac.type) { |
1051 | case e1000_82571: | |
1052 | case e1000_82572: | |
1053 | reg &= ~((1 << 29) | (1 << 30)); | |
1054 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1055 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1056 | reg &= ~(1 << 28); | |
1057 | else | |
1058 | reg |= (1 << 28); | |
e9ec2c0f | 1059 | ew32(TARC(1), reg); |
bc7f75fa AK |
1060 | break; |
1061 | default: | |
1062 | break; | |
1063 | } | |
1064 | ||
1065 | /* Device Control */ | |
8c81c9c3 AD |
1066 | switch (hw->mac.type) { |
1067 | case e1000_82573: | |
1068 | case e1000_82574: | |
1069 | case e1000_82583: | |
bc7f75fa AK |
1070 | reg = er32(CTRL); |
1071 | reg &= ~(1 << 29); | |
1072 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1073 | break; |
1074 | default: | |
1075 | break; | |
bc7f75fa AK |
1076 | } |
1077 | ||
1078 | /* Extended Device Control */ | |
8c81c9c3 AD |
1079 | switch (hw->mac.type) { |
1080 | case e1000_82573: | |
1081 | case e1000_82574: | |
1082 | case e1000_82583: | |
bc7f75fa AK |
1083 | reg = er32(CTRL_EXT); |
1084 | reg &= ~(1 << 23); | |
1085 | reg |= (1 << 22); | |
1086 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1087 | break; |
1088 | default: | |
1089 | break; | |
bc7f75fa | 1090 | } |
4662e82b | 1091 | |
6ea7ae1d AD |
1092 | if (hw->mac.type == e1000_82571) { |
1093 | reg = er32(PBA_ECC); | |
1094 | reg |= E1000_PBA_ECC_CORR_EN; | |
1095 | ew32(PBA_ECC, reg); | |
1096 | } | |
5df3f0ea | 1097 | /* |
1098 | * Workaround for hardware errata. | |
1099 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1100 | */ | |
1101 | ||
1102 | if ((hw->mac.type == e1000_82571) || | |
1103 | (hw->mac.type == e1000_82572)) { | |
1104 | reg = er32(CTRL_EXT); | |
1105 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1106 | ew32(CTRL_EXT, reg); | |
1107 | } | |
1108 | ||
6ea7ae1d | 1109 | |
78272bba | 1110 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1111 | switch (hw->mac.type) { |
1112 | case e1000_82574: | |
1113 | case e1000_82583: | |
4662e82b BA |
1114 | reg = er32(GCR); |
1115 | reg |= (1 << 22); | |
1116 | ew32(GCR, reg); | |
78272bba | 1117 | |
84efb7b9 BA |
1118 | /* |
1119 | * Workaround for hardware errata. | |
1120 | * apply workaround for hardware errata documented in errata | |
1121 | * docs Fixes issue where some error prone or unreliable PCIe | |
1122 | * completions are occurring, particularly with ASPM enabled. | |
1123 | * Without fix, issue can cause tx timeouts. | |
1124 | */ | |
78272bba JB |
1125 | reg = er32(GCR2); |
1126 | reg |= 1; | |
1127 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1128 | break; |
1129 | default: | |
1130 | break; | |
4662e82b BA |
1131 | } |
1132 | ||
1133 | return; | |
bc7f75fa AK |
1134 | } |
1135 | ||
1136 | /** | |
1137 | * e1000e_clear_vfta - Clear VLAN filter table | |
1138 | * @hw: pointer to the HW structure | |
1139 | * | |
1140 | * Clears the register array which contains the VLAN filter table by | |
1141 | * setting all the values to 0. | |
1142 | **/ | |
1143 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
1144 | { | |
1145 | u32 offset; | |
1146 | u32 vfta_value = 0; | |
1147 | u32 vfta_offset = 0; | |
1148 | u32 vfta_bit_in_reg = 0; | |
1149 | ||
8c81c9c3 AD |
1150 | switch (hw->mac.type) { |
1151 | case e1000_82573: | |
1152 | case e1000_82574: | |
1153 | case e1000_82583: | |
bc7f75fa | 1154 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1155 | /* |
1156 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1157 | * a single VLAN ID. The following operations |
1158 | * determine which 32b entry (i.e. offset) into the | |
1159 | * array we want to set the VLAN ID (i.e. bit) of | |
1160 | * the manageability unit. | |
1161 | */ | |
1162 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1163 | E1000_VFTA_ENTRY_SHIFT) & | |
1164 | E1000_VFTA_ENTRY_MASK; | |
1165 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1166 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1167 | } | |
8c81c9c3 AD |
1168 | break; |
1169 | default: | |
1170 | break; | |
bc7f75fa AK |
1171 | } |
1172 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1173 | /* |
1174 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1175 | * manageability VLAN ID, then clear all bits except that of |
1176 | * the manageability unit. | |
1177 | */ | |
1178 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1179 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1180 | e1e_flush(); | |
1181 | } | |
1182 | } | |
1183 | ||
4662e82b BA |
1184 | /** |
1185 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1186 | * @hw: pointer to the HW structure | |
1187 | * | |
1188 | * Reads the NVM Initialization Control Word 2 and returns true | |
1189 | * (>0) if any manageability is enabled, else false (0). | |
1190 | **/ | |
1191 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1192 | { | |
1193 | u16 data; | |
1194 | ||
1195 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1196 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * e1000_led_on_82574 - Turn LED on | |
1201 | * @hw: pointer to the HW structure | |
1202 | * | |
1203 | * Turn LED on. | |
1204 | **/ | |
1205 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1206 | { | |
1207 | u32 ctrl; | |
1208 | u32 i; | |
1209 | ||
1210 | ctrl = hw->mac.ledctl_mode2; | |
1211 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1212 | /* | |
1213 | * If no link, then turn LED on by setting the invert bit | |
1214 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1215 | */ | |
1216 | for (i = 0; i < 4; i++) | |
1217 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1218 | E1000_LEDCTL_MODE_LED_ON) | |
1219 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1220 | } | |
1221 | ew32(LEDCTL, ctrl); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
bc7f75fa | 1226 | /** |
e2de3eb6 | 1227 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
1228 | * @hw: pointer to the HW structure |
1229 | * @mc_addr_list: array of multicast addresses to program | |
1230 | * @mc_addr_count: number of multicast addresses to program | |
1231 | * @rar_used_count: the first RAR register free to program | |
1232 | * @rar_count: total number of supported Receive Address Registers | |
1233 | * | |
1234 | * Updates the Receive Address Registers and Multicast Table Array. | |
1235 | * The caller must have a packed mc_addr_list of multicast addresses. | |
1236 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
1237 | * unless there are workarounds that change this. | |
1238 | **/ | |
e2de3eb6 | 1239 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
1240 | u8 *mc_addr_list, |
1241 | u32 mc_addr_count, | |
1242 | u32 rar_used_count, | |
1243 | u32 rar_count) | |
1244 | { | |
1245 | if (e1000e_get_laa_state_82571(hw)) | |
1246 | rar_count--; | |
1247 | ||
e2de3eb6 JK |
1248 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1249 | rar_used_count, rar_count); | |
bc7f75fa AK |
1250 | } |
1251 | ||
1252 | /** | |
1253 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1254 | * @hw: pointer to the HW structure | |
1255 | * | |
1256 | * Determines which flow control settings to use, then configures flow | |
1257 | * control. Calls the appropriate media-specific link configuration | |
1258 | * function. Assuming the adapter has a valid link partner, a valid link | |
1259 | * should be established. Assumes the hardware has previously been reset | |
1260 | * and the transmitter and receiver are not enabled. | |
1261 | **/ | |
1262 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1263 | { | |
ad68076e BA |
1264 | /* |
1265 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1266 | * the default flow control setting, so we explicitly |
1267 | * set it to full. | |
1268 | */ | |
8c81c9c3 AD |
1269 | switch (hw->mac.type) { |
1270 | case e1000_82573: | |
1271 | case e1000_82574: | |
1272 | case e1000_82583: | |
1273 | if (hw->fc.requested_mode == e1000_fc_default) | |
1274 | hw->fc.requested_mode = e1000_fc_full; | |
1275 | break; | |
1276 | default: | |
1277 | break; | |
1278 | } | |
bc7f75fa AK |
1279 | |
1280 | return e1000e_setup_link(hw); | |
1281 | } | |
1282 | ||
1283 | /** | |
1284 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1285 | * @hw: pointer to the HW structure | |
1286 | * | |
1287 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1288 | * for link, once link is established calls to configure collision distance | |
1289 | * and flow control are called. | |
1290 | **/ | |
1291 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1292 | { | |
1293 | u32 ctrl; | |
1294 | u32 led_ctrl; | |
1295 | s32 ret_val; | |
1296 | ||
1297 | ctrl = er32(CTRL); | |
1298 | ctrl |= E1000_CTRL_SLU; | |
1299 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1300 | ew32(CTRL, ctrl); | |
1301 | ||
1302 | switch (hw->phy.type) { | |
1303 | case e1000_phy_m88: | |
4662e82b | 1304 | case e1000_phy_bm: |
bc7f75fa AK |
1305 | ret_val = e1000e_copper_link_setup_m88(hw); |
1306 | break; | |
1307 | case e1000_phy_igp_2: | |
1308 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1309 | /* Setup activity LED */ | |
1310 | led_ctrl = er32(LEDCTL); | |
1311 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1312 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1313 | ew32(LEDCTL, led_ctrl); | |
1314 | break; | |
1315 | default: | |
1316 | return -E1000_ERR_PHY; | |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | if (ret_val) | |
1321 | return ret_val; | |
1322 | ||
1323 | ret_val = e1000e_setup_copper_link(hw); | |
1324 | ||
1325 | return ret_val; | |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1330 | * @hw: pointer to the HW structure | |
1331 | * | |
1332 | * Configures collision distance and flow control for fiber and serdes links. | |
1333 | * Upon successful setup, poll for link. | |
1334 | **/ | |
1335 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1336 | { | |
1337 | switch (hw->mac.type) { | |
1338 | case e1000_82571: | |
1339 | case e1000_82572: | |
ad68076e BA |
1340 | /* |
1341 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1342 | * of reset to take the adapter out of that mode. So we |
1343 | * have to explicitly take the adapter out of loopback | |
489815ce | 1344 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1345 | * if another tool failed to take it out of loopback mode. |
1346 | */ | |
ad68076e | 1347 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1348 | break; |
1349 | default: | |
1350 | break; | |
1351 | } | |
1352 | ||
1353 | return e1000e_setup_fiber_serdes_link(hw); | |
1354 | } | |
1355 | ||
c9523379 | 1356 | /** |
1357 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1358 | * @hw: pointer to the HW structure | |
1359 | * | |
1360 | * Checks for link up on the hardware. If link is not up and we have | |
1361 | * a signal, then we need to force link up. | |
1362 | **/ | |
f6370117 | 1363 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1364 | { |
1365 | struct e1000_mac_info *mac = &hw->mac; | |
1366 | u32 rxcw; | |
1367 | u32 ctrl; | |
1368 | u32 status; | |
1369 | s32 ret_val = 0; | |
1370 | ||
1371 | ctrl = er32(CTRL); | |
1372 | status = er32(STATUS); | |
1373 | rxcw = er32(RXCW); | |
1374 | ||
1375 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1376 | ||
1377 | /* Receiver is synchronized with no invalid bits. */ | |
1378 | switch (mac->serdes_link_state) { | |
1379 | case e1000_serdes_link_autoneg_complete: | |
1380 | if (!(status & E1000_STATUS_LU)) { | |
1381 | /* | |
1382 | * We have lost link, retry autoneg before | |
1383 | * reporting link failure | |
1384 | */ | |
1385 | mac->serdes_link_state = | |
1386 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1387 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1388 | } |
1389 | break; | |
1390 | ||
1391 | case e1000_serdes_link_forced_up: | |
1392 | /* | |
1393 | * If we are receiving /C/ ordered sets, re-enable | |
1394 | * auto-negotiation in the TXCW register and disable | |
1395 | * forced link in the Device Control register in an | |
1396 | * attempt to auto-negotiate with our link partner. | |
1397 | */ | |
1398 | if (rxcw & E1000_RXCW_C) { | |
1399 | /* Enable autoneg, and unforce link up */ | |
1400 | ew32(TXCW, mac->txcw); | |
1401 | ew32(CTRL, | |
1402 | (ctrl & ~E1000_CTRL_SLU)); | |
1403 | mac->serdes_link_state = | |
1404 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1405 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1406 | } |
1407 | break; | |
1408 | ||
1409 | case e1000_serdes_link_autoneg_progress: | |
1410 | /* | |
1411 | * If the LU bit is set in the STATUS register, | |
1412 | * autoneg has completed sucessfully. If not, | |
1413 | * try foring the link because the far end may be | |
1414 | * available but not capable of autonegotiation. | |
1415 | */ | |
1416 | if (status & E1000_STATUS_LU) { | |
1417 | mac->serdes_link_state = | |
1418 | e1000_serdes_link_autoneg_complete; | |
3bb99fe2 | 1419 | e_dbg("AN_PROG -> AN_UP\n"); |
c9523379 | 1420 | } else { |
1421 | /* | |
1422 | * Disable autoneg, force link up and | |
1423 | * full duplex, and change state to forced | |
1424 | */ | |
1425 | ew32(TXCW, | |
1426 | (mac->txcw & ~E1000_TXCW_ANE)); | |
1427 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
1428 | ew32(CTRL, ctrl); | |
1429 | ||
1430 | /* Configure Flow Control after link up. */ | |
1431 | ret_val = | |
1432 | e1000e_config_fc_after_link_up(hw); | |
1433 | if (ret_val) { | |
3bb99fe2 | 1434 | e_dbg("Error config flow control\n"); |
c9523379 | 1435 | break; |
1436 | } | |
1437 | mac->serdes_link_state = | |
1438 | e1000_serdes_link_forced_up; | |
3bb99fe2 | 1439 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1440 | } |
1441 | mac->serdes_has_link = true; | |
1442 | break; | |
1443 | ||
1444 | case e1000_serdes_link_down: | |
1445 | default: | |
1446 | /* The link was down but the receiver has now gained | |
1447 | * valid sync, so lets see if we can bring the link | |
1448 | * up. */ | |
1449 | ew32(TXCW, mac->txcw); | |
1450 | ew32(CTRL, | |
1451 | (ctrl & ~E1000_CTRL_SLU)); | |
1452 | mac->serdes_link_state = | |
1453 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1454 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1455 | break; |
1456 | } | |
1457 | } else { | |
1458 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1459 | mac->serdes_has_link = false; | |
1460 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1461 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1462 | } else { |
1463 | /* | |
1464 | * We have sync, and can tolerate one | |
1465 | * invalid (IV) codeword before declaring | |
1466 | * link down, so reread to look again | |
1467 | */ | |
1468 | udelay(10); | |
1469 | rxcw = er32(RXCW); | |
1470 | if (rxcw & E1000_RXCW_IV) { | |
1471 | mac->serdes_link_state = e1000_serdes_link_down; | |
1472 | mac->serdes_has_link = false; | |
3bb99fe2 | 1473 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1474 | } |
1475 | } | |
1476 | } | |
1477 | ||
1478 | return ret_val; | |
1479 | } | |
1480 | ||
bc7f75fa AK |
1481 | /** |
1482 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1483 | * @hw: pointer to the HW structure | |
1484 | * @data: pointer to the NVM (EEPROM) | |
1485 | * | |
1486 | * Read the EEPROM for the current default LED configuration. If the | |
1487 | * LED configuration is not valid, set to a valid LED configuration. | |
1488 | **/ | |
1489 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1490 | { | |
1491 | s32 ret_val; | |
1492 | ||
1493 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1494 | if (ret_val) { | |
3bb99fe2 | 1495 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1496 | return ret_val; |
1497 | } | |
1498 | ||
8c81c9c3 AD |
1499 | switch (hw->mac.type) { |
1500 | case e1000_82573: | |
1501 | case e1000_82574: | |
1502 | case e1000_82583: | |
1503 | if (*data == ID_LED_RESERVED_F746) | |
1504 | *data = ID_LED_DEFAULT_82573; | |
1505 | break; | |
1506 | default: | |
1507 | if (*data == ID_LED_RESERVED_0000 || | |
1508 | *data == ID_LED_RESERVED_FFFF) | |
1509 | *data = ID_LED_DEFAULT; | |
1510 | break; | |
1511 | } | |
bc7f75fa AK |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /** | |
1517 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1518 | * @hw: pointer to the HW structure | |
1519 | * | |
489815ce | 1520 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1521 | **/ |
1522 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1523 | { | |
1524 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1525 | return false; |
bc7f75fa AK |
1526 | |
1527 | return hw->dev_spec.e82571.laa_is_present; | |
1528 | } | |
1529 | ||
1530 | /** | |
1531 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1532 | * @hw: pointer to the HW structure | |
1533 | * @state: enable/disable locally administered address | |
1534 | * | |
489815ce | 1535 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1536 | **/ |
1537 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1538 | { | |
1539 | if (hw->mac.type != e1000_82571) | |
1540 | return; | |
1541 | ||
1542 | hw->dev_spec.e82571.laa_is_present = state; | |
1543 | ||
1544 | /* If workaround is activated... */ | |
1545 | if (state) | |
ad68076e BA |
1546 | /* |
1547 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1548 | * between the time RAR[0] gets clobbered and the time it |
1549 | * gets fixed, the actual LAA is in one of the RARs and no | |
1550 | * incoming packets directed to this port are dropped. | |
1551 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1552 | */ | |
1553 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1554 | } | |
1555 | ||
1556 | /** | |
1557 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1558 | * @hw: pointer to the HW structure | |
1559 | * | |
1560 | * Verifies that the EEPROM has completed the update. After updating the | |
1561 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1562 | * the checksum fix is not implemented, we need to set the bit and update | |
1563 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1564 | * we need to return bad checksum. | |
1565 | **/ | |
1566 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1567 | { | |
1568 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1569 | s32 ret_val; | |
1570 | u16 data; | |
1571 | ||
1572 | if (nvm->type != e1000_nvm_flash_hw) | |
1573 | return 0; | |
1574 | ||
ad68076e BA |
1575 | /* |
1576 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1577 | * 10h-12h. Checksum may need to be fixed. |
1578 | */ | |
1579 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1580 | if (ret_val) | |
1581 | return ret_val; | |
1582 | ||
1583 | if (!(data & 0x10)) { | |
ad68076e BA |
1584 | /* |
1585 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1586 | * when the checksum has already been fixed. If |
1587 | * the checksum is still wrong and this bit is a | |
1588 | * 1, we need to return bad checksum. Otherwise, | |
1589 | * we need to set this bit to a 1 and update the | |
1590 | * checksum. | |
1591 | */ | |
1592 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1593 | if (ret_val) | |
1594 | return ret_val; | |
1595 | ||
1596 | if (!(data & 0x8000)) { | |
1597 | data |= 0x8000; | |
1598 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1599 | if (ret_val) | |
1600 | return ret_val; | |
1601 | ret_val = e1000e_update_nvm_checksum(hw); | |
1602 | } | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | /** | |
1609 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1610 | * @hw: pointer to the HW structure | |
1611 | * | |
1612 | * Clears the hardware counters by reading the counter registers. | |
1613 | **/ | |
1614 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1615 | { | |
1616 | u32 temp; | |
1617 | ||
1618 | e1000e_clear_hw_cntrs_base(hw); | |
1619 | ||
1620 | temp = er32(PRC64); | |
1621 | temp = er32(PRC127); | |
1622 | temp = er32(PRC255); | |
1623 | temp = er32(PRC511); | |
1624 | temp = er32(PRC1023); | |
1625 | temp = er32(PRC1522); | |
1626 | temp = er32(PTC64); | |
1627 | temp = er32(PTC127); | |
1628 | temp = er32(PTC255); | |
1629 | temp = er32(PTC511); | |
1630 | temp = er32(PTC1023); | |
1631 | temp = er32(PTC1522); | |
1632 | ||
1633 | temp = er32(ALGNERRC); | |
1634 | temp = er32(RXERRC); | |
1635 | temp = er32(TNCRS); | |
1636 | temp = er32(CEXTERR); | |
1637 | temp = er32(TSCTC); | |
1638 | temp = er32(TSCTFC); | |
1639 | ||
1640 | temp = er32(MGTPRC); | |
1641 | temp = er32(MGTPDC); | |
1642 | temp = er32(MGTPTC); | |
1643 | ||
1644 | temp = er32(IAC); | |
1645 | temp = er32(ICRXOC); | |
1646 | ||
1647 | temp = er32(ICRXPTC); | |
1648 | temp = er32(ICRXATC); | |
1649 | temp = er32(ICTXPTC); | |
1650 | temp = er32(ICTXATC); | |
1651 | temp = er32(ICTXQEC); | |
1652 | temp = er32(ICTXQMTC); | |
1653 | temp = er32(ICRXDMTC); | |
1654 | } | |
1655 | ||
1656 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1657 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1658 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1659 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1660 | .cleanup_led = e1000e_cleanup_led_generic, |
1661 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1662 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1663 | /* .get_link_up_info: media type dependent */ | |
4662e82b | 1664 | /* .led_on: mac type dependent */ |
bc7f75fa | 1665 | .led_off = e1000e_led_off_generic, |
e2de3eb6 | 1666 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
bc7f75fa AK |
1667 | .reset_hw = e1000_reset_hw_82571, |
1668 | .init_hw = e1000_init_hw_82571, | |
1669 | .setup_link = e1000_setup_link_82571, | |
1670 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1671 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1672 | }; |
1673 | ||
1674 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1675 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1676 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1677 | .commit = NULL, |
bc7f75fa AK |
1678 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1679 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1680 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1681 | .get_info = e1000e_get_phy_info_igp, |
1682 | .read_reg = e1000e_read_phy_reg_igp, | |
1683 | .release = e1000_put_hw_semaphore_82571, | |
1684 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1685 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1686 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1687 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1688 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1689 | }; |
1690 | ||
1691 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1692 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1693 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1694 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1695 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1696 | .get_cfg_done = e1000e_get_cfg_done, | |
1697 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1698 | .get_info = e1000e_get_phy_info_m88, |
1699 | .read_reg = e1000e_read_phy_reg_m88, | |
1700 | .release = e1000_put_hw_semaphore_82571, | |
1701 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1702 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1703 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1704 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1705 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1706 | }; |
1707 | ||
4662e82b | 1708 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1709 | .acquire = e1000_get_hw_semaphore_82571, |
4662e82b | 1710 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1711 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1712 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1713 | .get_cfg_done = e1000e_get_cfg_done, | |
1714 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1715 | .get_info = e1000e_get_phy_info_m88, |
1716 | .read_reg = e1000e_read_phy_reg_bm2, | |
1717 | .release = e1000_put_hw_semaphore_82571, | |
1718 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1719 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1720 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1721 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1722 | .cfg_on_link_up = NULL, |
4662e82b BA |
1723 | }; |
1724 | ||
bc7f75fa | 1725 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1726 | .acquire = e1000_acquire_nvm_82571, |
1727 | .read = e1000e_read_nvm_eerd, | |
1728 | .release = e1000_release_nvm_82571, | |
1729 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1730 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1731 | .validate = e1000_validate_nvm_checksum_82571, |
1732 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1733 | }; |
1734 | ||
1735 | struct e1000_info e1000_82571_info = { | |
1736 | .mac = e1000_82571, | |
1737 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1738 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1739 | | FLAG_HAS_WOL |
1740 | | FLAG_APME_IN_CTRL3 | |
1741 | | FLAG_RX_CSUM_ENABLED | |
1742 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1743 | | FLAG_HAS_SMART_POWER_DOWN |
1744 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1745 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1746 | | FLAG_APME_CHECK_PORT_B, | |
1747 | .pba = 38, | |
2adc55c9 | 1748 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1749 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1750 | .mac_ops = &e82571_mac_ops, |
1751 | .phy_ops = &e82_phy_ops_igp, | |
1752 | .nvm_ops = &e82571_nvm_ops, | |
1753 | }; | |
1754 | ||
1755 | struct e1000_info e1000_82572_info = { | |
1756 | .mac = e1000_82572, | |
1757 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1758 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1759 | | FLAG_HAS_WOL |
1760 | | FLAG_APME_IN_CTRL3 | |
1761 | | FLAG_RX_CSUM_ENABLED | |
1762 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1763 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1764 | .pba = 38, | |
2adc55c9 | 1765 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1766 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1767 | .mac_ops = &e82571_mac_ops, |
1768 | .phy_ops = &e82_phy_ops_igp, | |
1769 | .nvm_ops = &e82571_nvm_ops, | |
1770 | }; | |
1771 | ||
1772 | struct e1000_info e1000_82573_info = { | |
1773 | .mac = e1000_82573, | |
1774 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1775 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1776 | | FLAG_HAS_WOL |
1777 | | FLAG_APME_IN_CTRL3 | |
1778 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1779 | | FLAG_HAS_SMART_POWER_DOWN |
1780 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1781 | | FLAG_HAS_ERT |
1782 | | FLAG_HAS_SWSM_ON_LOAD, | |
1783 | .pba = 20, | |
2adc55c9 | 1784 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1785 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1786 | .mac_ops = &e82571_mac_ops, |
1787 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1788 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1789 | }; |
1790 | ||
4662e82b BA |
1791 | struct e1000_info e1000_82574_info = { |
1792 | .mac = e1000_82574, | |
1793 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1794 | | FLAG_HAS_MSIX | |
1795 | | FLAG_HAS_JUMBO_FRAMES | |
1796 | | FLAG_HAS_WOL | |
1797 | | FLAG_APME_IN_CTRL3 | |
1798 | | FLAG_RX_CSUM_ENABLED | |
1799 | | FLAG_HAS_SMART_POWER_DOWN | |
1800 | | FLAG_HAS_AMT | |
1801 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1802 | .pba = 20, | |
a825e00c | 1803 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
1804 | .get_variants = e1000_get_variants_82571, |
1805 | .mac_ops = &e82571_mac_ops, | |
1806 | .phy_ops = &e82_phy_ops_bm, | |
1807 | .nvm_ops = &e82571_nvm_ops, | |
1808 | }; | |
1809 | ||
8c81c9c3 AD |
1810 | struct e1000_info e1000_82583_info = { |
1811 | .mac = e1000_82583, | |
1812 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1813 | | FLAG_HAS_WOL | |
1814 | | FLAG_APME_IN_CTRL3 | |
1815 | | FLAG_RX_CSUM_ENABLED | |
1816 | | FLAG_HAS_SMART_POWER_DOWN | |
1817 | | FLAG_HAS_AMT | |
1818 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1819 | .pba = 20, | |
a825e00c | 1820 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
1821 | .get_variants = e1000_get_variants_82571, |
1822 | .mac_ops = &e82571_mac_ops, | |
1823 | .phy_ops = &e82_phy_ops_bm, | |
1824 | .nvm_ops = &e82571_nvm_ops, | |
1825 | }; | |
1826 |