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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
451152d9 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
ff10e13c CW |
55 | #define E1000_BASE1000T_STATUS 10 |
56 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF | |
57 | #define E1000_RECEIVE_ERROR_COUNTER 21 | |
58 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF | |
bc7f75fa | 59 | |
4662e82b BA |
60 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
61 | ||
bc7f75fa AK |
62 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
63 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
64 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 65 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
66 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
67 | u16 words, u16 *data); | |
68 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
69 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
70 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
71 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 72 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
73 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
74 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 75 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 76 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
bc7f75fa AK |
77 | |
78 | /** | |
79 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
80 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
81 | **/ |
82 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
83 | { | |
84 | struct e1000_phy_info *phy = &hw->phy; | |
85 | s32 ret_val; | |
86 | ||
318a94d6 | 87 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
88 | phy->type = e1000_phy_none; |
89 | return 0; | |
90 | } | |
91 | ||
92 | phy->addr = 1; | |
93 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
94 | phy->reset_delay_us = 100; | |
95 | ||
17f208de BA |
96 | phy->ops.power_up = e1000_power_up_phy_copper; |
97 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
98 | ||
bc7f75fa AK |
99 | switch (hw->mac.type) { |
100 | case e1000_82571: | |
101 | case e1000_82572: | |
102 | phy->type = e1000_phy_igp_2; | |
103 | break; | |
104 | case e1000_82573: | |
105 | phy->type = e1000_phy_m88; | |
106 | break; | |
4662e82b | 107 | case e1000_82574: |
8c81c9c3 | 108 | case e1000_82583: |
4662e82b BA |
109 | phy->type = e1000_phy_bm; |
110 | break; | |
bc7f75fa AK |
111 | default: |
112 | return -E1000_ERR_PHY; | |
113 | break; | |
114 | } | |
115 | ||
116 | /* This can only be done after all function pointers are setup. */ | |
117 | ret_val = e1000_get_phy_id_82571(hw); | |
118 | ||
119 | /* Verify phy id */ | |
120 | switch (hw->mac.type) { | |
121 | case e1000_82571: | |
122 | case e1000_82572: | |
123 | if (phy->id != IGP01E1000_I_PHY_ID) | |
124 | return -E1000_ERR_PHY; | |
125 | break; | |
126 | case e1000_82573: | |
127 | if (phy->id != M88E1111_I_PHY_ID) | |
128 | return -E1000_ERR_PHY; | |
129 | break; | |
4662e82b | 130 | case e1000_82574: |
8c81c9c3 | 131 | case e1000_82583: |
4662e82b BA |
132 | if (phy->id != BME1000_E_PHY_ID_R2) |
133 | return -E1000_ERR_PHY; | |
134 | break; | |
bc7f75fa AK |
135 | default: |
136 | return -E1000_ERR_PHY; | |
137 | break; | |
138 | } | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | /** | |
144 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
145 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
146 | **/ |
147 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
148 | { | |
149 | struct e1000_nvm_info *nvm = &hw->nvm; | |
150 | u32 eecd = er32(EECD); | |
151 | u16 size; | |
152 | ||
153 | nvm->opcode_bits = 8; | |
154 | nvm->delay_usec = 1; | |
155 | switch (nvm->override) { | |
156 | case e1000_nvm_override_spi_large: | |
157 | nvm->page_size = 32; | |
158 | nvm->address_bits = 16; | |
159 | break; | |
160 | case e1000_nvm_override_spi_small: | |
161 | nvm->page_size = 8; | |
162 | nvm->address_bits = 8; | |
163 | break; | |
164 | default: | |
165 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
166 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
167 | break; | |
168 | } | |
169 | ||
170 | switch (hw->mac.type) { | |
171 | case e1000_82573: | |
4662e82b | 172 | case e1000_82574: |
8c81c9c3 | 173 | case e1000_82583: |
bc7f75fa AK |
174 | if (((eecd >> 15) & 0x3) == 0x3) { |
175 | nvm->type = e1000_nvm_flash_hw; | |
176 | nvm->word_size = 2048; | |
ad68076e BA |
177 | /* |
178 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
179 | * to Flash update issue. |
180 | */ | |
181 | eecd &= ~E1000_EECD_AUPDEN; | |
182 | ew32(EECD, eecd); | |
183 | break; | |
184 | } | |
185 | /* Fall Through */ | |
186 | default: | |
ad68076e | 187 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
188 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
189 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
190 | /* |
191 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
192 | * for setting word_size. |
193 | */ | |
194 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
195 | |
196 | /* EEPROM access above 16k is unsupported */ | |
197 | if (size > 14) | |
198 | size = 14; | |
bc7f75fa AK |
199 | nvm->word_size = 1 << size; |
200 | break; | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | /** | |
207 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
208 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
209 | **/ |
210 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
211 | { | |
212 | struct e1000_hw *hw = &adapter->hw; | |
213 | struct e1000_mac_info *mac = &hw->mac; | |
214 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
215 | u32 swsm = 0; |
216 | u32 swsm2 = 0; | |
217 | bool force_clear_smbi = false; | |
bc7f75fa AK |
218 | |
219 | /* Set media type */ | |
220 | switch (adapter->pdev->device) { | |
221 | case E1000_DEV_ID_82571EB_FIBER: | |
222 | case E1000_DEV_ID_82572EI_FIBER: | |
223 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 224 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
225 | break; |
226 | case E1000_DEV_ID_82571EB_SERDES: | |
227 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
228 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
229 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 230 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
231 | break; |
232 | default: | |
318a94d6 | 233 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
234 | break; |
235 | } | |
236 | ||
237 | /* Set mta register count */ | |
238 | mac->mta_reg_count = 128; | |
239 | /* Set rar entry count */ | |
240 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
f464ba87 BA |
241 | /* Adaptive IFS supported */ |
242 | mac->adaptive_ifs = true; | |
bc7f75fa AK |
243 | |
244 | /* check for link */ | |
318a94d6 | 245 | switch (hw->phy.media_type) { |
bc7f75fa AK |
246 | case e1000_media_type_copper: |
247 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
248 | func->check_for_link = e1000e_check_for_copper_link; | |
249 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
250 | break; | |
251 | case e1000_media_type_fiber: | |
ad68076e BA |
252 | func->setup_physical_interface = |
253 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 254 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
255 | func->get_link_up_info = |
256 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
257 | break; |
258 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
259 | func->setup_physical_interface = |
260 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 261 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
262 | func->get_link_up_info = |
263 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
264 | break; |
265 | default: | |
266 | return -E1000_ERR_CONFIG; | |
267 | break; | |
268 | } | |
269 | ||
4662e82b | 270 | switch (hw->mac.type) { |
f4d2dd4c BA |
271 | case e1000_82573: |
272 | func->set_lan_id = e1000_set_lan_id_single_port; | |
273 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
274 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
275 | |
276 | /* FWSM register */ | |
277 | mac->has_fwsm = true; | |
278 | /* | |
279 | * ARC supported; valid only if manageability features are | |
280 | * enabled. | |
281 | */ | |
282 | mac->arc_subsystem_valid = | |
283 | (er32(FWSM) & E1000_FWSM_MODE_MASK) | |
284 | ? true : false; | |
f4d2dd4c | 285 | break; |
4662e82b | 286 | case e1000_82574: |
8c81c9c3 | 287 | case e1000_82583: |
f4d2dd4c | 288 | func->set_lan_id = e1000_set_lan_id_single_port; |
4662e82b BA |
289 | func->check_mng_mode = e1000_check_mng_mode_82574; |
290 | func->led_on = e1000_led_on_82574; | |
291 | break; | |
292 | default: | |
293 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
294 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
295 | |
296 | /* FWSM register */ | |
297 | mac->has_fwsm = true; | |
4662e82b BA |
298 | break; |
299 | } | |
300 | ||
23a2d1b2 DG |
301 | /* |
302 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
303 | * first NVM or PHY acess. This should be done for single-port | |
304 | * devices, and for one port only on dual-port devices so that | |
305 | * for those devices we can still use the SMBI lock to synchronize | |
306 | * inter-port accesses to the PHY & NVM. | |
307 | */ | |
308 | switch (hw->mac.type) { | |
309 | case e1000_82571: | |
310 | case e1000_82572: | |
311 | swsm2 = er32(SWSM2); | |
312 | ||
313 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
314 | /* Only do this for the first interface on this card */ | |
315 | ew32(SWSM2, | |
316 | swsm2 | E1000_SWSM2_LOCK); | |
317 | force_clear_smbi = true; | |
318 | } else | |
319 | force_clear_smbi = false; | |
320 | break; | |
321 | default: | |
322 | force_clear_smbi = true; | |
323 | break; | |
324 | } | |
325 | ||
326 | if (force_clear_smbi) { | |
327 | /* Make sure SWSM.SMBI is clear */ | |
328 | swsm = er32(SWSM); | |
329 | if (swsm & E1000_SWSM_SMBI) { | |
330 | /* This bit should not be set on a first interface, and | |
331 | * indicates that the bootagent or EFI code has | |
332 | * improperly left this bit enabled | |
333 | */ | |
3bb99fe2 | 334 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
335 | } |
336 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
337 | } | |
338 | ||
339 | /* | |
2c73e1fe | 340 | * Initialize device specific counter of SMBI acquisition |
23a2d1b2 DG |
341 | * timeouts. |
342 | */ | |
343 | hw->dev_spec.e82571.smb_counter = 0; | |
344 | ||
bc7f75fa AK |
345 | return 0; |
346 | } | |
347 | ||
69e3fd8c | 348 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
349 | { |
350 | struct e1000_hw *hw = &adapter->hw; | |
351 | static int global_quad_port_a; /* global port a indication */ | |
352 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
353 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
354 | s32 rc; | |
355 | ||
356 | rc = e1000_init_mac_params_82571(adapter); | |
357 | if (rc) | |
358 | return rc; | |
359 | ||
360 | rc = e1000_init_nvm_params_82571(hw); | |
361 | if (rc) | |
362 | return rc; | |
363 | ||
364 | rc = e1000_init_phy_params_82571(hw); | |
365 | if (rc) | |
366 | return rc; | |
367 | ||
368 | /* tag quad port adapters first, it's used below */ | |
369 | switch (pdev->device) { | |
370 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
371 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
372 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 373 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
374 | adapter->flags |= FLAG_IS_QUAD_PORT; |
375 | /* mark the first port */ | |
376 | if (global_quad_port_a == 0) | |
377 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
378 | /* Reset for multiple quad port adapters */ | |
379 | global_quad_port_a++; | |
380 | if (global_quad_port_a == 4) | |
381 | global_quad_port_a = 0; | |
382 | break; | |
383 | default: | |
384 | break; | |
385 | } | |
386 | ||
387 | switch (adapter->hw.mac.type) { | |
388 | case e1000_82571: | |
389 | /* these dual ports don't have WoL on port B at all */ | |
390 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
391 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
392 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
393 | (is_port_b)) | |
394 | adapter->flags &= ~FLAG_HAS_WOL; | |
395 | /* quad ports only support WoL on port A */ | |
396 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 397 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 398 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
399 | /* Does not support WoL on any port */ |
400 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
401 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa | 402 | break; |
bc7f75fa | 403 | case e1000_82573: |
6f461f6c BA |
404 | case e1000_82574: |
405 | case e1000_82583: | |
406 | /* Disable ASPM L0s due to hardware errata */ | |
407 | e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); | |
408 | ||
bc7f75fa | 409 | if (pdev->device == E1000_DEV_ID_82573L) { |
6f461f6c BA |
410 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
411 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
bc7f75fa AK |
412 | } |
413 | break; | |
414 | default: | |
415 | break; | |
416 | } | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | /** | |
422 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
423 | * @hw: pointer to the HW structure | |
424 | * | |
425 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
426 | * revision in the hardware structure. | |
427 | **/ | |
428 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
429 | { | |
430 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
431 | s32 ret_val; |
432 | u16 phy_id = 0; | |
bc7f75fa AK |
433 | |
434 | switch (hw->mac.type) { | |
435 | case e1000_82571: | |
436 | case e1000_82572: | |
ad68076e BA |
437 | /* |
438 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
439 | * In this case, we cannot access the PHY until the |
440 | * configuration is done. So we explicitly set the | |
ad68076e BA |
441 | * PHY ID. |
442 | */ | |
bc7f75fa AK |
443 | phy->id = IGP01E1000_I_PHY_ID; |
444 | break; | |
445 | case e1000_82573: | |
446 | return e1000e_get_phy_id(hw); | |
447 | break; | |
4662e82b | 448 | case e1000_82574: |
8c81c9c3 | 449 | case e1000_82583: |
4662e82b BA |
450 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
451 | if (ret_val) | |
452 | return ret_val; | |
453 | ||
454 | phy->id = (u32)(phy_id << 16); | |
455 | udelay(20); | |
456 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
457 | if (ret_val) | |
458 | return ret_val; | |
459 | ||
460 | phy->id |= (u32)(phy_id); | |
461 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
462 | break; | |
bc7f75fa AK |
463 | default: |
464 | return -E1000_ERR_PHY; | |
465 | break; | |
466 | } | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | /** | |
472 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
473 | * @hw: pointer to the HW structure | |
474 | * | |
475 | * Acquire the HW semaphore to access the PHY or NVM | |
476 | **/ | |
477 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
478 | { | |
479 | u32 swsm; | |
23a2d1b2 DG |
480 | s32 sw_timeout = hw->nvm.word_size + 1; |
481 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
482 | s32 i = 0; |
483 | ||
23a2d1b2 DG |
484 | /* |
485 | * If we have timedout 3 times on trying to acquire | |
486 | * the inter-port SMBI semaphore, there is old code | |
487 | * operating on the other port, and it is not | |
488 | * releasing SMBI. Modify the number of times that | |
489 | * we try for the semaphore to interwork with this | |
490 | * older code. | |
491 | */ | |
492 | if (hw->dev_spec.e82571.smb_counter > 2) | |
493 | sw_timeout = 1; | |
494 | ||
495 | /* Get the SW semaphore */ | |
496 | while (i < sw_timeout) { | |
497 | swsm = er32(SWSM); | |
498 | if (!(swsm & E1000_SWSM_SMBI)) | |
499 | break; | |
500 | ||
501 | udelay(50); | |
502 | i++; | |
503 | } | |
504 | ||
505 | if (i == sw_timeout) { | |
3bb99fe2 | 506 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
507 | hw->dev_spec.e82571.smb_counter++; |
508 | } | |
bc7f75fa | 509 | /* Get the FW semaphore. */ |
23a2d1b2 | 510 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
511 | swsm = er32(SWSM); |
512 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
513 | ||
514 | /* Semaphore acquired if bit latched */ | |
515 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
516 | break; | |
517 | ||
518 | udelay(50); | |
519 | } | |
520 | ||
23a2d1b2 | 521 | if (i == fw_timeout) { |
bc7f75fa | 522 | /* Release semaphores */ |
23a2d1b2 | 523 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 524 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
525 | return -E1000_ERR_NVM; |
526 | } | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | /** | |
532 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
533 | * @hw: pointer to the HW structure | |
534 | * | |
535 | * Release hardware semaphore used to access the PHY or NVM | |
536 | **/ | |
537 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
538 | { | |
539 | u32 swsm; | |
540 | ||
541 | swsm = er32(SWSM); | |
23a2d1b2 | 542 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
543 | ew32(SWSM, swsm); |
544 | } | |
545 | ||
546 | /** | |
547 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
548 | * @hw: pointer to the HW structure | |
549 | * | |
550 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
551 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
552 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
553 | * hardware semaphore. | |
554 | **/ | |
555 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
556 | { | |
557 | s32 ret_val; | |
558 | ||
559 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
560 | if (ret_val) | |
561 | return ret_val; | |
562 | ||
8c81c9c3 AD |
563 | switch (hw->mac.type) { |
564 | case e1000_82573: | |
565 | case e1000_82574: | |
566 | case e1000_82583: | |
567 | break; | |
568 | default: | |
bc7f75fa | 569 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
570 | break; |
571 | } | |
bc7f75fa AK |
572 | |
573 | if (ret_val) | |
574 | e1000_put_hw_semaphore_82571(hw); | |
575 | ||
576 | return ret_val; | |
577 | } | |
578 | ||
579 | /** | |
580 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
581 | * @hw: pointer to the HW structure | |
582 | * | |
583 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
584 | **/ | |
585 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
586 | { | |
587 | e1000e_release_nvm(hw); | |
588 | e1000_put_hw_semaphore_82571(hw); | |
589 | } | |
590 | ||
591 | /** | |
592 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
593 | * @hw: pointer to the HW structure | |
594 | * @offset: offset within the EEPROM to be written to | |
595 | * @words: number of words to write | |
596 | * @data: 16 bit word(s) to be written to the EEPROM | |
597 | * | |
598 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
599 | * | |
600 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 601 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
602 | **/ |
603 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
604 | u16 *data) | |
605 | { | |
606 | s32 ret_val; | |
607 | ||
608 | switch (hw->mac.type) { | |
609 | case e1000_82573: | |
4662e82b | 610 | case e1000_82574: |
8c81c9c3 | 611 | case e1000_82583: |
bc7f75fa AK |
612 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
613 | break; | |
614 | case e1000_82571: | |
615 | case e1000_82572: | |
616 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
617 | break; | |
618 | default: | |
619 | ret_val = -E1000_ERR_NVM; | |
620 | break; | |
621 | } | |
622 | ||
623 | return ret_val; | |
624 | } | |
625 | ||
626 | /** | |
627 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
628 | * @hw: pointer to the HW structure | |
629 | * | |
630 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
631 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
632 | * value to the EEPROM. | |
633 | **/ | |
634 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
635 | { | |
636 | u32 eecd; | |
637 | s32 ret_val; | |
638 | u16 i; | |
639 | ||
640 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
641 | if (ret_val) | |
642 | return ret_val; | |
643 | ||
ad68076e BA |
644 | /* |
645 | * If our nvm is an EEPROM, then we're done | |
646 | * otherwise, commit the checksum to the flash NVM. | |
647 | */ | |
bc7f75fa AK |
648 | if (hw->nvm.type != e1000_nvm_flash_hw) |
649 | return ret_val; | |
650 | ||
651 | /* Check for pending operations. */ | |
652 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
653 | msleep(1); | |
654 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
655 | break; | |
656 | } | |
657 | ||
658 | if (i == E1000_FLASH_UPDATES) | |
659 | return -E1000_ERR_NVM; | |
660 | ||
661 | /* Reset the firmware if using STM opcode. */ | |
662 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
663 | /* |
664 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
665 | * in two write cycles. |
666 | */ | |
667 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
668 | e1e_flush(); | |
669 | ew32(HICR, E1000_HICR_FW_RESET); | |
670 | } | |
671 | ||
672 | /* Commit the write to flash */ | |
673 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
674 | ew32(EECD, eecd); | |
675 | ||
676 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
677 | msleep(1); | |
678 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
679 | break; | |
680 | } | |
681 | ||
682 | if (i == E1000_FLASH_UPDATES) | |
683 | return -E1000_ERR_NVM; | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
688 | /** | |
689 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
690 | * @hw: pointer to the HW structure | |
691 | * | |
692 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
693 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
694 | **/ | |
695 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
696 | { | |
697 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
698 | e1000_fix_nvm_checksum_82571(hw); | |
699 | ||
700 | return e1000e_validate_nvm_checksum_generic(hw); | |
701 | } | |
702 | ||
703 | /** | |
704 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
705 | * @hw: pointer to the HW structure | |
706 | * @offset: offset within the EEPROM to be written to | |
707 | * @words: number of words to write | |
708 | * @data: 16 bit word(s) to be written to the EEPROM | |
709 | * | |
710 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
711 | * command has completed before trying to write the next word. After write | |
712 | * poll for completion. | |
713 | * | |
714 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 715 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
716 | **/ |
717 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
718 | u16 words, u16 *data) | |
719 | { | |
720 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 721 | u32 i, eewr = 0; |
bc7f75fa AK |
722 | s32 ret_val = 0; |
723 | ||
ad68076e BA |
724 | /* |
725 | * A check for invalid values: offset too large, too many words, | |
726 | * and not enough words. | |
727 | */ | |
bc7f75fa AK |
728 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
729 | (words == 0)) { | |
3bb99fe2 | 730 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
731 | return -E1000_ERR_NVM; |
732 | } | |
733 | ||
734 | for (i = 0; i < words; i++) { | |
735 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
736 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
737 | E1000_NVM_RW_REG_START; | |
738 | ||
739 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
740 | if (ret_val) | |
741 | break; | |
742 | ||
743 | ew32(EEWR, eewr); | |
744 | ||
745 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
746 | if (ret_val) | |
747 | break; | |
748 | } | |
749 | ||
750 | return ret_val; | |
751 | } | |
752 | ||
753 | /** | |
754 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
755 | * @hw: pointer to the HW structure | |
756 | * | |
757 | * Reads the management control register for the config done bit to be set. | |
758 | **/ | |
759 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
760 | { | |
761 | s32 timeout = PHY_CFG_TIMEOUT; | |
762 | ||
763 | while (timeout) { | |
764 | if (er32(EEMNGCTL) & | |
765 | E1000_NVM_CFG_DONE_PORT_0) | |
766 | break; | |
767 | msleep(1); | |
768 | timeout--; | |
769 | } | |
770 | if (!timeout) { | |
3bb99fe2 | 771 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
772 | return -E1000_ERR_RESET; |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /** | |
779 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
780 | * @hw: pointer to the HW structure | |
564ea9bb | 781 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
782 | * |
783 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
784 | * this function also disables smart speed and vice versa. LPLU will not be | |
785 | * activated unless the device autonegotiation advertisement meets standards | |
786 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
787 | * pointer entry point only called by PHY setup routines. | |
788 | **/ | |
789 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
790 | { | |
791 | struct e1000_phy_info *phy = &hw->phy; | |
792 | s32 ret_val; | |
793 | u16 data; | |
794 | ||
795 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
796 | if (ret_val) | |
797 | return ret_val; | |
798 | ||
799 | if (active) { | |
800 | data |= IGP02E1000_PM_D0_LPLU; | |
801 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
802 | if (ret_val) | |
803 | return ret_val; | |
804 | ||
805 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
806 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
807 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
808 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
809 | if (ret_val) | |
810 | return ret_val; | |
811 | } else { | |
812 | data &= ~IGP02E1000_PM_D0_LPLU; | |
813 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
814 | /* |
815 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
816 | * during Dx states where the power conservation is most |
817 | * important. During driver activity we should enable | |
ad68076e BA |
818 | * SmartSpeed, so performance is maintained. |
819 | */ | |
bc7f75fa AK |
820 | if (phy->smart_speed == e1000_smart_speed_on) { |
821 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 822 | &data); |
bc7f75fa AK |
823 | if (ret_val) |
824 | return ret_val; | |
825 | ||
826 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
827 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 828 | data); |
bc7f75fa AK |
829 | if (ret_val) |
830 | return ret_val; | |
831 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
832 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 833 | &data); |
bc7f75fa AK |
834 | if (ret_val) |
835 | return ret_val; | |
836 | ||
837 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
838 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 839 | data); |
bc7f75fa AK |
840 | if (ret_val) |
841 | return ret_val; | |
842 | } | |
843 | } | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | /** | |
849 | * e1000_reset_hw_82571 - Reset hardware | |
850 | * @hw: pointer to the HW structure | |
851 | * | |
fe401674 | 852 | * This resets the hardware into a known state. |
bc7f75fa AK |
853 | **/ |
854 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
855 | { | |
a708dd88 | 856 | u32 ctrl, extcnf_ctrl, ctrl_ext, icr; |
bc7f75fa AK |
857 | s32 ret_val; |
858 | u16 i = 0; | |
859 | ||
ad68076e BA |
860 | /* |
861 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
862 | * on the last TLP read/write transaction when MAC is reset. |
863 | */ | |
864 | ret_val = e1000e_disable_pcie_master(hw); | |
865 | if (ret_val) | |
3bb99fe2 | 866 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 867 | |
3bb99fe2 | 868 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
869 | ew32(IMC, 0xffffffff); |
870 | ||
871 | ew32(RCTL, 0); | |
872 | ew32(TCTL, E1000_TCTL_PSP); | |
873 | e1e_flush(); | |
874 | ||
875 | msleep(10); | |
876 | ||
ad68076e BA |
877 | /* |
878 | * Must acquire the MDIO ownership before MAC reset. | |
879 | * Ownership defaults to firmware after a reset. | |
880 | */ | |
8c81c9c3 AD |
881 | switch (hw->mac.type) { |
882 | case e1000_82573: | |
883 | case e1000_82574: | |
884 | case e1000_82583: | |
bc7f75fa AK |
885 | extcnf_ctrl = er32(EXTCNF_CTRL); |
886 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
887 | ||
888 | do { | |
889 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
890 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
891 | ||
892 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
893 | break; | |
894 | ||
895 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
896 | ||
897 | msleep(2); | |
898 | i++; | |
899 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
900 | break; |
901 | default: | |
902 | break; | |
bc7f75fa AK |
903 | } |
904 | ||
905 | ctrl = er32(CTRL); | |
906 | ||
3bb99fe2 | 907 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
908 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
909 | ||
910 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
911 | udelay(10); | |
912 | ctrl_ext = er32(CTRL_EXT); | |
913 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
914 | ew32(CTRL_EXT, ctrl_ext); | |
915 | e1e_flush(); | |
916 | } | |
917 | ||
918 | ret_val = e1000e_get_auto_rd_done(hw); | |
919 | if (ret_val) | |
920 | /* We don't want to continue accessing MAC registers. */ | |
921 | return ret_val; | |
922 | ||
ad68076e BA |
923 | /* |
924 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
925 | * Need to wait for Phy configuration completion before accessing |
926 | * NVM and Phy. | |
927 | */ | |
8c81c9c3 AD |
928 | |
929 | switch (hw->mac.type) { | |
930 | case e1000_82573: | |
931 | case e1000_82574: | |
932 | case e1000_82583: | |
bc7f75fa | 933 | msleep(25); |
8c81c9c3 AD |
934 | break; |
935 | default: | |
936 | break; | |
937 | } | |
bc7f75fa AK |
938 | |
939 | /* Clear any pending interrupt events. */ | |
940 | ew32(IMC, 0xffffffff); | |
941 | icr = er32(ICR); | |
942 | ||
1aef70ef BA |
943 | if (hw->mac.type == e1000_82571) { |
944 | /* Install any alternate MAC address into RAR0 */ | |
945 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
946 | if (ret_val) | |
947 | return ret_val; | |
608f8a0d | 948 | |
1aef70ef BA |
949 | e1000e_set_laa_state_82571(hw, true); |
950 | } | |
93ca1610 | 951 | |
c9523379 | 952 | /* Reinitialize the 82571 serdes link state machine */ |
953 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
954 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
955 | ||
bc7f75fa AK |
956 | return 0; |
957 | } | |
958 | ||
959 | /** | |
960 | * e1000_init_hw_82571 - Initialize hardware | |
961 | * @hw: pointer to the HW structure | |
962 | * | |
963 | * This inits the hardware readying it for operation. | |
964 | **/ | |
965 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
966 | { | |
967 | struct e1000_mac_info *mac = &hw->mac; | |
968 | u32 reg_data; | |
969 | s32 ret_val; | |
a708dd88 | 970 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
971 | |
972 | e1000_initialize_hw_bits_82571(hw); | |
973 | ||
974 | /* Initialize identification LED */ | |
975 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 976 | if (ret_val) |
3bb99fe2 | 977 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 978 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
979 | |
980 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 981 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 982 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
983 | |
984 | /* Setup the receive address. */ | |
ad68076e BA |
985 | /* |
986 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
987 | * 82571, we must reserve a RAR for it to work around an issue where |
988 | * resetting one port will reload the MAC on the other port. | |
989 | */ | |
990 | if (e1000e_get_laa_state_82571(hw)) | |
991 | rar_count--; | |
992 | e1000e_init_rx_addrs(hw, rar_count); | |
993 | ||
994 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 995 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
996 | for (i = 0; i < mac->mta_reg_count; i++) |
997 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
998 | ||
999 | /* Setup link and flow control */ | |
1000 | ret_val = e1000_setup_link_82571(hw); | |
1001 | ||
1002 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 1003 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
1004 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1005 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1006 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1007 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
1008 | |
1009 | /* ...for both queues. */ | |
8c81c9c3 AD |
1010 | switch (mac->type) { |
1011 | case e1000_82573: | |
a65a4a0d BA |
1012 | e1000e_enable_tx_pkt_filtering(hw); |
1013 | /* fall through */ | |
8c81c9c3 AD |
1014 | case e1000_82574: |
1015 | case e1000_82583: | |
8c81c9c3 AD |
1016 | reg_data = er32(GCR); |
1017 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1018 | ew32(GCR, reg_data); | |
1019 | break; | |
1020 | default: | |
e9ec2c0f | 1021 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1022 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1023 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1024 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1025 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1026 | break; |
bc7f75fa AK |
1027 | } |
1028 | ||
ad68076e BA |
1029 | /* |
1030 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1031 | * important that we do this after we have tried to establish link |
1032 | * because the symbol error count will increment wildly if there | |
1033 | * is no link. | |
1034 | */ | |
1035 | e1000_clear_hw_cntrs_82571(hw); | |
1036 | ||
1037 | return ret_val; | |
1038 | } | |
1039 | ||
1040 | /** | |
1041 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1042 | * @hw: pointer to the HW structure | |
1043 | * | |
1044 | * Initializes required hardware-dependent bits needed for normal operation. | |
1045 | **/ | |
1046 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1047 | { | |
1048 | u32 reg; | |
1049 | ||
1050 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1051 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1052 | reg |= (1 << 22); |
e9ec2c0f | 1053 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1054 | |
1055 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1056 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1057 | reg |= (1 << 22); |
e9ec2c0f | 1058 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1059 | |
1060 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1061 | reg = er32(TARC(0)); |
bc7f75fa AK |
1062 | reg &= ~(0xF << 27); /* 30:27 */ |
1063 | switch (hw->mac.type) { | |
1064 | case e1000_82571: | |
1065 | case e1000_82572: | |
1066 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1067 | break; | |
1068 | default: | |
1069 | break; | |
1070 | } | |
e9ec2c0f | 1071 | ew32(TARC(0), reg); |
bc7f75fa AK |
1072 | |
1073 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1074 | reg = er32(TARC(1)); |
bc7f75fa AK |
1075 | switch (hw->mac.type) { |
1076 | case e1000_82571: | |
1077 | case e1000_82572: | |
1078 | reg &= ~((1 << 29) | (1 << 30)); | |
1079 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1080 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1081 | reg &= ~(1 << 28); | |
1082 | else | |
1083 | reg |= (1 << 28); | |
e9ec2c0f | 1084 | ew32(TARC(1), reg); |
bc7f75fa AK |
1085 | break; |
1086 | default: | |
1087 | break; | |
1088 | } | |
1089 | ||
1090 | /* Device Control */ | |
8c81c9c3 AD |
1091 | switch (hw->mac.type) { |
1092 | case e1000_82573: | |
1093 | case e1000_82574: | |
1094 | case e1000_82583: | |
bc7f75fa AK |
1095 | reg = er32(CTRL); |
1096 | reg &= ~(1 << 29); | |
1097 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1098 | break; |
1099 | default: | |
1100 | break; | |
bc7f75fa AK |
1101 | } |
1102 | ||
1103 | /* Extended Device Control */ | |
8c81c9c3 AD |
1104 | switch (hw->mac.type) { |
1105 | case e1000_82573: | |
1106 | case e1000_82574: | |
1107 | case e1000_82583: | |
bc7f75fa AK |
1108 | reg = er32(CTRL_EXT); |
1109 | reg &= ~(1 << 23); | |
1110 | reg |= (1 << 22); | |
1111 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1112 | break; |
1113 | default: | |
1114 | break; | |
bc7f75fa | 1115 | } |
4662e82b | 1116 | |
6ea7ae1d AD |
1117 | if (hw->mac.type == e1000_82571) { |
1118 | reg = er32(PBA_ECC); | |
1119 | reg |= E1000_PBA_ECC_CORR_EN; | |
1120 | ew32(PBA_ECC, reg); | |
1121 | } | |
5df3f0ea | 1122 | /* |
1123 | * Workaround for hardware errata. | |
1124 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1125 | */ | |
1126 | ||
1127 | if ((hw->mac.type == e1000_82571) || | |
1128 | (hw->mac.type == e1000_82572)) { | |
1129 | reg = er32(CTRL_EXT); | |
1130 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1131 | ew32(CTRL_EXT, reg); | |
1132 | } | |
1133 | ||
6ea7ae1d | 1134 | |
78272bba | 1135 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1136 | switch (hw->mac.type) { |
1137 | case e1000_82574: | |
1138 | case e1000_82583: | |
4662e82b BA |
1139 | reg = er32(GCR); |
1140 | reg |= (1 << 22); | |
1141 | ew32(GCR, reg); | |
78272bba | 1142 | |
84efb7b9 BA |
1143 | /* |
1144 | * Workaround for hardware errata. | |
1145 | * apply workaround for hardware errata documented in errata | |
1146 | * docs Fixes issue where some error prone or unreliable PCIe | |
1147 | * completions are occurring, particularly with ASPM enabled. | |
1148 | * Without fix, issue can cause tx timeouts. | |
1149 | */ | |
78272bba JB |
1150 | reg = er32(GCR2); |
1151 | reg |= 1; | |
1152 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1153 | break; |
1154 | default: | |
1155 | break; | |
4662e82b | 1156 | } |
bc7f75fa AK |
1157 | } |
1158 | ||
1159 | /** | |
caaddaf8 | 1160 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1161 | * @hw: pointer to the HW structure |
1162 | * | |
1163 | * Clears the register array which contains the VLAN filter table by | |
1164 | * setting all the values to 0. | |
1165 | **/ | |
caaddaf8 | 1166 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1167 | { |
1168 | u32 offset; | |
1169 | u32 vfta_value = 0; | |
1170 | u32 vfta_offset = 0; | |
1171 | u32 vfta_bit_in_reg = 0; | |
1172 | ||
8c81c9c3 AD |
1173 | switch (hw->mac.type) { |
1174 | case e1000_82573: | |
1175 | case e1000_82574: | |
1176 | case e1000_82583: | |
bc7f75fa | 1177 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1178 | /* |
1179 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1180 | * a single VLAN ID. The following operations |
1181 | * determine which 32b entry (i.e. offset) into the | |
1182 | * array we want to set the VLAN ID (i.e. bit) of | |
1183 | * the manageability unit. | |
1184 | */ | |
1185 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1186 | E1000_VFTA_ENTRY_SHIFT) & | |
1187 | E1000_VFTA_ENTRY_MASK; | |
1188 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1189 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1190 | } | |
8c81c9c3 AD |
1191 | break; |
1192 | default: | |
1193 | break; | |
bc7f75fa AK |
1194 | } |
1195 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1196 | /* |
1197 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1198 | * manageability VLAN ID, then clear all bits except that of |
1199 | * the manageability unit. | |
1200 | */ | |
1201 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1202 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1203 | e1e_flush(); | |
1204 | } | |
1205 | } | |
1206 | ||
4662e82b BA |
1207 | /** |
1208 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1209 | * @hw: pointer to the HW structure | |
1210 | * | |
1211 | * Reads the NVM Initialization Control Word 2 and returns true | |
1212 | * (>0) if any manageability is enabled, else false (0). | |
1213 | **/ | |
1214 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1215 | { | |
1216 | u16 data; | |
1217 | ||
1218 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1219 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * e1000_led_on_82574 - Turn LED on | |
1224 | * @hw: pointer to the HW structure | |
1225 | * | |
1226 | * Turn LED on. | |
1227 | **/ | |
1228 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1229 | { | |
1230 | u32 ctrl; | |
1231 | u32 i; | |
1232 | ||
1233 | ctrl = hw->mac.ledctl_mode2; | |
1234 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1235 | /* | |
1236 | * If no link, then turn LED on by setting the invert bit | |
1237 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1238 | */ | |
1239 | for (i = 0; i < 4; i++) | |
1240 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1241 | E1000_LEDCTL_MODE_LED_ON) | |
1242 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1243 | } | |
1244 | ew32(LEDCTL, ctrl); | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
ff10e13c CW |
1249 | /** |
1250 | * e1000_check_phy_82574 - check 82574 phy hung state | |
1251 | * @hw: pointer to the HW structure | |
1252 | * | |
1253 | * Returns whether phy is hung or not | |
1254 | **/ | |
1255 | bool e1000_check_phy_82574(struct e1000_hw *hw) | |
1256 | { | |
1257 | u16 status_1kbt = 0; | |
1258 | u16 receive_errors = 0; | |
1259 | bool phy_hung = false; | |
1260 | s32 ret_val = 0; | |
1261 | ||
1262 | /* | |
1263 | * Read PHY Receive Error counter first, if its is max - all F's then | |
1264 | * read the Base1000T status register If both are max then PHY is hung. | |
1265 | */ | |
1266 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | |
1267 | ||
1268 | if (ret_val) | |
1269 | goto out; | |
1270 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { | |
1271 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | |
1272 | if (ret_val) | |
1273 | goto out; | |
1274 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == | |
1275 | E1000_IDLE_ERROR_COUNT_MASK) | |
1276 | phy_hung = true; | |
1277 | } | |
1278 | out: | |
1279 | return phy_hung; | |
1280 | } | |
1281 | ||
bc7f75fa AK |
1282 | /** |
1283 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1284 | * @hw: pointer to the HW structure | |
1285 | * | |
1286 | * Determines which flow control settings to use, then configures flow | |
1287 | * control. Calls the appropriate media-specific link configuration | |
1288 | * function. Assuming the adapter has a valid link partner, a valid link | |
1289 | * should be established. Assumes the hardware has previously been reset | |
1290 | * and the transmitter and receiver are not enabled. | |
1291 | **/ | |
1292 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1293 | { | |
ad68076e BA |
1294 | /* |
1295 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1296 | * the default flow control setting, so we explicitly |
1297 | * set it to full. | |
1298 | */ | |
8c81c9c3 AD |
1299 | switch (hw->mac.type) { |
1300 | case e1000_82573: | |
1301 | case e1000_82574: | |
1302 | case e1000_82583: | |
1303 | if (hw->fc.requested_mode == e1000_fc_default) | |
1304 | hw->fc.requested_mode = e1000_fc_full; | |
1305 | break; | |
1306 | default: | |
1307 | break; | |
1308 | } | |
bc7f75fa AK |
1309 | |
1310 | return e1000e_setup_link(hw); | |
1311 | } | |
1312 | ||
1313 | /** | |
1314 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1315 | * @hw: pointer to the HW structure | |
1316 | * | |
1317 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1318 | * for link, once link is established calls to configure collision distance | |
1319 | * and flow control are called. | |
1320 | **/ | |
1321 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1322 | { | |
1323 | u32 ctrl; | |
bc7f75fa AK |
1324 | s32 ret_val; |
1325 | ||
1326 | ctrl = er32(CTRL); | |
1327 | ctrl |= E1000_CTRL_SLU; | |
1328 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1329 | ew32(CTRL, ctrl); | |
1330 | ||
1331 | switch (hw->phy.type) { | |
1332 | case e1000_phy_m88: | |
4662e82b | 1333 | case e1000_phy_bm: |
bc7f75fa AK |
1334 | ret_val = e1000e_copper_link_setup_m88(hw); |
1335 | break; | |
1336 | case e1000_phy_igp_2: | |
1337 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1338 | break; |
1339 | default: | |
1340 | return -E1000_ERR_PHY; | |
1341 | break; | |
1342 | } | |
1343 | ||
1344 | if (ret_val) | |
1345 | return ret_val; | |
1346 | ||
1347 | ret_val = e1000e_setup_copper_link(hw); | |
1348 | ||
1349 | return ret_val; | |
1350 | } | |
1351 | ||
1352 | /** | |
1353 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1354 | * @hw: pointer to the HW structure | |
1355 | * | |
1356 | * Configures collision distance and flow control for fiber and serdes links. | |
1357 | * Upon successful setup, poll for link. | |
1358 | **/ | |
1359 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1360 | { | |
1361 | switch (hw->mac.type) { | |
1362 | case e1000_82571: | |
1363 | case e1000_82572: | |
ad68076e BA |
1364 | /* |
1365 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1366 | * of reset to take the adapter out of that mode. So we |
1367 | * have to explicitly take the adapter out of loopback | |
489815ce | 1368 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1369 | * if another tool failed to take it out of loopback mode. |
1370 | */ | |
ad68076e | 1371 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1372 | break; |
1373 | default: | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | return e1000e_setup_fiber_serdes_link(hw); | |
1378 | } | |
1379 | ||
c9523379 | 1380 | /** |
1381 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1382 | * @hw: pointer to the HW structure | |
1383 | * | |
1a40d5c1 BA |
1384 | * Reports the link state as up or down. |
1385 | * | |
1386 | * If autonegotiation is supported by the link partner, the link state is | |
1387 | * determined by the result of autonegotiation. This is the most likely case. | |
1388 | * If autonegotiation is not supported by the link partner, and the link | |
1389 | * has a valid signal, force the link up. | |
1390 | * | |
1391 | * The link state is represented internally here by 4 states: | |
1392 | * | |
1393 | * 1) down | |
1394 | * 2) autoneg_progress | |
3ad2f3fb | 1395 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1396 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1397 | * | |
c9523379 | 1398 | **/ |
f6370117 | 1399 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1400 | { |
1401 | struct e1000_mac_info *mac = &hw->mac; | |
1402 | u32 rxcw; | |
1403 | u32 ctrl; | |
1404 | u32 status; | |
1405 | s32 ret_val = 0; | |
1406 | ||
1407 | ctrl = er32(CTRL); | |
1408 | status = er32(STATUS); | |
1409 | rxcw = er32(RXCW); | |
1410 | ||
1411 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1412 | ||
1413 | /* Receiver is synchronized with no invalid bits. */ | |
1414 | switch (mac->serdes_link_state) { | |
1415 | case e1000_serdes_link_autoneg_complete: | |
1416 | if (!(status & E1000_STATUS_LU)) { | |
1417 | /* | |
1418 | * We have lost link, retry autoneg before | |
1419 | * reporting link failure | |
1420 | */ | |
1421 | mac->serdes_link_state = | |
1422 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1423 | mac->serdes_has_link = false; |
3bb99fe2 | 1424 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1425 | } |
1426 | break; | |
1427 | ||
1428 | case e1000_serdes_link_forced_up: | |
1429 | /* | |
1430 | * If we are receiving /C/ ordered sets, re-enable | |
1431 | * auto-negotiation in the TXCW register and disable | |
1432 | * forced link in the Device Control register in an | |
1433 | * attempt to auto-negotiate with our link partner. | |
1434 | */ | |
1435 | if (rxcw & E1000_RXCW_C) { | |
1436 | /* Enable autoneg, and unforce link up */ | |
1437 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1438 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1439 | mac->serdes_link_state = |
1440 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1441 | mac->serdes_has_link = false; |
3bb99fe2 | 1442 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1443 | } |
1444 | break; | |
1445 | ||
1446 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1447 | if (rxcw & E1000_RXCW_C) { |
1448 | /* | |
1449 | * We received /C/ ordered sets, meaning the | |
1450 | * link partner has autonegotiated, and we can | |
1451 | * trust the Link Up (LU) status bit. | |
1452 | */ | |
1453 | if (status & E1000_STATUS_LU) { | |
1454 | mac->serdes_link_state = | |
1455 | e1000_serdes_link_autoneg_complete; | |
1456 | e_dbg("AN_PROG -> AN_UP\n"); | |
1457 | mac->serdes_has_link = true; | |
1458 | } else { | |
1459 | /* Autoneg completed, but failed. */ | |
1460 | mac->serdes_link_state = | |
1461 | e1000_serdes_link_down; | |
1462 | e_dbg("AN_PROG -> DOWN\n"); | |
1463 | } | |
c9523379 | 1464 | } else { |
1465 | /* | |
1a40d5c1 BA |
1466 | * The link partner did not autoneg. |
1467 | * Force link up and full duplex, and change | |
1468 | * state to forced. | |
c9523379 | 1469 | */ |
1a40d5c1 | 1470 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1471 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1472 | ew32(CTRL, ctrl); | |
1473 | ||
1474 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1475 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1476 | if (ret_val) { |
3bb99fe2 | 1477 | e_dbg("Error config flow control\n"); |
c9523379 | 1478 | break; |
1479 | } | |
1480 | mac->serdes_link_state = | |
1481 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1482 | mac->serdes_has_link = true; |
3bb99fe2 | 1483 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1484 | } |
c9523379 | 1485 | break; |
1486 | ||
1487 | case e1000_serdes_link_down: | |
1488 | default: | |
1a40d5c1 BA |
1489 | /* |
1490 | * The link was down but the receiver has now gained | |
c9523379 | 1491 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1492 | * up. |
1493 | */ | |
c9523379 | 1494 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1495 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1496 | mac->serdes_link_state = |
1497 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1498 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1499 | break; |
1500 | } | |
1501 | } else { | |
1502 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1503 | mac->serdes_has_link = false; | |
1504 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1505 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1506 | } else { |
1507 | /* | |
1a40d5c1 BA |
1508 | * We have sync, and can tolerate one invalid (IV) |
1509 | * codeword before declaring link down, so reread | |
1510 | * to look again. | |
c9523379 | 1511 | */ |
1512 | udelay(10); | |
1513 | rxcw = er32(RXCW); | |
1514 | if (rxcw & E1000_RXCW_IV) { | |
1515 | mac->serdes_link_state = e1000_serdes_link_down; | |
1516 | mac->serdes_has_link = false; | |
3bb99fe2 | 1517 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1518 | } |
1519 | } | |
1520 | } | |
1521 | ||
1522 | return ret_val; | |
1523 | } | |
1524 | ||
bc7f75fa AK |
1525 | /** |
1526 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1527 | * @hw: pointer to the HW structure | |
1528 | * @data: pointer to the NVM (EEPROM) | |
1529 | * | |
1530 | * Read the EEPROM for the current default LED configuration. If the | |
1531 | * LED configuration is not valid, set to a valid LED configuration. | |
1532 | **/ | |
1533 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1534 | { | |
1535 | s32 ret_val; | |
1536 | ||
1537 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1538 | if (ret_val) { | |
3bb99fe2 | 1539 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1540 | return ret_val; |
1541 | } | |
1542 | ||
8c81c9c3 AD |
1543 | switch (hw->mac.type) { |
1544 | case e1000_82573: | |
1545 | case e1000_82574: | |
1546 | case e1000_82583: | |
1547 | if (*data == ID_LED_RESERVED_F746) | |
1548 | *data = ID_LED_DEFAULT_82573; | |
1549 | break; | |
1550 | default: | |
1551 | if (*data == ID_LED_RESERVED_0000 || | |
1552 | *data == ID_LED_RESERVED_FFFF) | |
1553 | *data = ID_LED_DEFAULT; | |
1554 | break; | |
1555 | } | |
bc7f75fa AK |
1556 | |
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | /** | |
1561 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1562 | * @hw: pointer to the HW structure | |
1563 | * | |
489815ce | 1564 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1565 | **/ |
1566 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1567 | { | |
1568 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1569 | return false; |
bc7f75fa AK |
1570 | |
1571 | return hw->dev_spec.e82571.laa_is_present; | |
1572 | } | |
1573 | ||
1574 | /** | |
1575 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1576 | * @hw: pointer to the HW structure | |
1577 | * @state: enable/disable locally administered address | |
1578 | * | |
5ff5b664 | 1579 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1580 | **/ |
1581 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1582 | { | |
1583 | if (hw->mac.type != e1000_82571) | |
1584 | return; | |
1585 | ||
1586 | hw->dev_spec.e82571.laa_is_present = state; | |
1587 | ||
1588 | /* If workaround is activated... */ | |
1589 | if (state) | |
ad68076e BA |
1590 | /* |
1591 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1592 | * between the time RAR[0] gets clobbered and the time it |
1593 | * gets fixed, the actual LAA is in one of the RARs and no | |
1594 | * incoming packets directed to this port are dropped. | |
1595 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1596 | */ | |
1597 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1598 | } | |
1599 | ||
1600 | /** | |
1601 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1602 | * @hw: pointer to the HW structure | |
1603 | * | |
1604 | * Verifies that the EEPROM has completed the update. After updating the | |
1605 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1606 | * the checksum fix is not implemented, we need to set the bit and update | |
1607 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1608 | * we need to return bad checksum. | |
1609 | **/ | |
1610 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1611 | { | |
1612 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1613 | s32 ret_val; | |
1614 | u16 data; | |
1615 | ||
1616 | if (nvm->type != e1000_nvm_flash_hw) | |
1617 | return 0; | |
1618 | ||
ad68076e BA |
1619 | /* |
1620 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1621 | * 10h-12h. Checksum may need to be fixed. |
1622 | */ | |
1623 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1624 | if (ret_val) | |
1625 | return ret_val; | |
1626 | ||
1627 | if (!(data & 0x10)) { | |
ad68076e BA |
1628 | /* |
1629 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1630 | * when the checksum has already been fixed. If |
1631 | * the checksum is still wrong and this bit is a | |
1632 | * 1, we need to return bad checksum. Otherwise, | |
1633 | * we need to set this bit to a 1 and update the | |
1634 | * checksum. | |
1635 | */ | |
1636 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1637 | if (ret_val) | |
1638 | return ret_val; | |
1639 | ||
1640 | if (!(data & 0x8000)) { | |
1641 | data |= 0x8000; | |
1642 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1643 | if (ret_val) | |
1644 | return ret_val; | |
1645 | ret_val = e1000e_update_nvm_checksum(hw); | |
1646 | } | |
1647 | } | |
1648 | ||
1649 | return 0; | |
1650 | } | |
1651 | ||
608f8a0d BA |
1652 | /** |
1653 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1654 | * @hw: pointer to the HW structure | |
1655 | **/ | |
1656 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1657 | { | |
1658 | s32 ret_val = 0; | |
1659 | ||
1aef70ef BA |
1660 | if (hw->mac.type == e1000_82571) { |
1661 | /* | |
1662 | * If there's an alternate MAC address place it in RAR0 | |
1663 | * so that it will override the Si installed default perm | |
1664 | * address. | |
1665 | */ | |
1666 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1667 | if (ret_val) | |
1668 | goto out; | |
1669 | } | |
608f8a0d BA |
1670 | |
1671 | ret_val = e1000_read_mac_addr_generic(hw); | |
1672 | ||
1673 | out: | |
1674 | return ret_val; | |
1675 | } | |
1676 | ||
17f208de BA |
1677 | /** |
1678 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1679 | * @hw: pointer to the HW structure | |
1680 | * | |
1681 | * In the case of a PHY power down to save power, or to turn off link during a | |
1682 | * driver unload, or wake on lan is not enabled, remove the link. | |
1683 | **/ | |
1684 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1685 | { | |
1686 | struct e1000_phy_info *phy = &hw->phy; | |
1687 | struct e1000_mac_info *mac = &hw->mac; | |
1688 | ||
1689 | if (!(phy->ops.check_reset_block)) | |
1690 | return; | |
1691 | ||
1692 | /* If the management interface is not enabled, then power down */ | |
1693 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1694 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1695 | } |
1696 | ||
bc7f75fa AK |
1697 | /** |
1698 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1699 | * @hw: pointer to the HW structure | |
1700 | * | |
1701 | * Clears the hardware counters by reading the counter registers. | |
1702 | **/ | |
1703 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1704 | { | |
bc7f75fa AK |
1705 | e1000e_clear_hw_cntrs_base(hw); |
1706 | ||
99673d9b BA |
1707 | er32(PRC64); |
1708 | er32(PRC127); | |
1709 | er32(PRC255); | |
1710 | er32(PRC511); | |
1711 | er32(PRC1023); | |
1712 | er32(PRC1522); | |
1713 | er32(PTC64); | |
1714 | er32(PTC127); | |
1715 | er32(PTC255); | |
1716 | er32(PTC511); | |
1717 | er32(PTC1023); | |
1718 | er32(PTC1522); | |
1719 | ||
1720 | er32(ALGNERRC); | |
1721 | er32(RXERRC); | |
1722 | er32(TNCRS); | |
1723 | er32(CEXTERR); | |
1724 | er32(TSCTC); | |
1725 | er32(TSCTFC); | |
1726 | ||
1727 | er32(MGTPRC); | |
1728 | er32(MGTPDC); | |
1729 | er32(MGTPTC); | |
1730 | ||
1731 | er32(IAC); | |
1732 | er32(ICRXOC); | |
1733 | ||
1734 | er32(ICRXPTC); | |
1735 | er32(ICRXATC); | |
1736 | er32(ICTXPTC); | |
1737 | er32(ICTXATC); | |
1738 | er32(ICTXQEC); | |
1739 | er32(ICTXQMTC); | |
1740 | er32(ICRXDMTC); | |
bc7f75fa AK |
1741 | } |
1742 | ||
1743 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1744 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1745 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1746 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1747 | .cleanup_led = e1000e_cleanup_led_generic, |
1748 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1749 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1750 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1751 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1752 | /* .led_on: mac type dependent */ |
bc7f75fa | 1753 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1754 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1755 | .write_vfta = e1000_write_vfta_generic, |
1756 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1757 | .reset_hw = e1000_reset_hw_82571, |
1758 | .init_hw = e1000_init_hw_82571, | |
1759 | .setup_link = e1000_setup_link_82571, | |
1760 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1761 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1762 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1763 | }; |
1764 | ||
1765 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1766 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1767 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1768 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1769 | .commit = NULL, |
bc7f75fa AK |
1770 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1771 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1772 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1773 | .get_info = e1000e_get_phy_info_igp, |
1774 | .read_reg = e1000e_read_phy_reg_igp, | |
1775 | .release = e1000_put_hw_semaphore_82571, | |
1776 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1777 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1778 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1779 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1780 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1781 | }; |
1782 | ||
1783 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1784 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1785 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1786 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1787 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1788 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1789 | .get_cfg_done = e1000e_get_cfg_done, | |
1790 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1791 | .get_info = e1000e_get_phy_info_m88, |
1792 | .read_reg = e1000e_read_phy_reg_m88, | |
1793 | .release = e1000_put_hw_semaphore_82571, | |
1794 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1795 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1796 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1797 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1798 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1799 | }; |
1800 | ||
4662e82b | 1801 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1802 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1803 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1804 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1805 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1806 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1807 | .get_cfg_done = e1000e_get_cfg_done, | |
1808 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1809 | .get_info = e1000e_get_phy_info_m88, |
1810 | .read_reg = e1000e_read_phy_reg_bm2, | |
1811 | .release = e1000_put_hw_semaphore_82571, | |
1812 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1813 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1814 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1815 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1816 | .cfg_on_link_up = NULL, |
4662e82b BA |
1817 | }; |
1818 | ||
bc7f75fa | 1819 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1820 | .acquire = e1000_acquire_nvm_82571, |
1821 | .read = e1000e_read_nvm_eerd, | |
1822 | .release = e1000_release_nvm_82571, | |
1823 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1824 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1825 | .validate = e1000_validate_nvm_checksum_82571, |
1826 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1827 | }; |
1828 | ||
1829 | struct e1000_info e1000_82571_info = { | |
1830 | .mac = e1000_82571, | |
1831 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1832 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1833 | | FLAG_HAS_WOL |
1834 | | FLAG_APME_IN_CTRL3 | |
1835 | | FLAG_RX_CSUM_ENABLED | |
1836 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1837 | | FLAG_HAS_SMART_POWER_DOWN |
1838 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1839 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1840 | | FLAG_APME_CHECK_PORT_B, | |
3a3b7586 JB |
1841 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1842 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1843 | .pba = 38, |
2adc55c9 | 1844 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1845 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1846 | .mac_ops = &e82571_mac_ops, |
1847 | .phy_ops = &e82_phy_ops_igp, | |
1848 | .nvm_ops = &e82571_nvm_ops, | |
1849 | }; | |
1850 | ||
1851 | struct e1000_info e1000_82572_info = { | |
1852 | .mac = e1000_82572, | |
1853 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1854 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1855 | | FLAG_HAS_WOL |
1856 | | FLAG_APME_IN_CTRL3 | |
1857 | | FLAG_RX_CSUM_ENABLED | |
1858 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa | 1859 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
3a3b7586 JB |
1860 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1861 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1862 | .pba = 38, |
2adc55c9 | 1863 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1864 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1865 | .mac_ops = &e82571_mac_ops, |
1866 | .phy_ops = &e82_phy_ops_igp, | |
1867 | .nvm_ops = &e82571_nvm_ops, | |
1868 | }; | |
1869 | ||
1870 | struct e1000_info e1000_82573_info = { | |
1871 | .mac = e1000_82573, | |
1872 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
bc7f75fa AK |
1873 | | FLAG_HAS_WOL |
1874 | | FLAG_APME_IN_CTRL3 | |
1875 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1876 | | FLAG_HAS_SMART_POWER_DOWN |
1877 | | FLAG_HAS_AMT | |
bc7f75fa | 1878 | | FLAG_HAS_SWSM_ON_LOAD, |
19833b5d | 1879 | .flags2 = FLAG2_DISABLE_ASPM_L1, |
bc7f75fa | 1880 | .pba = 20, |
2adc55c9 | 1881 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1882 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1883 | .mac_ops = &e82571_mac_ops, |
1884 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1885 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1886 | }; |
1887 | ||
4662e82b BA |
1888 | struct e1000_info e1000_82574_info = { |
1889 | .mac = e1000_82574, | |
1890 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1891 | | FLAG_HAS_MSIX | |
1892 | | FLAG_HAS_JUMBO_FRAMES | |
1893 | | FLAG_HAS_WOL | |
1894 | | FLAG_APME_IN_CTRL3 | |
1895 | | FLAG_RX_CSUM_ENABLED | |
1896 | | FLAG_HAS_SMART_POWER_DOWN | |
1897 | | FLAG_HAS_AMT | |
1898 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ff10e13c | 1899 | .flags2 = FLAG2_CHECK_PHY_HANG, |
edf15c17 | 1900 | .pba = 36, |
a825e00c | 1901 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
1902 | .get_variants = e1000_get_variants_82571, |
1903 | .mac_ops = &e82571_mac_ops, | |
1904 | .phy_ops = &e82_phy_ops_bm, | |
1905 | .nvm_ops = &e82571_nvm_ops, | |
1906 | }; | |
1907 | ||
8c81c9c3 AD |
1908 | struct e1000_info e1000_82583_info = { |
1909 | .mac = e1000_82583, | |
1910 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1911 | | FLAG_HAS_WOL | |
1912 | | FLAG_APME_IN_CTRL3 | |
1913 | | FLAG_RX_CSUM_ENABLED | |
1914 | | FLAG_HAS_SMART_POWER_DOWN | |
1915 | | FLAG_HAS_AMT | |
1916 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
edf15c17 | 1917 | .pba = 36, |
a825e00c | 1918 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
1919 | .get_variants = e1000_get_variants_82571, |
1920 | .mac_ops = &e82571_mac_ops, | |
1921 | .phy_ops = &e82_phy_ops_bm, | |
1922 | .nvm_ops = &e82571_nvm_ops, | |
1923 | }; | |
1924 |