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1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
4 | Copyright(c) 1999 - 2007 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
31 | * 82571EB Gigabit Ethernet Controller (Fiber) | |
32 | * 82572EI Gigabit Ethernet Controller (Copper) | |
33 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
34 | * 82572EI Gigabit Ethernet Controller | |
35 | * 82573V Gigabit Ethernet Controller (Copper) | |
36 | * 82573E Gigabit Ethernet Controller (Copper) | |
37 | * 82573L Gigabit Ethernet Controller | |
38 | */ | |
39 | ||
40 | #include <linux/netdevice.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/pci.h> | |
43 | ||
44 | #include "e1000.h" | |
45 | ||
46 | #define ID_LED_RESERVED_F746 0xF746 | |
47 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
48 | (ID_LED_OFF1_ON2 << 8) | \ | |
49 | (ID_LED_DEF1_DEF2 << 4) | \ | |
50 | (ID_LED_DEF1_DEF2)) | |
51 | ||
52 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
53 | ||
54 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); | |
55 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
56 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
57 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
58 | u16 words, u16 *data); | |
59 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
60 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
61 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
62 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
63 | ||
64 | /** | |
65 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
66 | * @hw: pointer to the HW structure | |
67 | * | |
68 | * This is a function pointer entry point called by the api module. | |
69 | **/ | |
70 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
71 | { | |
72 | struct e1000_phy_info *phy = &hw->phy; | |
73 | s32 ret_val; | |
74 | ||
75 | if (hw->media_type != e1000_media_type_copper) { | |
76 | phy->type = e1000_phy_none; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | phy->addr = 1; | |
81 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
82 | phy->reset_delay_us = 100; | |
83 | ||
84 | switch (hw->mac.type) { | |
85 | case e1000_82571: | |
86 | case e1000_82572: | |
87 | phy->type = e1000_phy_igp_2; | |
88 | break; | |
89 | case e1000_82573: | |
90 | phy->type = e1000_phy_m88; | |
91 | break; | |
92 | default: | |
93 | return -E1000_ERR_PHY; | |
94 | break; | |
95 | } | |
96 | ||
97 | /* This can only be done after all function pointers are setup. */ | |
98 | ret_val = e1000_get_phy_id_82571(hw); | |
99 | ||
100 | /* Verify phy id */ | |
101 | switch (hw->mac.type) { | |
102 | case e1000_82571: | |
103 | case e1000_82572: | |
104 | if (phy->id != IGP01E1000_I_PHY_ID) | |
105 | return -E1000_ERR_PHY; | |
106 | break; | |
107 | case e1000_82573: | |
108 | if (phy->id != M88E1111_I_PHY_ID) | |
109 | return -E1000_ERR_PHY; | |
110 | break; | |
111 | default: | |
112 | return -E1000_ERR_PHY; | |
113 | break; | |
114 | } | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | /** | |
120 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
121 | * @hw: pointer to the HW structure | |
122 | * | |
123 | * This is a function pointer entry point called by the api module. | |
124 | **/ | |
125 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
126 | { | |
127 | struct e1000_nvm_info *nvm = &hw->nvm; | |
128 | u32 eecd = er32(EECD); | |
129 | u16 size; | |
130 | ||
131 | nvm->opcode_bits = 8; | |
132 | nvm->delay_usec = 1; | |
133 | switch (nvm->override) { | |
134 | case e1000_nvm_override_spi_large: | |
135 | nvm->page_size = 32; | |
136 | nvm->address_bits = 16; | |
137 | break; | |
138 | case e1000_nvm_override_spi_small: | |
139 | nvm->page_size = 8; | |
140 | nvm->address_bits = 8; | |
141 | break; | |
142 | default: | |
143 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
144 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
145 | break; | |
146 | } | |
147 | ||
148 | switch (hw->mac.type) { | |
149 | case e1000_82573: | |
150 | if (((eecd >> 15) & 0x3) == 0x3) { | |
151 | nvm->type = e1000_nvm_flash_hw; | |
152 | nvm->word_size = 2048; | |
153 | /* Autonomous Flash update bit must be cleared due | |
154 | * to Flash update issue. | |
155 | */ | |
156 | eecd &= ~E1000_EECD_AUPDEN; | |
157 | ew32(EECD, eecd); | |
158 | break; | |
159 | } | |
160 | /* Fall Through */ | |
161 | default: | |
162 | nvm->type = e1000_nvm_eeprom_spi; | |
163 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
164 | E1000_EECD_SIZE_EX_SHIFT); | |
165 | /* Added to a constant, "size" becomes the left-shift value | |
166 | * for setting word_size. | |
167 | */ | |
168 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
169 | nvm->word_size = 1 << size; | |
170 | break; | |
171 | } | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | /** | |
177 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
178 | * @hw: pointer to the HW structure | |
179 | * | |
180 | * This is a function pointer entry point called by the api module. | |
181 | **/ | |
182 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
183 | { | |
184 | struct e1000_hw *hw = &adapter->hw; | |
185 | struct e1000_mac_info *mac = &hw->mac; | |
186 | struct e1000_mac_operations *func = &mac->ops; | |
187 | ||
188 | /* Set media type */ | |
189 | switch (adapter->pdev->device) { | |
190 | case E1000_DEV_ID_82571EB_FIBER: | |
191 | case E1000_DEV_ID_82572EI_FIBER: | |
192 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
193 | hw->media_type = e1000_media_type_fiber; | |
194 | break; | |
195 | case E1000_DEV_ID_82571EB_SERDES: | |
196 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
197 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
198 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
bc7f75fa AK |
199 | hw->media_type = e1000_media_type_internal_serdes; |
200 | break; | |
201 | default: | |
202 | hw->media_type = e1000_media_type_copper; | |
203 | break; | |
204 | } | |
205 | ||
206 | /* Set mta register count */ | |
207 | mac->mta_reg_count = 128; | |
208 | /* Set rar entry count */ | |
209 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
210 | /* Set if manageability features are enabled. */ | |
211 | mac->arc_subsystem_valid = | |
212 | (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; | |
213 | ||
214 | /* check for link */ | |
215 | switch (hw->media_type) { | |
216 | case e1000_media_type_copper: | |
217 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
218 | func->check_for_link = e1000e_check_for_copper_link; | |
219 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
220 | break; | |
221 | case e1000_media_type_fiber: | |
222 | func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; | |
223 | func->check_for_link = e1000e_check_for_fiber_link; | |
224 | func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; | |
225 | break; | |
226 | case e1000_media_type_internal_serdes: | |
227 | func->setup_physical_interface = e1000_setup_fiber_serdes_link_82571; | |
228 | func->check_for_link = e1000e_check_for_serdes_link; | |
229 | func->get_link_up_info = e1000e_get_speed_and_duplex_fiber_serdes; | |
230 | break; | |
231 | default: | |
232 | return -E1000_ERR_CONFIG; | |
233 | break; | |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) | |
240 | { | |
241 | struct e1000_hw *hw = &adapter->hw; | |
242 | static int global_quad_port_a; /* global port a indication */ | |
243 | struct pci_dev *pdev = adapter->pdev; | |
244 | u16 eeprom_data = 0; | |
245 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
246 | s32 rc; | |
247 | ||
248 | rc = e1000_init_mac_params_82571(adapter); | |
249 | if (rc) | |
250 | return rc; | |
251 | ||
252 | rc = e1000_init_nvm_params_82571(hw); | |
253 | if (rc) | |
254 | return rc; | |
255 | ||
256 | rc = e1000_init_phy_params_82571(hw); | |
257 | if (rc) | |
258 | return rc; | |
259 | ||
260 | /* tag quad port adapters first, it's used below */ | |
261 | switch (pdev->device) { | |
262 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
263 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
264 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 265 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
266 | adapter->flags |= FLAG_IS_QUAD_PORT; |
267 | /* mark the first port */ | |
268 | if (global_quad_port_a == 0) | |
269 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
270 | /* Reset for multiple quad port adapters */ | |
271 | global_quad_port_a++; | |
272 | if (global_quad_port_a == 4) | |
273 | global_quad_port_a = 0; | |
274 | break; | |
275 | default: | |
276 | break; | |
277 | } | |
278 | ||
279 | switch (adapter->hw.mac.type) { | |
280 | case e1000_82571: | |
281 | /* these dual ports don't have WoL on port B at all */ | |
282 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
283 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
284 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
285 | (is_port_b)) | |
286 | adapter->flags &= ~FLAG_HAS_WOL; | |
287 | /* quad ports only support WoL on port A */ | |
288 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 289 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 290 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
291 | /* Does not support WoL on any port */ |
292 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
293 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
294 | break; |
295 | ||
296 | case e1000_82573: | |
297 | if (pdev->device == E1000_DEV_ID_82573L) { | |
298 | e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, | |
299 | &eeprom_data); | |
300 | if (eeprom_data & NVM_WORD1A_ASPM_MASK) | |
301 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
302 | } | |
303 | break; | |
304 | default: | |
305 | break; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | /** | |
312 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
313 | * @hw: pointer to the HW structure | |
314 | * | |
315 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
316 | * revision in the hardware structure. | |
317 | **/ | |
318 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
319 | { | |
320 | struct e1000_phy_info *phy = &hw->phy; | |
321 | ||
322 | switch (hw->mac.type) { | |
323 | case e1000_82571: | |
324 | case e1000_82572: | |
325 | /* The 82571 firmware may still be configuring the PHY. | |
326 | * In this case, we cannot access the PHY until the | |
327 | * configuration is done. So we explicitly set the | |
328 | * PHY ID. */ | |
329 | phy->id = IGP01E1000_I_PHY_ID; | |
330 | break; | |
331 | case e1000_82573: | |
332 | return e1000e_get_phy_id(hw); | |
333 | break; | |
334 | default: | |
335 | return -E1000_ERR_PHY; | |
336 | break; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | /** | |
343 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
344 | * @hw: pointer to the HW structure | |
345 | * | |
346 | * Acquire the HW semaphore to access the PHY or NVM | |
347 | **/ | |
348 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
349 | { | |
350 | u32 swsm; | |
351 | s32 timeout = hw->nvm.word_size + 1; | |
352 | s32 i = 0; | |
353 | ||
354 | /* Get the FW semaphore. */ | |
355 | for (i = 0; i < timeout; i++) { | |
356 | swsm = er32(SWSM); | |
357 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
358 | ||
359 | /* Semaphore acquired if bit latched */ | |
360 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
361 | break; | |
362 | ||
363 | udelay(50); | |
364 | } | |
365 | ||
366 | if (i == timeout) { | |
367 | /* Release semaphores */ | |
368 | e1000e_put_hw_semaphore(hw); | |
369 | hw_dbg(hw, "Driver can't access the NVM\n"); | |
370 | return -E1000_ERR_NVM; | |
371 | } | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | /** | |
377 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
378 | * @hw: pointer to the HW structure | |
379 | * | |
380 | * Release hardware semaphore used to access the PHY or NVM | |
381 | **/ | |
382 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
383 | { | |
384 | u32 swsm; | |
385 | ||
386 | swsm = er32(SWSM); | |
387 | ||
388 | swsm &= ~E1000_SWSM_SWESMBI; | |
389 | ||
390 | ew32(SWSM, swsm); | |
391 | } | |
392 | ||
393 | /** | |
394 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
395 | * @hw: pointer to the HW structure | |
396 | * | |
397 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
398 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
399 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
400 | * hardware semaphore. | |
401 | **/ | |
402 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
403 | { | |
404 | s32 ret_val; | |
405 | ||
406 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
407 | if (ret_val) | |
408 | return ret_val; | |
409 | ||
410 | if (hw->mac.type != e1000_82573) | |
411 | ret_val = e1000e_acquire_nvm(hw); | |
412 | ||
413 | if (ret_val) | |
414 | e1000_put_hw_semaphore_82571(hw); | |
415 | ||
416 | return ret_val; | |
417 | } | |
418 | ||
419 | /** | |
420 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
421 | * @hw: pointer to the HW structure | |
422 | * | |
423 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
424 | **/ | |
425 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
426 | { | |
427 | e1000e_release_nvm(hw); | |
428 | e1000_put_hw_semaphore_82571(hw); | |
429 | } | |
430 | ||
431 | /** | |
432 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
433 | * @hw: pointer to the HW structure | |
434 | * @offset: offset within the EEPROM to be written to | |
435 | * @words: number of words to write | |
436 | * @data: 16 bit word(s) to be written to the EEPROM | |
437 | * | |
438 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
439 | * | |
440 | * If e1000e_update_nvm_checksum is not called after this function, the | |
441 | * EEPROM will most likley contain an invalid checksum. | |
442 | **/ | |
443 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
444 | u16 *data) | |
445 | { | |
446 | s32 ret_val; | |
447 | ||
448 | switch (hw->mac.type) { | |
449 | case e1000_82573: | |
450 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); | |
451 | break; | |
452 | case e1000_82571: | |
453 | case e1000_82572: | |
454 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
455 | break; | |
456 | default: | |
457 | ret_val = -E1000_ERR_NVM; | |
458 | break; | |
459 | } | |
460 | ||
461 | return ret_val; | |
462 | } | |
463 | ||
464 | /** | |
465 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
466 | * @hw: pointer to the HW structure | |
467 | * | |
468 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
469 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
470 | * value to the EEPROM. | |
471 | **/ | |
472 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
473 | { | |
474 | u32 eecd; | |
475 | s32 ret_val; | |
476 | u16 i; | |
477 | ||
478 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
479 | if (ret_val) | |
480 | return ret_val; | |
481 | ||
482 | /* If our nvm is an EEPROM, then we're done | |
483 | * otherwise, commit the checksum to the flash NVM. */ | |
484 | if (hw->nvm.type != e1000_nvm_flash_hw) | |
485 | return ret_val; | |
486 | ||
487 | /* Check for pending operations. */ | |
488 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
489 | msleep(1); | |
490 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
491 | break; | |
492 | } | |
493 | ||
494 | if (i == E1000_FLASH_UPDATES) | |
495 | return -E1000_ERR_NVM; | |
496 | ||
497 | /* Reset the firmware if using STM opcode. */ | |
498 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
499 | /* The enabling of and the actual reset must be done | |
500 | * in two write cycles. | |
501 | */ | |
502 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
503 | e1e_flush(); | |
504 | ew32(HICR, E1000_HICR_FW_RESET); | |
505 | } | |
506 | ||
507 | /* Commit the write to flash */ | |
508 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
509 | ew32(EECD, eecd); | |
510 | ||
511 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
512 | msleep(1); | |
513 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
514 | break; | |
515 | } | |
516 | ||
517 | if (i == E1000_FLASH_UPDATES) | |
518 | return -E1000_ERR_NVM; | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | /** | |
524 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
525 | * @hw: pointer to the HW structure | |
526 | * | |
527 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
528 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
529 | **/ | |
530 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
531 | { | |
532 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
533 | e1000_fix_nvm_checksum_82571(hw); | |
534 | ||
535 | return e1000e_validate_nvm_checksum_generic(hw); | |
536 | } | |
537 | ||
538 | /** | |
539 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
540 | * @hw: pointer to the HW structure | |
541 | * @offset: offset within the EEPROM to be written to | |
542 | * @words: number of words to write | |
543 | * @data: 16 bit word(s) to be written to the EEPROM | |
544 | * | |
545 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
546 | * command has completed before trying to write the next word. After write | |
547 | * poll for completion. | |
548 | * | |
549 | * If e1000e_update_nvm_checksum is not called after this function, the | |
550 | * EEPROM will most likley contain an invalid checksum. | |
551 | **/ | |
552 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
553 | u16 words, u16 *data) | |
554 | { | |
555 | struct e1000_nvm_info *nvm = &hw->nvm; | |
556 | u32 i; | |
557 | u32 eewr = 0; | |
558 | s32 ret_val = 0; | |
559 | ||
560 | /* A check for invalid values: offset too large, too many words, | |
561 | * and not enough words. */ | |
562 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
563 | (words == 0)) { | |
564 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
565 | return -E1000_ERR_NVM; | |
566 | } | |
567 | ||
568 | for (i = 0; i < words; i++) { | |
569 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
570 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
571 | E1000_NVM_RW_REG_START; | |
572 | ||
573 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
574 | if (ret_val) | |
575 | break; | |
576 | ||
577 | ew32(EEWR, eewr); | |
578 | ||
579 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
580 | if (ret_val) | |
581 | break; | |
582 | } | |
583 | ||
584 | return ret_val; | |
585 | } | |
586 | ||
587 | /** | |
588 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
589 | * @hw: pointer to the HW structure | |
590 | * | |
591 | * Reads the management control register for the config done bit to be set. | |
592 | **/ | |
593 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
594 | { | |
595 | s32 timeout = PHY_CFG_TIMEOUT; | |
596 | ||
597 | while (timeout) { | |
598 | if (er32(EEMNGCTL) & | |
599 | E1000_NVM_CFG_DONE_PORT_0) | |
600 | break; | |
601 | msleep(1); | |
602 | timeout--; | |
603 | } | |
604 | if (!timeout) { | |
605 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
606 | return -E1000_ERR_RESET; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | /** | |
613 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
614 | * @hw: pointer to the HW structure | |
615 | * @active: TRUE to enable LPLU, FALSE to disable | |
616 | * | |
617 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
618 | * this function also disables smart speed and vice versa. LPLU will not be | |
619 | * activated unless the device autonegotiation advertisement meets standards | |
620 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
621 | * pointer entry point only called by PHY setup routines. | |
622 | **/ | |
623 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
624 | { | |
625 | struct e1000_phy_info *phy = &hw->phy; | |
626 | s32 ret_val; | |
627 | u16 data; | |
628 | ||
629 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
630 | if (ret_val) | |
631 | return ret_val; | |
632 | ||
633 | if (active) { | |
634 | data |= IGP02E1000_PM_D0_LPLU; | |
635 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
636 | if (ret_val) | |
637 | return ret_val; | |
638 | ||
639 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
640 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
641 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
642 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
643 | if (ret_val) | |
644 | return ret_val; | |
645 | } else { | |
646 | data &= ~IGP02E1000_PM_D0_LPLU; | |
647 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
648 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
649 | * during Dx states where the power conservation is most | |
650 | * important. During driver activity we should enable | |
651 | * SmartSpeed, so performance is maintained. */ | |
652 | if (phy->smart_speed == e1000_smart_speed_on) { | |
653 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
654 | &data); | |
655 | if (ret_val) | |
656 | return ret_val; | |
657 | ||
658 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
659 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
660 | data); | |
661 | if (ret_val) | |
662 | return ret_val; | |
663 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
664 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
665 | &data); | |
666 | if (ret_val) | |
667 | return ret_val; | |
668 | ||
669 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
670 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
671 | data); | |
672 | if (ret_val) | |
673 | return ret_val; | |
674 | } | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | /** | |
681 | * e1000_reset_hw_82571 - Reset hardware | |
682 | * @hw: pointer to the HW structure | |
683 | * | |
684 | * This resets the hardware into a known state. This is a | |
685 | * function pointer entry point called by the api module. | |
686 | **/ | |
687 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
688 | { | |
689 | u32 ctrl; | |
690 | u32 extcnf_ctrl; | |
691 | u32 ctrl_ext; | |
692 | u32 icr; | |
693 | s32 ret_val; | |
694 | u16 i = 0; | |
695 | ||
696 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | |
697 | * on the last TLP read/write transaction when MAC is reset. | |
698 | */ | |
699 | ret_val = e1000e_disable_pcie_master(hw); | |
700 | if (ret_val) | |
701 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
702 | ||
703 | hw_dbg(hw, "Masking off all interrupts\n"); | |
704 | ew32(IMC, 0xffffffff); | |
705 | ||
706 | ew32(RCTL, 0); | |
707 | ew32(TCTL, E1000_TCTL_PSP); | |
708 | e1e_flush(); | |
709 | ||
710 | msleep(10); | |
711 | ||
712 | /* Must acquire the MDIO ownership before MAC reset. | |
713 | * Ownership defaults to firmware after a reset. */ | |
714 | if (hw->mac.type == e1000_82573) { | |
715 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
716 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
717 | ||
718 | do { | |
719 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
720 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
721 | ||
722 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
723 | break; | |
724 | ||
725 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
726 | ||
727 | msleep(2); | |
728 | i++; | |
729 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
730 | } | |
731 | ||
732 | ctrl = er32(CTRL); | |
733 | ||
734 | hw_dbg(hw, "Issuing a global reset to MAC\n"); | |
735 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
736 | ||
737 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
738 | udelay(10); | |
739 | ctrl_ext = er32(CTRL_EXT); | |
740 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
741 | ew32(CTRL_EXT, ctrl_ext); | |
742 | e1e_flush(); | |
743 | } | |
744 | ||
745 | ret_val = e1000e_get_auto_rd_done(hw); | |
746 | if (ret_val) | |
747 | /* We don't want to continue accessing MAC registers. */ | |
748 | return ret_val; | |
749 | ||
750 | /* Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
751 | * Need to wait for Phy configuration completion before accessing | |
752 | * NVM and Phy. | |
753 | */ | |
754 | if (hw->mac.type == e1000_82573) | |
755 | msleep(25); | |
756 | ||
757 | /* Clear any pending interrupt events. */ | |
758 | ew32(IMC, 0xffffffff); | |
759 | icr = er32(ICR); | |
760 | ||
93ca1610 BH |
761 | if (hw->mac.type == e1000_82571 && |
762 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
763 | e1000e_set_laa_state_82571(hw, true); | |
764 | ||
bc7f75fa AK |
765 | return 0; |
766 | } | |
767 | ||
768 | /** | |
769 | * e1000_init_hw_82571 - Initialize hardware | |
770 | * @hw: pointer to the HW structure | |
771 | * | |
772 | * This inits the hardware readying it for operation. | |
773 | **/ | |
774 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
775 | { | |
776 | struct e1000_mac_info *mac = &hw->mac; | |
777 | u32 reg_data; | |
778 | s32 ret_val; | |
779 | u16 i; | |
780 | u16 rar_count = mac->rar_entry_count; | |
781 | ||
782 | e1000_initialize_hw_bits_82571(hw); | |
783 | ||
784 | /* Initialize identification LED */ | |
785 | ret_val = e1000e_id_led_init(hw); | |
786 | if (ret_val) { | |
787 | hw_dbg(hw, "Error initializing identification LED\n"); | |
788 | return ret_val; | |
789 | } | |
790 | ||
791 | /* Disabling VLAN filtering */ | |
792 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
793 | e1000e_clear_vfta(hw); | |
794 | ||
795 | /* Setup the receive address. */ | |
796 | /* If, however, a locally administered address was assigned to the | |
797 | * 82571, we must reserve a RAR for it to work around an issue where | |
798 | * resetting one port will reload the MAC on the other port. | |
799 | */ | |
800 | if (e1000e_get_laa_state_82571(hw)) | |
801 | rar_count--; | |
802 | e1000e_init_rx_addrs(hw, rar_count); | |
803 | ||
804 | /* Zero out the Multicast HASH table */ | |
805 | hw_dbg(hw, "Zeroing the MTA\n"); | |
806 | for (i = 0; i < mac->mta_reg_count; i++) | |
807 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
808 | ||
809 | /* Setup link and flow control */ | |
810 | ret_val = e1000_setup_link_82571(hw); | |
811 | ||
812 | /* Set the transmit descriptor write-back policy */ | |
813 | reg_data = er32(TXDCTL); | |
814 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | |
815 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
816 | E1000_TXDCTL_COUNT_DESC; | |
817 | ew32(TXDCTL, reg_data); | |
818 | ||
819 | /* ...for both queues. */ | |
820 | if (mac->type != e1000_82573) { | |
821 | reg_data = er32(TXDCTL1); | |
822 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | | |
823 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
824 | E1000_TXDCTL_COUNT_DESC; | |
825 | ew32(TXDCTL1, reg_data); | |
826 | } else { | |
827 | e1000e_enable_tx_pkt_filtering(hw); | |
828 | reg_data = er32(GCR); | |
829 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
830 | ew32(GCR, reg_data); | |
831 | } | |
832 | ||
833 | /* Clear all of the statistics registers (clear on read). It is | |
834 | * important that we do this after we have tried to establish link | |
835 | * because the symbol error count will increment wildly if there | |
836 | * is no link. | |
837 | */ | |
838 | e1000_clear_hw_cntrs_82571(hw); | |
839 | ||
840 | return ret_val; | |
841 | } | |
842 | ||
843 | /** | |
844 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
845 | * @hw: pointer to the HW structure | |
846 | * | |
847 | * Initializes required hardware-dependent bits needed for normal operation. | |
848 | **/ | |
849 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
850 | { | |
851 | u32 reg; | |
852 | ||
853 | /* Transmit Descriptor Control 0 */ | |
854 | reg = er32(TXDCTL); | |
855 | reg |= (1 << 22); | |
856 | ew32(TXDCTL, reg); | |
857 | ||
858 | /* Transmit Descriptor Control 1 */ | |
859 | reg = er32(TXDCTL1); | |
860 | reg |= (1 << 22); | |
861 | ew32(TXDCTL1, reg); | |
862 | ||
863 | /* Transmit Arbitration Control 0 */ | |
864 | reg = er32(TARC0); | |
865 | reg &= ~(0xF << 27); /* 30:27 */ | |
866 | switch (hw->mac.type) { | |
867 | case e1000_82571: | |
868 | case e1000_82572: | |
869 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
870 | break; | |
871 | default: | |
872 | break; | |
873 | } | |
874 | ew32(TARC0, reg); | |
875 | ||
876 | /* Transmit Arbitration Control 1 */ | |
877 | reg = er32(TARC1); | |
878 | switch (hw->mac.type) { | |
879 | case e1000_82571: | |
880 | case e1000_82572: | |
881 | reg &= ~((1 << 29) | (1 << 30)); | |
882 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
883 | if (er32(TCTL) & E1000_TCTL_MULR) | |
884 | reg &= ~(1 << 28); | |
885 | else | |
886 | reg |= (1 << 28); | |
887 | ew32(TARC1, reg); | |
888 | break; | |
889 | default: | |
890 | break; | |
891 | } | |
892 | ||
893 | /* Device Control */ | |
894 | if (hw->mac.type == e1000_82573) { | |
895 | reg = er32(CTRL); | |
896 | reg &= ~(1 << 29); | |
897 | ew32(CTRL, reg); | |
898 | } | |
899 | ||
900 | /* Extended Device Control */ | |
901 | if (hw->mac.type == e1000_82573) { | |
902 | reg = er32(CTRL_EXT); | |
903 | reg &= ~(1 << 23); | |
904 | reg |= (1 << 22); | |
905 | ew32(CTRL_EXT, reg); | |
906 | } | |
907 | } | |
908 | ||
909 | /** | |
910 | * e1000e_clear_vfta - Clear VLAN filter table | |
911 | * @hw: pointer to the HW structure | |
912 | * | |
913 | * Clears the register array which contains the VLAN filter table by | |
914 | * setting all the values to 0. | |
915 | **/ | |
916 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
917 | { | |
918 | u32 offset; | |
919 | u32 vfta_value = 0; | |
920 | u32 vfta_offset = 0; | |
921 | u32 vfta_bit_in_reg = 0; | |
922 | ||
923 | if (hw->mac.type == e1000_82573) { | |
924 | if (hw->mng_cookie.vlan_id != 0) { | |
925 | /* The VFTA is a 4096b bit-field, each identifying | |
926 | * a single VLAN ID. The following operations | |
927 | * determine which 32b entry (i.e. offset) into the | |
928 | * array we want to set the VLAN ID (i.e. bit) of | |
929 | * the manageability unit. | |
930 | */ | |
931 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
932 | E1000_VFTA_ENTRY_SHIFT) & | |
933 | E1000_VFTA_ENTRY_MASK; | |
934 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
935 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
936 | } | |
937 | } | |
938 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
939 | /* If the offset we want to clear is the same offset of the | |
940 | * manageability VLAN ID, then clear all bits except that of | |
941 | * the manageability unit. | |
942 | */ | |
943 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
944 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
945 | e1e_flush(); | |
946 | } | |
947 | } | |
948 | ||
949 | /** | |
950 | * e1000_mc_addr_list_update_82571 - Update Multicast addresses | |
951 | * @hw: pointer to the HW structure | |
952 | * @mc_addr_list: array of multicast addresses to program | |
953 | * @mc_addr_count: number of multicast addresses to program | |
954 | * @rar_used_count: the first RAR register free to program | |
955 | * @rar_count: total number of supported Receive Address Registers | |
956 | * | |
957 | * Updates the Receive Address Registers and Multicast Table Array. | |
958 | * The caller must have a packed mc_addr_list of multicast addresses. | |
959 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
960 | * unless there are workarounds that change this. | |
961 | **/ | |
962 | static void e1000_mc_addr_list_update_82571(struct e1000_hw *hw, | |
963 | u8 *mc_addr_list, | |
964 | u32 mc_addr_count, | |
965 | u32 rar_used_count, | |
966 | u32 rar_count) | |
967 | { | |
968 | if (e1000e_get_laa_state_82571(hw)) | |
969 | rar_count--; | |
970 | ||
971 | e1000e_mc_addr_list_update_generic(hw, mc_addr_list, mc_addr_count, | |
972 | rar_used_count, rar_count); | |
973 | } | |
974 | ||
975 | /** | |
976 | * e1000_setup_link_82571 - Setup flow control and link settings | |
977 | * @hw: pointer to the HW structure | |
978 | * | |
979 | * Determines which flow control settings to use, then configures flow | |
980 | * control. Calls the appropriate media-specific link configuration | |
981 | * function. Assuming the adapter has a valid link partner, a valid link | |
982 | * should be established. Assumes the hardware has previously been reset | |
983 | * and the transmitter and receiver are not enabled. | |
984 | **/ | |
985 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
986 | { | |
987 | /* 82573 does not have a word in the NVM to determine | |
988 | * the default flow control setting, so we explicitly | |
989 | * set it to full. | |
990 | */ | |
991 | if (hw->mac.type == e1000_82573) | |
992 | hw->mac.fc = e1000_fc_full; | |
993 | ||
994 | return e1000e_setup_link(hw); | |
995 | } | |
996 | ||
997 | /** | |
998 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
999 | * @hw: pointer to the HW structure | |
1000 | * | |
1001 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1002 | * for link, once link is established calls to configure collision distance | |
1003 | * and flow control are called. | |
1004 | **/ | |
1005 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1006 | { | |
1007 | u32 ctrl; | |
1008 | u32 led_ctrl; | |
1009 | s32 ret_val; | |
1010 | ||
1011 | ctrl = er32(CTRL); | |
1012 | ctrl |= E1000_CTRL_SLU; | |
1013 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1014 | ew32(CTRL, ctrl); | |
1015 | ||
1016 | switch (hw->phy.type) { | |
1017 | case e1000_phy_m88: | |
1018 | ret_val = e1000e_copper_link_setup_m88(hw); | |
1019 | break; | |
1020 | case e1000_phy_igp_2: | |
1021 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1022 | /* Setup activity LED */ | |
1023 | led_ctrl = er32(LEDCTL); | |
1024 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1025 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1026 | ew32(LEDCTL, led_ctrl); | |
1027 | break; | |
1028 | default: | |
1029 | return -E1000_ERR_PHY; | |
1030 | break; | |
1031 | } | |
1032 | ||
1033 | if (ret_val) | |
1034 | return ret_val; | |
1035 | ||
1036 | ret_val = e1000e_setup_copper_link(hw); | |
1037 | ||
1038 | return ret_val; | |
1039 | } | |
1040 | ||
1041 | /** | |
1042 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1043 | * @hw: pointer to the HW structure | |
1044 | * | |
1045 | * Configures collision distance and flow control for fiber and serdes links. | |
1046 | * Upon successful setup, poll for link. | |
1047 | **/ | |
1048 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1049 | { | |
1050 | switch (hw->mac.type) { | |
1051 | case e1000_82571: | |
1052 | case e1000_82572: | |
1053 | /* If SerDes loopback mode is entered, there is no form | |
1054 | * of reset to take the adapter out of that mode. So we | |
1055 | * have to explicitly take the adapter out of loopback | |
1056 | * mode. This prevents drivers from twidling their thumbs | |
1057 | * if another tool failed to take it out of loopback mode. | |
1058 | */ | |
1059 | ew32(SCTL, | |
1060 | E1000_SCTL_DISABLE_SERDES_LOOPBACK); | |
1061 | break; | |
1062 | default: | |
1063 | break; | |
1064 | } | |
1065 | ||
1066 | return e1000e_setup_fiber_serdes_link(hw); | |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1071 | * @hw: pointer to the HW structure | |
1072 | * @data: pointer to the NVM (EEPROM) | |
1073 | * | |
1074 | * Read the EEPROM for the current default LED configuration. If the | |
1075 | * LED configuration is not valid, set to a valid LED configuration. | |
1076 | **/ | |
1077 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1078 | { | |
1079 | s32 ret_val; | |
1080 | ||
1081 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1082 | if (ret_val) { | |
1083 | hw_dbg(hw, "NVM Read Error\n"); | |
1084 | return ret_val; | |
1085 | } | |
1086 | ||
1087 | if (hw->mac.type == e1000_82573 && | |
1088 | *data == ID_LED_RESERVED_F746) | |
1089 | *data = ID_LED_DEFAULT_82573; | |
1090 | else if (*data == ID_LED_RESERVED_0000 || | |
1091 | *data == ID_LED_RESERVED_FFFF) | |
1092 | *data = ID_LED_DEFAULT; | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1099 | * @hw: pointer to the HW structure | |
1100 | * | |
1101 | * Retrieve and return the current locally administed address state. | |
1102 | **/ | |
1103 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1104 | { | |
1105 | if (hw->mac.type != e1000_82571) | |
1106 | return 0; | |
1107 | ||
1108 | return hw->dev_spec.e82571.laa_is_present; | |
1109 | } | |
1110 | ||
1111 | /** | |
1112 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1113 | * @hw: pointer to the HW structure | |
1114 | * @state: enable/disable locally administered address | |
1115 | * | |
1116 | * Enable/Disable the current locally administed address state. | |
1117 | **/ | |
1118 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1119 | { | |
1120 | if (hw->mac.type != e1000_82571) | |
1121 | return; | |
1122 | ||
1123 | hw->dev_spec.e82571.laa_is_present = state; | |
1124 | ||
1125 | /* If workaround is activated... */ | |
1126 | if (state) | |
1127 | /* Hold a copy of the LAA in RAR[14] This is done so that | |
1128 | * between the time RAR[0] gets clobbered and the time it | |
1129 | * gets fixed, the actual LAA is in one of the RARs and no | |
1130 | * incoming packets directed to this port are dropped. | |
1131 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1132 | */ | |
1133 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1134 | } | |
1135 | ||
1136 | /** | |
1137 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1138 | * @hw: pointer to the HW structure | |
1139 | * | |
1140 | * Verifies that the EEPROM has completed the update. After updating the | |
1141 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1142 | * the checksum fix is not implemented, we need to set the bit and update | |
1143 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1144 | * we need to return bad checksum. | |
1145 | **/ | |
1146 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1147 | { | |
1148 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1149 | s32 ret_val; | |
1150 | u16 data; | |
1151 | ||
1152 | if (nvm->type != e1000_nvm_flash_hw) | |
1153 | return 0; | |
1154 | ||
1155 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | |
1156 | * 10h-12h. Checksum may need to be fixed. | |
1157 | */ | |
1158 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1159 | if (ret_val) | |
1160 | return ret_val; | |
1161 | ||
1162 | if (!(data & 0x10)) { | |
1163 | /* Read 0x23 and check bit 15. This bit is a 1 | |
1164 | * when the checksum has already been fixed. If | |
1165 | * the checksum is still wrong and this bit is a | |
1166 | * 1, we need to return bad checksum. Otherwise, | |
1167 | * we need to set this bit to a 1 and update the | |
1168 | * checksum. | |
1169 | */ | |
1170 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1171 | if (ret_val) | |
1172 | return ret_val; | |
1173 | ||
1174 | if (!(data & 0x8000)) { | |
1175 | data |= 0x8000; | |
1176 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1177 | if (ret_val) | |
1178 | return ret_val; | |
1179 | ret_val = e1000e_update_nvm_checksum(hw); | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1188 | * @hw: pointer to the HW structure | |
1189 | * | |
1190 | * Clears the hardware counters by reading the counter registers. | |
1191 | **/ | |
1192 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1193 | { | |
1194 | u32 temp; | |
1195 | ||
1196 | e1000e_clear_hw_cntrs_base(hw); | |
1197 | ||
1198 | temp = er32(PRC64); | |
1199 | temp = er32(PRC127); | |
1200 | temp = er32(PRC255); | |
1201 | temp = er32(PRC511); | |
1202 | temp = er32(PRC1023); | |
1203 | temp = er32(PRC1522); | |
1204 | temp = er32(PTC64); | |
1205 | temp = er32(PTC127); | |
1206 | temp = er32(PTC255); | |
1207 | temp = er32(PTC511); | |
1208 | temp = er32(PTC1023); | |
1209 | temp = er32(PTC1522); | |
1210 | ||
1211 | temp = er32(ALGNERRC); | |
1212 | temp = er32(RXERRC); | |
1213 | temp = er32(TNCRS); | |
1214 | temp = er32(CEXTERR); | |
1215 | temp = er32(TSCTC); | |
1216 | temp = er32(TSCTFC); | |
1217 | ||
1218 | temp = er32(MGTPRC); | |
1219 | temp = er32(MGTPDC); | |
1220 | temp = er32(MGTPTC); | |
1221 | ||
1222 | temp = er32(IAC); | |
1223 | temp = er32(ICRXOC); | |
1224 | ||
1225 | temp = er32(ICRXPTC); | |
1226 | temp = er32(ICRXATC); | |
1227 | temp = er32(ICTXPTC); | |
1228 | temp = er32(ICTXATC); | |
1229 | temp = er32(ICTXQEC); | |
1230 | temp = er32(ICTXQMTC); | |
1231 | temp = er32(ICRXDMTC); | |
1232 | } | |
1233 | ||
1234 | static struct e1000_mac_operations e82571_mac_ops = { | |
1235 | .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, | |
1236 | /* .check_for_link: media type dependent */ | |
1237 | .cleanup_led = e1000e_cleanup_led_generic, | |
1238 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1239 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1240 | /* .get_link_up_info: media type dependent */ | |
1241 | .led_on = e1000e_led_on_generic, | |
1242 | .led_off = e1000e_led_off_generic, | |
1243 | .mc_addr_list_update = e1000_mc_addr_list_update_82571, | |
1244 | .reset_hw = e1000_reset_hw_82571, | |
1245 | .init_hw = e1000_init_hw_82571, | |
1246 | .setup_link = e1000_setup_link_82571, | |
1247 | /* .setup_physical_interface: media type dependent */ | |
1248 | }; | |
1249 | ||
1250 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
1251 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1252 | .check_reset_block = e1000e_check_reset_block_generic, | |
1253 | .commit_phy = NULL, | |
1254 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, | |
1255 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1256 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
1257 | .get_phy_info = e1000e_get_phy_info_igp, | |
1258 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
1259 | .release_phy = e1000_put_hw_semaphore_82571, | |
1260 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1261 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1262 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1263 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
1264 | }; | |
1265 | ||
1266 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
1267 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1268 | .check_reset_block = e1000e_check_reset_block_generic, | |
1269 | .commit_phy = e1000e_phy_sw_reset, | |
1270 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1271 | .get_cfg_done = e1000e_get_cfg_done, | |
1272 | .get_cable_length = e1000e_get_cable_length_m88, | |
1273 | .get_phy_info = e1000e_get_phy_info_m88, | |
1274 | .read_phy_reg = e1000e_read_phy_reg_m88, | |
1275 | .release_phy = e1000_put_hw_semaphore_82571, | |
1276 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1277 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1278 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1279 | .write_phy_reg = e1000e_write_phy_reg_m88, | |
1280 | }; | |
1281 | ||
1282 | static struct e1000_nvm_operations e82571_nvm_ops = { | |
1283 | .acquire_nvm = e1000_acquire_nvm_82571, | |
1284 | .read_nvm = e1000e_read_nvm_spi, | |
1285 | .release_nvm = e1000_release_nvm_82571, | |
1286 | .update_nvm = e1000_update_nvm_checksum_82571, | |
1287 | .valid_led_default = e1000_valid_led_default_82571, | |
1288 | .validate_nvm = e1000_validate_nvm_checksum_82571, | |
1289 | .write_nvm = e1000_write_nvm_82571, | |
1290 | }; | |
1291 | ||
1292 | static struct e1000_nvm_operations e82573_nvm_ops = { | |
1293 | .acquire_nvm = e1000_acquire_nvm_82571, | |
1294 | .read_nvm = e1000e_read_nvm_eerd, | |
1295 | .release_nvm = e1000_release_nvm_82571, | |
1296 | .update_nvm = e1000_update_nvm_checksum_82571, | |
1297 | .valid_led_default = e1000_valid_led_default_82571, | |
1298 | .validate_nvm = e1000_validate_nvm_checksum_82571, | |
1299 | .write_nvm = e1000_write_nvm_82571, | |
1300 | }; | |
1301 | ||
1302 | struct e1000_info e1000_82571_info = { | |
1303 | .mac = e1000_82571, | |
1304 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1305 | | FLAG_HAS_JUMBO_FRAMES | |
1306 | | FLAG_HAS_STATS_PTC_PRC | |
1307 | | FLAG_HAS_WOL | |
1308 | | FLAG_APME_IN_CTRL3 | |
1309 | | FLAG_RX_CSUM_ENABLED | |
1310 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
1311 | | FLAG_HAS_STATS_ICR_ICT | |
1312 | | FLAG_HAS_SMART_POWER_DOWN | |
1313 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1314 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1315 | | FLAG_APME_CHECK_PORT_B, | |
1316 | .pba = 38, | |
1317 | .get_invariants = e1000_get_invariants_82571, | |
1318 | .mac_ops = &e82571_mac_ops, | |
1319 | .phy_ops = &e82_phy_ops_igp, | |
1320 | .nvm_ops = &e82571_nvm_ops, | |
1321 | }; | |
1322 | ||
1323 | struct e1000_info e1000_82572_info = { | |
1324 | .mac = e1000_82572, | |
1325 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1326 | | FLAG_HAS_JUMBO_FRAMES | |
1327 | | FLAG_HAS_STATS_PTC_PRC | |
1328 | | FLAG_HAS_WOL | |
1329 | | FLAG_APME_IN_CTRL3 | |
1330 | | FLAG_RX_CSUM_ENABLED | |
1331 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
1332 | | FLAG_HAS_STATS_ICR_ICT | |
1333 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ | |
1334 | .pba = 38, | |
1335 | .get_invariants = e1000_get_invariants_82571, | |
1336 | .mac_ops = &e82571_mac_ops, | |
1337 | .phy_ops = &e82_phy_ops_igp, | |
1338 | .nvm_ops = &e82571_nvm_ops, | |
1339 | }; | |
1340 | ||
1341 | struct e1000_info e1000_82573_info = { | |
1342 | .mac = e1000_82573, | |
1343 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1344 | | FLAG_HAS_JUMBO_FRAMES | |
1345 | | FLAG_HAS_STATS_PTC_PRC | |
1346 | | FLAG_HAS_WOL | |
1347 | | FLAG_APME_IN_CTRL3 | |
1348 | | FLAG_RX_CSUM_ENABLED | |
1349 | | FLAG_HAS_STATS_ICR_ICT | |
1350 | | FLAG_HAS_SMART_POWER_DOWN | |
1351 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1352 | | FLAG_HAS_ERT |
1353 | | FLAG_HAS_SWSM_ON_LOAD, | |
1354 | .pba = 20, | |
1355 | .get_invariants = e1000_get_invariants_82571, | |
1356 | .mac_ops = &e82571_mac_ops, | |
1357 | .phy_ops = &e82_phy_ops_m88, | |
1358 | .nvm_ops = &e82573_nvm_ops, | |
1359 | }; | |
1360 |