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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
31 | * 82571EB Gigabit Ethernet Controller (Fiber) | |
ad68076e BA |
32 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
33 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
34 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
35 | * 82572EI Gigabit Ethernet Controller (Copper) |
36 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
37 | * 82572EI Gigabit Ethernet Controller | |
38 | * 82573V Gigabit Ethernet Controller (Copper) | |
39 | * 82573E Gigabit Ethernet Controller (Copper) | |
40 | * 82573L Gigabit Ethernet Controller | |
41 | */ | |
42 | ||
43 | #include <linux/netdevice.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/pci.h> | |
46 | ||
47 | #include "e1000.h" | |
48 | ||
49 | #define ID_LED_RESERVED_F746 0xF746 | |
50 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
51 | (ID_LED_OFF1_ON2 << 8) | \ | |
52 | (ID_LED_DEF1_DEF2 << 4) | \ | |
53 | (ID_LED_DEF1_DEF2)) | |
54 | ||
55 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
56 | ||
57 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); | |
58 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
59 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
60 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
61 | u16 words, u16 *data); | |
62 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
63 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
64 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
65 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
66 | ||
67 | /** | |
68 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
69 | * @hw: pointer to the HW structure | |
70 | * | |
71 | * This is a function pointer entry point called by the api module. | |
72 | **/ | |
73 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
74 | { | |
75 | struct e1000_phy_info *phy = &hw->phy; | |
76 | s32 ret_val; | |
77 | ||
318a94d6 | 78 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
79 | phy->type = e1000_phy_none; |
80 | return 0; | |
81 | } | |
82 | ||
83 | phy->addr = 1; | |
84 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
85 | phy->reset_delay_us = 100; | |
86 | ||
87 | switch (hw->mac.type) { | |
88 | case e1000_82571: | |
89 | case e1000_82572: | |
90 | phy->type = e1000_phy_igp_2; | |
91 | break; | |
92 | case e1000_82573: | |
93 | phy->type = e1000_phy_m88; | |
94 | break; | |
95 | default: | |
96 | return -E1000_ERR_PHY; | |
97 | break; | |
98 | } | |
99 | ||
100 | /* This can only be done after all function pointers are setup. */ | |
101 | ret_val = e1000_get_phy_id_82571(hw); | |
102 | ||
103 | /* Verify phy id */ | |
104 | switch (hw->mac.type) { | |
105 | case e1000_82571: | |
106 | case e1000_82572: | |
107 | if (phy->id != IGP01E1000_I_PHY_ID) | |
108 | return -E1000_ERR_PHY; | |
109 | break; | |
110 | case e1000_82573: | |
111 | if (phy->id != M88E1111_I_PHY_ID) | |
112 | return -E1000_ERR_PHY; | |
113 | break; | |
114 | default: | |
115 | return -E1000_ERR_PHY; | |
116 | break; | |
117 | } | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | /** | |
123 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
124 | * @hw: pointer to the HW structure | |
125 | * | |
126 | * This is a function pointer entry point called by the api module. | |
127 | **/ | |
128 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
129 | { | |
130 | struct e1000_nvm_info *nvm = &hw->nvm; | |
131 | u32 eecd = er32(EECD); | |
132 | u16 size; | |
133 | ||
134 | nvm->opcode_bits = 8; | |
135 | nvm->delay_usec = 1; | |
136 | switch (nvm->override) { | |
137 | case e1000_nvm_override_spi_large: | |
138 | nvm->page_size = 32; | |
139 | nvm->address_bits = 16; | |
140 | break; | |
141 | case e1000_nvm_override_spi_small: | |
142 | nvm->page_size = 8; | |
143 | nvm->address_bits = 8; | |
144 | break; | |
145 | default: | |
146 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
147 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
148 | break; | |
149 | } | |
150 | ||
151 | switch (hw->mac.type) { | |
152 | case e1000_82573: | |
153 | if (((eecd >> 15) & 0x3) == 0x3) { | |
154 | nvm->type = e1000_nvm_flash_hw; | |
155 | nvm->word_size = 2048; | |
ad68076e BA |
156 | /* |
157 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
158 | * to Flash update issue. |
159 | */ | |
160 | eecd &= ~E1000_EECD_AUPDEN; | |
161 | ew32(EECD, eecd); | |
162 | break; | |
163 | } | |
164 | /* Fall Through */ | |
165 | default: | |
ad68076e | 166 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
167 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
168 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
169 | /* |
170 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
171 | * for setting word_size. |
172 | */ | |
173 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
174 | |
175 | /* EEPROM access above 16k is unsupported */ | |
176 | if (size > 14) | |
177 | size = 14; | |
bc7f75fa AK |
178 | nvm->word_size = 1 << size; |
179 | break; | |
180 | } | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | /** | |
186 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
187 | * @hw: pointer to the HW structure | |
188 | * | |
189 | * This is a function pointer entry point called by the api module. | |
190 | **/ | |
191 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
192 | { | |
193 | struct e1000_hw *hw = &adapter->hw; | |
194 | struct e1000_mac_info *mac = &hw->mac; | |
195 | struct e1000_mac_operations *func = &mac->ops; | |
196 | ||
197 | /* Set media type */ | |
198 | switch (adapter->pdev->device) { | |
199 | case E1000_DEV_ID_82571EB_FIBER: | |
200 | case E1000_DEV_ID_82572EI_FIBER: | |
201 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 202 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
203 | break; |
204 | case E1000_DEV_ID_82571EB_SERDES: | |
205 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
206 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
207 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 208 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
209 | break; |
210 | default: | |
318a94d6 | 211 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
212 | break; |
213 | } | |
214 | ||
215 | /* Set mta register count */ | |
216 | mac->mta_reg_count = 128; | |
217 | /* Set rar entry count */ | |
218 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
219 | /* Set if manageability features are enabled. */ | |
ad68076e | 220 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
bc7f75fa AK |
221 | |
222 | /* check for link */ | |
318a94d6 | 223 | switch (hw->phy.media_type) { |
bc7f75fa AK |
224 | case e1000_media_type_copper: |
225 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
226 | func->check_for_link = e1000e_check_for_copper_link; | |
227 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
228 | break; | |
229 | case e1000_media_type_fiber: | |
ad68076e BA |
230 | func->setup_physical_interface = |
231 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 232 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
233 | func->get_link_up_info = |
234 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
235 | break; |
236 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
237 | func->setup_physical_interface = |
238 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 239 | func->check_for_link = e1000e_check_for_serdes_link; |
ad68076e BA |
240 | func->get_link_up_info = |
241 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
242 | break; |
243 | default: | |
244 | return -E1000_ERR_CONFIG; | |
245 | break; | |
246 | } | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | static s32 e1000_get_invariants_82571(struct e1000_adapter *adapter) | |
252 | { | |
253 | struct e1000_hw *hw = &adapter->hw; | |
254 | static int global_quad_port_a; /* global port a indication */ | |
255 | struct pci_dev *pdev = adapter->pdev; | |
256 | u16 eeprom_data = 0; | |
257 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
258 | s32 rc; | |
259 | ||
260 | rc = e1000_init_mac_params_82571(adapter); | |
261 | if (rc) | |
262 | return rc; | |
263 | ||
264 | rc = e1000_init_nvm_params_82571(hw); | |
265 | if (rc) | |
266 | return rc; | |
267 | ||
268 | rc = e1000_init_phy_params_82571(hw); | |
269 | if (rc) | |
270 | return rc; | |
271 | ||
272 | /* tag quad port adapters first, it's used below */ | |
273 | switch (pdev->device) { | |
274 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
275 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
276 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 277 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
278 | adapter->flags |= FLAG_IS_QUAD_PORT; |
279 | /* mark the first port */ | |
280 | if (global_quad_port_a == 0) | |
281 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
282 | /* Reset for multiple quad port adapters */ | |
283 | global_quad_port_a++; | |
284 | if (global_quad_port_a == 4) | |
285 | global_quad_port_a = 0; | |
286 | break; | |
287 | default: | |
288 | break; | |
289 | } | |
290 | ||
291 | switch (adapter->hw.mac.type) { | |
292 | case e1000_82571: | |
293 | /* these dual ports don't have WoL on port B at all */ | |
294 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
295 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
296 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
297 | (is_port_b)) | |
298 | adapter->flags &= ~FLAG_HAS_WOL; | |
299 | /* quad ports only support WoL on port A */ | |
300 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 301 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 302 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
303 | /* Does not support WoL on any port */ |
304 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
305 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
306 | break; |
307 | ||
308 | case e1000_82573: | |
309 | if (pdev->device == E1000_DEV_ID_82573L) { | |
310 | e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, | |
311 | &eeprom_data); | |
312 | if (eeprom_data & NVM_WORD1A_ASPM_MASK) | |
313 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
314 | } | |
315 | break; | |
316 | default: | |
317 | break; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | /** | |
324 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
325 | * @hw: pointer to the HW structure | |
326 | * | |
327 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
328 | * revision in the hardware structure. | |
329 | **/ | |
330 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
331 | { | |
332 | struct e1000_phy_info *phy = &hw->phy; | |
333 | ||
334 | switch (hw->mac.type) { | |
335 | case e1000_82571: | |
336 | case e1000_82572: | |
ad68076e BA |
337 | /* |
338 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
339 | * In this case, we cannot access the PHY until the |
340 | * configuration is done. So we explicitly set the | |
ad68076e BA |
341 | * PHY ID. |
342 | */ | |
bc7f75fa AK |
343 | phy->id = IGP01E1000_I_PHY_ID; |
344 | break; | |
345 | case e1000_82573: | |
346 | return e1000e_get_phy_id(hw); | |
347 | break; | |
348 | default: | |
349 | return -E1000_ERR_PHY; | |
350 | break; | |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | /** | |
357 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
358 | * @hw: pointer to the HW structure | |
359 | * | |
360 | * Acquire the HW semaphore to access the PHY or NVM | |
361 | **/ | |
362 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
363 | { | |
364 | u32 swsm; | |
365 | s32 timeout = hw->nvm.word_size + 1; | |
366 | s32 i = 0; | |
367 | ||
368 | /* Get the FW semaphore. */ | |
369 | for (i = 0; i < timeout; i++) { | |
370 | swsm = er32(SWSM); | |
371 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
372 | ||
373 | /* Semaphore acquired if bit latched */ | |
374 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
375 | break; | |
376 | ||
377 | udelay(50); | |
378 | } | |
379 | ||
380 | if (i == timeout) { | |
381 | /* Release semaphores */ | |
382 | e1000e_put_hw_semaphore(hw); | |
383 | hw_dbg(hw, "Driver can't access the NVM\n"); | |
384 | return -E1000_ERR_NVM; | |
385 | } | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | /** | |
391 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
392 | * @hw: pointer to the HW structure | |
393 | * | |
394 | * Release hardware semaphore used to access the PHY or NVM | |
395 | **/ | |
396 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
397 | { | |
398 | u32 swsm; | |
399 | ||
400 | swsm = er32(SWSM); | |
401 | ||
402 | swsm &= ~E1000_SWSM_SWESMBI; | |
403 | ||
404 | ew32(SWSM, swsm); | |
405 | } | |
406 | ||
407 | /** | |
408 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
409 | * @hw: pointer to the HW structure | |
410 | * | |
411 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
412 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
413 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
414 | * hardware semaphore. | |
415 | **/ | |
416 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
417 | { | |
418 | s32 ret_val; | |
419 | ||
420 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
421 | if (ret_val) | |
422 | return ret_val; | |
423 | ||
424 | if (hw->mac.type != e1000_82573) | |
425 | ret_val = e1000e_acquire_nvm(hw); | |
426 | ||
427 | if (ret_val) | |
428 | e1000_put_hw_semaphore_82571(hw); | |
429 | ||
430 | return ret_val; | |
431 | } | |
432 | ||
433 | /** | |
434 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
435 | * @hw: pointer to the HW structure | |
436 | * | |
437 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
438 | **/ | |
439 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
440 | { | |
441 | e1000e_release_nvm(hw); | |
442 | e1000_put_hw_semaphore_82571(hw); | |
443 | } | |
444 | ||
445 | /** | |
446 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
447 | * @hw: pointer to the HW structure | |
448 | * @offset: offset within the EEPROM to be written to | |
449 | * @words: number of words to write | |
450 | * @data: 16 bit word(s) to be written to the EEPROM | |
451 | * | |
452 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
453 | * | |
454 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 455 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
456 | **/ |
457 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
458 | u16 *data) | |
459 | { | |
460 | s32 ret_val; | |
461 | ||
462 | switch (hw->mac.type) { | |
463 | case e1000_82573: | |
464 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); | |
465 | break; | |
466 | case e1000_82571: | |
467 | case e1000_82572: | |
468 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
469 | break; | |
470 | default: | |
471 | ret_val = -E1000_ERR_NVM; | |
472 | break; | |
473 | } | |
474 | ||
475 | return ret_val; | |
476 | } | |
477 | ||
478 | /** | |
479 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
480 | * @hw: pointer to the HW structure | |
481 | * | |
482 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
483 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
484 | * value to the EEPROM. | |
485 | **/ | |
486 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
487 | { | |
488 | u32 eecd; | |
489 | s32 ret_val; | |
490 | u16 i; | |
491 | ||
492 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
493 | if (ret_val) | |
494 | return ret_val; | |
495 | ||
ad68076e BA |
496 | /* |
497 | * If our nvm is an EEPROM, then we're done | |
498 | * otherwise, commit the checksum to the flash NVM. | |
499 | */ | |
bc7f75fa AK |
500 | if (hw->nvm.type != e1000_nvm_flash_hw) |
501 | return ret_val; | |
502 | ||
503 | /* Check for pending operations. */ | |
504 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
505 | msleep(1); | |
506 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
507 | break; | |
508 | } | |
509 | ||
510 | if (i == E1000_FLASH_UPDATES) | |
511 | return -E1000_ERR_NVM; | |
512 | ||
513 | /* Reset the firmware if using STM opcode. */ | |
514 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
515 | /* |
516 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
517 | * in two write cycles. |
518 | */ | |
519 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
520 | e1e_flush(); | |
521 | ew32(HICR, E1000_HICR_FW_RESET); | |
522 | } | |
523 | ||
524 | /* Commit the write to flash */ | |
525 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
526 | ew32(EECD, eecd); | |
527 | ||
528 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
529 | msleep(1); | |
530 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
531 | break; | |
532 | } | |
533 | ||
534 | if (i == E1000_FLASH_UPDATES) | |
535 | return -E1000_ERR_NVM; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | /** | |
541 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
542 | * @hw: pointer to the HW structure | |
543 | * | |
544 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
545 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
546 | **/ | |
547 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
548 | { | |
549 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
550 | e1000_fix_nvm_checksum_82571(hw); | |
551 | ||
552 | return e1000e_validate_nvm_checksum_generic(hw); | |
553 | } | |
554 | ||
555 | /** | |
556 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
557 | * @hw: pointer to the HW structure | |
558 | * @offset: offset within the EEPROM to be written to | |
559 | * @words: number of words to write | |
560 | * @data: 16 bit word(s) to be written to the EEPROM | |
561 | * | |
562 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
563 | * command has completed before trying to write the next word. After write | |
564 | * poll for completion. | |
565 | * | |
566 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 567 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
568 | **/ |
569 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
570 | u16 words, u16 *data) | |
571 | { | |
572 | struct e1000_nvm_info *nvm = &hw->nvm; | |
573 | u32 i; | |
574 | u32 eewr = 0; | |
575 | s32 ret_val = 0; | |
576 | ||
ad68076e BA |
577 | /* |
578 | * A check for invalid values: offset too large, too many words, | |
579 | * and not enough words. | |
580 | */ | |
bc7f75fa AK |
581 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
582 | (words == 0)) { | |
583 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
584 | return -E1000_ERR_NVM; | |
585 | } | |
586 | ||
587 | for (i = 0; i < words; i++) { | |
588 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
589 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
590 | E1000_NVM_RW_REG_START; | |
591 | ||
592 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
593 | if (ret_val) | |
594 | break; | |
595 | ||
596 | ew32(EEWR, eewr); | |
597 | ||
598 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
599 | if (ret_val) | |
600 | break; | |
601 | } | |
602 | ||
603 | return ret_val; | |
604 | } | |
605 | ||
606 | /** | |
607 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
608 | * @hw: pointer to the HW structure | |
609 | * | |
610 | * Reads the management control register for the config done bit to be set. | |
611 | **/ | |
612 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
613 | { | |
614 | s32 timeout = PHY_CFG_TIMEOUT; | |
615 | ||
616 | while (timeout) { | |
617 | if (er32(EEMNGCTL) & | |
618 | E1000_NVM_CFG_DONE_PORT_0) | |
619 | break; | |
620 | msleep(1); | |
621 | timeout--; | |
622 | } | |
623 | if (!timeout) { | |
624 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
625 | return -E1000_ERR_RESET; | |
626 | } | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | /** | |
632 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
633 | * @hw: pointer to the HW structure | |
634 | * @active: TRUE to enable LPLU, FALSE to disable | |
635 | * | |
636 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
637 | * this function also disables smart speed and vice versa. LPLU will not be | |
638 | * activated unless the device autonegotiation advertisement meets standards | |
639 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
640 | * pointer entry point only called by PHY setup routines. | |
641 | **/ | |
642 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
643 | { | |
644 | struct e1000_phy_info *phy = &hw->phy; | |
645 | s32 ret_val; | |
646 | u16 data; | |
647 | ||
648 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
649 | if (ret_val) | |
650 | return ret_val; | |
651 | ||
652 | if (active) { | |
653 | data |= IGP02E1000_PM_D0_LPLU; | |
654 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
655 | if (ret_val) | |
656 | return ret_val; | |
657 | ||
658 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
659 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
660 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
661 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
662 | if (ret_val) | |
663 | return ret_val; | |
664 | } else { | |
665 | data &= ~IGP02E1000_PM_D0_LPLU; | |
666 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
667 | /* |
668 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
669 | * during Dx states where the power conservation is most |
670 | * important. During driver activity we should enable | |
ad68076e BA |
671 | * SmartSpeed, so performance is maintained. |
672 | */ | |
bc7f75fa AK |
673 | if (phy->smart_speed == e1000_smart_speed_on) { |
674 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 675 | &data); |
bc7f75fa AK |
676 | if (ret_val) |
677 | return ret_val; | |
678 | ||
679 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
680 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 681 | data); |
bc7f75fa AK |
682 | if (ret_val) |
683 | return ret_val; | |
684 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
685 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 686 | &data); |
bc7f75fa AK |
687 | if (ret_val) |
688 | return ret_val; | |
689 | ||
690 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
691 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 692 | data); |
bc7f75fa AK |
693 | if (ret_val) |
694 | return ret_val; | |
695 | } | |
696 | } | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | /** | |
702 | * e1000_reset_hw_82571 - Reset hardware | |
703 | * @hw: pointer to the HW structure | |
704 | * | |
705 | * This resets the hardware into a known state. This is a | |
706 | * function pointer entry point called by the api module. | |
707 | **/ | |
708 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
709 | { | |
710 | u32 ctrl; | |
711 | u32 extcnf_ctrl; | |
712 | u32 ctrl_ext; | |
713 | u32 icr; | |
714 | s32 ret_val; | |
715 | u16 i = 0; | |
716 | ||
ad68076e BA |
717 | /* |
718 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
719 | * on the last TLP read/write transaction when MAC is reset. |
720 | */ | |
721 | ret_val = e1000e_disable_pcie_master(hw); | |
722 | if (ret_val) | |
723 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
724 | ||
725 | hw_dbg(hw, "Masking off all interrupts\n"); | |
726 | ew32(IMC, 0xffffffff); | |
727 | ||
728 | ew32(RCTL, 0); | |
729 | ew32(TCTL, E1000_TCTL_PSP); | |
730 | e1e_flush(); | |
731 | ||
732 | msleep(10); | |
733 | ||
ad68076e BA |
734 | /* |
735 | * Must acquire the MDIO ownership before MAC reset. | |
736 | * Ownership defaults to firmware after a reset. | |
737 | */ | |
bc7f75fa AK |
738 | if (hw->mac.type == e1000_82573) { |
739 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
740 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
741 | ||
742 | do { | |
743 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
744 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
745 | ||
746 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
747 | break; | |
748 | ||
749 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
750 | ||
751 | msleep(2); | |
752 | i++; | |
753 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
754 | } | |
755 | ||
756 | ctrl = er32(CTRL); | |
757 | ||
758 | hw_dbg(hw, "Issuing a global reset to MAC\n"); | |
759 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
760 | ||
761 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
762 | udelay(10); | |
763 | ctrl_ext = er32(CTRL_EXT); | |
764 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
765 | ew32(CTRL_EXT, ctrl_ext); | |
766 | e1e_flush(); | |
767 | } | |
768 | ||
769 | ret_val = e1000e_get_auto_rd_done(hw); | |
770 | if (ret_val) | |
771 | /* We don't want to continue accessing MAC registers. */ | |
772 | return ret_val; | |
773 | ||
ad68076e BA |
774 | /* |
775 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
776 | * Need to wait for Phy configuration completion before accessing |
777 | * NVM and Phy. | |
778 | */ | |
779 | if (hw->mac.type == e1000_82573) | |
780 | msleep(25); | |
781 | ||
782 | /* Clear any pending interrupt events. */ | |
783 | ew32(IMC, 0xffffffff); | |
784 | icr = er32(ICR); | |
785 | ||
93ca1610 BH |
786 | if (hw->mac.type == e1000_82571 && |
787 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
788 | e1000e_set_laa_state_82571(hw, true); | |
789 | ||
bc7f75fa AK |
790 | return 0; |
791 | } | |
792 | ||
793 | /** | |
794 | * e1000_init_hw_82571 - Initialize hardware | |
795 | * @hw: pointer to the HW structure | |
796 | * | |
797 | * This inits the hardware readying it for operation. | |
798 | **/ | |
799 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
800 | { | |
801 | struct e1000_mac_info *mac = &hw->mac; | |
802 | u32 reg_data; | |
803 | s32 ret_val; | |
804 | u16 i; | |
805 | u16 rar_count = mac->rar_entry_count; | |
806 | ||
807 | e1000_initialize_hw_bits_82571(hw); | |
808 | ||
809 | /* Initialize identification LED */ | |
810 | ret_val = e1000e_id_led_init(hw); | |
811 | if (ret_val) { | |
812 | hw_dbg(hw, "Error initializing identification LED\n"); | |
813 | return ret_val; | |
814 | } | |
815 | ||
816 | /* Disabling VLAN filtering */ | |
817 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
818 | e1000e_clear_vfta(hw); | |
819 | ||
820 | /* Setup the receive address. */ | |
ad68076e BA |
821 | /* |
822 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
823 | * 82571, we must reserve a RAR for it to work around an issue where |
824 | * resetting one port will reload the MAC on the other port. | |
825 | */ | |
826 | if (e1000e_get_laa_state_82571(hw)) | |
827 | rar_count--; | |
828 | e1000e_init_rx_addrs(hw, rar_count); | |
829 | ||
830 | /* Zero out the Multicast HASH table */ | |
831 | hw_dbg(hw, "Zeroing the MTA\n"); | |
832 | for (i = 0; i < mac->mta_reg_count; i++) | |
833 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
834 | ||
835 | /* Setup link and flow control */ | |
836 | ret_val = e1000_setup_link_82571(hw); | |
837 | ||
838 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 839 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
840 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
841 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
842 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 843 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
844 | |
845 | /* ...for both queues. */ | |
846 | if (mac->type != e1000_82573) { | |
e9ec2c0f | 847 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
848 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
849 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
850 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 851 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
852 | } else { |
853 | e1000e_enable_tx_pkt_filtering(hw); | |
854 | reg_data = er32(GCR); | |
855 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
856 | ew32(GCR, reg_data); | |
857 | } | |
858 | ||
ad68076e BA |
859 | /* |
860 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
861 | * important that we do this after we have tried to establish link |
862 | * because the symbol error count will increment wildly if there | |
863 | * is no link. | |
864 | */ | |
865 | e1000_clear_hw_cntrs_82571(hw); | |
866 | ||
867 | return ret_val; | |
868 | } | |
869 | ||
870 | /** | |
871 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
872 | * @hw: pointer to the HW structure | |
873 | * | |
874 | * Initializes required hardware-dependent bits needed for normal operation. | |
875 | **/ | |
876 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
877 | { | |
878 | u32 reg; | |
879 | ||
880 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 881 | reg = er32(TXDCTL(0)); |
bc7f75fa | 882 | reg |= (1 << 22); |
e9ec2c0f | 883 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
884 | |
885 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 886 | reg = er32(TXDCTL(1)); |
bc7f75fa | 887 | reg |= (1 << 22); |
e9ec2c0f | 888 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
889 | |
890 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 891 | reg = er32(TARC(0)); |
bc7f75fa AK |
892 | reg &= ~(0xF << 27); /* 30:27 */ |
893 | switch (hw->mac.type) { | |
894 | case e1000_82571: | |
895 | case e1000_82572: | |
896 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
897 | break; | |
898 | default: | |
899 | break; | |
900 | } | |
e9ec2c0f | 901 | ew32(TARC(0), reg); |
bc7f75fa AK |
902 | |
903 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 904 | reg = er32(TARC(1)); |
bc7f75fa AK |
905 | switch (hw->mac.type) { |
906 | case e1000_82571: | |
907 | case e1000_82572: | |
908 | reg &= ~((1 << 29) | (1 << 30)); | |
909 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
910 | if (er32(TCTL) & E1000_TCTL_MULR) | |
911 | reg &= ~(1 << 28); | |
912 | else | |
913 | reg |= (1 << 28); | |
e9ec2c0f | 914 | ew32(TARC(1), reg); |
bc7f75fa AK |
915 | break; |
916 | default: | |
917 | break; | |
918 | } | |
919 | ||
920 | /* Device Control */ | |
921 | if (hw->mac.type == e1000_82573) { | |
922 | reg = er32(CTRL); | |
923 | reg &= ~(1 << 29); | |
924 | ew32(CTRL, reg); | |
925 | } | |
926 | ||
927 | /* Extended Device Control */ | |
928 | if (hw->mac.type == e1000_82573) { | |
929 | reg = er32(CTRL_EXT); | |
930 | reg &= ~(1 << 23); | |
931 | reg |= (1 << 22); | |
932 | ew32(CTRL_EXT, reg); | |
933 | } | |
934 | } | |
935 | ||
936 | /** | |
937 | * e1000e_clear_vfta - Clear VLAN filter table | |
938 | * @hw: pointer to the HW structure | |
939 | * | |
940 | * Clears the register array which contains the VLAN filter table by | |
941 | * setting all the values to 0. | |
942 | **/ | |
943 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
944 | { | |
945 | u32 offset; | |
946 | u32 vfta_value = 0; | |
947 | u32 vfta_offset = 0; | |
948 | u32 vfta_bit_in_reg = 0; | |
949 | ||
950 | if (hw->mac.type == e1000_82573) { | |
951 | if (hw->mng_cookie.vlan_id != 0) { | |
ad68076e BA |
952 | /* |
953 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
954 | * a single VLAN ID. The following operations |
955 | * determine which 32b entry (i.e. offset) into the | |
956 | * array we want to set the VLAN ID (i.e. bit) of | |
957 | * the manageability unit. | |
958 | */ | |
959 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
960 | E1000_VFTA_ENTRY_SHIFT) & | |
961 | E1000_VFTA_ENTRY_MASK; | |
962 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
963 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
964 | } | |
965 | } | |
966 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
967 | /* |
968 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
969 | * manageability VLAN ID, then clear all bits except that of |
970 | * the manageability unit. | |
971 | */ | |
972 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
973 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
974 | e1e_flush(); | |
975 | } | |
976 | } | |
977 | ||
978 | /** | |
e2de3eb6 | 979 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
980 | * @hw: pointer to the HW structure |
981 | * @mc_addr_list: array of multicast addresses to program | |
982 | * @mc_addr_count: number of multicast addresses to program | |
983 | * @rar_used_count: the first RAR register free to program | |
984 | * @rar_count: total number of supported Receive Address Registers | |
985 | * | |
986 | * Updates the Receive Address Registers and Multicast Table Array. | |
987 | * The caller must have a packed mc_addr_list of multicast addresses. | |
988 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
989 | * unless there are workarounds that change this. | |
990 | **/ | |
e2de3eb6 | 991 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
992 | u8 *mc_addr_list, |
993 | u32 mc_addr_count, | |
994 | u32 rar_used_count, | |
995 | u32 rar_count) | |
996 | { | |
997 | if (e1000e_get_laa_state_82571(hw)) | |
998 | rar_count--; | |
999 | ||
e2de3eb6 JK |
1000 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1001 | rar_used_count, rar_count); | |
bc7f75fa AK |
1002 | } |
1003 | ||
1004 | /** | |
1005 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1006 | * @hw: pointer to the HW structure | |
1007 | * | |
1008 | * Determines which flow control settings to use, then configures flow | |
1009 | * control. Calls the appropriate media-specific link configuration | |
1010 | * function. Assuming the adapter has a valid link partner, a valid link | |
1011 | * should be established. Assumes the hardware has previously been reset | |
1012 | * and the transmitter and receiver are not enabled. | |
1013 | **/ | |
1014 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1015 | { | |
ad68076e BA |
1016 | /* |
1017 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1018 | * the default flow control setting, so we explicitly |
1019 | * set it to full. | |
1020 | */ | |
1021 | if (hw->mac.type == e1000_82573) | |
318a94d6 | 1022 | hw->fc.type = e1000_fc_full; |
bc7f75fa AK |
1023 | |
1024 | return e1000e_setup_link(hw); | |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1029 | * @hw: pointer to the HW structure | |
1030 | * | |
1031 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1032 | * for link, once link is established calls to configure collision distance | |
1033 | * and flow control are called. | |
1034 | **/ | |
1035 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1036 | { | |
1037 | u32 ctrl; | |
1038 | u32 led_ctrl; | |
1039 | s32 ret_val; | |
1040 | ||
1041 | ctrl = er32(CTRL); | |
1042 | ctrl |= E1000_CTRL_SLU; | |
1043 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1044 | ew32(CTRL, ctrl); | |
1045 | ||
1046 | switch (hw->phy.type) { | |
1047 | case e1000_phy_m88: | |
1048 | ret_val = e1000e_copper_link_setup_m88(hw); | |
1049 | break; | |
1050 | case e1000_phy_igp_2: | |
1051 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1052 | /* Setup activity LED */ | |
1053 | led_ctrl = er32(LEDCTL); | |
1054 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1055 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1056 | ew32(LEDCTL, led_ctrl); | |
1057 | break; | |
1058 | default: | |
1059 | return -E1000_ERR_PHY; | |
1060 | break; | |
1061 | } | |
1062 | ||
1063 | if (ret_val) | |
1064 | return ret_val; | |
1065 | ||
1066 | ret_val = e1000e_setup_copper_link(hw); | |
1067 | ||
1068 | return ret_val; | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1073 | * @hw: pointer to the HW structure | |
1074 | * | |
1075 | * Configures collision distance and flow control for fiber and serdes links. | |
1076 | * Upon successful setup, poll for link. | |
1077 | **/ | |
1078 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1079 | { | |
1080 | switch (hw->mac.type) { | |
1081 | case e1000_82571: | |
1082 | case e1000_82572: | |
ad68076e BA |
1083 | /* |
1084 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1085 | * of reset to take the adapter out of that mode. So we |
1086 | * have to explicitly take the adapter out of loopback | |
489815ce | 1087 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1088 | * if another tool failed to take it out of loopback mode. |
1089 | */ | |
ad68076e | 1090 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1091 | break; |
1092 | default: | |
1093 | break; | |
1094 | } | |
1095 | ||
1096 | return e1000e_setup_fiber_serdes_link(hw); | |
1097 | } | |
1098 | ||
1099 | /** | |
1100 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1101 | * @hw: pointer to the HW structure | |
1102 | * @data: pointer to the NVM (EEPROM) | |
1103 | * | |
1104 | * Read the EEPROM for the current default LED configuration. If the | |
1105 | * LED configuration is not valid, set to a valid LED configuration. | |
1106 | **/ | |
1107 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1108 | { | |
1109 | s32 ret_val; | |
1110 | ||
1111 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1112 | if (ret_val) { | |
1113 | hw_dbg(hw, "NVM Read Error\n"); | |
1114 | return ret_val; | |
1115 | } | |
1116 | ||
1117 | if (hw->mac.type == e1000_82573 && | |
1118 | *data == ID_LED_RESERVED_F746) | |
1119 | *data = ID_LED_DEFAULT_82573; | |
1120 | else if (*data == ID_LED_RESERVED_0000 || | |
1121 | *data == ID_LED_RESERVED_FFFF) | |
1122 | *data = ID_LED_DEFAULT; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | /** | |
1128 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1129 | * @hw: pointer to the HW structure | |
1130 | * | |
489815ce | 1131 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1132 | **/ |
1133 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1134 | { | |
1135 | if (hw->mac.type != e1000_82571) | |
1136 | return 0; | |
1137 | ||
1138 | return hw->dev_spec.e82571.laa_is_present; | |
1139 | } | |
1140 | ||
1141 | /** | |
1142 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1143 | * @hw: pointer to the HW structure | |
1144 | * @state: enable/disable locally administered address | |
1145 | * | |
489815ce | 1146 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1147 | **/ |
1148 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1149 | { | |
1150 | if (hw->mac.type != e1000_82571) | |
1151 | return; | |
1152 | ||
1153 | hw->dev_spec.e82571.laa_is_present = state; | |
1154 | ||
1155 | /* If workaround is activated... */ | |
1156 | if (state) | |
ad68076e BA |
1157 | /* |
1158 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1159 | * between the time RAR[0] gets clobbered and the time it |
1160 | * gets fixed, the actual LAA is in one of the RARs and no | |
1161 | * incoming packets directed to this port are dropped. | |
1162 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1163 | */ | |
1164 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1165 | } | |
1166 | ||
1167 | /** | |
1168 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1169 | * @hw: pointer to the HW structure | |
1170 | * | |
1171 | * Verifies that the EEPROM has completed the update. After updating the | |
1172 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1173 | * the checksum fix is not implemented, we need to set the bit and update | |
1174 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1175 | * we need to return bad checksum. | |
1176 | **/ | |
1177 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1178 | { | |
1179 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1180 | s32 ret_val; | |
1181 | u16 data; | |
1182 | ||
1183 | if (nvm->type != e1000_nvm_flash_hw) | |
1184 | return 0; | |
1185 | ||
ad68076e BA |
1186 | /* |
1187 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1188 | * 10h-12h. Checksum may need to be fixed. |
1189 | */ | |
1190 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1191 | if (ret_val) | |
1192 | return ret_val; | |
1193 | ||
1194 | if (!(data & 0x10)) { | |
ad68076e BA |
1195 | /* |
1196 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1197 | * when the checksum has already been fixed. If |
1198 | * the checksum is still wrong and this bit is a | |
1199 | * 1, we need to return bad checksum. Otherwise, | |
1200 | * we need to set this bit to a 1 and update the | |
1201 | * checksum. | |
1202 | */ | |
1203 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1204 | if (ret_val) | |
1205 | return ret_val; | |
1206 | ||
1207 | if (!(data & 0x8000)) { | |
1208 | data |= 0x8000; | |
1209 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1210 | if (ret_val) | |
1211 | return ret_val; | |
1212 | ret_val = e1000e_update_nvm_checksum(hw); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | /** | |
1220 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1221 | * @hw: pointer to the HW structure | |
1222 | * | |
1223 | * Clears the hardware counters by reading the counter registers. | |
1224 | **/ | |
1225 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1226 | { | |
1227 | u32 temp; | |
1228 | ||
1229 | e1000e_clear_hw_cntrs_base(hw); | |
1230 | ||
1231 | temp = er32(PRC64); | |
1232 | temp = er32(PRC127); | |
1233 | temp = er32(PRC255); | |
1234 | temp = er32(PRC511); | |
1235 | temp = er32(PRC1023); | |
1236 | temp = er32(PRC1522); | |
1237 | temp = er32(PTC64); | |
1238 | temp = er32(PTC127); | |
1239 | temp = er32(PTC255); | |
1240 | temp = er32(PTC511); | |
1241 | temp = er32(PTC1023); | |
1242 | temp = er32(PTC1522); | |
1243 | ||
1244 | temp = er32(ALGNERRC); | |
1245 | temp = er32(RXERRC); | |
1246 | temp = er32(TNCRS); | |
1247 | temp = er32(CEXTERR); | |
1248 | temp = er32(TSCTC); | |
1249 | temp = er32(TSCTFC); | |
1250 | ||
1251 | temp = er32(MGTPRC); | |
1252 | temp = er32(MGTPDC); | |
1253 | temp = er32(MGTPTC); | |
1254 | ||
1255 | temp = er32(IAC); | |
1256 | temp = er32(ICRXOC); | |
1257 | ||
1258 | temp = er32(ICRXPTC); | |
1259 | temp = er32(ICRXATC); | |
1260 | temp = er32(ICTXPTC); | |
1261 | temp = er32(ICTXATC); | |
1262 | temp = er32(ICTXQEC); | |
1263 | temp = er32(ICTXQMTC); | |
1264 | temp = er32(ICRXDMTC); | |
1265 | } | |
1266 | ||
1267 | static struct e1000_mac_operations e82571_mac_ops = { | |
1268 | .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, | |
1269 | /* .check_for_link: media type dependent */ | |
1270 | .cleanup_led = e1000e_cleanup_led_generic, | |
1271 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1272 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1273 | /* .get_link_up_info: media type dependent */ | |
1274 | .led_on = e1000e_led_on_generic, | |
1275 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1276 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
bc7f75fa AK |
1277 | .reset_hw = e1000_reset_hw_82571, |
1278 | .init_hw = e1000_init_hw_82571, | |
1279 | .setup_link = e1000_setup_link_82571, | |
1280 | /* .setup_physical_interface: media type dependent */ | |
1281 | }; | |
1282 | ||
1283 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
1284 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1285 | .check_reset_block = e1000e_check_reset_block_generic, | |
1286 | .commit_phy = NULL, | |
1287 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, | |
1288 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1289 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
1290 | .get_phy_info = e1000e_get_phy_info_igp, | |
1291 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
1292 | .release_phy = e1000_put_hw_semaphore_82571, | |
1293 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1294 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1295 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1296 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
1297 | }; | |
1298 | ||
1299 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
1300 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1301 | .check_reset_block = e1000e_check_reset_block_generic, | |
1302 | .commit_phy = e1000e_phy_sw_reset, | |
1303 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1304 | .get_cfg_done = e1000e_get_cfg_done, | |
1305 | .get_cable_length = e1000e_get_cable_length_m88, | |
1306 | .get_phy_info = e1000e_get_phy_info_m88, | |
1307 | .read_phy_reg = e1000e_read_phy_reg_m88, | |
1308 | .release_phy = e1000_put_hw_semaphore_82571, | |
1309 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1310 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1311 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1312 | .write_phy_reg = e1000e_write_phy_reg_m88, | |
1313 | }; | |
1314 | ||
1315 | static struct e1000_nvm_operations e82571_nvm_ops = { | |
bc7f75fa AK |
1316 | .acquire_nvm = e1000_acquire_nvm_82571, |
1317 | .read_nvm = e1000e_read_nvm_eerd, | |
1318 | .release_nvm = e1000_release_nvm_82571, | |
1319 | .update_nvm = e1000_update_nvm_checksum_82571, | |
1320 | .valid_led_default = e1000_valid_led_default_82571, | |
1321 | .validate_nvm = e1000_validate_nvm_checksum_82571, | |
1322 | .write_nvm = e1000_write_nvm_82571, | |
1323 | }; | |
1324 | ||
1325 | struct e1000_info e1000_82571_info = { | |
1326 | .mac = e1000_82571, | |
1327 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1328 | | FLAG_HAS_JUMBO_FRAMES | |
1329 | | FLAG_HAS_STATS_PTC_PRC | |
1330 | | FLAG_HAS_WOL | |
1331 | | FLAG_APME_IN_CTRL3 | |
1332 | | FLAG_RX_CSUM_ENABLED | |
1333 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
1334 | | FLAG_HAS_STATS_ICR_ICT | |
1335 | | FLAG_HAS_SMART_POWER_DOWN | |
1336 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1337 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1338 | | FLAG_APME_CHECK_PORT_B, | |
1339 | .pba = 38, | |
1340 | .get_invariants = e1000_get_invariants_82571, | |
1341 | .mac_ops = &e82571_mac_ops, | |
1342 | .phy_ops = &e82_phy_ops_igp, | |
1343 | .nvm_ops = &e82571_nvm_ops, | |
1344 | }; | |
1345 | ||
1346 | struct e1000_info e1000_82572_info = { | |
1347 | .mac = e1000_82572, | |
1348 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1349 | | FLAG_HAS_JUMBO_FRAMES | |
1350 | | FLAG_HAS_STATS_PTC_PRC | |
1351 | | FLAG_HAS_WOL | |
1352 | | FLAG_APME_IN_CTRL3 | |
1353 | | FLAG_RX_CSUM_ENABLED | |
1354 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
1355 | | FLAG_HAS_STATS_ICR_ICT | |
1356 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ | |
1357 | .pba = 38, | |
1358 | .get_invariants = e1000_get_invariants_82571, | |
1359 | .mac_ops = &e82571_mac_ops, | |
1360 | .phy_ops = &e82_phy_ops_igp, | |
1361 | .nvm_ops = &e82571_nvm_ops, | |
1362 | }; | |
1363 | ||
1364 | struct e1000_info e1000_82573_info = { | |
1365 | .mac = e1000_82573, | |
1366 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1367 | | FLAG_HAS_JUMBO_FRAMES | |
1368 | | FLAG_HAS_STATS_PTC_PRC | |
1369 | | FLAG_HAS_WOL | |
1370 | | FLAG_APME_IN_CTRL3 | |
1371 | | FLAG_RX_CSUM_ENABLED | |
1372 | | FLAG_HAS_STATS_ICR_ICT | |
1373 | | FLAG_HAS_SMART_POWER_DOWN | |
1374 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1375 | | FLAG_HAS_ERT |
1376 | | FLAG_HAS_SWSM_ON_LOAD, | |
1377 | .pba = 20, | |
1378 | .get_invariants = e1000_get_invariants_82571, | |
1379 | .mac_ops = &e82571_mac_ops, | |
1380 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1381 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1382 | }; |
1383 |