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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
1605927f | 30 | * 82562G 10/100 Network Connection |
bc7f75fa AK |
31 | * 82562G-2 10/100 Network Connection |
32 | * 82562GT 10/100 Network Connection | |
33 | * 82562GT-2 10/100 Network Connection | |
34 | * 82562V 10/100 Network Connection | |
35 | * 82562V-2 10/100 Network Connection | |
36 | * 82566DC-2 Gigabit Network Connection | |
37 | * 82566DC Gigabit Network Connection | |
38 | * 82566DM-2 Gigabit Network Connection | |
39 | * 82566DM Gigabit Network Connection | |
40 | * 82566MC Gigabit Network Connection | |
41 | * 82566MM Gigabit Network Connection | |
97ac8cae BA |
42 | * 82567LM Gigabit Network Connection |
43 | * 82567LF Gigabit Network Connection | |
1605927f | 44 | * 82567V Gigabit Network Connection |
97ac8cae BA |
45 | * 82567LM-2 Gigabit Network Connection |
46 | * 82567LF-2 Gigabit Network Connection | |
47 | * 82567V-2 Gigabit Network Connection | |
f4187b56 BA |
48 | * 82567LF-3 Gigabit Network Connection |
49 | * 82567LM-3 Gigabit Network Connection | |
2f15f9d6 | 50 | * 82567LM-4 Gigabit Network Connection |
a4f58f54 BA |
51 | * 82577LM Gigabit Network Connection |
52 | * 82577LC Gigabit Network Connection | |
53 | * 82578DM Gigabit Network Connection | |
54 | * 82578DC Gigabit Network Connection | |
bc7f75fa AK |
55 | */ |
56 | ||
57 | #include <linux/netdevice.h> | |
58 | #include <linux/ethtool.h> | |
59 | #include <linux/delay.h> | |
60 | #include <linux/pci.h> | |
61 | ||
62 | #include "e1000.h" | |
63 | ||
64 | #define ICH_FLASH_GFPREG 0x0000 | |
65 | #define ICH_FLASH_HSFSTS 0x0004 | |
66 | #define ICH_FLASH_HSFCTL 0x0006 | |
67 | #define ICH_FLASH_FADDR 0x0008 | |
68 | #define ICH_FLASH_FDATA0 0x0010 | |
4a770358 | 69 | #define ICH_FLASH_PR0 0x0074 |
bc7f75fa AK |
70 | |
71 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 | |
72 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 | |
73 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 | |
74 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
75 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
76 | ||
77 | #define ICH_CYCLE_READ 0 | |
78 | #define ICH_CYCLE_WRITE 2 | |
79 | #define ICH_CYCLE_ERASE 3 | |
80 | ||
81 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
82 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
83 | ||
84 | #define ICH_FLASH_SEG_SIZE_256 256 | |
85 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
86 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
87 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
88 | ||
89 | ||
90 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
91 | ||
92 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
93 | ||
94 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | |
95 | (ID_LED_DEF1_OFF2 << 8) | \ | |
96 | (ID_LED_DEF1_ON2 << 4) | \ | |
97 | (ID_LED_DEF1_DEF2)) | |
98 | ||
99 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
100 | #define E1000_ICH_NVM_SIG_MASK 0xC000 | |
e243455d BA |
101 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
102 | #define E1000_ICH_NVM_SIG_VALUE 0x80 | |
bc7f75fa AK |
103 | |
104 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
105 | ||
106 | #define E1000_FEXTNVM_SW_CONFIG 1 | |
107 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ | |
108 | ||
109 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL | |
110 | ||
111 | #define E1000_ICH_RAR_ENTRIES 7 | |
112 | ||
113 | #define PHY_PAGE_SHIFT 5 | |
114 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
115 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
116 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
117 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
118 | ||
119 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
120 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
121 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
122 | ||
a4f58f54 BA |
123 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
124 | ||
bc7f75fa AK |
125 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
126 | /* Offset 04h HSFSTS */ | |
127 | union ich8_hws_flash_status { | |
128 | struct ich8_hsfsts { | |
129 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | |
130 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | |
131 | u16 dael :1; /* bit 2 Direct Access error Log */ | |
132 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ | |
133 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ | |
134 | u16 reserved1 :2; /* bit 13:6 Reserved */ | |
135 | u16 reserved2 :6; /* bit 13:6 Reserved */ | |
136 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | |
137 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ | |
138 | } hsf_status; | |
139 | u16 regval; | |
140 | }; | |
141 | ||
142 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
143 | /* Offset 06h FLCTL */ | |
144 | union ich8_hws_flash_ctrl { | |
145 | struct ich8_hsflctl { | |
146 | u16 flcgo :1; /* 0 Flash Cycle Go */ | |
147 | u16 flcycle :2; /* 2:1 Flash Cycle */ | |
148 | u16 reserved :5; /* 7:3 Reserved */ | |
149 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | |
150 | u16 flockdn :6; /* 15:10 Reserved */ | |
151 | } hsf_ctrl; | |
152 | u16 regval; | |
153 | }; | |
154 | ||
155 | /* ICH Flash Region Access Permissions */ | |
156 | union ich8_hws_flash_regacc { | |
157 | struct ich8_flracc { | |
158 | u32 grra :8; /* 0:7 GbE region Read Access */ | |
159 | u32 grwa :8; /* 8:15 GbE region Write Access */ | |
160 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | |
161 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | |
162 | } hsf_flregacc; | |
163 | u16 regval; | |
164 | }; | |
165 | ||
4a770358 BA |
166 | /* ICH Flash Protected Region */ |
167 | union ich8_flash_protected_range { | |
168 | struct ich8_pr { | |
169 | u32 base:13; /* 0:12 Protected Range Base */ | |
170 | u32 reserved1:2; /* 13:14 Reserved */ | |
171 | u32 rpe:1; /* 15 Read Protection Enable */ | |
172 | u32 limit:13; /* 16:28 Protected Range Limit */ | |
173 | u32 reserved2:2; /* 29:30 Reserved */ | |
174 | u32 wpe:1; /* 31 Write Protection Enable */ | |
175 | } range; | |
176 | u32 regval; | |
177 | }; | |
178 | ||
bc7f75fa AK |
179 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
180 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
181 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
182 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); | |
183 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | |
184 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
185 | u32 offset, u8 byte); | |
f4187b56 BA |
186 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
187 | u8 *data); | |
bc7f75fa AK |
188 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
189 | u16 *data); | |
190 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
191 | u8 size, u16 *data); | |
192 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | |
193 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
f4187b56 | 194 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); |
a4f58f54 BA |
195 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
196 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); | |
197 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); | |
198 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); | |
199 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); | |
200 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); | |
201 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); | |
202 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); | |
bc7f75fa AK |
203 | |
204 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
205 | { | |
206 | return readw(hw->flash_address + reg); | |
207 | } | |
208 | ||
209 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
210 | { | |
211 | return readl(hw->flash_address + reg); | |
212 | } | |
213 | ||
214 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
215 | { | |
216 | writew(val, hw->flash_address + reg); | |
217 | } | |
218 | ||
219 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
220 | { | |
221 | writel(val, hw->flash_address + reg); | |
222 | } | |
223 | ||
224 | #define er16flash(reg) __er16flash(hw, (reg)) | |
225 | #define er32flash(reg) __er32flash(hw, (reg)) | |
226 | #define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) | |
227 | #define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) | |
228 | ||
a4f58f54 BA |
229 | /** |
230 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers | |
231 | * @hw: pointer to the HW structure | |
232 | * | |
233 | * Initialize family-specific PHY parameters and function pointers. | |
234 | **/ | |
235 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |
236 | { | |
237 | struct e1000_phy_info *phy = &hw->phy; | |
238 | s32 ret_val = 0; | |
239 | ||
240 | phy->addr = 1; | |
241 | phy->reset_delay_us = 100; | |
242 | ||
243 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; | |
244 | phy->ops.read_phy_reg = e1000_read_phy_reg_hv; | |
245 | phy->ops.write_phy_reg = e1000_write_phy_reg_hv; | |
246 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
247 | ||
248 | phy->id = e1000_phy_unknown; | |
249 | e1000e_get_phy_id(hw); | |
250 | phy->type = e1000e_get_phy_type_from_id(phy->id); | |
251 | ||
252 | if (phy->type == e1000_phy_82577) { | |
253 | phy->ops.check_polarity = e1000_check_polarity_82577; | |
254 | phy->ops.force_speed_duplex = | |
255 | e1000_phy_force_speed_duplex_82577; | |
256 | phy->ops.get_cable_length = e1000_get_cable_length_82577; | |
257 | phy->ops.get_phy_info = e1000_get_phy_info_82577; | |
258 | phy->ops.commit_phy = e1000e_phy_sw_reset; | |
259 | } | |
260 | ||
261 | return ret_val; | |
262 | } | |
263 | ||
bc7f75fa AK |
264 | /** |
265 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
266 | * @hw: pointer to the HW structure | |
267 | * | |
268 | * Initialize family-specific PHY parameters and function pointers. | |
269 | **/ | |
270 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
271 | { | |
272 | struct e1000_phy_info *phy = &hw->phy; | |
273 | s32 ret_val; | |
274 | u16 i = 0; | |
275 | ||
276 | phy->addr = 1; | |
277 | phy->reset_delay_us = 100; | |
278 | ||
97ac8cae BA |
279 | /* |
280 | * We may need to do this twice - once for IGP and if that fails, | |
281 | * we'll set BM func pointers and try again | |
282 | */ | |
283 | ret_val = e1000e_determine_phy_address(hw); | |
284 | if (ret_val) { | |
285 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
286 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
287 | ret_val = e1000e_determine_phy_address(hw); | |
288 | if (ret_val) | |
289 | return ret_val; | |
290 | } | |
291 | ||
bc7f75fa AK |
292 | phy->id = 0; |
293 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
294 | (i++ < 100)) { | |
295 | msleep(1); | |
296 | ret_val = e1000e_get_phy_id(hw); | |
297 | if (ret_val) | |
298 | return ret_val; | |
299 | } | |
300 | ||
301 | /* Verify phy id */ | |
302 | switch (phy->id) { | |
303 | case IGP03E1000_E_PHY_ID: | |
304 | phy->type = e1000_phy_igp_3; | |
305 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
306 | break; | |
307 | case IFE_E_PHY_ID: | |
308 | case IFE_PLUS_E_PHY_ID: | |
309 | case IFE_C_E_PHY_ID: | |
310 | phy->type = e1000_phy_ife; | |
311 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
312 | break; | |
97ac8cae BA |
313 | case BME1000_E_PHY_ID: |
314 | phy->type = e1000_phy_bm; | |
315 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
316 | hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm; | |
317 | hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm; | |
318 | hw->phy.ops.commit_phy = e1000e_phy_sw_reset; | |
319 | break; | |
bc7f75fa AK |
320 | default: |
321 | return -E1000_ERR_PHY; | |
322 | break; | |
323 | } | |
324 | ||
a4f58f54 BA |
325 | phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan; |
326 | ||
bc7f75fa AK |
327 | return 0; |
328 | } | |
329 | ||
330 | /** | |
331 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
332 | * @hw: pointer to the HW structure | |
333 | * | |
334 | * Initialize family-specific NVM parameters and function | |
335 | * pointers. | |
336 | **/ | |
337 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
338 | { | |
339 | struct e1000_nvm_info *nvm = &hw->nvm; | |
340 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
341 | u32 gfpreg; | |
342 | u32 sector_base_addr; | |
343 | u32 sector_end_addr; | |
344 | u16 i; | |
345 | ||
ad68076e | 346 | /* Can't read flash registers if the register set isn't mapped. */ |
bc7f75fa AK |
347 | if (!hw->flash_address) { |
348 | hw_dbg(hw, "ERROR: Flash registers not mapped\n"); | |
349 | return -E1000_ERR_CONFIG; | |
350 | } | |
351 | ||
352 | nvm->type = e1000_nvm_flash_sw; | |
353 | ||
354 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
355 | ||
ad68076e BA |
356 | /* |
357 | * sector_X_addr is a "sector"-aligned address (4096 bytes) | |
bc7f75fa | 358 | * Add 1 to sector_end_addr since this sector is included in |
ad68076e BA |
359 | * the overall size. |
360 | */ | |
bc7f75fa AK |
361 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
362 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
363 | ||
364 | /* flash_base_addr is byte-aligned */ | |
365 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
366 | ||
ad68076e BA |
367 | /* |
368 | * find total size of the NVM, then cut in half since the total | |
369 | * size represents two separate NVM banks. | |
370 | */ | |
bc7f75fa AK |
371 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
372 | << FLASH_SECTOR_ADDR_SHIFT; | |
373 | nvm->flash_bank_size /= 2; | |
374 | /* Adjust to word count */ | |
375 | nvm->flash_bank_size /= sizeof(u16); | |
376 | ||
377 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
378 | ||
379 | /* Clear shadow ram */ | |
380 | for (i = 0; i < nvm->word_size; i++) { | |
381 | dev_spec->shadow_ram[i].modified = 0; | |
382 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
388 | /** | |
389 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
390 | * @hw: pointer to the HW structure | |
391 | * | |
392 | * Initialize family-specific MAC parameters and function | |
393 | * pointers. | |
394 | **/ | |
395 | static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) | |
396 | { | |
397 | struct e1000_hw *hw = &adapter->hw; | |
398 | struct e1000_mac_info *mac = &hw->mac; | |
399 | ||
400 | /* Set media type function pointer */ | |
318a94d6 | 401 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
402 | |
403 | /* Set mta register count */ | |
404 | mac->mta_reg_count = 32; | |
405 | /* Set rar entry count */ | |
406 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
407 | if (mac->type == e1000_ich8lan) | |
408 | mac->rar_entry_count--; | |
409 | /* Set if manageability features are enabled. */ | |
410 | mac->arc_subsystem_valid = 1; | |
411 | ||
a4f58f54 BA |
412 | /* LED operations */ |
413 | switch (mac->type) { | |
414 | case e1000_ich8lan: | |
415 | case e1000_ich9lan: | |
416 | case e1000_ich10lan: | |
417 | /* ID LED init */ | |
418 | mac->ops.id_led_init = e1000e_id_led_init; | |
419 | /* setup LED */ | |
420 | mac->ops.setup_led = e1000e_setup_led_generic; | |
421 | /* cleanup LED */ | |
422 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; | |
423 | /* turn on/off LED */ | |
424 | mac->ops.led_on = e1000_led_on_ich8lan; | |
425 | mac->ops.led_off = e1000_led_off_ich8lan; | |
426 | break; | |
427 | case e1000_pchlan: | |
428 | /* ID LED init */ | |
429 | mac->ops.id_led_init = e1000_id_led_init_pchlan; | |
430 | /* setup LED */ | |
431 | mac->ops.setup_led = e1000_setup_led_pchlan; | |
432 | /* cleanup LED */ | |
433 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; | |
434 | /* turn on/off LED */ | |
435 | mac->ops.led_on = e1000_led_on_pchlan; | |
436 | mac->ops.led_off = e1000_led_off_pchlan; | |
437 | break; | |
438 | default: | |
439 | break; | |
440 | } | |
441 | ||
bc7f75fa AK |
442 | /* Enable PCS Lock-loss workaround for ICH8 */ |
443 | if (mac->type == e1000_ich8lan) | |
444 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
69e3fd8c | 449 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
450 | { |
451 | struct e1000_hw *hw = &adapter->hw; | |
452 | s32 rc; | |
453 | ||
454 | rc = e1000_init_mac_params_ich8lan(adapter); | |
455 | if (rc) | |
456 | return rc; | |
457 | ||
458 | rc = e1000_init_nvm_params_ich8lan(hw); | |
459 | if (rc) | |
460 | return rc; | |
461 | ||
a4f58f54 BA |
462 | if (hw->mac.type == e1000_pchlan) |
463 | rc = e1000_init_phy_params_pchlan(hw); | |
464 | else | |
465 | rc = e1000_init_phy_params_ich8lan(hw); | |
bc7f75fa AK |
466 | if (rc) |
467 | return rc; | |
468 | ||
2adc55c9 BA |
469 | if (adapter->hw.phy.type == e1000_phy_ife) { |
470 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
471 | adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; | |
472 | } | |
473 | ||
bc7f75fa AK |
474 | if ((adapter->hw.mac.type == e1000_ich8lan) && |
475 | (adapter->hw.phy.type == e1000_phy_igp_3)) | |
476 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
717d438d | 481 | static DEFINE_MUTEX(nvm_mutex); |
717d438d | 482 | |
bc7f75fa AK |
483 | /** |
484 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
485 | * @hw: pointer to the HW structure | |
486 | * | |
487 | * Acquires the software control flag for performing NVM and PHY | |
488 | * operations. This is a function pointer entry point only called by | |
489 | * read/write routines for the PHY and NVM parts. | |
490 | **/ | |
491 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
492 | { | |
493 | u32 extcnf_ctrl; | |
494 | u32 timeout = PHY_CFG_TIMEOUT; | |
495 | ||
95b866d5 | 496 | might_sleep(); |
717d438d | 497 | |
0a834a36 | 498 | mutex_lock(&nvm_mutex); |
717d438d | 499 | |
bc7f75fa AK |
500 | while (timeout) { |
501 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
bc7f75fa | 502 | |
a4f58f54 BA |
503 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) { |
504 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
505 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
506 | ||
507 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
508 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
509 | break; | |
510 | } | |
bc7f75fa AK |
511 | mdelay(1); |
512 | timeout--; | |
513 | } | |
514 | ||
515 | if (!timeout) { | |
516 | hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); | |
2e2e8d53 BA |
517 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
518 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
717d438d | 519 | mutex_unlock(&nvm_mutex); |
bc7f75fa AK |
520 | return -E1000_ERR_CONFIG; |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /** | |
527 | * e1000_release_swflag_ich8lan - Release software control flag | |
528 | * @hw: pointer to the HW structure | |
529 | * | |
530 | * Releases the software control flag for performing NVM and PHY operations. | |
531 | * This is a function pointer entry point only called by read/write | |
532 | * routines for the PHY and NVM parts. | |
533 | **/ | |
534 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
535 | { | |
536 | u32 extcnf_ctrl; | |
537 | ||
538 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
539 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
540 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
717d438d | 541 | |
717d438d | 542 | mutex_unlock(&nvm_mutex); |
bc7f75fa AK |
543 | } |
544 | ||
4662e82b BA |
545 | /** |
546 | * e1000_check_mng_mode_ich8lan - Checks management mode | |
547 | * @hw: pointer to the HW structure | |
548 | * | |
549 | * This checks if the adapter has manageability enabled. | |
550 | * This is a function pointer entry point only called by read/write | |
551 | * routines for the PHY and NVM parts. | |
552 | **/ | |
553 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) | |
554 | { | |
555 | u32 fwsm = er32(FWSM); | |
556 | ||
557 | return (fwsm & E1000_FWSM_MODE_MASK) == | |
558 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); | |
559 | } | |
560 | ||
bc7f75fa AK |
561 | /** |
562 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
563 | * @hw: pointer to the HW structure | |
564 | * | |
565 | * Checks if firmware is blocking the reset of the PHY. | |
566 | * This is a function pointer entry point only called by | |
567 | * reset routines. | |
568 | **/ | |
569 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
570 | { | |
571 | u32 fwsm; | |
572 | ||
573 | fwsm = er32(FWSM); | |
574 | ||
575 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; | |
576 | } | |
577 | ||
578 | /** | |
579 | * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex | |
580 | * @hw: pointer to the HW structure | |
581 | * | |
582 | * Forces the speed and duplex settings of the PHY. | |
583 | * This is a function pointer entry point only called by | |
584 | * PHY setup routines. | |
585 | **/ | |
586 | static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |
587 | { | |
588 | struct e1000_phy_info *phy = &hw->phy; | |
589 | s32 ret_val; | |
590 | u16 data; | |
591 | bool link; | |
592 | ||
593 | if (phy->type != e1000_phy_ife) { | |
594 | ret_val = e1000e_phy_force_speed_duplex_igp(hw); | |
595 | return ret_val; | |
596 | } | |
597 | ||
598 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
599 | if (ret_val) | |
600 | return ret_val; | |
601 | ||
602 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
603 | ||
604 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
605 | if (ret_val) | |
606 | return ret_val; | |
607 | ||
608 | /* Disable MDI-X support for 10/100 */ | |
609 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
610 | if (ret_val) | |
611 | return ret_val; | |
612 | ||
613 | data &= ~IFE_PMC_AUTO_MDIX; | |
614 | data &= ~IFE_PMC_FORCE_MDIX; | |
615 | ||
616 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
617 | if (ret_val) | |
618 | return ret_val; | |
619 | ||
620 | hw_dbg(hw, "IFE PMC: %X\n", data); | |
621 | ||
622 | udelay(1); | |
623 | ||
318a94d6 | 624 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
625 | hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); |
626 | ||
627 | ret_val = e1000e_phy_has_link_generic(hw, | |
628 | PHY_FORCE_LIMIT, | |
629 | 100000, | |
630 | &link); | |
631 | if (ret_val) | |
632 | return ret_val; | |
633 | ||
634 | if (!link) | |
635 | hw_dbg(hw, "Link taking longer than expected.\n"); | |
636 | ||
637 | /* Try once more */ | |
638 | ret_val = e1000e_phy_has_link_generic(hw, | |
639 | PHY_FORCE_LIMIT, | |
640 | 100000, | |
641 | &link); | |
642 | if (ret_val) | |
643 | return ret_val; | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
a4f58f54 BA |
649 | /** |
650 | * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
651 | * done after every PHY reset. | |
652 | **/ | |
653 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
654 | { | |
655 | s32 ret_val = 0; | |
656 | ||
657 | if (hw->mac.type != e1000_pchlan) | |
658 | return ret_val; | |
659 | ||
660 | if (((hw->phy.type == e1000_phy_82577) && | |
661 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || | |
662 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { | |
663 | /* Disable generation of early preamble */ | |
664 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); | |
665 | if (ret_val) | |
666 | return ret_val; | |
667 | ||
668 | /* Preamble tuning for SSC */ | |
669 | ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); | |
670 | if (ret_val) | |
671 | return ret_val; | |
672 | } | |
673 | ||
674 | if (hw->phy.type == e1000_phy_82578) { | |
675 | /* | |
676 | * Return registers to default by doing a soft reset then | |
677 | * writing 0x3140 to the control register. | |
678 | */ | |
679 | if (hw->phy.revision < 2) { | |
680 | e1000e_phy_sw_reset(hw); | |
681 | ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); | |
682 | } | |
683 | } | |
684 | ||
685 | /* Select page 0 */ | |
686 | ret_val = hw->phy.ops.acquire_phy(hw); | |
687 | if (ret_val) | |
688 | return ret_val; | |
689 | hw->phy.addr = 1; | |
690 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); | |
691 | hw->phy.ops.release_phy(hw); | |
692 | ||
693 | return ret_val; | |
694 | } | |
695 | ||
bc7f75fa AK |
696 | /** |
697 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
698 | * @hw: pointer to the HW structure | |
699 | * | |
700 | * Resets the PHY | |
701 | * This is a function pointer entry point called by drivers | |
702 | * or other shared routines. | |
703 | **/ | |
704 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
705 | { | |
706 | struct e1000_phy_info *phy = &hw->phy; | |
707 | u32 i; | |
708 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
709 | s32 ret_val; | |
710 | u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
711 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | |
712 | ||
713 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
714 | if (ret_val) | |
715 | return ret_val; | |
716 | ||
a4f58f54 BA |
717 | if (hw->mac.type == e1000_pchlan) { |
718 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | |
719 | if (ret_val) | |
720 | return ret_val; | |
721 | } | |
722 | ||
ad68076e BA |
723 | /* |
724 | * Initialize the PHY from the NVM on ICH platforms. This | |
bc7f75fa AK |
725 | * is needed due to an issue where the NVM configuration is |
726 | * not properly autoloaded after power transitions. | |
727 | * Therefore, after each PHY reset, we will load the | |
728 | * configuration data out of the NVM manually. | |
729 | */ | |
730 | if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { | |
731 | struct e1000_adapter *adapter = hw->adapter; | |
732 | ||
733 | /* Check if SW needs configure the PHY */ | |
734 | if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || | |
735 | (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M)) | |
736 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; | |
737 | else | |
738 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; | |
739 | ||
740 | data = er32(FEXTNVM); | |
741 | if (!(data & sw_cfg_mask)) | |
742 | return 0; | |
743 | ||
744 | /* Wait for basic configuration completes before proceeding*/ | |
745 | do { | |
746 | data = er32(STATUS); | |
747 | data &= E1000_STATUS_LAN_INIT_DONE; | |
748 | udelay(100); | |
749 | } while ((!data) && --loop); | |
750 | ||
ad68076e BA |
751 | /* |
752 | * If basic configuration is incomplete before the above loop | |
bc7f75fa AK |
753 | * count reaches 0, loading the configuration from NVM will |
754 | * leave the PHY in a bad state possibly resulting in no link. | |
755 | */ | |
756 | if (loop == 0) { | |
757 | hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); | |
758 | } | |
759 | ||
760 | /* Clear the Init Done bit for the next init event */ | |
761 | data = er32(STATUS); | |
762 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
763 | ew32(STATUS, data); | |
764 | ||
ad68076e BA |
765 | /* |
766 | * Make sure HW does not configure LCD from PHY | |
767 | * extended configuration before SW configuration | |
768 | */ | |
bc7f75fa AK |
769 | data = er32(EXTCNF_CTRL); |
770 | if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) | |
771 | return 0; | |
772 | ||
773 | cnf_size = er32(EXTCNF_SIZE); | |
774 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
775 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
776 | if (!cnf_size) | |
777 | return 0; | |
778 | ||
779 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
780 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
781 | ||
ad68076e | 782 | /* Configure LCD from extended configuration region. */ |
bc7f75fa AK |
783 | |
784 | /* cnf_base_addr is in DWORD */ | |
785 | word_addr = (u16)(cnf_base_addr << 1); | |
786 | ||
787 | for (i = 0; i < cnf_size; i++) { | |
788 | ret_val = e1000_read_nvm(hw, | |
789 | (word_addr + i * 2), | |
790 | 1, | |
791 | ®_data); | |
792 | if (ret_val) | |
793 | return ret_val; | |
794 | ||
795 | ret_val = e1000_read_nvm(hw, | |
796 | (word_addr + i * 2 + 1), | |
797 | 1, | |
798 | ®_addr); | |
799 | if (ret_val) | |
800 | return ret_val; | |
801 | ||
802 | /* Save off the PHY page for future writes. */ | |
803 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
804 | phy_page = reg_data; | |
805 | continue; | |
806 | } | |
807 | ||
808 | reg_addr |= phy_page; | |
809 | ||
810 | ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); | |
811 | if (ret_val) | |
812 | return ret_val; | |
813 | } | |
814 | } | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | /** | |
820 | * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states | |
821 | * @hw: pointer to the HW structure | |
822 | * | |
823 | * Populates "phy" structure with various feature states. | |
824 | * This function is only called by other family-specific | |
825 | * routines. | |
826 | **/ | |
827 | static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) | |
828 | { | |
829 | struct e1000_phy_info *phy = &hw->phy; | |
830 | s32 ret_val; | |
831 | u16 data; | |
832 | bool link; | |
833 | ||
834 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
835 | if (ret_val) | |
836 | return ret_val; | |
837 | ||
838 | if (!link) { | |
839 | hw_dbg(hw, "Phy info is only valid if link is up\n"); | |
840 | return -E1000_ERR_CONFIG; | |
841 | } | |
842 | ||
843 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
844 | if (ret_val) | |
845 | return ret_val; | |
846 | phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); | |
847 | ||
848 | if (phy->polarity_correction) { | |
a4f58f54 | 849 | ret_val = phy->ops.check_polarity(hw); |
bc7f75fa AK |
850 | if (ret_val) |
851 | return ret_val; | |
852 | } else { | |
853 | /* Polarity is forced */ | |
854 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
855 | ? e1000_rev_polarity_reversed | |
856 | : e1000_rev_polarity_normal; | |
857 | } | |
858 | ||
859 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
860 | if (ret_val) | |
861 | return ret_val; | |
862 | ||
863 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); | |
864 | ||
865 | /* The following parameters are undefined for 10/100 operation. */ | |
866 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
867 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
868 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
869 | ||
870 | return 0; | |
871 | } | |
872 | ||
873 | /** | |
874 | * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info | |
875 | * @hw: pointer to the HW structure | |
876 | * | |
877 | * Wrapper for calling the get_phy_info routines for the appropriate phy type. | |
878 | * This is a function pointer entry point called by drivers | |
879 | * or other shared routines. | |
880 | **/ | |
881 | static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) | |
882 | { | |
883 | switch (hw->phy.type) { | |
884 | case e1000_phy_ife: | |
885 | return e1000_get_phy_info_ife_ich8lan(hw); | |
886 | break; | |
887 | case e1000_phy_igp_3: | |
97ac8cae | 888 | case e1000_phy_bm: |
a4f58f54 BA |
889 | case e1000_phy_82578: |
890 | case e1000_phy_82577: | |
bc7f75fa AK |
891 | return e1000e_get_phy_info_igp(hw); |
892 | break; | |
893 | default: | |
894 | break; | |
895 | } | |
896 | ||
897 | return -E1000_ERR_PHY_TYPE; | |
898 | } | |
899 | ||
900 | /** | |
901 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY | |
902 | * @hw: pointer to the HW structure | |
903 | * | |
489815ce | 904 | * Polarity is determined on the polarity reversal feature being enabled. |
bc7f75fa AK |
905 | * This function is only called by other family-specific |
906 | * routines. | |
907 | **/ | |
908 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) | |
909 | { | |
910 | struct e1000_phy_info *phy = &hw->phy; | |
911 | s32 ret_val; | |
912 | u16 phy_data, offset, mask; | |
913 | ||
ad68076e BA |
914 | /* |
915 | * Polarity is determined based on the reversal feature being enabled. | |
bc7f75fa AK |
916 | */ |
917 | if (phy->polarity_correction) { | |
918 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
919 | mask = IFE_PESC_POLARITY_REVERSED; | |
920 | } else { | |
921 | offset = IFE_PHY_SPECIAL_CONTROL; | |
922 | mask = IFE_PSC_FORCE_POLARITY; | |
923 | } | |
924 | ||
925 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
926 | ||
927 | if (!ret_val) | |
928 | phy->cable_polarity = (phy_data & mask) | |
929 | ? e1000_rev_polarity_reversed | |
930 | : e1000_rev_polarity_normal; | |
931 | ||
932 | return ret_val; | |
933 | } | |
934 | ||
935 | /** | |
936 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
937 | * @hw: pointer to the HW structure | |
938 | * @active: TRUE to enable LPLU, FALSE to disable | |
939 | * | |
940 | * Sets the LPLU D0 state according to the active flag. When | |
941 | * activating LPLU this function also disables smart speed | |
942 | * and vice versa. LPLU will not be activated unless the | |
943 | * device autonegotiation advertisement meets standards of | |
944 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
945 | * This is a function pointer entry point only called by | |
946 | * PHY setup routines. | |
947 | **/ | |
948 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
949 | { | |
950 | struct e1000_phy_info *phy = &hw->phy; | |
951 | u32 phy_ctrl; | |
952 | s32 ret_val = 0; | |
953 | u16 data; | |
954 | ||
97ac8cae | 955 | if (phy->type == e1000_phy_ife) |
bc7f75fa AK |
956 | return ret_val; |
957 | ||
958 | phy_ctrl = er32(PHY_CTRL); | |
959 | ||
960 | if (active) { | |
961 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
962 | ew32(PHY_CTRL, phy_ctrl); | |
963 | ||
ad68076e BA |
964 | /* |
965 | * Call gig speed drop workaround on LPLU before accessing | |
966 | * any PHY registers | |
967 | */ | |
bc7f75fa AK |
968 | if ((hw->mac.type == e1000_ich8lan) && |
969 | (hw->phy.type == e1000_phy_igp_3)) | |
970 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
971 | ||
972 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
973 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
974 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
975 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
976 | if (ret_val) | |
977 | return ret_val; | |
978 | } else { | |
979 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
980 | ew32(PHY_CTRL, phy_ctrl); | |
981 | ||
ad68076e BA |
982 | /* |
983 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
984 | * during Dx states where the power conservation is most |
985 | * important. During driver activity we should enable | |
ad68076e BA |
986 | * SmartSpeed, so performance is maintained. |
987 | */ | |
bc7f75fa AK |
988 | if (phy->smart_speed == e1000_smart_speed_on) { |
989 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 990 | &data); |
bc7f75fa AK |
991 | if (ret_val) |
992 | return ret_val; | |
993 | ||
994 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
995 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 996 | data); |
bc7f75fa AK |
997 | if (ret_val) |
998 | return ret_val; | |
999 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1000 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1001 | &data); |
bc7f75fa AK |
1002 | if (ret_val) |
1003 | return ret_val; | |
1004 | ||
1005 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1006 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1007 | data); |
bc7f75fa AK |
1008 | if (ret_val) |
1009 | return ret_val; | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | /** | |
1017 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
1018 | * @hw: pointer to the HW structure | |
1019 | * @active: TRUE to enable LPLU, FALSE to disable | |
1020 | * | |
1021 | * Sets the LPLU D3 state according to the active flag. When | |
1022 | * activating LPLU this function also disables smart speed | |
1023 | * and vice versa. LPLU will not be activated unless the | |
1024 | * device autonegotiation advertisement meets standards of | |
1025 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
1026 | * This is a function pointer entry point only called by | |
1027 | * PHY setup routines. | |
1028 | **/ | |
1029 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
1030 | { | |
1031 | struct e1000_phy_info *phy = &hw->phy; | |
1032 | u32 phy_ctrl; | |
1033 | s32 ret_val; | |
1034 | u16 data; | |
1035 | ||
1036 | phy_ctrl = er32(PHY_CTRL); | |
1037 | ||
1038 | if (!active) { | |
1039 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
1040 | ew32(PHY_CTRL, phy_ctrl); | |
ad68076e BA |
1041 | /* |
1042 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1043 | * during Dx states where the power conservation is most |
1044 | * important. During driver activity we should enable | |
ad68076e BA |
1045 | * SmartSpeed, so performance is maintained. |
1046 | */ | |
bc7f75fa | 1047 | if (phy->smart_speed == e1000_smart_speed_on) { |
ad68076e BA |
1048 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1049 | &data); | |
bc7f75fa AK |
1050 | if (ret_val) |
1051 | return ret_val; | |
1052 | ||
1053 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
1054 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1055 | data); | |
bc7f75fa AK |
1056 | if (ret_val) |
1057 | return ret_val; | |
1058 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
ad68076e BA |
1059 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1060 | &data); | |
bc7f75fa AK |
1061 | if (ret_val) |
1062 | return ret_val; | |
1063 | ||
1064 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
1065 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
1066 | data); | |
bc7f75fa AK |
1067 | if (ret_val) |
1068 | return ret_val; | |
1069 | } | |
1070 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1071 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1072 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1073 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
1074 | ew32(PHY_CTRL, phy_ctrl); | |
1075 | ||
ad68076e BA |
1076 | /* |
1077 | * Call gig speed drop workaround on LPLU before accessing | |
1078 | * any PHY registers | |
1079 | */ | |
bc7f75fa AK |
1080 | if ((hw->mac.type == e1000_ich8lan) && |
1081 | (hw->phy.type == e1000_phy_igp_3)) | |
1082 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
1083 | ||
1084 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
ad68076e | 1085 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
bc7f75fa AK |
1086 | if (ret_val) |
1087 | return ret_val; | |
1088 | ||
1089 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e | 1090 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
bc7f75fa AK |
1091 | } |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
f4187b56 BA |
1096 | /** |
1097 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 | |
1098 | * @hw: pointer to the HW structure | |
1099 | * @bank: pointer to the variable that returns the active bank | |
1100 | * | |
1101 | * Reads signature byte from the NVM using the flash access registers. | |
e243455d | 1102 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
f4187b56 BA |
1103 | **/ |
1104 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |
1105 | { | |
e243455d | 1106 | u32 eecd; |
f4187b56 | 1107 | struct e1000_nvm_info *nvm = &hw->nvm; |
f4187b56 BA |
1108 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
1109 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; | |
e243455d BA |
1110 | u8 sig_byte = 0; |
1111 | s32 ret_val = 0; | |
f4187b56 | 1112 | |
e243455d BA |
1113 | switch (hw->mac.type) { |
1114 | case e1000_ich8lan: | |
1115 | case e1000_ich9lan: | |
1116 | eecd = er32(EECD); | |
1117 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == | |
1118 | E1000_EECD_SEC1VAL_VALID_MASK) { | |
1119 | if (eecd & E1000_EECD_SEC1VAL) | |
1120 | *bank = 1; | |
1121 | else | |
1122 | *bank = 0; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | hw_dbg(hw, "Unable to determine valid NVM bank via EEC - " | |
1127 | "reading flash signature\n"); | |
1128 | /* fall-thru */ | |
1129 | default: | |
1130 | /* set bank to 0 in case flash read fails */ | |
1131 | *bank = 0; | |
1132 | ||
1133 | /* Check bank 0 */ | |
1134 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, | |
1135 | &sig_byte); | |
1136 | if (ret_val) | |
1137 | return ret_val; | |
1138 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
1139 | E1000_ICH_NVM_SIG_VALUE) { | |
f4187b56 | 1140 | *bank = 0; |
e243455d BA |
1141 | return 0; |
1142 | } | |
f4187b56 | 1143 | |
e243455d BA |
1144 | /* Check bank 1 */ |
1145 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + | |
1146 | bank1_offset, | |
1147 | &sig_byte); | |
1148 | if (ret_val) | |
1149 | return ret_val; | |
1150 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
1151 | E1000_ICH_NVM_SIG_VALUE) { | |
1152 | *bank = 1; | |
1153 | return 0; | |
f4187b56 | 1154 | } |
e243455d BA |
1155 | |
1156 | hw_dbg(hw, "ERROR: No valid NVM bank present\n"); | |
1157 | return -E1000_ERR_NVM; | |
f4187b56 BA |
1158 | } |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
bc7f75fa AK |
1163 | /** |
1164 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
1165 | * @hw: pointer to the HW structure | |
1166 | * @offset: The offset (in bytes) of the word(s) to read. | |
1167 | * @words: Size of data to read in words | |
1168 | * @data: Pointer to the word(s) to read at offset. | |
1169 | * | |
1170 | * Reads a word(s) from the NVM using the flash access registers. | |
1171 | **/ | |
1172 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1173 | u16 *data) | |
1174 | { | |
1175 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1176 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1177 | u32 act_offset; | |
1178 | s32 ret_val; | |
f4187b56 | 1179 | u32 bank = 0; |
bc7f75fa AK |
1180 | u16 i, word; |
1181 | ||
1182 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1183 | (words == 0)) { | |
1184 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1185 | return -E1000_ERR_NVM; | |
1186 | } | |
1187 | ||
1188 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1189 | if (ret_val) | |
e243455d | 1190 | goto out; |
bc7f75fa | 1191 | |
f4187b56 BA |
1192 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
1193 | if (ret_val) | |
e243455d | 1194 | goto release; |
f4187b56 BA |
1195 | |
1196 | act_offset = (bank) ? nvm->flash_bank_size : 0; | |
bc7f75fa AK |
1197 | act_offset += offset; |
1198 | ||
1199 | for (i = 0; i < words; i++) { | |
1200 | if ((dev_spec->shadow_ram) && | |
1201 | (dev_spec->shadow_ram[offset+i].modified)) { | |
1202 | data[i] = dev_spec->shadow_ram[offset+i].value; | |
1203 | } else { | |
1204 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
1205 | act_offset + i, | |
1206 | &word); | |
1207 | if (ret_val) | |
1208 | break; | |
1209 | data[i] = word; | |
1210 | } | |
1211 | } | |
1212 | ||
e243455d | 1213 | release: |
bc7f75fa AK |
1214 | e1000_release_swflag_ich8lan(hw); |
1215 | ||
e243455d BA |
1216 | out: |
1217 | if (ret_val) | |
1218 | hw_dbg(hw, "NVM read error: %d\n", ret_val); | |
1219 | ||
bc7f75fa AK |
1220 | return ret_val; |
1221 | } | |
1222 | ||
1223 | /** | |
1224 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
1225 | * @hw: pointer to the HW structure | |
1226 | * | |
1227 | * This function does initial flash setup so that a new read/write/erase cycle | |
1228 | * can be started. | |
1229 | **/ | |
1230 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
1231 | { | |
1232 | union ich8_hws_flash_status hsfsts; | |
1233 | s32 ret_val = -E1000_ERR_NVM; | |
1234 | s32 i = 0; | |
1235 | ||
1236 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1237 | ||
1238 | /* Check if the flash descriptor is valid */ | |
1239 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
1240 | hw_dbg(hw, "Flash descriptor invalid. " | |
1241 | "SW Sequencing must be used."); | |
1242 | return -E1000_ERR_NVM; | |
1243 | } | |
1244 | ||
1245 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
1246 | hsfsts.hsf_status.flcerr = 1; | |
1247 | hsfsts.hsf_status.dael = 1; | |
1248 | ||
1249 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1250 | ||
ad68076e BA |
1251 | /* |
1252 | * Either we should have a hardware SPI cycle in progress | |
bc7f75fa AK |
1253 | * bit to check against, in order to start a new cycle or |
1254 | * FDONE bit should be changed in the hardware so that it | |
489815ce | 1255 | * is 1 after hardware reset, which can then be used as an |
bc7f75fa AK |
1256 | * indication whether a cycle is in progress or has been |
1257 | * completed. | |
1258 | */ | |
1259 | ||
1260 | if (hsfsts.hsf_status.flcinprog == 0) { | |
ad68076e BA |
1261 | /* |
1262 | * There is no cycle running at present, | |
1263 | * so we can start a cycle | |
1264 | * Begin by setting Flash Cycle Done. | |
1265 | */ | |
bc7f75fa AK |
1266 | hsfsts.hsf_status.flcdone = 1; |
1267 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1268 | ret_val = 0; | |
1269 | } else { | |
ad68076e BA |
1270 | /* |
1271 | * otherwise poll for sometime so the current | |
1272 | * cycle has a chance to end before giving up. | |
1273 | */ | |
bc7f75fa AK |
1274 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
1275 | hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); | |
1276 | if (hsfsts.hsf_status.flcinprog == 0) { | |
1277 | ret_val = 0; | |
1278 | break; | |
1279 | } | |
1280 | udelay(1); | |
1281 | } | |
1282 | if (ret_val == 0) { | |
ad68076e BA |
1283 | /* |
1284 | * Successful in waiting for previous cycle to timeout, | |
1285 | * now set the Flash Cycle Done. | |
1286 | */ | |
bc7f75fa AK |
1287 | hsfsts.hsf_status.flcdone = 1; |
1288 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1289 | } else { | |
1290 | hw_dbg(hw, "Flash controller busy, cannot get access"); | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | return ret_val; | |
1295 | } | |
1296 | ||
1297 | /** | |
1298 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
1299 | * @hw: pointer to the HW structure | |
1300 | * @timeout: maximum time to wait for completion | |
1301 | * | |
1302 | * This function starts a flash cycle and waits for its completion. | |
1303 | **/ | |
1304 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
1305 | { | |
1306 | union ich8_hws_flash_ctrl hsflctl; | |
1307 | union ich8_hws_flash_status hsfsts; | |
1308 | s32 ret_val = -E1000_ERR_NVM; | |
1309 | u32 i = 0; | |
1310 | ||
1311 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
1312 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1313 | hsflctl.hsf_ctrl.flcgo = 1; | |
1314 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1315 | ||
1316 | /* wait till FDONE bit is set to 1 */ | |
1317 | do { | |
1318 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1319 | if (hsfsts.hsf_status.flcdone == 1) | |
1320 | break; | |
1321 | udelay(1); | |
1322 | } while (i++ < timeout); | |
1323 | ||
1324 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) | |
1325 | return 0; | |
1326 | ||
1327 | return ret_val; | |
1328 | } | |
1329 | ||
1330 | /** | |
1331 | * e1000_read_flash_word_ich8lan - Read word from flash | |
1332 | * @hw: pointer to the HW structure | |
1333 | * @offset: offset to data location | |
1334 | * @data: pointer to the location for storing the data | |
1335 | * | |
1336 | * Reads the flash word at offset into data. Offset is converted | |
1337 | * to bytes before read. | |
1338 | **/ | |
1339 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
1340 | u16 *data) | |
1341 | { | |
1342 | /* Must convert offset into bytes. */ | |
1343 | offset <<= 1; | |
1344 | ||
1345 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
1346 | } | |
1347 | ||
f4187b56 BA |
1348 | /** |
1349 | * e1000_read_flash_byte_ich8lan - Read byte from flash | |
1350 | * @hw: pointer to the HW structure | |
1351 | * @offset: The offset of the byte to read. | |
1352 | * @data: Pointer to a byte to store the value read. | |
1353 | * | |
1354 | * Reads a single byte from the NVM using the flash access registers. | |
1355 | **/ | |
1356 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1357 | u8 *data) | |
1358 | { | |
1359 | s32 ret_val; | |
1360 | u16 word = 0; | |
1361 | ||
1362 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); | |
1363 | if (ret_val) | |
1364 | return ret_val; | |
1365 | ||
1366 | *data = (u8)word; | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
bc7f75fa AK |
1371 | /** |
1372 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
1373 | * @hw: pointer to the HW structure | |
1374 | * @offset: The offset (in bytes) of the byte or word to read. | |
1375 | * @size: Size of data to read, 1=byte 2=word | |
1376 | * @data: Pointer to the word to store the value read. | |
1377 | * | |
1378 | * Reads a byte or word from the NVM using the flash access registers. | |
1379 | **/ | |
1380 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1381 | u8 size, u16 *data) | |
1382 | { | |
1383 | union ich8_hws_flash_status hsfsts; | |
1384 | union ich8_hws_flash_ctrl hsflctl; | |
1385 | u32 flash_linear_addr; | |
1386 | u32 flash_data = 0; | |
1387 | s32 ret_val = -E1000_ERR_NVM; | |
1388 | u8 count = 0; | |
1389 | ||
1390 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1391 | return -E1000_ERR_NVM; | |
1392 | ||
1393 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1394 | hw->nvm.flash_base_addr; | |
1395 | ||
1396 | do { | |
1397 | udelay(1); | |
1398 | /* Steps */ | |
1399 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1400 | if (ret_val != 0) | |
1401 | break; | |
1402 | ||
1403 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1404 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1405 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
1406 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
1407 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1408 | ||
1409 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1410 | ||
1411 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1412 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
1413 | ||
ad68076e BA |
1414 | /* |
1415 | * Check if FCERR is set to 1, if set to 1, clear it | |
bc7f75fa AK |
1416 | * and try the whole sequence a few more times, else |
1417 | * read in (shift in) the Flash Data0, the order is | |
ad68076e BA |
1418 | * least significant byte first msb to lsb |
1419 | */ | |
bc7f75fa AK |
1420 | if (ret_val == 0) { |
1421 | flash_data = er32flash(ICH_FLASH_FDATA0); | |
1422 | if (size == 1) { | |
1423 | *data = (u8)(flash_data & 0x000000FF); | |
1424 | } else if (size == 2) { | |
1425 | *data = (u16)(flash_data & 0x0000FFFF); | |
1426 | } | |
1427 | break; | |
1428 | } else { | |
ad68076e BA |
1429 | /* |
1430 | * If we've gotten here, then things are probably | |
bc7f75fa AK |
1431 | * completely hosed, but if the error condition is |
1432 | * detected, it won't hurt to give it another try... | |
1433 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1434 | */ | |
1435 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1436 | if (hsfsts.hsf_status.flcerr == 1) { | |
1437 | /* Repeat for some time before giving up. */ | |
1438 | continue; | |
1439 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
1440 | hw_dbg(hw, "Timeout error - flash cycle " | |
1441 | "did not complete."); | |
1442 | break; | |
1443 | } | |
1444 | } | |
1445 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1446 | ||
1447 | return ret_val; | |
1448 | } | |
1449 | ||
1450 | /** | |
1451 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
1452 | * @hw: pointer to the HW structure | |
1453 | * @offset: The offset (in bytes) of the word(s) to write. | |
1454 | * @words: Size of data to write in words | |
1455 | * @data: Pointer to the word(s) to write at offset. | |
1456 | * | |
1457 | * Writes a byte or word to the NVM using the flash access registers. | |
1458 | **/ | |
1459 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1460 | u16 *data) | |
1461 | { | |
1462 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1463 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1464 | s32 ret_val; | |
1465 | u16 i; | |
1466 | ||
1467 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1468 | (words == 0)) { | |
1469 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1470 | return -E1000_ERR_NVM; | |
1471 | } | |
1472 | ||
1473 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1474 | if (ret_val) | |
1475 | return ret_val; | |
1476 | ||
1477 | for (i = 0; i < words; i++) { | |
1478 | dev_spec->shadow_ram[offset+i].modified = 1; | |
1479 | dev_spec->shadow_ram[offset+i].value = data[i]; | |
1480 | } | |
1481 | ||
1482 | e1000_release_swflag_ich8lan(hw); | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | /** | |
1488 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
1489 | * @hw: pointer to the HW structure | |
1490 | * | |
1491 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
1492 | * which writes the checksum to the shadow ram. The changes in the shadow | |
1493 | * ram are then committed to the EEPROM by processing each bank at a time | |
1494 | * checking for the modified bit and writing only the pending changes. | |
489815ce | 1495 | * After a successful commit, the shadow ram is cleared and is ready for |
bc7f75fa AK |
1496 | * future writes. |
1497 | **/ | |
1498 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1499 | { | |
1500 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1501 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
f4187b56 | 1502 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
bc7f75fa AK |
1503 | s32 ret_val; |
1504 | u16 data; | |
1505 | ||
1506 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
1507 | if (ret_val) | |
e243455d | 1508 | goto out; |
bc7f75fa AK |
1509 | |
1510 | if (nvm->type != e1000_nvm_flash_sw) | |
e243455d | 1511 | goto out; |
bc7f75fa AK |
1512 | |
1513 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1514 | if (ret_val) | |
e243455d | 1515 | goto out; |
bc7f75fa | 1516 | |
ad68076e BA |
1517 | /* |
1518 | * We're writing to the opposite bank so if we're on bank 1, | |
bc7f75fa | 1519 | * write to bank 0 etc. We also need to erase the segment that |
ad68076e BA |
1520 | * is going to be written |
1521 | */ | |
f4187b56 | 1522 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
e243455d BA |
1523 | if (ret_val) { |
1524 | e1000_release_swflag_ich8lan(hw); | |
1525 | goto out; | |
1526 | } | |
f4187b56 BA |
1527 | |
1528 | if (bank == 0) { | |
bc7f75fa AK |
1529 | new_bank_offset = nvm->flash_bank_size; |
1530 | old_bank_offset = 0; | |
e243455d BA |
1531 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
1532 | if (ret_val) { | |
1533 | e1000_release_swflag_ich8lan(hw); | |
1534 | goto out; | |
1535 | } | |
bc7f75fa AK |
1536 | } else { |
1537 | old_bank_offset = nvm->flash_bank_size; | |
1538 | new_bank_offset = 0; | |
e243455d BA |
1539 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
1540 | if (ret_val) { | |
1541 | e1000_release_swflag_ich8lan(hw); | |
1542 | goto out; | |
1543 | } | |
bc7f75fa AK |
1544 | } |
1545 | ||
1546 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
ad68076e BA |
1547 | /* |
1548 | * Determine whether to write the value stored | |
bc7f75fa | 1549 | * in the other NVM bank or a modified value stored |
ad68076e BA |
1550 | * in the shadow RAM |
1551 | */ | |
bc7f75fa AK |
1552 | if (dev_spec->shadow_ram[i].modified) { |
1553 | data = dev_spec->shadow_ram[i].value; | |
1554 | } else { | |
e243455d BA |
1555 | ret_val = e1000_read_flash_word_ich8lan(hw, i + |
1556 | old_bank_offset, | |
1557 | &data); | |
1558 | if (ret_val) | |
1559 | break; | |
bc7f75fa AK |
1560 | } |
1561 | ||
ad68076e BA |
1562 | /* |
1563 | * If the word is 0x13, then make sure the signature bits | |
bc7f75fa AK |
1564 | * (15:14) are 11b until the commit has completed. |
1565 | * This will allow us to write 10b which indicates the | |
1566 | * signature is valid. We want to do this after the write | |
1567 | * has completed so that we don't mark the segment valid | |
ad68076e BA |
1568 | * while the write is still in progress |
1569 | */ | |
bc7f75fa AK |
1570 | if (i == E1000_ICH_NVM_SIG_WORD) |
1571 | data |= E1000_ICH_NVM_SIG_MASK; | |
1572 | ||
1573 | /* Convert offset to bytes. */ | |
1574 | act_offset = (i + new_bank_offset) << 1; | |
1575 | ||
1576 | udelay(100); | |
1577 | /* Write the bytes to the new bank. */ | |
1578 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1579 | act_offset, | |
1580 | (u8)data); | |
1581 | if (ret_val) | |
1582 | break; | |
1583 | ||
1584 | udelay(100); | |
1585 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1586 | act_offset + 1, | |
1587 | (u8)(data >> 8)); | |
1588 | if (ret_val) | |
1589 | break; | |
1590 | } | |
1591 | ||
ad68076e BA |
1592 | /* |
1593 | * Don't bother writing the segment valid bits if sector | |
1594 | * programming failed. | |
1595 | */ | |
bc7f75fa | 1596 | if (ret_val) { |
4a770358 | 1597 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
bc7f75fa AK |
1598 | hw_dbg(hw, "Flash commit failed.\n"); |
1599 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1600 | goto out; |
bc7f75fa AK |
1601 | } |
1602 | ||
ad68076e BA |
1603 | /* |
1604 | * Finally validate the new segment by setting bit 15:14 | |
bc7f75fa AK |
1605 | * to 10b in word 0x13 , this can be done without an |
1606 | * erase as well since these bits are 11 to start with | |
ad68076e BA |
1607 | * and we need to change bit 14 to 0b |
1608 | */ | |
bc7f75fa | 1609 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
e243455d BA |
1610 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
1611 | if (ret_val) { | |
1612 | e1000_release_swflag_ich8lan(hw); | |
1613 | goto out; | |
1614 | } | |
bc7f75fa AK |
1615 | data &= 0xBFFF; |
1616 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1617 | act_offset * 2 + 1, | |
1618 | (u8)(data >> 8)); | |
1619 | if (ret_val) { | |
1620 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1621 | goto out; |
bc7f75fa AK |
1622 | } |
1623 | ||
ad68076e BA |
1624 | /* |
1625 | * And invalidate the previously valid segment by setting | |
bc7f75fa AK |
1626 | * its signature word (0x13) high_byte to 0b. This can be |
1627 | * done without an erase because flash erase sets all bits | |
ad68076e BA |
1628 | * to 1's. We can write 1's to 0's without an erase |
1629 | */ | |
bc7f75fa AK |
1630 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
1631 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
1632 | if (ret_val) { | |
1633 | e1000_release_swflag_ich8lan(hw); | |
e243455d | 1634 | goto out; |
bc7f75fa AK |
1635 | } |
1636 | ||
1637 | /* Great! Everything worked, we can now clear the cached entries. */ | |
1638 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
1639 | dev_spec->shadow_ram[i].modified = 0; | |
1640 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
1641 | } | |
1642 | ||
1643 | e1000_release_swflag_ich8lan(hw); | |
1644 | ||
ad68076e BA |
1645 | /* |
1646 | * Reload the EEPROM, or else modifications will not appear | |
bc7f75fa AK |
1647 | * until after the next adapter reset. |
1648 | */ | |
1649 | e1000e_reload_nvm(hw); | |
1650 | msleep(10); | |
1651 | ||
e243455d BA |
1652 | out: |
1653 | if (ret_val) | |
1654 | hw_dbg(hw, "NVM update error: %d\n", ret_val); | |
1655 | ||
bc7f75fa AK |
1656 | return ret_val; |
1657 | } | |
1658 | ||
1659 | /** | |
1660 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
1661 | * @hw: pointer to the HW structure | |
1662 | * | |
1663 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
1664 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
1665 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
1666 | **/ | |
1667 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1668 | { | |
1669 | s32 ret_val; | |
1670 | u16 data; | |
1671 | ||
ad68076e BA |
1672 | /* |
1673 | * Read 0x19 and check bit 6. If this bit is 0, the checksum | |
bc7f75fa AK |
1674 | * needs to be fixed. This bit is an indication that the NVM |
1675 | * was prepared by OEM software and did not calculate the | |
1676 | * checksum...a likely scenario. | |
1677 | */ | |
1678 | ret_val = e1000_read_nvm(hw, 0x19, 1, &data); | |
1679 | if (ret_val) | |
1680 | return ret_val; | |
1681 | ||
1682 | if ((data & 0x40) == 0) { | |
1683 | data |= 0x40; | |
1684 | ret_val = e1000_write_nvm(hw, 0x19, 1, &data); | |
1685 | if (ret_val) | |
1686 | return ret_val; | |
1687 | ret_val = e1000e_update_nvm_checksum(hw); | |
1688 | if (ret_val) | |
1689 | return ret_val; | |
1690 | } | |
1691 | ||
1692 | return e1000e_validate_nvm_checksum_generic(hw); | |
1693 | } | |
1694 | ||
4a770358 BA |
1695 | /** |
1696 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only | |
1697 | * @hw: pointer to the HW structure | |
1698 | * | |
1699 | * To prevent malicious write/erase of the NVM, set it to be read-only | |
1700 | * so that the hardware ignores all write/erase cycles of the NVM via | |
1701 | * the flash control registers. The shadow-ram copy of the NVM will | |
1702 | * still be updated, however any updates to this copy will not stick | |
1703 | * across driver reloads. | |
1704 | **/ | |
1705 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |
1706 | { | |
1707 | union ich8_flash_protected_range pr0; | |
1708 | union ich8_hws_flash_status hsfsts; | |
1709 | u32 gfpreg; | |
1710 | s32 ret_val; | |
1711 | ||
1712 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1713 | if (ret_val) | |
1714 | return; | |
1715 | ||
1716 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
1717 | ||
1718 | /* Write-protect GbE Sector of NVM */ | |
1719 | pr0.regval = er32flash(ICH_FLASH_PR0); | |
1720 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; | |
1721 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); | |
1722 | pr0.range.wpe = true; | |
1723 | ew32flash(ICH_FLASH_PR0, pr0.regval); | |
1724 | ||
1725 | /* | |
1726 | * Lock down a subset of GbE Flash Control Registers, e.g. | |
1727 | * PR0 to prevent the write-protection from being lifted. | |
1728 | * Once FLOCKDN is set, the registers protected by it cannot | |
1729 | * be written until FLOCKDN is cleared by a hardware reset. | |
1730 | */ | |
1731 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1732 | hsfsts.hsf_status.flockdn = true; | |
1733 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
1734 | ||
1735 | e1000_release_swflag_ich8lan(hw); | |
1736 | } | |
1737 | ||
bc7f75fa AK |
1738 | /** |
1739 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
1740 | * @hw: pointer to the HW structure | |
1741 | * @offset: The offset (in bytes) of the byte/word to read. | |
1742 | * @size: Size of data to read, 1=byte 2=word | |
1743 | * @data: The byte(s) to write to the NVM. | |
1744 | * | |
1745 | * Writes one/two bytes to the NVM using the flash access registers. | |
1746 | **/ | |
1747 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1748 | u8 size, u16 data) | |
1749 | { | |
1750 | union ich8_hws_flash_status hsfsts; | |
1751 | union ich8_hws_flash_ctrl hsflctl; | |
1752 | u32 flash_linear_addr; | |
1753 | u32 flash_data = 0; | |
1754 | s32 ret_val; | |
1755 | u8 count = 0; | |
1756 | ||
1757 | if (size < 1 || size > 2 || data > size * 0xff || | |
1758 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1759 | return -E1000_ERR_NVM; | |
1760 | ||
1761 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1762 | hw->nvm.flash_base_addr; | |
1763 | ||
1764 | do { | |
1765 | udelay(1); | |
1766 | /* Steps */ | |
1767 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1768 | if (ret_val) | |
1769 | break; | |
1770 | ||
1771 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1772 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1773 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
1774 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
1775 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1776 | ||
1777 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1778 | ||
1779 | if (size == 1) | |
1780 | flash_data = (u32)data & 0x00FF; | |
1781 | else | |
1782 | flash_data = (u32)data; | |
1783 | ||
1784 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
1785 | ||
ad68076e BA |
1786 | /* |
1787 | * check if FCERR is set to 1 , if set to 1, clear it | |
1788 | * and try the whole sequence a few more times else done | |
1789 | */ | |
bc7f75fa AK |
1790 | ret_val = e1000_flash_cycle_ich8lan(hw, |
1791 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
1792 | if (!ret_val) | |
1793 | break; | |
1794 | ||
ad68076e BA |
1795 | /* |
1796 | * If we're here, then things are most likely | |
bc7f75fa AK |
1797 | * completely hosed, but if the error condition |
1798 | * is detected, it won't hurt to give it another | |
1799 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1800 | */ | |
1801 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1802 | if (hsfsts.hsf_status.flcerr == 1) | |
1803 | /* Repeat for some time before giving up. */ | |
1804 | continue; | |
1805 | if (hsfsts.hsf_status.flcdone == 0) { | |
1806 | hw_dbg(hw, "Timeout error - flash cycle " | |
1807 | "did not complete."); | |
1808 | break; | |
1809 | } | |
1810 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1811 | ||
1812 | return ret_val; | |
1813 | } | |
1814 | ||
1815 | /** | |
1816 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
1817 | * @hw: pointer to the HW structure | |
1818 | * @offset: The index of the byte to read. | |
1819 | * @data: The byte to write to the NVM. | |
1820 | * | |
1821 | * Writes a single byte to the NVM using the flash access registers. | |
1822 | **/ | |
1823 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1824 | u8 data) | |
1825 | { | |
1826 | u16 word = (u16)data; | |
1827 | ||
1828 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
1829 | } | |
1830 | ||
1831 | /** | |
1832 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
1833 | * @hw: pointer to the HW structure | |
1834 | * @offset: The offset of the byte to write. | |
1835 | * @byte: The byte to write to the NVM. | |
1836 | * | |
1837 | * Writes a single byte to the NVM using the flash access registers. | |
1838 | * Goes through a retry algorithm before giving up. | |
1839 | **/ | |
1840 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
1841 | u32 offset, u8 byte) | |
1842 | { | |
1843 | s32 ret_val; | |
1844 | u16 program_retries; | |
1845 | ||
1846 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1847 | if (!ret_val) | |
1848 | return ret_val; | |
1849 | ||
1850 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
1851 | hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); | |
1852 | udelay(100); | |
1853 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1854 | if (!ret_val) | |
1855 | break; | |
1856 | } | |
1857 | if (program_retries == 100) | |
1858 | return -E1000_ERR_NVM; | |
1859 | ||
1860 | return 0; | |
1861 | } | |
1862 | ||
1863 | /** | |
1864 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
1865 | * @hw: pointer to the HW structure | |
1866 | * @bank: 0 for first bank, 1 for second bank, etc. | |
1867 | * | |
1868 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
1869 | * bank N is 4096 * N + flash_reg_addr. | |
1870 | **/ | |
1871 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
1872 | { | |
1873 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1874 | union ich8_hws_flash_status hsfsts; | |
1875 | union ich8_hws_flash_ctrl hsflctl; | |
1876 | u32 flash_linear_addr; | |
1877 | /* bank size is in 16bit words - adjust to bytes */ | |
1878 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
1879 | s32 ret_val; | |
1880 | s32 count = 0; | |
1881 | s32 iteration; | |
1882 | s32 sector_size; | |
1883 | s32 j; | |
1884 | ||
1885 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1886 | ||
ad68076e BA |
1887 | /* |
1888 | * Determine HW Sector size: Read BERASE bits of hw flash status | |
1889 | * register | |
1890 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
bc7f75fa AK |
1891 | * consecutive sectors. The start index for the nth Hw sector |
1892 | * can be calculated as = bank * 4096 + n * 256 | |
1893 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
1894 | * The start index for the nth Hw sector can be calculated | |
1895 | * as = bank * 4096 | |
1896 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
1897 | * (ich9 only, otherwise error condition) | |
1898 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
1899 | */ | |
1900 | switch (hsfsts.hsf_status.berasesz) { | |
1901 | case 0: | |
1902 | /* Hw sector size 256 */ | |
1903 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
1904 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
1905 | break; | |
1906 | case 1: | |
1907 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
1908 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; | |
1909 | break; | |
1910 | case 2: | |
1911 | if (hw->mac.type == e1000_ich9lan) { | |
1912 | sector_size = ICH_FLASH_SEG_SIZE_8K; | |
1913 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; | |
1914 | } else { | |
1915 | return -E1000_ERR_NVM; | |
1916 | } | |
1917 | break; | |
1918 | case 3: | |
1919 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
1920 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; | |
1921 | break; | |
1922 | default: | |
1923 | return -E1000_ERR_NVM; | |
1924 | } | |
1925 | ||
1926 | /* Start with the base address, then add the sector offset. */ | |
1927 | flash_linear_addr = hw->nvm.flash_base_addr; | |
1928 | flash_linear_addr += (bank) ? (sector_size * iteration) : 0; | |
1929 | ||
1930 | for (j = 0; j < iteration ; j++) { | |
1931 | do { | |
1932 | /* Steps */ | |
1933 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1934 | if (ret_val) | |
1935 | return ret_val; | |
1936 | ||
ad68076e BA |
1937 | /* |
1938 | * Write a value 11 (block Erase) in Flash | |
1939 | * Cycle field in hw flash control | |
1940 | */ | |
bc7f75fa AK |
1941 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
1942 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
1943 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1944 | ||
ad68076e BA |
1945 | /* |
1946 | * Write the last 24 bits of an index within the | |
bc7f75fa AK |
1947 | * block into Flash Linear address field in Flash |
1948 | * Address. | |
1949 | */ | |
1950 | flash_linear_addr += (j * sector_size); | |
1951 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1952 | ||
1953 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1954 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); | |
1955 | if (ret_val == 0) | |
1956 | break; | |
1957 | ||
ad68076e BA |
1958 | /* |
1959 | * Check if FCERR is set to 1. If 1, | |
bc7f75fa | 1960 | * clear it and try the whole sequence |
ad68076e BA |
1961 | * a few more times else Done |
1962 | */ | |
bc7f75fa AK |
1963 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
1964 | if (hsfsts.hsf_status.flcerr == 1) | |
ad68076e | 1965 | /* repeat for some time before giving up */ |
bc7f75fa AK |
1966 | continue; |
1967 | else if (hsfsts.hsf_status.flcdone == 0) | |
1968 | return ret_val; | |
1969 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1970 | } | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | /** | |
1976 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
1977 | * @hw: pointer to the HW structure | |
1978 | * @data: Pointer to the LED settings | |
1979 | * | |
1980 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
1981 | * settings is all 0's or F's, set the LED default to a valid LED default | |
1982 | * setting. | |
1983 | **/ | |
1984 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
1985 | { | |
1986 | s32 ret_val; | |
1987 | ||
1988 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1989 | if (ret_val) { | |
1990 | hw_dbg(hw, "NVM Read Error\n"); | |
1991 | return ret_val; | |
1992 | } | |
1993 | ||
1994 | if (*data == ID_LED_RESERVED_0000 || | |
1995 | *data == ID_LED_RESERVED_FFFF) | |
1996 | *data = ID_LED_DEFAULT_ICH8LAN; | |
1997 | ||
1998 | return 0; | |
1999 | } | |
2000 | ||
a4f58f54 BA |
2001 | /** |
2002 | * e1000_id_led_init_pchlan - store LED configurations | |
2003 | * @hw: pointer to the HW structure | |
2004 | * | |
2005 | * PCH does not control LEDs via the LEDCTL register, rather it uses | |
2006 | * the PHY LED configuration register. | |
2007 | * | |
2008 | * PCH also does not have an "always on" or "always off" mode which | |
2009 | * complicates the ID feature. Instead of using the "on" mode to indicate | |
2010 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), | |
2011 | * use "link_up" mode. The LEDs will still ID on request if there is no | |
2012 | * link based on logic in e1000_led_[on|off]_pchlan(). | |
2013 | **/ | |
2014 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |
2015 | { | |
2016 | struct e1000_mac_info *mac = &hw->mac; | |
2017 | s32 ret_val; | |
2018 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; | |
2019 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; | |
2020 | u16 data, i, temp, shift; | |
2021 | ||
2022 | /* Get default ID LED modes */ | |
2023 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | |
2024 | if (ret_val) | |
2025 | goto out; | |
2026 | ||
2027 | mac->ledctl_default = er32(LEDCTL); | |
2028 | mac->ledctl_mode1 = mac->ledctl_default; | |
2029 | mac->ledctl_mode2 = mac->ledctl_default; | |
2030 | ||
2031 | for (i = 0; i < 4; i++) { | |
2032 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; | |
2033 | shift = (i * 5); | |
2034 | switch (temp) { | |
2035 | case ID_LED_ON1_DEF2: | |
2036 | case ID_LED_ON1_ON2: | |
2037 | case ID_LED_ON1_OFF2: | |
2038 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
2039 | mac->ledctl_mode1 |= (ledctl_on << shift); | |
2040 | break; | |
2041 | case ID_LED_OFF1_DEF2: | |
2042 | case ID_LED_OFF1_ON2: | |
2043 | case ID_LED_OFF1_OFF2: | |
2044 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
2045 | mac->ledctl_mode1 |= (ledctl_off << shift); | |
2046 | break; | |
2047 | default: | |
2048 | /* Do nothing */ | |
2049 | break; | |
2050 | } | |
2051 | switch (temp) { | |
2052 | case ID_LED_DEF1_ON2: | |
2053 | case ID_LED_ON1_ON2: | |
2054 | case ID_LED_OFF1_ON2: | |
2055 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
2056 | mac->ledctl_mode2 |= (ledctl_on << shift); | |
2057 | break; | |
2058 | case ID_LED_DEF1_OFF2: | |
2059 | case ID_LED_ON1_OFF2: | |
2060 | case ID_LED_OFF1_OFF2: | |
2061 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
2062 | mac->ledctl_mode2 |= (ledctl_off << shift); | |
2063 | break; | |
2064 | default: | |
2065 | /* Do nothing */ | |
2066 | break; | |
2067 | } | |
2068 | } | |
2069 | ||
2070 | out: | |
2071 | return ret_val; | |
2072 | } | |
2073 | ||
bc7f75fa AK |
2074 | /** |
2075 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
2076 | * @hw: pointer to the HW structure | |
2077 | * | |
2078 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
2079 | * register, so the the bus width is hard coded. | |
2080 | **/ | |
2081 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
2082 | { | |
2083 | struct e1000_bus_info *bus = &hw->bus; | |
2084 | s32 ret_val; | |
2085 | ||
2086 | ret_val = e1000e_get_bus_info_pcie(hw); | |
2087 | ||
ad68076e BA |
2088 | /* |
2089 | * ICH devices are "PCI Express"-ish. They have | |
bc7f75fa AK |
2090 | * a configuration space, but do not contain |
2091 | * PCI Express Capability registers, so bus width | |
2092 | * must be hardcoded. | |
2093 | */ | |
2094 | if (bus->width == e1000_bus_width_unknown) | |
2095 | bus->width = e1000_bus_width_pcie_x1; | |
2096 | ||
2097 | return ret_val; | |
2098 | } | |
2099 | ||
2100 | /** | |
2101 | * e1000_reset_hw_ich8lan - Reset the hardware | |
2102 | * @hw: pointer to the HW structure | |
2103 | * | |
2104 | * Does a full reset of the hardware which includes a reset of the PHY and | |
2105 | * MAC. | |
2106 | **/ | |
2107 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
2108 | { | |
2109 | u32 ctrl, icr, kab; | |
2110 | s32 ret_val; | |
2111 | ||
ad68076e BA |
2112 | /* |
2113 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
2114 | * on the last TLP read/write transaction when MAC is reset. |
2115 | */ | |
2116 | ret_val = e1000e_disable_pcie_master(hw); | |
2117 | if (ret_val) { | |
2118 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
2119 | } | |
2120 | ||
2121 | hw_dbg(hw, "Masking off all interrupts\n"); | |
2122 | ew32(IMC, 0xffffffff); | |
2123 | ||
ad68076e BA |
2124 | /* |
2125 | * Disable the Transmit and Receive units. Then delay to allow | |
bc7f75fa AK |
2126 | * any pending transactions to complete before we hit the MAC |
2127 | * with the global reset. | |
2128 | */ | |
2129 | ew32(RCTL, 0); | |
2130 | ew32(TCTL, E1000_TCTL_PSP); | |
2131 | e1e_flush(); | |
2132 | ||
2133 | msleep(10); | |
2134 | ||
2135 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
2136 | if (hw->mac.type == e1000_ich8lan) { | |
2137 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
2138 | ew32(PBA, E1000_PBA_8K); | |
2139 | /* Set Packet Buffer Size to 16k. */ | |
2140 | ew32(PBS, E1000_PBS_16K); | |
2141 | } | |
2142 | ||
2143 | ctrl = er32(CTRL); | |
2144 | ||
2145 | if (!e1000_check_reset_block(hw)) { | |
ad68076e BA |
2146 | /* |
2147 | * PHY HW reset requires MAC CORE reset at the same | |
bc7f75fa AK |
2148 | * time to make sure the interface between MAC and the |
2149 | * external PHY is reset. | |
2150 | */ | |
2151 | ctrl |= E1000_CTRL_PHY_RST; | |
2152 | } | |
2153 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
30bb0e0d | 2154 | /* Whether or not the swflag was acquired, we need to reset the part */ |
0285c8dc | 2155 | hw_dbg(hw, "Issuing a global reset to ich8lan\n"); |
bc7f75fa AK |
2156 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
2157 | msleep(20); | |
2158 | ||
30bb0e0d JK |
2159 | if (!ret_val) { |
2160 | /* release the swflag because it is not reset by | |
2161 | * hardware reset | |
2162 | */ | |
2163 | e1000_release_swflag_ich8lan(hw); | |
2164 | } | |
37f40239 | 2165 | |
bc7f75fa AK |
2166 | ret_val = e1000e_get_auto_rd_done(hw); |
2167 | if (ret_val) { | |
2168 | /* | |
2169 | * When auto config read does not complete, do not | |
2170 | * return with an error. This can happen in situations | |
2171 | * where there is no eeprom and prevents getting link. | |
2172 | */ | |
2173 | hw_dbg(hw, "Auto Read Done did not complete\n"); | |
2174 | } | |
2175 | ||
2176 | ew32(IMC, 0xffffffff); | |
2177 | icr = er32(ICR); | |
2178 | ||
2179 | kab = er32(KABGTXD); | |
2180 | kab |= E1000_KABGTXD_BGSQLBIAS; | |
2181 | ew32(KABGTXD, kab); | |
2182 | ||
a4f58f54 BA |
2183 | if (hw->mac.type == e1000_pchlan) |
2184 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | |
2185 | ||
bc7f75fa AK |
2186 | return ret_val; |
2187 | } | |
2188 | ||
2189 | /** | |
2190 | * e1000_init_hw_ich8lan - Initialize the hardware | |
2191 | * @hw: pointer to the HW structure | |
2192 | * | |
2193 | * Prepares the hardware for transmit and receive by doing the following: | |
2194 | * - initialize hardware bits | |
2195 | * - initialize LED identification | |
2196 | * - setup receive address registers | |
2197 | * - setup flow control | |
489815ce | 2198 | * - setup transmit descriptors |
bc7f75fa AK |
2199 | * - clear statistics |
2200 | **/ | |
2201 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
2202 | { | |
2203 | struct e1000_mac_info *mac = &hw->mac; | |
2204 | u32 ctrl_ext, txdctl, snoop; | |
2205 | s32 ret_val; | |
2206 | u16 i; | |
2207 | ||
2208 | e1000_initialize_hw_bits_ich8lan(hw); | |
2209 | ||
2210 | /* Initialize identification LED */ | |
a4f58f54 | 2211 | ret_val = mac->ops.id_led_init(hw); |
bc7f75fa AK |
2212 | if (ret_val) { |
2213 | hw_dbg(hw, "Error initializing identification LED\n"); | |
2214 | return ret_val; | |
2215 | } | |
2216 | ||
2217 | /* Setup the receive address. */ | |
2218 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
2219 | ||
2220 | /* Zero out the Multicast HASH table */ | |
2221 | hw_dbg(hw, "Zeroing the MTA\n"); | |
2222 | for (i = 0; i < mac->mta_reg_count; i++) | |
2223 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
2224 | ||
2225 | /* Setup link and flow control */ | |
2226 | ret_val = e1000_setup_link_ich8lan(hw); | |
2227 | ||
2228 | /* Set the transmit descriptor write-back policy for both queues */ | |
e9ec2c0f | 2229 | txdctl = er32(TXDCTL(0)); |
bc7f75fa AK |
2230 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
2231 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2232 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
2233 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f JK |
2234 | ew32(TXDCTL(0), txdctl); |
2235 | txdctl = er32(TXDCTL(1)); | |
bc7f75fa AK |
2236 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
2237 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2238 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
2239 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f | 2240 | ew32(TXDCTL(1), txdctl); |
bc7f75fa | 2241 | |
ad68076e BA |
2242 | /* |
2243 | * ICH8 has opposite polarity of no_snoop bits. | |
2244 | * By default, we should use snoop behavior. | |
2245 | */ | |
bc7f75fa AK |
2246 | if (mac->type == e1000_ich8lan) |
2247 | snoop = PCIE_ICH8_SNOOP_ALL; | |
2248 | else | |
2249 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); | |
2250 | e1000e_set_pcie_no_snoop(hw, snoop); | |
2251 | ||
2252 | ctrl_ext = er32(CTRL_EXT); | |
2253 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
2254 | ew32(CTRL_EXT, ctrl_ext); | |
2255 | ||
a4f58f54 BA |
2256 | /* |
2257 | * The 82578 Rx buffer will stall if wakeup is enabled in host and | |
2258 | * the ME. Reading the BM_WUC register will clear the host wakeup bit. | |
2259 | * Reset the phy after disabling host wakeup to reset the Rx buffer. | |
2260 | */ | |
2261 | if (hw->phy.type == e1000_phy_82578) { | |
2262 | e1e_rphy(hw, BM_WUC, &i); | |
2263 | e1000e_phy_hw_reset_generic(hw); | |
2264 | } | |
2265 | ||
ad68076e BA |
2266 | /* |
2267 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
2268 | * important that we do this after we have tried to establish link |
2269 | * because the symbol error count will increment wildly if there | |
2270 | * is no link. | |
2271 | */ | |
2272 | e1000_clear_hw_cntrs_ich8lan(hw); | |
2273 | ||
2274 | return 0; | |
2275 | } | |
2276 | /** | |
2277 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
2278 | * @hw: pointer to the HW structure | |
2279 | * | |
2280 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
2281 | * hardware for transmit and receive. | |
2282 | **/ | |
2283 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
2284 | { | |
2285 | u32 reg; | |
2286 | ||
2287 | /* Extended Device Control */ | |
2288 | reg = er32(CTRL_EXT); | |
2289 | reg |= (1 << 22); | |
a4f58f54 BA |
2290 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
2291 | if (hw->mac.type >= e1000_pchlan) | |
2292 | reg |= E1000_CTRL_EXT_PHYPDEN; | |
bc7f75fa AK |
2293 | ew32(CTRL_EXT, reg); |
2294 | ||
2295 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 2296 | reg = er32(TXDCTL(0)); |
bc7f75fa | 2297 | reg |= (1 << 22); |
e9ec2c0f | 2298 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
2299 | |
2300 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 2301 | reg = er32(TXDCTL(1)); |
bc7f75fa | 2302 | reg |= (1 << 22); |
e9ec2c0f | 2303 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
2304 | |
2305 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 2306 | reg = er32(TARC(0)); |
bc7f75fa AK |
2307 | if (hw->mac.type == e1000_ich8lan) |
2308 | reg |= (1 << 28) | (1 << 29); | |
2309 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
e9ec2c0f | 2310 | ew32(TARC(0), reg); |
bc7f75fa AK |
2311 | |
2312 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 2313 | reg = er32(TARC(1)); |
bc7f75fa AK |
2314 | if (er32(TCTL) & E1000_TCTL_MULR) |
2315 | reg &= ~(1 << 28); | |
2316 | else | |
2317 | reg |= (1 << 28); | |
2318 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
e9ec2c0f | 2319 | ew32(TARC(1), reg); |
bc7f75fa AK |
2320 | |
2321 | /* Device Status */ | |
2322 | if (hw->mac.type == e1000_ich8lan) { | |
2323 | reg = er32(STATUS); | |
2324 | reg &= ~(1 << 31); | |
2325 | ew32(STATUS, reg); | |
2326 | } | |
2327 | } | |
2328 | ||
2329 | /** | |
2330 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
2331 | * @hw: pointer to the HW structure | |
2332 | * | |
2333 | * Determines which flow control settings to use, then configures flow | |
2334 | * control. Calls the appropriate media-specific link configuration | |
2335 | * function. Assuming the adapter has a valid link partner, a valid link | |
2336 | * should be established. Assumes the hardware has previously been reset | |
2337 | * and the transmitter and receiver are not enabled. | |
2338 | **/ | |
2339 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
2340 | { | |
bc7f75fa AK |
2341 | s32 ret_val; |
2342 | ||
2343 | if (e1000_check_reset_block(hw)) | |
2344 | return 0; | |
2345 | ||
ad68076e BA |
2346 | /* |
2347 | * ICH parts do not have a word in the NVM to determine | |
bc7f75fa AK |
2348 | * the default flow control setting, so we explicitly |
2349 | * set it to full. | |
2350 | */ | |
37289d9c BA |
2351 | if (hw->fc.requested_mode == e1000_fc_default) { |
2352 | /* Workaround h/w hang when Tx flow control enabled */ | |
2353 | if (hw->mac.type == e1000_pchlan) | |
2354 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
2355 | else | |
2356 | hw->fc.requested_mode = e1000_fc_full; | |
2357 | } | |
bc7f75fa | 2358 | |
5c48ef3e BA |
2359 | /* |
2360 | * Save off the requested flow control mode for use later. Depending | |
2361 | * on the link partner's capabilities, we may or may not use this mode. | |
2362 | */ | |
2363 | hw->fc.current_mode = hw->fc.requested_mode; | |
bc7f75fa | 2364 | |
5c48ef3e BA |
2365 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", |
2366 | hw->fc.current_mode); | |
bc7f75fa AK |
2367 | |
2368 | /* Continue to configure the copper link. */ | |
2369 | ret_val = e1000_setup_copper_link_ich8lan(hw); | |
2370 | if (ret_val) | |
2371 | return ret_val; | |
2372 | ||
318a94d6 | 2373 | ew32(FCTTV, hw->fc.pause_time); |
a4f58f54 BA |
2374 | if ((hw->phy.type == e1000_phy_82578) || |
2375 | (hw->phy.type == e1000_phy_82577)) { | |
2376 | ret_val = hw->phy.ops.write_phy_reg(hw, | |
2377 | PHY_REG(BM_PORT_CTRL_PAGE, 27), | |
2378 | hw->fc.pause_time); | |
2379 | if (ret_val) | |
2380 | return ret_val; | |
2381 | } | |
bc7f75fa AK |
2382 | |
2383 | return e1000e_set_fc_watermarks(hw); | |
2384 | } | |
2385 | ||
2386 | /** | |
2387 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
2388 | * @hw: pointer to the HW structure | |
2389 | * | |
2390 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
2391 | * when polling the PHY, then call the generic setup_copper_link to finish | |
2392 | * configuring the copper link. | |
2393 | **/ | |
2394 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
2395 | { | |
2396 | u32 ctrl; | |
2397 | s32 ret_val; | |
2398 | u16 reg_data; | |
2399 | ||
2400 | ctrl = er32(CTRL); | |
2401 | ctrl |= E1000_CTRL_SLU; | |
2402 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2403 | ew32(CTRL, ctrl); | |
2404 | ||
ad68076e BA |
2405 | /* |
2406 | * Set the mac to wait the maximum time between each iteration | |
bc7f75fa | 2407 | * and increase the max iterations when polling the phy; |
ad68076e BA |
2408 | * this fixes erroneous timeouts at 10Mbps. |
2409 | */ | |
bc7f75fa AK |
2410 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
2411 | if (ret_val) | |
2412 | return ret_val; | |
2413 | ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
2414 | if (ret_val) | |
2415 | return ret_val; | |
2416 | reg_data |= 0x3F; | |
2417 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
2418 | if (ret_val) | |
2419 | return ret_val; | |
2420 | ||
a4f58f54 BA |
2421 | switch (hw->phy.type) { |
2422 | case e1000_phy_igp_3: | |
bc7f75fa AK |
2423 | ret_val = e1000e_copper_link_setup_igp(hw); |
2424 | if (ret_val) | |
2425 | return ret_val; | |
a4f58f54 BA |
2426 | break; |
2427 | case e1000_phy_bm: | |
2428 | case e1000_phy_82578: | |
97ac8cae BA |
2429 | ret_val = e1000e_copper_link_setup_m88(hw); |
2430 | if (ret_val) | |
2431 | return ret_val; | |
a4f58f54 BA |
2432 | break; |
2433 | case e1000_phy_82577: | |
2434 | ret_val = e1000_copper_link_setup_82577(hw); | |
2435 | if (ret_val) | |
2436 | return ret_val; | |
2437 | break; | |
2438 | case e1000_phy_ife: | |
2439 | ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, | |
2440 | ®_data); | |
97ac8cae BA |
2441 | if (ret_val) |
2442 | return ret_val; | |
2443 | ||
2444 | reg_data &= ~IFE_PMC_AUTO_MDIX; | |
2445 | ||
2446 | switch (hw->phy.mdix) { | |
2447 | case 1: | |
2448 | reg_data &= ~IFE_PMC_FORCE_MDIX; | |
2449 | break; | |
2450 | case 2: | |
2451 | reg_data |= IFE_PMC_FORCE_MDIX; | |
2452 | break; | |
2453 | case 0: | |
2454 | default: | |
2455 | reg_data |= IFE_PMC_AUTO_MDIX; | |
2456 | break; | |
2457 | } | |
a4f58f54 BA |
2458 | ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, |
2459 | reg_data); | |
97ac8cae BA |
2460 | if (ret_val) |
2461 | return ret_val; | |
a4f58f54 BA |
2462 | break; |
2463 | default: | |
2464 | break; | |
97ac8cae | 2465 | } |
bc7f75fa AK |
2466 | return e1000e_setup_copper_link(hw); |
2467 | } | |
2468 | ||
2469 | /** | |
2470 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
2471 | * @hw: pointer to the HW structure | |
2472 | * @speed: pointer to store current link speed | |
2473 | * @duplex: pointer to store the current link duplex | |
2474 | * | |
ad68076e | 2475 | * Calls the generic get_speed_and_duplex to retrieve the current link |
bc7f75fa AK |
2476 | * information and then calls the Kumeran lock loss workaround for links at |
2477 | * gigabit speeds. | |
2478 | **/ | |
2479 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
2480 | u16 *duplex) | |
2481 | { | |
2482 | s32 ret_val; | |
2483 | ||
2484 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
2485 | if (ret_val) | |
2486 | return ret_val; | |
2487 | ||
2488 | if ((hw->mac.type == e1000_ich8lan) && | |
2489 | (hw->phy.type == e1000_phy_igp_3) && | |
2490 | (*speed == SPEED_1000)) { | |
2491 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
2492 | } | |
2493 | ||
2494 | return ret_val; | |
2495 | } | |
2496 | ||
2497 | /** | |
2498 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
2499 | * @hw: pointer to the HW structure | |
2500 | * | |
2501 | * Work-around for 82566 Kumeran PCS lock loss: | |
2502 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
2503 | * speed is gigabit- | |
2504 | * 0) if workaround is optionally disabled do nothing | |
2505 | * 1) wait 1ms for Kumeran link to come up | |
2506 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
2507 | * 3) if not set the link is locked (all is good), otherwise... | |
2508 | * 4) reset the PHY | |
2509 | * 5) repeat up to 10 times | |
2510 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
2511 | **/ | |
2512 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
2513 | { | |
2514 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2515 | u32 phy_ctrl; | |
2516 | s32 ret_val; | |
2517 | u16 i, data; | |
2518 | bool link; | |
2519 | ||
2520 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
2521 | return 0; | |
2522 | ||
ad68076e BA |
2523 | /* |
2524 | * Make sure link is up before proceeding. If not just return. | |
bc7f75fa | 2525 | * Attempting this while link is negotiating fouled up link |
ad68076e BA |
2526 | * stability |
2527 | */ | |
bc7f75fa AK |
2528 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
2529 | if (!link) | |
2530 | return 0; | |
2531 | ||
2532 | for (i = 0; i < 10; i++) { | |
2533 | /* read once to clear */ | |
2534 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2535 | if (ret_val) | |
2536 | return ret_val; | |
2537 | /* and again to get new status */ | |
2538 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
2539 | if (ret_val) | |
2540 | return ret_val; | |
2541 | ||
2542 | /* check for PCS lock */ | |
2543 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
2544 | return 0; | |
2545 | ||
2546 | /* Issue PHY reset */ | |
2547 | e1000_phy_hw_reset(hw); | |
2548 | mdelay(5); | |
2549 | } | |
2550 | /* Disable GigE link negotiation */ | |
2551 | phy_ctrl = er32(PHY_CTRL); | |
2552 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2553 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2554 | ew32(PHY_CTRL, phy_ctrl); | |
2555 | ||
ad68076e BA |
2556 | /* |
2557 | * Call gig speed drop workaround on Gig disable before accessing | |
2558 | * any PHY registers | |
2559 | */ | |
bc7f75fa AK |
2560 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2561 | ||
2562 | /* unable to acquire PCS lock */ | |
2563 | return -E1000_ERR_PHY; | |
2564 | } | |
2565 | ||
2566 | /** | |
ad68076e | 2567 | * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
bc7f75fa | 2568 | * @hw: pointer to the HW structure |
489815ce | 2569 | * @state: boolean value used to set the current Kumeran workaround state |
bc7f75fa AK |
2570 | * |
2571 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE | |
2572 | * /disabled - FALSE). | |
2573 | **/ | |
2574 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
2575 | bool state) | |
2576 | { | |
2577 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2578 | ||
2579 | if (hw->mac.type != e1000_ich8lan) { | |
2580 | hw_dbg(hw, "Workaround applies to ICH8 only.\n"); | |
2581 | return; | |
2582 | } | |
2583 | ||
2584 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
2585 | } | |
2586 | ||
2587 | /** | |
2588 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
2589 | * @hw: pointer to the HW structure | |
2590 | * | |
2591 | * Workaround for 82566 power-down on D3 entry: | |
2592 | * 1) disable gigabit link | |
2593 | * 2) write VR power-down enable | |
2594 | * 3) read it back | |
2595 | * Continue if successful, else issue LCD reset and repeat | |
2596 | **/ | |
2597 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
2598 | { | |
2599 | u32 reg; | |
2600 | u16 data; | |
2601 | u8 retry = 0; | |
2602 | ||
2603 | if (hw->phy.type != e1000_phy_igp_3) | |
2604 | return; | |
2605 | ||
2606 | /* Try the workaround twice (if needed) */ | |
2607 | do { | |
2608 | /* Disable link */ | |
2609 | reg = er32(PHY_CTRL); | |
2610 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2611 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2612 | ew32(PHY_CTRL, reg); | |
2613 | ||
ad68076e BA |
2614 | /* |
2615 | * Call gig speed drop workaround on Gig disable before | |
2616 | * accessing any PHY registers | |
2617 | */ | |
bc7f75fa AK |
2618 | if (hw->mac.type == e1000_ich8lan) |
2619 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2620 | ||
2621 | /* Write VR power-down enable */ | |
2622 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2623 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2624 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
2625 | ||
2626 | /* Read it back and test */ | |
2627 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2628 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2629 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
2630 | break; | |
2631 | ||
2632 | /* Issue PHY reset and repeat at most one more time */ | |
2633 | reg = er32(CTRL); | |
2634 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
2635 | retry++; | |
2636 | } while (retry); | |
2637 | } | |
2638 | ||
2639 | /** | |
2640 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
2641 | * @hw: pointer to the HW structure | |
2642 | * | |
2643 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
489815ce | 2644 | * LPLU, Gig disable, MDIC PHY reset): |
bc7f75fa AK |
2645 | * 1) Set Kumeran Near-end loopback |
2646 | * 2) Clear Kumeran Near-end loopback | |
2647 | * Should only be called for ICH8[m] devices with IGP_3 Phy. | |
2648 | **/ | |
2649 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
2650 | { | |
2651 | s32 ret_val; | |
2652 | u16 reg_data; | |
2653 | ||
2654 | if ((hw->mac.type != e1000_ich8lan) || | |
2655 | (hw->phy.type != e1000_phy_igp_3)) | |
2656 | return; | |
2657 | ||
2658 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2659 | ®_data); | |
2660 | if (ret_val) | |
2661 | return; | |
2662 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2663 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2664 | reg_data); | |
2665 | if (ret_val) | |
2666 | return; | |
2667 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2668 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2669 | reg_data); | |
2670 | } | |
2671 | ||
97ac8cae BA |
2672 | /** |
2673 | * e1000e_disable_gig_wol_ich8lan - disable gig during WoL | |
2674 | * @hw: pointer to the HW structure | |
2675 | * | |
2676 | * During S0 to Sx transition, it is possible the link remains at gig | |
2677 | * instead of negotiating to a lower speed. Before going to Sx, set | |
2678 | * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation | |
2679 | * to a lower speed. | |
2680 | * | |
a4f58f54 | 2681 | * Should only be called for applicable parts. |
97ac8cae BA |
2682 | **/ |
2683 | void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) | |
2684 | { | |
2685 | u32 phy_ctrl; | |
2686 | ||
a4f58f54 BA |
2687 | switch (hw->mac.type) { |
2688 | case e1000_ich9lan: | |
2689 | case e1000_ich10lan: | |
2690 | case e1000_pchlan: | |
97ac8cae BA |
2691 | phy_ctrl = er32(PHY_CTRL); |
2692 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | | |
2693 | E1000_PHY_CTRL_GBE_DISABLE; | |
2694 | ew32(PHY_CTRL, phy_ctrl); | |
a4f58f54 BA |
2695 | |
2696 | /* Workaround SWFLAG unexpectedly set during S0->Sx */ | |
2697 | if (hw->mac.type == e1000_pchlan) | |
2698 | udelay(500); | |
2699 | default: | |
2700 | break; | |
97ac8cae BA |
2701 | } |
2702 | ||
2703 | return; | |
2704 | } | |
2705 | ||
bc7f75fa AK |
2706 | /** |
2707 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
2708 | * @hw: pointer to the HW structure | |
2709 | * | |
2710 | * Return the LED back to the default configuration. | |
2711 | **/ | |
2712 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
2713 | { | |
2714 | if (hw->phy.type == e1000_phy_ife) | |
2715 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
2716 | ||
2717 | ew32(LEDCTL, hw->mac.ledctl_default); | |
2718 | return 0; | |
2719 | } | |
2720 | ||
2721 | /** | |
489815ce | 2722 | * e1000_led_on_ich8lan - Turn LEDs on |
bc7f75fa AK |
2723 | * @hw: pointer to the HW structure |
2724 | * | |
489815ce | 2725 | * Turn on the LEDs. |
bc7f75fa AK |
2726 | **/ |
2727 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
2728 | { | |
2729 | if (hw->phy.type == e1000_phy_ife) | |
2730 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2731 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
2732 | ||
2733 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
2734 | return 0; | |
2735 | } | |
2736 | ||
2737 | /** | |
489815ce | 2738 | * e1000_led_off_ich8lan - Turn LEDs off |
bc7f75fa AK |
2739 | * @hw: pointer to the HW structure |
2740 | * | |
489815ce | 2741 | * Turn off the LEDs. |
bc7f75fa AK |
2742 | **/ |
2743 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
2744 | { | |
2745 | if (hw->phy.type == e1000_phy_ife) | |
2746 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2747 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
2748 | ||
2749 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
2750 | return 0; | |
2751 | } | |
2752 | ||
a4f58f54 BA |
2753 | /** |
2754 | * e1000_setup_led_pchlan - Configures SW controllable LED | |
2755 | * @hw: pointer to the HW structure | |
2756 | * | |
2757 | * This prepares the SW controllable LED for use. | |
2758 | **/ | |
2759 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) | |
2760 | { | |
2761 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, | |
2762 | (u16)hw->mac.ledctl_mode1); | |
2763 | } | |
2764 | ||
2765 | /** | |
2766 | * e1000_cleanup_led_pchlan - Restore the default LED operation | |
2767 | * @hw: pointer to the HW structure | |
2768 | * | |
2769 | * Return the LED back to the default configuration. | |
2770 | **/ | |
2771 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) | |
2772 | { | |
2773 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, | |
2774 | (u16)hw->mac.ledctl_default); | |
2775 | } | |
2776 | ||
2777 | /** | |
2778 | * e1000_led_on_pchlan - Turn LEDs on | |
2779 | * @hw: pointer to the HW structure | |
2780 | * | |
2781 | * Turn on the LEDs. | |
2782 | **/ | |
2783 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) | |
2784 | { | |
2785 | u16 data = (u16)hw->mac.ledctl_mode2; | |
2786 | u32 i, led; | |
2787 | ||
2788 | /* | |
2789 | * If no link, then turn LED on by setting the invert bit | |
2790 | * for each LED that's mode is "link_up" in ledctl_mode2. | |
2791 | */ | |
2792 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
2793 | for (i = 0; i < 3; i++) { | |
2794 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
2795 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
2796 | E1000_LEDCTL_MODE_LINK_UP) | |
2797 | continue; | |
2798 | if (led & E1000_PHY_LED0_IVRT) | |
2799 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
2800 | else | |
2801 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
2802 | } | |
2803 | } | |
2804 | ||
2805 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); | |
2806 | } | |
2807 | ||
2808 | /** | |
2809 | * e1000_led_off_pchlan - Turn LEDs off | |
2810 | * @hw: pointer to the HW structure | |
2811 | * | |
2812 | * Turn off the LEDs. | |
2813 | **/ | |
2814 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) | |
2815 | { | |
2816 | u16 data = (u16)hw->mac.ledctl_mode1; | |
2817 | u32 i, led; | |
2818 | ||
2819 | /* | |
2820 | * If no link, then turn LED off by clearing the invert bit | |
2821 | * for each LED that's mode is "link_up" in ledctl_mode1. | |
2822 | */ | |
2823 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
2824 | for (i = 0; i < 3; i++) { | |
2825 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
2826 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
2827 | E1000_LEDCTL_MODE_LINK_UP) | |
2828 | continue; | |
2829 | if (led & E1000_PHY_LED0_IVRT) | |
2830 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
2831 | else | |
2832 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data); | |
2837 | } | |
2838 | ||
f4187b56 BA |
2839 | /** |
2840 | * e1000_get_cfg_done_ich8lan - Read config done bit | |
2841 | * @hw: pointer to the HW structure | |
2842 | * | |
2843 | * Read the management control register for the config done bit for | |
2844 | * completion status. NOTE: silicon which is EEPROM-less will fail trying | |
2845 | * to read the config done bit, so an error is *ONLY* logged and returns | |
a4f58f54 | 2846 | * 0. If we were to return with error, EEPROM-less silicon |
f4187b56 BA |
2847 | * would not be able to be reset or change link. |
2848 | **/ | |
2849 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |
2850 | { | |
2851 | u32 bank = 0; | |
2852 | ||
2853 | e1000e_get_cfg_done(hw); | |
2854 | ||
2855 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ | |
a4f58f54 BA |
2856 | if ((hw->mac.type != e1000_ich10lan) && |
2857 | (hw->mac.type != e1000_pchlan)) { | |
f4187b56 BA |
2858 | if (((er32(EECD) & E1000_EECD_PRES) == 0) && |
2859 | (hw->phy.type == e1000_phy_igp_3)) { | |
2860 | e1000e_phy_init_script_igp3(hw); | |
2861 | } | |
2862 | } else { | |
2863 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | |
2864 | /* Maybe we should do a basic PHY config */ | |
2865 | hw_dbg(hw, "EEPROM not present\n"); | |
2866 | return -E1000_ERR_CONFIG; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
bc7f75fa AK |
2873 | /** |
2874 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
2875 | * @hw: pointer to the HW structure | |
2876 | * | |
2877 | * Clears hardware counters specific to the silicon family and calls | |
2878 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
2879 | **/ | |
2880 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
2881 | { | |
2882 | u32 temp; | |
a4f58f54 | 2883 | u16 phy_data; |
bc7f75fa AK |
2884 | |
2885 | e1000e_clear_hw_cntrs_base(hw); | |
2886 | ||
2887 | temp = er32(ALGNERRC); | |
2888 | temp = er32(RXERRC); | |
2889 | temp = er32(TNCRS); | |
2890 | temp = er32(CEXTERR); | |
2891 | temp = er32(TSCTC); | |
2892 | temp = er32(TSCTFC); | |
2893 | ||
2894 | temp = er32(MGTPRC); | |
2895 | temp = er32(MGTPDC); | |
2896 | temp = er32(MGTPTC); | |
2897 | ||
2898 | temp = er32(IAC); | |
2899 | temp = er32(ICRXOC); | |
2900 | ||
a4f58f54 BA |
2901 | /* Clear PHY statistics registers */ |
2902 | if ((hw->phy.type == e1000_phy_82578) || | |
2903 | (hw->phy.type == e1000_phy_82577)) { | |
2904 | hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data); | |
2905 | hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data); | |
2906 | hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); | |
2907 | hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); | |
2908 | hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data); | |
2909 | hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data); | |
2910 | hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); | |
2911 | hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); | |
2912 | hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data); | |
2913 | hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data); | |
2914 | hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data); | |
2915 | hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data); | |
2916 | hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); | |
2917 | hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); | |
2918 | } | |
bc7f75fa AK |
2919 | } |
2920 | ||
2921 | static struct e1000_mac_operations ich8_mac_ops = { | |
a4f58f54 | 2922 | .id_led_init = e1000e_id_led_init, |
4662e82b | 2923 | .check_mng_mode = e1000_check_mng_mode_ich8lan, |
bc7f75fa | 2924 | .check_for_link = e1000e_check_for_copper_link, |
a4f58f54 | 2925 | /* cleanup_led dependent on mac type */ |
bc7f75fa AK |
2926 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
2927 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
2928 | .get_link_up_info = e1000_get_link_up_info_ich8lan, | |
a4f58f54 BA |
2929 | /* led_on dependent on mac type */ |
2930 | /* led_off dependent on mac type */ | |
e2de3eb6 | 2931 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
2932 | .reset_hw = e1000_reset_hw_ich8lan, |
2933 | .init_hw = e1000_init_hw_ich8lan, | |
2934 | .setup_link = e1000_setup_link_ich8lan, | |
2935 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, | |
a4f58f54 | 2936 | /* id_led_init dependent on mac type */ |
bc7f75fa AK |
2937 | }; |
2938 | ||
2939 | static struct e1000_phy_operations ich8_phy_ops = { | |
2940 | .acquire_phy = e1000_acquire_swflag_ich8lan, | |
2941 | .check_reset_block = e1000_check_reset_block_ich8lan, | |
2942 | .commit_phy = NULL, | |
2943 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, | |
f4187b56 | 2944 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
bc7f75fa AK |
2945 | .get_cable_length = e1000e_get_cable_length_igp_2, |
2946 | .get_phy_info = e1000_get_phy_info_ich8lan, | |
2947 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
2948 | .release_phy = e1000_release_swflag_ich8lan, | |
2949 | .reset_phy = e1000_phy_hw_reset_ich8lan, | |
2950 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, | |
2951 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
2952 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
2953 | }; | |
2954 | ||
2955 | static struct e1000_nvm_operations ich8_nvm_ops = { | |
2956 | .acquire_nvm = e1000_acquire_swflag_ich8lan, | |
2957 | .read_nvm = e1000_read_nvm_ich8lan, | |
2958 | .release_nvm = e1000_release_swflag_ich8lan, | |
2959 | .update_nvm = e1000_update_nvm_checksum_ich8lan, | |
2960 | .valid_led_default = e1000_valid_led_default_ich8lan, | |
2961 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, | |
2962 | .write_nvm = e1000_write_nvm_ich8lan, | |
2963 | }; | |
2964 | ||
2965 | struct e1000_info e1000_ich8_info = { | |
2966 | .mac = e1000_ich8lan, | |
2967 | .flags = FLAG_HAS_WOL | |
97ac8cae | 2968 | | FLAG_IS_ICH |
bc7f75fa AK |
2969 | | FLAG_RX_CSUM_ENABLED |
2970 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2971 | | FLAG_HAS_AMT | |
2972 | | FLAG_HAS_FLASH | |
2973 | | FLAG_APME_IN_WUC, | |
2974 | .pba = 8, | |
2adc55c9 | 2975 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 2976 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
2977 | .mac_ops = &ich8_mac_ops, |
2978 | .phy_ops = &ich8_phy_ops, | |
2979 | .nvm_ops = &ich8_nvm_ops, | |
2980 | }; | |
2981 | ||
2982 | struct e1000_info e1000_ich9_info = { | |
2983 | .mac = e1000_ich9lan, | |
2984 | .flags = FLAG_HAS_JUMBO_FRAMES | |
97ac8cae | 2985 | | FLAG_IS_ICH |
bc7f75fa AK |
2986 | | FLAG_HAS_WOL |
2987 | | FLAG_RX_CSUM_ENABLED | |
2988 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2989 | | FLAG_HAS_AMT | |
2990 | | FLAG_HAS_ERT | |
2991 | | FLAG_HAS_FLASH | |
2992 | | FLAG_APME_IN_WUC, | |
2993 | .pba = 10, | |
2adc55c9 | 2994 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 2995 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
2996 | .mac_ops = &ich8_mac_ops, |
2997 | .phy_ops = &ich8_phy_ops, | |
2998 | .nvm_ops = &ich8_nvm_ops, | |
2999 | }; | |
3000 | ||
f4187b56 BA |
3001 | struct e1000_info e1000_ich10_info = { |
3002 | .mac = e1000_ich10lan, | |
3003 | .flags = FLAG_HAS_JUMBO_FRAMES | |
3004 | | FLAG_IS_ICH | |
3005 | | FLAG_HAS_WOL | |
3006 | | FLAG_RX_CSUM_ENABLED | |
3007 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3008 | | FLAG_HAS_AMT | |
3009 | | FLAG_HAS_ERT | |
3010 | | FLAG_HAS_FLASH | |
3011 | | FLAG_APME_IN_WUC, | |
3012 | .pba = 10, | |
2adc55c9 | 3013 | .max_hw_frame_size = DEFAULT_JUMBO, |
f4187b56 BA |
3014 | .get_variants = e1000_get_variants_ich8lan, |
3015 | .mac_ops = &ich8_mac_ops, | |
3016 | .phy_ops = &ich8_phy_ops, | |
3017 | .nvm_ops = &ich8_nvm_ops, | |
3018 | }; | |
a4f58f54 BA |
3019 | |
3020 | struct e1000_info e1000_pch_info = { | |
3021 | .mac = e1000_pchlan, | |
3022 | .flags = FLAG_IS_ICH | |
3023 | | FLAG_HAS_WOL | |
3024 | | FLAG_RX_CSUM_ENABLED | |
3025 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
3026 | | FLAG_HAS_AMT | |
3027 | | FLAG_HAS_FLASH | |
3028 | | FLAG_HAS_JUMBO_FRAMES | |
3029 | | FLAG_APME_IN_WUC, | |
3030 | .pba = 26, | |
3031 | .max_hw_frame_size = 4096, | |
3032 | .get_variants = e1000_get_variants_ich8lan, | |
3033 | .mac_ops = &ich8_mac_ops, | |
3034 | .phy_ops = &ich8_phy_ops, | |
3035 | .nvm_ops = &ich8_nvm_ops, | |
3036 | }; |