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3ec9c11d CL |
1 | /* |
2 | * Microchip ENC28J60 ethernet driver (MAC + PHY) | |
3 | * | |
4 | * Copyright (C) 2007 Eurek srl | |
5 | * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com> | |
6 | * based on enc28j60.c written by David Anders for 2.4 kernel version | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $ | |
14 | */ | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/fcntl.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/tcp.h> | |
29 | #include <linux/skbuff.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/spi/spi.h> | |
32 | ||
33 | #include "enc28j60_hw.h" | |
34 | ||
35 | #define DRV_NAME "enc28j60" | |
36 | #define DRV_VERSION "1.01" | |
37 | ||
38 | #define SPI_OPLEN 1 | |
39 | ||
40 | #define ENC28J60_MSG_DEFAULT \ | |
41 | (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK) | |
42 | ||
43 | /* Buffer size required for the largest SPI transfer (i.e., reading a | |
44 | * frame). */ | |
45 | #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN) | |
46 | ||
47 | #define TX_TIMEOUT (4 * HZ) | |
48 | ||
49 | /* Max TX retries in case of collision as suggested by errata datasheet */ | |
50 | #define MAX_TX_RETRYCOUNT 16 | |
51 | ||
52 | enum { | |
53 | RXFILTER_NORMAL, | |
54 | RXFILTER_MULTI, | |
55 | RXFILTER_PROMISC | |
56 | }; | |
57 | ||
58 | /* Driver local data */ | |
59 | struct enc28j60_net { | |
60 | struct net_device *netdev; | |
61 | struct spi_device *spi; | |
62 | struct mutex lock; | |
63 | struct sk_buff *tx_skb; | |
64 | struct work_struct tx_work; | |
65 | struct work_struct irq_work; | |
66 | struct work_struct setrx_work; | |
67 | struct work_struct restart_work; | |
68 | u8 bank; /* current register bank selected */ | |
69 | u16 next_pk_ptr; /* next packet pointer within FIFO */ | |
70 | u16 max_pk_counter; /* statistics: max packet counter */ | |
71 | u16 tx_retry_count; | |
72 | bool hw_enable; | |
73 | bool full_duplex; | |
74 | int rxfilter; | |
75 | u32 msg_enable; | |
76 | u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN]; | |
77 | }; | |
78 | ||
79 | /* use ethtool to change the level for any given device */ | |
80 | static struct { | |
81 | u32 msg_enable; | |
82 | } debug = { -1 }; | |
83 | ||
84 | /* | |
85 | * SPI read buffer | |
86 | * wait for the SPI transfer and copy received data to destination | |
87 | */ | |
88 | static int | |
89 | spi_read_buf(struct enc28j60_net *priv, int len, u8 *data) | |
90 | { | |
91 | u8 *rx_buf = priv->spi_transfer_buf + 4; | |
92 | u8 *tx_buf = priv->spi_transfer_buf; | |
93 | struct spi_transfer t = { | |
94 | .tx_buf = tx_buf, | |
95 | .rx_buf = rx_buf, | |
96 | .len = SPI_OPLEN + len, | |
97 | }; | |
98 | struct spi_message msg; | |
99 | int ret; | |
100 | ||
101 | tx_buf[0] = ENC28J60_READ_BUF_MEM; | |
102 | tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */ | |
103 | ||
104 | spi_message_init(&msg); | |
105 | spi_message_add_tail(&t, &msg); | |
106 | ret = spi_sync(priv->spi, &msg); | |
107 | if (ret == 0) { | |
108 | memcpy(data, &rx_buf[SPI_OPLEN], len); | |
109 | ret = msg.status; | |
110 | } | |
111 | if (ret && netif_msg_drv(priv)) | |
112 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 113 | __func__, ret); |
3ec9c11d CL |
114 | |
115 | return ret; | |
116 | } | |
117 | ||
118 | /* | |
119 | * SPI write buffer | |
120 | */ | |
121 | static int spi_write_buf(struct enc28j60_net *priv, int len, | |
122 | const u8 *data) | |
123 | { | |
124 | int ret; | |
125 | ||
126 | if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0) | |
127 | ret = -EINVAL; | |
128 | else { | |
129 | priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM; | |
130 | memcpy(&priv->spi_transfer_buf[1], data, len); | |
131 | ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1); | |
132 | if (ret && netif_msg_drv(priv)) | |
133 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 134 | __func__, ret); |
3ec9c11d CL |
135 | } |
136 | return ret; | |
137 | } | |
138 | ||
139 | /* | |
140 | * basic SPI read operation | |
141 | */ | |
142 | static u8 spi_read_op(struct enc28j60_net *priv, u8 op, | |
143 | u8 addr) | |
144 | { | |
145 | u8 tx_buf[2]; | |
146 | u8 rx_buf[4]; | |
147 | u8 val = 0; | |
148 | int ret; | |
149 | int slen = SPI_OPLEN; | |
150 | ||
151 | /* do dummy read if needed */ | |
152 | if (addr & SPRD_MASK) | |
153 | slen++; | |
154 | ||
155 | tx_buf[0] = op | (addr & ADDR_MASK); | |
156 | ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen); | |
157 | if (ret) | |
158 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 159 | __func__, ret); |
3ec9c11d CL |
160 | else |
161 | val = rx_buf[slen - 1]; | |
162 | ||
163 | return val; | |
164 | } | |
165 | ||
166 | /* | |
167 | * basic SPI write operation | |
168 | */ | |
169 | static int spi_write_op(struct enc28j60_net *priv, u8 op, | |
170 | u8 addr, u8 val) | |
171 | { | |
172 | int ret; | |
173 | ||
174 | priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK); | |
175 | priv->spi_transfer_buf[1] = val; | |
176 | ret = spi_write(priv->spi, priv->spi_transfer_buf, 2); | |
177 | if (ret && netif_msg_drv(priv)) | |
178 | printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n", | |
b39d66a8 | 179 | __func__, ret); |
3ec9c11d CL |
180 | return ret; |
181 | } | |
182 | ||
183 | static void enc28j60_soft_reset(struct enc28j60_net *priv) | |
184 | { | |
185 | if (netif_msg_hw(priv)) | |
b39d66a8 | 186 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
187 | |
188 | spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET); | |
189 | /* Errata workaround #1, CLKRDY check is unreliable, | |
190 | * delay at least 1 mS instead */ | |
191 | udelay(2000); | |
192 | } | |
193 | ||
194 | /* | |
195 | * select the current register bank if necessary | |
196 | */ | |
197 | static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr) | |
198 | { | |
199 | if ((addr & BANK_MASK) != priv->bank) { | |
200 | u8 b = (addr & BANK_MASK) >> 5; | |
201 | ||
202 | if (b != (ECON1_BSEL1 | ECON1_BSEL0)) | |
203 | spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1, | |
204 | ECON1_BSEL1 | ECON1_BSEL0); | |
205 | if (b != 0) | |
206 | spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b); | |
207 | priv->bank = (addr & BANK_MASK); | |
208 | } | |
209 | } | |
210 | ||
211 | /* | |
212 | * Register access routines through the SPI bus. | |
213 | * Every register access comes in two flavours: | |
214 | * - nolock_xxx: caller needs to invoke mutex_lock, usually to access | |
215 | * atomically more than one register | |
216 | * - locked_xxx: caller doesn't need to invoke mutex_lock, single access | |
217 | * | |
218 | * Some registers can be accessed through the bit field clear and | |
219 | * bit field set to avoid a read modify write cycle. | |
220 | */ | |
221 | ||
222 | /* | |
223 | * Register bit field Set | |
224 | */ | |
225 | static void nolock_reg_bfset(struct enc28j60_net *priv, | |
226 | u8 addr, u8 mask) | |
227 | { | |
228 | enc28j60_set_bank(priv, addr); | |
229 | spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask); | |
230 | } | |
231 | ||
232 | static void locked_reg_bfset(struct enc28j60_net *priv, | |
233 | u8 addr, u8 mask) | |
234 | { | |
235 | mutex_lock(&priv->lock); | |
236 | nolock_reg_bfset(priv, addr, mask); | |
237 | mutex_unlock(&priv->lock); | |
238 | } | |
239 | ||
240 | /* | |
241 | * Register bit field Clear | |
242 | */ | |
243 | static void nolock_reg_bfclr(struct enc28j60_net *priv, | |
244 | u8 addr, u8 mask) | |
245 | { | |
246 | enc28j60_set_bank(priv, addr); | |
247 | spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask); | |
248 | } | |
249 | ||
250 | static void locked_reg_bfclr(struct enc28j60_net *priv, | |
251 | u8 addr, u8 mask) | |
252 | { | |
253 | mutex_lock(&priv->lock); | |
254 | nolock_reg_bfclr(priv, addr, mask); | |
255 | mutex_unlock(&priv->lock); | |
256 | } | |
257 | ||
258 | /* | |
259 | * Register byte read | |
260 | */ | |
261 | static int nolock_regb_read(struct enc28j60_net *priv, | |
262 | u8 address) | |
263 | { | |
264 | enc28j60_set_bank(priv, address); | |
265 | return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); | |
266 | } | |
267 | ||
268 | static int locked_regb_read(struct enc28j60_net *priv, | |
269 | u8 address) | |
270 | { | |
271 | int ret; | |
272 | ||
273 | mutex_lock(&priv->lock); | |
274 | ret = nolock_regb_read(priv, address); | |
275 | mutex_unlock(&priv->lock); | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
280 | /* | |
281 | * Register word read | |
282 | */ | |
283 | static int nolock_regw_read(struct enc28j60_net *priv, | |
284 | u8 address) | |
285 | { | |
286 | int rl, rh; | |
287 | ||
288 | enc28j60_set_bank(priv, address); | |
289 | rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address); | |
290 | rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1); | |
291 | ||
292 | return (rh << 8) | rl; | |
293 | } | |
294 | ||
295 | static int locked_regw_read(struct enc28j60_net *priv, | |
296 | u8 address) | |
297 | { | |
298 | int ret; | |
299 | ||
300 | mutex_lock(&priv->lock); | |
301 | ret = nolock_regw_read(priv, address); | |
302 | mutex_unlock(&priv->lock); | |
303 | ||
304 | return ret; | |
305 | } | |
306 | ||
307 | /* | |
308 | * Register byte write | |
309 | */ | |
310 | static void nolock_regb_write(struct enc28j60_net *priv, | |
311 | u8 address, u8 data) | |
312 | { | |
313 | enc28j60_set_bank(priv, address); | |
314 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data); | |
315 | } | |
316 | ||
317 | static void locked_regb_write(struct enc28j60_net *priv, | |
318 | u8 address, u8 data) | |
319 | { | |
320 | mutex_lock(&priv->lock); | |
321 | nolock_regb_write(priv, address, data); | |
322 | mutex_unlock(&priv->lock); | |
323 | } | |
324 | ||
325 | /* | |
326 | * Register word write | |
327 | */ | |
328 | static void nolock_regw_write(struct enc28j60_net *priv, | |
329 | u8 address, u16 data) | |
330 | { | |
331 | enc28j60_set_bank(priv, address); | |
332 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data); | |
333 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1, | |
334 | (u8) (data >> 8)); | |
335 | } | |
336 | ||
337 | static void locked_regw_write(struct enc28j60_net *priv, | |
338 | u8 address, u16 data) | |
339 | { | |
340 | mutex_lock(&priv->lock); | |
341 | nolock_regw_write(priv, address, data); | |
342 | mutex_unlock(&priv->lock); | |
343 | } | |
344 | ||
345 | /* | |
346 | * Buffer memory read | |
347 | * Select the starting address and execute a SPI buffer read | |
348 | */ | |
349 | static void enc28j60_mem_read(struct enc28j60_net *priv, | |
350 | u16 addr, int len, u8 *data) | |
351 | { | |
352 | mutex_lock(&priv->lock); | |
353 | nolock_regw_write(priv, ERDPTL, addr); | |
354 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
355 | if (netif_msg_drv(priv)) { | |
356 | u16 reg; | |
357 | reg = nolock_regw_read(priv, ERDPTL); | |
358 | if (reg != addr) | |
359 | printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT " | |
b39d66a8 | 360 | "(0x%04x - 0x%04x)\n", __func__, reg, addr); |
3ec9c11d CL |
361 | } |
362 | #endif | |
363 | spi_read_buf(priv, len, data); | |
364 | mutex_unlock(&priv->lock); | |
365 | } | |
366 | ||
367 | /* | |
368 | * Write packet to enc28j60 TX buffer memory | |
369 | */ | |
370 | static void | |
371 | enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data) | |
372 | { | |
373 | mutex_lock(&priv->lock); | |
374 | /* Set the write pointer to start of transmit buffer area */ | |
375 | nolock_regw_write(priv, EWRPTL, TXSTART_INIT); | |
376 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
377 | if (netif_msg_drv(priv)) { | |
378 | u16 reg; | |
379 | reg = nolock_regw_read(priv, EWRPTL); | |
380 | if (reg != TXSTART_INIT) | |
381 | printk(KERN_DEBUG DRV_NAME | |
382 | ": %s() ERWPT:0x%04x != 0x%04x\n", | |
b39d66a8 | 383 | __func__, reg, TXSTART_INIT); |
3ec9c11d CL |
384 | } |
385 | #endif | |
386 | /* Set the TXND pointer to correspond to the packet size given */ | |
387 | nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len); | |
388 | /* write per-packet control byte */ | |
389 | spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00); | |
390 | if (netif_msg_hw(priv)) | |
391 | printk(KERN_DEBUG DRV_NAME | |
392 | ": %s() after control byte ERWPT:0x%04x\n", | |
b39d66a8 | 393 | __func__, nolock_regw_read(priv, EWRPTL)); |
3ec9c11d CL |
394 | /* copy the packet into the transmit buffer */ |
395 | spi_write_buf(priv, len, data); | |
396 | if (netif_msg_hw(priv)) | |
397 | printk(KERN_DEBUG DRV_NAME | |
398 | ": %s() after write packet ERWPT:0x%04x, len=%d\n", | |
b39d66a8 | 399 | __func__, nolock_regw_read(priv, EWRPTL), len); |
3ec9c11d CL |
400 | mutex_unlock(&priv->lock); |
401 | } | |
402 | ||
7dac6f8d DB |
403 | static unsigned long msec20_to_jiffies; |
404 | ||
405 | static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) | |
3ec9c11d | 406 | { |
7dac6f8d | 407 | unsigned long timeout = jiffies + msec20_to_jiffies; |
3ec9c11d CL |
408 | |
409 | /* 20 msec timeout read */ | |
7dac6f8d | 410 | while ((nolock_regb_read(priv, reg) & mask) != val) { |
3ec9c11d CL |
411 | if (time_after(jiffies, timeout)) { |
412 | if (netif_msg_drv(priv)) | |
7dac6f8d DB |
413 | dev_dbg(&priv->spi->dev, |
414 | "reg %02x ready timeout!\n", reg); | |
415 | return -ETIMEDOUT; | |
3ec9c11d CL |
416 | } |
417 | cpu_relax(); | |
418 | } | |
7dac6f8d DB |
419 | return 0; |
420 | } | |
421 | ||
422 | /* | |
423 | * Wait until the PHY operation is complete. | |
424 | */ | |
425 | static int wait_phy_ready(struct enc28j60_net *priv) | |
426 | { | |
427 | return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1; | |
3ec9c11d CL |
428 | } |
429 | ||
430 | /* | |
431 | * PHY register read | |
432 | * PHY registers are not accessed directly, but through the MII | |
433 | */ | |
434 | static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address) | |
435 | { | |
436 | u16 ret; | |
437 | ||
438 | mutex_lock(&priv->lock); | |
439 | /* set the PHY register address */ | |
440 | nolock_regb_write(priv, MIREGADR, address); | |
441 | /* start the register read operation */ | |
442 | nolock_regb_write(priv, MICMD, MICMD_MIIRD); | |
443 | /* wait until the PHY read completes */ | |
444 | wait_phy_ready(priv); | |
445 | /* quit reading */ | |
446 | nolock_regb_write(priv, MICMD, 0x00); | |
447 | /* return the data */ | |
448 | ret = nolock_regw_read(priv, MIRDL); | |
449 | mutex_unlock(&priv->lock); | |
450 | ||
451 | return ret; | |
452 | } | |
453 | ||
454 | static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data) | |
455 | { | |
456 | int ret; | |
457 | ||
458 | mutex_lock(&priv->lock); | |
459 | /* set the PHY register address */ | |
460 | nolock_regb_write(priv, MIREGADR, address); | |
461 | /* write the PHY data */ | |
462 | nolock_regw_write(priv, MIWRL, data); | |
463 | /* wait until the PHY write completes and return */ | |
464 | ret = wait_phy_ready(priv); | |
465 | mutex_unlock(&priv->lock); | |
466 | ||
467 | return ret; | |
468 | } | |
469 | ||
470 | /* | |
471 | * Program the hardware MAC address from dev->dev_addr. | |
472 | */ | |
473 | static int enc28j60_set_hw_macaddr(struct net_device *ndev) | |
474 | { | |
475 | int ret; | |
476 | struct enc28j60_net *priv = netdev_priv(ndev); | |
477 | ||
478 | mutex_lock(&priv->lock); | |
479 | if (!priv->hw_enable) { | |
480 | if (netif_msg_drv(priv)) { | |
481 | DECLARE_MAC_BUF(mac); | |
482 | printk(KERN_INFO DRV_NAME | |
483 | ": %s: Setting MAC address to %s\n", | |
484 | ndev->name, print_mac(mac, ndev->dev_addr)); | |
485 | } | |
486 | /* NOTE: MAC address in ENC28J60 is byte-backward */ | |
487 | nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]); | |
488 | nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]); | |
489 | nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]); | |
490 | nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]); | |
491 | nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]); | |
492 | nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]); | |
493 | ret = 0; | |
494 | } else { | |
495 | if (netif_msg_drv(priv)) | |
496 | printk(KERN_DEBUG DRV_NAME | |
497 | ": %s() Hardware must be disabled to set " | |
b39d66a8 | 498 | "Mac address\n", __func__); |
3ec9c11d CL |
499 | ret = -EBUSY; |
500 | } | |
501 | mutex_unlock(&priv->lock); | |
502 | return ret; | |
503 | } | |
504 | ||
505 | /* | |
506 | * Store the new hardware address in dev->dev_addr, and update the MAC. | |
507 | */ | |
508 | static int enc28j60_set_mac_address(struct net_device *dev, void *addr) | |
509 | { | |
510 | struct sockaddr *address = addr; | |
511 | ||
512 | if (netif_running(dev)) | |
513 | return -EBUSY; | |
514 | if (!is_valid_ether_addr(address->sa_data)) | |
515 | return -EADDRNOTAVAIL; | |
516 | ||
517 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); | |
518 | return enc28j60_set_hw_macaddr(dev); | |
519 | } | |
520 | ||
521 | /* | |
522 | * Debug routine to dump useful register contents | |
523 | */ | |
524 | static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg) | |
525 | { | |
526 | mutex_lock(&priv->lock); | |
527 | printk(KERN_DEBUG DRV_NAME " %s\n" | |
528 | "HwRevID: 0x%02x\n" | |
529 | "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n" | |
530 | " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n" | |
531 | "MAC : MACON1 MACON3 MACON4\n" | |
532 | " 0x%02x 0x%02x 0x%02x\n" | |
533 | "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n" | |
534 | " 0x%04x 0x%04x 0x%04x 0x%04x " | |
535 | "0x%02x 0x%02x 0x%04x\n" | |
536 | "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n" | |
537 | " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n", | |
538 | msg, nolock_regb_read(priv, EREVID), | |
539 | nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2), | |
540 | nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR), | |
541 | nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1), | |
542 | nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4), | |
543 | nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL), | |
544 | nolock_regw_read(priv, ERXWRPTL), | |
545 | nolock_regw_read(priv, ERXRDPTL), | |
546 | nolock_regb_read(priv, ERXFCON), | |
547 | nolock_regb_read(priv, EPKTCNT), | |
548 | nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL), | |
549 | nolock_regw_read(priv, ETXNDL), | |
550 | nolock_regb_read(priv, MACLCON1), | |
551 | nolock_regb_read(priv, MACLCON2), | |
552 | nolock_regb_read(priv, MAPHSUP)); | |
553 | mutex_unlock(&priv->lock); | |
554 | } | |
555 | ||
556 | /* | |
557 | * ERXRDPT need to be set always at odd addresses, refer to errata datasheet | |
558 | */ | |
559 | static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end) | |
560 | { | |
561 | u16 erxrdpt; | |
562 | ||
563 | if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end)) | |
564 | erxrdpt = end; | |
565 | else | |
566 | erxrdpt = next_packet_ptr - 1; | |
567 | ||
568 | return erxrdpt; | |
569 | } | |
570 | ||
5176da7e BS |
571 | /* |
572 | * Calculate wrap around when reading beyond the end of the RX buffer | |
573 | */ | |
574 | static u16 rx_packet_start(u16 ptr) | |
575 | { | |
576 | if (ptr + RSV_SIZE > RXEND_INIT) | |
577 | return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1); | |
578 | else | |
579 | return ptr + RSV_SIZE; | |
580 | } | |
581 | ||
3ec9c11d CL |
582 | static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end) |
583 | { | |
584 | u16 erxrdpt; | |
585 | ||
586 | if (start > 0x1FFF || end > 0x1FFF || start > end) { | |
587 | if (netif_msg_drv(priv)) | |
588 | printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO " | |
b39d66a8 | 589 | "bad parameters!\n", __func__, start, end); |
3ec9c11d CL |
590 | return; |
591 | } | |
592 | /* set receive buffer start + end */ | |
593 | priv->next_pk_ptr = start; | |
594 | nolock_regw_write(priv, ERXSTL, start); | |
595 | erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end); | |
596 | nolock_regw_write(priv, ERXRDPTL, erxrdpt); | |
597 | nolock_regw_write(priv, ERXNDL, end); | |
598 | } | |
599 | ||
600 | static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end) | |
601 | { | |
602 | if (start > 0x1FFF || end > 0x1FFF || start > end) { | |
603 | if (netif_msg_drv(priv)) | |
604 | printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO " | |
b39d66a8 | 605 | "bad parameters!\n", __func__, start, end); |
3ec9c11d CL |
606 | return; |
607 | } | |
608 | /* set transmit buffer start + end */ | |
609 | nolock_regw_write(priv, ETXSTL, start); | |
610 | nolock_regw_write(priv, ETXNDL, end); | |
611 | } | |
612 | ||
7dac6f8d DB |
613 | /* |
614 | * Low power mode shrinks power consumption about 100x, so we'd like | |
615 | * the chip to be in that mode whenever it's inactive. (However, we | |
616 | * can't stay in lowpower mode during suspend with WOL active.) | |
617 | */ | |
618 | static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low) | |
619 | { | |
620 | if (netif_msg_drv(priv)) | |
621 | dev_dbg(&priv->spi->dev, "%s power...\n", | |
622 | is_low ? "low" : "high"); | |
623 | ||
624 | mutex_lock(&priv->lock); | |
625 | if (is_low) { | |
626 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
627 | poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0); | |
628 | poll_ready(priv, ECON1, ECON1_TXRTS, 0); | |
629 | /* ECON2_VRPS was set during initialization */ | |
630 | nolock_reg_bfset(priv, ECON2, ECON2_PWRSV); | |
631 | } else { | |
632 | nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV); | |
633 | poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY); | |
634 | /* caller sets ECON1_RXEN */ | |
635 | } | |
636 | mutex_unlock(&priv->lock); | |
637 | } | |
638 | ||
3ec9c11d CL |
639 | static int enc28j60_hw_init(struct enc28j60_net *priv) |
640 | { | |
641 | u8 reg; | |
642 | ||
643 | if (netif_msg_drv(priv)) | |
b39d66a8 | 644 | printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__, |
3ec9c11d CL |
645 | priv->full_duplex ? "FullDuplex" : "HalfDuplex"); |
646 | ||
647 | mutex_lock(&priv->lock); | |
648 | /* first reset the chip */ | |
649 | enc28j60_soft_reset(priv); | |
650 | /* Clear ECON1 */ | |
651 | spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00); | |
652 | priv->bank = 0; | |
653 | priv->hw_enable = false; | |
654 | priv->tx_retry_count = 0; | |
655 | priv->max_pk_counter = 0; | |
656 | priv->rxfilter = RXFILTER_NORMAL; | |
7dac6f8d DB |
657 | /* enable address auto increment and voltage regulator powersave */ |
658 | nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS); | |
3ec9c11d CL |
659 | |
660 | nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); | |
661 | nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); | |
662 | mutex_unlock(&priv->lock); | |
663 | ||
664 | /* | |
665 | * Check the RevID. | |
666 | * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or | |
667 | * damaged | |
668 | */ | |
669 | reg = locked_regb_read(priv, EREVID); | |
670 | if (netif_msg_drv(priv)) | |
671 | printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg); | |
672 | if (reg == 0x00 || reg == 0xff) { | |
673 | if (netif_msg_drv(priv)) | |
674 | printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n", | |
b39d66a8 | 675 | __func__, reg); |
3ec9c11d CL |
676 | return 0; |
677 | } | |
678 | ||
679 | /* default filter mode: (unicast OR broadcast) AND crc valid */ | |
680 | locked_regb_write(priv, ERXFCON, | |
681 | ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN); | |
682 | ||
683 | /* enable MAC receive */ | |
684 | locked_regb_write(priv, MACON1, | |
685 | MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS); | |
686 | /* enable automatic padding and CRC operations */ | |
687 | if (priv->full_duplex) { | |
688 | locked_regb_write(priv, MACON3, | |
689 | MACON3_PADCFG0 | MACON3_TXCRCEN | | |
690 | MACON3_FRMLNEN | MACON3_FULDPX); | |
691 | /* set inter-frame gap (non-back-to-back) */ | |
692 | locked_regb_write(priv, MAIPGL, 0x12); | |
693 | /* set inter-frame gap (back-to-back) */ | |
694 | locked_regb_write(priv, MABBIPG, 0x15); | |
695 | } else { | |
696 | locked_regb_write(priv, MACON3, | |
697 | MACON3_PADCFG0 | MACON3_TXCRCEN | | |
698 | MACON3_FRMLNEN); | |
699 | locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */ | |
700 | /* set inter-frame gap (non-back-to-back) */ | |
701 | locked_regw_write(priv, MAIPGL, 0x0C12); | |
702 | /* set inter-frame gap (back-to-back) */ | |
703 | locked_regb_write(priv, MABBIPG, 0x12); | |
704 | } | |
705 | /* | |
706 | * MACLCON1 (default) | |
707 | * MACLCON2 (default) | |
708 | * Set the maximum packet size which the controller will accept | |
709 | */ | |
710 | locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN); | |
711 | ||
712 | /* Configure LEDs */ | |
713 | if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE)) | |
714 | return 0; | |
715 | ||
716 | if (priv->full_duplex) { | |
717 | if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD)) | |
718 | return 0; | |
719 | if (!enc28j60_phy_write(priv, PHCON2, 0x00)) | |
720 | return 0; | |
721 | } else { | |
722 | if (!enc28j60_phy_write(priv, PHCON1, 0x00)) | |
723 | return 0; | |
724 | if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS)) | |
725 | return 0; | |
726 | } | |
727 | if (netif_msg_hw(priv)) | |
728 | enc28j60_dump_regs(priv, "Hw initialized."); | |
729 | ||
730 | return 1; | |
731 | } | |
732 | ||
733 | static void enc28j60_hw_enable(struct enc28j60_net *priv) | |
734 | { | |
7dac6f8d | 735 | /* enable interrupts */ |
3ec9c11d CL |
736 | if (netif_msg_hw(priv)) |
737 | printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n", | |
b39d66a8 | 738 | __func__); |
3ec9c11d CL |
739 | |
740 | enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE); | |
741 | ||
742 | mutex_lock(&priv->lock); | |
743 | nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF | | |
744 | EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF); | |
745 | nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE | | |
746 | EIE_TXIE | EIE_TXERIE | EIE_RXERIE); | |
747 | ||
748 | /* enable receive logic */ | |
749 | nolock_reg_bfset(priv, ECON1, ECON1_RXEN); | |
750 | priv->hw_enable = true; | |
751 | mutex_unlock(&priv->lock); | |
752 | } | |
753 | ||
754 | static void enc28j60_hw_disable(struct enc28j60_net *priv) | |
755 | { | |
756 | mutex_lock(&priv->lock); | |
757 | /* disable interrutps and packet reception */ | |
758 | nolock_regb_write(priv, EIE, 0x00); | |
759 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
760 | priv->hw_enable = false; | |
761 | mutex_unlock(&priv->lock); | |
762 | } | |
763 | ||
764 | static int | |
765 | enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex) | |
766 | { | |
767 | struct enc28j60_net *priv = netdev_priv(ndev); | |
768 | int ret = 0; | |
769 | ||
770 | if (!priv->hw_enable) { | |
7dac6f8d DB |
771 | /* link is in low power mode now; duplex setting |
772 | * will take effect on next enc28j60_hw_init(). | |
773 | */ | |
774 | if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) | |
3ec9c11d | 775 | priv->full_duplex = (duplex == DUPLEX_FULL); |
7dac6f8d | 776 | else { |
3ec9c11d CL |
777 | if (netif_msg_link(priv)) |
778 | dev_warn(&ndev->dev, | |
779 | "unsupported link setting\n"); | |
780 | ret = -EOPNOTSUPP; | |
781 | } | |
782 | } else { | |
783 | if (netif_msg_link(priv)) | |
784 | dev_warn(&ndev->dev, "Warning: hw must be disabled " | |
785 | "to set link mode\n"); | |
786 | ret = -EBUSY; | |
787 | } | |
788 | return ret; | |
789 | } | |
790 | ||
791 | /* | |
792 | * Read the Transmit Status Vector | |
793 | */ | |
794 | static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE]) | |
795 | { | |
796 | int endptr; | |
797 | ||
798 | endptr = locked_regw_read(priv, ETXNDL); | |
799 | if (netif_msg_hw(priv)) | |
800 | printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n", | |
801 | endptr + 1); | |
802 | enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv); | |
803 | } | |
804 | ||
805 | static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg, | |
806 | u8 tsv[TSV_SIZE]) | |
807 | { | |
808 | u16 tmp1, tmp2; | |
809 | ||
810 | printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg); | |
811 | tmp1 = tsv[1]; | |
812 | tmp1 <<= 8; | |
813 | tmp1 |= tsv[0]; | |
814 | ||
815 | tmp2 = tsv[5]; | |
816 | tmp2 <<= 8; | |
817 | tmp2 |= tsv[4]; | |
818 | ||
819 | printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d," | |
820 | " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2); | |
821 | printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d," | |
822 | " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE), | |
823 | TSV_GETBIT(tsv, TSV_TXCRCERROR), | |
824 | TSV_GETBIT(tsv, TSV_TXLENCHKERROR), | |
825 | TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE)); | |
826 | printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " | |
827 | "PacketDefer: %d, ExDefer: %d\n", | |
828 | TSV_GETBIT(tsv, TSV_TXMULTICAST), | |
829 | TSV_GETBIT(tsv, TSV_TXBROADCAST), | |
830 | TSV_GETBIT(tsv, TSV_TXPACKETDEFER), | |
831 | TSV_GETBIT(tsv, TSV_TXEXDEFER)); | |
832 | printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, " | |
833 | "Giant: %d, Underrun: %d\n", | |
834 | TSV_GETBIT(tsv, TSV_TXEXCOLLISION), | |
835 | TSV_GETBIT(tsv, TSV_TXLATECOLLISION), | |
836 | TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN)); | |
837 | printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, " | |
838 | "BackPressApp: %d, VLanTagFrame: %d\n", | |
839 | TSV_GETBIT(tsv, TSV_TXCONTROLFRAME), | |
840 | TSV_GETBIT(tsv, TSV_TXPAUSEFRAME), | |
841 | TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP), | |
842 | TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME)); | |
843 | } | |
844 | ||
845 | /* | |
846 | * Receive Status vector | |
847 | */ | |
848 | static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg, | |
849 | u16 pk_ptr, int len, u16 sts) | |
850 | { | |
851 | printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n", | |
852 | msg, pk_ptr); | |
853 | printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len, | |
854 | RSV_GETBIT(sts, RSV_DRIBBLENIBBLE)); | |
855 | printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d," | |
856 | " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK), | |
857 | RSV_GETBIT(sts, RSV_CRCERROR), | |
858 | RSV_GETBIT(sts, RSV_LENCHECKERR), | |
859 | RSV_GETBIT(sts, RSV_LENOUTOFRANGE)); | |
860 | printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, " | |
861 | "LongDropEvent: %d, CarrierEvent: %d\n", | |
862 | RSV_GETBIT(sts, RSV_RXMULTICAST), | |
863 | RSV_GETBIT(sts, RSV_RXBROADCAST), | |
864 | RSV_GETBIT(sts, RSV_RXLONGEVDROPEV), | |
865 | RSV_GETBIT(sts, RSV_CARRIEREV)); | |
866 | printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d," | |
867 | " UnknownOp: %d, VLanTagFrame: %d\n", | |
868 | RSV_GETBIT(sts, RSV_RXCONTROLFRAME), | |
869 | RSV_GETBIT(sts, RSV_RXPAUSEFRAME), | |
870 | RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE), | |
871 | RSV_GETBIT(sts, RSV_RXTYPEVLAN)); | |
872 | } | |
873 | ||
874 | static void dump_packet(const char *msg, int len, const char *data) | |
875 | { | |
876 | printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len); | |
877 | print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
878 | data, len, true); | |
879 | } | |
880 | ||
881 | /* | |
882 | * Hardware receive function. | |
883 | * Read the buffer memory, update the FIFO pointer to free the buffer, | |
884 | * check the status vector and decrement the packet counter. | |
885 | */ | |
886 | static void enc28j60_hw_rx(struct net_device *ndev) | |
887 | { | |
888 | struct enc28j60_net *priv = netdev_priv(ndev); | |
889 | struct sk_buff *skb = NULL; | |
890 | u16 erxrdpt, next_packet, rxstat; | |
891 | u8 rsv[RSV_SIZE]; | |
892 | int len; | |
893 | ||
894 | if (netif_msg_rx_status(priv)) | |
895 | printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n", | |
896 | priv->next_pk_ptr); | |
897 | ||
898 | if (unlikely(priv->next_pk_ptr > RXEND_INIT)) { | |
899 | if (netif_msg_rx_err(priv)) | |
900 | dev_err(&ndev->dev, | |
901 | "%s() Invalid packet address!! 0x%04x\n", | |
b39d66a8 | 902 | __func__, priv->next_pk_ptr); |
3ec9c11d CL |
903 | /* packet address corrupted: reset RX logic */ |
904 | mutex_lock(&priv->lock); | |
905 | nolock_reg_bfclr(priv, ECON1, ECON1_RXEN); | |
906 | nolock_reg_bfset(priv, ECON1, ECON1_RXRST); | |
907 | nolock_reg_bfclr(priv, ECON1, ECON1_RXRST); | |
908 | nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT); | |
909 | nolock_reg_bfclr(priv, EIR, EIR_RXERIF); | |
910 | nolock_reg_bfset(priv, ECON1, ECON1_RXEN); | |
911 | mutex_unlock(&priv->lock); | |
912 | ndev->stats.rx_errors++; | |
913 | return; | |
914 | } | |
915 | /* Read next packet pointer and rx status vector */ | |
916 | enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv); | |
917 | ||
918 | next_packet = rsv[1]; | |
919 | next_packet <<= 8; | |
920 | next_packet |= rsv[0]; | |
921 | ||
922 | len = rsv[3]; | |
923 | len <<= 8; | |
924 | len |= rsv[2]; | |
925 | ||
926 | rxstat = rsv[5]; | |
927 | rxstat <<= 8; | |
928 | rxstat |= rsv[4]; | |
929 | ||
930 | if (netif_msg_rx_status(priv)) | |
b39d66a8 | 931 | enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat); |
3ec9c11d CL |
932 | |
933 | if (!RSV_GETBIT(rxstat, RSV_RXOK)) { | |
934 | if (netif_msg_rx_err(priv)) | |
935 | dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat); | |
936 | ndev->stats.rx_errors++; | |
937 | if (RSV_GETBIT(rxstat, RSV_CRCERROR)) | |
938 | ndev->stats.rx_crc_errors++; | |
939 | if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) | |
940 | ndev->stats.rx_frame_errors++; | |
941 | } else { | |
02ff05c4 | 942 | skb = dev_alloc_skb(len + NET_IP_ALIGN); |
3ec9c11d CL |
943 | if (!skb) { |
944 | if (netif_msg_rx_err(priv)) | |
945 | dev_err(&ndev->dev, | |
946 | "out of memory for Rx'd frame\n"); | |
947 | ndev->stats.rx_dropped++; | |
948 | } else { | |
949 | skb->dev = ndev; | |
02ff05c4 | 950 | skb_reserve(skb, NET_IP_ALIGN); |
3ec9c11d | 951 | /* copy the packet from the receive buffer */ |
5176da7e BS |
952 | enc28j60_mem_read(priv, |
953 | rx_packet_start(priv->next_pk_ptr), | |
954 | len, skb_put(skb, len)); | |
3ec9c11d | 955 | if (netif_msg_pktdata(priv)) |
b39d66a8 | 956 | dump_packet(__func__, skb->len, skb->data); |
3ec9c11d CL |
957 | skb->protocol = eth_type_trans(skb, ndev); |
958 | /* update statistics */ | |
959 | ndev->stats.rx_packets++; | |
960 | ndev->stats.rx_bytes += len; | |
961 | ndev->last_rx = jiffies; | |
962 | netif_rx(skb); | |
963 | } | |
964 | } | |
965 | /* | |
966 | * Move the RX read pointer to the start of the next | |
967 | * received packet. | |
968 | * This frees the memory we just read out | |
969 | */ | |
970 | erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT); | |
971 | if (netif_msg_hw(priv)) | |
972 | printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n", | |
b39d66a8 | 973 | __func__, erxrdpt); |
3ec9c11d CL |
974 | |
975 | mutex_lock(&priv->lock); | |
976 | nolock_regw_write(priv, ERXRDPTL, erxrdpt); | |
977 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
978 | if (netif_msg_drv(priv)) { | |
979 | u16 reg; | |
980 | reg = nolock_regw_read(priv, ERXRDPTL); | |
981 | if (reg != erxrdpt) | |
982 | printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify " | |
b39d66a8 | 983 | "error (0x%04x - 0x%04x)\n", __func__, |
3ec9c11d CL |
984 | reg, erxrdpt); |
985 | } | |
986 | #endif | |
987 | priv->next_pk_ptr = next_packet; | |
988 | /* we are done with this packet, decrement the packet counter */ | |
989 | nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC); | |
990 | mutex_unlock(&priv->lock); | |
991 | } | |
992 | ||
993 | /* | |
994 | * Calculate free space in RxFIFO | |
995 | */ | |
996 | static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv) | |
997 | { | |
998 | int epkcnt, erxst, erxnd, erxwr, erxrd; | |
999 | int free_space; | |
1000 | ||
1001 | mutex_lock(&priv->lock); | |
1002 | epkcnt = nolock_regb_read(priv, EPKTCNT); | |
1003 | if (epkcnt >= 255) | |
1004 | free_space = -1; | |
1005 | else { | |
1006 | erxst = nolock_regw_read(priv, ERXSTL); | |
1007 | erxnd = nolock_regw_read(priv, ERXNDL); | |
1008 | erxwr = nolock_regw_read(priv, ERXWRPTL); | |
1009 | erxrd = nolock_regw_read(priv, ERXRDPTL); | |
1010 | ||
1011 | if (erxwr > erxrd) | |
1012 | free_space = (erxnd - erxst) - (erxwr - erxrd); | |
1013 | else if (erxwr == erxrd) | |
1014 | free_space = (erxnd - erxst); | |
1015 | else | |
1016 | free_space = erxrd - erxwr - 1; | |
1017 | } | |
1018 | mutex_unlock(&priv->lock); | |
1019 | if (netif_msg_rx_status(priv)) | |
1020 | printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n", | |
b39d66a8 | 1021 | __func__, free_space); |
3ec9c11d CL |
1022 | return free_space; |
1023 | } | |
1024 | ||
1025 | /* | |
1026 | * Access the PHY to determine link status | |
1027 | */ | |
1028 | static void enc28j60_check_link_status(struct net_device *ndev) | |
1029 | { | |
1030 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1031 | u16 reg; | |
1032 | int duplex; | |
1033 | ||
1034 | reg = enc28j60_phy_read(priv, PHSTAT2); | |
1035 | if (netif_msg_hw(priv)) | |
1036 | printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, " | |
b39d66a8 | 1037 | "PHSTAT2: %04x\n", __func__, |
3ec9c11d CL |
1038 | enc28j60_phy_read(priv, PHSTAT1), reg); |
1039 | duplex = reg & PHSTAT2_DPXSTAT; | |
1040 | ||
1041 | if (reg & PHSTAT2_LSTAT) { | |
1042 | netif_carrier_on(ndev); | |
1043 | if (netif_msg_ifup(priv)) | |
1044 | dev_info(&ndev->dev, "link up - %s\n", | |
1045 | duplex ? "Full duplex" : "Half duplex"); | |
1046 | } else { | |
1047 | if (netif_msg_ifdown(priv)) | |
1048 | dev_info(&ndev->dev, "link down\n"); | |
1049 | netif_carrier_off(ndev); | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | static void enc28j60_tx_clear(struct net_device *ndev, bool err) | |
1054 | { | |
1055 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1056 | ||
1057 | if (err) | |
1058 | ndev->stats.tx_errors++; | |
1059 | else | |
1060 | ndev->stats.tx_packets++; | |
1061 | ||
1062 | if (priv->tx_skb) { | |
1063 | if (!err) | |
1064 | ndev->stats.tx_bytes += priv->tx_skb->len; | |
1065 | dev_kfree_skb(priv->tx_skb); | |
1066 | priv->tx_skb = NULL; | |
1067 | } | |
1068 | locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); | |
1069 | netif_wake_queue(ndev); | |
1070 | } | |
1071 | ||
1072 | /* | |
1073 | * RX handler | |
1074 | * ignore PKTIF because is unreliable! (look at the errata datasheet) | |
1075 | * check EPKTCNT is the suggested workaround. | |
1076 | * We don't need to clear interrupt flag, automatically done when | |
1077 | * enc28j60_hw_rx() decrements the packet counter. | |
1078 | * Returns how many packet processed. | |
1079 | */ | |
1080 | static int enc28j60_rx_interrupt(struct net_device *ndev) | |
1081 | { | |
1082 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1083 | int pk_counter, ret; | |
1084 | ||
1085 | pk_counter = locked_regb_read(priv, EPKTCNT); | |
1086 | if (pk_counter && netif_msg_intr(priv)) | |
1087 | printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter); | |
1088 | if (pk_counter > priv->max_pk_counter) { | |
1089 | /* update statistics */ | |
1090 | priv->max_pk_counter = pk_counter; | |
1091 | if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1) | |
1092 | printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n", | |
1093 | priv->max_pk_counter); | |
1094 | } | |
1095 | ret = pk_counter; | |
1096 | while (pk_counter-- > 0) | |
1097 | enc28j60_hw_rx(ndev); | |
1098 | ||
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | static void enc28j60_irq_work_handler(struct work_struct *work) | |
1103 | { | |
1104 | struct enc28j60_net *priv = | |
1105 | container_of(work, struct enc28j60_net, irq_work); | |
1106 | struct net_device *ndev = priv->netdev; | |
1107 | int intflags, loop; | |
1108 | ||
1109 | if (netif_msg_intr(priv)) | |
b39d66a8 | 1110 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1111 | /* disable further interrupts */ |
1112 | locked_reg_bfclr(priv, EIE, EIE_INTIE); | |
1113 | ||
1114 | do { | |
1115 | loop = 0; | |
1116 | intflags = locked_regb_read(priv, EIR); | |
1117 | /* DMA interrupt handler (not currently used) */ | |
1118 | if ((intflags & EIR_DMAIF) != 0) { | |
1119 | loop++; | |
1120 | if (netif_msg_intr(priv)) | |
1121 | printk(KERN_DEBUG DRV_NAME | |
1122 | ": intDMA(%d)\n", loop); | |
1123 | locked_reg_bfclr(priv, EIR, EIR_DMAIF); | |
1124 | } | |
1125 | /* LINK changed handler */ | |
1126 | if ((intflags & EIR_LINKIF) != 0) { | |
1127 | loop++; | |
1128 | if (netif_msg_intr(priv)) | |
1129 | printk(KERN_DEBUG DRV_NAME | |
1130 | ": intLINK(%d)\n", loop); | |
1131 | enc28j60_check_link_status(ndev); | |
1132 | /* read PHIR to clear the flag */ | |
1133 | enc28j60_phy_read(priv, PHIR); | |
1134 | } | |
1135 | /* TX complete handler */ | |
1136 | if ((intflags & EIR_TXIF) != 0) { | |
1137 | bool err = false; | |
1138 | loop++; | |
1139 | if (netif_msg_intr(priv)) | |
1140 | printk(KERN_DEBUG DRV_NAME | |
1141 | ": intTX(%d)\n", loop); | |
1142 | priv->tx_retry_count = 0; | |
1143 | if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) { | |
1144 | if (netif_msg_tx_err(priv)) | |
1145 | dev_err(&ndev->dev, | |
1146 | "Tx Error (aborted)\n"); | |
1147 | err = true; | |
1148 | } | |
1149 | if (netif_msg_tx_done(priv)) { | |
1150 | u8 tsv[TSV_SIZE]; | |
1151 | enc28j60_read_tsv(priv, tsv); | |
1152 | enc28j60_dump_tsv(priv, "Tx Done", tsv); | |
1153 | } | |
1154 | enc28j60_tx_clear(ndev, err); | |
1155 | locked_reg_bfclr(priv, EIR, EIR_TXIF); | |
1156 | } | |
1157 | /* TX Error handler */ | |
1158 | if ((intflags & EIR_TXERIF) != 0) { | |
1159 | u8 tsv[TSV_SIZE]; | |
1160 | ||
1161 | loop++; | |
1162 | if (netif_msg_intr(priv)) | |
1163 | printk(KERN_DEBUG DRV_NAME | |
1164 | ": intTXErr(%d)\n", loop); | |
1165 | locked_reg_bfclr(priv, ECON1, ECON1_TXRTS); | |
1166 | enc28j60_read_tsv(priv, tsv); | |
1167 | if (netif_msg_tx_err(priv)) | |
1168 | enc28j60_dump_tsv(priv, "Tx Error", tsv); | |
1169 | /* Reset TX logic */ | |
1170 | mutex_lock(&priv->lock); | |
1171 | nolock_reg_bfset(priv, ECON1, ECON1_TXRST); | |
1172 | nolock_reg_bfclr(priv, ECON1, ECON1_TXRST); | |
1173 | nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT); | |
1174 | mutex_unlock(&priv->lock); | |
1175 | /* Transmit Late collision check for retransmit */ | |
1176 | if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) { | |
1177 | if (netif_msg_tx_err(priv)) | |
1178 | printk(KERN_DEBUG DRV_NAME | |
1179 | ": LateCollision TXErr (%d)\n", | |
1180 | priv->tx_retry_count); | |
1181 | if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT) | |
1182 | locked_reg_bfset(priv, ECON1, | |
1183 | ECON1_TXRTS); | |
1184 | else | |
1185 | enc28j60_tx_clear(ndev, true); | |
1186 | } else | |
1187 | enc28j60_tx_clear(ndev, true); | |
1188 | locked_reg_bfclr(priv, EIR, EIR_TXERIF); | |
1189 | } | |
1190 | /* RX Error handler */ | |
1191 | if ((intflags & EIR_RXERIF) != 0) { | |
1192 | loop++; | |
1193 | if (netif_msg_intr(priv)) | |
1194 | printk(KERN_DEBUG DRV_NAME | |
1195 | ": intRXErr(%d)\n", loop); | |
1196 | /* Check free FIFO space to flag RX overrun */ | |
1197 | if (enc28j60_get_free_rxfifo(priv) <= 0) { | |
1198 | if (netif_msg_rx_err(priv)) | |
1199 | printk(KERN_DEBUG DRV_NAME | |
1200 | ": RX Overrun\n"); | |
1201 | ndev->stats.rx_dropped++; | |
1202 | } | |
1203 | locked_reg_bfclr(priv, EIR, EIR_RXERIF); | |
1204 | } | |
1205 | /* RX handler */ | |
1206 | if (enc28j60_rx_interrupt(ndev)) | |
1207 | loop++; | |
1208 | } while (loop); | |
1209 | ||
1210 | /* re-enable interrupts */ | |
1211 | locked_reg_bfset(priv, EIE, EIE_INTIE); | |
1212 | if (netif_msg_intr(priv)) | |
b39d66a8 | 1213 | printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__); |
3ec9c11d CL |
1214 | } |
1215 | ||
1216 | /* | |
1217 | * Hardware transmit function. | |
1218 | * Fill the buffer memory and send the contents of the transmit buffer | |
1219 | * onto the network | |
1220 | */ | |
1221 | static void enc28j60_hw_tx(struct enc28j60_net *priv) | |
1222 | { | |
1223 | if (netif_msg_tx_queued(priv)) | |
1224 | printk(KERN_DEBUG DRV_NAME | |
1225 | ": Tx Packet Len:%d\n", priv->tx_skb->len); | |
1226 | ||
1227 | if (netif_msg_pktdata(priv)) | |
b39d66a8 | 1228 | dump_packet(__func__, |
3ec9c11d CL |
1229 | priv->tx_skb->len, priv->tx_skb->data); |
1230 | enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data); | |
1231 | ||
1232 | #ifdef CONFIG_ENC28J60_WRITEVERIFY | |
1233 | /* readback and verify written data */ | |
1234 | if (netif_msg_drv(priv)) { | |
1235 | int test_len, k; | |
1236 | u8 test_buf[64]; /* limit the test to the first 64 bytes */ | |
1237 | int okflag; | |
1238 | ||
1239 | test_len = priv->tx_skb->len; | |
1240 | if (test_len > sizeof(test_buf)) | |
1241 | test_len = sizeof(test_buf); | |
1242 | ||
1243 | /* + 1 to skip control byte */ | |
1244 | enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf); | |
1245 | okflag = 1; | |
1246 | for (k = 0; k < test_len; k++) { | |
1247 | if (priv->tx_skb->data[k] != test_buf[k]) { | |
1248 | printk(KERN_DEBUG DRV_NAME | |
1249 | ": Error, %d location differ: " | |
1250 | "0x%02x-0x%02x\n", k, | |
1251 | priv->tx_skb->data[k], test_buf[k]); | |
1252 | okflag = 0; | |
1253 | } | |
1254 | } | |
1255 | if (!okflag) | |
1256 | printk(KERN_DEBUG DRV_NAME ": Tx write buffer, " | |
1257 | "verify ERROR!\n"); | |
1258 | } | |
1259 | #endif | |
1260 | /* set TX request flag */ | |
1261 | locked_reg_bfset(priv, ECON1, ECON1_TXRTS); | |
1262 | } | |
1263 | ||
1264 | static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev) | |
1265 | { | |
1266 | struct enc28j60_net *priv = netdev_priv(dev); | |
1267 | ||
1268 | if (netif_msg_tx_queued(priv)) | |
b39d66a8 | 1269 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1270 | |
1271 | /* If some error occurs while trying to transmit this | |
1272 | * packet, you should return '1' from this function. | |
1273 | * In such a case you _may not_ do anything to the | |
1274 | * SKB, it is still owned by the network queueing | |
1275 | * layer when an error is returned. This means you | |
1276 | * may not modify any SKB fields, you may not free | |
1277 | * the SKB, etc. | |
1278 | */ | |
1279 | netif_stop_queue(dev); | |
1280 | ||
1281 | /* save the timestamp */ | |
1282 | priv->netdev->trans_start = jiffies; | |
1283 | /* Remember the skb for deferred processing */ | |
1284 | priv->tx_skb = skb; | |
1285 | schedule_work(&priv->tx_work); | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static void enc28j60_tx_work_handler(struct work_struct *work) | |
1291 | { | |
1292 | struct enc28j60_net *priv = | |
1293 | container_of(work, struct enc28j60_net, tx_work); | |
1294 | ||
1295 | /* actual delivery of data */ | |
1296 | enc28j60_hw_tx(priv); | |
1297 | } | |
1298 | ||
1299 | static irqreturn_t enc28j60_irq(int irq, void *dev_id) | |
1300 | { | |
1301 | struct enc28j60_net *priv = dev_id; | |
1302 | ||
1303 | /* | |
1304 | * Can't do anything in interrupt context because we need to | |
1305 | * block (spi_sync() is blocking) so fire of the interrupt | |
1306 | * handling workqueue. | |
1307 | * Remember that we access enc28j60 registers through SPI bus | |
1308 | * via spi_sync() call. | |
1309 | */ | |
1310 | schedule_work(&priv->irq_work); | |
1311 | ||
1312 | return IRQ_HANDLED; | |
1313 | } | |
1314 | ||
1315 | static void enc28j60_tx_timeout(struct net_device *ndev) | |
1316 | { | |
1317 | struct enc28j60_net *priv = netdev_priv(ndev); | |
1318 | ||
1319 | if (netif_msg_timer(priv)) | |
1320 | dev_err(&ndev->dev, DRV_NAME " tx timeout\n"); | |
1321 | ||
1322 | ndev->stats.tx_errors++; | |
1323 | /* can't restart safely under softirq */ | |
1324 | schedule_work(&priv->restart_work); | |
1325 | } | |
1326 | ||
1327 | /* | |
1328 | * Open/initialize the board. This is called (in the current kernel) | |
1329 | * sometime after booting when the 'ifconfig' program is run. | |
1330 | * | |
1331 | * This routine should set everything up anew at each open, even | |
1332 | * registers that "should" only need to be set once at boot, so that | |
1333 | * there is non-reboot way to recover if something goes wrong. | |
1334 | */ | |
1335 | static int enc28j60_net_open(struct net_device *dev) | |
1336 | { | |
1337 | struct enc28j60_net *priv = netdev_priv(dev); | |
1338 | ||
1339 | if (netif_msg_drv(priv)) | |
b39d66a8 | 1340 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1341 | |
1342 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1343 | if (netif_msg_ifup(priv)) { | |
1344 | DECLARE_MAC_BUF(mac); | |
1345 | dev_err(&dev->dev, "invalid MAC address %s\n", | |
1346 | print_mac(mac, dev->dev_addr)); | |
1347 | } | |
1348 | return -EADDRNOTAVAIL; | |
1349 | } | |
7dac6f8d DB |
1350 | /* Reset the hardware here (and take it out of low power mode) */ |
1351 | enc28j60_lowpower(priv, false); | |
3ec9c11d CL |
1352 | enc28j60_hw_disable(priv); |
1353 | if (!enc28j60_hw_init(priv)) { | |
1354 | if (netif_msg_ifup(priv)) | |
1355 | dev_err(&dev->dev, "hw_reset() failed\n"); | |
1356 | return -EINVAL; | |
1357 | } | |
1358 | /* Update the MAC address (in case user has changed it) */ | |
1359 | enc28j60_set_hw_macaddr(dev); | |
1360 | /* Enable interrupts */ | |
1361 | enc28j60_hw_enable(priv); | |
1362 | /* check link status */ | |
1363 | enc28j60_check_link_status(dev); | |
1364 | /* We are now ready to accept transmit requests from | |
1365 | * the queueing layer of the networking. | |
1366 | */ | |
1367 | netif_start_queue(dev); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | /* The inverse routine to net_open(). */ | |
1373 | static int enc28j60_net_close(struct net_device *dev) | |
1374 | { | |
1375 | struct enc28j60_net *priv = netdev_priv(dev); | |
1376 | ||
1377 | if (netif_msg_drv(priv)) | |
b39d66a8 | 1378 | printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__); |
3ec9c11d CL |
1379 | |
1380 | enc28j60_hw_disable(priv); | |
7dac6f8d | 1381 | enc28j60_lowpower(priv, true); |
3ec9c11d CL |
1382 | netif_stop_queue(dev); |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | /* | |
1388 | * Set or clear the multicast filter for this adapter | |
1389 | * num_addrs == -1 Promiscuous mode, receive all packets | |
1390 | * num_addrs == 0 Normal mode, filter out multicast packets | |
1391 | * num_addrs > 0 Multicast mode, receive normal and MC packets | |
1392 | */ | |
1393 | static void enc28j60_set_multicast_list(struct net_device *dev) | |
1394 | { | |
1395 | struct enc28j60_net *priv = netdev_priv(dev); | |
1396 | int oldfilter = priv->rxfilter; | |
1397 | ||
1398 | if (dev->flags & IFF_PROMISC) { | |
1399 | if (netif_msg_link(priv)) | |
1400 | dev_info(&dev->dev, "promiscuous mode\n"); | |
1401 | priv->rxfilter = RXFILTER_PROMISC; | |
1402 | } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) { | |
1403 | if (netif_msg_link(priv)) | |
1404 | dev_info(&dev->dev, "%smulticast mode\n", | |
1405 | (dev->flags & IFF_ALLMULTI) ? "all-" : ""); | |
1406 | priv->rxfilter = RXFILTER_MULTI; | |
1407 | } else { | |
1408 | if (netif_msg_link(priv)) | |
1409 | dev_info(&dev->dev, "normal mode\n"); | |
1410 | priv->rxfilter = RXFILTER_NORMAL; | |
1411 | } | |
1412 | ||
1413 | if (oldfilter != priv->rxfilter) | |
1414 | schedule_work(&priv->setrx_work); | |
1415 | } | |
1416 | ||
1417 | static void enc28j60_setrx_work_handler(struct work_struct *work) | |
1418 | { | |
1419 | struct enc28j60_net *priv = | |
1420 | container_of(work, struct enc28j60_net, setrx_work); | |
1421 | ||
1422 | if (priv->rxfilter == RXFILTER_PROMISC) { | |
1423 | if (netif_msg_drv(priv)) | |
1424 | printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n"); | |
1425 | locked_regb_write(priv, ERXFCON, 0x00); | |
1426 | } else if (priv->rxfilter == RXFILTER_MULTI) { | |
1427 | if (netif_msg_drv(priv)) | |
1428 | printk(KERN_DEBUG DRV_NAME ": multicast mode\n"); | |
1429 | locked_regb_write(priv, ERXFCON, | |
1430 | ERXFCON_UCEN | ERXFCON_CRCEN | | |
1431 | ERXFCON_BCEN | ERXFCON_MCEN); | |
1432 | } else { | |
1433 | if (netif_msg_drv(priv)) | |
1434 | printk(KERN_DEBUG DRV_NAME ": normal mode\n"); | |
1435 | locked_regb_write(priv, ERXFCON, | |
1436 | ERXFCON_UCEN | ERXFCON_CRCEN | | |
1437 | ERXFCON_BCEN); | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | static void enc28j60_restart_work_handler(struct work_struct *work) | |
1442 | { | |
1443 | struct enc28j60_net *priv = | |
1444 | container_of(work, struct enc28j60_net, restart_work); | |
1445 | struct net_device *ndev = priv->netdev; | |
1446 | int ret; | |
1447 | ||
1448 | rtnl_lock(); | |
1449 | if (netif_running(ndev)) { | |
1450 | enc28j60_net_close(ndev); | |
1451 | ret = enc28j60_net_open(ndev); | |
1452 | if (unlikely(ret)) { | |
1453 | dev_info(&ndev->dev, " could not restart %d\n", ret); | |
1454 | dev_close(ndev); | |
1455 | } | |
1456 | } | |
1457 | rtnl_unlock(); | |
1458 | } | |
1459 | ||
1460 | /* ......................... ETHTOOL SUPPORT ........................... */ | |
1461 | ||
1462 | static void | |
1463 | enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1464 | { | |
1465 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | |
1466 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1467 | strlcpy(info->bus_info, | |
1468 | dev->dev.parent->bus_id, sizeof(info->bus_info)); | |
1469 | } | |
1470 | ||
1471 | static int | |
1472 | enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1473 | { | |
1474 | struct enc28j60_net *priv = netdev_priv(dev); | |
1475 | ||
1476 | cmd->transceiver = XCVR_INTERNAL; | |
1477 | cmd->supported = SUPPORTED_10baseT_Half | |
1478 | | SUPPORTED_10baseT_Full | |
1479 | | SUPPORTED_TP; | |
1480 | cmd->speed = SPEED_10; | |
1481 | cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF; | |
1482 | cmd->port = PORT_TP; | |
1483 | cmd->autoneg = AUTONEG_DISABLE; | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | static int | |
1489 | enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1490 | { | |
1491 | return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex); | |
1492 | } | |
1493 | ||
1494 | static u32 enc28j60_get_msglevel(struct net_device *dev) | |
1495 | { | |
1496 | struct enc28j60_net *priv = netdev_priv(dev); | |
1497 | return priv->msg_enable; | |
1498 | } | |
1499 | ||
1500 | static void enc28j60_set_msglevel(struct net_device *dev, u32 val) | |
1501 | { | |
1502 | struct enc28j60_net *priv = netdev_priv(dev); | |
1503 | priv->msg_enable = val; | |
1504 | } | |
1505 | ||
1506 | static const struct ethtool_ops enc28j60_ethtool_ops = { | |
1507 | .get_settings = enc28j60_get_settings, | |
1508 | .set_settings = enc28j60_set_settings, | |
1509 | .get_drvinfo = enc28j60_get_drvinfo, | |
1510 | .get_msglevel = enc28j60_get_msglevel, | |
1511 | .set_msglevel = enc28j60_set_msglevel, | |
1512 | }; | |
1513 | ||
1514 | static int enc28j60_chipset_init(struct net_device *dev) | |
1515 | { | |
1516 | struct enc28j60_net *priv = netdev_priv(dev); | |
1517 | ||
1518 | return enc28j60_hw_init(priv); | |
1519 | } | |
1520 | ||
1521 | static int __devinit enc28j60_probe(struct spi_device *spi) | |
1522 | { | |
1523 | struct net_device *dev; | |
1524 | struct enc28j60_net *priv; | |
1525 | int ret = 0; | |
1526 | ||
1527 | if (netif_msg_drv(&debug)) | |
1528 | dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n", | |
1529 | DRV_VERSION); | |
1530 | ||
1531 | dev = alloc_etherdev(sizeof(struct enc28j60_net)); | |
1532 | if (!dev) { | |
1533 | if (netif_msg_drv(&debug)) | |
1534 | dev_err(&spi->dev, DRV_NAME | |
1535 | ": unable to alloc new ethernet\n"); | |
1536 | ret = -ENOMEM; | |
1537 | goto error_alloc; | |
1538 | } | |
1539 | priv = netdev_priv(dev); | |
1540 | ||
1541 | priv->netdev = dev; /* priv to netdev reference */ | |
1542 | priv->spi = spi; /* priv to spi reference */ | |
1543 | priv->msg_enable = netif_msg_init(debug.msg_enable, | |
1544 | ENC28J60_MSG_DEFAULT); | |
1545 | mutex_init(&priv->lock); | |
1546 | INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler); | |
1547 | INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler); | |
1548 | INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler); | |
1549 | INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler); | |
1550 | dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */ | |
1551 | SET_NETDEV_DEV(dev, &spi->dev); | |
1552 | ||
1553 | if (!enc28j60_chipset_init(dev)) { | |
1554 | if (netif_msg_probe(priv)) | |
1555 | dev_info(&spi->dev, DRV_NAME " chip not found\n"); | |
1556 | ret = -EIO; | |
1557 | goto error_irq; | |
1558 | } | |
1559 | random_ether_addr(dev->dev_addr); | |
1560 | enc28j60_set_hw_macaddr(dev); | |
1561 | ||
c7b7b042 DB |
1562 | /* Board setup must set the relevant edge trigger type; |
1563 | * level triggers won't currently work. | |
1564 | */ | |
1565 | ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv); | |
3ec9c11d CL |
1566 | if (ret < 0) { |
1567 | if (netif_msg_probe(priv)) | |
1568 | dev_err(&spi->dev, DRV_NAME ": request irq %d failed " | |
1569 | "(ret = %d)\n", spi->irq, ret); | |
1570 | goto error_irq; | |
1571 | } | |
1572 | ||
1573 | dev->if_port = IF_PORT_10BASET; | |
1574 | dev->irq = spi->irq; | |
1575 | dev->open = enc28j60_net_open; | |
1576 | dev->stop = enc28j60_net_close; | |
1577 | dev->hard_start_xmit = enc28j60_send_packet; | |
1578 | dev->set_multicast_list = &enc28j60_set_multicast_list; | |
1579 | dev->set_mac_address = enc28j60_set_mac_address; | |
1580 | dev->tx_timeout = &enc28j60_tx_timeout; | |
1581 | dev->watchdog_timeo = TX_TIMEOUT; | |
1582 | SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops); | |
1583 | ||
7dac6f8d DB |
1584 | enc28j60_lowpower(priv, true); |
1585 | ||
3ec9c11d CL |
1586 | ret = register_netdev(dev); |
1587 | if (ret) { | |
1588 | if (netif_msg_probe(priv)) | |
1589 | dev_err(&spi->dev, "register netdev " DRV_NAME | |
1590 | " failed (ret = %d)\n", ret); | |
1591 | goto error_register; | |
1592 | } | |
1593 | dev_info(&dev->dev, DRV_NAME " driver registered\n"); | |
1594 | ||
1595 | return 0; | |
1596 | ||
1597 | error_register: | |
1598 | free_irq(spi->irq, priv); | |
1599 | error_irq: | |
1600 | free_netdev(dev); | |
1601 | error_alloc: | |
1602 | return ret; | |
1603 | } | |
1604 | ||
6fd65882 | 1605 | static int __devexit enc28j60_remove(struct spi_device *spi) |
3ec9c11d CL |
1606 | { |
1607 | struct enc28j60_net *priv = dev_get_drvdata(&spi->dev); | |
1608 | ||
1609 | if (netif_msg_drv(priv)) | |
1610 | printk(KERN_DEBUG DRV_NAME ": remove\n"); | |
1611 | ||
1612 | unregister_netdev(priv->netdev); | |
1613 | free_irq(spi->irq, priv); | |
1614 | free_netdev(priv->netdev); | |
1615 | ||
1616 | return 0; | |
1617 | } | |
1618 | ||
1619 | static struct spi_driver enc28j60_driver = { | |
1620 | .driver = { | |
1621 | .name = DRV_NAME, | |
3ec9c11d | 1622 | .owner = THIS_MODULE, |
6fd65882 | 1623 | }, |
3ec9c11d CL |
1624 | .probe = enc28j60_probe, |
1625 | .remove = __devexit_p(enc28j60_remove), | |
1626 | }; | |
1627 | ||
1628 | static int __init enc28j60_init(void) | |
1629 | { | |
7dac6f8d DB |
1630 | msec20_to_jiffies = msecs_to_jiffies(20); |
1631 | ||
3ec9c11d CL |
1632 | return spi_register_driver(&enc28j60_driver); |
1633 | } | |
1634 | ||
1635 | module_init(enc28j60_init); | |
1636 | ||
1637 | static void __exit enc28j60_exit(void) | |
1638 | { | |
1639 | spi_unregister_driver(&enc28j60_driver); | |
1640 | } | |
1641 | ||
1642 | module_exit(enc28j60_exit); | |
1643 | ||
1644 | MODULE_DESCRIPTION(DRV_NAME " ethernet driver"); | |
1645 | MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>"); | |
1646 | MODULE_LICENSE("GPL"); | |
1647 | module_param_named(debug, debug.msg_enable, int, 0); | |
1648 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)"); |