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1da177e4 LT |
1 | /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */ |
2 | /* | |
3 | Written 1996-1999 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms | |
6 | of the GNU General Public License, incorporated herein by reference. | |
7 | ||
8 | This driver is for the 3Com "Vortex" and "Boomerang" series ethercards. | |
9 | Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597 | |
10 | and the EtherLink XL 3c900 and 3c905 cards. | |
11 | ||
12 | Problem reports and questions should be directed to | |
13 | vortex@scyld.com | |
14 | ||
15 | The author may be reached as becker@scyld.com, or C/O | |
16 | Scyld Computing Corporation | |
17 | 410 Severn Ave., Suite 210 | |
18 | Annapolis MD 21403 | |
19 | ||
1da177e4 LT |
20 | */ |
21 | ||
22 | /* | |
23 | * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation | |
24 | * as well as other drivers | |
25 | * | |
26 | * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k | |
27 | * due to dead code elimination. There will be some performance benefits from this due to | |
28 | * elimination of all the tests and reduced cache footprint. | |
29 | */ | |
30 | ||
31 | ||
32 | #define DRV_NAME "3c59x" | |
1da177e4 LT |
33 | |
34 | ||
35 | ||
36 | /* A few values that may be tweaked. */ | |
37 | /* Keep the ring sizes a power of two for efficiency. */ | |
38 | #define TX_RING_SIZE 16 | |
39 | #define RX_RING_SIZE 32 | |
40 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
41 | ||
42 | /* "Knobs" that adjust features and parameters. */ | |
43 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
44 | Setting to > 1512 effectively disables this feature. */ | |
45 | #ifndef __arm__ | |
46 | static int rx_copybreak = 200; | |
47 | #else | |
48 | /* ARM systems perform better by disregarding the bus-master | |
49 | transfer capability of these cards. -- rmk */ | |
50 | static int rx_copybreak = 1513; | |
51 | #endif | |
52 | /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */ | |
53 | static const int mtu = 1500; | |
54 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ | |
55 | static int max_interrupt_work = 32; | |
56 | /* Tx timeout interval (millisecs) */ | |
57 | static int watchdog = 5000; | |
58 | ||
59 | /* Allow aggregation of Tx interrupts. Saves CPU load at the cost | |
60 | * of possible Tx stalls if the system is blocking interrupts | |
61 | * somewhere else. Undefine this to disable. | |
62 | */ | |
63 | #define tx_interrupt_mitigation 1 | |
64 | ||
65 | /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */ | |
66 | #define vortex_debug debug | |
67 | #ifdef VORTEX_DEBUG | |
68 | static int vortex_debug = VORTEX_DEBUG; | |
69 | #else | |
70 | static int vortex_debug = 1; | |
71 | #endif | |
72 | ||
1da177e4 LT |
73 | #include <linux/module.h> |
74 | #include <linux/kernel.h> | |
75 | #include <linux/string.h> | |
76 | #include <linux/timer.h> | |
77 | #include <linux/errno.h> | |
78 | #include <linux/in.h> | |
79 | #include <linux/ioport.h> | |
1da177e4 LT |
80 | #include <linux/interrupt.h> |
81 | #include <linux/pci.h> | |
82 | #include <linux/mii.h> | |
83 | #include <linux/init.h> | |
84 | #include <linux/netdevice.h> | |
85 | #include <linux/etherdevice.h> | |
86 | #include <linux/skbuff.h> | |
87 | #include <linux/ethtool.h> | |
88 | #include <linux/highmem.h> | |
89 | #include <linux/eisa.h> | |
90 | #include <linux/bitops.h> | |
ff5688ae | 91 | #include <linux/jiffies.h> |
5a0e3ad6 | 92 | #include <linux/gfp.h> |
60e4ad7a | 93 | #include <asm/irq.h> /* For nr_irqs only. */ |
1da177e4 LT |
94 | #include <asm/io.h> |
95 | #include <asm/uaccess.h> | |
96 | ||
97 | /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. | |
98 | This is only in the support-all-kernels source code. */ | |
99 | ||
100 | #define RUN_AT(x) (jiffies + (x)) | |
101 | ||
102 | #include <linux/delay.h> | |
103 | ||
104 | ||
86de79b6 SH |
105 | static const char version[] __devinitconst = |
106 | DRV_NAME ": Donald Becker and others.\n"; | |
1da177e4 LT |
107 | |
108 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
61238602 | 109 | MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "); |
1da177e4 | 110 | MODULE_LICENSE("GPL"); |
1da177e4 LT |
111 | |
112 | ||
113 | /* Operational parameter that usually are not changed. */ | |
114 | ||
115 | /* The Vortex size is twice that of the original EtherLinkIII series: the | |
116 | runtime register window, window 1, is now always mapped in. | |
117 | The Boomerang size is twice as large as the Vortex -- it has additional | |
118 | bus master control registers. */ | |
119 | #define VORTEX_TOTAL_SIZE 0x20 | |
120 | #define BOOMERANG_TOTAL_SIZE 0x40 | |
121 | ||
122 | /* Set iff a MII transceiver on any interface requires mdio preamble. | |
123 | This only set with the original DP83840 on older 3c905 boards, so the extra | |
124 | code size of a per-interface flag is not worthwhile. */ | |
125 | static char mii_preamble_required; | |
126 | ||
127 | #define PFX DRV_NAME ": " | |
128 | ||
129 | ||
130 | ||
131 | /* | |
132 | Theory of Operation | |
133 | ||
134 | I. Board Compatibility | |
135 | ||
136 | This device driver is designed for the 3Com FastEtherLink and FastEtherLink | |
137 | XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs | |
138 | versions of the FastEtherLink cards. The supported product IDs are | |
139 | 3c590, 3c592, 3c595, 3c597, 3c900, 3c905 | |
140 | ||
141 | The related ISA 3c515 is supported with a separate driver, 3c515.c, included | |
142 | with the kernel source or available from | |
143 | cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html | |
144 | ||
145 | II. Board-specific settings | |
146 | ||
147 | PCI bus devices are configured by the system at boot time, so no jumpers | |
148 | need to be set on the board. The system BIOS should be set to assign the | |
149 | PCI INTA signal to an otherwise unused system IRQ line. | |
150 | ||
151 | The EEPROM settings for media type and forced-full-duplex are observed. | |
152 | The EEPROM media type should be left at the default "autoselect" unless using | |
153 | 10base2 or AUI connections which cannot be reliably detected. | |
154 | ||
155 | III. Driver operation | |
156 | ||
157 | The 3c59x series use an interface that's very similar to the previous 3c5x9 | |
158 | series. The primary interface is two programmed-I/O FIFOs, with an | |
159 | alternate single-contiguous-region bus-master transfer (see next). | |
160 | ||
161 | The 3c900 "Boomerang" series uses a full-bus-master interface with separate | |
162 | lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet, | |
163 | DEC Tulip and Intel Speedo3. The first chip version retains a compatible | |
164 | programmed-I/O interface that has been removed in 'B' and subsequent board | |
165 | revisions. | |
166 | ||
167 | One extension that is advertised in a very large font is that the adapters | |
168 | are capable of being bus masters. On the Vortex chip this capability was | |
169 | only for a single contiguous region making it far less useful than the full | |
170 | bus master capability. There is a significant performance impact of taking | |
171 | an extra interrupt or polling for the completion of each transfer, as well | |
172 | as difficulty sharing the single transfer engine between the transmit and | |
173 | receive threads. Using DMA transfers is a win only with large blocks or | |
174 | with the flawed versions of the Intel Orion motherboard PCI controller. | |
175 | ||
176 | The Boomerang chip's full-bus-master interface is useful, and has the | |
177 | currently-unused advantages over other similar chips that queued transmit | |
178 | packets may be reordered and receive buffer groups are associated with a | |
179 | single frame. | |
180 | ||
181 | With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme. | |
182 | Rather than a fixed intermediate receive buffer, this scheme allocates | |
183 | full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as | |
184 | the copying breakpoint: it is chosen to trade-off the memory wasted by | |
185 | passing the full-sized skbuff to the queue layer for all frames vs. the | |
186 | copying cost of copying a frame to a correctly-sized skbuff. | |
187 | ||
188 | IIIC. Synchronization | |
189 | The driver runs as two independent, single-threaded flows of control. One | |
190 | is the send-packet routine, which enforces single-threaded use by the | |
191 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
192 | threaded by the hardware and other software. | |
193 | ||
194 | IV. Notes | |
195 | ||
196 | Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development | |
197 | 3c590, 3c595, and 3c900 boards. | |
198 | The name "Vortex" is the internal 3Com project name for the PCI ASIC, and | |
199 | the EISA version is called "Demon". According to Terry these names come | |
200 | from rides at the local amusement park. | |
201 | ||
202 | The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes! | |
203 | This driver only supports ethernet packets because of the skbuff allocation | |
204 | limit of 4K. | |
205 | */ | |
206 | ||
207 | /* This table drives the PCI probe routines. It's mostly boilerplate in all | |
208 | of the drivers, and will likely be provided by some future kernel. | |
209 | */ | |
210 | enum pci_flags_bit { | |
1f1bd5fc | 211 | PCI_USES_MASTER=4, |
1da177e4 LT |
212 | }; |
213 | ||
214 | enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8, | |
215 | EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */ | |
216 | HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100, | |
217 | INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800, | |
218 | EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000, | |
219 | EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, }; | |
220 | ||
221 | enum vortex_chips { | |
222 | CH_3C590 = 0, | |
223 | CH_3C592, | |
224 | CH_3C597, | |
225 | CH_3C595_1, | |
226 | CH_3C595_2, | |
227 | ||
228 | CH_3C595_3, | |
229 | CH_3C900_1, | |
230 | CH_3C900_2, | |
231 | CH_3C900_3, | |
232 | CH_3C900_4, | |
233 | ||
234 | CH_3C900_5, | |
235 | CH_3C900B_FL, | |
236 | CH_3C905_1, | |
237 | CH_3C905_2, | |
b4adbb4d | 238 | CH_3C905B_TX, |
1da177e4 LT |
239 | CH_3C905B_1, |
240 | ||
241 | CH_3C905B_2, | |
242 | CH_3C905B_FX, | |
243 | CH_3C905C, | |
244 | CH_3C9202, | |
245 | CH_3C980, | |
246 | CH_3C9805, | |
247 | ||
248 | CH_3CSOHO100_TX, | |
249 | CH_3C555, | |
250 | CH_3C556, | |
251 | CH_3C556B, | |
252 | CH_3C575, | |
253 | ||
254 | CH_3C575_1, | |
255 | CH_3CCFE575, | |
256 | CH_3CCFE575CT, | |
257 | CH_3CCFE656, | |
258 | CH_3CCFEM656, | |
259 | ||
260 | CH_3CCFEM656_1, | |
261 | CH_3C450, | |
262 | CH_3C920, | |
263 | CH_3C982A, | |
264 | CH_3C982B, | |
265 | ||
266 | CH_905BT4, | |
267 | CH_920B_EMB_WNM, | |
268 | }; | |
269 | ||
270 | ||
271 | /* note: this array directly indexed by above enums, and MUST | |
272 | * be kept in sync with both the enums above, and the PCI device | |
273 | * table below | |
274 | */ | |
275 | static struct vortex_chip_info { | |
276 | const char *name; | |
277 | int flags; | |
278 | int drv_flags; | |
279 | int io_size; | |
280 | } vortex_info_tbl[] __devinitdata = { | |
281 | {"3c590 Vortex 10Mbps", | |
1f1bd5fc | 282 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 | 283 | {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */ |
1f1bd5fc | 284 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 | 285 | {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */ |
1f1bd5fc | 286 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 | 287 | {"3c595 Vortex 100baseTx", |
1f1bd5fc | 288 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 | 289 | {"3c595 Vortex 100baseT4", |
1f1bd5fc | 290 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 LT |
291 | |
292 | {"3c595 Vortex 100base-MII", | |
1f1bd5fc | 293 | PCI_USES_MASTER, IS_VORTEX, 32, }, |
1da177e4 | 294 | {"3c900 Boomerang 10baseT", |
1f1bd5fc | 295 | PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, }, |
1da177e4 | 296 | {"3c900 Boomerang 10Mbps Combo", |
1f1bd5fc | 297 | PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, }, |
1da177e4 | 298 | {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */ |
1f1bd5fc | 299 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, |
1da177e4 | 300 | {"3c900 Cyclone 10Mbps Combo", |
1f1bd5fc | 301 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, |
1da177e4 LT |
302 | |
303 | {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */ | |
1f1bd5fc | 304 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, |
1da177e4 | 305 | {"3c900B-FL Cyclone 10base-FL", |
1f1bd5fc | 306 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, |
1da177e4 | 307 | {"3c905 Boomerang 100baseTx", |
1f1bd5fc | 308 | PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, |
1da177e4 | 309 | {"3c905 Boomerang 100baseT4", |
1f1bd5fc | 310 | PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, |
b4adbb4d PT |
311 | {"3C905B-TX Fast Etherlink XL PCI", |
312 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, | |
1da177e4 | 313 | {"3c905B Cyclone 100baseTx", |
1f1bd5fc | 314 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, |
1da177e4 LT |
315 | |
316 | {"3c905B Cyclone 10/100/BNC", | |
1f1bd5fc | 317 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, }, |
1da177e4 | 318 | {"3c905B-FX Cyclone 100baseFx", |
1f1bd5fc | 319 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, |
1da177e4 | 320 | {"3c905C Tornado", |
1f1bd5fc | 321 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, |
1da177e4 | 322 | {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)", |
1f1bd5fc | 323 | PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, }, |
1da177e4 | 324 | {"3c980 Cyclone", |
aa807f79 | 325 | PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, |
1da177e4 LT |
326 | |
327 | {"3c980C Python-T", | |
1f1bd5fc | 328 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, }, |
1da177e4 | 329 | {"3cSOHO100-TX Hurricane", |
b8a1fcee | 330 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, |
1da177e4 | 331 | {"3c555 Laptop Hurricane", |
1f1bd5fc | 332 | PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, }, |
1da177e4 | 333 | {"3c556 Laptop Tornado", |
1f1bd5fc | 334 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR| |
1da177e4 LT |
335 | HAS_HWCKSM, 128, }, |
336 | {"3c556B Laptop Hurricane", | |
1f1bd5fc | 337 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR| |
1da177e4 LT |
338 | WNO_XCVR_PWR|HAS_HWCKSM, 128, }, |
339 | ||
340 | {"3c575 [Megahertz] 10/100 LAN CardBus", | |
1f1bd5fc | 341 | PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, }, |
1da177e4 | 342 | {"3c575 Boomerang CardBus", |
1f1bd5fc | 343 | PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, }, |
1da177e4 | 344 | {"3CCFE575BT Cyclone CardBus", |
1f1bd5fc | 345 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT| |
1da177e4 LT |
346 | INVERT_LED_PWR|HAS_HWCKSM, 128, }, |
347 | {"3CCFE575CT Tornado CardBus", | |
1f1bd5fc | 348 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| |
1da177e4 LT |
349 | MAX_COLLISION_RESET|HAS_HWCKSM, 128, }, |
350 | {"3CCFE656 Cyclone CardBus", | |
1f1bd5fc | 351 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| |
1da177e4 LT |
352 | INVERT_LED_PWR|HAS_HWCKSM, 128, }, |
353 | ||
354 | {"3CCFEM656B Cyclone+Winmodem CardBus", | |
1f1bd5fc | 355 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| |
1da177e4 LT |
356 | INVERT_LED_PWR|HAS_HWCKSM, 128, }, |
357 | {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */ | |
1f1bd5fc | 358 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| |
1da177e4 LT |
359 | MAX_COLLISION_RESET|HAS_HWCKSM, 128, }, |
360 | {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */ | |
1f1bd5fc | 361 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, |
1da177e4 | 362 | {"3c920 Tornado", |
1f1bd5fc | 363 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, |
1da177e4 | 364 | {"3c982 Hydra Dual Port A", |
1f1bd5fc | 365 | PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, }, |
1da177e4 LT |
366 | |
367 | {"3c982 Hydra Dual Port B", | |
1f1bd5fc | 368 | PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, }, |
1da177e4 | 369 | {"3c905B-T4", |
1f1bd5fc | 370 | PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, |
1da177e4 | 371 | {"3c920B-EMB-WNM Tornado", |
1f1bd5fc | 372 | PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, |
1da177e4 LT |
373 | |
374 | {NULL,}, /* NULL terminated list. */ | |
375 | }; | |
376 | ||
377 | ||
a3aa1884 | 378 | static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = { |
1da177e4 LT |
379 | { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 }, |
380 | { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 }, | |
381 | { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 }, | |
382 | { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 }, | |
383 | { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 }, | |
384 | ||
385 | { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 }, | |
386 | { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 }, | |
387 | { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 }, | |
388 | { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 }, | |
389 | { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 }, | |
390 | ||
391 | { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 }, | |
392 | { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL }, | |
393 | { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 }, | |
394 | { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 }, | |
b4adbb4d | 395 | { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX }, |
1da177e4 LT |
396 | { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 }, |
397 | ||
398 | { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 }, | |
399 | { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX }, | |
400 | { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C }, | |
401 | { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 }, | |
402 | { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 }, | |
403 | { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 }, | |
404 | ||
405 | { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX }, | |
406 | { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 }, | |
407 | { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 }, | |
408 | { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B }, | |
409 | { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 }, | |
410 | ||
411 | { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 }, | |
412 | { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 }, | |
413 | { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT }, | |
414 | { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 }, | |
415 | { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 }, | |
416 | ||
417 | { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 }, | |
418 | { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 }, | |
419 | { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 }, | |
420 | { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A }, | |
421 | { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B }, | |
422 | ||
423 | { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 }, | |
424 | { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM }, | |
425 | ||
426 | {0,} /* 0 terminated list. */ | |
427 | }; | |
428 | MODULE_DEVICE_TABLE(pci, vortex_pci_tbl); | |
429 | ||
430 | ||
431 | /* Operational definitions. | |
432 | These are not used by other compilation units and thus are not | |
433 | exported in a ".h" file. | |
434 | ||
435 | First the windows. There are eight register windows, with the command | |
436 | and status registers available in each. | |
437 | */ | |
1da177e4 LT |
438 | #define EL3_CMD 0x0e |
439 | #define EL3_STATUS 0x0e | |
440 | ||
441 | /* The top five bits written to EL3_CMD are a command, the lower | |
442 | 11 bits are the parameter, if applicable. | |
443 | Note that 11 parameters bits was fine for ethernet, but the new chip | |
444 | can handle FDDI length frames (~4500 octets) and now parameters count | |
445 | 32-bit 'Dwords' rather than octets. */ | |
446 | ||
447 | enum vortex_cmd { | |
448 | TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, | |
449 | RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, | |
450 | UpStall = 6<<11, UpUnstall = (6<<11)+1, | |
451 | DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, | |
452 | RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, | |
453 | FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, | |
454 | SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, | |
455 | SetTxThreshold = 18<<11, SetTxStart = 19<<11, | |
456 | StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, | |
457 | StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,}; | |
458 | ||
459 | /* The SetRxFilter command accepts the following classes: */ | |
460 | enum RxFilter { | |
461 | RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }; | |
462 | ||
463 | /* Bits in the general status register. */ | |
464 | enum vortex_status { | |
465 | IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, | |
466 | TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, | |
467 | IntReq = 0x0040, StatsFull = 0x0080, | |
468 | DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, | |
469 | DMAInProgress = 1<<11, /* DMA controller is still busy.*/ | |
470 | CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/ | |
471 | }; | |
472 | ||
473 | /* Register window 1 offsets, the window used in normal operation. | |
474 | On the Vortex this window is always mapped at offsets 0x10-0x1f. */ | |
475 | enum Window1 { | |
476 | TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, | |
477 | RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B, | |
478 | TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ | |
479 | }; | |
480 | enum Window0 { | |
481 | Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ | |
482 | Wn0EepromData = 12, /* Window 0: EEPROM results register. */ | |
483 | IntrStatus=0x0E, /* Valid in all windows. */ | |
484 | }; | |
485 | enum Win0_EEPROM_bits { | |
486 | EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, | |
487 | EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ | |
488 | EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ | |
489 | }; | |
490 | /* EEPROM locations. */ | |
491 | enum eeprom_offset { | |
492 | PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3, | |
493 | EtherLink3ID=7, IFXcvrIO=8, IRQLine=9, | |
494 | NodeAddr01=10, NodeAddr23=11, NodeAddr45=12, | |
495 | DriverTune=13, Checksum=15}; | |
496 | ||
497 | enum Window2 { /* Window 2. */ | |
498 | Wn2_ResetOptions=12, | |
499 | }; | |
500 | enum Window3 { /* Window 3: MAC/config bits. */ | |
501 | Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8, | |
502 | }; | |
503 | ||
504 | #define BFEXT(value, offset, bitcount) \ | |
505 | ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) | |
506 | ||
507 | #define BFINS(lhs, rhs, offset, bitcount) \ | |
508 | (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ | |
509 | (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) | |
510 | ||
511 | #define RAM_SIZE(v) BFEXT(v, 0, 3) | |
512 | #define RAM_WIDTH(v) BFEXT(v, 3, 1) | |
513 | #define RAM_SPEED(v) BFEXT(v, 4, 2) | |
514 | #define ROM_SIZE(v) BFEXT(v, 6, 2) | |
515 | #define RAM_SPLIT(v) BFEXT(v, 16, 2) | |
516 | #define XCVR(v) BFEXT(v, 20, 4) | |
517 | #define AUTOSELECT(v) BFEXT(v, 24, 1) | |
518 | ||
519 | enum Window4 { /* Window 4: Xcvr/media bits. */ | |
520 | Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10, | |
521 | }; | |
522 | enum Win4_Media_bits { | |
523 | Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ | |
524 | Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ | |
525 | Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ | |
526 | Media_LnkBeat = 0x0800, | |
527 | }; | |
528 | enum Window7 { /* Window 7: Bus Master control. */ | |
529 | Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6, | |
530 | Wn7_MasterStatus = 12, | |
531 | }; | |
532 | /* Boomerang bus master control registers. */ | |
533 | enum MasterCtrl { | |
534 | PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, | |
535 | TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38, | |
536 | }; | |
537 | ||
538 | /* The Rx and Tx descriptor lists. | |
539 | Caution Alpha hackers: these types are 32 bits! Note also the 8 byte | |
540 | alignment contraint on tx_ring[] and rx_ring[]. */ | |
541 | #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ | |
542 | #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ | |
543 | struct boom_rx_desc { | |
cc2d6596 AV |
544 | __le32 next; /* Last entry points to 0. */ |
545 | __le32 status; | |
546 | __le32 addr; /* Up to 63 addr/len pairs possible. */ | |
547 | __le32 length; /* Set LAST_FRAG to indicate last pair. */ | |
1da177e4 LT |
548 | }; |
549 | /* Values for the Rx status entry. */ | |
550 | enum rx_desc_status { | |
551 | RxDComplete=0x00008000, RxDError=0x4000, | |
552 | /* See boomerang_rx() for actual error bits */ | |
553 | IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27, | |
554 | IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31, | |
555 | }; | |
556 | ||
557 | #ifdef MAX_SKB_FRAGS | |
558 | #define DO_ZEROCOPY 1 | |
559 | #else | |
560 | #define DO_ZEROCOPY 0 | |
561 | #endif | |
562 | ||
563 | struct boom_tx_desc { | |
cc2d6596 AV |
564 | __le32 next; /* Last entry points to 0. */ |
565 | __le32 status; /* bits 0:12 length, others see below. */ | |
1da177e4 LT |
566 | #if DO_ZEROCOPY |
567 | struct { | |
cc2d6596 AV |
568 | __le32 addr; |
569 | __le32 length; | |
1da177e4 LT |
570 | } frag[1+MAX_SKB_FRAGS]; |
571 | #else | |
cc2d6596 AV |
572 | __le32 addr; |
573 | __le32 length; | |
1da177e4 LT |
574 | #endif |
575 | }; | |
576 | ||
577 | /* Values for the Tx status entry. */ | |
578 | enum tx_desc_status { | |
579 | CRCDisable=0x2000, TxDComplete=0x8000, | |
580 | AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000, | |
581 | TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */ | |
582 | }; | |
583 | ||
584 | /* Chip features we care about in vp->capabilities, read from the EEPROM. */ | |
585 | enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 }; | |
586 | ||
587 | struct vortex_extra_stats { | |
8d1d0340 SK |
588 | unsigned long tx_deferred; |
589 | unsigned long tx_max_collisions; | |
590 | unsigned long tx_multiple_collisions; | |
591 | unsigned long tx_single_collisions; | |
592 | unsigned long rx_bad_ssd; | |
1da177e4 LT |
593 | }; |
594 | ||
595 | struct vortex_private { | |
596 | /* The Rx and Tx rings should be quad-word-aligned. */ | |
597 | struct boom_rx_desc* rx_ring; | |
598 | struct boom_tx_desc* tx_ring; | |
599 | dma_addr_t rx_ring_dma; | |
600 | dma_addr_t tx_ring_dma; | |
601 | /* The addresses of transmit- and receive-in-place skbuffs. */ | |
602 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
603 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
604 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
605 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ | |
1da177e4 LT |
606 | struct vortex_extra_stats xstats; /* NIC-specific extra stats */ |
607 | struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ | |
608 | dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */ | |
609 | ||
610 | /* PCI configuration space information. */ | |
611 | struct device *gendev; | |
62afe595 JL |
612 | void __iomem *ioaddr; /* IO address space */ |
613 | void __iomem *cb_fn_base; /* CardBus function status addr space. */ | |
1da177e4 LT |
614 | |
615 | /* Some values here only for performance evaluation and path-coverage */ | |
616 | int rx_nocopy, rx_copy, queued_packet, rx_csumhits; | |
617 | int card_idx; | |
618 | ||
619 | /* The remainder are related to chip state, mostly media selection. */ | |
620 | struct timer_list timer; /* Media selection timer. */ | |
621 | struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */ | |
622 | int options; /* User-settable misc. driver options. */ | |
623 | unsigned int media_override:4, /* Passed-in media type. */ | |
624 | default_media:4, /* Read from the EEPROM/Wn3_Config. */ | |
09ce3512 | 625 | full_duplex:1, autoselect:1, |
1da177e4 LT |
626 | bus_master:1, /* Vortex can only do a fragment bus-m. */ |
627 | full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */ | |
628 | flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */ | |
629 | partner_flow_ctrl:1, /* Partner supports flow control */ | |
630 | has_nway:1, | |
631 | enable_wol:1, /* Wake-on-LAN is enabled */ | |
632 | pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */ | |
633 | open:1, | |
634 | medialock:1, | |
635 | must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */ | |
aa25ab7d NH |
636 | large_frames:1, /* accept large frames */ |
637 | handling_irq:1; /* private in_irq indicator */ | |
84176b7b DK |
638 | /* {get|set}_wol operations are already serialized by rtnl. |
639 | * no additional locking is required for the enable_wol and acpi_set_WOL() | |
640 | */ | |
1da177e4 LT |
641 | int drv_flags; |
642 | u16 status_enable; | |
643 | u16 intr_enable; | |
644 | u16 available_media; /* From Wn3_Options. */ | |
645 | u16 capabilities, info1, info2; /* Various, from EEPROM. */ | |
646 | u16 advertising; /* NWay media advertisement */ | |
647 | unsigned char phys[2]; /* MII device addresses. */ | |
648 | u16 deferred; /* Resend these interrupts when we | |
649 | * bale from the ISR */ | |
650 | u16 io_size; /* Size of PCI region (for release_region) */ | |
de847272 BH |
651 | |
652 | /* Serialises access to hardware other than MII and variables below. | |
24cd804d | 653 | * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */ |
de847272 BH |
654 | spinlock_t lock; |
655 | ||
656 | spinlock_t mii_lock; /* Serialises access to MII */ | |
657 | struct mii_if_info mii; /* MII lib hooks/info */ | |
658 | spinlock_t window_lock; /* Serialises access to windowed regs */ | |
659 | int window; /* Register window */ | |
1da177e4 LT |
660 | }; |
661 | ||
a095cfc4 BH |
662 | static void window_set(struct vortex_private *vp, int window) |
663 | { | |
664 | if (window != vp->window) { | |
665 | iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD); | |
666 | vp->window = window; | |
667 | } | |
668 | } | |
669 | ||
670 | #define DEFINE_WINDOW_IO(size) \ | |
671 | static u ## size \ | |
672 | window_read ## size(struct vortex_private *vp, int window, int addr) \ | |
673 | { \ | |
de847272 BH |
674 | unsigned long flags; \ |
675 | u ## size ret; \ | |
676 | spin_lock_irqsave(&vp->window_lock, flags); \ | |
a095cfc4 | 677 | window_set(vp, window); \ |
de847272 BH |
678 | ret = ioread ## size(vp->ioaddr + addr); \ |
679 | spin_unlock_irqrestore(&vp->window_lock, flags); \ | |
680 | return ret; \ | |
a095cfc4 BH |
681 | } \ |
682 | static void \ | |
683 | window_write ## size(struct vortex_private *vp, u ## size value, \ | |
684 | int window, int addr) \ | |
685 | { \ | |
de847272 BH |
686 | unsigned long flags; \ |
687 | spin_lock_irqsave(&vp->window_lock, flags); \ | |
a095cfc4 BH |
688 | window_set(vp, window); \ |
689 | iowrite ## size(value, vp->ioaddr + addr); \ | |
de847272 | 690 | spin_unlock_irqrestore(&vp->window_lock, flags); \ |
a095cfc4 BH |
691 | } |
692 | DEFINE_WINDOW_IO(8) | |
693 | DEFINE_WINDOW_IO(16) | |
694 | DEFINE_WINDOW_IO(32) | |
695 | ||
1da177e4 LT |
696 | #ifdef CONFIG_PCI |
697 | #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL) | |
698 | #else | |
699 | #define DEVICE_PCI(dev) NULL | |
700 | #endif | |
701 | ||
d530db0d NK |
702 | #define VORTEX_PCI(vp) \ |
703 | ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)) | |
1da177e4 LT |
704 | |
705 | #ifdef CONFIG_EISA | |
706 | #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL) | |
707 | #else | |
708 | #define DEVICE_EISA(dev) NULL | |
709 | #endif | |
710 | ||
d530db0d NK |
711 | #define VORTEX_EISA(vp) \ |
712 | ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)) | |
1da177e4 LT |
713 | |
714 | /* The action to take with a media selection timer tick. | |
715 | Note that we deviate from the 3Com order by checking 10base2 before AUI. | |
716 | */ | |
717 | enum xcvr_types { | |
718 | XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, | |
719 | XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10, | |
720 | }; | |
721 | ||
f71e1309 | 722 | static const struct media_table { |
1da177e4 LT |
723 | char *name; |
724 | unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ | |
725 | mask:8, /* The transceiver-present bit in Wn3_Config.*/ | |
726 | next:8; /* The media type to try next. */ | |
727 | int wait; /* Time before we check media status. */ | |
728 | } media_tbl[] = { | |
729 | { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10}, | |
730 | { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10}, | |
731 | { "undefined", 0, 0x80, XCVR_10baseT, 10000}, | |
732 | { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10}, | |
733 | { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10}, | |
734 | { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10}, | |
735 | { "MII", 0, 0x41, XCVR_10baseT, 3*HZ }, | |
736 | { "undefined", 0, 0x01, XCVR_10baseT, 10000}, | |
737 | { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ}, | |
738 | { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ }, | |
739 | { "Default", 0, 0xFF, XCVR_10baseT, 10000}, | |
740 | }; | |
741 | ||
742 | static struct { | |
743 | const char str[ETH_GSTRING_LEN]; | |
744 | } ethtool_stats_keys[] = { | |
745 | { "tx_deferred" }, | |
8d1d0340 | 746 | { "tx_max_collisions" }, |
1da177e4 | 747 | { "tx_multiple_collisions" }, |
8d1d0340 | 748 | { "tx_single_collisions" }, |
1da177e4 LT |
749 | { "rx_bad_ssd" }, |
750 | }; | |
751 | ||
752 | /* number of ETHTOOL_GSTATS u64's */ | |
8d1d0340 | 753 | #define VORTEX_NUM_STATS 5 |
1da177e4 | 754 | |
62afe595 | 755 | static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq, |
1da177e4 | 756 | int chip_idx, int card_idx); |
c8303d10 | 757 | static int vortex_up(struct net_device *dev); |
1da177e4 LT |
758 | static void vortex_down(struct net_device *dev, int final); |
759 | static int vortex_open(struct net_device *dev); | |
a095cfc4 | 760 | static void mdio_sync(struct vortex_private *vp, int bits); |
1da177e4 LT |
761 | static int mdio_read(struct net_device *dev, int phy_id, int location); |
762 | static void mdio_write(struct net_device *vp, int phy_id, int location, int value); | |
763 | static void vortex_timer(unsigned long arg); | |
764 | static void rx_oom_timer(unsigned long arg); | |
27a1de95 SH |
765 | static netdev_tx_t vortex_start_xmit(struct sk_buff *skb, |
766 | struct net_device *dev); | |
767 | static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb, | |
768 | struct net_device *dev); | |
1da177e4 LT |
769 | static int vortex_rx(struct net_device *dev); |
770 | static int boomerang_rx(struct net_device *dev); | |
7d12e780 DH |
771 | static irqreturn_t vortex_interrupt(int irq, void *dev_id); |
772 | static irqreturn_t boomerang_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
773 | static int vortex_close(struct net_device *dev); |
774 | static void dump_tx_ring(struct net_device *dev); | |
62afe595 | 775 | static void update_stats(void __iomem *ioaddr, struct net_device *dev); |
1da177e4 LT |
776 | static struct net_device_stats *vortex_get_stats(struct net_device *dev); |
777 | static void set_rx_mode(struct net_device *dev); | |
778 | #ifdef CONFIG_PCI | |
779 | static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
780 | #endif | |
781 | static void vortex_tx_timeout(struct net_device *dev); | |
782 | static void acpi_set_WOL(struct net_device *dev); | |
7282d491 | 783 | static const struct ethtool_ops vortex_ethtool_ops; |
1da177e4 LT |
784 | static void set_8021q_mode(struct net_device *dev, int enable); |
785 | ||
1da177e4 LT |
786 | /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ |
787 | /* Option count limit only -- unlimited interfaces are supported. */ | |
788 | #define MAX_UNITS 8 | |
9954ab7f JL |
789 | static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 }; |
790 | static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; | |
791 | static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; | |
792 | static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; | |
793 | static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; | |
900fd17d | 794 | static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; |
1da177e4 LT |
795 | static int global_options = -1; |
796 | static int global_full_duplex = -1; | |
797 | static int global_enable_wol = -1; | |
900fd17d | 798 | static int global_use_mmio = -1; |
1da177e4 | 799 | |
1da177e4 LT |
800 | /* Variables to work-around the Compaq PCI BIOS32 problem. */ |
801 | static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900; | |
802 | static struct net_device *compaq_net_device; | |
803 | ||
804 | static int vortex_cards_found; | |
805 | ||
806 | module_param(debug, int, 0); | |
807 | module_param(global_options, int, 0); | |
808 | module_param_array(options, int, NULL, 0); | |
809 | module_param(global_full_duplex, int, 0); | |
810 | module_param_array(full_duplex, int, NULL, 0); | |
811 | module_param_array(hw_checksums, int, NULL, 0); | |
812 | module_param_array(flow_ctrl, int, NULL, 0); | |
813 | module_param(global_enable_wol, int, 0); | |
814 | module_param_array(enable_wol, int, NULL, 0); | |
815 | module_param(rx_copybreak, int, 0); | |
816 | module_param(max_interrupt_work, int, 0); | |
817 | module_param(compaq_ioaddr, int, 0); | |
818 | module_param(compaq_irq, int, 0); | |
819 | module_param(compaq_device_id, int, 0); | |
820 | module_param(watchdog, int, 0); | |
900fd17d JL |
821 | module_param(global_use_mmio, int, 0); |
822 | module_param_array(use_mmio, int, NULL, 0); | |
1da177e4 LT |
823 | MODULE_PARM_DESC(debug, "3c59x debug level (0-6)"); |
824 | MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex"); | |
825 | MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset"); | |
826 | MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)"); | |
46e5e4a8 | 827 | MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset"); |
1da177e4 LT |
828 | MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)"); |
829 | MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)"); | |
830 | MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)"); | |
46e5e4a8 | 831 | MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset"); |
1da177e4 LT |
832 | MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames"); |
833 | MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt"); | |
834 | MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)"); | |
835 | MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)"); | |
836 | MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)"); | |
837 | MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds"); | |
900fd17d JL |
838 | MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset"); |
839 | MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)"); | |
1da177e4 LT |
840 | |
841 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
842 | static void poll_vortex(struct net_device *dev) | |
843 | { | |
844 | struct vortex_private *vp = netdev_priv(dev); | |
845 | unsigned long flags; | |
0d38ff1d | 846 | local_irq_save(flags); |
7d12e780 | 847 | (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev); |
1da177e4 | 848 | local_irq_restore(flags); |
6aa20a22 | 849 | } |
1da177e4 LT |
850 | #endif |
851 | ||
852 | #ifdef CONFIG_PM | |
853 | ||
7bfc4ab5 | 854 | static int vortex_suspend(struct device *dev) |
1da177e4 | 855 | { |
7bfc4ab5 AV |
856 | struct pci_dev *pdev = to_pci_dev(dev); |
857 | struct net_device *ndev = pci_get_drvdata(pdev); | |
858 | ||
859 | if (!ndev || !netif_running(ndev)) | |
860 | return 0; | |
861 | ||
862 | netif_device_detach(ndev); | |
863 | vortex_down(ndev, 1); | |
1da177e4 | 864 | |
1da177e4 LT |
865 | return 0; |
866 | } | |
867 | ||
7bfc4ab5 | 868 | static int vortex_resume(struct device *dev) |
1da177e4 | 869 | { |
7bfc4ab5 AV |
870 | struct pci_dev *pdev = to_pci_dev(dev); |
871 | struct net_device *ndev = pci_get_drvdata(pdev); | |
e1265153 | 872 | int err; |
1da177e4 | 873 | |
7bfc4ab5 AV |
874 | if (!ndev || !netif_running(ndev)) |
875 | return 0; | |
876 | ||
877 | err = vortex_up(ndev); | |
878 | if (err) | |
879 | return err; | |
880 | ||
881 | netif_device_attach(ndev); | |
882 | ||
1da177e4 LT |
883 | return 0; |
884 | } | |
885 | ||
47145210 | 886 | static const struct dev_pm_ops vortex_pm_ops = { |
7bfc4ab5 AV |
887 | .suspend = vortex_suspend, |
888 | .resume = vortex_resume, | |
889 | .freeze = vortex_suspend, | |
890 | .thaw = vortex_resume, | |
891 | .poweroff = vortex_suspend, | |
892 | .restore = vortex_resume, | |
893 | }; | |
894 | ||
895 | #define VORTEX_PM_OPS (&vortex_pm_ops) | |
896 | ||
897 | #else /* !CONFIG_PM */ | |
898 | ||
899 | #define VORTEX_PM_OPS NULL | |
900 | ||
901 | #endif /* !CONFIG_PM */ | |
1da177e4 LT |
902 | |
903 | #ifdef CONFIG_EISA | |
948252cb | 904 | static struct eisa_device_id vortex_eisa_ids[] = { |
1da177e4 LT |
905 | { "TCM5920", CH_3C592 }, |
906 | { "TCM5970", CH_3C597 }, | |
907 | { "" } | |
908 | }; | |
07563c71 | 909 | MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids); |
1da177e4 | 910 | |
948252cb | 911 | static int __init vortex_eisa_probe(struct device *device) |
1da177e4 | 912 | { |
62afe595 | 913 | void __iomem *ioaddr; |
1da177e4 LT |
914 | struct eisa_device *edev; |
915 | ||
a880c4cd | 916 | edev = to_eisa_device(device); |
1da177e4 | 917 | |
62afe595 | 918 | if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME)) |
1da177e4 LT |
919 | return -EBUSY; |
920 | ||
62afe595 JL |
921 | ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE); |
922 | ||
923 | if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12, | |
1da177e4 | 924 | edev->id.driver_data, vortex_cards_found)) { |
a880c4cd | 925 | release_region(edev->base_addr, VORTEX_TOTAL_SIZE); |
1da177e4 LT |
926 | return -ENODEV; |
927 | } | |
928 | ||
929 | vortex_cards_found++; | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
95c408a9 | 934 | static int __devexit vortex_eisa_remove(struct device *device) |
1da177e4 LT |
935 | { |
936 | struct eisa_device *edev; | |
937 | struct net_device *dev; | |
938 | struct vortex_private *vp; | |
62afe595 | 939 | void __iomem *ioaddr; |
1da177e4 | 940 | |
a880c4cd SK |
941 | edev = to_eisa_device(device); |
942 | dev = eisa_get_drvdata(edev); | |
1da177e4 LT |
943 | |
944 | if (!dev) { | |
39738e16 | 945 | pr_err("vortex_eisa_remove called for Compaq device!\n"); |
1da177e4 LT |
946 | BUG(); |
947 | } | |
948 | ||
949 | vp = netdev_priv(dev); | |
62afe595 | 950 | ioaddr = vp->ioaddr; |
6aa20a22 | 951 | |
a880c4cd SK |
952 | unregister_netdev(dev); |
953 | iowrite16(TotalReset|0x14, ioaddr + EL3_CMD); | |
954 | release_region(dev->base_addr, VORTEX_TOTAL_SIZE); | |
1da177e4 | 955 | |
a880c4cd | 956 | free_netdev(dev); |
1da177e4 LT |
957 | return 0; |
958 | } | |
95c408a9 RB |
959 | |
960 | static struct eisa_driver vortex_eisa_driver = { | |
961 | .id_table = vortex_eisa_ids, | |
962 | .driver = { | |
963 | .name = "3c59x", | |
964 | .probe = vortex_eisa_probe, | |
965 | .remove = __devexit_p(vortex_eisa_remove) | |
966 | } | |
967 | }; | |
968 | ||
969 | #endif /* CONFIG_EISA */ | |
1da177e4 LT |
970 | |
971 | /* returns count found (>= 0), or negative on error */ | |
a880c4cd | 972 | static int __init vortex_eisa_init(void) |
1da177e4 LT |
973 | { |
974 | int eisa_found = 0; | |
975 | int orig_cards_found = vortex_cards_found; | |
976 | ||
977 | #ifdef CONFIG_EISA | |
c2f6fabb BH |
978 | int err; |
979 | ||
980 | err = eisa_driver_register (&vortex_eisa_driver); | |
981 | if (!err) { | |
982 | /* | |
983 | * Because of the way EISA bus is probed, we cannot assume | |
984 | * any device have been found when we exit from | |
985 | * eisa_driver_register (the bus root driver may not be | |
986 | * initialized yet). So we blindly assume something was | |
25985edc | 987 | * found, and let the sysfs magic happened... |
c2f6fabb BH |
988 | */ |
989 | eisa_found = 1; | |
1da177e4 LT |
990 | } |
991 | #endif | |
6aa20a22 | 992 | |
1da177e4 LT |
993 | /* Special code to work-around the Compaq PCI BIOS32 problem. */ |
994 | if (compaq_ioaddr) { | |
62afe595 JL |
995 | vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE), |
996 | compaq_irq, compaq_device_id, vortex_cards_found++); | |
1da177e4 LT |
997 | } |
998 | ||
999 | return vortex_cards_found - orig_cards_found + eisa_found; | |
1000 | } | |
1001 | ||
1002 | /* returns count (>= 0), or negative on error */ | |
a880c4cd | 1003 | static int __devinit vortex_init_one(struct pci_dev *pdev, |
1da177e4 LT |
1004 | const struct pci_device_id *ent) |
1005 | { | |
900fd17d JL |
1006 | int rc, unit, pci_bar; |
1007 | struct vortex_chip_info *vci; | |
1008 | void __iomem *ioaddr; | |
1da177e4 | 1009 | |
6aa20a22 | 1010 | /* wake up and enable device */ |
a880c4cd | 1011 | rc = pci_enable_device(pdev); |
1da177e4 LT |
1012 | if (rc < 0) |
1013 | goto out; | |
1014 | ||
900fd17d JL |
1015 | unit = vortex_cards_found; |
1016 | ||
1017 | if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) { | |
1018 | /* Determine the default if the user didn't override us */ | |
1019 | vci = &vortex_info_tbl[ent->driver_data]; | |
1020 | pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0; | |
1021 | } else if (unit < MAX_UNITS && use_mmio[unit] >= 0) | |
1022 | pci_bar = use_mmio[unit] ? 1 : 0; | |
1023 | else | |
1024 | pci_bar = global_use_mmio ? 1 : 0; | |
1025 | ||
1026 | ioaddr = pci_iomap(pdev, pci_bar, 0); | |
1027 | if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */ | |
1028 | ioaddr = pci_iomap(pdev, 0, 0); | |
8cd47ea1 KV |
1029 | if (!ioaddr) { |
1030 | pci_disable_device(pdev); | |
1031 | rc = -ENOMEM; | |
1032 | goto out; | |
1033 | } | |
900fd17d JL |
1034 | |
1035 | rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq, | |
1036 | ent->driver_data, unit); | |
1da177e4 | 1037 | if (rc < 0) { |
f89f5d0e | 1038 | pci_iounmap(pdev, ioaddr); |
a880c4cd | 1039 | pci_disable_device(pdev); |
1da177e4 LT |
1040 | goto out; |
1041 | } | |
1042 | ||
1043 | vortex_cards_found++; | |
1044 | ||
1045 | out: | |
1046 | return rc; | |
1047 | } | |
1048 | ||
48b47a5e SH |
1049 | static const struct net_device_ops boomrang_netdev_ops = { |
1050 | .ndo_open = vortex_open, | |
1051 | .ndo_stop = vortex_close, | |
1052 | .ndo_start_xmit = boomerang_start_xmit, | |
1053 | .ndo_tx_timeout = vortex_tx_timeout, | |
1054 | .ndo_get_stats = vortex_get_stats, | |
1055 | #ifdef CONFIG_PCI | |
1056 | .ndo_do_ioctl = vortex_ioctl, | |
1057 | #endif | |
afc4b13d | 1058 | .ndo_set_rx_mode = set_rx_mode, |
48b47a5e SH |
1059 | .ndo_change_mtu = eth_change_mtu, |
1060 | .ndo_set_mac_address = eth_mac_addr, | |
1061 | .ndo_validate_addr = eth_validate_addr, | |
1062 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1063 | .ndo_poll_controller = poll_vortex, | |
1064 | #endif | |
1065 | }; | |
1066 | ||
1067 | static const struct net_device_ops vortex_netdev_ops = { | |
1068 | .ndo_open = vortex_open, | |
1069 | .ndo_stop = vortex_close, | |
1070 | .ndo_start_xmit = vortex_start_xmit, | |
1071 | .ndo_tx_timeout = vortex_tx_timeout, | |
1072 | .ndo_get_stats = vortex_get_stats, | |
1073 | #ifdef CONFIG_PCI | |
1074 | .ndo_do_ioctl = vortex_ioctl, | |
1075 | #endif | |
afc4b13d | 1076 | .ndo_set_rx_mode = set_rx_mode, |
48b47a5e SH |
1077 | .ndo_change_mtu = eth_change_mtu, |
1078 | .ndo_set_mac_address = eth_mac_addr, | |
1079 | .ndo_validate_addr = eth_validate_addr, | |
1080 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1081 | .ndo_poll_controller = poll_vortex, | |
1082 | #endif | |
1083 | }; | |
1084 | ||
1da177e4 LT |
1085 | /* |
1086 | * Start up the PCI/EISA device which is described by *gendev. | |
1087 | * Return 0 on success. | |
1088 | * | |
1089 | * NOTE: pdev can be NULL, for the case of a Compaq device | |
1090 | */ | |
1091 | static int __devinit vortex_probe1(struct device *gendev, | |
62afe595 | 1092 | void __iomem *ioaddr, int irq, |
1da177e4 LT |
1093 | int chip_idx, int card_idx) |
1094 | { | |
1095 | struct vortex_private *vp; | |
1096 | int option; | |
1097 | unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ | |
1098 | int i, step; | |
1099 | struct net_device *dev; | |
1100 | static int printed_version; | |
1101 | int retval, print_info; | |
1102 | struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx]; | |
361d5ee3 | 1103 | const char *print_name = "3c59x"; |
1da177e4 LT |
1104 | struct pci_dev *pdev = NULL; |
1105 | struct eisa_device *edev = NULL; | |
1106 | ||
1107 | if (!printed_version) { | |
39738e16 | 1108 | pr_info("%s", version); |
1da177e4 LT |
1109 | printed_version = 1; |
1110 | } | |
1111 | ||
1112 | if (gendev) { | |
1113 | if ((pdev = DEVICE_PCI(gendev))) { | |
1114 | print_name = pci_name(pdev); | |
1115 | } | |
1116 | ||
1117 | if ((edev = DEVICE_EISA(gendev))) { | |
fb28ad35 | 1118 | print_name = dev_name(&edev->dev); |
1da177e4 LT |
1119 | } |
1120 | } | |
1121 | ||
1122 | dev = alloc_etherdev(sizeof(*vp)); | |
1123 | retval = -ENOMEM; | |
41de8d4c | 1124 | if (!dev) |
1da177e4 | 1125 | goto out; |
41de8d4c | 1126 | |
1da177e4 LT |
1127 | SET_NETDEV_DEV(dev, gendev); |
1128 | vp = netdev_priv(dev); | |
1129 | ||
1130 | option = global_options; | |
1131 | ||
1132 | /* The lower four bits are the media type. */ | |
1133 | if (dev->mem_start) { | |
1134 | /* | |
1135 | * The 'options' param is passed in as the third arg to the | |
1136 | * LILO 'ether=' argument for non-modular use | |
1137 | */ | |
1138 | option = dev->mem_start; | |
1139 | } | |
1140 | else if (card_idx < MAX_UNITS) { | |
1141 | if (options[card_idx] >= 0) | |
1142 | option = options[card_idx]; | |
1143 | } | |
1144 | ||
1145 | if (option > 0) { | |
1146 | if (option & 0x8000) | |
1147 | vortex_debug = 7; | |
1148 | if (option & 0x4000) | |
1149 | vortex_debug = 2; | |
1150 | if (option & 0x0400) | |
1151 | vp->enable_wol = 1; | |
1152 | } | |
1153 | ||
1154 | print_info = (vortex_debug > 1); | |
1155 | if (print_info) | |
39738e16 | 1156 | pr_info("See Documentation/networking/vortex.txt\n"); |
1da177e4 | 1157 | |
39738e16 | 1158 | pr_info("%s: 3Com %s %s at %p.\n", |
1da177e4 LT |
1159 | print_name, |
1160 | pdev ? "PCI" : "EISA", | |
1161 | vci->name, | |
1162 | ioaddr); | |
1163 | ||
62afe595 | 1164 | dev->base_addr = (unsigned long)ioaddr; |
1da177e4 LT |
1165 | dev->irq = irq; |
1166 | dev->mtu = mtu; | |
62afe595 | 1167 | vp->ioaddr = ioaddr; |
1da177e4 LT |
1168 | vp->large_frames = mtu > 1500; |
1169 | vp->drv_flags = vci->drv_flags; | |
1170 | vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0; | |
1171 | vp->io_size = vci->io_size; | |
1172 | vp->card_idx = card_idx; | |
a095cfc4 | 1173 | vp->window = -1; |
1da177e4 LT |
1174 | |
1175 | /* module list only for Compaq device */ | |
1176 | if (gendev == NULL) { | |
1177 | compaq_net_device = dev; | |
1178 | } | |
1179 | ||
1180 | /* PCI-only startup logic */ | |
1181 | if (pdev) { | |
1182 | /* EISA resources already marked, so only PCI needs to do this here */ | |
1183 | /* Ignore return value, because Cardbus drivers already allocate for us */ | |
62afe595 | 1184 | if (request_region(dev->base_addr, vci->io_size, print_name) != NULL) |
1da177e4 LT |
1185 | vp->must_free_region = 1; |
1186 | ||
6aa20a22 | 1187 | /* enable bus-mastering if necessary */ |
1da177e4 | 1188 | if (vci->flags & PCI_USES_MASTER) |
a880c4cd | 1189 | pci_set_master(pdev); |
1da177e4 LT |
1190 | |
1191 | if (vci->drv_flags & IS_VORTEX) { | |
1192 | u8 pci_latency; | |
1193 | u8 new_latency = 248; | |
1194 | ||
1195 | /* Check the PCI latency value. On the 3c590 series the latency timer | |
1196 | must be set to the maximum value to avoid data corruption that occurs | |
1197 | when the timer expires during a transfer. This bug exists the Vortex | |
1198 | chip only. */ | |
1199 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency); | |
1200 | if (pci_latency < new_latency) { | |
39738e16 | 1201 | pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n", |
1da177e4 | 1202 | print_name, pci_latency, new_latency); |
39738e16 | 1203 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency); |
1da177e4 LT |
1204 | } |
1205 | } | |
1206 | } | |
1207 | ||
1208 | spin_lock_init(&vp->lock); | |
de847272 BH |
1209 | spin_lock_init(&vp->mii_lock); |
1210 | spin_lock_init(&vp->window_lock); | |
1da177e4 LT |
1211 | vp->gendev = gendev; |
1212 | vp->mii.dev = dev; | |
1213 | vp->mii.mdio_read = mdio_read; | |
1214 | vp->mii.mdio_write = mdio_write; | |
1215 | vp->mii.phy_id_mask = 0x1f; | |
1216 | vp->mii.reg_num_mask = 0x1f; | |
1217 | ||
1218 | /* Makes sure rings are at least 16 byte aligned. */ | |
1219 | vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE | |
1220 | + sizeof(struct boom_tx_desc) * TX_RING_SIZE, | |
1221 | &vp->rx_ring_dma); | |
1222 | retval = -ENOMEM; | |
cc2d6596 | 1223 | if (!vp->rx_ring) |
1da177e4 LT |
1224 | goto free_region; |
1225 | ||
1226 | vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE); | |
1227 | vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE; | |
1228 | ||
1229 | /* if we are a PCI driver, we store info in pdev->driver_data | |
6aa20a22 | 1230 | * instead of a module list */ |
1da177e4 LT |
1231 | if (pdev) |
1232 | pci_set_drvdata(pdev, dev); | |
1233 | if (edev) | |
a880c4cd | 1234 | eisa_set_drvdata(edev, dev); |
1da177e4 LT |
1235 | |
1236 | vp->media_override = 7; | |
1237 | if (option >= 0) { | |
1238 | vp->media_override = ((option & 7) == 2) ? 0 : option & 15; | |
1239 | if (vp->media_override != 7) | |
1240 | vp->medialock = 1; | |
1241 | vp->full_duplex = (option & 0x200) ? 1 : 0; | |
1242 | vp->bus_master = (option & 16) ? 1 : 0; | |
1243 | } | |
1244 | ||
1245 | if (global_full_duplex > 0) | |
1246 | vp->full_duplex = 1; | |
1247 | if (global_enable_wol > 0) | |
1248 | vp->enable_wol = 1; | |
1249 | ||
1250 | if (card_idx < MAX_UNITS) { | |
1251 | if (full_duplex[card_idx] > 0) | |
1252 | vp->full_duplex = 1; | |
1253 | if (flow_ctrl[card_idx] > 0) | |
1254 | vp->flow_ctrl = 1; | |
1255 | if (enable_wol[card_idx] > 0) | |
1256 | vp->enable_wol = 1; | |
1257 | } | |
1258 | ||
125d5ce8 | 1259 | vp->mii.force_media = vp->full_duplex; |
1da177e4 LT |
1260 | vp->options = option; |
1261 | /* Read the station address from the EEPROM. */ | |
1da177e4 LT |
1262 | { |
1263 | int base; | |
1264 | ||
1265 | if (vci->drv_flags & EEPROM_8BIT) | |
1266 | base = 0x230; | |
1267 | else if (vci->drv_flags & EEPROM_OFFSET) | |
1268 | base = EEPROM_Read + 0x30; | |
1269 | else | |
1270 | base = EEPROM_Read; | |
1271 | ||
1272 | for (i = 0; i < 0x40; i++) { | |
1273 | int timer; | |
a095cfc4 | 1274 | window_write16(vp, base + i, 0, Wn0EepromCmd); |
1da177e4 LT |
1275 | /* Pause for at least 162 us. for the read to take place. */ |
1276 | for (timer = 10; timer >= 0; timer--) { | |
1277 | udelay(162); | |
a095cfc4 BH |
1278 | if ((window_read16(vp, 0, Wn0EepromCmd) & |
1279 | 0x8000) == 0) | |
1da177e4 LT |
1280 | break; |
1281 | } | |
a095cfc4 | 1282 | eeprom[i] = window_read16(vp, 0, Wn0EepromData); |
1da177e4 LT |
1283 | } |
1284 | } | |
1285 | for (i = 0; i < 0x18; i++) | |
1286 | checksum ^= eeprom[i]; | |
1287 | checksum = (checksum ^ (checksum >> 8)) & 0xff; | |
1288 | if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ | |
1289 | while (i < 0x21) | |
1290 | checksum ^= eeprom[i++]; | |
1291 | checksum = (checksum ^ (checksum >> 8)) & 0xff; | |
1292 | } | |
1293 | if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO)) | |
39738e16 | 1294 | pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum); |
1da177e4 | 1295 | for (i = 0; i < 3; i++) |
cc2d6596 | 1296 | ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]); |
bb531fc0 | 1297 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
0795af57 | 1298 | if (print_info) |
39738e16 | 1299 | pr_cont(" %pM", dev->dev_addr); |
1da177e4 LT |
1300 | /* Unfortunately an all zero eeprom passes the checksum and this |
1301 | gets found in the wild in failure cases. Crypto is hard 8) */ | |
1302 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1303 | retval = -EINVAL; | |
39738e16 | 1304 | pr_err("*** EEPROM MAC address is invalid.\n"); |
1da177e4 LT |
1305 | goto free_ring; /* With every pack */ |
1306 | } | |
1da177e4 | 1307 | for (i = 0; i < 6; i++) |
a095cfc4 | 1308 | window_write8(vp, dev->dev_addr[i], 2, i); |
1da177e4 | 1309 | |
1da177e4 | 1310 | if (print_info) |
39738e16 | 1311 | pr_cont(", IRQ %d\n", dev->irq); |
1da177e4 | 1312 | /* Tell them about an invalid IRQ. */ |
60e4ad7a | 1313 | if (dev->irq <= 0 || dev->irq >= nr_irqs) |
39738e16 | 1314 | pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n", |
1da177e4 | 1315 | dev->irq); |
1da177e4 | 1316 | |
a095cfc4 | 1317 | step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1; |
1da177e4 | 1318 | if (print_info) { |
39738e16 AB |
1319 | pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n", |
1320 | eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14], | |
1da177e4 LT |
1321 | step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9); |
1322 | } | |
1323 | ||
1324 | ||
1325 | if (pdev && vci->drv_flags & HAS_CB_FNS) { | |
1da177e4 LT |
1326 | unsigned short n; |
1327 | ||
62afe595 JL |
1328 | vp->cb_fn_base = pci_iomap(pdev, 2, 0); |
1329 | if (!vp->cb_fn_base) { | |
1da177e4 | 1330 | retval = -ENOMEM; |
62afe595 | 1331 | goto free_ring; |
1da177e4 | 1332 | } |
62afe595 | 1333 | |
1da177e4 | 1334 | if (print_info) { |
39738e16 | 1335 | pr_info("%s: CardBus functions mapped %16.16llx->%p\n", |
7c7459d1 GKH |
1336 | print_name, |
1337 | (unsigned long long)pci_resource_start(pdev, 2), | |
62afe595 | 1338 | vp->cb_fn_base); |
1da177e4 | 1339 | } |
1da177e4 | 1340 | |
a095cfc4 | 1341 | n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; |
1da177e4 LT |
1342 | if (vp->drv_flags & INVERT_LED_PWR) |
1343 | n |= 0x10; | |
1344 | if (vp->drv_flags & INVERT_MII_PWR) | |
1345 | n |= 0x4000; | |
a095cfc4 | 1346 | window_write16(vp, n, 2, Wn2_ResetOptions); |
1da177e4 | 1347 | if (vp->drv_flags & WNO_XCVR_PWR) { |
a095cfc4 | 1348 | window_write16(vp, 0x0800, 0, 0); |
1da177e4 LT |
1349 | } |
1350 | } | |
1351 | ||
1352 | /* Extract our information from the EEPROM data. */ | |
1353 | vp->info1 = eeprom[13]; | |
1354 | vp->info2 = eeprom[15]; | |
1355 | vp->capabilities = eeprom[16]; | |
1356 | ||
1357 | if (vp->info1 & 0x8000) { | |
1358 | vp->full_duplex = 1; | |
1359 | if (print_info) | |
39738e16 | 1360 | pr_info("Full duplex capable\n"); |
1da177e4 LT |
1361 | } |
1362 | ||
1363 | { | |
f71e1309 | 1364 | static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; |
1da177e4 | 1365 | unsigned int config; |
a095cfc4 | 1366 | vp->available_media = window_read16(vp, 3, Wn3_Options); |
1da177e4 LT |
1367 | if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ |
1368 | vp->available_media = 0x40; | |
a095cfc4 | 1369 | config = window_read32(vp, 3, Wn3_Config); |
1da177e4 | 1370 | if (print_info) { |
39738e16 | 1371 | pr_debug(" Internal config register is %4.4x, transceivers %#x.\n", |
a095cfc4 | 1372 | config, window_read16(vp, 3, Wn3_Options)); |
39738e16 | 1373 | pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", |
1da177e4 LT |
1374 | 8 << RAM_SIZE(config), |
1375 | RAM_WIDTH(config) ? "word" : "byte", | |
1376 | ram_split[RAM_SPLIT(config)], | |
1377 | AUTOSELECT(config) ? "autoselect/" : "", | |
1378 | XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" : | |
1379 | media_tbl[XCVR(config)].name); | |
1380 | } | |
1381 | vp->default_media = XCVR(config); | |
1382 | if (vp->default_media == XCVR_NWAY) | |
1383 | vp->has_nway = 1; | |
1384 | vp->autoselect = AUTOSELECT(config); | |
1385 | } | |
1386 | ||
1387 | if (vp->media_override != 7) { | |
39738e16 | 1388 | pr_info("%s: Media override to transceiver type %d (%s).\n", |
1da177e4 LT |
1389 | print_name, vp->media_override, |
1390 | media_tbl[vp->media_override].name); | |
1391 | dev->if_port = vp->media_override; | |
1392 | } else | |
1393 | dev->if_port = vp->default_media; | |
1394 | ||
1395 | if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) || | |
1396 | dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { | |
1397 | int phy, phy_idx = 0; | |
1da177e4 LT |
1398 | mii_preamble_required++; |
1399 | if (vp->drv_flags & EXTRA_PREAMBLE) | |
1400 | mii_preamble_required++; | |
344e0f62 | 1401 | mdio_sync(vp, 32); |
106427e6 | 1402 | mdio_read(dev, 24, MII_BMSR); |
1da177e4 LT |
1403 | for (phy = 0; phy < 32 && phy_idx < 1; phy++) { |
1404 | int mii_status, phyx; | |
1405 | ||
1406 | /* | |
1407 | * For the 3c905CX we look at index 24 first, because it bogusly | |
1408 | * reports an external PHY at all indices | |
1409 | */ | |
1410 | if (phy == 0) | |
1411 | phyx = 24; | |
1412 | else if (phy <= 24) | |
1413 | phyx = phy - 1; | |
1414 | else | |
1415 | phyx = phy; | |
106427e6 | 1416 | mii_status = mdio_read(dev, phyx, MII_BMSR); |
1da177e4 LT |
1417 | if (mii_status && mii_status != 0xffff) { |
1418 | vp->phys[phy_idx++] = phyx; | |
1419 | if (print_info) { | |
39738e16 AB |
1420 | pr_info(" MII transceiver found at address %d, status %4x.\n", |
1421 | phyx, mii_status); | |
1da177e4 LT |
1422 | } |
1423 | if ((mii_status & 0x0040) == 0) | |
1424 | mii_preamble_required++; | |
1425 | } | |
1426 | } | |
1427 | mii_preamble_required--; | |
1428 | if (phy_idx == 0) { | |
39738e16 | 1429 | pr_warning(" ***WARNING*** No MII transceivers found!\n"); |
1da177e4 LT |
1430 | vp->phys[0] = 24; |
1431 | } else { | |
106427e6 | 1432 | vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE); |
1da177e4 LT |
1433 | if (vp->full_duplex) { |
1434 | /* Only advertise the FD media types. */ | |
1435 | vp->advertising &= ~0x02A0; | |
1436 | mdio_write(dev, vp->phys[0], 4, vp->advertising); | |
1437 | } | |
1438 | } | |
1439 | vp->mii.phy_id = vp->phys[0]; | |
1440 | } | |
1441 | ||
1442 | if (vp->capabilities & CapBusMaster) { | |
1443 | vp->full_bus_master_tx = 1; | |
1444 | if (print_info) { | |
39738e16 | 1445 | pr_info(" Enabling bus-master transmits and %s receives.\n", |
1da177e4 LT |
1446 | (vp->info2 & 1) ? "early" : "whole-frame" ); |
1447 | } | |
1448 | vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2; | |
1449 | vp->bus_master = 0; /* AKPM: vortex only */ | |
1450 | } | |
1451 | ||
1452 | /* The 3c59x-specific entries in the device structure. */ | |
1da177e4 | 1453 | if (vp->full_bus_master_tx) { |
48b47a5e | 1454 | dev->netdev_ops = &boomrang_netdev_ops; |
1da177e4 | 1455 | /* Actually, it still should work with iommu. */ |
32fb5f06 JL |
1456 | if (card_idx < MAX_UNITS && |
1457 | ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) || | |
1458 | hw_checksums[card_idx] == 1)) { | |
d311b0d3 | 1459 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
1da177e4 | 1460 | } |
48b47a5e SH |
1461 | } else |
1462 | dev->netdev_ops = &vortex_netdev_ops; | |
1da177e4 LT |
1463 | |
1464 | if (print_info) { | |
39738e16 | 1465 | pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n", |
1da177e4 LT |
1466 | print_name, |
1467 | (dev->features & NETIF_F_SG) ? "en":"dis", | |
1468 | (dev->features & NETIF_F_IP_CSUM) ? "en":"dis"); | |
1469 | } | |
1470 | ||
1da177e4 | 1471 | dev->ethtool_ops = &vortex_ethtool_ops; |
1da177e4 | 1472 | dev->watchdog_timeo = (watchdog * HZ) / 1000; |
48b47a5e | 1473 | |
1da177e4 LT |
1474 | if (pdev) { |
1475 | vp->pm_state_valid = 1; | |
1476 | pci_save_state(VORTEX_PCI(vp)); | |
1477 | acpi_set_WOL(dev); | |
1478 | } | |
1479 | retval = register_netdev(dev); | |
1480 | if (retval == 0) | |
1481 | return 0; | |
1482 | ||
1483 | free_ring: | |
1484 | pci_free_consistent(pdev, | |
1485 | sizeof(struct boom_rx_desc) * RX_RING_SIZE | |
1486 | + sizeof(struct boom_tx_desc) * TX_RING_SIZE, | |
1487 | vp->rx_ring, | |
1488 | vp->rx_ring_dma); | |
1489 | free_region: | |
1490 | if (vp->must_free_region) | |
62afe595 | 1491 | release_region(dev->base_addr, vci->io_size); |
1da177e4 | 1492 | free_netdev(dev); |
39738e16 | 1493 | pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval); |
1da177e4 LT |
1494 | out: |
1495 | return retval; | |
1496 | } | |
1497 | ||
1498 | static void | |
1499 | issue_and_wait(struct net_device *dev, int cmd) | |
1500 | { | |
62afe595 JL |
1501 | struct vortex_private *vp = netdev_priv(dev); |
1502 | void __iomem *ioaddr = vp->ioaddr; | |
1da177e4 LT |
1503 | int i; |
1504 | ||
62afe595 | 1505 | iowrite16(cmd, ioaddr + EL3_CMD); |
1da177e4 | 1506 | for (i = 0; i < 2000; i++) { |
62afe595 | 1507 | if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) |
1da177e4 LT |
1508 | return; |
1509 | } | |
1510 | ||
1511 | /* OK, that didn't work. Do it the slow way. One second */ | |
1512 | for (i = 0; i < 100000; i++) { | |
62afe595 | 1513 | if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) { |
1da177e4 | 1514 | if (vortex_debug > 1) |
39738e16 | 1515 | pr_info("%s: command 0x%04x took %d usecs\n", |
1da177e4 LT |
1516 | dev->name, cmd, i * 10); |
1517 | return; | |
1518 | } | |
1519 | udelay(10); | |
1520 | } | |
39738e16 | 1521 | pr_err("%s: command 0x%04x did not complete! Status=0x%x\n", |
62afe595 | 1522 | dev->name, cmd, ioread16(ioaddr + EL3_STATUS)); |
1da177e4 LT |
1523 | } |
1524 | ||
125d5ce8 SK |
1525 | static void |
1526 | vortex_set_duplex(struct net_device *dev) | |
1527 | { | |
1528 | struct vortex_private *vp = netdev_priv(dev); | |
125d5ce8 | 1529 | |
39738e16 | 1530 | pr_info("%s: setting %s-duplex.\n", |
125d5ce8 SK |
1531 | dev->name, (vp->full_duplex) ? "full" : "half"); |
1532 | ||
125d5ce8 | 1533 | /* Set the full-duplex bit. */ |
a095cfc4 BH |
1534 | window_write16(vp, |
1535 | ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | | |
1536 | (vp->large_frames ? 0x40 : 0) | | |
1537 | ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? | |
1538 | 0x100 : 0), | |
1539 | 3, Wn3_MAC_Ctrl); | |
125d5ce8 SK |
1540 | } |
1541 | ||
1542 | static void vortex_check_media(struct net_device *dev, unsigned int init) | |
1543 | { | |
1544 | struct vortex_private *vp = netdev_priv(dev); | |
1545 | unsigned int ok_to_print = 0; | |
1546 | ||
1547 | if (vortex_debug > 3) | |
1548 | ok_to_print = 1; | |
1549 | ||
1550 | if (mii_check_media(&vp->mii, ok_to_print, init)) { | |
1551 | vp->full_duplex = vp->mii.full_duplex; | |
1552 | vortex_set_duplex(dev); | |
1553 | } else if (init) { | |
1554 | vortex_set_duplex(dev); | |
1555 | } | |
1556 | } | |
1557 | ||
c8303d10 | 1558 | static int |
1da177e4 LT |
1559 | vortex_up(struct net_device *dev) |
1560 | { | |
1da177e4 | 1561 | struct vortex_private *vp = netdev_priv(dev); |
62afe595 | 1562 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 | 1563 | unsigned int config; |
0280f9f9 | 1564 | int i, mii_reg1, mii_reg5, err = 0; |
1da177e4 LT |
1565 | |
1566 | if (VORTEX_PCI(vp)) { | |
1567 | pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */ | |
3c8fad18 DR |
1568 | if (vp->pm_state_valid) |
1569 | pci_restore_state(VORTEX_PCI(vp)); | |
c8303d10 MH |
1570 | err = pci_enable_device(VORTEX_PCI(vp)); |
1571 | if (err) { | |
39738e16 | 1572 | pr_warning("%s: Could not enable device\n", |
c8303d10 MH |
1573 | dev->name); |
1574 | goto err_out; | |
1575 | } | |
1da177e4 LT |
1576 | } |
1577 | ||
1578 | /* Before initializing select the active media port. */ | |
a095cfc4 | 1579 | config = window_read32(vp, 3, Wn3_Config); |
1da177e4 LT |
1580 | |
1581 | if (vp->media_override != 7) { | |
39738e16 | 1582 | pr_info("%s: Media override to transceiver %d (%s).\n", |
1da177e4 LT |
1583 | dev->name, vp->media_override, |
1584 | media_tbl[vp->media_override].name); | |
1585 | dev->if_port = vp->media_override; | |
1586 | } else if (vp->autoselect) { | |
1587 | if (vp->has_nway) { | |
1588 | if (vortex_debug > 1) | |
39738e16 | 1589 | pr_info("%s: using NWAY device table, not %d\n", |
1da177e4 LT |
1590 | dev->name, dev->if_port); |
1591 | dev->if_port = XCVR_NWAY; | |
1592 | } else { | |
1593 | /* Find first available media type, starting with 100baseTx. */ | |
1594 | dev->if_port = XCVR_100baseTx; | |
1595 | while (! (vp->available_media & media_tbl[dev->if_port].mask)) | |
1596 | dev->if_port = media_tbl[dev->if_port].next; | |
1597 | if (vortex_debug > 1) | |
39738e16 | 1598 | pr_info("%s: first available media type: %s\n", |
1da177e4 LT |
1599 | dev->name, media_tbl[dev->if_port].name); |
1600 | } | |
1601 | } else { | |
1602 | dev->if_port = vp->default_media; | |
1603 | if (vortex_debug > 1) | |
39738e16 | 1604 | pr_info("%s: using default media %s\n", |
1da177e4 LT |
1605 | dev->name, media_tbl[dev->if_port].name); |
1606 | } | |
1607 | ||
1608 | init_timer(&vp->timer); | |
1609 | vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait); | |
1610 | vp->timer.data = (unsigned long)dev; | |
1611 | vp->timer.function = vortex_timer; /* timer handler */ | |
1612 | add_timer(&vp->timer); | |
1613 | ||
1614 | init_timer(&vp->rx_oom_timer); | |
1615 | vp->rx_oom_timer.data = (unsigned long)dev; | |
1616 | vp->rx_oom_timer.function = rx_oom_timer; | |
1617 | ||
1618 | if (vortex_debug > 1) | |
39738e16 | 1619 | pr_debug("%s: Initial media type %s.\n", |
1da177e4 LT |
1620 | dev->name, media_tbl[dev->if_port].name); |
1621 | ||
125d5ce8 | 1622 | vp->full_duplex = vp->mii.force_media; |
1da177e4 LT |
1623 | config = BFINS(config, dev->if_port, 20, 4); |
1624 | if (vortex_debug > 6) | |
39738e16 | 1625 | pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config); |
a095cfc4 | 1626 | window_write32(vp, config, 3, Wn3_Config); |
1da177e4 LT |
1627 | |
1628 | if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { | |
09ce3512 SK |
1629 | mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR); |
1630 | mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA); | |
1631 | vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0); | |
373492d0 | 1632 | vp->mii.full_duplex = vp->full_duplex; |
09ce3512 | 1633 | |
125d5ce8 | 1634 | vortex_check_media(dev, 1); |
1da177e4 | 1635 | } |
125d5ce8 SK |
1636 | else |
1637 | vortex_set_duplex(dev); | |
1da177e4 | 1638 | |
09ce3512 SK |
1639 | issue_and_wait(dev, TxReset); |
1640 | /* | |
1641 | * Don't reset the PHY - that upsets autonegotiation during DHCP operations. | |
1642 | */ | |
1643 | issue_and_wait(dev, RxReset|0x04); | |
1644 | ||
1da177e4 | 1645 | |
62afe595 | 1646 | iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD); |
1da177e4 LT |
1647 | |
1648 | if (vortex_debug > 1) { | |
39738e16 | 1649 | pr_debug("%s: vortex_up() irq %d media status %4.4x.\n", |
a095cfc4 | 1650 | dev->name, dev->irq, window_read16(vp, 4, Wn4_Media)); |
1da177e4 LT |
1651 | } |
1652 | ||
1653 | /* Set the station address and mask in window 2 each time opened. */ | |
1da177e4 | 1654 | for (i = 0; i < 6; i++) |
a095cfc4 | 1655 | window_write8(vp, dev->dev_addr[i], 2, i); |
1da177e4 | 1656 | for (; i < 12; i+=2) |
a095cfc4 | 1657 | window_write16(vp, 0, 2, i); |
1da177e4 LT |
1658 | |
1659 | if (vp->cb_fn_base) { | |
a095cfc4 | 1660 | unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; |
1da177e4 LT |
1661 | if (vp->drv_flags & INVERT_LED_PWR) |
1662 | n |= 0x10; | |
1663 | if (vp->drv_flags & INVERT_MII_PWR) | |
1664 | n |= 0x4000; | |
a095cfc4 | 1665 | window_write16(vp, n, 2, Wn2_ResetOptions); |
1da177e4 LT |
1666 | } |
1667 | ||
1668 | if (dev->if_port == XCVR_10base2) | |
1669 | /* Start the thinnet transceiver. We should really wait 50ms...*/ | |
62afe595 | 1670 | iowrite16(StartCoax, ioaddr + EL3_CMD); |
1da177e4 | 1671 | if (dev->if_port != XCVR_NWAY) { |
a095cfc4 BH |
1672 | window_write16(vp, |
1673 | (window_read16(vp, 4, Wn4_Media) & | |
1674 | ~(Media_10TP|Media_SQE)) | | |
1675 | media_tbl[dev->if_port].media_bits, | |
1676 | 4, Wn4_Media); | |
1da177e4 LT |
1677 | } |
1678 | ||
1679 | /* Switch to the stats window, and clear all stats by reading. */ | |
62afe595 | 1680 | iowrite16(StatsDisable, ioaddr + EL3_CMD); |
1da177e4 | 1681 | for (i = 0; i < 10; i++) |
a095cfc4 BH |
1682 | window_read8(vp, 6, i); |
1683 | window_read16(vp, 6, 10); | |
1684 | window_read16(vp, 6, 12); | |
1da177e4 | 1685 | /* New: On the Vortex we must also clear the BadSSD counter. */ |
a095cfc4 | 1686 | window_read8(vp, 4, 12); |
1da177e4 | 1687 | /* ..and on the Boomerang we enable the extra statistics bits. */ |
a095cfc4 | 1688 | window_write16(vp, 0x0040, 4, Wn4_NetDiag); |
1da177e4 LT |
1689 | |
1690 | if (vp->full_bus_master_rx) { /* Boomerang bus master. */ | |
1691 | vp->cur_rx = vp->dirty_rx = 0; | |
1692 | /* Initialize the RxEarly register as recommended. */ | |
62afe595 JL |
1693 | iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD); |
1694 | iowrite32(0x0020, ioaddr + PktStatus); | |
1695 | iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr); | |
1da177e4 LT |
1696 | } |
1697 | if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ | |
1698 | vp->cur_tx = vp->dirty_tx = 0; | |
1699 | if (vp->drv_flags & IS_BOOMERANG) | |
62afe595 | 1700 | iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */ |
1da177e4 LT |
1701 | /* Clear the Rx, Tx rings. */ |
1702 | for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */ | |
1703 | vp->rx_ring[i].status = 0; | |
1704 | for (i = 0; i < TX_RING_SIZE; i++) | |
1705 | vp->tx_skbuff[i] = NULL; | |
62afe595 | 1706 | iowrite32(0, ioaddr + DownListPtr); |
1da177e4 LT |
1707 | } |
1708 | /* Set receiver mode: presumably accept b-case and phys addr only. */ | |
1709 | set_rx_mode(dev); | |
1710 | /* enable 802.1q tagged frames */ | |
1711 | set_8021q_mode(dev, 1); | |
62afe595 | 1712 | iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ |
1da177e4 | 1713 | |
62afe595 JL |
1714 | iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */ |
1715 | iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */ | |
1da177e4 LT |
1716 | /* Allow status bits to be seen. */ |
1717 | vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete| | |
1718 | (vp->full_bus_master_tx ? DownComplete : TxAvailable) | | |
1719 | (vp->full_bus_master_rx ? UpComplete : RxComplete) | | |
1720 | (vp->bus_master ? DMADone : 0); | |
1721 | vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | | |
1722 | (vp->full_bus_master_rx ? 0 : RxComplete) | | |
1723 | StatsFull | HostError | TxComplete | IntReq | |
1724 | | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; | |
62afe595 | 1725 | iowrite16(vp->status_enable, ioaddr + EL3_CMD); |
1da177e4 | 1726 | /* Ack all pending events, and set active indicator mask. */ |
62afe595 | 1727 | iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, |
1da177e4 | 1728 | ioaddr + EL3_CMD); |
62afe595 | 1729 | iowrite16(vp->intr_enable, ioaddr + EL3_CMD); |
1da177e4 | 1730 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
62afe595 | 1731 | iowrite32(0x8000, vp->cb_fn_base + 4); |
1da177e4 | 1732 | netif_start_queue (dev); |
c8303d10 MH |
1733 | err_out: |
1734 | return err; | |
1da177e4 LT |
1735 | } |
1736 | ||
1737 | static int | |
1738 | vortex_open(struct net_device *dev) | |
1739 | { | |
1740 | struct vortex_private *vp = netdev_priv(dev); | |
1741 | int i; | |
1742 | int retval; | |
1743 | ||
1744 | /* Use the now-standard shared IRQ implementation. */ | |
1745 | if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ? | |
c061b18d | 1746 | boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) { |
39738e16 | 1747 | pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq); |
c8303d10 | 1748 | goto err; |
1da177e4 LT |
1749 | } |
1750 | ||
1751 | if (vp->full_bus_master_rx) { /* Boomerang bus master. */ | |
1752 | if (vortex_debug > 2) | |
39738e16 | 1753 | pr_debug("%s: Filling in the Rx ring.\n", dev->name); |
1da177e4 LT |
1754 | for (i = 0; i < RX_RING_SIZE; i++) { |
1755 | struct sk_buff *skb; | |
1756 | vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1)); | |
1757 | vp->rx_ring[i].status = 0; /* Clear complete bit. */ | |
1758 | vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); | |
9a5d3414 SH |
1759 | |
1760 | skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN, | |
1761 | GFP_KERNEL); | |
1da177e4 LT |
1762 | vp->rx_skbuff[i] = skb; |
1763 | if (skb == NULL) | |
1764 | break; /* Bad news! */ | |
9a5d3414 SH |
1765 | |
1766 | skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */ | |
689be439 | 1767 | vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); |
1da177e4 LT |
1768 | } |
1769 | if (i != RX_RING_SIZE) { | |
1770 | int j; | |
39738e16 | 1771 | pr_emerg("%s: no memory for rx ring\n", dev->name); |
1da177e4 LT |
1772 | for (j = 0; j < i; j++) { |
1773 | if (vp->rx_skbuff[j]) { | |
1774 | dev_kfree_skb(vp->rx_skbuff[j]); | |
1775 | vp->rx_skbuff[j] = NULL; | |
1776 | } | |
1777 | } | |
1778 | retval = -ENOMEM; | |
c8303d10 | 1779 | goto err_free_irq; |
1da177e4 LT |
1780 | } |
1781 | /* Wrap the ring. */ | |
1782 | vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma); | |
1783 | } | |
1784 | ||
c8303d10 MH |
1785 | retval = vortex_up(dev); |
1786 | if (!retval) | |
1787 | goto out; | |
1da177e4 | 1788 | |
c8303d10 | 1789 | err_free_irq: |
1da177e4 | 1790 | free_irq(dev->irq, dev); |
c8303d10 | 1791 | err: |
1da177e4 | 1792 | if (vortex_debug > 1) |
39738e16 | 1793 | pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval); |
c8303d10 | 1794 | out: |
1da177e4 LT |
1795 | return retval; |
1796 | } | |
1797 | ||
1798 | static void | |
1799 | vortex_timer(unsigned long data) | |
1800 | { | |
1801 | struct net_device *dev = (struct net_device *)data; | |
1802 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 1803 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
1804 | int next_tick = 60*HZ; |
1805 | int ok = 0; | |
a095cfc4 | 1806 | int media_status; |
1da177e4 LT |
1807 | |
1808 | if (vortex_debug > 2) { | |
39738e16 | 1809 | pr_debug("%s: Media selection timer tick happened, %s.\n", |
1da177e4 | 1810 | dev->name, media_tbl[dev->if_port].name); |
39738e16 | 1811 | pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo); |
1da177e4 LT |
1812 | } |
1813 | ||
a095cfc4 | 1814 | media_status = window_read16(vp, 4, Wn4_Media); |
1da177e4 LT |
1815 | switch (dev->if_port) { |
1816 | case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: | |
1817 | if (media_status & Media_LnkBeat) { | |
1818 | netif_carrier_on(dev); | |
1819 | ok = 1; | |
1820 | if (vortex_debug > 1) | |
39738e16 | 1821 | pr_debug("%s: Media %s has link beat, %x.\n", |
1da177e4 LT |
1822 | dev->name, media_tbl[dev->if_port].name, media_status); |
1823 | } else { | |
1824 | netif_carrier_off(dev); | |
1825 | if (vortex_debug > 1) { | |
39738e16 | 1826 | pr_debug("%s: Media %s has no link beat, %x.\n", |
1da177e4 LT |
1827 | dev->name, media_tbl[dev->if_port].name, media_status); |
1828 | } | |
1829 | } | |
1830 | break; | |
1831 | case XCVR_MII: case XCVR_NWAY: | |
1832 | { | |
1da177e4 | 1833 | ok = 1; |
125d5ce8 | 1834 | vortex_check_media(dev, 0); |
1da177e4 LT |
1835 | } |
1836 | break; | |
1837 | default: /* Other media types handled by Tx timeouts. */ | |
1838 | if (vortex_debug > 1) | |
39738e16 | 1839 | pr_debug("%s: Media %s has no indication, %x.\n", |
1da177e4 LT |
1840 | dev->name, media_tbl[dev->if_port].name, media_status); |
1841 | ok = 1; | |
1842 | } | |
b4ff6450 SK |
1843 | |
1844 | if (!netif_carrier_ok(dev)) | |
1845 | next_tick = 5*HZ; | |
1846 | ||
e94d10eb SK |
1847 | if (vp->medialock) |
1848 | goto leave_media_alone; | |
1849 | ||
a880c4cd | 1850 | if (!ok) { |
1da177e4 LT |
1851 | unsigned int config; |
1852 | ||
de847272 BH |
1853 | spin_lock_irq(&vp->lock); |
1854 | ||
1da177e4 LT |
1855 | do { |
1856 | dev->if_port = media_tbl[dev->if_port].next; | |
1857 | } while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); | |
1858 | if (dev->if_port == XCVR_Default) { /* Go back to default. */ | |
1859 | dev->if_port = vp->default_media; | |
1860 | if (vortex_debug > 1) | |
39738e16 | 1861 | pr_debug("%s: Media selection failing, using default %s port.\n", |
1da177e4 LT |
1862 | dev->name, media_tbl[dev->if_port].name); |
1863 | } else { | |
1864 | if (vortex_debug > 1) | |
39738e16 | 1865 | pr_debug("%s: Media selection failed, now trying %s port.\n", |
1da177e4 LT |
1866 | dev->name, media_tbl[dev->if_port].name); |
1867 | next_tick = media_tbl[dev->if_port].wait; | |
1868 | } | |
a095cfc4 BH |
1869 | window_write16(vp, |
1870 | (media_status & ~(Media_10TP|Media_SQE)) | | |
1871 | media_tbl[dev->if_port].media_bits, | |
1872 | 4, Wn4_Media); | |
1da177e4 | 1873 | |
a095cfc4 | 1874 | config = window_read32(vp, 3, Wn3_Config); |
1da177e4 | 1875 | config = BFINS(config, dev->if_port, 20, 4); |
a095cfc4 | 1876 | window_write32(vp, config, 3, Wn3_Config); |
1da177e4 | 1877 | |
62afe595 | 1878 | iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, |
1da177e4 LT |
1879 | ioaddr + EL3_CMD); |
1880 | if (vortex_debug > 1) | |
39738e16 | 1881 | pr_debug("wrote 0x%08x to Wn3_Config\n", config); |
1da177e4 | 1882 | /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */ |
de847272 BH |
1883 | |
1884 | spin_unlock_irq(&vp->lock); | |
1da177e4 | 1885 | } |
1da177e4 LT |
1886 | |
1887 | leave_media_alone: | |
1888 | if (vortex_debug > 2) | |
39738e16 | 1889 | pr_debug("%s: Media selection timer finished, %s.\n", |
1da177e4 LT |
1890 | dev->name, media_tbl[dev->if_port].name); |
1891 | ||
1892 | mod_timer(&vp->timer, RUN_AT(next_tick)); | |
1893 | if (vp->deferred) | |
62afe595 | 1894 | iowrite16(FakeIntr, ioaddr + EL3_CMD); |
1da177e4 LT |
1895 | } |
1896 | ||
1897 | static void vortex_tx_timeout(struct net_device *dev) | |
1898 | { | |
1899 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 1900 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 | 1901 | |
39738e16 | 1902 | pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n", |
62afe595 JL |
1903 | dev->name, ioread8(ioaddr + TxStatus), |
1904 | ioread16(ioaddr + EL3_STATUS)); | |
39738e16 | 1905 | pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n", |
a095cfc4 BH |
1906 | window_read16(vp, 4, Wn4_NetDiag), |
1907 | window_read16(vp, 4, Wn4_Media), | |
62afe595 | 1908 | ioread32(ioaddr + PktStatus), |
a095cfc4 | 1909 | window_read16(vp, 4, Wn4_FIFODiag)); |
1da177e4 | 1910 | /* Slight code bloat to be user friendly. */ |
62afe595 | 1911 | if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88) |
39738e16 | 1912 | pr_err("%s: Transmitter encountered 16 collisions --" |
1da177e4 | 1913 | " network cable problem?\n", dev->name); |
62afe595 | 1914 | if (ioread16(ioaddr + EL3_STATUS) & IntLatch) { |
39738e16 | 1915 | pr_err("%s: Interrupt posted but not delivered --" |
1da177e4 LT |
1916 | " IRQ blocked by another device?\n", dev->name); |
1917 | /* Bad idea here.. but we might as well handle a few events. */ | |
1918 | { | |
1919 | /* | |
1920 | * Block interrupts because vortex_interrupt does a bare spin_lock() | |
1921 | */ | |
1922 | unsigned long flags; | |
1923 | local_irq_save(flags); | |
1924 | if (vp->full_bus_master_tx) | |
7d12e780 | 1925 | boomerang_interrupt(dev->irq, dev); |
1da177e4 | 1926 | else |
7d12e780 | 1927 | vortex_interrupt(dev->irq, dev); |
1da177e4 LT |
1928 | local_irq_restore(flags); |
1929 | } | |
1930 | } | |
1931 | ||
1932 | if (vortex_debug > 0) | |
1933 | dump_tx_ring(dev); | |
1934 | ||
1935 | issue_and_wait(dev, TxReset); | |
1936 | ||
1daad055 | 1937 | dev->stats.tx_errors++; |
1da177e4 | 1938 | if (vp->full_bus_master_tx) { |
39738e16 | 1939 | pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name); |
62afe595 JL |
1940 | if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0) |
1941 | iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc), | |
1da177e4 LT |
1942 | ioaddr + DownListPtr); |
1943 | if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) | |
1944 | netif_wake_queue (dev); | |
1945 | if (vp->drv_flags & IS_BOOMERANG) | |
62afe595 JL |
1946 | iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); |
1947 | iowrite16(DownUnstall, ioaddr + EL3_CMD); | |
1da177e4 | 1948 | } else { |
1daad055 | 1949 | dev->stats.tx_dropped++; |
1da177e4 LT |
1950 | netif_wake_queue(dev); |
1951 | } | |
6aa20a22 | 1952 | |
1da177e4 | 1953 | /* Issue Tx Enable */ |
62afe595 | 1954 | iowrite16(TxEnable, ioaddr + EL3_CMD); |
1ae5dc34 | 1955 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
1956 | } |
1957 | ||
1958 | /* | |
1959 | * Handle uncommon interrupt sources. This is a separate routine to minimize | |
1960 | * the cache impact. | |
1961 | */ | |
1962 | static void | |
1963 | vortex_error(struct net_device *dev, int status) | |
1964 | { | |
1965 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 1966 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
1967 | int do_tx_reset = 0, reset_mask = 0; |
1968 | unsigned char tx_status = 0; | |
1969 | ||
1970 | if (vortex_debug > 2) { | |
39738e16 | 1971 | pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status); |
1da177e4 LT |
1972 | } |
1973 | ||
1974 | if (status & TxComplete) { /* Really "TxError" for us. */ | |
62afe595 | 1975 | tx_status = ioread8(ioaddr + TxStatus); |
1da177e4 | 1976 | /* Presumably a tx-timeout. We must merely re-enable. */ |
8e95a202 JP |
1977 | if (vortex_debug > 2 || |
1978 | (tx_status != 0x88 && vortex_debug > 0)) { | |
39738e16 | 1979 | pr_err("%s: Transmit error, Tx status register %2.2x.\n", |
1da177e4 LT |
1980 | dev->name, tx_status); |
1981 | if (tx_status == 0x82) { | |
39738e16 | 1982 | pr_err("Probably a duplex mismatch. See " |
1da177e4 LT |
1983 | "Documentation/networking/vortex.txt\n"); |
1984 | } | |
1985 | dump_tx_ring(dev); | |
1986 | } | |
1daad055 PZ |
1987 | if (tx_status & 0x14) dev->stats.tx_fifo_errors++; |
1988 | if (tx_status & 0x38) dev->stats.tx_aborted_errors++; | |
0000754c | 1989 | if (tx_status & 0x08) vp->xstats.tx_max_collisions++; |
62afe595 | 1990 | iowrite8(0, ioaddr + TxStatus); |
1da177e4 LT |
1991 | if (tx_status & 0x30) { /* txJabber or txUnderrun */ |
1992 | do_tx_reset = 1; | |
0000754c AM |
1993 | } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */ |
1994 | do_tx_reset = 1; | |
1995 | reset_mask = 0x0108; /* Reset interface logic, but not download logic */ | |
1996 | } else { /* Merely re-enable the transmitter. */ | |
62afe595 | 1997 | iowrite16(TxEnable, ioaddr + EL3_CMD); |
1da177e4 LT |
1998 | } |
1999 | } | |
2000 | ||
89b12fab | 2001 | if (status & RxEarly) /* Rx early is unused. */ |
62afe595 | 2002 | iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD); |
89b12fab | 2003 | |
1da177e4 LT |
2004 | if (status & StatsFull) { /* Empty statistics. */ |
2005 | static int DoneDidThat; | |
2006 | if (vortex_debug > 4) | |
39738e16 | 2007 | pr_debug("%s: Updating stats.\n", dev->name); |
1da177e4 LT |
2008 | update_stats(ioaddr, dev); |
2009 | /* HACK: Disable statistics as an interrupt source. */ | |
2010 | /* This occurs when we have the wrong media type! */ | |
2011 | if (DoneDidThat == 0 && | |
62afe595 | 2012 | ioread16(ioaddr + EL3_STATUS) & StatsFull) { |
39738e16 | 2013 | pr_warning("%s: Updating statistics failed, disabling " |
1da177e4 | 2014 | "stats as an interrupt source.\n", dev->name); |
a095cfc4 BH |
2015 | iowrite16(SetIntrEnb | |
2016 | (window_read16(vp, 5, 10) & ~StatsFull), | |
2017 | ioaddr + EL3_CMD); | |
1da177e4 | 2018 | vp->intr_enable &= ~StatsFull; |
1da177e4 LT |
2019 | DoneDidThat++; |
2020 | } | |
2021 | } | |
2022 | if (status & IntReq) { /* Restore all interrupt sources. */ | |
62afe595 JL |
2023 | iowrite16(vp->status_enable, ioaddr + EL3_CMD); |
2024 | iowrite16(vp->intr_enable, ioaddr + EL3_CMD); | |
1da177e4 LT |
2025 | } |
2026 | if (status & HostError) { | |
2027 | u16 fifo_diag; | |
a095cfc4 | 2028 | fifo_diag = window_read16(vp, 4, Wn4_FIFODiag); |
39738e16 | 2029 | pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n", |
1da177e4 LT |
2030 | dev->name, fifo_diag); |
2031 | /* Adapter failure requires Tx/Rx reset and reinit. */ | |
2032 | if (vp->full_bus_master_tx) { | |
62afe595 | 2033 | int bus_status = ioread32(ioaddr + PktStatus); |
1da177e4 LT |
2034 | /* 0x80000000 PCI master abort. */ |
2035 | /* 0x40000000 PCI target abort. */ | |
2036 | if (vortex_debug) | |
39738e16 | 2037 | pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status); |
1da177e4 LT |
2038 | |
2039 | /* In this case, blow the card away */ | |
2040 | /* Must not enter D3 or we can't legally issue the reset! */ | |
2041 | vortex_down(dev, 0); | |
2042 | issue_and_wait(dev, TotalReset | 0xff); | |
2043 | vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */ | |
2044 | } else if (fifo_diag & 0x0400) | |
2045 | do_tx_reset = 1; | |
2046 | if (fifo_diag & 0x3000) { | |
2047 | /* Reset Rx fifo and upload logic */ | |
2048 | issue_and_wait(dev, RxReset|0x07); | |
2049 | /* Set the Rx filter to the current state. */ | |
2050 | set_rx_mode(dev); | |
2051 | /* enable 802.1q VLAN tagged frames */ | |
2052 | set_8021q_mode(dev, 1); | |
62afe595 JL |
2053 | iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ |
2054 | iowrite16(AckIntr | HostError, ioaddr + EL3_CMD); | |
1da177e4 LT |
2055 | } |
2056 | } | |
2057 | ||
2058 | if (do_tx_reset) { | |
2059 | issue_and_wait(dev, TxReset|reset_mask); | |
62afe595 | 2060 | iowrite16(TxEnable, ioaddr + EL3_CMD); |
1da177e4 LT |
2061 | if (!vp->full_bus_master_tx) |
2062 | netif_wake_queue(dev); | |
2063 | } | |
2064 | } | |
2065 | ||
27a1de95 | 2066 | static netdev_tx_t |
1da177e4 LT |
2067 | vortex_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2068 | { | |
2069 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2070 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2071 | |
2072 | /* Put out the doubleword header... */ | |
62afe595 | 2073 | iowrite32(skb->len, ioaddr + TX_FIFO); |
1da177e4 LT |
2074 | if (vp->bus_master) { |
2075 | /* Set the bus-master controller to transfer the packet. */ | |
2076 | int len = (skb->len + 3) & ~3; | |
a095cfc4 BH |
2077 | vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, |
2078 | PCI_DMA_TODEVICE); | |
de847272 | 2079 | spin_lock_irq(&vp->window_lock); |
a095cfc4 BH |
2080 | window_set(vp, 7); |
2081 | iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr); | |
62afe595 | 2082 | iowrite16(len, ioaddr + Wn7_MasterLen); |
de847272 | 2083 | spin_unlock_irq(&vp->window_lock); |
1da177e4 | 2084 | vp->tx_skb = skb; |
62afe595 | 2085 | iowrite16(StartDMADown, ioaddr + EL3_CMD); |
1da177e4 LT |
2086 | /* netif_wake_queue() will be called at the DMADone interrupt. */ |
2087 | } else { | |
2088 | /* ... and the packet rounded to a doubleword. */ | |
62afe595 | 2089 | iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); |
1da177e4 | 2090 | dev_kfree_skb (skb); |
62afe595 | 2091 | if (ioread16(ioaddr + TxFree) > 1536) { |
1da177e4 LT |
2092 | netif_start_queue (dev); /* AKPM: redundant? */ |
2093 | } else { | |
2094 | /* Interrupt us when the FIFO has room for max-sized packet. */ | |
2095 | netif_stop_queue(dev); | |
62afe595 | 2096 | iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
1da177e4 LT |
2097 | } |
2098 | } | |
2099 | ||
1da177e4 LT |
2100 | |
2101 | /* Clear the Tx status stack. */ | |
2102 | { | |
2103 | int tx_status; | |
2104 | int i = 32; | |
2105 | ||
62afe595 | 2106 | while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) { |
1da177e4 LT |
2107 | if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ |
2108 | if (vortex_debug > 2) | |
39738e16 | 2109 | pr_debug("%s: Tx error, status %2.2x.\n", |
1da177e4 | 2110 | dev->name, tx_status); |
1daad055 PZ |
2111 | if (tx_status & 0x04) dev->stats.tx_fifo_errors++; |
2112 | if (tx_status & 0x38) dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
2113 | if (tx_status & 0x30) { |
2114 | issue_and_wait(dev, TxReset); | |
2115 | } | |
62afe595 | 2116 | iowrite16(TxEnable, ioaddr + EL3_CMD); |
1da177e4 | 2117 | } |
62afe595 | 2118 | iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */ |
1da177e4 LT |
2119 | } |
2120 | } | |
6ed10654 | 2121 | return NETDEV_TX_OK; |
1da177e4 LT |
2122 | } |
2123 | ||
27a1de95 | 2124 | static netdev_tx_t |
1da177e4 LT |
2125 | boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2126 | { | |
2127 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2128 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2129 | /* Calculate the next Tx descriptor entry. */ |
2130 | int entry = vp->cur_tx % TX_RING_SIZE; | |
2131 | struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]; | |
2132 | unsigned long flags; | |
2133 | ||
2134 | if (vortex_debug > 6) { | |
39738e16 AB |
2135 | pr_debug("boomerang_start_xmit()\n"); |
2136 | pr_debug("%s: Trying to send a packet, Tx index %d.\n", | |
0f667ff5 | 2137 | dev->name, vp->cur_tx); |
1da177e4 LT |
2138 | } |
2139 | ||
aa25ab7d NH |
2140 | /* |
2141 | * We can't allow a recursion from our interrupt handler back into the | |
2142 | * tx routine, as they take the same spin lock, and that causes | |
2143 | * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in | |
2144 | * a bit | |
2145 | */ | |
2146 | if (vp->handling_irq) | |
2147 | return NETDEV_TX_BUSY; | |
2148 | ||
1da177e4 LT |
2149 | if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) { |
2150 | if (vortex_debug > 0) | |
39738e16 | 2151 | pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n", |
1da177e4 LT |
2152 | dev->name); |
2153 | netif_stop_queue(dev); | |
5b548140 | 2154 | return NETDEV_TX_BUSY; |
1da177e4 LT |
2155 | } |
2156 | ||
2157 | vp->tx_skbuff[entry] = skb; | |
2158 | ||
2159 | vp->tx_ring[entry].next = 0; | |
2160 | #if DO_ZEROCOPY | |
84fa7933 | 2161 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1da177e4 LT |
2162 | vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); |
2163 | else | |
2164 | vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum); | |
2165 | ||
2166 | if (!skb_shinfo(skb)->nr_frags) { | |
2167 | vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, | |
2168 | skb->len, PCI_DMA_TODEVICE)); | |
2169 | vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG); | |
2170 | } else { | |
2171 | int i; | |
2172 | ||
2173 | vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, | |
e743d313 ED |
2174 | skb_headlen(skb), PCI_DMA_TODEVICE)); |
2175 | vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb)); | |
1da177e4 LT |
2176 | |
2177 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2178 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2179 | ||
2180 | vp->tx_ring[entry].frag[i+1].addr = | |
7b63e3a8 IC |
2181 | cpu_to_le32(pci_map_single( |
2182 | VORTEX_PCI(vp), | |
2183 | (void *)skb_frag_address(frag), | |
9e903e08 | 2184 | skb_frag_size(frag), PCI_DMA_TODEVICE)); |
1da177e4 LT |
2185 | |
2186 | if (i == skb_shinfo(skb)->nr_frags-1) | |
9e903e08 | 2187 | vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG); |
1da177e4 | 2188 | else |
9e903e08 | 2189 | vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)); |
1da177e4 LT |
2190 | } |
2191 | } | |
2192 | #else | |
2193 | vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE)); | |
2194 | vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG); | |
2195 | vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); | |
2196 | #endif | |
2197 | ||
2198 | spin_lock_irqsave(&vp->lock, flags); | |
2199 | /* Wait for the stall to complete. */ | |
2200 | issue_and_wait(dev, DownStall); | |
2201 | prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc)); | |
62afe595 JL |
2202 | if (ioread32(ioaddr + DownListPtr) == 0) { |
2203 | iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr); | |
1da177e4 LT |
2204 | vp->queued_packet++; |
2205 | } | |
2206 | ||
2207 | vp->cur_tx++; | |
2208 | if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) { | |
2209 | netif_stop_queue (dev); | |
2210 | } else { /* Clear previous interrupt enable. */ | |
2211 | #if defined(tx_interrupt_mitigation) | |
2212 | /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef | |
2213 | * were selected, this would corrupt DN_COMPLETE. No? | |
2214 | */ | |
2215 | prev_entry->status &= cpu_to_le32(~TxIntrUploaded); | |
2216 | #endif | |
2217 | } | |
62afe595 | 2218 | iowrite16(DownUnstall, ioaddr + EL3_CMD); |
1da177e4 | 2219 | spin_unlock_irqrestore(&vp->lock, flags); |
6ed10654 | 2220 | return NETDEV_TX_OK; |
1da177e4 LT |
2221 | } |
2222 | ||
2223 | /* The interrupt handler does all of the Rx thread work and cleans up | |
2224 | after the Tx thread. */ | |
2225 | ||
2226 | /* | |
2227 | * This is the ISR for the vortex series chips. | |
2228 | * full_bus_master_tx == 0 && full_bus_master_rx == 0 | |
2229 | */ | |
2230 | ||
2231 | static irqreturn_t | |
7d12e780 | 2232 | vortex_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2233 | { |
2234 | struct net_device *dev = dev_id; | |
2235 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2236 | void __iomem *ioaddr; |
1da177e4 LT |
2237 | int status; |
2238 | int work_done = max_interrupt_work; | |
2239 | int handled = 0; | |
2240 | ||
62afe595 | 2241 | ioaddr = vp->ioaddr; |
1da177e4 LT |
2242 | spin_lock(&vp->lock); |
2243 | ||
62afe595 | 2244 | status = ioread16(ioaddr + EL3_STATUS); |
1da177e4 LT |
2245 | |
2246 | if (vortex_debug > 6) | |
39738e16 | 2247 | pr_debug("vortex_interrupt(). status=0x%4x\n", status); |
1da177e4 LT |
2248 | |
2249 | if ((status & IntLatch) == 0) | |
2250 | goto handler_exit; /* No interrupt: shared IRQs cause this */ | |
2251 | handled = 1; | |
2252 | ||
2253 | if (status & IntReq) { | |
2254 | status |= vp->deferred; | |
2255 | vp->deferred = 0; | |
2256 | } | |
2257 | ||
2258 | if (status == 0xffff) /* h/w no longer present (hotplug)? */ | |
2259 | goto handler_exit; | |
2260 | ||
2261 | if (vortex_debug > 4) | |
39738e16 | 2262 | pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n", |
62afe595 | 2263 | dev->name, status, ioread8(ioaddr + Timer)); |
1da177e4 | 2264 | |
de847272 | 2265 | spin_lock(&vp->window_lock); |
a095cfc4 BH |
2266 | window_set(vp, 7); |
2267 | ||
1da177e4 LT |
2268 | do { |
2269 | if (vortex_debug > 5) | |
39738e16 | 2270 | pr_debug("%s: In interrupt loop, status %4.4x.\n", |
1da177e4 LT |
2271 | dev->name, status); |
2272 | if (status & RxComplete) | |
2273 | vortex_rx(dev); | |
2274 | ||
2275 | if (status & TxAvailable) { | |
2276 | if (vortex_debug > 5) | |
39738e16 | 2277 | pr_debug(" TX room bit was handled.\n"); |
1da177e4 | 2278 | /* There's room in the FIFO for a full-sized packet. */ |
62afe595 | 2279 | iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD); |
1da177e4 LT |
2280 | netif_wake_queue (dev); |
2281 | } | |
2282 | ||
2283 | if (status & DMADone) { | |
62afe595 JL |
2284 | if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) { |
2285 | iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ | |
1da177e4 LT |
2286 | pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE); |
2287 | dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */ | |
62afe595 | 2288 | if (ioread16(ioaddr + TxFree) > 1536) { |
1da177e4 LT |
2289 | /* |
2290 | * AKPM: FIXME: I don't think we need this. If the queue was stopped due to | |
2291 | * insufficient FIFO room, the TxAvailable test will succeed and call | |
2292 | * netif_wake_queue() | |
2293 | */ | |
2294 | netif_wake_queue(dev); | |
2295 | } else { /* Interrupt when FIFO has room for max-sized packet. */ | |
62afe595 | 2296 | iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
1da177e4 LT |
2297 | netif_stop_queue(dev); |
2298 | } | |
2299 | } | |
2300 | } | |
2301 | /* Check for all uncommon interrupts at once. */ | |
2302 | if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { | |
2303 | if (status == 0xffff) | |
2304 | break; | |
89b12fab BH |
2305 | if (status & RxEarly) |
2306 | vortex_rx(dev); | |
2307 | spin_unlock(&vp->window_lock); | |
1da177e4 | 2308 | vortex_error(dev, status); |
89b12fab BH |
2309 | spin_lock(&vp->window_lock); |
2310 | window_set(vp, 7); | |
1da177e4 LT |
2311 | } |
2312 | ||
2313 | if (--work_done < 0) { | |
39738e16 AB |
2314 | pr_warning("%s: Too much work in interrupt, status %4.4x.\n", |
2315 | dev->name, status); | |
1da177e4 LT |
2316 | /* Disable all pending interrupts. */ |
2317 | do { | |
2318 | vp->deferred |= status; | |
62afe595 | 2319 | iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable), |
1da177e4 | 2320 | ioaddr + EL3_CMD); |
62afe595 JL |
2321 | iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); |
2322 | } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch); | |
1da177e4 LT |
2323 | /* The timer will reenable interrupts. */ |
2324 | mod_timer(&vp->timer, jiffies + 1*HZ); | |
2325 | break; | |
2326 | } | |
2327 | /* Acknowledge the IRQ. */ | |
62afe595 JL |
2328 | iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
2329 | } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete)); | |
1da177e4 | 2330 | |
de847272 BH |
2331 | spin_unlock(&vp->window_lock); |
2332 | ||
1da177e4 | 2333 | if (vortex_debug > 4) |
39738e16 | 2334 | pr_debug("%s: exiting interrupt, status %4.4x.\n", |
1da177e4 LT |
2335 | dev->name, status); |
2336 | handler_exit: | |
2337 | spin_unlock(&vp->lock); | |
2338 | return IRQ_RETVAL(handled); | |
2339 | } | |
2340 | ||
2341 | /* | |
2342 | * This is the ISR for the boomerang series chips. | |
2343 | * full_bus_master_tx == 1 && full_bus_master_rx == 1 | |
2344 | */ | |
2345 | ||
2346 | static irqreturn_t | |
7d12e780 | 2347 | boomerang_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2348 | { |
2349 | struct net_device *dev = dev_id; | |
2350 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2351 | void __iomem *ioaddr; |
1da177e4 LT |
2352 | int status; |
2353 | int work_done = max_interrupt_work; | |
2354 | ||
62afe595 | 2355 | ioaddr = vp->ioaddr; |
1da177e4 | 2356 | |
aa25ab7d | 2357 | |
1da177e4 LT |
2358 | /* |
2359 | * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout | |
2360 | * and boomerang_start_xmit | |
2361 | */ | |
2362 | spin_lock(&vp->lock); | |
aa25ab7d | 2363 | vp->handling_irq = 1; |
1da177e4 | 2364 | |
62afe595 | 2365 | status = ioread16(ioaddr + EL3_STATUS); |
1da177e4 LT |
2366 | |
2367 | if (vortex_debug > 6) | |
39738e16 | 2368 | pr_debug("boomerang_interrupt. status=0x%4x\n", status); |
1da177e4 LT |
2369 | |
2370 | if ((status & IntLatch) == 0) | |
2371 | goto handler_exit; /* No interrupt: shared IRQs can cause this */ | |
2372 | ||
2373 | if (status == 0xffff) { /* h/w no longer present (hotplug)? */ | |
2374 | if (vortex_debug > 1) | |
39738e16 | 2375 | pr_debug("boomerang_interrupt(1): status = 0xffff\n"); |
1da177e4 LT |
2376 | goto handler_exit; |
2377 | } | |
2378 | ||
2379 | if (status & IntReq) { | |
2380 | status |= vp->deferred; | |
2381 | vp->deferred = 0; | |
2382 | } | |
2383 | ||
2384 | if (vortex_debug > 4) | |
39738e16 | 2385 | pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n", |
62afe595 | 2386 | dev->name, status, ioread8(ioaddr + Timer)); |
1da177e4 LT |
2387 | do { |
2388 | if (vortex_debug > 5) | |
39738e16 | 2389 | pr_debug("%s: In interrupt loop, status %4.4x.\n", |
1da177e4 LT |
2390 | dev->name, status); |
2391 | if (status & UpComplete) { | |
62afe595 | 2392 | iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD); |
1da177e4 | 2393 | if (vortex_debug > 5) |
39738e16 | 2394 | pr_debug("boomerang_interrupt->boomerang_rx\n"); |
1da177e4 LT |
2395 | boomerang_rx(dev); |
2396 | } | |
2397 | ||
2398 | if (status & DownComplete) { | |
2399 | unsigned int dirty_tx = vp->dirty_tx; | |
2400 | ||
62afe595 | 2401 | iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD); |
1da177e4 LT |
2402 | while (vp->cur_tx - dirty_tx > 0) { |
2403 | int entry = dirty_tx % TX_RING_SIZE; | |
2404 | #if 1 /* AKPM: the latter is faster, but cyclone-only */ | |
62afe595 | 2405 | if (ioread32(ioaddr + DownListPtr) == |
1da177e4 LT |
2406 | vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc)) |
2407 | break; /* It still hasn't been processed. */ | |
2408 | #else | |
2409 | if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0) | |
2410 | break; /* It still hasn't been processed. */ | |
2411 | #endif | |
6aa20a22 | 2412 | |
1da177e4 LT |
2413 | if (vp->tx_skbuff[entry]) { |
2414 | struct sk_buff *skb = vp->tx_skbuff[entry]; | |
6aa20a22 | 2415 | #if DO_ZEROCOPY |
1da177e4 LT |
2416 | int i; |
2417 | for (i=0; i<=skb_shinfo(skb)->nr_frags; i++) | |
2418 | pci_unmap_single(VORTEX_PCI(vp), | |
2419 | le32_to_cpu(vp->tx_ring[entry].frag[i].addr), | |
2420 | le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF, | |
2421 | PCI_DMA_TODEVICE); | |
2422 | #else | |
2423 | pci_unmap_single(VORTEX_PCI(vp), | |
2424 | le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE); | |
2425 | #endif | |
2426 | dev_kfree_skb_irq(skb); | |
2427 | vp->tx_skbuff[entry] = NULL; | |
2428 | } else { | |
39738e16 | 2429 | pr_debug("boomerang_interrupt: no skb!\n"); |
1da177e4 | 2430 | } |
1daad055 | 2431 | /* dev->stats.tx_packets++; Counted below. */ |
1da177e4 LT |
2432 | dirty_tx++; |
2433 | } | |
2434 | vp->dirty_tx = dirty_tx; | |
2435 | if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) { | |
2436 | if (vortex_debug > 6) | |
39738e16 | 2437 | pr_debug("boomerang_interrupt: wake queue\n"); |
1da177e4 LT |
2438 | netif_wake_queue (dev); |
2439 | } | |
2440 | } | |
2441 | ||
2442 | /* Check for all uncommon interrupts at once. */ | |
2443 | if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) | |
2444 | vortex_error(dev, status); | |
2445 | ||
2446 | if (--work_done < 0) { | |
39738e16 AB |
2447 | pr_warning("%s: Too much work in interrupt, status %4.4x.\n", |
2448 | dev->name, status); | |
1da177e4 LT |
2449 | /* Disable all pending interrupts. */ |
2450 | do { | |
2451 | vp->deferred |= status; | |
62afe595 | 2452 | iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable), |
1da177e4 | 2453 | ioaddr + EL3_CMD); |
62afe595 JL |
2454 | iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); |
2455 | } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch); | |
1da177e4 LT |
2456 | /* The timer will reenable interrupts. */ |
2457 | mod_timer(&vp->timer, jiffies + 1*HZ); | |
2458 | break; | |
2459 | } | |
2460 | /* Acknowledge the IRQ. */ | |
62afe595 | 2461 | iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
1da177e4 | 2462 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
62afe595 | 2463 | iowrite32(0x8000, vp->cb_fn_base + 4); |
1da177e4 | 2464 | |
62afe595 | 2465 | } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch); |
1da177e4 LT |
2466 | |
2467 | if (vortex_debug > 4) | |
39738e16 | 2468 | pr_debug("%s: exiting interrupt, status %4.4x.\n", |
1da177e4 LT |
2469 | dev->name, status); |
2470 | handler_exit: | |
aa25ab7d | 2471 | vp->handling_irq = 0; |
1da177e4 LT |
2472 | spin_unlock(&vp->lock); |
2473 | return IRQ_HANDLED; | |
2474 | } | |
2475 | ||
2476 | static int vortex_rx(struct net_device *dev) | |
2477 | { | |
2478 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2479 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2480 | int i; |
2481 | short rx_status; | |
2482 | ||
2483 | if (vortex_debug > 5) | |
39738e16 | 2484 | pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n", |
62afe595 JL |
2485 | ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus)); |
2486 | while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) { | |
1da177e4 | 2487 | if (rx_status & 0x4000) { /* Error, update stats. */ |
62afe595 | 2488 | unsigned char rx_error = ioread8(ioaddr + RxErrors); |
1da177e4 | 2489 | if (vortex_debug > 2) |
39738e16 | 2490 | pr_debug(" Rx error: status %2.2x.\n", rx_error); |
1daad055 PZ |
2491 | dev->stats.rx_errors++; |
2492 | if (rx_error & 0x01) dev->stats.rx_over_errors++; | |
2493 | if (rx_error & 0x02) dev->stats.rx_length_errors++; | |
2494 | if (rx_error & 0x04) dev->stats.rx_frame_errors++; | |
2495 | if (rx_error & 0x08) dev->stats.rx_crc_errors++; | |
2496 | if (rx_error & 0x10) dev->stats.rx_length_errors++; | |
1da177e4 LT |
2497 | } else { |
2498 | /* The packet length: up to 4.5K!. */ | |
2499 | int pkt_len = rx_status & 0x1fff; | |
2500 | struct sk_buff *skb; | |
2501 | ||
2502 | skb = dev_alloc_skb(pkt_len + 5); | |
2503 | if (vortex_debug > 4) | |
39738e16 | 2504 | pr_debug("Receiving packet size %d status %4.4x.\n", |
1da177e4 LT |
2505 | pkt_len, rx_status); |
2506 | if (skb != NULL) { | |
1da177e4 LT |
2507 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
2508 | /* 'skb_put()' points to the start of sk_buff data area. */ | |
2509 | if (vp->bus_master && | |
62afe595 | 2510 | ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) { |
1da177e4 LT |
2511 | dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len), |
2512 | pkt_len, PCI_DMA_FROMDEVICE); | |
62afe595 JL |
2513 | iowrite32(dma, ioaddr + Wn7_MasterAddr); |
2514 | iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); | |
2515 | iowrite16(StartDMAUp, ioaddr + EL3_CMD); | |
2516 | while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000) | |
1da177e4 LT |
2517 | ; |
2518 | pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE); | |
2519 | } else { | |
62afe595 JL |
2520 | ioread32_rep(ioaddr + RX_FIFO, |
2521 | skb_put(skb, pkt_len), | |
2522 | (pkt_len + 3) >> 2); | |
1da177e4 | 2523 | } |
62afe595 | 2524 | iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */ |
1da177e4 LT |
2525 | skb->protocol = eth_type_trans(skb, dev); |
2526 | netif_rx(skb); | |
1daad055 | 2527 | dev->stats.rx_packets++; |
1da177e4 LT |
2528 | /* Wait a limited time to go to next packet. */ |
2529 | for (i = 200; i >= 0; i--) | |
62afe595 | 2530 | if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) |
1da177e4 LT |
2531 | break; |
2532 | continue; | |
2533 | } else if (vortex_debug > 0) | |
39738e16 AB |
2534 | pr_notice("%s: No memory to allocate a sk_buff of size %d.\n", |
2535 | dev->name, pkt_len); | |
1daad055 | 2536 | dev->stats.rx_dropped++; |
1da177e4 | 2537 | } |
1da177e4 LT |
2538 | issue_and_wait(dev, RxDiscard); |
2539 | } | |
2540 | ||
2541 | return 0; | |
2542 | } | |
2543 | ||
2544 | static int | |
2545 | boomerang_rx(struct net_device *dev) | |
2546 | { | |
2547 | struct vortex_private *vp = netdev_priv(dev); | |
2548 | int entry = vp->cur_rx % RX_RING_SIZE; | |
62afe595 | 2549 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2550 | int rx_status; |
2551 | int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx; | |
2552 | ||
2553 | if (vortex_debug > 5) | |
39738e16 | 2554 | pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS)); |
1da177e4 LT |
2555 | |
2556 | while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){ | |
2557 | if (--rx_work_limit < 0) | |
2558 | break; | |
2559 | if (rx_status & RxDError) { /* Error, update stats. */ | |
2560 | unsigned char rx_error = rx_status >> 16; | |
2561 | if (vortex_debug > 2) | |
39738e16 | 2562 | pr_debug(" Rx error: status %2.2x.\n", rx_error); |
1daad055 PZ |
2563 | dev->stats.rx_errors++; |
2564 | if (rx_error & 0x01) dev->stats.rx_over_errors++; | |
2565 | if (rx_error & 0x02) dev->stats.rx_length_errors++; | |
2566 | if (rx_error & 0x04) dev->stats.rx_frame_errors++; | |
2567 | if (rx_error & 0x08) dev->stats.rx_crc_errors++; | |
2568 | if (rx_error & 0x10) dev->stats.rx_length_errors++; | |
1da177e4 LT |
2569 | } else { |
2570 | /* The packet length: up to 4.5K!. */ | |
2571 | int pkt_len = rx_status & 0x1fff; | |
2572 | struct sk_buff *skb; | |
2573 | dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr); | |
2574 | ||
2575 | if (vortex_debug > 4) | |
39738e16 | 2576 | pr_debug("Receiving packet size %d status %4.4x.\n", |
1da177e4 LT |
2577 | pkt_len, rx_status); |
2578 | ||
2579 | /* Check if the packet is long enough to just accept without | |
2580 | copying to a properly sized skbuff. */ | |
cc2d6596 | 2581 | if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { |
1da177e4 LT |
2582 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
2583 | pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
2584 | /* 'skb_put()' points to the start of sk_buff data area. */ | |
2585 | memcpy(skb_put(skb, pkt_len), | |
689be439 | 2586 | vp->rx_skbuff[entry]->data, |
1da177e4 LT |
2587 | pkt_len); |
2588 | pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
2589 | vp->rx_copy++; | |
2590 | } else { | |
2591 | /* Pass up the skbuff already on the Rx ring. */ | |
2592 | skb = vp->rx_skbuff[entry]; | |
2593 | vp->rx_skbuff[entry] = NULL; | |
2594 | skb_put(skb, pkt_len); | |
2595 | pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
2596 | vp->rx_nocopy++; | |
2597 | } | |
2598 | skb->protocol = eth_type_trans(skb, dev); | |
2599 | { /* Use hardware checksum info. */ | |
2600 | int csum_bits = rx_status & 0xee000000; | |
2601 | if (csum_bits && | |
2602 | (csum_bits == (IPChksumValid | TCPChksumValid) || | |
2603 | csum_bits == (IPChksumValid | UDPChksumValid))) { | |
2604 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
2605 | vp->rx_csumhits++; | |
2606 | } | |
2607 | } | |
2608 | netif_rx(skb); | |
1daad055 | 2609 | dev->stats.rx_packets++; |
1da177e4 LT |
2610 | } |
2611 | entry = (++vp->cur_rx) % RX_RING_SIZE; | |
2612 | } | |
2613 | /* Refill the Rx ring buffers. */ | |
2614 | for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) { | |
2615 | struct sk_buff *skb; | |
2616 | entry = vp->dirty_rx % RX_RING_SIZE; | |
2617 | if (vp->rx_skbuff[entry] == NULL) { | |
89d71a66 | 2618 | skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ); |
1da177e4 LT |
2619 | if (skb == NULL) { |
2620 | static unsigned long last_jif; | |
ff5688ae | 2621 | if (time_after(jiffies, last_jif + 10 * HZ)) { |
39738e16 | 2622 | pr_warning("%s: memory shortage\n", dev->name); |
1da177e4 LT |
2623 | last_jif = jiffies; |
2624 | } | |
2625 | if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) | |
2626 | mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1)); | |
2627 | break; /* Bad news! */ | |
2628 | } | |
9a5d3414 | 2629 | |
689be439 | 2630 | vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); |
1da177e4 LT |
2631 | vp->rx_skbuff[entry] = skb; |
2632 | } | |
2633 | vp->rx_ring[entry].status = 0; /* Clear complete bit. */ | |
62afe595 | 2634 | iowrite16(UpUnstall, ioaddr + EL3_CMD); |
1da177e4 LT |
2635 | } |
2636 | return 0; | |
2637 | } | |
2638 | ||
2639 | /* | |
2640 | * If we've hit a total OOM refilling the Rx ring we poll once a second | |
2641 | * for some memory. Otherwise there is no way to restart the rx process. | |
2642 | */ | |
2643 | static void | |
2644 | rx_oom_timer(unsigned long arg) | |
2645 | { | |
2646 | struct net_device *dev = (struct net_device *)arg; | |
2647 | struct vortex_private *vp = netdev_priv(dev); | |
2648 | ||
2649 | spin_lock_irq(&vp->lock); | |
2650 | if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */ | |
2651 | boomerang_rx(dev); | |
2652 | if (vortex_debug > 1) { | |
39738e16 | 2653 | pr_debug("%s: rx_oom_timer %s\n", dev->name, |
1da177e4 LT |
2654 | ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying"); |
2655 | } | |
2656 | spin_unlock_irq(&vp->lock); | |
2657 | } | |
2658 | ||
2659 | static void | |
2660 | vortex_down(struct net_device *dev, int final_down) | |
2661 | { | |
2662 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2663 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2664 | |
2665 | netif_stop_queue (dev); | |
2666 | ||
2667 | del_timer_sync(&vp->rx_oom_timer); | |
2668 | del_timer_sync(&vp->timer); | |
2669 | ||
1daad055 | 2670 | /* Turn off statistics ASAP. We update dev->stats below. */ |
62afe595 | 2671 | iowrite16(StatsDisable, ioaddr + EL3_CMD); |
1da177e4 LT |
2672 | |
2673 | /* Disable the receiver and transmitter. */ | |
62afe595 JL |
2674 | iowrite16(RxDisable, ioaddr + EL3_CMD); |
2675 | iowrite16(TxDisable, ioaddr + EL3_CMD); | |
1da177e4 LT |
2676 | |
2677 | /* Disable receiving 802.1q tagged frames */ | |
2678 | set_8021q_mode(dev, 0); | |
2679 | ||
2680 | if (dev->if_port == XCVR_10base2) | |
2681 | /* Turn off thinnet power. Green! */ | |
62afe595 | 2682 | iowrite16(StopCoax, ioaddr + EL3_CMD); |
1da177e4 | 2683 | |
62afe595 | 2684 | iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); |
1da177e4 LT |
2685 | |
2686 | update_stats(ioaddr, dev); | |
2687 | if (vp->full_bus_master_rx) | |
62afe595 | 2688 | iowrite32(0, ioaddr + UpListPtr); |
1da177e4 | 2689 | if (vp->full_bus_master_tx) |
62afe595 | 2690 | iowrite32(0, ioaddr + DownListPtr); |
1da177e4 LT |
2691 | |
2692 | if (final_down && VORTEX_PCI(vp)) { | |
3c8fad18 | 2693 | vp->pm_state_valid = 1; |
1da177e4 LT |
2694 | pci_save_state(VORTEX_PCI(vp)); |
2695 | acpi_set_WOL(dev); | |
2696 | } | |
2697 | } | |
2698 | ||
2699 | static int | |
2700 | vortex_close(struct net_device *dev) | |
2701 | { | |
2702 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2703 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2704 | int i; |
2705 | ||
2706 | if (netif_device_present(dev)) | |
2707 | vortex_down(dev, 1); | |
2708 | ||
2709 | if (vortex_debug > 1) { | |
39738e16 | 2710 | pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n", |
62afe595 | 2711 | dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus)); |
39738e16 | 2712 | pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d" |
1da177e4 LT |
2713 | " tx_queued %d Rx pre-checksummed %d.\n", |
2714 | dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits); | |
2715 | } | |
2716 | ||
2717 | #if DO_ZEROCOPY | |
32fb5f06 JL |
2718 | if (vp->rx_csumhits && |
2719 | (vp->drv_flags & HAS_HWCKSM) == 0 && | |
2720 | (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) { | |
39738e16 | 2721 | pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name); |
1da177e4 LT |
2722 | } |
2723 | #endif | |
6aa20a22 | 2724 | |
1da177e4 LT |
2725 | free_irq(dev->irq, dev); |
2726 | ||
2727 | if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */ | |
2728 | for (i = 0; i < RX_RING_SIZE; i++) | |
2729 | if (vp->rx_skbuff[i]) { | |
2730 | pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr), | |
2731 | PKT_BUF_SZ, PCI_DMA_FROMDEVICE); | |
2732 | dev_kfree_skb(vp->rx_skbuff[i]); | |
2733 | vp->rx_skbuff[i] = NULL; | |
2734 | } | |
2735 | } | |
2736 | if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */ | |
2737 | for (i = 0; i < TX_RING_SIZE; i++) { | |
2738 | if (vp->tx_skbuff[i]) { | |
2739 | struct sk_buff *skb = vp->tx_skbuff[i]; | |
2740 | #if DO_ZEROCOPY | |
2741 | int k; | |
2742 | ||
2743 | for (k=0; k<=skb_shinfo(skb)->nr_frags; k++) | |
2744 | pci_unmap_single(VORTEX_PCI(vp), | |
2745 | le32_to_cpu(vp->tx_ring[i].frag[k].addr), | |
2746 | le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF, | |
2747 | PCI_DMA_TODEVICE); | |
2748 | #else | |
2749 | pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE); | |
2750 | #endif | |
2751 | dev_kfree_skb(skb); | |
2752 | vp->tx_skbuff[i] = NULL; | |
2753 | } | |
2754 | } | |
2755 | } | |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | ||
2760 | static void | |
2761 | dump_tx_ring(struct net_device *dev) | |
2762 | { | |
2763 | if (vortex_debug > 0) { | |
2764 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2765 | void __iomem *ioaddr = vp->ioaddr; |
6aa20a22 | 2766 | |
1da177e4 LT |
2767 | if (vp->full_bus_master_tx) { |
2768 | int i; | |
62afe595 | 2769 | int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */ |
1da177e4 | 2770 | |
39738e16 | 2771 | pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n", |
1da177e4 LT |
2772 | vp->full_bus_master_tx, |
2773 | vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE, | |
2774 | vp->cur_tx, vp->cur_tx % TX_RING_SIZE); | |
39738e16 | 2775 | pr_err(" Transmit list %8.8x vs. %p.\n", |
62afe595 | 2776 | ioread32(ioaddr + DownListPtr), |
1da177e4 LT |
2777 | &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); |
2778 | issue_and_wait(dev, DownStall); | |
2779 | for (i = 0; i < TX_RING_SIZE; i++) { | |
0cb13536 JD |
2780 | unsigned int length; |
2781 | ||
1da177e4 | 2782 | #if DO_ZEROCOPY |
0cb13536 | 2783 | length = le32_to_cpu(vp->tx_ring[i].frag[0].length); |
1da177e4 | 2784 | #else |
0cb13536 | 2785 | length = le32_to_cpu(vp->tx_ring[i].length); |
1da177e4 | 2786 | #endif |
0cb13536 JD |
2787 | pr_err(" %d: @%p length %8.8x status %8.8x\n", |
2788 | i, &vp->tx_ring[i], length, | |
1da177e4 LT |
2789 | le32_to_cpu(vp->tx_ring[i].status)); |
2790 | } | |
2791 | if (!stalled) | |
62afe595 | 2792 | iowrite16(DownUnstall, ioaddr + EL3_CMD); |
1da177e4 LT |
2793 | } |
2794 | } | |
2795 | } | |
2796 | ||
2797 | static struct net_device_stats *vortex_get_stats(struct net_device *dev) | |
2798 | { | |
2799 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2800 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2801 | unsigned long flags; |
2802 | ||
2803 | if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */ | |
2804 | spin_lock_irqsave (&vp->lock, flags); | |
62afe595 | 2805 | update_stats(ioaddr, dev); |
1da177e4 LT |
2806 | spin_unlock_irqrestore (&vp->lock, flags); |
2807 | } | |
1daad055 | 2808 | return &dev->stats; |
1da177e4 LT |
2809 | } |
2810 | ||
2811 | /* Update statistics. | |
2812 | Unlike with the EL3 we need not worry about interrupts changing | |
2813 | the window setting from underneath us, but we must still guard | |
2814 | against a race condition with a StatsUpdate interrupt updating the | |
2815 | table. This is done by checking that the ASM (!) code generated uses | |
2816 | atomic updates with '+='. | |
2817 | */ | |
62afe595 | 2818 | static void update_stats(void __iomem *ioaddr, struct net_device *dev) |
1da177e4 LT |
2819 | { |
2820 | struct vortex_private *vp = netdev_priv(dev); | |
1da177e4 | 2821 | |
1da177e4 LT |
2822 | /* Unlike the 3c5x9 we need not turn off stats updates while reading. */ |
2823 | /* Switch to the stats window, and read everything. */ | |
a095cfc4 BH |
2824 | dev->stats.tx_carrier_errors += window_read8(vp, 6, 0); |
2825 | dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1); | |
2826 | dev->stats.tx_window_errors += window_read8(vp, 6, 4); | |
2827 | dev->stats.rx_fifo_errors += window_read8(vp, 6, 5); | |
2828 | dev->stats.tx_packets += window_read8(vp, 6, 6); | |
2829 | dev->stats.tx_packets += (window_read8(vp, 6, 9) & | |
2830 | 0x30) << 4; | |
2831 | /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */ | |
1da177e4 LT |
2832 | /* Don't bother with register 9, an extension of registers 6&7. |
2833 | If we do use the 6&7 values the atomic update assumption above | |
2834 | is invalid. */ | |
a095cfc4 BH |
2835 | dev->stats.rx_bytes += window_read16(vp, 6, 10); |
2836 | dev->stats.tx_bytes += window_read16(vp, 6, 12); | |
1da177e4 | 2837 | /* Extra stats for get_ethtool_stats() */ |
a095cfc4 BH |
2838 | vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2); |
2839 | vp->xstats.tx_single_collisions += window_read8(vp, 6, 3); | |
2840 | vp->xstats.tx_deferred += window_read8(vp, 6, 8); | |
2841 | vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12); | |
1da177e4 | 2842 | |
1daad055 | 2843 | dev->stats.collisions = vp->xstats.tx_multiple_collisions |
8d1d0340 SK |
2844 | + vp->xstats.tx_single_collisions |
2845 | + vp->xstats.tx_max_collisions; | |
2846 | ||
1da177e4 | 2847 | { |
a095cfc4 | 2848 | u8 up = window_read8(vp, 4, 13); |
1daad055 PZ |
2849 | dev->stats.rx_bytes += (up & 0x0f) << 16; |
2850 | dev->stats.tx_bytes += (up & 0xf0) << 12; | |
1da177e4 | 2851 | } |
1da177e4 LT |
2852 | } |
2853 | ||
2854 | static int vortex_nway_reset(struct net_device *dev) | |
2855 | { | |
2856 | struct vortex_private *vp = netdev_priv(dev); | |
1da177e4 | 2857 | |
de847272 | 2858 | return mii_nway_restart(&vp->mii); |
1da177e4 LT |
2859 | } |
2860 | ||
1da177e4 LT |
2861 | static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
2862 | { | |
2863 | struct vortex_private *vp = netdev_priv(dev); | |
1da177e4 | 2864 | |
de847272 | 2865 | return mii_ethtool_gset(&vp->mii, cmd); |
1da177e4 LT |
2866 | } |
2867 | ||
2868 | static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2869 | { | |
2870 | struct vortex_private *vp = netdev_priv(dev); | |
1da177e4 | 2871 | |
de847272 | 2872 | return mii_ethtool_sset(&vp->mii, cmd); |
1da177e4 LT |
2873 | } |
2874 | ||
2875 | static u32 vortex_get_msglevel(struct net_device *dev) | |
2876 | { | |
2877 | return vortex_debug; | |
2878 | } | |
2879 | ||
2880 | static void vortex_set_msglevel(struct net_device *dev, u32 dbg) | |
2881 | { | |
2882 | vortex_debug = dbg; | |
2883 | } | |
2884 | ||
b9f2c044 | 2885 | static int vortex_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 2886 | { |
b9f2c044 JG |
2887 | switch (sset) { |
2888 | case ETH_SS_STATS: | |
2889 | return VORTEX_NUM_STATS; | |
2890 | default: | |
2891 | return -EOPNOTSUPP; | |
2892 | } | |
1da177e4 LT |
2893 | } |
2894 | ||
2895 | static void vortex_get_ethtool_stats(struct net_device *dev, | |
2896 | struct ethtool_stats *stats, u64 *data) | |
2897 | { | |
2898 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 2899 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 LT |
2900 | unsigned long flags; |
2901 | ||
2902 | spin_lock_irqsave(&vp->lock, flags); | |
62afe595 | 2903 | update_stats(ioaddr, dev); |
1da177e4 LT |
2904 | spin_unlock_irqrestore(&vp->lock, flags); |
2905 | ||
2906 | data[0] = vp->xstats.tx_deferred; | |
8d1d0340 SK |
2907 | data[1] = vp->xstats.tx_max_collisions; |
2908 | data[2] = vp->xstats.tx_multiple_collisions; | |
2909 | data[3] = vp->xstats.tx_single_collisions; | |
2910 | data[4] = vp->xstats.rx_bad_ssd; | |
1da177e4 LT |
2911 | } |
2912 | ||
2913 | ||
2914 | static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
2915 | { | |
2916 | switch (stringset) { | |
2917 | case ETH_SS_STATS: | |
2918 | memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
2919 | break; | |
2920 | default: | |
2921 | WARN_ON(1); | |
2922 | break; | |
2923 | } | |
2924 | } | |
2925 | ||
2926 | static void vortex_get_drvinfo(struct net_device *dev, | |
2927 | struct ethtool_drvinfo *info) | |
2928 | { | |
2929 | struct vortex_private *vp = netdev_priv(dev); | |
2930 | ||
68aad78c | 2931 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
1da177e4 | 2932 | if (VORTEX_PCI(vp)) { |
68aad78c RJ |
2933 | strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)), |
2934 | sizeof(info->bus_info)); | |
1da177e4 LT |
2935 | } else { |
2936 | if (VORTEX_EISA(vp)) | |
68aad78c RJ |
2937 | strlcpy(info->bus_info, dev_name(vp->gendev), |
2938 | sizeof(info->bus_info)); | |
1da177e4 | 2939 | else |
68aad78c RJ |
2940 | snprintf(info->bus_info, sizeof(info->bus_info), |
2941 | "EISA 0x%lx %d", dev->base_addr, dev->irq); | |
1da177e4 LT |
2942 | } |
2943 | } | |
2944 | ||
690a1f20 AS |
2945 | static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
2946 | { | |
2947 | struct vortex_private *vp = netdev_priv(dev); | |
2948 | ||
3fd6c88e JB |
2949 | if (!VORTEX_PCI(vp)) |
2950 | return; | |
2951 | ||
690a1f20 AS |
2952 | wol->supported = WAKE_MAGIC; |
2953 | ||
2954 | wol->wolopts = 0; | |
2955 | if (vp->enable_wol) | |
2956 | wol->wolopts |= WAKE_MAGIC; | |
690a1f20 AS |
2957 | } |
2958 | ||
2959 | static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2960 | { | |
2961 | struct vortex_private *vp = netdev_priv(dev); | |
3fd6c88e JB |
2962 | |
2963 | if (!VORTEX_PCI(vp)) | |
2964 | return -EOPNOTSUPP; | |
2965 | ||
690a1f20 AS |
2966 | if (wol->wolopts & ~WAKE_MAGIC) |
2967 | return -EINVAL; | |
2968 | ||
690a1f20 AS |
2969 | if (wol->wolopts & WAKE_MAGIC) |
2970 | vp->enable_wol = 1; | |
2971 | else | |
2972 | vp->enable_wol = 0; | |
2973 | acpi_set_WOL(dev); | |
690a1f20 AS |
2974 | |
2975 | return 0; | |
2976 | } | |
2977 | ||
7282d491 | 2978 | static const struct ethtool_ops vortex_ethtool_ops = { |
1da177e4 LT |
2979 | .get_drvinfo = vortex_get_drvinfo, |
2980 | .get_strings = vortex_get_strings, | |
2981 | .get_msglevel = vortex_get_msglevel, | |
2982 | .set_msglevel = vortex_set_msglevel, | |
2983 | .get_ethtool_stats = vortex_get_ethtool_stats, | |
b9f2c044 | 2984 | .get_sset_count = vortex_get_sset_count, |
1da177e4 LT |
2985 | .get_settings = vortex_get_settings, |
2986 | .set_settings = vortex_set_settings, | |
373a6887 | 2987 | .get_link = ethtool_op_get_link, |
1da177e4 | 2988 | .nway_reset = vortex_nway_reset, |
690a1f20 AS |
2989 | .get_wol = vortex_get_wol, |
2990 | .set_wol = vortex_set_wol, | |
1da177e4 LT |
2991 | }; |
2992 | ||
2993 | #ifdef CONFIG_PCI | |
2994 | /* | |
2995 | * Must power the device up to do MDIO operations | |
2996 | */ | |
2997 | static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2998 | { | |
2999 | int err; | |
3000 | struct vortex_private *vp = netdev_priv(dev); | |
cc2d6596 | 3001 | pci_power_t state = 0; |
1da177e4 LT |
3002 | |
3003 | if(VORTEX_PCI(vp)) | |
3004 | state = VORTEX_PCI(vp)->current_state; | |
3005 | ||
3006 | /* The kernel core really should have pci_get_power_state() */ | |
3007 | ||
3008 | if(state != 0) | |
3009 | pci_set_power_state(VORTEX_PCI(vp), PCI_D0); | |
1da177e4 | 3010 | err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL); |
1da177e4 LT |
3011 | if(state != 0) |
3012 | pci_set_power_state(VORTEX_PCI(vp), state); | |
3013 | ||
3014 | return err; | |
3015 | } | |
3016 | #endif | |
3017 | ||
3018 | ||
3019 | /* Pre-Cyclone chips have no documented multicast filter, so the only | |
3020 | multicast setting is to receive all multicast frames. At least | |
3021 | the chip has a very clean way to set the mode, unlike many others. */ | |
3022 | static void set_rx_mode(struct net_device *dev) | |
3023 | { | |
62afe595 JL |
3024 | struct vortex_private *vp = netdev_priv(dev); |
3025 | void __iomem *ioaddr = vp->ioaddr; | |
1da177e4 LT |
3026 | int new_mode; |
3027 | ||
3028 | if (dev->flags & IFF_PROMISC) { | |
d5b20697 | 3029 | if (vortex_debug > 3) |
39738e16 | 3030 | pr_notice("%s: Setting promiscuous mode.\n", dev->name); |
1da177e4 | 3031 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm; |
59ce25d9 | 3032 | } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) { |
1da177e4 LT |
3033 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast; |
3034 | } else | |
3035 | new_mode = SetRxFilter | RxStation | RxBroadcast; | |
3036 | ||
62afe595 | 3037 | iowrite16(new_mode, ioaddr + EL3_CMD); |
1da177e4 LT |
3038 | } |
3039 | ||
3040 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
3041 | /* Setup the card so that it can receive frames with an 802.1q VLAN tag. | |
3042 | Note that this must be done after each RxReset due to some backwards | |
3043 | compatibility logic in the Cyclone and Tornado ASICs */ | |
3044 | ||
3045 | /* The Ethernet Type used for 802.1q tagged frames */ | |
3046 | #define VLAN_ETHER_TYPE 0x8100 | |
3047 | ||
3048 | static void set_8021q_mode(struct net_device *dev, int enable) | |
3049 | { | |
3050 | struct vortex_private *vp = netdev_priv(dev); | |
1da177e4 LT |
3051 | int mac_ctrl; |
3052 | ||
3053 | if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) { | |
3054 | /* cyclone and tornado chipsets can recognize 802.1q | |
3055 | * tagged frames and treat them correctly */ | |
3056 | ||
3057 | int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */ | |
3058 | if (enable) | |
3059 | max_pkt_size += 4; /* 802.1Q VLAN tag */ | |
3060 | ||
a095cfc4 | 3061 | window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize); |
1da177e4 LT |
3062 | |
3063 | /* set VlanEtherType to let the hardware checksumming | |
3064 | treat tagged frames correctly */ | |
a095cfc4 | 3065 | window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType); |
1da177e4 LT |
3066 | } else { |
3067 | /* on older cards we have to enable large frames */ | |
3068 | ||
3069 | vp->large_frames = dev->mtu > 1500 || enable; | |
3070 | ||
a095cfc4 | 3071 | mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl); |
1da177e4 LT |
3072 | if (vp->large_frames) |
3073 | mac_ctrl |= 0x40; | |
3074 | else | |
3075 | mac_ctrl &= ~0x40; | |
a095cfc4 | 3076 | window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl); |
1da177e4 | 3077 | } |
1da177e4 LT |
3078 | } |
3079 | #else | |
3080 | ||
3081 | static void set_8021q_mode(struct net_device *dev, int enable) | |
3082 | { | |
3083 | } | |
3084 | ||
3085 | ||
3086 | #endif | |
3087 | ||
3088 | /* MII transceiver control section. | |
3089 | Read and write the MII registers using software-generated serial | |
3090 | MDIO protocol. See the MII specifications or DP83840A data sheet | |
3091 | for details. */ | |
3092 | ||
3093 | /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
3094 | met by back-to-back PCI I/O cycles, but we insert a delay to avoid | |
3095 | "overclocking" issues. */ | |
a095cfc4 BH |
3096 | static void mdio_delay(struct vortex_private *vp) |
3097 | { | |
3098 | window_read32(vp, 4, Wn4_PhysicalMgmt); | |
3099 | } | |
1da177e4 LT |
3100 | |
3101 | #define MDIO_SHIFT_CLK 0x01 | |
3102 | #define MDIO_DIR_WRITE 0x04 | |
3103 | #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) | |
3104 | #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) | |
3105 | #define MDIO_DATA_READ 0x02 | |
3106 | #define MDIO_ENB_IN 0x00 | |
3107 | ||
3108 | /* Generate the preamble required for initial synchronization and | |
3109 | a few older transceivers. */ | |
a095cfc4 | 3110 | static void mdio_sync(struct vortex_private *vp, int bits) |
1da177e4 | 3111 | { |
1da177e4 LT |
3112 | /* Establish sync by sending at least 32 logic ones. */ |
3113 | while (-- bits >= 0) { | |
a095cfc4 BH |
3114 | window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt); |
3115 | mdio_delay(vp); | |
3116 | window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, | |
3117 | 4, Wn4_PhysicalMgmt); | |
3118 | mdio_delay(vp); | |
1da177e4 LT |
3119 | } |
3120 | } | |
3121 | ||
3122 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
3123 | { | |
3124 | int i; | |
62afe595 | 3125 | struct vortex_private *vp = netdev_priv(dev); |
1da177e4 LT |
3126 | int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; |
3127 | unsigned int retval = 0; | |
1da177e4 | 3128 | |
de847272 BH |
3129 | spin_lock_bh(&vp->mii_lock); |
3130 | ||
1da177e4 | 3131 | if (mii_preamble_required) |
a095cfc4 | 3132 | mdio_sync(vp, 32); |
1da177e4 LT |
3133 | |
3134 | /* Shift the read command bits out. */ | |
3135 | for (i = 14; i >= 0; i--) { | |
3136 | int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; | |
a095cfc4 BH |
3137 | window_write16(vp, dataval, 4, Wn4_PhysicalMgmt); |
3138 | mdio_delay(vp); | |
3139 | window_write16(vp, dataval | MDIO_SHIFT_CLK, | |
3140 | 4, Wn4_PhysicalMgmt); | |
3141 | mdio_delay(vp); | |
1da177e4 LT |
3142 | } |
3143 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
3144 | for (i = 19; i > 0; i--) { | |
a095cfc4 BH |
3145 | window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt); |
3146 | mdio_delay(vp); | |
3147 | retval = (retval << 1) | | |
3148 | ((window_read16(vp, 4, Wn4_PhysicalMgmt) & | |
3149 | MDIO_DATA_READ) ? 1 : 0); | |
3150 | window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK, | |
3151 | 4, Wn4_PhysicalMgmt); | |
3152 | mdio_delay(vp); | |
1da177e4 | 3153 | } |
de847272 BH |
3154 | |
3155 | spin_unlock_bh(&vp->mii_lock); | |
3156 | ||
1da177e4 LT |
3157 | return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; |
3158 | } | |
3159 | ||
3160 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
3161 | { | |
62afe595 | 3162 | struct vortex_private *vp = netdev_priv(dev); |
1da177e4 | 3163 | int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; |
1da177e4 LT |
3164 | int i; |
3165 | ||
de847272 BH |
3166 | spin_lock_bh(&vp->mii_lock); |
3167 | ||
1da177e4 | 3168 | if (mii_preamble_required) |
a095cfc4 | 3169 | mdio_sync(vp, 32); |
1da177e4 LT |
3170 | |
3171 | /* Shift the command bits out. */ | |
3172 | for (i = 31; i >= 0; i--) { | |
3173 | int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; | |
a095cfc4 BH |
3174 | window_write16(vp, dataval, 4, Wn4_PhysicalMgmt); |
3175 | mdio_delay(vp); | |
3176 | window_write16(vp, dataval | MDIO_SHIFT_CLK, | |
3177 | 4, Wn4_PhysicalMgmt); | |
3178 | mdio_delay(vp); | |
1da177e4 LT |
3179 | } |
3180 | /* Leave the interface idle. */ | |
3181 | for (i = 1; i >= 0; i--) { | |
a095cfc4 BH |
3182 | window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt); |
3183 | mdio_delay(vp); | |
3184 | window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK, | |
3185 | 4, Wn4_PhysicalMgmt); | |
3186 | mdio_delay(vp); | |
1da177e4 | 3187 | } |
de847272 BH |
3188 | |
3189 | spin_unlock_bh(&vp->mii_lock); | |
1da177e4 | 3190 | } |
a880c4cd | 3191 | |
1da177e4 LT |
3192 | /* ACPI: Advanced Configuration and Power Interface. */ |
3193 | /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */ | |
3194 | static void acpi_set_WOL(struct net_device *dev) | |
3195 | { | |
3196 | struct vortex_private *vp = netdev_priv(dev); | |
62afe595 | 3197 | void __iomem *ioaddr = vp->ioaddr; |
1da177e4 | 3198 | |
c17931c5 SK |
3199 | device_set_wakeup_enable(vp->gendev, vp->enable_wol); |
3200 | ||
1da177e4 LT |
3201 | if (vp->enable_wol) { |
3202 | /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ | |
a095cfc4 | 3203 | window_write16(vp, 2, 7, 0x0c); |
1da177e4 | 3204 | /* The RxFilter must accept the WOL frames. */ |
62afe595 JL |
3205 | iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD); |
3206 | iowrite16(RxEnable, ioaddr + EL3_CMD); | |
1da177e4 | 3207 | |
1a1769f3 | 3208 | if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) { |
39738e16 | 3209 | pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp))); |
1a1769f3 SK |
3210 | |
3211 | vp->enable_wol = 0; | |
3212 | return; | |
3213 | } | |
3c8fad18 | 3214 | |
3fd6c88e JB |
3215 | if (VORTEX_PCI(vp)->current_state < PCI_D3hot) |
3216 | return; | |
3217 | ||
3c8fad18 DR |
3218 | /* Change the power state to D3; RxEnable doesn't take effect. */ |
3219 | pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot); | |
1da177e4 | 3220 | } |
1da177e4 LT |
3221 | } |
3222 | ||
3223 | ||
a880c4cd | 3224 | static void __devexit vortex_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
3225 | { |
3226 | struct net_device *dev = pci_get_drvdata(pdev); | |
3227 | struct vortex_private *vp; | |
3228 | ||
3229 | if (!dev) { | |
39738e16 | 3230 | pr_err("vortex_remove_one called for Compaq device!\n"); |
1da177e4 LT |
3231 | BUG(); |
3232 | } | |
3233 | ||
3234 | vp = netdev_priv(dev); | |
3235 | ||
62afe595 JL |
3236 | if (vp->cb_fn_base) |
3237 | pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base); | |
3238 | ||
1da177e4 LT |
3239 | unregister_netdev(dev); |
3240 | ||
3241 | if (VORTEX_PCI(vp)) { | |
3242 | pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */ | |
3243 | if (vp->pm_state_valid) | |
3244 | pci_restore_state(VORTEX_PCI(vp)); | |
3245 | pci_disable_device(VORTEX_PCI(vp)); | |
3246 | } | |
3247 | /* Should really use issue_and_wait() here */ | |
62afe595 JL |
3248 | iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14), |
3249 | vp->ioaddr + EL3_CMD); | |
3250 | ||
3251 | pci_iounmap(VORTEX_PCI(vp), vp->ioaddr); | |
1da177e4 LT |
3252 | |
3253 | pci_free_consistent(pdev, | |
3254 | sizeof(struct boom_rx_desc) * RX_RING_SIZE | |
3255 | + sizeof(struct boom_tx_desc) * TX_RING_SIZE, | |
3256 | vp->rx_ring, | |
3257 | vp->rx_ring_dma); | |
3258 | if (vp->must_free_region) | |
3259 | release_region(dev->base_addr, vp->io_size); | |
3260 | free_netdev(dev); | |
3261 | } | |
3262 | ||
3263 | ||
3264 | static struct pci_driver vortex_driver = { | |
3265 | .name = "3c59x", | |
3266 | .probe = vortex_init_one, | |
3267 | .remove = __devexit_p(vortex_remove_one), | |
3268 | .id_table = vortex_pci_tbl, | |
7bfc4ab5 | 3269 | .driver.pm = VORTEX_PM_OPS, |
1da177e4 LT |
3270 | }; |
3271 | ||
3272 | ||
3273 | static int vortex_have_pci; | |
3274 | static int vortex_have_eisa; | |
3275 | ||
3276 | ||
a880c4cd | 3277 | static int __init vortex_init(void) |
1da177e4 LT |
3278 | { |
3279 | int pci_rc, eisa_rc; | |
3280 | ||
29917620 | 3281 | pci_rc = pci_register_driver(&vortex_driver); |
1da177e4 LT |
3282 | eisa_rc = vortex_eisa_init(); |
3283 | ||
3284 | if (pci_rc == 0) | |
3285 | vortex_have_pci = 1; | |
3286 | if (eisa_rc > 0) | |
3287 | vortex_have_eisa = 1; | |
3288 | ||
3289 | return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV; | |
3290 | } | |
3291 | ||
3292 | ||
a880c4cd | 3293 | static void __exit vortex_eisa_cleanup(void) |
1da177e4 LT |
3294 | { |
3295 | struct vortex_private *vp; | |
62afe595 | 3296 | void __iomem *ioaddr; |
1da177e4 LT |
3297 | |
3298 | #ifdef CONFIG_EISA | |
3299 | /* Take care of the EISA devices */ | |
a880c4cd | 3300 | eisa_driver_unregister(&vortex_eisa_driver); |
1da177e4 | 3301 | #endif |
6aa20a22 | 3302 | |
1da177e4 | 3303 | if (compaq_net_device) { |
454d7c9b | 3304 | vp = netdev_priv(compaq_net_device); |
62afe595 JL |
3305 | ioaddr = ioport_map(compaq_net_device->base_addr, |
3306 | VORTEX_TOTAL_SIZE); | |
1da177e4 | 3307 | |
a880c4cd SK |
3308 | unregister_netdev(compaq_net_device); |
3309 | iowrite16(TotalReset, ioaddr + EL3_CMD); | |
62afe595 JL |
3310 | release_region(compaq_net_device->base_addr, |
3311 | VORTEX_TOTAL_SIZE); | |
1da177e4 | 3312 | |
a880c4cd | 3313 | free_netdev(compaq_net_device); |
1da177e4 LT |
3314 | } |
3315 | } | |
3316 | ||
3317 | ||
a880c4cd | 3318 | static void __exit vortex_cleanup(void) |
1da177e4 LT |
3319 | { |
3320 | if (vortex_have_pci) | |
a880c4cd | 3321 | pci_unregister_driver(&vortex_driver); |
1da177e4 | 3322 | if (vortex_have_eisa) |
a880c4cd | 3323 | vortex_eisa_cleanup(); |
1da177e4 LT |
3324 | } |
3325 | ||
3326 | ||
3327 | module_init(vortex_init); | |
3328 | module_exit(vortex_cleanup); |