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1da177e4 LT |
1 | /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */ |
2 | /* | |
3 | Written 1998-2000 by Donald Becker. | |
4 | ||
fdecea66 | 5 | Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please |
1da177e4 LT |
6 | send all bug reports to me, and not to Donald Becker, as this code |
7 | has been heavily modified from Donald's original version. | |
8 | ||
9 | This software may be used and distributed according to the terms of | |
10 | the GNU General Public License (GPL), incorporated herein by reference. | |
11 | Drivers based on or derived from this code fall under the GPL and must | |
12 | retain the authorship, copyright and license notice. This file is not | |
13 | a complete program and may only be used when the entire operating | |
14 | system is licensed under the GPL. | |
15 | ||
16 | The information below comes from Donald Becker's original driver: | |
17 | ||
18 | The author may be reached as becker@scyld.com, or C/O | |
19 | Scyld Computing Corporation | |
20 | 410 Severn Ave., Suite 210 | |
21 | Annapolis MD 21403 | |
22 | ||
23 | Support and updates available at | |
24 | http://www.scyld.com/network/starfire.html | |
03a8c661 | 25 | [link no longer provides useful info -jgarzik] |
1da177e4 | 26 | |
1da177e4 LT |
27 | */ |
28 | ||
29 | #define DRV_NAME "starfire" | |
a6676019 FR |
30 | #define DRV_VERSION "2.1" |
31 | #define DRV_RELDATE "July 6, 2008" | |
1da177e4 | 32 | |
a6b7a407 | 33 | #include <linux/interrupt.h> |
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
fdecea66 JG |
41 | #include <linux/crc32.h> |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/if_vlan.h> | |
d7fe0f24 | 45 | #include <linux/mm.h> |
cfc3a44c | 46 | #include <linux/firmware.h> |
1da177e4 LT |
47 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
48 | #include <asm/uaccess.h> | |
49 | #include <asm/io.h> | |
50 | ||
1da177e4 LT |
51 | /* |
52 | * The current frame processor firmware fails to checksum a fragment | |
53 | * of length 1. If and when this is fixed, the #define below can be removed. | |
54 | */ | |
55 | #define HAS_BROKEN_FIRMWARE | |
67974231 IB |
56 | |
57 | /* | |
58 | * If using the broken firmware, data must be padded to the next 32-bit boundary. | |
59 | */ | |
60 | #ifdef HAS_BROKEN_FIRMWARE | |
61 | #define PADDING_MASK 3 | |
62 | #endif | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Define this if using the driver with the zero-copy patch | |
66 | */ | |
1da177e4 | 67 | #define ZEROCOPY |
1da177e4 LT |
68 | |
69 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
70 | #define VLAN_SUPPORT | |
71 | #endif | |
72 | ||
1da177e4 LT |
73 | /* The user-configurable values. |
74 | These may be modified when a driver module is loaded.*/ | |
75 | ||
76 | /* Used for tuning interrupt latency vs. overhead. */ | |
77 | static int intr_latency; | |
78 | static int small_frames; | |
79 | ||
80 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
81 | static int max_interrupt_work = 20; | |
82 | static int mtu; | |
83 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
84 | The Starfire has a 512 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 512; |
1da177e4 | 86 | /* Whether to do TCP/UDP checksums in hardware */ |
1da177e4 | 87 | static int enable_hw_cksum = 1; |
1da177e4 LT |
88 | |
89 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
90 | /* | |
91 | * Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
92 | * Setting to > 1518 effectively disables this feature. | |
93 | * | |
94 | * NOTE: | |
95 | * The ia64 doesn't allow for unaligned loads even of integers being | |
96 | * misaligned on a 2 byte boundary. Thus always force copying of | |
97 | * packets as the starfire doesn't allow for misaligned DMAs ;-( | |
98 | * 23/10/2000 - Jes | |
99 | * | |
100 | * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64, | |
101 | * at least, having unaligned frames leads to a rather serious performance | |
102 | * penalty. -Ion | |
103 | */ | |
104 | #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) | |
105 | static int rx_copybreak = PKT_BUF_SZ; | |
106 | #else | |
107 | static int rx_copybreak /* = 0 */; | |
108 | #endif | |
109 | ||
110 | /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */ | |
111 | #ifdef __sparc__ | |
112 | #define DMA_BURST_SIZE 64 | |
113 | #else | |
114 | #define DMA_BURST_SIZE 128 | |
115 | #endif | |
116 | ||
117 | /* Used to pass the media type, etc. | |
118 | Both 'options[]' and 'full_duplex[]' exist for driver interoperability. | |
119 | The media type is usually passed in 'options[]'. | |
120 | These variables are deprecated, use ethtool instead. -Ion | |
121 | */ | |
122 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
123 | static int options[MAX_UNITS] = {0, }; | |
124 | static int full_duplex[MAX_UNITS] = {0, }; | |
125 | ||
126 | /* Operational parameters that are set at compile time. */ | |
127 | ||
128 | /* The "native" ring sizes are either 256 or 2048. | |
129 | However in some modes a descriptor may be marked to wrap the ring earlier. | |
130 | */ | |
131 | #define RX_RING_SIZE 256 | |
132 | #define TX_RING_SIZE 32 | |
133 | /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */ | |
134 | #define DONE_Q_SIZE 1024 | |
135 | /* All queues must be aligned on a 256-byte boundary */ | |
136 | #define QUEUE_ALIGN 256 | |
137 | ||
138 | #if RX_RING_SIZE > 256 | |
139 | #define RX_Q_ENTRIES Rx2048QEntries | |
140 | #else | |
141 | #define RX_Q_ENTRIES Rx256QEntries | |
142 | #endif | |
143 | ||
144 | /* Operational parameters that usually are not changed. */ | |
145 | /* Time in jiffies before concluding the transmitter is hung. */ | |
146 | #define TX_TIMEOUT (2 * HZ) | |
147 | ||
1591cb60 | 148 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
1da177e4 LT |
149 | /* 64-bit dma_addr_t */ |
150 | #define ADDR_64BITS /* This chip uses 64 bit addresses. */ | |
88b1943b | 151 | #define netdrv_addr_t __le64 |
1da177e4 LT |
152 | #define cpu_to_dma(x) cpu_to_le64(x) |
153 | #define dma_to_cpu(x) le64_to_cpu(x) | |
154 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit | |
155 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit | |
156 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit | |
157 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit | |
158 | #define RX_DESC_ADDR_SIZE RxDescAddr64bit | |
159 | #else /* 32-bit dma_addr_t */ | |
88b1943b | 160 | #define netdrv_addr_t __le32 |
1da177e4 LT |
161 | #define cpu_to_dma(x) cpu_to_le32(x) |
162 | #define dma_to_cpu(x) le32_to_cpu(x) | |
163 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit | |
164 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit | |
165 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit | |
166 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit | |
167 | #define RX_DESC_ADDR_SIZE RxDescAddr32bit | |
168 | #endif | |
169 | ||
1da177e4 LT |
170 | #define skb_first_frag_len(skb) skb_headlen(skb) |
171 | #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) | |
1da177e4 | 172 | |
cfc3a44c JSR |
173 | /* Firmware names */ |
174 | #define FIRMWARE_RX "adaptec/starfire_rx.bin" | |
175 | #define FIRMWARE_TX "adaptec/starfire_tx.bin" | |
176 | ||
1da177e4 | 177 | /* These identify the driver base version and may not be removed. */ |
b5defaa5 | 178 | static const char version[] __devinitconst = |
1da177e4 | 179 | KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" |
ad361c98 | 180 | " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; |
1da177e4 LT |
181 | |
182 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
183 | MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver"); | |
184 | MODULE_LICENSE("GPL"); | |
fdecea66 | 185 | MODULE_VERSION(DRV_VERSION); |
cfc3a44c JSR |
186 | MODULE_FIRMWARE(FIRMWARE_RX); |
187 | MODULE_FIRMWARE(FIRMWARE_TX); | |
1da177e4 LT |
188 | |
189 | module_param(max_interrupt_work, int, 0); | |
190 | module_param(mtu, int, 0); | |
191 | module_param(debug, int, 0); | |
192 | module_param(rx_copybreak, int, 0); | |
193 | module_param(intr_latency, int, 0); | |
194 | module_param(small_frames, int, 0); | |
195 | module_param_array(options, int, NULL, 0); | |
196 | module_param_array(full_duplex, int, NULL, 0); | |
197 | module_param(enable_hw_cksum, int, 0); | |
198 | MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt"); | |
199 | MODULE_PARM_DESC(mtu, "MTU (all boards)"); | |
200 | MODULE_PARM_DESC(debug, "Debug level (0-6)"); | |
201 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); | |
202 | MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds"); | |
203 | MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)"); | |
204 | MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex"); | |
205 | MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)"); | |
206 | MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)"); | |
207 | ||
208 | /* | |
209 | Theory of Operation | |
210 | ||
211 | I. Board Compatibility | |
212 | ||
213 | This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter. | |
214 | ||
215 | II. Board-specific settings | |
216 | ||
217 | III. Driver operation | |
218 | ||
219 | IIIa. Ring buffers | |
220 | ||
221 | The Starfire hardware uses multiple fixed-size descriptor queues/rings. The | |
222 | ring sizes are set fixed by the hardware, but may optionally be wrapped | |
223 | earlier by the END bit in the descriptor. | |
224 | This driver uses that hardware queue size for the Rx ring, where a large | |
225 | number of entries has no ill effect beyond increases the potential backlog. | |
226 | The Tx ring is wrapped with the END bit, since a large hardware Tx queue | |
227 | disables the queue layer priority ordering and we have no mechanism to | |
228 | utilize the hardware two-level priority queue. When modifying the | |
229 | RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning | |
230 | levels. | |
231 | ||
232 | IIIb/c. Transmit/Receive Structure | |
233 | ||
234 | See the Adaptec manual for the many possible structures, and options for | |
235 | each structure. There are far too many to document all of them here. | |
236 | ||
237 | For transmit this driver uses type 0/1 transmit descriptors (depending | |
238 | on the 32/64 bitness of the architecture), and relies on automatic | |
239 | minimum-length padding. It does not use the completion queue | |
240 | consumer index, but instead checks for non-zero status entries. | |
241 | ||
fdecea66 | 242 | For receive this driver uses type 2/3 receive descriptors. The driver |
1da177e4 LT |
243 | allocates full frame size skbuffs for the Rx ring buffers, so all frames |
244 | should fit in a single descriptor. The driver does not use the completion | |
245 | queue consumer index, but instead checks for non-zero status entries. | |
246 | ||
247 | When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff | |
248 | is allocated and the frame is copied to the new skbuff. When the incoming | |
249 | frame is larger, the skbuff is passed directly up the protocol stack. | |
250 | Buffers consumed this way are replaced by newly allocated skbuffs in a later | |
251 | phase of receive. | |
252 | ||
253 | A notable aspect of operation is that unaligned buffers are not permitted by | |
254 | the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame | |
255 | isn't longword aligned, which may cause problems on some machine | |
256 | e.g. Alphas and IA64. For these architectures, the driver is forced to copy | |
257 | the frame into a new skbuff unconditionally. Copied frames are put into the | |
258 | skbuff at an offset of "+2", thus 16-byte aligning the IP header. | |
259 | ||
260 | IIId. Synchronization | |
261 | ||
262 | The driver runs as two independent, single-threaded flows of control. One | |
263 | is the send-packet routine, which enforces single-threaded use by the | |
264 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
265 | threaded by the hardware and interrupt handling software. | |
266 | ||
267 | The send packet thread has partial control over the Tx ring and the netif_queue | |
268 | status. If the number of free Tx slots in the ring falls below a certain number | |
269 | (currently hardcoded to 4), it signals the upper layer to stop the queue. | |
270 | ||
271 | The interrupt handler has exclusive control over the Rx ring and records stats | |
272 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
273 | empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the | |
274 | number of free Tx slow is above the threshold, it signals the upper layer to | |
275 | restart the queue. | |
276 | ||
277 | IV. Notes | |
278 | ||
279 | IVb. References | |
280 | ||
281 | The Adaptec Starfire manuals, available only from Adaptec. | |
282 | http://www.scyld.com/expert/100mbps.html | |
283 | http://www.scyld.com/expert/NWay.html | |
284 | ||
285 | IVc. Errata | |
286 | ||
287 | - StopOnPerr is broken, don't enable | |
288 | - Hardware ethernet padding exposes random data, perform software padding | |
289 | instead (unverified -- works correctly for all the hardware I have) | |
290 | ||
291 | */ | |
292 | ||
fdecea66 | 293 | |
1da177e4 LT |
294 | |
295 | enum chip_capability_flags {CanHaveMII=1, }; | |
296 | ||
297 | enum chipset { | |
298 | CH_6915 = 0, | |
299 | }; | |
300 | ||
a3aa1884 | 301 | static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = { |
d08336e9 | 302 | { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 }, |
1da177e4 LT |
303 | { 0, } |
304 | }; | |
305 | MODULE_DEVICE_TABLE(pci, starfire_pci_tbl); | |
306 | ||
307 | /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */ | |
f71e1309 | 308 | static const struct chip_info { |
1da177e4 LT |
309 | const char *name; |
310 | int drv_flags; | |
311 | } netdrv_tbl[] __devinitdata = { | |
312 | { "Adaptec Starfire 6915", CanHaveMII }, | |
313 | }; | |
314 | ||
315 | ||
316 | /* Offsets to the device registers. | |
317 | Unlike software-only systems, device drivers interact with complex hardware. | |
318 | It's not useful to define symbolic names for every register bit in the | |
319 | device. The name can only partially document the semantics and make | |
320 | the driver longer and more difficult to read. | |
321 | In general, only the important configuration values or bits changed | |
322 | multiple times should be defined symbolically. | |
323 | */ | |
324 | enum register_offsets { | |
325 | PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074, | |
326 | IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088, | |
327 | MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000, | |
328 | GPIOCtrl=0x5008C, TxDescCtrl=0x50090, | |
329 | TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */ | |
330 | TxRingHiAddr=0x5009C, /* 64 bit address extension. */ | |
331 | TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4, | |
332 | TxThreshold=0x500B0, | |
333 | CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8, | |
334 | RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0, | |
335 | CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0, | |
336 | RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0, | |
337 | RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4, | |
338 | TxMode=0x55000, VlanType=0x55064, | |
339 | PerfFilterTable=0x56000, HashTable=0x56100, | |
340 | TxGfpMem=0x58000, RxGfpMem=0x5a000, | |
341 | }; | |
342 | ||
343 | /* | |
344 | * Bits in the interrupt status/mask registers. | |
345 | * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register | |
346 | * enables all the interrupt sources that are or'ed into those status bits. | |
347 | */ | |
348 | enum intr_status_bits { | |
349 | IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000, | |
350 | IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000, | |
351 | IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000, | |
352 | IntrTxComplQLow=0x200000, IntrPCI=0x100000, | |
353 | IntrDMAErr=0x080000, IntrTxDataLow=0x040000, | |
354 | IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000, | |
355 | IntrNormalSummary=0x8000, IntrTxDone=0x4000, | |
356 | IntrTxDMADone=0x2000, IntrTxEmpty=0x1000, | |
357 | IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400, | |
358 | IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100, | |
359 | IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40, | |
360 | IntrNoTxCsum=0x20, IntrTxBadID=0x10, | |
361 | IntrHiPriTxBadID=0x08, IntrRxGfp=0x04, | |
362 | IntrTxGfp=0x02, IntrPCIPad=0x01, | |
363 | /* not quite bits */ | |
364 | IntrRxDone=IntrRxQ2Done | IntrRxQ1Done, | |
365 | IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low, | |
366 | IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe, | |
367 | }; | |
368 | ||
369 | /* Bits in the RxFilterMode register. */ | |
370 | enum rx_mode_bits { | |
371 | AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01, | |
372 | AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30, | |
373 | PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200, | |
374 | WakeupOnGFP=0x0800, | |
375 | }; | |
376 | ||
377 | /* Bits in the TxMode register */ | |
378 | enum tx_mode_bits { | |
379 | MiiSoftReset=0x8000, MIILoopback=0x4000, | |
380 | TxFlowEnable=0x0800, RxFlowEnable=0x0400, | |
381 | PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01, | |
382 | }; | |
383 | ||
384 | /* Bits in the TxDescCtrl register. */ | |
385 | enum tx_ctrl_bits { | |
386 | TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20, | |
387 | TxDescSpace128=0x30, TxDescSpace256=0x40, | |
388 | TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02, | |
389 | TxDescType3=0x03, TxDescType4=0x04, | |
390 | TxNoDMACompletion=0x08, | |
391 | TxDescQAddr64bit=0x80, TxDescQAddr32bit=0, | |
392 | TxHiPriFIFOThreshShift=24, TxPadLenShift=16, | |
393 | TxDMABurstSizeShift=8, | |
394 | }; | |
395 | ||
396 | /* Bits in the RxDescQCtrl register. */ | |
397 | enum rx_ctrl_bits { | |
398 | RxBufferLenShift=16, RxMinDescrThreshShift=0, | |
399 | RxPrefetchMode=0x8000, RxVariableQ=0x2000, | |
400 | Rx2048QEntries=0x4000, Rx256QEntries=0, | |
401 | RxDescAddr64bit=0x1000, RxDescAddr32bit=0, | |
402 | RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0, | |
403 | RxDescSpace4=0x000, RxDescSpace8=0x100, | |
404 | RxDescSpace16=0x200, RxDescSpace32=0x300, | |
405 | RxDescSpace64=0x400, RxDescSpace128=0x500, | |
406 | RxConsumerWrEn=0x80, | |
407 | }; | |
408 | ||
409 | /* Bits in the RxDMACtrl register. */ | |
410 | enum rx_dmactrl_bits { | |
411 | RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000, | |
412 | RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000, | |
413 | RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000, | |
414 | RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000, | |
415 | RxChecksumRejectTCPOnly=0x01000000, | |
416 | RxCompletionQ2Enable=0x800000, | |
417 | RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000, | |
418 | RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000, | |
419 | RxDMAQ2NonIP=0x400000, | |
420 | RxUseBackupQueue=0x080000, RxDMACRC=0x040000, | |
421 | RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8, | |
422 | RxBurstSizeShift=0, | |
423 | }; | |
424 | ||
425 | /* Bits in the RxCompletionAddr register */ | |
426 | enum rx_compl_bits { | |
427 | RxComplQAddr64bit=0x80, RxComplQAddr32bit=0, | |
428 | RxComplProducerWrEn=0x40, | |
429 | RxComplType0=0x00, RxComplType1=0x10, | |
430 | RxComplType2=0x20, RxComplType3=0x30, | |
431 | RxComplThreshShift=0, | |
432 | }; | |
433 | ||
434 | /* Bits in the TxCompletionAddr register */ | |
435 | enum tx_compl_bits { | |
436 | TxComplQAddr64bit=0x80, TxComplQAddr32bit=0, | |
437 | TxComplProducerWrEn=0x40, | |
438 | TxComplIntrStatus=0x20, | |
439 | CommonQueueMode=0x10, | |
440 | TxComplThreshShift=0, | |
441 | }; | |
442 | ||
443 | /* Bits in the GenCtrl register */ | |
444 | enum gen_ctrl_bits { | |
445 | RxEnable=0x05, TxEnable=0x0a, | |
446 | RxGFPEnable=0x10, TxGFPEnable=0x20, | |
447 | }; | |
448 | ||
449 | /* Bits in the IntrTimerCtrl register */ | |
450 | enum intr_ctrl_bits { | |
451 | Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100, | |
452 | SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600, | |
453 | IntrLatencyMask=0x1f, | |
454 | }; | |
455 | ||
456 | /* The Rx and Tx buffer descriptors. */ | |
457 | struct starfire_rx_desc { | |
88b1943b | 458 | netdrv_addr_t rxaddr; |
1da177e4 LT |
459 | }; |
460 | enum rx_desc_bits { | |
461 | RxDescValid=1, RxDescEndRing=2, | |
462 | }; | |
463 | ||
464 | /* Completion queue entry. */ | |
465 | struct short_rx_done_desc { | |
88b1943b | 466 | __le32 status; /* Low 16 bits is length. */ |
1da177e4 LT |
467 | }; |
468 | struct basic_rx_done_desc { | |
88b1943b AV |
469 | __le32 status; /* Low 16 bits is length. */ |
470 | __le16 vlanid; | |
471 | __le16 status2; | |
1da177e4 LT |
472 | }; |
473 | struct csum_rx_done_desc { | |
88b1943b AV |
474 | __le32 status; /* Low 16 bits is length. */ |
475 | __le16 csum; /* Partial checksum */ | |
476 | __le16 status2; | |
1da177e4 LT |
477 | }; |
478 | struct full_rx_done_desc { | |
88b1943b AV |
479 | __le32 status; /* Low 16 bits is length. */ |
480 | __le16 status3; | |
481 | __le16 status2; | |
482 | __le16 vlanid; | |
483 | __le16 csum; /* partial checksum */ | |
484 | __le32 timestamp; | |
1da177e4 LT |
485 | }; |
486 | /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ | |
1da177e4 LT |
487 | #ifdef VLAN_SUPPORT |
488 | typedef struct full_rx_done_desc rx_done_desc; | |
489 | #define RxComplType RxComplType3 | |
490 | #else /* not VLAN_SUPPORT */ | |
491 | typedef struct csum_rx_done_desc rx_done_desc; | |
492 | #define RxComplType RxComplType2 | |
493 | #endif /* not VLAN_SUPPORT */ | |
1da177e4 LT |
494 | |
495 | enum rx_done_bits { | |
496 | RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000, | |
497 | }; | |
498 | ||
499 | /* Type 1 Tx descriptor. */ | |
500 | struct starfire_tx_desc_1 { | |
88b1943b AV |
501 | __le32 status; /* Upper bits are status, lower 16 length. */ |
502 | __le32 addr; | |
1da177e4 LT |
503 | }; |
504 | ||
505 | /* Type 2 Tx descriptor. */ | |
506 | struct starfire_tx_desc_2 { | |
88b1943b AV |
507 | __le32 status; /* Upper bits are status, lower 16 length. */ |
508 | __le32 reserved; | |
509 | __le64 addr; | |
1da177e4 LT |
510 | }; |
511 | ||
512 | #ifdef ADDR_64BITS | |
513 | typedef struct starfire_tx_desc_2 starfire_tx_desc; | |
514 | #define TX_DESC_TYPE TxDescType2 | |
515 | #else /* not ADDR_64BITS */ | |
516 | typedef struct starfire_tx_desc_1 starfire_tx_desc; | |
517 | #define TX_DESC_TYPE TxDescType1 | |
518 | #endif /* not ADDR_64BITS */ | |
519 | #define TX_DESC_SPACING TxDescSpaceUnlim | |
520 | ||
521 | enum tx_desc_bits { | |
522 | TxDescID=0xB0000000, | |
523 | TxCRCEn=0x01000000, TxDescIntr=0x08000000, | |
524 | TxRingWrap=0x04000000, TxCalTCP=0x02000000, | |
525 | }; | |
526 | struct tx_done_desc { | |
88b1943b | 527 | __le32 status; /* timestamp, index. */ |
1da177e4 | 528 | #if 0 |
88b1943b | 529 | __le32 intrstatus; /* interrupt status */ |
1da177e4 LT |
530 | #endif |
531 | }; | |
532 | ||
533 | struct rx_ring_info { | |
534 | struct sk_buff *skb; | |
535 | dma_addr_t mapping; | |
536 | }; | |
537 | struct tx_ring_info { | |
538 | struct sk_buff *skb; | |
539 | dma_addr_t mapping; | |
540 | unsigned int used_slots; | |
541 | }; | |
542 | ||
543 | #define PHY_CNT 2 | |
544 | struct netdev_private { | |
545 | /* Descriptor rings first for alignment. */ | |
546 | struct starfire_rx_desc *rx_ring; | |
547 | starfire_tx_desc *tx_ring; | |
548 | dma_addr_t rx_ring_dma; | |
549 | dma_addr_t tx_ring_dma; | |
550 | /* The addresses of rx/tx-in-place skbuffs. */ | |
551 | struct rx_ring_info rx_info[RX_RING_SIZE]; | |
552 | struct tx_ring_info tx_info[TX_RING_SIZE]; | |
553 | /* Pointers to completion queues (full pages). */ | |
554 | rx_done_desc *rx_done_q; | |
555 | dma_addr_t rx_done_q_dma; | |
556 | unsigned int rx_done; | |
557 | struct tx_done_desc *tx_done_q; | |
558 | dma_addr_t tx_done_q_dma; | |
559 | unsigned int tx_done; | |
bea3348e SH |
560 | struct napi_struct napi; |
561 | struct net_device *dev; | |
1da177e4 LT |
562 | struct pci_dev *pci_dev; |
563 | #ifdef VLAN_SUPPORT | |
5da96be5 | 564 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
1da177e4 LT |
565 | #endif |
566 | void *queue_mem; | |
567 | dma_addr_t queue_mem_dma; | |
568 | size_t queue_mem_size; | |
569 | ||
570 | /* Frequently used values: keep some adjacent for cache effect. */ | |
571 | spinlock_t lock; | |
572 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
573 | unsigned int cur_tx, dirty_tx, reap_tx; | |
574 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
575 | /* These values keep track of the transceiver/media in use. */ | |
576 | int speed100; /* Set if speed == 100MBit. */ | |
577 | u32 tx_mode; | |
578 | u32 intr_timer_ctrl; | |
579 | u8 tx_threshold; | |
580 | /* MII transceiver section. */ | |
581 | struct mii_if_info mii_if; /* MII lib hooks/info */ | |
582 | int phy_cnt; /* MII device addresses. */ | |
583 | unsigned char phys[PHY_CNT]; /* MII device addresses. */ | |
584 | void __iomem *base; | |
585 | }; | |
586 | ||
587 | ||
588 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
589 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
590 | static int netdev_open(struct net_device *dev); | |
591 | static void check_duplex(struct net_device *dev); | |
592 | static void tx_timeout(struct net_device *dev); | |
593 | static void init_ring(struct net_device *dev); | |
61357325 | 594 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); |
7d12e780 | 595 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 LT |
596 | static void netdev_error(struct net_device *dev, int intr_status); |
597 | static int __netdev_rx(struct net_device *dev, int *quota); | |
a6676019 | 598 | static int netdev_poll(struct napi_struct *napi, int budget); |
1da177e4 LT |
599 | static void refill_rx_ring(struct net_device *dev); |
600 | static void netdev_error(struct net_device *dev, int intr_status); | |
601 | static void set_rx_mode(struct net_device *dev); | |
602 | static struct net_device_stats *get_stats(struct net_device *dev); | |
603 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
604 | static int netdev_close(struct net_device *dev); | |
605 | static void netdev_media_change(struct net_device *dev); | |
7282d491 | 606 | static const struct ethtool_ops ethtool_ops; |
1da177e4 LT |
607 | |
608 | ||
609 | #ifdef VLAN_SUPPORT | |
8e586137 | 610 | static int netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) |
1da177e4 LT |
611 | { |
612 | struct netdev_private *np = netdev_priv(dev); | |
613 | ||
614 | spin_lock(&np->lock); | |
615 | if (debug > 1) | |
616 | printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid); | |
5da96be5 | 617 | set_bit(vid, np->active_vlans); |
1da177e4 LT |
618 | set_rx_mode(dev); |
619 | spin_unlock(&np->lock); | |
8e586137 JP |
620 | |
621 | return 0; | |
1da177e4 LT |
622 | } |
623 | ||
8e586137 | 624 | static int netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) |
1da177e4 LT |
625 | { |
626 | struct netdev_private *np = netdev_priv(dev); | |
627 | ||
628 | spin_lock(&np->lock); | |
629 | if (debug > 1) | |
630 | printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid); | |
5da96be5 | 631 | clear_bit(vid, np->active_vlans); |
1da177e4 LT |
632 | set_rx_mode(dev); |
633 | spin_unlock(&np->lock); | |
8e586137 JP |
634 | |
635 | return 0; | |
1da177e4 LT |
636 | } |
637 | #endif /* VLAN_SUPPORT */ | |
638 | ||
639 | ||
4fc8006e SH |
640 | static const struct net_device_ops netdev_ops = { |
641 | .ndo_open = netdev_open, | |
642 | .ndo_stop = netdev_close, | |
643 | .ndo_start_xmit = start_tx, | |
5da96be5 JP |
644 | .ndo_tx_timeout = tx_timeout, |
645 | .ndo_get_stats = get_stats, | |
afc4b13d | 646 | .ndo_set_rx_mode = set_rx_mode, |
5da96be5 | 647 | .ndo_do_ioctl = netdev_ioctl, |
4fc8006e | 648 | .ndo_change_mtu = eth_change_mtu, |
5da96be5 | 649 | .ndo_set_mac_address = eth_mac_addr, |
4fc8006e SH |
650 | .ndo_validate_addr = eth_validate_addr, |
651 | #ifdef VLAN_SUPPORT | |
4fc8006e SH |
652 | .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid, |
653 | .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid, | |
654 | #endif | |
655 | }; | |
656 | ||
1da177e4 LT |
657 | static int __devinit starfire_init_one(struct pci_dev *pdev, |
658 | const struct pci_device_id *ent) | |
659 | { | |
660 | struct netdev_private *np; | |
661 | int i, irq, option, chip_idx = ent->driver_data; | |
662 | struct net_device *dev; | |
663 | static int card_idx = -1; | |
664 | long ioaddr; | |
665 | void __iomem *base; | |
666 | int drv_flags, io_size; | |
667 | int boguscnt; | |
668 | ||
669 | /* when built into the kernel, we only print version if device is found */ | |
670 | #ifndef MODULE | |
671 | static int printed_version; | |
672 | if (!printed_version++) | |
673 | printk(version); | |
674 | #endif | |
675 | ||
676 | card_idx++; | |
677 | ||
678 | if (pci_enable_device (pdev)) | |
679 | return -EIO; | |
680 | ||
681 | ioaddr = pci_resource_start(pdev, 0); | |
682 | io_size = pci_resource_len(pdev, 0); | |
683 | if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) { | |
684 | printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx); | |
685 | return -ENODEV; | |
686 | } | |
687 | ||
688 | dev = alloc_etherdev(sizeof(*np)); | |
41de8d4c | 689 | if (!dev) |
1da177e4 | 690 | return -ENOMEM; |
41de8d4c | 691 | |
1da177e4 LT |
692 | SET_NETDEV_DEV(dev, &pdev->dev); |
693 | ||
694 | irq = pdev->irq; | |
695 | ||
696 | if (pci_request_regions (pdev, DRV_NAME)) { | |
697 | printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx); | |
698 | goto err_out_free_netdev; | |
699 | } | |
700 | ||
1da177e4 LT |
701 | base = ioremap(ioaddr, io_size); |
702 | if (!base) { | |
703 | printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n", | |
704 | card_idx, io_size, ioaddr); | |
705 | goto err_out_free_res; | |
706 | } | |
707 | ||
708 | pci_set_master(pdev); | |
709 | ||
710 | /* enable MWI -- it vastly improves Rx performance on sparc64 */ | |
694625c0 | 711 | pci_try_set_mwi(pdev); |
1da177e4 | 712 | |
1da177e4 LT |
713 | #ifdef ZEROCOPY |
714 | /* Starfire can do TCP/UDP checksumming */ | |
715 | if (enable_hw_cksum) | |
fdecea66 | 716 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
1da177e4 | 717 | #endif /* ZEROCOPY */ |
4fc8006e | 718 | |
1da177e4 LT |
719 | #ifdef VLAN_SUPPORT |
720 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; | |
1da177e4 LT |
721 | #endif /* VLAN_RX_KILL_VID */ |
722 | #ifdef ADDR_64BITS | |
723 | dev->features |= NETIF_F_HIGHDMA; | |
724 | #endif /* ADDR_64BITS */ | |
725 | ||
726 | /* Serial EEPROM reads are hidden by the hardware. */ | |
727 | for (i = 0; i < 6; i++) | |
728 | dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i); | |
729 | ||
730 | #if ! defined(final_version) /* Dump the EEPROM contents during development. */ | |
731 | if (debug > 4) | |
732 | for (i = 0; i < 0x20; i++) | |
733 | printk("%2.2x%s", | |
734 | (unsigned int)readb(base + EEPROMCtrl + i), | |
735 | i % 16 != 15 ? " " : "\n"); | |
736 | #endif | |
737 | ||
738 | /* Issue soft reset */ | |
739 | writel(MiiSoftReset, base + TxMode); | |
740 | udelay(1000); | |
741 | writel(0, base + TxMode); | |
742 | ||
743 | /* Reset the chip to erase previous misconfiguration. */ | |
744 | writel(1, base + PCIDeviceConfig); | |
745 | boguscnt = 1000; | |
746 | while (--boguscnt > 0) { | |
747 | udelay(10); | |
748 | if ((readl(base + PCIDeviceConfig) & 1) == 0) | |
749 | break; | |
750 | } | |
751 | if (boguscnt == 0) | |
752 | printk("%s: chipset reset never completed!\n", dev->name); | |
753 | /* wait a little longer */ | |
754 | udelay(1000); | |
755 | ||
756 | dev->base_addr = (unsigned long)base; | |
757 | dev->irq = irq; | |
758 | ||
759 | np = netdev_priv(dev); | |
bea3348e | 760 | np->dev = dev; |
1da177e4 LT |
761 | np->base = base; |
762 | spin_lock_init(&np->lock); | |
763 | pci_set_drvdata(pdev, dev); | |
764 | ||
765 | np->pci_dev = pdev; | |
766 | ||
767 | np->mii_if.dev = dev; | |
768 | np->mii_if.mdio_read = mdio_read; | |
769 | np->mii_if.mdio_write = mdio_write; | |
770 | np->mii_if.phy_id_mask = 0x1f; | |
771 | np->mii_if.reg_num_mask = 0x1f; | |
772 | ||
773 | drv_flags = netdrv_tbl[chip_idx].drv_flags; | |
774 | ||
775 | option = card_idx < MAX_UNITS ? options[card_idx] : 0; | |
776 | if (dev->mem_start) | |
777 | option = dev->mem_start; | |
778 | ||
779 | /* The lower four bits are the media type. */ | |
780 | if (option & 0x200) | |
781 | np->mii_if.full_duplex = 1; | |
782 | ||
783 | if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) | |
784 | np->mii_if.full_duplex = 1; | |
785 | ||
786 | if (np->mii_if.full_duplex) | |
787 | np->mii_if.force_media = 1; | |
788 | else | |
789 | np->mii_if.force_media = 0; | |
790 | np->speed100 = 1; | |
791 | ||
792 | /* timer resolution is 128 * 0.8us */ | |
793 | np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) | | |
794 | Timer10X | EnableIntrMasking; | |
795 | ||
796 | if (small_frames > 0) { | |
797 | np->intr_timer_ctrl |= SmallFrameBypass; | |
798 | switch (small_frames) { | |
799 | case 1 ... 64: | |
800 | np->intr_timer_ctrl |= SmallFrame64; | |
801 | break; | |
802 | case 65 ... 128: | |
803 | np->intr_timer_ctrl |= SmallFrame128; | |
804 | break; | |
805 | case 129 ... 256: | |
806 | np->intr_timer_ctrl |= SmallFrame256; | |
807 | break; | |
808 | default: | |
809 | np->intr_timer_ctrl |= SmallFrame512; | |
810 | if (small_frames > 512) | |
811 | printk("Adjusting small_frames down to 512\n"); | |
812 | break; | |
813 | } | |
814 | } | |
815 | ||
4fc8006e | 816 | dev->netdev_ops = &netdev_ops; |
fdecea66 | 817 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 LT |
818 | SET_ETHTOOL_OPS(dev, ðtool_ops); |
819 | ||
4fc8006e SH |
820 | netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work); |
821 | ||
1da177e4 LT |
822 | if (mtu) |
823 | dev->mtu = mtu; | |
824 | ||
825 | if (register_netdev(dev)) | |
826 | goto err_out_cleardev; | |
827 | ||
e174961c | 828 | printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", |
0795af57 | 829 | dev->name, netdrv_tbl[chip_idx].name, base, |
e174961c | 830 | dev->dev_addr, irq); |
1da177e4 LT |
831 | |
832 | if (drv_flags & CanHaveMII) { | |
833 | int phy, phy_idx = 0; | |
834 | int mii_status; | |
835 | for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) { | |
836 | mdio_write(dev, phy, MII_BMCR, BMCR_RESET); | |
837 | mdelay(100); | |
838 | boguscnt = 1000; | |
839 | while (--boguscnt > 0) | |
840 | if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) | |
841 | break; | |
842 | if (boguscnt == 0) { | |
fdecea66 | 843 | printk("%s: PHY#%d reset never completed!\n", dev->name, phy); |
1da177e4 LT |
844 | continue; |
845 | } | |
846 | mii_status = mdio_read(dev, phy, MII_BMSR); | |
847 | if (mii_status != 0) { | |
848 | np->phys[phy_idx++] = phy; | |
849 | np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
850 | printk(KERN_INFO "%s: MII PHY found at address %d, status " | |
851 | "%#4.4x advertising %#4.4x.\n", | |
852 | dev->name, phy, mii_status, np->mii_if.advertising); | |
853 | /* there can be only one PHY on-board */ | |
854 | break; | |
855 | } | |
856 | } | |
857 | np->phy_cnt = phy_idx; | |
858 | if (np->phy_cnt > 0) | |
859 | np->mii_if.phy_id = np->phys[0]; | |
860 | else | |
861 | memset(&np->mii_if, 0, sizeof(np->mii_if)); | |
862 | } | |
863 | ||
864 | printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n", | |
865 | dev->name, enable_hw_cksum ? "enabled" : "disabled"); | |
866 | return 0; | |
867 | ||
868 | err_out_cleardev: | |
869 | pci_set_drvdata(pdev, NULL); | |
870 | iounmap(base); | |
871 | err_out_free_res: | |
872 | pci_release_regions (pdev); | |
873 | err_out_free_netdev: | |
874 | free_netdev(dev); | |
875 | return -ENODEV; | |
876 | } | |
877 | ||
878 | ||
879 | /* Read the MII Management Data I/O (MDIO) interfaces. */ | |
880 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
881 | { | |
882 | struct netdev_private *np = netdev_priv(dev); | |
883 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
884 | int result, boguscnt=1000; | |
885 | /* ??? Should we add a busy-wait here? */ | |
e4c3c13c | 886 | do { |
1da177e4 | 887 | result = readl(mdio_addr); |
e4c3c13c | 888 | } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0); |
1da177e4 LT |
889 | if (boguscnt == 0) |
890 | return 0; | |
891 | if ((result & 0xffff) == 0xffff) | |
892 | return 0; | |
893 | return result & 0xffff; | |
894 | } | |
895 | ||
896 | ||
897 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
898 | { | |
899 | struct netdev_private *np = netdev_priv(dev); | |
900 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
901 | writel(value, mdio_addr); | |
902 | /* The busy-wait will occur before a read. */ | |
903 | } | |
904 | ||
905 | ||
906 | static int netdev_open(struct net_device *dev) | |
907 | { | |
cfc3a44c JSR |
908 | const struct firmware *fw_rx, *fw_tx; |
909 | const __be32 *fw_rx_data, *fw_tx_data; | |
1da177e4 LT |
910 | struct netdev_private *np = netdev_priv(dev); |
911 | void __iomem *ioaddr = np->base; | |
912 | int i, retval; | |
cfc3a44c | 913 | size_t tx_size, rx_size; |
1da177e4 LT |
914 | size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size; |
915 | ||
916 | /* Do we ever need to reset the chip??? */ | |
fdecea66 | 917 | |
a0607fd3 | 918 | retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
919 | if (retval) |
920 | return retval; | |
921 | ||
922 | /* Disable the Rx and Tx, and reset the chip. */ | |
923 | writel(0, ioaddr + GenCtrl); | |
924 | writel(1, ioaddr + PCIDeviceConfig); | |
925 | if (debug > 1) | |
926 | printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", | |
927 | dev->name, dev->irq); | |
928 | ||
929 | /* Allocate the various queues. */ | |
88b1943b | 930 | if (!np->queue_mem) { |
1da177e4 LT |
931 | tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; |
932 | rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
933 | tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
934 | rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE; | |
935 | np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size; | |
936 | np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma); | |
d8840ac9 AD |
937 | if (np->queue_mem == NULL) { |
938 | free_irq(dev->irq, dev); | |
1da177e4 | 939 | return -ENOMEM; |
d8840ac9 | 940 | } |
1da177e4 LT |
941 | |
942 | np->tx_done_q = np->queue_mem; | |
943 | np->tx_done_q_dma = np->queue_mem_dma; | |
944 | np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size; | |
945 | np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size; | |
946 | np->tx_ring = (void *) np->rx_done_q + rx_done_q_size; | |
947 | np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size; | |
948 | np->rx_ring = (void *) np->tx_ring + tx_ring_size; | |
949 | np->rx_ring_dma = np->tx_ring_dma + tx_ring_size; | |
950 | } | |
951 | ||
952 | /* Start with no carrier, it gets adjusted later */ | |
953 | netif_carrier_off(dev); | |
954 | init_ring(dev); | |
955 | /* Set the size of the Rx buffers. */ | |
956 | writel((np->rx_buf_sz << RxBufferLenShift) | | |
957 | (0 << RxMinDescrThreshShift) | | |
958 | RxPrefetchMode | RxVariableQ | | |
959 | RX_Q_ENTRIES | | |
960 | RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE | | |
961 | RxDescSpace4, | |
962 | ioaddr + RxDescQCtrl); | |
963 | ||
964 | /* Set up the Rx DMA controller. */ | |
965 | writel(RxChecksumIgnore | | |
966 | (0 << RxEarlyIntThreshShift) | | |
967 | (6 << RxHighPrioThreshShift) | | |
968 | ((DMA_BURST_SIZE / 32) << RxBurstSizeShift), | |
969 | ioaddr + RxDMACtrl); | |
970 | ||
971 | /* Set Tx descriptor */ | |
972 | writel((2 << TxHiPriFIFOThreshShift) | | |
973 | (0 << TxPadLenShift) | | |
974 | ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) | | |
975 | TX_DESC_Q_ADDR_SIZE | | |
976 | TX_DESC_SPACING | TX_DESC_TYPE, | |
977 | ioaddr + TxDescCtrl); | |
978 | ||
979 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr); | |
980 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr); | |
981 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr); | |
982 | writel(np->rx_ring_dma, ioaddr + RxDescQAddr); | |
983 | writel(np->tx_ring_dma, ioaddr + TxRingPtr); | |
984 | ||
985 | writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr); | |
986 | writel(np->rx_done_q_dma | | |
987 | RxComplType | | |
988 | (0 << RxComplThreshShift), | |
989 | ioaddr + RxCompletionAddr); | |
990 | ||
991 | if (debug > 1) | |
992 | printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name); | |
993 | ||
994 | /* Fill both the Tx SA register and the Rx perfect filter. */ | |
995 | for (i = 0; i < 6; i++) | |
996 | writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i); | |
997 | /* The first entry is special because it bypasses the VLAN filter. | |
998 | Don't use it. */ | |
999 | writew(0, ioaddr + PerfFilterTable); | |
1000 | writew(0, ioaddr + PerfFilterTable + 4); | |
1001 | writew(0, ioaddr + PerfFilterTable + 8); | |
1002 | for (i = 1; i < 16; i++) { | |
88b1943b | 1003 | __be16 *eaddrs = (__be16 *)dev->dev_addr; |
1da177e4 | 1004 | void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; |
88b1943b AV |
1005 | writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4; |
1006 | writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4; | |
1007 | writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8; | |
1da177e4 LT |
1008 | } |
1009 | ||
1010 | /* Initialize other registers. */ | |
1011 | /* Configure the PCI bus bursts and FIFO thresholds. */ | |
1012 | np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */ | |
1013 | writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode); | |
1014 | udelay(1000); | |
1015 | writel(np->tx_mode, ioaddr + TxMode); | |
1016 | np->tx_threshold = 4; | |
1017 | writel(np->tx_threshold, ioaddr + TxThreshold); | |
1018 | ||
1019 | writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
1020 | ||
bea3348e | 1021 | napi_enable(&np->napi); |
a6676019 | 1022 | |
1da177e4 LT |
1023 | netif_start_queue(dev); |
1024 | ||
1025 | if (debug > 1) | |
1026 | printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name); | |
1027 | set_rx_mode(dev); | |
1028 | ||
1029 | np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
1030 | check_duplex(dev); | |
1031 | ||
1032 | /* Enable GPIO interrupts on link change */ | |
1033 | writel(0x0f00ff00, ioaddr + GPIOCtrl); | |
1034 | ||
1035 | /* Set the interrupt mask */ | |
1036 | writel(IntrRxDone | IntrRxEmpty | IntrDMAErr | | |
1037 | IntrTxDMADone | IntrStatsMax | IntrLinkChange | | |
1038 | IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID, | |
1039 | ioaddr + IntrEnable); | |
1040 | /* Enable PCI interrupts. */ | |
1041 | writel(0x00800000 | readl(ioaddr + PCIDeviceConfig), | |
1042 | ioaddr + PCIDeviceConfig); | |
1043 | ||
1044 | #ifdef VLAN_SUPPORT | |
1045 | /* Set VLAN type to 802.1q */ | |
1046 | writel(ETH_P_8021Q, ioaddr + VlanType); | |
1047 | #endif /* VLAN_SUPPORT */ | |
1048 | ||
cfc3a44c JSR |
1049 | retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev); |
1050 | if (retval) { | |
1051 | printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n", | |
1052 | FIRMWARE_RX); | |
c928febf | 1053 | goto out_init; |
cfc3a44c JSR |
1054 | } |
1055 | if (fw_rx->size % 4) { | |
1056 | printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", | |
1057 | fw_rx->size, FIRMWARE_RX); | |
1058 | retval = -EINVAL; | |
1059 | goto out_rx; | |
1060 | } | |
1061 | retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev); | |
1062 | if (retval) { | |
1063 | printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n", | |
1064 | FIRMWARE_TX); | |
1065 | goto out_rx; | |
1066 | } | |
1067 | if (fw_tx->size % 4) { | |
1068 | printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", | |
1069 | fw_tx->size, FIRMWARE_TX); | |
1070 | retval = -EINVAL; | |
1071 | goto out_tx; | |
1072 | } | |
1073 | fw_rx_data = (const __be32 *)&fw_rx->data[0]; | |
1074 | fw_tx_data = (const __be32 *)&fw_tx->data[0]; | |
1075 | rx_size = fw_rx->size / 4; | |
1076 | tx_size = fw_tx->size / 4; | |
1077 | ||
1da177e4 | 1078 | /* Load Rx/Tx firmware into the frame processors */ |
cfc3a44c JSR |
1079 | for (i = 0; i < rx_size; i++) |
1080 | writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4); | |
1081 | for (i = 0; i < tx_size; i++) | |
1082 | writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4); | |
1da177e4 LT |
1083 | if (enable_hw_cksum) |
1084 | /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */ | |
1085 | writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl); | |
1086 | else | |
1087 | /* Enable the Rx and Tx units only. */ | |
1088 | writel(TxEnable|RxEnable, ioaddr + GenCtrl); | |
1089 | ||
1090 | if (debug > 1) | |
1091 | printk(KERN_DEBUG "%s: Done netdev_open().\n", | |
1092 | dev->name); | |
1093 | ||
cfc3a44c JSR |
1094 | out_tx: |
1095 | release_firmware(fw_tx); | |
1096 | out_rx: | |
1097 | release_firmware(fw_rx); | |
c928febf BH |
1098 | out_init: |
1099 | if (retval) | |
1100 | netdev_close(dev); | |
cfc3a44c | 1101 | return retval; |
1da177e4 LT |
1102 | } |
1103 | ||
1104 | ||
1105 | static void check_duplex(struct net_device *dev) | |
1106 | { | |
1107 | struct netdev_private *np = netdev_priv(dev); | |
1108 | u16 reg0; | |
1109 | int silly_count = 1000; | |
1110 | ||
1111 | mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising); | |
1112 | mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET); | |
1113 | udelay(500); | |
1114 | while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET) | |
1115 | /* do nothing */; | |
1116 | if (!silly_count) { | |
1117 | printk("%s: MII reset failed!\n", dev->name); | |
1118 | return; | |
1119 | } | |
1120 | ||
1121 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1122 | ||
1123 | if (!np->mii_if.force_media) { | |
1124 | reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; | |
1125 | } else { | |
1126 | reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); | |
1127 | if (np->speed100) | |
1128 | reg0 |= BMCR_SPEED100; | |
1129 | if (np->mii_if.full_duplex) | |
1130 | reg0 |= BMCR_FULLDPLX; | |
1131 | printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n", | |
1132 | dev->name, | |
1133 | np->speed100 ? "100" : "10", | |
1134 | np->mii_if.full_duplex ? "full" : "half"); | |
1135 | } | |
1136 | mdio_write(dev, np->phys[0], MII_BMCR, reg0); | |
1137 | } | |
1138 | ||
1139 | ||
1140 | static void tx_timeout(struct net_device *dev) | |
1141 | { | |
1142 | struct netdev_private *np = netdev_priv(dev); | |
1143 | void __iomem *ioaddr = np->base; | |
1144 | int old_debug; | |
1145 | ||
1146 | printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, " | |
1147 | "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus)); | |
1148 | ||
1149 | /* Perhaps we should reinitialize the hardware here. */ | |
1150 | ||
1151 | /* | |
1152 | * Stop and restart the interface. | |
1153 | * Cheat and increase the debug level temporarily. | |
1154 | */ | |
1155 | old_debug = debug; | |
1156 | debug = 2; | |
1157 | netdev_close(dev); | |
1158 | netdev_open(dev); | |
1159 | debug = old_debug; | |
1160 | ||
1161 | /* Trigger an immediate transmit demand. */ | |
1162 | ||
1ae5dc34 | 1163 | dev->trans_start = jiffies; /* prevent tx timeout */ |
86678a20 | 1164 | dev->stats.tx_errors++; |
1da177e4 LT |
1165 | netif_wake_queue(dev); |
1166 | } | |
1167 | ||
1168 | ||
1169 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
1170 | static void init_ring(struct net_device *dev) | |
1171 | { | |
1172 | struct netdev_private *np = netdev_priv(dev); | |
1173 | int i; | |
1174 | ||
1175 | np->cur_rx = np->cur_tx = np->reap_tx = 0; | |
1176 | np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0; | |
1177 | ||
1178 | np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
1179 | ||
1180 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
1181 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1182 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); | |
1183 | np->rx_info[i].skb = skb; | |
1184 | if (skb == NULL) | |
1185 | break; | |
689be439 | 1186 | np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1187 | skb->dev = dev; /* Mark as being used by this device. */ |
1188 | /* Grrr, we cannot offset to correctly align the IP header. */ | |
1189 | np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid); | |
1190 | } | |
1191 | writew(i - 1, np->base + RxDescQIdx); | |
1192 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
1193 | ||
1194 | /* Clear the remainder of the Rx buffer ring. */ | |
1195 | for ( ; i < RX_RING_SIZE; i++) { | |
1196 | np->rx_ring[i].rxaddr = 0; | |
1197 | np->rx_info[i].skb = NULL; | |
1198 | np->rx_info[i].mapping = 0; | |
1199 | } | |
1200 | /* Mark the last entry as wrapping the ring. */ | |
1201 | np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1202 | ||
1203 | /* Clear the completion rings. */ | |
1204 | for (i = 0; i < DONE_Q_SIZE; i++) { | |
1205 | np->rx_done_q[i].status = 0; | |
1206 | np->tx_done_q[i].status = 0; | |
1207 | } | |
1208 | ||
1209 | for (i = 0; i < TX_RING_SIZE; i++) | |
1210 | memset(&np->tx_info[i], 0, sizeof(np->tx_info[i])); | |
1da177e4 LT |
1211 | } |
1212 | ||
1213 | ||
61357325 | 1214 | static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
1215 | { |
1216 | struct netdev_private *np = netdev_priv(dev); | |
1217 | unsigned int entry; | |
1218 | u32 status; | |
1219 | int i; | |
1220 | ||
1da177e4 LT |
1221 | /* |
1222 | * be cautious here, wrapping the queue has weird semantics | |
1223 | * and we may not have enough slots even when it seems we do. | |
1224 | */ | |
1225 | if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) { | |
1226 | netif_stop_queue(dev); | |
5b548140 | 1227 | return NETDEV_TX_BUSY; |
1da177e4 LT |
1228 | } |
1229 | ||
1230 | #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE) | |
84fa7933 | 1231 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5b057c6b | 1232 | if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK)) |
67974231 | 1233 | return NETDEV_TX_OK; |
1da177e4 LT |
1234 | } |
1235 | #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */ | |
1236 | ||
1237 | entry = np->cur_tx % TX_RING_SIZE; | |
1238 | for (i = 0; i < skb_num_frags(skb); i++) { | |
1239 | int wrap_ring = 0; | |
1240 | status = TxDescID; | |
1241 | ||
1242 | if (i == 0) { | |
1243 | np->tx_info[entry].skb = skb; | |
1244 | status |= TxCRCEn; | |
1245 | if (entry >= TX_RING_SIZE - skb_num_frags(skb)) { | |
1246 | status |= TxRingWrap; | |
1247 | wrap_ring = 1; | |
1248 | } | |
1249 | if (np->reap_tx) { | |
1250 | status |= TxDescIntr; | |
1251 | np->reap_tx = 0; | |
1252 | } | |
84fa7933 | 1253 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1da177e4 | 1254 | status |= TxCalTCP; |
86678a20 | 1255 | dev->stats.tx_compressed++; |
1da177e4 LT |
1256 | } |
1257 | status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16); | |
1258 | ||
1259 | np->tx_info[entry].mapping = | |
1260 | pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1261 | } else { | |
9e903e08 ED |
1262 | const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1]; |
1263 | status |= skb_frag_size(this_frag); | |
1da177e4 | 1264 | np->tx_info[entry].mapping = |
0cd83cc0 IC |
1265 | pci_map_single(np->pci_dev, |
1266 | skb_frag_address(this_frag), | |
9e903e08 | 1267 | skb_frag_size(this_frag), |
0cd83cc0 | 1268 | PCI_DMA_TODEVICE); |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping); | |
1272 | np->tx_ring[entry].status = cpu_to_le32(status); | |
1273 | if (debug > 3) | |
1274 | printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n", | |
1275 | dev->name, np->cur_tx, np->dirty_tx, | |
1276 | entry, status); | |
1277 | if (wrap_ring) { | |
1278 | np->tx_info[entry].used_slots = TX_RING_SIZE - entry; | |
1279 | np->cur_tx += np->tx_info[entry].used_slots; | |
1280 | entry = 0; | |
1281 | } else { | |
1282 | np->tx_info[entry].used_slots = 1; | |
1283 | np->cur_tx += np->tx_info[entry].used_slots; | |
1284 | entry++; | |
1285 | } | |
1286 | /* scavenge the tx descriptors twice per TX_RING_SIZE */ | |
1287 | if (np->cur_tx % (TX_RING_SIZE / 2) == 0) | |
1288 | np->reap_tx = 1; | |
1289 | } | |
1290 | ||
1291 | /* Non-x86: explicitly flush descriptor cache lines here. */ | |
1292 | /* Ensure all descriptors are written back before the transmit is | |
1293 | initiated. - Jes */ | |
1294 | wmb(); | |
1295 | ||
1296 | /* Update the producer index. */ | |
1297 | writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx); | |
1298 | ||
1299 | /* 4 is arbitrary, but should be ok */ | |
1300 | if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE) | |
1301 | netif_stop_queue(dev); | |
1302 | ||
6ed10654 | 1303 | return NETDEV_TX_OK; |
1da177e4 LT |
1304 | } |
1305 | ||
1306 | ||
1307 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1308 | after the Tx thread. */ | |
7d12e780 | 1309 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
1310 | { |
1311 | struct net_device *dev = dev_instance; | |
1312 | struct netdev_private *np = netdev_priv(dev); | |
1313 | void __iomem *ioaddr = np->base; | |
1314 | int boguscnt = max_interrupt_work; | |
1315 | int consumer; | |
1316 | int tx_status; | |
1317 | int handled = 0; | |
1318 | ||
1319 | do { | |
1320 | u32 intr_status = readl(ioaddr + IntrClear); | |
1321 | ||
1322 | if (debug > 4) | |
1323 | printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n", | |
1324 | dev->name, intr_status); | |
1325 | ||
1326 | if (intr_status == 0 || intr_status == (u32) -1) | |
1327 | break; | |
1328 | ||
1329 | handled = 1; | |
1330 | ||
a6676019 FR |
1331 | if (intr_status & (IntrRxDone | IntrRxEmpty)) { |
1332 | u32 enable; | |
1333 | ||
288379f0 BH |
1334 | if (likely(napi_schedule_prep(&np->napi))) { |
1335 | __napi_schedule(&np->napi); | |
a6676019 FR |
1336 | enable = readl(ioaddr + IntrEnable); |
1337 | enable &= ~(IntrRxDone | IntrRxEmpty); | |
1338 | writel(enable, ioaddr + IntrEnable); | |
1339 | /* flush PCI posting buffers */ | |
1340 | readl(ioaddr + IntrEnable); | |
1341 | } else { | |
1342 | /* Paranoia check */ | |
1343 | enable = readl(ioaddr + IntrEnable); | |
1344 | if (enable & (IntrRxDone | IntrRxEmpty)) { | |
1345 | printk(KERN_INFO | |
1346 | "%s: interrupt while in poll!\n", | |
1347 | dev->name); | |
1348 | enable &= ~(IntrRxDone | IntrRxEmpty); | |
1349 | writel(enable, ioaddr + IntrEnable); | |
1350 | } | |
1351 | } | |
1352 | } | |
1da177e4 LT |
1353 | |
1354 | /* Scavenge the skbuff list based on the Tx-done queue. | |
1355 | There are redundant checks here that may be cleaned up | |
1356 | after the driver has proven to be reliable. */ | |
1357 | consumer = readl(ioaddr + TxConsumerIdx); | |
1358 | if (debug > 3) | |
1359 | printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n", | |
1360 | dev->name, consumer); | |
1361 | ||
1362 | while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) { | |
1363 | if (debug > 3) | |
1364 | printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n", | |
1365 | dev->name, np->dirty_tx, np->tx_done, tx_status); | |
1366 | if ((tx_status & 0xe0000000) == 0xa0000000) { | |
86678a20 | 1367 | dev->stats.tx_packets++; |
1da177e4 LT |
1368 | } else if ((tx_status & 0xe0000000) == 0x80000000) { |
1369 | u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc); | |
1370 | struct sk_buff *skb = np->tx_info[entry].skb; | |
1371 | np->tx_info[entry].skb = NULL; | |
1372 | pci_unmap_single(np->pci_dev, | |
1373 | np->tx_info[entry].mapping, | |
1374 | skb_first_frag_len(skb), | |
1375 | PCI_DMA_TODEVICE); | |
1376 | np->tx_info[entry].mapping = 0; | |
1377 | np->dirty_tx += np->tx_info[entry].used_slots; | |
1378 | entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE; | |
1da177e4 LT |
1379 | { |
1380 | int i; | |
1381 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1382 | pci_unmap_single(np->pci_dev, | |
1383 | np->tx_info[entry].mapping, | |
9e903e08 | 1384 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
1da177e4 LT |
1385 | PCI_DMA_TODEVICE); |
1386 | np->dirty_tx++; | |
1387 | entry++; | |
1388 | } | |
1389 | } | |
fdecea66 | 1390 | |
1da177e4 LT |
1391 | dev_kfree_skb_irq(skb); |
1392 | } | |
1393 | np->tx_done_q[np->tx_done].status = 0; | |
1394 | np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE; | |
1395 | } | |
1396 | writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2); | |
1397 | ||
1398 | if (netif_queue_stopped(dev) && | |
1399 | (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) { | |
1400 | /* The ring is no longer full, wake the queue. */ | |
1401 | netif_wake_queue(dev); | |
1402 | } | |
1403 | ||
1404 | /* Stats overflow */ | |
1405 | if (intr_status & IntrStatsMax) | |
1406 | get_stats(dev); | |
1407 | ||
1408 | /* Media change interrupt. */ | |
1409 | if (intr_status & IntrLinkChange) | |
1410 | netdev_media_change(dev); | |
1411 | ||
1412 | /* Abnormal error summary/uncommon events handlers. */ | |
1413 | if (intr_status & IntrAbnormalSummary) | |
1414 | netdev_error(dev, intr_status); | |
1415 | ||
1416 | if (--boguscnt < 0) { | |
1417 | if (debug > 1) | |
1418 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1419 | "status=%#8.8x.\n", | |
1420 | dev->name, intr_status); | |
1421 | break; | |
1422 | } | |
1423 | } while (1); | |
1424 | ||
1425 | if (debug > 4) | |
1426 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n", | |
1427 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1428 | return IRQ_RETVAL(handled); | |
1429 | } | |
1430 | ||
1431 | ||
a6676019 FR |
1432 | /* |
1433 | * This routine is logically part of the interrupt/poll handler, but separated | |
1434 | * for clarity and better register allocation. | |
1435 | */ | |
1da177e4 LT |
1436 | static int __netdev_rx(struct net_device *dev, int *quota) |
1437 | { | |
1438 | struct netdev_private *np = netdev_priv(dev); | |
1439 | u32 desc_status; | |
1440 | int retcode = 0; | |
1441 | ||
1442 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1443 | while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) { | |
1444 | struct sk_buff *skb; | |
1445 | u16 pkt_len; | |
1446 | int entry; | |
1447 | rx_done_desc *desc = &np->rx_done_q[np->rx_done]; | |
1448 | ||
1449 | if (debug > 4) | |
1450 | printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status); | |
1451 | if (!(desc_status & RxOK)) { | |
fdecea66 | 1452 | /* There was an error. */ |
1da177e4 LT |
1453 | if (debug > 2) |
1454 | printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status); | |
86678a20 | 1455 | dev->stats.rx_errors++; |
1da177e4 | 1456 | if (desc_status & RxFIFOErr) |
86678a20 | 1457 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
1458 | goto next_rx; |
1459 | } | |
1460 | ||
1461 | if (*quota <= 0) { /* out of rx quota */ | |
1462 | retcode = 1; | |
1463 | goto out; | |
1464 | } | |
1465 | (*quota)--; | |
1466 | ||
1467 | pkt_len = desc_status; /* Implicitly Truncate */ | |
1468 | entry = (desc_status >> 16) & 0x7ff; | |
1469 | ||
1470 | if (debug > 4) | |
1471 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota); | |
1472 | /* Check if the packet is long enough to accept without copying | |
1473 | to a minimally-sized skbuff. */ | |
8e95a202 JP |
1474 | if (pkt_len < rx_copybreak && |
1475 | (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1476 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1477 | pci_dma_sync_single_for_cpu(np->pci_dev, | |
1478 | np->rx_info[entry].mapping, | |
1479 | pkt_len, PCI_DMA_FROMDEVICE); | |
8c7b7faa | 1480 | skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len); |
1da177e4 LT |
1481 | pci_dma_sync_single_for_device(np->pci_dev, |
1482 | np->rx_info[entry].mapping, | |
1483 | pkt_len, PCI_DMA_FROMDEVICE); | |
1484 | skb_put(skb, pkt_len); | |
1485 | } else { | |
1486 | pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1487 | skb = np->rx_info[entry].skb; | |
1488 | skb_put(skb, pkt_len); | |
1489 | np->rx_info[entry].skb = NULL; | |
1490 | np->rx_info[entry].mapping = 0; | |
1491 | } | |
1492 | #ifndef final_version /* Remove after testing. */ | |
1493 | /* You will want this info for the initial debug. */ | |
0795af57 | 1494 | if (debug > 5) { |
e174961c JB |
1495 | printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n", |
1496 | skb->data, skb->data + 6, | |
0795af57 JP |
1497 | skb->data[12], skb->data[13]); |
1498 | } | |
1da177e4 LT |
1499 | #endif |
1500 | ||
1501 | skb->protocol = eth_type_trans(skb, dev); | |
fdecea66 | 1502 | #ifdef VLAN_SUPPORT |
1da177e4 LT |
1503 | if (debug > 4) |
1504 | printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2)); | |
1505 | #endif | |
1da177e4 LT |
1506 | if (le16_to_cpu(desc->status2) & 0x0100) { |
1507 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
86678a20 | 1508 | dev->stats.rx_compressed++; |
1da177e4 LT |
1509 | } |
1510 | /* | |
1511 | * This feature doesn't seem to be working, at least | |
1512 | * with the two firmware versions I have. If the GFP sees | |
1513 | * an IP fragment, it either ignores it completely, or reports | |
1514 | * "bad checksum" on it. | |
1515 | * | |
1516 | * Maybe I missed something -- corrections are welcome. | |
1517 | * Until then, the printk stays. :-) -Ion | |
1518 | */ | |
1519 | else if (le16_to_cpu(desc->status2) & 0x0040) { | |
84fa7933 | 1520 | skb->ip_summed = CHECKSUM_COMPLETE; |
1da177e4 LT |
1521 | skb->csum = le16_to_cpu(desc->csum); |
1522 | printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2)); | |
1523 | } | |
1da177e4 | 1524 | #ifdef VLAN_SUPPORT |
5da96be5 | 1525 | if (le16_to_cpu(desc->status2) & 0x0200) { |
a6676019 FR |
1526 | u16 vlid = le16_to_cpu(desc->vlanid); |
1527 | ||
1528 | if (debug > 4) { | |
1529 | printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", | |
1530 | vlid); | |
1531 | } | |
5da96be5 JP |
1532 | __vlan_hwaccel_put_tag(skb, vlid); |
1533 | } | |
1da177e4 | 1534 | #endif /* VLAN_SUPPORT */ |
5da96be5 | 1535 | netif_receive_skb(skb); |
86678a20 | 1536 | dev->stats.rx_packets++; |
1da177e4 LT |
1537 | |
1538 | next_rx: | |
1539 | np->cur_rx++; | |
1540 | desc->status = 0; | |
1541 | np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE; | |
1542 | } | |
9a3de255 JP |
1543 | |
1544 | if (*quota == 0) { /* out of rx quota */ | |
1545 | retcode = 1; | |
1546 | goto out; | |
1547 | } | |
1da177e4 LT |
1548 | writew(np->rx_done, np->base + CompletionQConsumerIdx); |
1549 | ||
1550 | out: | |
1551 | refill_rx_ring(dev); | |
1552 | if (debug > 5) | |
1553 | printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n", | |
1554 | retcode, np->rx_done, desc_status); | |
1555 | return retcode; | |
1556 | } | |
1557 | ||
bea3348e | 1558 | static int netdev_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1559 | { |
bea3348e SH |
1560 | struct netdev_private *np = container_of(napi, struct netdev_private, napi); |
1561 | struct net_device *dev = np->dev; | |
1da177e4 | 1562 | u32 intr_status; |
1da177e4 | 1563 | void __iomem *ioaddr = np->base; |
bea3348e | 1564 | int quota = budget; |
1da177e4 LT |
1565 | |
1566 | do { | |
1567 | writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear); | |
1568 | ||
bea3348e | 1569 | if (__netdev_rx(dev, "a)) |
1da177e4 LT |
1570 | goto out; |
1571 | ||
1572 | intr_status = readl(ioaddr + IntrStatus); | |
1573 | } while (intr_status & (IntrRxDone | IntrRxEmpty)); | |
1574 | ||
288379f0 | 1575 | napi_complete(napi); |
1da177e4 LT |
1576 | intr_status = readl(ioaddr + IntrEnable); |
1577 | intr_status |= IntrRxDone | IntrRxEmpty; | |
1578 | writel(intr_status, ioaddr + IntrEnable); | |
1579 | ||
1580 | out: | |
1581 | if (debug > 5) | |
bea3348e SH |
1582 | printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", |
1583 | budget - quota); | |
1da177e4 LT |
1584 | |
1585 | /* Restart Rx engine if stopped. */ | |
bea3348e | 1586 | return budget - quota; |
1da177e4 | 1587 | } |
1da177e4 LT |
1588 | |
1589 | static void refill_rx_ring(struct net_device *dev) | |
1590 | { | |
1591 | struct netdev_private *np = netdev_priv(dev); | |
1592 | struct sk_buff *skb; | |
1593 | int entry = -1; | |
1594 | ||
1595 | /* Refill the Rx ring buffers. */ | |
1596 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1597 | entry = np->dirty_rx % RX_RING_SIZE; | |
1598 | if (np->rx_info[entry].skb == NULL) { | |
1599 | skb = dev_alloc_skb(np->rx_buf_sz); | |
1600 | np->rx_info[entry].skb = skb; | |
1601 | if (skb == NULL) | |
1602 | break; /* Better luck next round. */ | |
1603 | np->rx_info[entry].mapping = | |
689be439 | 1604 | pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1605 | skb->dev = dev; /* Mark as being used by this device. */ |
1606 | np->rx_ring[entry].rxaddr = | |
1607 | cpu_to_dma(np->rx_info[entry].mapping | RxDescValid); | |
1608 | } | |
1609 | if (entry == RX_RING_SIZE - 1) | |
1610 | np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1611 | } | |
1612 | if (entry >= 0) | |
1613 | writew(entry, np->base + RxDescQIdx); | |
1614 | } | |
1615 | ||
1616 | ||
1617 | static void netdev_media_change(struct net_device *dev) | |
1618 | { | |
1619 | struct netdev_private *np = netdev_priv(dev); | |
1620 | void __iomem *ioaddr = np->base; | |
1621 | u16 reg0, reg1, reg4, reg5; | |
1622 | u32 new_tx_mode; | |
1623 | u32 new_intr_timer_ctrl; | |
1624 | ||
1625 | /* reset status first */ | |
1626 | mdio_read(dev, np->phys[0], MII_BMCR); | |
1627 | mdio_read(dev, np->phys[0], MII_BMSR); | |
1628 | ||
1629 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1630 | reg1 = mdio_read(dev, np->phys[0], MII_BMSR); | |
1631 | ||
1632 | if (reg1 & BMSR_LSTATUS) { | |
1633 | /* link is up */ | |
1634 | if (reg0 & BMCR_ANENABLE) { | |
1635 | /* autonegotiation is enabled */ | |
1636 | reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
1637 | reg5 = mdio_read(dev, np->phys[0], MII_LPA); | |
1638 | if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) { | |
1639 | np->speed100 = 1; | |
1640 | np->mii_if.full_duplex = 1; | |
1641 | } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) { | |
1642 | np->speed100 = 1; | |
1643 | np->mii_if.full_duplex = 0; | |
1644 | } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) { | |
1645 | np->speed100 = 0; | |
1646 | np->mii_if.full_duplex = 1; | |
1647 | } else { | |
1648 | np->speed100 = 0; | |
1649 | np->mii_if.full_duplex = 0; | |
1650 | } | |
1651 | } else { | |
1652 | /* autonegotiation is disabled */ | |
1653 | if (reg0 & BMCR_SPEED100) | |
1654 | np->speed100 = 1; | |
1655 | else | |
1656 | np->speed100 = 0; | |
1657 | if (reg0 & BMCR_FULLDPLX) | |
1658 | np->mii_if.full_duplex = 1; | |
1659 | else | |
1660 | np->mii_if.full_duplex = 0; | |
1661 | } | |
1662 | netif_carrier_on(dev); | |
1663 | printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n", | |
1664 | dev->name, | |
1665 | np->speed100 ? "100" : "10", | |
1666 | np->mii_if.full_duplex ? "full" : "half"); | |
1667 | ||
1668 | new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */ | |
1669 | if (np->mii_if.full_duplex) | |
1670 | new_tx_mode |= FullDuplex; | |
1671 | if (np->tx_mode != new_tx_mode) { | |
1672 | np->tx_mode = new_tx_mode; | |
1673 | writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode); | |
1674 | udelay(1000); | |
1675 | writel(np->tx_mode, ioaddr + TxMode); | |
1676 | } | |
1677 | ||
1678 | new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X; | |
1679 | if (np->speed100) | |
1680 | new_intr_timer_ctrl |= Timer10X; | |
1681 | if (np->intr_timer_ctrl != new_intr_timer_ctrl) { | |
1682 | np->intr_timer_ctrl = new_intr_timer_ctrl; | |
1683 | writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
1684 | } | |
1685 | } else { | |
1686 | netif_carrier_off(dev); | |
1687 | printk(KERN_DEBUG "%s: Link is down\n", dev->name); | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | ||
1692 | static void netdev_error(struct net_device *dev, int intr_status) | |
1693 | { | |
1694 | struct netdev_private *np = netdev_priv(dev); | |
1695 | ||
1696 | /* Came close to underrunning the Tx FIFO, increase threshold. */ | |
1697 | if (intr_status & IntrTxDataLow) { | |
1698 | if (np->tx_threshold <= PKT_BUF_SZ / 16) { | |
1699 | writel(++np->tx_threshold, np->base + TxThreshold); | |
1700 | printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n", | |
1701 | dev->name, np->tx_threshold * 16); | |
1702 | } else | |
1703 | printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name); | |
1704 | } | |
1705 | if (intr_status & IntrRxGFPDead) { | |
86678a20 KV |
1706 | dev->stats.rx_fifo_errors++; |
1707 | dev->stats.rx_errors++; | |
1da177e4 LT |
1708 | } |
1709 | if (intr_status & (IntrNoTxCsum | IntrDMAErr)) { | |
86678a20 KV |
1710 | dev->stats.tx_fifo_errors++; |
1711 | dev->stats.tx_errors++; | |
1da177e4 LT |
1712 | } |
1713 | if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug) | |
1714 | printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n", | |
1715 | dev->name, intr_status); | |
1716 | } | |
1717 | ||
1718 | ||
1719 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1720 | { | |
1721 | struct netdev_private *np = netdev_priv(dev); | |
1722 | void __iomem *ioaddr = np->base; | |
1723 | ||
1724 | /* This adapter architecture needs no SMP locks. */ | |
86678a20 KV |
1725 | dev->stats.tx_bytes = readl(ioaddr + 0x57010); |
1726 | dev->stats.rx_bytes = readl(ioaddr + 0x57044); | |
1727 | dev->stats.tx_packets = readl(ioaddr + 0x57000); | |
1728 | dev->stats.tx_aborted_errors = | |
1da177e4 | 1729 | readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028); |
86678a20 KV |
1730 | dev->stats.tx_window_errors = readl(ioaddr + 0x57018); |
1731 | dev->stats.collisions = | |
1da177e4 LT |
1732 | readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008); |
1733 | ||
1734 | /* The chip only need report frame silently dropped. */ | |
86678a20 | 1735 | dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus); |
1da177e4 | 1736 | writew(0, ioaddr + RxDMAStatus); |
86678a20 KV |
1737 | dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C); |
1738 | dev->stats.rx_frame_errors = readl(ioaddr + 0x57040); | |
1739 | dev->stats.rx_length_errors = readl(ioaddr + 0x57058); | |
1740 | dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C); | |
1da177e4 | 1741 | |
86678a20 | 1742 | return &dev->stats; |
1da177e4 LT |
1743 | } |
1744 | ||
5da96be5 JP |
1745 | #ifdef VLAN_SUPPORT |
1746 | static u32 set_vlan_mode(struct netdev_private *np) | |
1747 | { | |
1748 | u32 ret = VlanMode; | |
1749 | u16 vid; | |
1750 | void __iomem *filter_addr = np->base + HashTable + 8; | |
1751 | int vlan_count = 0; | |
1752 | ||
1753 | for_each_set_bit(vid, np->active_vlans, VLAN_N_VID) { | |
1754 | if (vlan_count == 32) | |
1755 | break; | |
1756 | writew(vid, filter_addr); | |
1757 | filter_addr += 16; | |
1758 | vlan_count++; | |
1759 | } | |
1760 | if (vlan_count == 32) { | |
1761 | ret |= PerfectFilterVlan; | |
1762 | while (vlan_count < 32) { | |
1763 | writew(0, filter_addr); | |
1764 | filter_addr += 16; | |
1765 | vlan_count++; | |
1766 | } | |
1767 | } | |
1768 | return ret; | |
1769 | } | |
1770 | #endif /* VLAN_SUPPORT */ | |
1da177e4 | 1771 | |
1da177e4 LT |
1772 | static void set_rx_mode(struct net_device *dev) |
1773 | { | |
1774 | struct netdev_private *np = netdev_priv(dev); | |
1775 | void __iomem *ioaddr = np->base; | |
1776 | u32 rx_mode = MinVLANPrio; | |
22bedad3 | 1777 | struct netdev_hw_addr *ha; |
1da177e4 | 1778 | int i; |
1da177e4 | 1779 | |
5da96be5 JP |
1780 | #ifdef VLAN_SUPPORT |
1781 | rx_mode |= set_vlan_mode(np); | |
1da177e4 LT |
1782 | #endif /* VLAN_SUPPORT */ |
1783 | ||
1784 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1785 | rx_mode |= AcceptAll; | |
4cd24eaf | 1786 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 1787 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
1788 | /* Too many to match, or accept all multicasts. */ |
1789 | rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter; | |
4cd24eaf | 1790 | } else if (netdev_mc_count(dev) <= 14) { |
1da177e4 LT |
1791 | /* Use the 16 element perfect filter, skip first two entries. */ |
1792 | void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
88b1943b | 1793 | __be16 *eaddrs; |
22bedad3 JP |
1794 | netdev_for_each_mc_addr(ha, dev) { |
1795 | eaddrs = (__be16 *) ha->addr; | |
88b1943b AV |
1796 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4; |
1797 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1798 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8; | |
1da177e4 | 1799 | } |
88b1943b | 1800 | eaddrs = (__be16 *)dev->dev_addr; |
5508590c | 1801 | i = netdev_mc_count(dev) + 2; |
1da177e4 | 1802 | while (i++ < 16) { |
88b1943b AV |
1803 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; |
1804 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1805 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8; | |
1da177e4 LT |
1806 | } |
1807 | rx_mode |= AcceptBroadcast|PerfectFilter; | |
1808 | } else { | |
1809 | /* Must use a multicast hash table. */ | |
1810 | void __iomem *filter_addr; | |
88b1943b AV |
1811 | __be16 *eaddrs; |
1812 | __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ | |
1da177e4 LT |
1813 | |
1814 | memset(mc_filter, 0, sizeof(mc_filter)); | |
22bedad3 | 1815 | netdev_for_each_mc_addr(ha, dev) { |
fdecea66 JG |
1816 | /* The chip uses the upper 9 CRC bits |
1817 | as index into the hash table */ | |
22bedad3 | 1818 | int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23; |
88b1943b | 1819 | __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1]; |
1da177e4 LT |
1820 | |
1821 | *fptr |= cpu_to_le32(1 << (bit_nr & 31)); | |
1822 | } | |
1823 | /* Clear the perfect filter list, skip first two entries. */ | |
1824 | filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
88b1943b | 1825 | eaddrs = (__be16 *)dev->dev_addr; |
1da177e4 | 1826 | for (i = 2; i < 16; i++) { |
88b1943b AV |
1827 | writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4; |
1828 | writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4; | |
1829 | writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8; | |
1da177e4 LT |
1830 | } |
1831 | for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) | |
1832 | writew(mc_filter[i], filter_addr); | |
1833 | rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter; | |
1834 | } | |
1835 | writel(rx_mode, ioaddr + RxFilterMode); | |
1836 | } | |
1837 | ||
1838 | static int check_if_running(struct net_device *dev) | |
1839 | { | |
1840 | if (!netif_running(dev)) | |
1841 | return -EINVAL; | |
1842 | return 0; | |
1843 | } | |
1844 | ||
1845 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1846 | { | |
1847 | struct netdev_private *np = netdev_priv(dev); | |
68aad78c RJ |
1848 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
1849 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1850 | strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1851 | } |
1852 | ||
1853 | static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1854 | { | |
1855 | struct netdev_private *np = netdev_priv(dev); | |
1856 | spin_lock_irq(&np->lock); | |
1857 | mii_ethtool_gset(&np->mii_if, ecmd); | |
1858 | spin_unlock_irq(&np->lock); | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1863 | { | |
1864 | struct netdev_private *np = netdev_priv(dev); | |
1865 | int res; | |
1866 | spin_lock_irq(&np->lock); | |
1867 | res = mii_ethtool_sset(&np->mii_if, ecmd); | |
1868 | spin_unlock_irq(&np->lock); | |
1869 | check_duplex(dev); | |
1870 | return res; | |
1871 | } | |
1872 | ||
1873 | static int nway_reset(struct net_device *dev) | |
1874 | { | |
1875 | struct netdev_private *np = netdev_priv(dev); | |
1876 | return mii_nway_restart(&np->mii_if); | |
1877 | } | |
1878 | ||
1879 | static u32 get_link(struct net_device *dev) | |
1880 | { | |
1881 | struct netdev_private *np = netdev_priv(dev); | |
1882 | return mii_link_ok(&np->mii_if); | |
1883 | } | |
1884 | ||
1885 | static u32 get_msglevel(struct net_device *dev) | |
1886 | { | |
1887 | return debug; | |
1888 | } | |
1889 | ||
1890 | static void set_msglevel(struct net_device *dev, u32 val) | |
1891 | { | |
1892 | debug = val; | |
1893 | } | |
1894 | ||
7282d491 | 1895 | static const struct ethtool_ops ethtool_ops = { |
1da177e4 LT |
1896 | .begin = check_if_running, |
1897 | .get_drvinfo = get_drvinfo, | |
1898 | .get_settings = get_settings, | |
1899 | .set_settings = set_settings, | |
1900 | .nway_reset = nway_reset, | |
1901 | .get_link = get_link, | |
1902 | .get_msglevel = get_msglevel, | |
1903 | .set_msglevel = set_msglevel, | |
1904 | }; | |
1905 | ||
1906 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1907 | { | |
1908 | struct netdev_private *np = netdev_priv(dev); | |
1909 | struct mii_ioctl_data *data = if_mii(rq); | |
1910 | int rc; | |
1911 | ||
1912 | if (!netif_running(dev)) | |
1913 | return -EINVAL; | |
1914 | ||
1915 | spin_lock_irq(&np->lock); | |
1916 | rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL); | |
1917 | spin_unlock_irq(&np->lock); | |
1918 | ||
1919 | if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0])) | |
1920 | check_duplex(dev); | |
1921 | ||
1922 | return rc; | |
1923 | } | |
1924 | ||
1925 | static int netdev_close(struct net_device *dev) | |
1926 | { | |
1927 | struct netdev_private *np = netdev_priv(dev); | |
1928 | void __iomem *ioaddr = np->base; | |
1929 | int i; | |
1930 | ||
1931 | netif_stop_queue(dev); | |
a6676019 | 1932 | |
bea3348e | 1933 | napi_disable(&np->napi); |
1da177e4 LT |
1934 | |
1935 | if (debug > 1) { | |
1936 | printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", | |
1937 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1938 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1939 | dev->name, np->cur_tx, np->dirty_tx, | |
1940 | np->cur_rx, np->dirty_rx); | |
1941 | } | |
1942 | ||
1943 | /* Disable interrupts by clearing the interrupt mask. */ | |
1944 | writel(0, ioaddr + IntrEnable); | |
1945 | ||
1946 | /* Stop the chip's Tx and Rx processes. */ | |
1947 | writel(0, ioaddr + GenCtrl); | |
1948 | readl(ioaddr + GenCtrl); | |
1949 | ||
1950 | if (debug > 5) { | |
1951 | printk(KERN_DEBUG" Tx ring at %#llx:\n", | |
1952 | (long long) np->tx_ring_dma); | |
1953 | for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++) | |
1954 | printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n", | |
1955 | i, le32_to_cpu(np->tx_ring[i].status), | |
1956 | (long long) dma_to_cpu(np->tx_ring[i].addr), | |
1957 | le32_to_cpu(np->tx_done_q[i].status)); | |
1958 | printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n", | |
1959 | (long long) np->rx_ring_dma, np->rx_done_q); | |
1960 | if (np->rx_done_q) | |
1961 | for (i = 0; i < 8 /* RX_RING_SIZE */; i++) { | |
1962 | printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n", | |
1963 | i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status)); | |
1964 | } | |
1965 | } | |
1966 | ||
1967 | free_irq(dev->irq, dev); | |
1968 | ||
1969 | /* Free all the skbuffs in the Rx queue. */ | |
1970 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1971 | np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */ | |
1972 | if (np->rx_info[i].skb != NULL) { | |
1973 | pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1974 | dev_kfree_skb(np->rx_info[i].skb); | |
1975 | } | |
1976 | np->rx_info[i].skb = NULL; | |
1977 | np->rx_info[i].mapping = 0; | |
1978 | } | |
1979 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1980 | struct sk_buff *skb = np->tx_info[i].skb; | |
1981 | if (skb == NULL) | |
1982 | continue; | |
1983 | pci_unmap_single(np->pci_dev, | |
1984 | np->tx_info[i].mapping, | |
1985 | skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1986 | np->tx_info[i].mapping = 0; | |
1987 | dev_kfree_skb(skb); | |
1988 | np->tx_info[i].skb = NULL; | |
1989 | } | |
1990 | ||
1991 | return 0; | |
1992 | } | |
1993 | ||
d4fbeabb SR |
1994 | #ifdef CONFIG_PM |
1995 | static int starfire_suspend(struct pci_dev *pdev, pm_message_t state) | |
1996 | { | |
1997 | struct net_device *dev = pci_get_drvdata(pdev); | |
1998 | ||
1999 | if (netif_running(dev)) { | |
2000 | netif_device_detach(dev); | |
2001 | netdev_close(dev); | |
2002 | } | |
2003 | ||
2004 | pci_save_state(pdev); | |
2005 | pci_set_power_state(pdev, pci_choose_state(pdev,state)); | |
2006 | ||
2007 | return 0; | |
2008 | } | |
2009 | ||
2010 | static int starfire_resume(struct pci_dev *pdev) | |
2011 | { | |
2012 | struct net_device *dev = pci_get_drvdata(pdev); | |
6aa20a22 | 2013 | |
d4fbeabb SR |
2014 | pci_set_power_state(pdev, PCI_D0); |
2015 | pci_restore_state(pdev); | |
2016 | ||
2017 | if (netif_running(dev)) { | |
2018 | netdev_open(dev); | |
2019 | netif_device_attach(dev); | |
2020 | } | |
2021 | ||
2022 | return 0; | |
2023 | } | |
2024 | #endif /* CONFIG_PM */ | |
2025 | ||
1da177e4 LT |
2026 | |
2027 | static void __devexit starfire_remove_one (struct pci_dev *pdev) | |
2028 | { | |
2029 | struct net_device *dev = pci_get_drvdata(pdev); | |
2030 | struct netdev_private *np = netdev_priv(dev); | |
2031 | ||
5d9428de | 2032 | BUG_ON(!dev); |
1da177e4 LT |
2033 | |
2034 | unregister_netdev(dev); | |
2035 | ||
2036 | if (np->queue_mem) | |
2037 | pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma); | |
2038 | ||
2039 | ||
2040 | /* XXX: add wakeup code -- requires firmware for MagicPacket */ | |
2041 | pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */ | |
2042 | pci_disable_device(pdev); | |
2043 | ||
2044 | iounmap(np->base); | |
2045 | pci_release_regions(pdev); | |
2046 | ||
2047 | pci_set_drvdata(pdev, NULL); | |
2048 | free_netdev(dev); /* Will also free np!! */ | |
2049 | } | |
2050 | ||
2051 | ||
2052 | static struct pci_driver starfire_driver = { | |
2053 | .name = DRV_NAME, | |
2054 | .probe = starfire_init_one, | |
2055 | .remove = __devexit_p(starfire_remove_one), | |
d4fbeabb SR |
2056 | #ifdef CONFIG_PM |
2057 | .suspend = starfire_suspend, | |
2058 | .resume = starfire_resume, | |
2059 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
2060 | .id_table = starfire_pci_tbl, |
2061 | }; | |
2062 | ||
2063 | ||
2064 | static int __init starfire_init (void) | |
2065 | { | |
2066 | /* when a module, this is printed whether or not devices are found in probe */ | |
2067 | #ifdef MODULE | |
2068 | printk(version); | |
a6676019 | 2069 | |
fdecea66 | 2070 | printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n"); |
fdecea66 JG |
2071 | #endif |
2072 | ||
56543af9 | 2073 | BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t)); |
67974231 | 2074 | |
29917620 | 2075 | return pci_register_driver(&starfire_driver); |
1da177e4 LT |
2076 | } |
2077 | ||
2078 | ||
2079 | static void __exit starfire_cleanup (void) | |
2080 | { | |
2081 | pci_unregister_driver (&starfire_driver); | |
2082 | } | |
2083 | ||
2084 | ||
2085 | module_init(starfire_init); | |
2086 | module_exit(starfire_cleanup); | |
2087 | ||
2088 | ||
2089 | /* | |
2090 | * Local variables: | |
2091 | * c-basic-offset: 8 | |
2092 | * tab-width: 8 | |
2093 | * End: | |
2094 | */ |