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60c140df LS |
1 | /* |
2 | * Driver for Gigabit Ethernet adapters based on the Session Layer | |
3 | * Interface (SLIC) technology by Alacritech. The driver does not | |
4 | * support the hardware acceleration features provided by these cards. | |
5 | * | |
6 | * Copyright (C) 2016 Lino Sanfilippo <LinoSanfilippo@gmx.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/etherdevice.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/crc32.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/mii.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/firmware.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/u64_stats_sync.h> | |
34 | ||
35 | #include "slic.h" | |
36 | ||
37 | #define DRV_NAME "slicoss" | |
38 | #define DRV_VERSION "1.0" | |
39 | ||
40 | static const struct pci_device_id slic_id_tbl[] = { | |
41 | { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, | |
42 | PCI_DEVICE_ID_ALACRITECH_MOJAVE) }, | |
43 | { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, | |
44 | PCI_DEVICE_ID_ALACRITECH_OASIS) }, | |
45 | { 0 } | |
46 | }; | |
47 | ||
48 | static const char slic_stats_strings[][ETH_GSTRING_LEN] = { | |
49 | "rx_packets", | |
50 | "rx_bytes", | |
51 | "rx_multicasts", | |
52 | "rx_errors", | |
53 | "rx_buff_miss", | |
54 | "rx_tp_csum", | |
55 | "rx_tp_oflow", | |
56 | "rx_tp_hlen", | |
57 | "rx_ip_csum", | |
58 | "rx_ip_len", | |
59 | "rx_ip_hdr_len", | |
60 | "rx_early", | |
61 | "rx_buff_oflow", | |
62 | "rx_lcode", | |
63 | "rx_drbl", | |
64 | "rx_crc", | |
65 | "rx_oflow_802", | |
66 | "rx_uflow_802", | |
67 | "tx_packets", | |
68 | "tx_bytes", | |
69 | "tx_carrier", | |
70 | "tx_dropped", | |
71 | "irq_errs", | |
72 | }; | |
73 | ||
74 | static inline int slic_next_queue_idx(unsigned int idx, unsigned int qlen) | |
75 | { | |
76 | return (idx + 1) & (qlen - 1); | |
77 | } | |
78 | ||
79 | static inline int slic_get_free_queue_descs(unsigned int put_idx, | |
80 | unsigned int done_idx, | |
81 | unsigned int qlen) | |
82 | { | |
83 | if (put_idx >= done_idx) | |
84 | return (qlen - (put_idx - done_idx) - 1); | |
85 | return (done_idx - put_idx - 1); | |
86 | } | |
87 | ||
88 | static unsigned int slic_next_compl_idx(struct slic_device *sdev) | |
89 | { | |
90 | struct slic_stat_queue *stq = &sdev->stq; | |
91 | unsigned int active = stq->active_array; | |
92 | struct slic_stat_desc *descs; | |
93 | struct slic_stat_desc *stat; | |
94 | unsigned int idx; | |
95 | ||
96 | descs = stq->descs[active]; | |
97 | stat = &descs[stq->done_idx]; | |
98 | ||
99 | if (!stat->status) | |
100 | return SLIC_INVALID_STAT_DESC_IDX; | |
101 | ||
102 | idx = (le32_to_cpu(stat->hnd) & 0xffff) - 1; | |
103 | /* reset desc */ | |
104 | stat->hnd = 0; | |
105 | stat->status = 0; | |
106 | ||
107 | stq->done_idx = slic_next_queue_idx(stq->done_idx, stq->len); | |
108 | /* check for wraparound */ | |
109 | if (!stq->done_idx) { | |
110 | dma_addr_t paddr = stq->paddr[active]; | |
111 | ||
112 | slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) | | |
113 | stq->len); | |
114 | /* make sure new status descriptors are immediately available */ | |
115 | slic_flush_write(sdev); | |
116 | active++; | |
117 | active &= (SLIC_NUM_STAT_DESC_ARRAYS - 1); | |
118 | stq->active_array = active; | |
119 | } | |
120 | return idx; | |
121 | } | |
122 | ||
123 | static unsigned int slic_get_free_tx_descs(struct slic_tx_queue *txq) | |
124 | { | |
125 | /* ensure tail idx is updated */ | |
126 | smp_mb(); | |
127 | return slic_get_free_queue_descs(txq->put_idx, txq->done_idx, txq->len); | |
128 | } | |
129 | ||
130 | static unsigned int slic_get_free_rx_descs(struct slic_rx_queue *rxq) | |
131 | { | |
132 | return slic_get_free_queue_descs(rxq->put_idx, rxq->done_idx, rxq->len); | |
133 | } | |
134 | ||
135 | static void slic_clear_upr_list(struct slic_upr_list *upr_list) | |
136 | { | |
137 | struct slic_upr *upr; | |
138 | struct slic_upr *tmp; | |
139 | ||
140 | spin_lock_bh(&upr_list->lock); | |
141 | list_for_each_entry_safe(upr, tmp, &upr_list->list, list) { | |
142 | list_del(&upr->list); | |
143 | kfree(upr); | |
144 | } | |
145 | upr_list->pending = false; | |
146 | spin_unlock_bh(&upr_list->lock); | |
147 | } | |
148 | ||
149 | static void slic_start_upr(struct slic_device *sdev, struct slic_upr *upr) | |
150 | { | |
151 | u32 reg; | |
152 | ||
153 | reg = (upr->type == SLIC_UPR_CONFIG) ? SLIC_REG_RCONFIG : | |
154 | SLIC_REG_LSTAT; | |
155 | slic_write(sdev, reg, lower_32_bits(upr->paddr)); | |
156 | slic_flush_write(sdev); | |
157 | } | |
158 | ||
159 | static void slic_queue_upr(struct slic_device *sdev, struct slic_upr *upr) | |
160 | { | |
161 | struct slic_upr_list *upr_list = &sdev->upr_list; | |
162 | bool pending; | |
163 | ||
164 | spin_lock_bh(&upr_list->lock); | |
165 | pending = upr_list->pending; | |
166 | INIT_LIST_HEAD(&upr->list); | |
167 | list_add_tail(&upr->list, &upr_list->list); | |
168 | upr_list->pending = true; | |
169 | spin_unlock_bh(&upr_list->lock); | |
170 | ||
171 | if (!pending) | |
172 | slic_start_upr(sdev, upr); | |
173 | } | |
174 | ||
175 | static struct slic_upr *slic_dequeue_upr(struct slic_device *sdev) | |
176 | { | |
177 | struct slic_upr_list *upr_list = &sdev->upr_list; | |
178 | struct slic_upr *next_upr = NULL; | |
179 | struct slic_upr *upr = NULL; | |
180 | ||
181 | spin_lock_bh(&upr_list->lock); | |
182 | if (!list_empty(&upr_list->list)) { | |
183 | upr = list_first_entry(&upr_list->list, struct slic_upr, list); | |
184 | list_del(&upr->list); | |
185 | ||
186 | if (list_empty(&upr_list->list)) | |
187 | upr_list->pending = false; | |
188 | else | |
189 | next_upr = list_first_entry(&upr_list->list, | |
190 | struct slic_upr, list); | |
191 | } | |
192 | spin_unlock_bh(&upr_list->lock); | |
193 | /* trigger processing of the next upr in list */ | |
194 | if (next_upr) | |
195 | slic_start_upr(sdev, next_upr); | |
196 | ||
197 | return upr; | |
198 | } | |
199 | ||
200 | static int slic_new_upr(struct slic_device *sdev, unsigned int type, | |
201 | dma_addr_t paddr) | |
202 | { | |
203 | struct slic_upr *upr; | |
204 | ||
205 | upr = kmalloc(sizeof(*upr), GFP_ATOMIC); | |
206 | if (!upr) | |
207 | return -ENOMEM; | |
208 | upr->type = type; | |
209 | upr->paddr = paddr; | |
210 | ||
211 | slic_queue_upr(sdev, upr); | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
216 | static void slic_set_mcast_bit(u64 *mcmask, unsigned char const *addr) | |
217 | { | |
218 | u64 mask = *mcmask; | |
219 | u8 crc; | |
220 | /* Get the CRC polynomial for the mac address: we use bits 1-8 (lsb), | |
221 | * bitwise reversed, msb (= lsb bit 0 before bitrev) is automatically | |
222 | * discarded. | |
223 | */ | |
224 | crc = ether_crc(ETH_ALEN, addr) >> 23; | |
225 | /* we only have space on the SLIC for 64 entries */ | |
226 | crc &= 0x3F; | |
227 | mask |= (u64)1 << crc; | |
228 | *mcmask = mask; | |
229 | } | |
230 | ||
231 | /* must be called with link_lock held */ | |
232 | static void slic_configure_rcv(struct slic_device *sdev) | |
233 | { | |
234 | u32 val; | |
235 | ||
236 | val = SLIC_GRCR_RESET | SLIC_GRCR_ADDRAEN | SLIC_GRCR_RCVEN | | |
237 | SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT | SLIC_GRCR_RCVBAD; | |
238 | ||
239 | if (sdev->duplex == DUPLEX_FULL) | |
240 | val |= SLIC_GRCR_CTLEN; | |
241 | ||
242 | if (sdev->promisc) | |
243 | val |= SLIC_GRCR_RCVALL; | |
244 | ||
245 | slic_write(sdev, SLIC_REG_WRCFG, val); | |
246 | } | |
247 | ||
248 | /* must be called with link_lock held */ | |
249 | static void slic_configure_xmt(struct slic_device *sdev) | |
250 | { | |
251 | u32 val; | |
252 | ||
253 | val = SLIC_GXCR_RESET | SLIC_GXCR_XMTEN; | |
254 | ||
255 | if (sdev->duplex == DUPLEX_FULL) | |
256 | val |= SLIC_GXCR_PAUSEEN; | |
257 | ||
258 | slic_write(sdev, SLIC_REG_WXCFG, val); | |
259 | } | |
260 | ||
261 | /* must be called with link_lock held */ | |
262 | static void slic_configure_mac(struct slic_device *sdev) | |
263 | { | |
264 | u32 val; | |
265 | ||
266 | if (sdev->speed == SPEED_1000) { | |
267 | val = SLIC_GMCR_GAPBB_1000 << SLIC_GMCR_GAPBB_SHIFT | | |
268 | SLIC_GMCR_GAPR1_1000 << SLIC_GMCR_GAPR1_SHIFT | | |
269 | SLIC_GMCR_GAPR2_1000 << SLIC_GMCR_GAPR2_SHIFT | | |
270 | SLIC_GMCR_GBIT; /* enable GMII */ | |
271 | } else { | |
272 | val = SLIC_GMCR_GAPBB_100 << SLIC_GMCR_GAPBB_SHIFT | | |
273 | SLIC_GMCR_GAPR1_100 << SLIC_GMCR_GAPR1_SHIFT | | |
274 | SLIC_GMCR_GAPR2_100 << SLIC_GMCR_GAPR2_SHIFT; | |
275 | } | |
276 | ||
277 | if (sdev->duplex == DUPLEX_FULL) | |
278 | val |= SLIC_GMCR_FULLD; | |
279 | ||
280 | slic_write(sdev, SLIC_REG_WMCFG, val); | |
281 | } | |
282 | ||
283 | static void slic_configure_link_locked(struct slic_device *sdev, int speed, | |
284 | unsigned int duplex) | |
285 | { | |
286 | struct net_device *dev = sdev->netdev; | |
287 | ||
288 | if (sdev->speed == speed && sdev->duplex == duplex) | |
289 | return; | |
290 | ||
291 | sdev->speed = speed; | |
292 | sdev->duplex = duplex; | |
293 | ||
294 | if (sdev->speed == SPEED_UNKNOWN) { | |
295 | if (netif_carrier_ok(dev)) | |
296 | netif_carrier_off(dev); | |
297 | } else { | |
298 | /* (re)configure link settings */ | |
299 | slic_configure_mac(sdev); | |
300 | slic_configure_xmt(sdev); | |
301 | slic_configure_rcv(sdev); | |
302 | slic_flush_write(sdev); | |
303 | ||
304 | if (!netif_carrier_ok(dev)) | |
305 | netif_carrier_on(dev); | |
306 | } | |
307 | } | |
308 | ||
309 | static void slic_configure_link(struct slic_device *sdev, int speed, | |
310 | unsigned int duplex) | |
311 | { | |
312 | spin_lock_bh(&sdev->link_lock); | |
313 | slic_configure_link_locked(sdev, speed, duplex); | |
314 | spin_unlock_bh(&sdev->link_lock); | |
315 | } | |
316 | ||
317 | static void slic_set_rx_mode(struct net_device *dev) | |
318 | { | |
319 | struct slic_device *sdev = netdev_priv(dev); | |
320 | struct netdev_hw_addr *hwaddr; | |
321 | bool set_promisc; | |
322 | u64 mcmask; | |
323 | ||
324 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { | |
325 | /* Turn on all multicast addresses. We have to do this for | |
326 | * promiscuous mode as well as ALLMCAST mode (it saves the | |
327 | * microcode from having to keep state about the MAC | |
328 | * configuration). | |
329 | */ | |
330 | mcmask = ~(u64)0; | |
331 | } else { | |
332 | mcmask = 0; | |
333 | ||
334 | netdev_for_each_mc_addr(hwaddr, dev) { | |
335 | slic_set_mcast_bit(&mcmask, hwaddr->addr); | |
336 | } | |
337 | } | |
338 | ||
339 | slic_write(sdev, SLIC_REG_MCASTLOW, lower_32_bits(mcmask)); | |
340 | slic_write(sdev, SLIC_REG_MCASTHIGH, upper_32_bits(mcmask)); | |
341 | ||
342 | set_promisc = !!(dev->flags & IFF_PROMISC); | |
343 | ||
344 | spin_lock_bh(&sdev->link_lock); | |
345 | if (sdev->promisc != set_promisc) { | |
346 | sdev->promisc = set_promisc; | |
347 | slic_configure_rcv(sdev); | |
348 | /* make sure writes to receiver cant leak out of the lock */ | |
349 | mmiowb(); | |
350 | } | |
351 | spin_unlock_bh(&sdev->link_lock); | |
352 | } | |
353 | ||
354 | static void slic_xmit_complete(struct slic_device *sdev) | |
355 | { | |
356 | struct slic_tx_queue *txq = &sdev->txq; | |
357 | struct net_device *dev = sdev->netdev; | |
60c140df LS |
358 | struct slic_tx_buffer *buff; |
359 | unsigned int frames = 0; | |
360 | unsigned int bytes = 0; | |
687d4f2b | 361 | unsigned int idx; |
60c140df LS |
362 | |
363 | /* Limit processing to SLIC_MAX_TX_COMPLETIONS frames to avoid that new | |
364 | * completions during processing keeps the loop running endlessly. | |
365 | */ | |
366 | do { | |
367 | idx = slic_next_compl_idx(sdev); | |
368 | if (idx == SLIC_INVALID_STAT_DESC_IDX) | |
369 | break; | |
370 | ||
371 | txq->done_idx = idx; | |
372 | buff = &txq->txbuffs[idx]; | |
373 | ||
374 | if (unlikely(!buff->skb)) { | |
375 | netdev_warn(dev, | |
376 | "no skb found for desc idx %i\n", idx); | |
377 | continue; | |
378 | } | |
379 | dma_unmap_single(&sdev->pdev->dev, | |
380 | dma_unmap_addr(buff, map_addr), | |
381 | dma_unmap_len(buff, map_len), DMA_TO_DEVICE); | |
382 | ||
383 | bytes += buff->skb->len; | |
384 | frames++; | |
385 | ||
386 | dev_kfree_skb_any(buff->skb); | |
387 | buff->skb = NULL; | |
388 | } while (frames < SLIC_MAX_TX_COMPLETIONS); | |
389 | /* make sure xmit sees the new value for done_idx */ | |
390 | smp_wmb(); | |
391 | ||
392 | u64_stats_update_begin(&sdev->stats.syncp); | |
393 | sdev->stats.tx_bytes += bytes; | |
394 | sdev->stats.tx_packets += frames; | |
395 | u64_stats_update_end(&sdev->stats.syncp); | |
396 | ||
397 | netif_tx_lock(dev); | |
398 | if (netif_queue_stopped(dev) && | |
399 | (slic_get_free_tx_descs(txq) >= SLIC_MIN_TX_WAKEUP_DESCS)) | |
400 | netif_wake_queue(dev); | |
401 | netif_tx_unlock(dev); | |
402 | } | |
403 | ||
404 | static void slic_refill_rx_queue(struct slic_device *sdev, gfp_t gfp) | |
405 | { | |
406 | const unsigned int ALIGN_MASK = SLIC_RX_BUFF_ALIGN - 1; | |
407 | unsigned int maplen = SLIC_RX_BUFF_SIZE; | |
408 | struct slic_rx_queue *rxq = &sdev->rxq; | |
409 | struct net_device *dev = sdev->netdev; | |
410 | struct slic_rx_buffer *buff; | |
411 | struct slic_rx_desc *desc; | |
412 | unsigned int misalign; | |
413 | unsigned int offset; | |
414 | struct sk_buff *skb; | |
415 | dma_addr_t paddr; | |
416 | ||
417 | while (slic_get_free_rx_descs(rxq) > SLIC_MAX_REQ_RX_DESCS) { | |
418 | skb = alloc_skb(maplen + ALIGN_MASK, gfp); | |
419 | if (!skb) | |
420 | break; | |
421 | ||
422 | paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen, | |
423 | DMA_FROM_DEVICE); | |
424 | if (dma_mapping_error(&sdev->pdev->dev, paddr)) { | |
425 | netdev_err(dev, "mapping rx packet failed\n"); | |
426 | /* drop skb */ | |
427 | dev_kfree_skb_any(skb); | |
428 | break; | |
429 | } | |
430 | /* ensure head buffer descriptors are 256 byte aligned */ | |
431 | offset = 0; | |
432 | misalign = paddr & ALIGN_MASK; | |
433 | if (misalign) { | |
434 | offset = SLIC_RX_BUFF_ALIGN - misalign; | |
435 | skb_reserve(skb, offset); | |
436 | } | |
437 | /* the HW expects dma chunks for descriptor + frame data */ | |
438 | desc = (struct slic_rx_desc *)skb->data; | |
439 | /* temporarily sync descriptor for CPU to clear status */ | |
440 | dma_sync_single_for_cpu(&sdev->pdev->dev, paddr, | |
441 | offset + sizeof(*desc), | |
442 | DMA_FROM_DEVICE); | |
443 | desc->status = 0; | |
444 | /* return it to HW again */ | |
445 | dma_sync_single_for_device(&sdev->pdev->dev, paddr, | |
446 | offset + sizeof(*desc), | |
447 | DMA_FROM_DEVICE); | |
448 | ||
449 | buff = &rxq->rxbuffs[rxq->put_idx]; | |
450 | buff->skb = skb; | |
451 | dma_unmap_addr_set(buff, map_addr, paddr); | |
452 | dma_unmap_len_set(buff, map_len, maplen); | |
453 | buff->addr_offset = offset; | |
454 | /* complete write to descriptor before it is handed to HW */ | |
455 | wmb(); | |
456 | /* head buffer descriptors are placed immediately before skb */ | |
457 | slic_write(sdev, SLIC_REG_HBAR, lower_32_bits(paddr) + offset); | |
458 | rxq->put_idx = slic_next_queue_idx(rxq->put_idx, rxq->len); | |
459 | } | |
460 | } | |
461 | ||
462 | static void slic_handle_frame_error(struct slic_device *sdev, | |
463 | struct sk_buff *skb) | |
464 | { | |
465 | struct slic_stats *stats = &sdev->stats; | |
466 | ||
467 | if (sdev->model == SLIC_MODEL_OASIS) { | |
468 | struct slic_rx_info_oasis *info; | |
469 | u32 status_b; | |
470 | u32 status; | |
471 | ||
472 | info = (struct slic_rx_info_oasis *)skb->data; | |
473 | status = le32_to_cpu(info->frame_status); | |
474 | status_b = le32_to_cpu(info->frame_status_b); | |
475 | /* transport layer */ | |
476 | if (status_b & SLIC_VRHSTATB_TPCSUM) | |
477 | SLIC_INC_STATS_COUNTER(stats, rx_tpcsum); | |
478 | if (status & SLIC_VRHSTAT_TPOFLO) | |
479 | SLIC_INC_STATS_COUNTER(stats, rx_tpoflow); | |
480 | if (status_b & SLIC_VRHSTATB_TPHLEN) | |
481 | SLIC_INC_STATS_COUNTER(stats, rx_tphlen); | |
482 | /* ip layer */ | |
483 | if (status_b & SLIC_VRHSTATB_IPCSUM) | |
484 | SLIC_INC_STATS_COUNTER(stats, rx_ipcsum); | |
485 | if (status_b & SLIC_VRHSTATB_IPLERR) | |
486 | SLIC_INC_STATS_COUNTER(stats, rx_iplen); | |
487 | if (status_b & SLIC_VRHSTATB_IPHERR) | |
488 | SLIC_INC_STATS_COUNTER(stats, rx_iphlen); | |
489 | /* link layer */ | |
490 | if (status_b & SLIC_VRHSTATB_RCVE) | |
491 | SLIC_INC_STATS_COUNTER(stats, rx_early); | |
492 | if (status_b & SLIC_VRHSTATB_BUFF) | |
493 | SLIC_INC_STATS_COUNTER(stats, rx_buffoflow); | |
494 | if (status_b & SLIC_VRHSTATB_CODE) | |
495 | SLIC_INC_STATS_COUNTER(stats, rx_lcode); | |
496 | if (status_b & SLIC_VRHSTATB_DRBL) | |
497 | SLIC_INC_STATS_COUNTER(stats, rx_drbl); | |
498 | if (status_b & SLIC_VRHSTATB_CRC) | |
499 | SLIC_INC_STATS_COUNTER(stats, rx_crc); | |
500 | if (status & SLIC_VRHSTAT_802OE) | |
501 | SLIC_INC_STATS_COUNTER(stats, rx_oflow802); | |
502 | if (status_b & SLIC_VRHSTATB_802UE) | |
503 | SLIC_INC_STATS_COUNTER(stats, rx_uflow802); | |
504 | if (status_b & SLIC_VRHSTATB_CARRE) | |
505 | SLIC_INC_STATS_COUNTER(stats, tx_carrier); | |
506 | } else { /* mojave */ | |
507 | struct slic_rx_info_mojave *info; | |
508 | u32 status; | |
509 | ||
510 | info = (struct slic_rx_info_mojave *)skb->data; | |
511 | status = le32_to_cpu(info->frame_status); | |
512 | /* transport layer */ | |
513 | if (status & SLIC_VGBSTAT_XPERR) { | |
514 | u32 xerr = status >> SLIC_VGBSTAT_XERRSHFT; | |
515 | ||
516 | if (xerr == SLIC_VGBSTAT_XCSERR) | |
517 | SLIC_INC_STATS_COUNTER(stats, rx_tpcsum); | |
518 | if (xerr == SLIC_VGBSTAT_XUFLOW) | |
519 | SLIC_INC_STATS_COUNTER(stats, rx_tpoflow); | |
520 | if (xerr == SLIC_VGBSTAT_XHLEN) | |
521 | SLIC_INC_STATS_COUNTER(stats, rx_tphlen); | |
522 | } | |
523 | /* ip layer */ | |
524 | if (status & SLIC_VGBSTAT_NETERR) { | |
525 | u32 nerr = status >> SLIC_VGBSTAT_NERRSHFT & | |
526 | SLIC_VGBSTAT_NERRMSK; | |
527 | ||
528 | if (nerr == SLIC_VGBSTAT_NCSERR) | |
529 | SLIC_INC_STATS_COUNTER(stats, rx_ipcsum); | |
530 | if (nerr == SLIC_VGBSTAT_NUFLOW) | |
531 | SLIC_INC_STATS_COUNTER(stats, rx_iplen); | |
532 | if (nerr == SLIC_VGBSTAT_NHLEN) | |
533 | SLIC_INC_STATS_COUNTER(stats, rx_iphlen); | |
534 | } | |
535 | /* link layer */ | |
536 | if (status & SLIC_VGBSTAT_LNKERR) { | |
537 | u32 lerr = status & SLIC_VGBSTAT_LERRMSK; | |
538 | ||
539 | if (lerr == SLIC_VGBSTAT_LDEARLY) | |
540 | SLIC_INC_STATS_COUNTER(stats, rx_early); | |
541 | if (lerr == SLIC_VGBSTAT_LBOFLO) | |
542 | SLIC_INC_STATS_COUNTER(stats, rx_buffoflow); | |
543 | if (lerr == SLIC_VGBSTAT_LCODERR) | |
544 | SLIC_INC_STATS_COUNTER(stats, rx_lcode); | |
545 | if (lerr == SLIC_VGBSTAT_LDBLNBL) | |
546 | SLIC_INC_STATS_COUNTER(stats, rx_drbl); | |
547 | if (lerr == SLIC_VGBSTAT_LCRCERR) | |
548 | SLIC_INC_STATS_COUNTER(stats, rx_crc); | |
549 | if (lerr == SLIC_VGBSTAT_LOFLO) | |
550 | SLIC_INC_STATS_COUNTER(stats, rx_oflow802); | |
551 | if (lerr == SLIC_VGBSTAT_LUFLO) | |
552 | SLIC_INC_STATS_COUNTER(stats, rx_uflow802); | |
553 | } | |
554 | } | |
555 | SLIC_INC_STATS_COUNTER(stats, rx_errors); | |
556 | } | |
557 | ||
558 | static void slic_handle_receive(struct slic_device *sdev, unsigned int todo, | |
559 | unsigned int *done) | |
560 | { | |
561 | struct slic_rx_queue *rxq = &sdev->rxq; | |
562 | struct net_device *dev = sdev->netdev; | |
563 | struct slic_rx_buffer *buff; | |
564 | struct slic_rx_desc *desc; | |
565 | unsigned int frames = 0; | |
566 | unsigned int bytes = 0; | |
567 | struct sk_buff *skb; | |
568 | u32 status; | |
569 | u32 len; | |
570 | ||
571 | while (todo && (rxq->done_idx != rxq->put_idx)) { | |
572 | buff = &rxq->rxbuffs[rxq->done_idx]; | |
573 | ||
574 | skb = buff->skb; | |
575 | if (!skb) | |
576 | break; | |
577 | ||
578 | desc = (struct slic_rx_desc *)skb->data; | |
579 | ||
580 | dma_sync_single_for_cpu(&sdev->pdev->dev, | |
581 | dma_unmap_addr(buff, map_addr), | |
582 | buff->addr_offset + sizeof(*desc), | |
583 | DMA_FROM_DEVICE); | |
584 | ||
585 | status = le32_to_cpu(desc->status); | |
586 | if (!(status & SLIC_IRHDDR_SVALID)) { | |
587 | dma_sync_single_for_device(&sdev->pdev->dev, | |
588 | dma_unmap_addr(buff, | |
589 | map_addr), | |
590 | buff->addr_offset + | |
591 | sizeof(*desc), | |
592 | DMA_FROM_DEVICE); | |
593 | break; | |
594 | } | |
595 | ||
596 | buff->skb = NULL; | |
597 | ||
598 | dma_unmap_single(&sdev->pdev->dev, | |
599 | dma_unmap_addr(buff, map_addr), | |
600 | dma_unmap_len(buff, map_len), | |
601 | DMA_FROM_DEVICE); | |
602 | ||
603 | /* skip rx descriptor that is placed before the frame data */ | |
604 | skb_reserve(skb, SLIC_RX_BUFF_HDR_SIZE); | |
605 | ||
606 | if (unlikely(status & SLIC_IRHDDR_ERR)) { | |
607 | slic_handle_frame_error(sdev, skb); | |
608 | dev_kfree_skb_any(skb); | |
609 | } else { | |
610 | struct ethhdr *eh = (struct ethhdr *)skb->data; | |
611 | ||
612 | if (is_multicast_ether_addr(eh->h_dest)) | |
613 | SLIC_INC_STATS_COUNTER(&sdev->stats, rx_mcasts); | |
614 | ||
615 | len = le32_to_cpu(desc->length) & SLIC_IRHDDR_FLEN_MSK; | |
616 | skb_put(skb, len); | |
617 | skb->protocol = eth_type_trans(skb, dev); | |
618 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
619 | ||
620 | napi_gro_receive(&sdev->napi, skb); | |
621 | ||
622 | bytes += len; | |
623 | frames++; | |
624 | } | |
625 | rxq->done_idx = slic_next_queue_idx(rxq->done_idx, rxq->len); | |
626 | todo--; | |
627 | } | |
628 | ||
629 | u64_stats_update_begin(&sdev->stats.syncp); | |
630 | sdev->stats.rx_bytes += bytes; | |
631 | sdev->stats.rx_packets += frames; | |
632 | u64_stats_update_end(&sdev->stats.syncp); | |
633 | ||
634 | slic_refill_rx_queue(sdev, GFP_ATOMIC); | |
635 | } | |
636 | ||
637 | static void slic_handle_link_irq(struct slic_device *sdev) | |
638 | { | |
639 | struct slic_shmem *sm = &sdev->shmem; | |
640 | struct slic_shmem_data *sm_data = sm->shmem_data; | |
641 | unsigned int duplex; | |
642 | int speed; | |
643 | u32 link; | |
644 | ||
645 | link = le32_to_cpu(sm_data->link); | |
646 | ||
647 | if (link & SLIC_GIG_LINKUP) { | |
648 | if (link & SLIC_GIG_SPEED_1000) | |
649 | speed = SPEED_1000; | |
650 | else if (link & SLIC_GIG_SPEED_100) | |
651 | speed = SPEED_100; | |
652 | else | |
653 | speed = SPEED_10; | |
654 | ||
655 | duplex = (link & SLIC_GIG_FULLDUPLEX) ? DUPLEX_FULL : | |
656 | DUPLEX_HALF; | |
657 | } else { | |
658 | duplex = DUPLEX_UNKNOWN; | |
659 | speed = SPEED_UNKNOWN; | |
660 | } | |
661 | slic_configure_link(sdev, speed, duplex); | |
662 | } | |
663 | ||
664 | static void slic_handle_upr_irq(struct slic_device *sdev, u32 irqs) | |
665 | { | |
666 | struct slic_upr *upr; | |
667 | ||
668 | /* remove upr that caused this irq (always the first entry in list) */ | |
669 | upr = slic_dequeue_upr(sdev); | |
670 | if (!upr) { | |
671 | netdev_warn(sdev->netdev, "no upr found on list\n"); | |
672 | return; | |
673 | } | |
674 | ||
675 | if (upr->type == SLIC_UPR_LSTAT) { | |
676 | if (unlikely(irqs & SLIC_ISR_UPCERR_MASK)) { | |
677 | /* try again */ | |
678 | slic_queue_upr(sdev, upr); | |
679 | return; | |
680 | } | |
681 | slic_handle_link_irq(sdev); | |
682 | } | |
683 | kfree(upr); | |
684 | } | |
685 | ||
686 | static int slic_handle_link_change(struct slic_device *sdev) | |
687 | { | |
688 | return slic_new_upr(sdev, SLIC_UPR_LSTAT, sdev->shmem.link_paddr); | |
689 | } | |
690 | ||
691 | static void slic_handle_err_irq(struct slic_device *sdev, u32 isr) | |
692 | { | |
693 | struct slic_stats *stats = &sdev->stats; | |
694 | ||
695 | if (isr & SLIC_ISR_RMISS) | |
696 | SLIC_INC_STATS_COUNTER(stats, rx_buff_miss); | |
697 | if (isr & SLIC_ISR_XDROP) | |
698 | SLIC_INC_STATS_COUNTER(stats, tx_dropped); | |
699 | if (!(isr & (SLIC_ISR_RMISS | SLIC_ISR_XDROP))) | |
700 | SLIC_INC_STATS_COUNTER(stats, irq_errs); | |
701 | } | |
702 | ||
703 | static void slic_handle_irq(struct slic_device *sdev, u32 isr, | |
704 | unsigned int todo, unsigned int *done) | |
705 | { | |
706 | if (isr & SLIC_ISR_ERR) | |
707 | slic_handle_err_irq(sdev, isr); | |
708 | ||
709 | if (isr & SLIC_ISR_LEVENT) | |
710 | slic_handle_link_change(sdev); | |
711 | ||
712 | if (isr & SLIC_ISR_UPC_MASK) | |
713 | slic_handle_upr_irq(sdev, isr); | |
714 | ||
715 | if (isr & SLIC_ISR_RCV) | |
716 | slic_handle_receive(sdev, todo, done); | |
717 | ||
718 | if (isr & SLIC_ISR_CMD) | |
719 | slic_xmit_complete(sdev); | |
720 | } | |
721 | ||
722 | static int slic_poll(struct napi_struct *napi, int todo) | |
723 | { | |
724 | struct slic_device *sdev = container_of(napi, struct slic_device, napi); | |
725 | struct slic_shmem *sm = &sdev->shmem; | |
726 | struct slic_shmem_data *sm_data = sm->shmem_data; | |
727 | u32 isr = le32_to_cpu(sm_data->isr); | |
728 | int done = 0; | |
729 | ||
730 | slic_handle_irq(sdev, isr, todo, &done); | |
731 | ||
732 | if (done < todo) { | |
733 | napi_complete_done(napi, done); | |
734 | /* reenable irqs */ | |
735 | sm_data->isr = 0; | |
736 | /* make sure sm_data->isr is cleard before irqs are reenabled */ | |
737 | wmb(); | |
738 | slic_write(sdev, SLIC_REG_ISR, 0); | |
739 | slic_flush_write(sdev); | |
740 | } | |
741 | ||
742 | return done; | |
743 | } | |
744 | ||
745 | static irqreturn_t slic_irq(int irq, void *dev_id) | |
746 | { | |
747 | struct slic_device *sdev = dev_id; | |
748 | struct slic_shmem *sm = &sdev->shmem; | |
749 | struct slic_shmem_data *sm_data = sm->shmem_data; | |
750 | ||
751 | slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_MASK); | |
752 | slic_flush_write(sdev); | |
753 | /* make sure sm_data->isr is read after ICR_INT_MASK is set */ | |
754 | wmb(); | |
755 | ||
756 | if (!sm_data->isr) { | |
757 | dma_rmb(); | |
758 | /* spurious interrupt */ | |
759 | slic_write(sdev, SLIC_REG_ISR, 0); | |
760 | slic_flush_write(sdev); | |
761 | return IRQ_NONE; | |
762 | } | |
763 | ||
764 | napi_schedule_irqoff(&sdev->napi); | |
765 | ||
766 | return IRQ_HANDLED; | |
767 | } | |
768 | ||
769 | static void slic_card_reset(struct slic_device *sdev) | |
770 | { | |
771 | u16 cmd; | |
772 | ||
773 | slic_write(sdev, SLIC_REG_RESET, SLIC_RESET_MAGIC); | |
774 | /* flush write by means of config space */ | |
775 | pci_read_config_word(sdev->pdev, PCI_COMMAND, &cmd); | |
776 | mdelay(1); | |
777 | } | |
778 | ||
779 | static int slic_init_stat_queue(struct slic_device *sdev) | |
780 | { | |
781 | const unsigned int DESC_ALIGN_MASK = SLIC_STATS_DESC_ALIGN - 1; | |
782 | struct slic_stat_queue *stq = &sdev->stq; | |
783 | struct slic_stat_desc *descs; | |
784 | unsigned int misalign; | |
785 | unsigned int offset; | |
786 | dma_addr_t paddr; | |
787 | size_t size; | |
788 | int err; | |
789 | int i; | |
790 | ||
791 | stq->len = SLIC_NUM_STAT_DESCS; | |
792 | stq->active_array = 0; | |
793 | stq->done_idx = 0; | |
794 | ||
795 | size = stq->len * sizeof(*descs) + DESC_ALIGN_MASK; | |
796 | ||
797 | for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) { | |
750afb08 LC |
798 | descs = dma_alloc_coherent(&sdev->pdev->dev, size, &paddr, |
799 | GFP_KERNEL); | |
60c140df LS |
800 | if (!descs) { |
801 | netdev_err(sdev->netdev, | |
802 | "failed to allocate status descriptors\n"); | |
803 | err = -ENOMEM; | |
804 | goto free_descs; | |
805 | } | |
806 | /* ensure correct alignment */ | |
807 | offset = 0; | |
808 | misalign = paddr & DESC_ALIGN_MASK; | |
809 | if (misalign) { | |
810 | offset = SLIC_STATS_DESC_ALIGN - misalign; | |
811 | descs += offset; | |
812 | paddr += offset; | |
813 | } | |
814 | ||
815 | slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) | | |
816 | stq->len); | |
817 | stq->descs[i] = descs; | |
818 | stq->paddr[i] = paddr; | |
819 | stq->addr_offset[i] = offset; | |
820 | } | |
821 | ||
822 | stq->mem_size = size; | |
823 | ||
824 | return 0; | |
825 | ||
826 | free_descs: | |
827 | while (i--) { | |
828 | dma_free_coherent(&sdev->pdev->dev, stq->mem_size, | |
829 | stq->descs[i] - stq->addr_offset[i], | |
830 | stq->paddr[i] - stq->addr_offset[i]); | |
831 | } | |
832 | ||
833 | return err; | |
834 | } | |
835 | ||
836 | static void slic_free_stat_queue(struct slic_device *sdev) | |
837 | { | |
838 | struct slic_stat_queue *stq = &sdev->stq; | |
839 | int i; | |
840 | ||
841 | for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) { | |
842 | dma_free_coherent(&sdev->pdev->dev, stq->mem_size, | |
843 | stq->descs[i] - stq->addr_offset[i], | |
844 | stq->paddr[i] - stq->addr_offset[i]); | |
845 | } | |
846 | } | |
847 | ||
848 | static int slic_init_tx_queue(struct slic_device *sdev) | |
849 | { | |
850 | struct slic_tx_queue *txq = &sdev->txq; | |
851 | struct slic_tx_buffer *buff; | |
852 | struct slic_tx_desc *desc; | |
853 | unsigned int i; | |
854 | int err; | |
855 | ||
856 | txq->len = SLIC_NUM_TX_DESCS; | |
857 | txq->put_idx = 0; | |
858 | txq->done_idx = 0; | |
859 | ||
860 | txq->txbuffs = kcalloc(txq->len, sizeof(*buff), GFP_KERNEL); | |
861 | if (!txq->txbuffs) | |
862 | return -ENOMEM; | |
863 | ||
864 | txq->dma_pool = dma_pool_create("slic_pool", &sdev->pdev->dev, | |
865 | sizeof(*desc), SLIC_TX_DESC_ALIGN, | |
866 | 4096); | |
867 | if (!txq->dma_pool) { | |
868 | err = -ENOMEM; | |
869 | netdev_err(sdev->netdev, "failed to create dma pool\n"); | |
870 | goto free_buffs; | |
871 | } | |
872 | ||
873 | for (i = 0; i < txq->len; i++) { | |
874 | buff = &txq->txbuffs[i]; | |
875 | desc = dma_pool_zalloc(txq->dma_pool, GFP_KERNEL, | |
876 | &buff->desc_paddr); | |
877 | if (!desc) { | |
878 | netdev_err(sdev->netdev, | |
879 | "failed to alloc pool chunk (%i)\n", i); | |
880 | err = -ENOMEM; | |
881 | goto free_descs; | |
882 | } | |
883 | ||
884 | desc->hnd = cpu_to_le32((u32)(i + 1)); | |
885 | desc->cmd = SLIC_CMD_XMT_REQ; | |
886 | desc->flags = 0; | |
887 | desc->type = cpu_to_le32(SLIC_CMD_TYPE_DUMB); | |
888 | buff->desc = desc; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | ||
893 | free_descs: | |
894 | while (i--) { | |
895 | buff = &txq->txbuffs[i]; | |
896 | dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr); | |
897 | } | |
898 | dma_pool_destroy(txq->dma_pool); | |
899 | ||
900 | free_buffs: | |
901 | kfree(txq->txbuffs); | |
902 | ||
903 | return err; | |
904 | } | |
905 | ||
906 | static void slic_free_tx_queue(struct slic_device *sdev) | |
907 | { | |
908 | struct slic_tx_queue *txq = &sdev->txq; | |
909 | struct slic_tx_buffer *buff; | |
910 | unsigned int i; | |
911 | ||
912 | for (i = 0; i < txq->len; i++) { | |
913 | buff = &txq->txbuffs[i]; | |
914 | dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr); | |
915 | if (!buff->skb) | |
916 | continue; | |
917 | ||
918 | dma_unmap_single(&sdev->pdev->dev, | |
919 | dma_unmap_addr(buff, map_addr), | |
920 | dma_unmap_len(buff, map_len), DMA_TO_DEVICE); | |
921 | consume_skb(buff->skb); | |
922 | } | |
923 | dma_pool_destroy(txq->dma_pool); | |
924 | ||
925 | kfree(txq->txbuffs); | |
926 | } | |
927 | ||
928 | static int slic_init_rx_queue(struct slic_device *sdev) | |
929 | { | |
930 | struct slic_rx_queue *rxq = &sdev->rxq; | |
931 | struct slic_rx_buffer *buff; | |
932 | ||
933 | rxq->len = SLIC_NUM_RX_LES; | |
934 | rxq->done_idx = 0; | |
935 | rxq->put_idx = 0; | |
936 | ||
937 | buff = kcalloc(rxq->len, sizeof(*buff), GFP_KERNEL); | |
938 | if (!buff) | |
939 | return -ENOMEM; | |
940 | ||
941 | rxq->rxbuffs = buff; | |
942 | slic_refill_rx_queue(sdev, GFP_KERNEL); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | static void slic_free_rx_queue(struct slic_device *sdev) | |
948 | { | |
949 | struct slic_rx_queue *rxq = &sdev->rxq; | |
950 | struct slic_rx_buffer *buff; | |
951 | unsigned int i; | |
952 | ||
953 | /* free rx buffers */ | |
954 | for (i = 0; i < rxq->len; i++) { | |
955 | buff = &rxq->rxbuffs[i]; | |
956 | ||
957 | if (!buff->skb) | |
958 | continue; | |
959 | ||
960 | dma_unmap_single(&sdev->pdev->dev, | |
961 | dma_unmap_addr(buff, map_addr), | |
962 | dma_unmap_len(buff, map_len), | |
963 | DMA_FROM_DEVICE); | |
964 | consume_skb(buff->skb); | |
965 | } | |
966 | kfree(rxq->rxbuffs); | |
967 | } | |
968 | ||
969 | static void slic_set_link_autoneg(struct slic_device *sdev) | |
970 | { | |
971 | unsigned int subid = sdev->pdev->subsystem_device; | |
972 | u32 val; | |
973 | ||
974 | if (sdev->is_fiber) { | |
975 | /* We've got a fiber gigabit interface, and register 4 is | |
976 | * different in fiber mode than in copper mode. | |
977 | */ | |
978 | /* advertise FD only @1000 Mb */ | |
979 | val = MII_ADVERTISE << 16 | ADVERTISE_1000XFULL | | |
980 | ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | |
981 | /* enable PAUSE frames */ | |
982 | slic_write(sdev, SLIC_REG_WPHY, val); | |
983 | /* reset phy, enable auto-neg */ | |
984 | val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE | | |
985 | BMCR_ANRESTART; | |
986 | slic_write(sdev, SLIC_REG_WPHY, val); | |
987 | } else { /* copper gigabit */ | |
988 | /* We've got a copper gigabit interface, and register 4 is | |
989 | * different in copper mode than in fiber mode. | |
990 | */ | |
991 | /* advertise 10/100 Mb modes */ | |
992 | val = MII_ADVERTISE << 16 | ADVERTISE_100FULL | | |
993 | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF; | |
994 | /* enable PAUSE frames */ | |
995 | val |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
996 | /* required by the Cicada PHY */ | |
997 | val |= ADVERTISE_CSMA; | |
998 | slic_write(sdev, SLIC_REG_WPHY, val); | |
999 | ||
1000 | /* advertise FD only @1000 Mb */ | |
1001 | val = MII_CTRL1000 << 16 | ADVERTISE_1000FULL; | |
1002 | slic_write(sdev, SLIC_REG_WPHY, val); | |
1003 | ||
1004 | if (subid != PCI_SUBDEVICE_ID_ALACRITECH_CICADA) { | |
1005 | /* if a Marvell PHY enable auto crossover */ | |
1006 | val = SLIC_MIICR_REG_16 | SLIC_MRV_REG16_XOVERON; | |
1007 | slic_write(sdev, SLIC_REG_WPHY, val); | |
1008 | ||
1009 | /* reset phy, enable auto-neg */ | |
1010 | val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE | | |
1011 | BMCR_ANRESTART; | |
1012 | slic_write(sdev, SLIC_REG_WPHY, val); | |
1013 | } else { | |
1014 | /* enable and restart auto-neg (don't reset) */ | |
1015 | val = MII_BMCR << 16 | BMCR_ANENABLE | BMCR_ANRESTART; | |
1016 | slic_write(sdev, SLIC_REG_WPHY, val); | |
1017 | } | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | static void slic_set_mac_address(struct slic_device *sdev) | |
1022 | { | |
1023 | u8 *addr = sdev->netdev->dev_addr; | |
1024 | u32 val; | |
1025 | ||
1026 | val = addr[5] | addr[4] << 8 | addr[3] << 16 | addr[2] << 24; | |
1027 | ||
1028 | slic_write(sdev, SLIC_REG_WRADDRAL, val); | |
1029 | slic_write(sdev, SLIC_REG_WRADDRBL, val); | |
1030 | ||
1031 | val = addr[0] << 8 | addr[1]; | |
1032 | ||
1033 | slic_write(sdev, SLIC_REG_WRADDRAH, val); | |
1034 | slic_write(sdev, SLIC_REG_WRADDRBH, val); | |
1035 | slic_flush_write(sdev); | |
1036 | } | |
1037 | ||
1038 | static u32 slic_read_dword_from_firmware(const struct firmware *fw, int *offset) | |
1039 | { | |
1040 | int idx = *offset; | |
1041 | __le32 val; | |
1042 | ||
1043 | memcpy(&val, fw->data + *offset, sizeof(val)); | |
1044 | idx += 4; | |
1045 | *offset = idx; | |
1046 | ||
1047 | return le32_to_cpu(val); | |
1048 | } | |
1049 | ||
1050 | MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_MOJAVE); | |
1051 | MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_OASIS); | |
1052 | ||
1053 | static int slic_load_rcvseq_firmware(struct slic_device *sdev) | |
1054 | { | |
1055 | const struct firmware *fw; | |
1056 | const char *file; | |
1057 | u32 codelen; | |
1058 | int idx = 0; | |
1059 | u32 instr; | |
1060 | u32 addr; | |
1061 | int err; | |
1062 | ||
1063 | file = (sdev->model == SLIC_MODEL_OASIS) ? SLIC_RCV_FIRMWARE_OASIS : | |
1064 | SLIC_RCV_FIRMWARE_MOJAVE; | |
1065 | err = request_firmware(&fw, file, &sdev->pdev->dev); | |
1066 | if (err) { | |
1067 | dev_err(&sdev->pdev->dev, | |
1068 | "failed to load receive sequencer firmware %s\n", file); | |
1069 | return err; | |
1070 | } | |
1071 | /* Do an initial sanity check concerning firmware size now. A further | |
1072 | * check follows below. | |
1073 | */ | |
1074 | if (fw->size < SLIC_FIRMWARE_MIN_SIZE) { | |
1075 | dev_err(&sdev->pdev->dev, | |
1076 | "invalid firmware size %zu (min %u expected)\n", | |
1077 | fw->size, SLIC_FIRMWARE_MIN_SIZE); | |
1078 | err = -EINVAL; | |
1079 | goto release; | |
1080 | } | |
1081 | ||
1082 | codelen = slic_read_dword_from_firmware(fw, &idx); | |
1083 | ||
1084 | /* do another sanity check against firmware size */ | |
1085 | if ((codelen + 4) > fw->size) { | |
1086 | dev_err(&sdev->pdev->dev, | |
1087 | "invalid rcv-sequencer firmware size %zu\n", fw->size); | |
1088 | err = -EINVAL; | |
1089 | goto release; | |
1090 | } | |
1091 | ||
1092 | /* download sequencer code to card */ | |
1093 | slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_BEGIN); | |
1094 | for (addr = 0; addr < codelen; addr++) { | |
1095 | __le32 val; | |
1096 | /* write out instruction address */ | |
1097 | slic_write(sdev, SLIC_REG_RCV_WCS, addr); | |
1098 | ||
1099 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1100 | /* write out the instruction data low addr */ | |
1101 | slic_write(sdev, SLIC_REG_RCV_WCS, instr); | |
1102 | ||
1103 | val = (__le32)fw->data[idx]; | |
1104 | instr = le32_to_cpu(val); | |
1105 | idx++; | |
1106 | /* write out the instruction data high addr */ | |
1107 | slic_write(sdev, SLIC_REG_RCV_WCS, instr); | |
1108 | } | |
1109 | /* finish download */ | |
1110 | slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_FINISH); | |
1111 | slic_flush_write(sdev); | |
1112 | release: | |
1113 | release_firmware(fw); | |
1114 | ||
1115 | return err; | |
1116 | } | |
1117 | ||
1118 | MODULE_FIRMWARE(SLIC_FIRMWARE_MOJAVE); | |
1119 | MODULE_FIRMWARE(SLIC_FIRMWARE_OASIS); | |
1120 | ||
1121 | static int slic_load_firmware(struct slic_device *sdev) | |
1122 | { | |
1123 | u32 sectstart[SLIC_FIRMWARE_MAX_SECTIONS]; | |
1124 | u32 sectsize[SLIC_FIRMWARE_MAX_SECTIONS]; | |
1125 | const struct firmware *fw; | |
1126 | unsigned int datalen; | |
1127 | const char *file; | |
1128 | int code_start; | |
1129 | unsigned int i; | |
1130 | u32 numsects; | |
1131 | int idx = 0; | |
1132 | u32 sect; | |
1133 | u32 instr; | |
1134 | u32 addr; | |
1135 | u32 base; | |
1136 | int err; | |
1137 | ||
1138 | file = (sdev->model == SLIC_MODEL_OASIS) ? SLIC_FIRMWARE_OASIS : | |
1139 | SLIC_FIRMWARE_MOJAVE; | |
1140 | err = request_firmware(&fw, file, &sdev->pdev->dev); | |
1141 | if (err) { | |
1142 | dev_err(&sdev->pdev->dev, "failed to load firmware %s\n", file); | |
1143 | return err; | |
1144 | } | |
1145 | /* Do an initial sanity check concerning firmware size now. A further | |
1146 | * check follows below. | |
1147 | */ | |
1148 | if (fw->size < SLIC_FIRMWARE_MIN_SIZE) { | |
1149 | dev_err(&sdev->pdev->dev, | |
1150 | "invalid firmware size %zu (min is %u)\n", fw->size, | |
1151 | SLIC_FIRMWARE_MIN_SIZE); | |
1152 | err = -EINVAL; | |
1153 | goto release; | |
1154 | } | |
1155 | ||
1156 | numsects = slic_read_dword_from_firmware(fw, &idx); | |
1157 | if (numsects == 0 || numsects > SLIC_FIRMWARE_MAX_SECTIONS) { | |
1158 | dev_err(&sdev->pdev->dev, | |
1159 | "invalid number of sections in firmware: %u", numsects); | |
1160 | err = -EINVAL; | |
1161 | goto release; | |
1162 | } | |
1163 | ||
1164 | datalen = numsects * 8 + 4; | |
1165 | for (i = 0; i < numsects; i++) { | |
1166 | sectsize[i] = slic_read_dword_from_firmware(fw, &idx); | |
1167 | datalen += sectsize[i]; | |
1168 | } | |
1169 | ||
1170 | /* do another sanity check against firmware size */ | |
1171 | if (datalen > fw->size) { | |
1172 | dev_err(&sdev->pdev->dev, | |
1173 | "invalid firmware size %zu (expected >= %u)\n", | |
1174 | fw->size, datalen); | |
1175 | err = -EINVAL; | |
1176 | goto release; | |
1177 | } | |
1178 | /* get sections */ | |
1179 | for (i = 0; i < numsects; i++) | |
1180 | sectstart[i] = slic_read_dword_from_firmware(fw, &idx); | |
1181 | ||
1182 | code_start = idx; | |
1183 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1184 | ||
1185 | for (sect = 0; sect < numsects; sect++) { | |
1186 | unsigned int ssize = sectsize[sect] >> 3; | |
1187 | ||
1188 | base = sectstart[sect]; | |
1189 | ||
1190 | for (addr = 0; addr < ssize; addr++) { | |
1191 | /* write out instruction address */ | |
1192 | slic_write(sdev, SLIC_REG_WCS, base + addr); | |
1193 | /* write out instruction to low addr */ | |
1194 | slic_write(sdev, SLIC_REG_WCS, instr); | |
1195 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1196 | /* write out instruction to high addr */ | |
1197 | slic_write(sdev, SLIC_REG_WCS, instr); | |
1198 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | idx = code_start; | |
1203 | ||
1204 | for (sect = 0; sect < numsects; sect++) { | |
1205 | unsigned int ssize = sectsize[sect] >> 3; | |
1206 | ||
1207 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1208 | base = sectstart[sect]; | |
1209 | if (base < 0x8000) | |
1210 | continue; | |
1211 | ||
1212 | for (addr = 0; addr < ssize; addr++) { | |
1213 | /* write out instruction address */ | |
1214 | slic_write(sdev, SLIC_REG_WCS, | |
1215 | SLIC_WCS_COMPARE | (base + addr)); | |
1216 | /* write out instruction to low addr */ | |
1217 | slic_write(sdev, SLIC_REG_WCS, instr); | |
1218 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1219 | /* write out instruction to high addr */ | |
1220 | slic_write(sdev, SLIC_REG_WCS, instr); | |
1221 | instr = slic_read_dword_from_firmware(fw, &idx); | |
1222 | } | |
1223 | } | |
1224 | slic_flush_write(sdev); | |
1225 | mdelay(10); | |
1226 | /* everything OK, kick off the card */ | |
1227 | slic_write(sdev, SLIC_REG_WCS, SLIC_WCS_START); | |
1228 | slic_flush_write(sdev); | |
1229 | /* wait long enough for ucode to init card and reach the mainloop */ | |
1230 | mdelay(20); | |
1231 | release: | |
1232 | release_firmware(fw); | |
1233 | ||
1234 | return err; | |
1235 | } | |
1236 | ||
1237 | static int slic_init_shmem(struct slic_device *sdev) | |
1238 | { | |
1239 | struct slic_shmem *sm = &sdev->shmem; | |
1240 | struct slic_shmem_data *sm_data; | |
1241 | dma_addr_t paddr; | |
1242 | ||
750afb08 LC |
1243 | sm_data = dma_alloc_coherent(&sdev->pdev->dev, sizeof(*sm_data), |
1244 | &paddr, GFP_KERNEL); | |
60c140df LS |
1245 | if (!sm_data) { |
1246 | dev_err(&sdev->pdev->dev, "failed to allocate shared memory\n"); | |
1247 | return -ENOMEM; | |
1248 | } | |
1249 | ||
1250 | sm->shmem_data = sm_data; | |
1251 | sm->isr_paddr = paddr; | |
1252 | sm->link_paddr = paddr + offsetof(struct slic_shmem_data, link); | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static void slic_free_shmem(struct slic_device *sdev) | |
1258 | { | |
1259 | struct slic_shmem *sm = &sdev->shmem; | |
1260 | struct slic_shmem_data *sm_data = sm->shmem_data; | |
1261 | ||
1262 | dma_free_coherent(&sdev->pdev->dev, sizeof(*sm_data), sm_data, | |
1263 | sm->isr_paddr); | |
1264 | } | |
1265 | ||
1266 | static int slic_init_iface(struct slic_device *sdev) | |
1267 | { | |
1268 | struct slic_shmem *sm = &sdev->shmem; | |
1269 | int err; | |
1270 | ||
1271 | sdev->upr_list.pending = false; | |
1272 | ||
1273 | err = slic_init_shmem(sdev); | |
1274 | if (err) { | |
1275 | netdev_err(sdev->netdev, "failed to init shared memory\n"); | |
1276 | return err; | |
1277 | } | |
1278 | ||
1279 | err = slic_load_firmware(sdev); | |
1280 | if (err) { | |
1281 | netdev_err(sdev->netdev, "failed to load firmware\n"); | |
1282 | goto free_sm; | |
1283 | } | |
1284 | ||
1285 | err = slic_load_rcvseq_firmware(sdev); | |
1286 | if (err) { | |
1287 | netdev_err(sdev->netdev, | |
1288 | "failed to load firmware for receive sequencer\n"); | |
1289 | goto free_sm; | |
1290 | } | |
1291 | ||
1292 | slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF); | |
1293 | slic_flush_write(sdev); | |
1294 | mdelay(1); | |
1295 | ||
1296 | err = slic_init_rx_queue(sdev); | |
1297 | if (err) { | |
1298 | netdev_err(sdev->netdev, "failed to init rx queue: %u\n", err); | |
1299 | goto free_sm; | |
1300 | } | |
1301 | ||
1302 | err = slic_init_tx_queue(sdev); | |
1303 | if (err) { | |
1304 | netdev_err(sdev->netdev, "failed to init tx queue: %u\n", err); | |
1305 | goto free_rxq; | |
1306 | } | |
1307 | ||
1308 | err = slic_init_stat_queue(sdev); | |
1309 | if (err) { | |
1310 | netdev_err(sdev->netdev, "failed to init status queue: %u\n", | |
1311 | err); | |
1312 | goto free_txq; | |
1313 | } | |
1314 | ||
1315 | slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr)); | |
1316 | napi_enable(&sdev->napi); | |
1317 | /* disable irq mitigation */ | |
1318 | slic_write(sdev, SLIC_REG_INTAGG, 0); | |
1319 | slic_write(sdev, SLIC_REG_ISR, 0); | |
1320 | slic_flush_write(sdev); | |
1321 | ||
1322 | slic_set_mac_address(sdev); | |
1323 | ||
1324 | spin_lock_bh(&sdev->link_lock); | |
1325 | sdev->duplex = DUPLEX_UNKNOWN; | |
1326 | sdev->speed = SPEED_UNKNOWN; | |
1327 | spin_unlock_bh(&sdev->link_lock); | |
1328 | ||
1329 | slic_set_link_autoneg(sdev); | |
1330 | ||
1331 | err = request_irq(sdev->pdev->irq, slic_irq, IRQF_SHARED, DRV_NAME, | |
1332 | sdev); | |
1333 | if (err) { | |
1334 | netdev_err(sdev->netdev, "failed to request irq: %u\n", err); | |
1335 | goto disable_napi; | |
1336 | } | |
1337 | ||
1338 | slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_ON); | |
1339 | slic_flush_write(sdev); | |
1340 | /* request initial link status */ | |
1341 | err = slic_handle_link_change(sdev); | |
1342 | if (err) | |
1343 | netdev_warn(sdev->netdev, | |
1344 | "failed to set initial link state: %u\n", err); | |
1345 | return 0; | |
1346 | ||
1347 | disable_napi: | |
1348 | napi_disable(&sdev->napi); | |
1349 | slic_free_stat_queue(sdev); | |
1350 | free_txq: | |
1351 | slic_free_tx_queue(sdev); | |
1352 | free_rxq: | |
1353 | slic_free_rx_queue(sdev); | |
1354 | free_sm: | |
1355 | slic_free_shmem(sdev); | |
1356 | slic_card_reset(sdev); | |
1357 | ||
1358 | return err; | |
1359 | } | |
1360 | ||
1361 | static int slic_open(struct net_device *dev) | |
1362 | { | |
1363 | struct slic_device *sdev = netdev_priv(dev); | |
1364 | int err; | |
1365 | ||
1366 | netif_carrier_off(dev); | |
1367 | ||
1368 | err = slic_init_iface(sdev); | |
1369 | if (err) { | |
1370 | netdev_err(dev, "failed to initialize interface: %i\n", err); | |
1371 | return err; | |
1372 | } | |
1373 | ||
1374 | netif_start_queue(dev); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | static int slic_close(struct net_device *dev) | |
1380 | { | |
1381 | struct slic_device *sdev = netdev_priv(dev); | |
1382 | u32 val; | |
1383 | ||
1384 | netif_stop_queue(dev); | |
1385 | ||
1386 | /* stop irq handling */ | |
1387 | napi_disable(&sdev->napi); | |
1388 | slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF); | |
1389 | slic_write(sdev, SLIC_REG_ISR, 0); | |
1390 | slic_flush_write(sdev); | |
1391 | ||
1392 | free_irq(sdev->pdev->irq, sdev); | |
1393 | /* turn off RCV and XMT and power down PHY */ | |
1394 | val = SLIC_GXCR_RESET | SLIC_GXCR_PAUSEEN; | |
1395 | slic_write(sdev, SLIC_REG_WXCFG, val); | |
1396 | ||
1397 | val = SLIC_GRCR_RESET | SLIC_GRCR_CTLEN | SLIC_GRCR_ADDRAEN | | |
1398 | SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT; | |
1399 | slic_write(sdev, SLIC_REG_WRCFG, val); | |
1400 | ||
1401 | val = MII_BMCR << 16 | BMCR_PDOWN; | |
1402 | slic_write(sdev, SLIC_REG_WPHY, val); | |
1403 | slic_flush_write(sdev); | |
1404 | ||
1405 | slic_clear_upr_list(&sdev->upr_list); | |
1406 | slic_write(sdev, SLIC_REG_QUIESCE, 0); | |
1407 | ||
1408 | slic_free_stat_queue(sdev); | |
1409 | slic_free_tx_queue(sdev); | |
1410 | slic_free_rx_queue(sdev); | |
1411 | slic_free_shmem(sdev); | |
1412 | ||
1413 | slic_card_reset(sdev); | |
1414 | netif_carrier_off(dev); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static netdev_tx_t slic_xmit(struct sk_buff *skb, struct net_device *dev) | |
1420 | { | |
1421 | struct slic_device *sdev = netdev_priv(dev); | |
1422 | struct slic_tx_queue *txq = &sdev->txq; | |
1423 | struct slic_tx_buffer *buff; | |
1424 | struct slic_tx_desc *desc; | |
1425 | dma_addr_t paddr; | |
1426 | u32 cbar_val; | |
1427 | u32 maplen; | |
1428 | ||
1429 | if (unlikely(slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS)) { | |
1430 | netdev_err(dev, "BUG! not enough tx LEs left: %u\n", | |
1431 | slic_get_free_tx_descs(txq)); | |
1432 | return NETDEV_TX_BUSY; | |
1433 | } | |
1434 | ||
1435 | maplen = skb_headlen(skb); | |
1436 | paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen, | |
1437 | DMA_TO_DEVICE); | |
1438 | if (dma_mapping_error(&sdev->pdev->dev, paddr)) { | |
1439 | netdev_err(dev, "failed to map tx buffer\n"); | |
1440 | goto drop_skb; | |
1441 | } | |
1442 | ||
1443 | buff = &txq->txbuffs[txq->put_idx]; | |
1444 | buff->skb = skb; | |
1445 | dma_unmap_addr_set(buff, map_addr, paddr); | |
1446 | dma_unmap_len_set(buff, map_len, maplen); | |
1447 | ||
1448 | desc = buff->desc; | |
1449 | desc->totlen = cpu_to_le32(maplen); | |
1450 | desc->paddrl = cpu_to_le32(lower_32_bits(paddr)); | |
1451 | desc->paddrh = cpu_to_le32(upper_32_bits(paddr)); | |
1452 | desc->len = cpu_to_le32(maplen); | |
1453 | ||
1454 | txq->put_idx = slic_next_queue_idx(txq->put_idx, txq->len); | |
1455 | ||
1456 | cbar_val = lower_32_bits(buff->desc_paddr) | 1; | |
1457 | /* complete writes to RAM and DMA before hardware is informed */ | |
1458 | wmb(); | |
1459 | ||
1460 | slic_write(sdev, SLIC_REG_CBAR, cbar_val); | |
1461 | ||
1462 | if (slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS) | |
1463 | netif_stop_queue(dev); | |
1464 | /* make sure writes to io-memory cant leak out of tx queue lock */ | |
1465 | mmiowb(); | |
1466 | ||
1467 | return NETDEV_TX_OK; | |
1468 | drop_skb: | |
1469 | dev_kfree_skb_any(skb); | |
1470 | ||
1471 | return NETDEV_TX_OK; | |
1472 | } | |
1473 | ||
bc1f4470 | 1474 | static void slic_get_stats(struct net_device *dev, |
1475 | struct rtnl_link_stats64 *lst) | |
60c140df LS |
1476 | { |
1477 | struct slic_device *sdev = netdev_priv(dev); | |
1478 | struct slic_stats *stats = &sdev->stats; | |
1479 | ||
1480 | SLIC_GET_STATS_COUNTER(lst->rx_packets, stats, rx_packets); | |
1481 | SLIC_GET_STATS_COUNTER(lst->tx_packets, stats, tx_packets); | |
1482 | SLIC_GET_STATS_COUNTER(lst->rx_bytes, stats, rx_bytes); | |
1483 | SLIC_GET_STATS_COUNTER(lst->tx_bytes, stats, tx_bytes); | |
1484 | SLIC_GET_STATS_COUNTER(lst->rx_errors, stats, rx_errors); | |
1485 | SLIC_GET_STATS_COUNTER(lst->rx_dropped, stats, rx_buff_miss); | |
1486 | SLIC_GET_STATS_COUNTER(lst->tx_dropped, stats, tx_dropped); | |
1487 | SLIC_GET_STATS_COUNTER(lst->multicast, stats, rx_mcasts); | |
1488 | SLIC_GET_STATS_COUNTER(lst->rx_over_errors, stats, rx_buffoflow); | |
1489 | SLIC_GET_STATS_COUNTER(lst->rx_crc_errors, stats, rx_crc); | |
1490 | SLIC_GET_STATS_COUNTER(lst->rx_fifo_errors, stats, rx_oflow802); | |
1491 | SLIC_GET_STATS_COUNTER(lst->tx_carrier_errors, stats, tx_carrier); | |
60c140df LS |
1492 | } |
1493 | ||
1494 | static int slic_get_sset_count(struct net_device *dev, int sset) | |
1495 | { | |
1496 | switch (sset) { | |
1497 | case ETH_SS_STATS: | |
1498 | return ARRAY_SIZE(slic_stats_strings); | |
1499 | default: | |
1500 | return -EOPNOTSUPP; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | static void slic_get_ethtool_stats(struct net_device *dev, | |
1505 | struct ethtool_stats *eth_stats, u64 *data) | |
1506 | { | |
1507 | struct slic_device *sdev = netdev_priv(dev); | |
1508 | struct slic_stats *stats = &sdev->stats; | |
1509 | ||
1510 | SLIC_GET_STATS_COUNTER(data[0], stats, rx_packets); | |
1511 | SLIC_GET_STATS_COUNTER(data[1], stats, rx_bytes); | |
1512 | SLIC_GET_STATS_COUNTER(data[2], stats, rx_mcasts); | |
1513 | SLIC_GET_STATS_COUNTER(data[3], stats, rx_errors); | |
1514 | SLIC_GET_STATS_COUNTER(data[4], stats, rx_buff_miss); | |
1515 | SLIC_GET_STATS_COUNTER(data[5], stats, rx_tpcsum); | |
1516 | SLIC_GET_STATS_COUNTER(data[6], stats, rx_tpoflow); | |
1517 | SLIC_GET_STATS_COUNTER(data[7], stats, rx_tphlen); | |
1518 | SLIC_GET_STATS_COUNTER(data[8], stats, rx_ipcsum); | |
1519 | SLIC_GET_STATS_COUNTER(data[9], stats, rx_iplen); | |
1520 | SLIC_GET_STATS_COUNTER(data[10], stats, rx_iphlen); | |
1521 | SLIC_GET_STATS_COUNTER(data[11], stats, rx_early); | |
1522 | SLIC_GET_STATS_COUNTER(data[12], stats, rx_buffoflow); | |
1523 | SLIC_GET_STATS_COUNTER(data[13], stats, rx_lcode); | |
1524 | SLIC_GET_STATS_COUNTER(data[14], stats, rx_drbl); | |
1525 | SLIC_GET_STATS_COUNTER(data[15], stats, rx_crc); | |
1526 | SLIC_GET_STATS_COUNTER(data[16], stats, rx_oflow802); | |
1527 | SLIC_GET_STATS_COUNTER(data[17], stats, rx_uflow802); | |
1528 | SLIC_GET_STATS_COUNTER(data[18], stats, tx_packets); | |
1529 | SLIC_GET_STATS_COUNTER(data[19], stats, tx_bytes); | |
1530 | SLIC_GET_STATS_COUNTER(data[20], stats, tx_carrier); | |
1531 | SLIC_GET_STATS_COUNTER(data[21], stats, tx_dropped); | |
1532 | SLIC_GET_STATS_COUNTER(data[22], stats, irq_errs); | |
1533 | } | |
1534 | ||
1535 | static void slic_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
1536 | { | |
1537 | if (stringset == ETH_SS_STATS) { | |
1538 | memcpy(data, slic_stats_strings, sizeof(slic_stats_strings)); | |
1539 | data += sizeof(slic_stats_strings); | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | static void slic_get_drvinfo(struct net_device *dev, | |
1544 | struct ethtool_drvinfo *info) | |
1545 | { | |
1546 | struct slic_device *sdev = netdev_priv(dev); | |
1547 | ||
1548 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | |
1549 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1550 | strlcpy(info->bus_info, pci_name(sdev->pdev), sizeof(info->bus_info)); | |
1551 | } | |
1552 | ||
1553 | static const struct ethtool_ops slic_ethtool_ops = { | |
1554 | .get_drvinfo = slic_get_drvinfo, | |
1555 | .get_link = ethtool_op_get_link, | |
1556 | .get_strings = slic_get_strings, | |
1557 | .get_ethtool_stats = slic_get_ethtool_stats, | |
1558 | .get_sset_count = slic_get_sset_count, | |
1559 | }; | |
1560 | ||
1561 | static const struct net_device_ops slic_netdev_ops = { | |
1562 | .ndo_open = slic_open, | |
1563 | .ndo_stop = slic_close, | |
1564 | .ndo_start_xmit = slic_xmit, | |
1565 | .ndo_set_mac_address = eth_mac_addr, | |
1566 | .ndo_get_stats64 = slic_get_stats, | |
1567 | .ndo_set_rx_mode = slic_set_rx_mode, | |
60c140df LS |
1568 | .ndo_validate_addr = eth_validate_addr, |
1569 | }; | |
1570 | ||
1571 | static u16 slic_eeprom_csum(unsigned char *eeprom, unsigned int len) | |
1572 | { | |
1573 | unsigned char *ptr = eeprom; | |
1574 | u32 csum = 0; | |
1575 | __le16 data; | |
1576 | ||
1577 | while (len > 1) { | |
1578 | memcpy(&data, ptr, sizeof(data)); | |
1579 | csum += le16_to_cpu(data); | |
1580 | ptr += 2; | |
1581 | len -= 2; | |
1582 | } | |
1583 | if (len > 0) | |
1584 | csum += *(u8 *)ptr; | |
1585 | while (csum >> 16) | |
1586 | csum = (csum & 0xFFFF) + ((csum >> 16) & 0xFFFF); | |
1587 | return ~csum; | |
1588 | } | |
1589 | ||
1590 | /* check eeprom size, magic and checksum */ | |
1591 | static bool slic_eeprom_valid(unsigned char *eeprom, unsigned int size) | |
1592 | { | |
1593 | const unsigned int MAX_SIZE = 128; | |
1594 | const unsigned int MIN_SIZE = 98; | |
1595 | __le16 magic; | |
1596 | __le16 csum; | |
1597 | ||
1598 | if (size < MIN_SIZE || size > MAX_SIZE) | |
1599 | return false; | |
1600 | memcpy(&magic, eeprom, sizeof(magic)); | |
1601 | if (le16_to_cpu(magic) != SLIC_EEPROM_MAGIC) | |
1602 | return false; | |
1603 | /* cut checksum bytes */ | |
1604 | size -= 2; | |
1605 | memcpy(&csum, eeprom + size, sizeof(csum)); | |
1606 | ||
1607 | return (le16_to_cpu(csum) == slic_eeprom_csum(eeprom, size)); | |
1608 | } | |
1609 | ||
1610 | static int slic_read_eeprom(struct slic_device *sdev) | |
1611 | { | |
1612 | unsigned int devfn = PCI_FUNC(sdev->pdev->devfn); | |
1613 | struct slic_shmem *sm = &sdev->shmem; | |
1614 | struct slic_shmem_data *sm_data = sm->shmem_data; | |
1615 | const unsigned int MAX_LOOPS = 5000; | |
1616 | unsigned int codesize; | |
1617 | unsigned char *eeprom; | |
1618 | struct slic_upr *upr; | |
1619 | unsigned int i = 0; | |
1620 | dma_addr_t paddr; | |
1621 | int err = 0; | |
1622 | u8 *mac[2]; | |
1623 | ||
750afb08 LC |
1624 | eeprom = dma_alloc_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE, |
1625 | &paddr, GFP_KERNEL); | |
60c140df LS |
1626 | if (!eeprom) |
1627 | return -ENOMEM; | |
1628 | ||
1629 | slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF); | |
1630 | /* setup ISP temporarily */ | |
1631 | slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr)); | |
1632 | ||
1633 | err = slic_new_upr(sdev, SLIC_UPR_CONFIG, paddr); | |
1634 | if (!err) { | |
1635 | for (i = 0; i < MAX_LOOPS; i++) { | |
1636 | if (le32_to_cpu(sm_data->isr) & SLIC_ISR_UPC) | |
1637 | break; | |
1638 | mdelay(1); | |
1639 | } | |
1640 | if (i == MAX_LOOPS) { | |
1641 | dev_err(&sdev->pdev->dev, | |
1642 | "timed out while waiting for eeprom data\n"); | |
1643 | err = -ETIMEDOUT; | |
1644 | } | |
1645 | upr = slic_dequeue_upr(sdev); | |
1646 | kfree(upr); | |
1647 | } | |
1648 | ||
1649 | slic_write(sdev, SLIC_REG_ISP, 0); | |
1650 | slic_write(sdev, SLIC_REG_ISR, 0); | |
1651 | slic_flush_write(sdev); | |
1652 | ||
1653 | if (err) | |
1654 | goto free_eeprom; | |
1655 | ||
1656 | if (sdev->model == SLIC_MODEL_OASIS) { | |
1657 | struct slic_oasis_eeprom *oee; | |
1658 | ||
1659 | oee = (struct slic_oasis_eeprom *)eeprom; | |
1660 | mac[0] = oee->mac; | |
1661 | mac[1] = oee->mac2; | |
1662 | codesize = le16_to_cpu(oee->eeprom_code_size); | |
1663 | } else { | |
1664 | struct slic_mojave_eeprom *mee; | |
1665 | ||
1666 | mee = (struct slic_mojave_eeprom *)eeprom; | |
1667 | mac[0] = mee->mac; | |
1668 | mac[1] = mee->mac2; | |
1669 | codesize = le16_to_cpu(mee->eeprom_code_size); | |
1670 | } | |
1671 | ||
1672 | if (!slic_eeprom_valid(eeprom, codesize)) { | |
1673 | dev_err(&sdev->pdev->dev, "invalid checksum in eeprom\n"); | |
1674 | err = -EINVAL; | |
1675 | goto free_eeprom; | |
1676 | } | |
1677 | /* set mac address */ | |
1678 | ether_addr_copy(sdev->netdev->dev_addr, mac[devfn]); | |
1679 | free_eeprom: | |
1680 | dma_free_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE, eeprom, paddr); | |
1681 | ||
1682 | return err; | |
1683 | } | |
1684 | ||
1685 | static int slic_init(struct slic_device *sdev) | |
1686 | { | |
1687 | int err; | |
1688 | ||
1689 | spin_lock_init(&sdev->upper_lock); | |
1690 | spin_lock_init(&sdev->link_lock); | |
1691 | INIT_LIST_HEAD(&sdev->upr_list.list); | |
1692 | spin_lock_init(&sdev->upr_list.lock); | |
1693 | u64_stats_init(&sdev->stats.syncp); | |
1694 | ||
1695 | slic_card_reset(sdev); | |
1696 | ||
1697 | err = slic_load_firmware(sdev); | |
1698 | if (err) { | |
1699 | dev_err(&sdev->pdev->dev, "failed to load firmware\n"); | |
1700 | return err; | |
1701 | } | |
1702 | ||
1703 | /* we need the shared memory to read EEPROM so set it up temporarily */ | |
1704 | err = slic_init_shmem(sdev); | |
1705 | if (err) { | |
1706 | dev_err(&sdev->pdev->dev, "failed to init shared memory\n"); | |
1707 | return err; | |
1708 | } | |
1709 | ||
1710 | err = slic_read_eeprom(sdev); | |
1711 | if (err) { | |
1712 | dev_err(&sdev->pdev->dev, "failed to read eeprom\n"); | |
1713 | goto free_sm; | |
1714 | } | |
1715 | ||
1716 | slic_card_reset(sdev); | |
1717 | slic_free_shmem(sdev); | |
1718 | ||
1719 | return 0; | |
1720 | free_sm: | |
1721 | slic_free_shmem(sdev); | |
1722 | ||
1723 | return err; | |
1724 | } | |
1725 | ||
1726 | static bool slic_is_fiber(unsigned short subdev) | |
1727 | { | |
1728 | switch (subdev) { | |
1729 | /* Mojave */ | |
1730 | case PCI_SUBDEVICE_ID_ALACRITECH_1000X1F: /* fallthrough */ | |
1731 | case PCI_SUBDEVICE_ID_ALACRITECH_SES1001F: /* fallthrough */ | |
1732 | /* Oasis */ | |
1733 | case PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF: /* fallthrough */ | |
1734 | case PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF: /* fallthrough */ | |
1735 | case PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF: /* fallthrough */ | |
1736 | case PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF: /* fallthrough */ | |
1737 | return true; | |
1738 | } | |
1739 | return false; | |
1740 | } | |
1741 | ||
1742 | static void slic_configure_pci(struct pci_dev *pdev) | |
1743 | { | |
1744 | u16 old; | |
1745 | u16 cmd; | |
1746 | ||
1747 | pci_read_config_word(pdev, PCI_COMMAND, &old); | |
1748 | ||
1749 | cmd = old | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
1750 | if (old != cmd) | |
1751 | pci_write_config_word(pdev, PCI_COMMAND, cmd); | |
1752 | } | |
1753 | ||
1754 | static int slic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1755 | { | |
1756 | struct slic_device *sdev; | |
1757 | struct net_device *dev; | |
1758 | int err; | |
1759 | ||
1760 | err = pci_enable_device(pdev); | |
1761 | if (err) { | |
1762 | dev_err(&pdev->dev, "failed to enable PCI device\n"); | |
1763 | return err; | |
1764 | } | |
1765 | ||
1766 | pci_set_master(pdev); | |
1767 | pci_try_set_mwi(pdev); | |
1768 | ||
1769 | slic_configure_pci(pdev); | |
1770 | ||
1771 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1772 | if (err) { | |
1773 | dev_err(&pdev->dev, "failed to setup DMA\n"); | |
1774 | goto disable; | |
1775 | } | |
1776 | ||
1777 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1778 | ||
1779 | err = pci_request_regions(pdev, DRV_NAME); | |
1780 | if (err) { | |
1781 | dev_err(&pdev->dev, "failed to obtain PCI regions\n"); | |
1782 | goto disable; | |
1783 | } | |
1784 | ||
1785 | dev = alloc_etherdev(sizeof(*sdev)); | |
1786 | if (!dev) { | |
1787 | dev_err(&pdev->dev, "failed to alloc ethernet device\n"); | |
1788 | err = -ENOMEM; | |
1789 | goto free_regions; | |
1790 | } | |
1791 | ||
1792 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1793 | pci_set_drvdata(pdev, dev); | |
1794 | dev->irq = pdev->irq; | |
1795 | dev->netdev_ops = &slic_netdev_ops; | |
1796 | dev->hw_features = NETIF_F_RXCSUM; | |
1797 | dev->features |= dev->hw_features; | |
1798 | ||
1799 | dev->ethtool_ops = &slic_ethtool_ops; | |
1800 | ||
1801 | sdev = netdev_priv(dev); | |
1802 | sdev->model = (pdev->device == PCI_DEVICE_ID_ALACRITECH_OASIS) ? | |
1803 | SLIC_MODEL_OASIS : SLIC_MODEL_MOJAVE; | |
1804 | sdev->is_fiber = slic_is_fiber(pdev->subsystem_device); | |
1805 | sdev->pdev = pdev; | |
1806 | sdev->netdev = dev; | |
1807 | sdev->regs = ioremap_nocache(pci_resource_start(pdev, 0), | |
1808 | pci_resource_len(pdev, 0)); | |
1809 | if (!sdev->regs) { | |
1810 | dev_err(&pdev->dev, "failed to map registers\n"); | |
1811 | err = -ENOMEM; | |
1812 | goto free_netdev; | |
1813 | } | |
1814 | ||
1815 | err = slic_init(sdev); | |
1816 | if (err) { | |
1817 | dev_err(&pdev->dev, "failed to initialize driver\n"); | |
1818 | goto unmap; | |
1819 | } | |
1820 | ||
1821 | netif_napi_add(dev, &sdev->napi, slic_poll, SLIC_NAPI_WEIGHT); | |
1822 | netif_carrier_off(dev); | |
1823 | ||
1824 | err = register_netdev(dev); | |
1825 | if (err) { | |
1826 | dev_err(&pdev->dev, "failed to register net device: %i\n", err); | |
1827 | goto unmap; | |
1828 | } | |
1829 | ||
1830 | return 0; | |
1831 | ||
1832 | unmap: | |
1833 | iounmap(sdev->regs); | |
1834 | free_netdev: | |
1835 | free_netdev(dev); | |
1836 | free_regions: | |
1837 | pci_release_regions(pdev); | |
1838 | disable: | |
1839 | pci_disable_device(pdev); | |
1840 | ||
1841 | return err; | |
1842 | } | |
1843 | ||
1844 | static void slic_remove(struct pci_dev *pdev) | |
1845 | { | |
1846 | struct net_device *dev = pci_get_drvdata(pdev); | |
1847 | struct slic_device *sdev = netdev_priv(dev); | |
1848 | ||
1849 | unregister_netdev(dev); | |
1850 | iounmap(sdev->regs); | |
1851 | free_netdev(dev); | |
1852 | pci_release_regions(pdev); | |
1853 | pci_disable_device(pdev); | |
1854 | } | |
1855 | ||
1856 | static struct pci_driver slic_driver = { | |
1857 | .name = DRV_NAME, | |
1858 | .id_table = slic_id_tbl, | |
1859 | .probe = slic_probe, | |
1860 | .remove = slic_remove, | |
1861 | }; | |
1862 | ||
3f0dd6b7 | 1863 | module_pci_driver(slic_driver); |
60c140df LS |
1864 | |
1865 | MODULE_DESCRIPTION("Alacritech non-accelerated SLIC driver"); | |
1866 | MODULE_AUTHOR("Lino Sanfilippo <LinoSanfilippo@gmx.de>"); | |
1867 | MODULE_LICENSE("GPL"); | |
1868 | MODULE_VERSION(DRV_VERSION); |