]>
Commit | Line | Data |
---|---|---|
49220505 SR |
1 | /* |
2 | * Allwinner EMAC Fast Ethernet driver for Linux. | |
3 | * | |
4 | * Copyright 2012-2013 Stefan Roese <sr@denx.de> | |
5 | * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> | |
6 | * | |
7 | * Based on the Linux driver provided by Allwinner: | |
8 | * Copyright (C) 1997 Sten Wang | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/gpio.h> | |
49220505 SR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/irq.h> | |
21 | #include <linux/mii.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/of_mdio.h> | |
27 | #include <linux/of_net.h> | |
28 | #include <linux/of_platform.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/phy.h> | |
542a64c7 | 31 | #include <linux/soc/sunxi/sunxi_sram.h> |
49220505 SR |
32 | |
33 | #include "sun4i-emac.h" | |
34 | ||
35 | #define DRV_NAME "sun4i-emac" | |
36 | #define DRV_VERSION "1.02" | |
37 | ||
38 | #define EMAC_MAX_FRAME_LEN 0x0600 | |
39 | ||
b8ca3387 MW |
40 | #define EMAC_DEFAULT_MSG_ENABLE 0x0000 |
41 | static int debug = -1; /* defaults above */; | |
42 | module_param(debug, int, 0); | |
43 | MODULE_PARM_DESC(debug, "debug message flags"); | |
44 | ||
49220505 SR |
45 | /* Transmit timeout, default 5 seconds. */ |
46 | static int watchdog = 5000; | |
47 | module_param(watchdog, int, 0400); | |
48 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
49 | ||
50 | /* EMAC register address locking. | |
51 | * | |
52 | * The EMAC uses an address register to control where data written | |
53 | * to the data register goes. This means that the address register | |
54 | * must be preserved over interrupts or similar calls. | |
55 | * | |
56 | * During interrupt and other critical calls, a spinlock is used to | |
57 | * protect the system, but the calls themselves save the address | |
58 | * in the address register in case they are interrupting another | |
59 | * access to the device. | |
60 | * | |
61 | * For general accesses a lock is provided so that calls which are | |
62 | * allowed to sleep are serialised so that the address register does | |
63 | * not need to be saved. This lock also serves to serialise access | |
64 | * to the EEPROM and PHY access registers which are shared between | |
65 | * these two devices. | |
66 | */ | |
67 | ||
68 | /* The driver supports the original EMACE, and now the two newer | |
69 | * devices, EMACA and EMACB. | |
70 | */ | |
71 | ||
72 | struct emac_board_info { | |
73 | struct clk *clk; | |
74 | struct device *dev; | |
75 | struct platform_device *pdev; | |
76 | spinlock_t lock; | |
77 | void __iomem *membase; | |
78 | u32 msg_enable; | |
79 | struct net_device *ndev; | |
80 | struct sk_buff *skb_last; | |
81 | u16 tx_fifo_stat; | |
82 | ||
83 | int emacrx_completed_flag; | |
84 | ||
49220505 SR |
85 | struct device_node *phy_node; |
86 | unsigned int link; | |
87 | unsigned int speed; | |
88 | unsigned int duplex; | |
89 | ||
90 | phy_interface_t phy_interface; | |
91 | }; | |
92 | ||
93 | static void emac_update_speed(struct net_device *dev) | |
94 | { | |
95 | struct emac_board_info *db = netdev_priv(dev); | |
96 | unsigned int reg_val; | |
97 | ||
98 | /* set EMAC SPEED, depend on PHY */ | |
99 | reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); | |
100 | reg_val &= ~(0x1 << 8); | |
101 | if (db->speed == SPEED_100) | |
102 | reg_val |= 1 << 8; | |
103 | writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); | |
104 | } | |
105 | ||
106 | static void emac_update_duplex(struct net_device *dev) | |
107 | { | |
108 | struct emac_board_info *db = netdev_priv(dev); | |
109 | unsigned int reg_val; | |
110 | ||
111 | /* set duplex depend on phy */ | |
112 | reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); | |
113 | reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; | |
114 | if (db->duplex) | |
115 | reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; | |
116 | writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); | |
117 | } | |
118 | ||
119 | static void emac_handle_link_change(struct net_device *dev) | |
120 | { | |
121 | struct emac_board_info *db = netdev_priv(dev); | |
5427ccaf | 122 | struct phy_device *phydev = dev->phydev; |
49220505 SR |
123 | unsigned long flags; |
124 | int status_change = 0; | |
125 | ||
126 | if (phydev->link) { | |
127 | if (db->speed != phydev->speed) { | |
128 | spin_lock_irqsave(&db->lock, flags); | |
129 | db->speed = phydev->speed; | |
130 | emac_update_speed(dev); | |
131 | spin_unlock_irqrestore(&db->lock, flags); | |
132 | status_change = 1; | |
133 | } | |
134 | ||
135 | if (db->duplex != phydev->duplex) { | |
136 | spin_lock_irqsave(&db->lock, flags); | |
137 | db->duplex = phydev->duplex; | |
138 | emac_update_duplex(dev); | |
139 | spin_unlock_irqrestore(&db->lock, flags); | |
140 | status_change = 1; | |
141 | } | |
142 | } | |
143 | ||
144 | if (phydev->link != db->link) { | |
145 | if (!phydev->link) { | |
146 | db->speed = 0; | |
147 | db->duplex = -1; | |
148 | } | |
149 | db->link = phydev->link; | |
150 | ||
151 | status_change = 1; | |
152 | } | |
153 | ||
154 | if (status_change) | |
155 | phy_print_status(phydev); | |
156 | } | |
157 | ||
158 | static int emac_mdio_probe(struct net_device *dev) | |
159 | { | |
160 | struct emac_board_info *db = netdev_priv(dev); | |
5427ccaf | 161 | struct phy_device *phydev; |
49220505 SR |
162 | |
163 | /* to-do: PHY interrupts are currently not supported */ | |
164 | ||
165 | /* attach the mac to the phy */ | |
5427ccaf PR |
166 | phydev = of_phy_connect(db->ndev, db->phy_node, |
167 | &emac_handle_link_change, 0, | |
168 | db->phy_interface); | |
169 | if (!phydev) { | |
49220505 SR |
170 | netdev_err(db->ndev, "could not find the PHY\n"); |
171 | return -ENODEV; | |
172 | } | |
173 | ||
174 | /* mask with MAC supported features */ | |
5427ccaf PR |
175 | phydev->supported &= PHY_BASIC_FEATURES; |
176 | phydev->advertising = phydev->supported; | |
49220505 SR |
177 | |
178 | db->link = 0; | |
179 | db->speed = 0; | |
180 | db->duplex = -1; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static void emac_mdio_remove(struct net_device *dev) | |
186 | { | |
5427ccaf | 187 | phy_disconnect(dev->phydev); |
49220505 SR |
188 | } |
189 | ||
190 | static void emac_reset(struct emac_board_info *db) | |
191 | { | |
192 | dev_dbg(db->dev, "resetting device\n"); | |
193 | ||
194 | /* RESET device */ | |
195 | writel(0, db->membase + EMAC_CTL_REG); | |
196 | udelay(200); | |
197 | writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); | |
198 | udelay(200); | |
199 | } | |
200 | ||
201 | static void emac_outblk_32bit(void __iomem *reg, void *data, int count) | |
202 | { | |
203 | writesl(reg, data, round_up(count, 4) / 4); | |
204 | } | |
205 | ||
206 | static void emac_inblk_32bit(void __iomem *reg, void *data, int count) | |
207 | { | |
208 | readsl(reg, data, round_up(count, 4) / 4); | |
209 | } | |
210 | ||
211 | static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
212 | { | |
5427ccaf | 213 | struct phy_device *phydev = dev->phydev; |
49220505 SR |
214 | |
215 | if (!netif_running(dev)) | |
216 | return -EINVAL; | |
217 | ||
218 | if (!phydev) | |
219 | return -ENODEV; | |
220 | ||
221 | return phy_mii_ioctl(phydev, rq, cmd); | |
222 | } | |
223 | ||
224 | /* ethtool ops */ | |
225 | static void emac_get_drvinfo(struct net_device *dev, | |
226 | struct ethtool_drvinfo *info) | |
227 | { | |
228 | strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME)); | |
229 | strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION)); | |
230 | strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); | |
231 | } | |
232 | ||
b8ca3387 MW |
233 | static u32 emac_get_msglevel(struct net_device *dev) |
234 | { | |
235 | struct emac_board_info *db = netdev_priv(dev); | |
236 | ||
237 | return db->msg_enable; | |
238 | } | |
239 | ||
240 | static void emac_set_msglevel(struct net_device *dev, u32 value) | |
241 | { | |
242 | struct emac_board_info *db = netdev_priv(dev); | |
243 | ||
244 | db->msg_enable = value; | |
245 | } | |
246 | ||
49220505 SR |
247 | static const struct ethtool_ops emac_ethtool_ops = { |
248 | .get_drvinfo = emac_get_drvinfo, | |
49220505 | 249 | .get_link = ethtool_op_get_link, |
91cd3b44 PR |
250 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
251 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
b8ca3387 MW |
252 | .get_msglevel = emac_get_msglevel, |
253 | .set_msglevel = emac_set_msglevel, | |
49220505 SR |
254 | }; |
255 | ||
11a164a0 | 256 | static unsigned int emac_setup(struct net_device *ndev) |
49220505 SR |
257 | { |
258 | struct emac_board_info *db = netdev_priv(ndev); | |
259 | unsigned int reg_val; | |
260 | ||
261 | /* set up TX */ | |
262 | reg_val = readl(db->membase + EMAC_TX_MODE_REG); | |
263 | ||
264 | writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, | |
265 | db->membase + EMAC_TX_MODE_REG); | |
266 | ||
49220505 SR |
267 | /* set MAC */ |
268 | /* set MAC CTL0 */ | |
269 | reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); | |
270 | writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | | |
271 | EMAC_MAC_CTL0_TX_FLOW_CTL_EN, | |
272 | db->membase + EMAC_MAC_CTL0_REG); | |
273 | ||
274 | /* set MAC CTL1 */ | |
275 | reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); | |
276 | reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; | |
277 | reg_val |= EMAC_MAC_CTL1_CRC_EN; | |
278 | reg_val |= EMAC_MAC_CTL1_PAD_EN; | |
279 | writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); | |
280 | ||
281 | /* set up IPGT */ | |
282 | writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); | |
283 | ||
284 | /* set up IPGR */ | |
285 | writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, | |
286 | db->membase + EMAC_MAC_IPGR_REG); | |
287 | ||
288 | /* set up Collison window */ | |
289 | writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, | |
290 | db->membase + EMAC_MAC_CLRT_REG); | |
291 | ||
292 | /* set up Max Frame Length */ | |
293 | writel(EMAC_MAX_FRAME_LEN, | |
294 | db->membase + EMAC_MAC_MAXF_REG); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
cec9ae50 MZ |
299 | static void emac_set_rx_mode(struct net_device *ndev) |
300 | { | |
301 | struct emac_board_info *db = netdev_priv(ndev); | |
302 | unsigned int reg_val; | |
303 | ||
304 | /* set up RX */ | |
305 | reg_val = readl(db->membase + EMAC_RX_CTL_REG); | |
306 | ||
307 | if (ndev->flags & IFF_PROMISC) | |
308 | reg_val |= EMAC_RX_CTL_PASS_ALL_EN; | |
309 | else | |
310 | reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN; | |
311 | ||
312 | writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | | |
313 | EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN | | |
314 | EMAC_RX_CTL_ACCEPT_MULTICAST_EN | | |
315 | EMAC_RX_CTL_ACCEPT_BROADCAST_EN, | |
316 | db->membase + EMAC_RX_CTL_REG); | |
317 | } | |
318 | ||
11a164a0 | 319 | static unsigned int emac_powerup(struct net_device *ndev) |
49220505 SR |
320 | { |
321 | struct emac_board_info *db = netdev_priv(ndev); | |
322 | unsigned int reg_val; | |
323 | ||
324 | /* initial EMAC */ | |
325 | /* flush RX FIFO */ | |
326 | reg_val = readl(db->membase + EMAC_RX_CTL_REG); | |
327 | reg_val |= 0x8; | |
328 | writel(reg_val, db->membase + EMAC_RX_CTL_REG); | |
329 | udelay(1); | |
330 | ||
331 | /* initial MAC */ | |
332 | /* soft reset MAC */ | |
333 | reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); | |
334 | reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; | |
335 | writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); | |
336 | ||
337 | /* set MII clock */ | |
338 | reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); | |
339 | reg_val &= (~(0xf << 2)); | |
340 | reg_val |= (0xD << 2); | |
341 | writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); | |
342 | ||
343 | /* clear RX counter */ | |
344 | writel(0x0, db->membase + EMAC_RX_FBC_REG); | |
345 | ||
346 | /* disable all interrupt and clear interrupt status */ | |
347 | writel(0, db->membase + EMAC_INT_CTL_REG); | |
348 | reg_val = readl(db->membase + EMAC_INT_STA_REG); | |
349 | writel(reg_val, db->membase + EMAC_INT_STA_REG); | |
350 | ||
351 | udelay(1); | |
352 | ||
353 | /* set up EMAC */ | |
354 | emac_setup(ndev); | |
355 | ||
356 | /* set mac_address to chip */ | |
357 | writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> | |
358 | dev_addr[2], db->membase + EMAC_MAC_A1_REG); | |
359 | writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> | |
360 | dev_addr[5], db->membase + EMAC_MAC_A0_REG); | |
361 | ||
362 | mdelay(1); | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static int emac_set_mac_address(struct net_device *dev, void *p) | |
368 | { | |
369 | struct sockaddr *addr = p; | |
370 | struct emac_board_info *db = netdev_priv(dev); | |
371 | ||
372 | if (netif_running(dev)) | |
373 | return -EBUSY; | |
374 | ||
375 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
376 | ||
377 | writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> | |
378 | dev_addr[2], db->membase + EMAC_MAC_A1_REG); | |
379 | writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> | |
380 | dev_addr[5], db->membase + EMAC_MAC_A0_REG); | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /* Initialize emac board */ | |
386 | static void emac_init_device(struct net_device *dev) | |
387 | { | |
388 | struct emac_board_info *db = netdev_priv(dev); | |
389 | unsigned long flags; | |
390 | unsigned int reg_val; | |
391 | ||
392 | spin_lock_irqsave(&db->lock, flags); | |
393 | ||
394 | emac_update_speed(dev); | |
395 | emac_update_duplex(dev); | |
396 | ||
397 | /* enable RX/TX */ | |
398 | reg_val = readl(db->membase + EMAC_CTL_REG); | |
399 | writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, | |
400 | db->membase + EMAC_CTL_REG); | |
401 | ||
402 | /* enable RX/TX0/RX Hlevel interrup */ | |
403 | reg_val = readl(db->membase + EMAC_INT_CTL_REG); | |
404 | reg_val |= (0xf << 0) | (0x01 << 8); | |
405 | writel(reg_val, db->membase + EMAC_INT_CTL_REG); | |
406 | ||
407 | spin_unlock_irqrestore(&db->lock, flags); | |
408 | } | |
409 | ||
410 | /* Our watchdog timed out. Called by the networking layer */ | |
411 | static void emac_timeout(struct net_device *dev) | |
412 | { | |
413 | struct emac_board_info *db = netdev_priv(dev); | |
414 | unsigned long flags; | |
415 | ||
416 | if (netif_msg_timer(db)) | |
417 | dev_err(db->dev, "tx time out.\n"); | |
418 | ||
419 | /* Save previous register address */ | |
420 | spin_lock_irqsave(&db->lock, flags); | |
421 | ||
422 | netif_stop_queue(dev); | |
423 | emac_reset(db); | |
424 | emac_init_device(dev); | |
425 | /* We can accept TX packets again */ | |
860e9538 | 426 | netif_trans_update(dev); |
49220505 SR |
427 | netif_wake_queue(dev); |
428 | ||
429 | /* Restore previous register address */ | |
430 | spin_unlock_irqrestore(&db->lock, flags); | |
431 | } | |
432 | ||
433 | /* Hardware start transmission. | |
434 | * Send a packet to media from the upper layer. | |
435 | */ | |
436 | static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
437 | { | |
438 | struct emac_board_info *db = netdev_priv(dev); | |
439 | unsigned long channel; | |
440 | unsigned long flags; | |
441 | ||
442 | channel = db->tx_fifo_stat & 3; | |
443 | if (channel == 3) | |
444 | return 1; | |
445 | ||
446 | channel = (channel == 1 ? 1 : 0); | |
447 | ||
448 | spin_lock_irqsave(&db->lock, flags); | |
449 | ||
450 | writel(channel, db->membase + EMAC_TX_INS_REG); | |
451 | ||
452 | emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, | |
453 | skb->data, skb->len); | |
454 | dev->stats.tx_bytes += skb->len; | |
455 | ||
456 | db->tx_fifo_stat |= 1 << channel; | |
457 | /* TX control: First packet immediately send, second packet queue */ | |
458 | if (channel == 0) { | |
459 | /* set TX len */ | |
460 | writel(skb->len, db->membase + EMAC_TX_PL0_REG); | |
461 | /* start translate from fifo to phy */ | |
462 | writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, | |
463 | db->membase + EMAC_TX_CTL0_REG); | |
464 | ||
465 | /* save the time stamp */ | |
860e9538 | 466 | netif_trans_update(dev); |
49220505 SR |
467 | } else if (channel == 1) { |
468 | /* set TX len */ | |
469 | writel(skb->len, db->membase + EMAC_TX_PL1_REG); | |
470 | /* start translate from fifo to phy */ | |
471 | writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, | |
472 | db->membase + EMAC_TX_CTL1_REG); | |
473 | ||
474 | /* save the time stamp */ | |
860e9538 | 475 | netif_trans_update(dev); |
49220505 SR |
476 | } |
477 | ||
478 | if ((db->tx_fifo_stat & 3) == 3) { | |
479 | /* Second packet */ | |
480 | netif_stop_queue(dev); | |
481 | } | |
482 | ||
483 | spin_unlock_irqrestore(&db->lock, flags); | |
484 | ||
485 | /* free this SKB */ | |
c99abc8b | 486 | dev_consume_skb_any(skb); |
49220505 SR |
487 | |
488 | return NETDEV_TX_OK; | |
489 | } | |
490 | ||
491 | /* EMAC interrupt handler | |
492 | * receive the packet to upper layer, free the transmitted packet | |
493 | */ | |
494 | static void emac_tx_done(struct net_device *dev, struct emac_board_info *db, | |
495 | unsigned int tx_status) | |
496 | { | |
497 | /* One packet sent complete */ | |
498 | db->tx_fifo_stat &= ~(tx_status & 3); | |
499 | if (3 == (tx_status & 3)) | |
500 | dev->stats.tx_packets += 2; | |
501 | else | |
502 | dev->stats.tx_packets++; | |
503 | ||
504 | if (netif_msg_tx_done(db)) | |
505 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
506 | ||
507 | netif_wake_queue(dev); | |
508 | } | |
509 | ||
510 | /* Received a packet and pass to upper layer | |
511 | */ | |
512 | static void emac_rx(struct net_device *dev) | |
513 | { | |
514 | struct emac_board_info *db = netdev_priv(dev); | |
515 | struct sk_buff *skb; | |
516 | u8 *rdptr; | |
517 | bool good_packet; | |
518 | static int rxlen_last; | |
519 | unsigned int reg_val; | |
520 | u32 rxhdr, rxstatus, rxcount, rxlen; | |
521 | ||
522 | /* Check packet ready or not */ | |
523 | while (1) { | |
524 | /* race warning: the first packet might arrive with | |
525 | * the interrupts disabled, but the second will fix | |
526 | * it | |
527 | */ | |
528 | rxcount = readl(db->membase + EMAC_RX_FBC_REG); | |
529 | ||
530 | if (netif_msg_rx_status(db)) | |
531 | dev_dbg(db->dev, "RXCount: %x\n", rxcount); | |
532 | ||
533 | if ((db->skb_last != NULL) && (rxlen_last > 0)) { | |
534 | dev->stats.rx_bytes += rxlen_last; | |
535 | ||
536 | /* Pass to upper layer */ | |
537 | db->skb_last->protocol = eth_type_trans(db->skb_last, | |
538 | dev); | |
539 | netif_rx(db->skb_last); | |
540 | dev->stats.rx_packets++; | |
541 | db->skb_last = NULL; | |
542 | rxlen_last = 0; | |
543 | ||
544 | reg_val = readl(db->membase + EMAC_RX_CTL_REG); | |
545 | reg_val &= ~EMAC_RX_CTL_DMA_EN; | |
546 | writel(reg_val, db->membase + EMAC_RX_CTL_REG); | |
547 | } | |
548 | ||
549 | if (!rxcount) { | |
550 | db->emacrx_completed_flag = 1; | |
551 | reg_val = readl(db->membase + EMAC_INT_CTL_REG); | |
552 | reg_val |= (0xf << 0) | (0x01 << 8); | |
553 | writel(reg_val, db->membase + EMAC_INT_CTL_REG); | |
554 | ||
555 | /* had one stuck? */ | |
556 | rxcount = readl(db->membase + EMAC_RX_FBC_REG); | |
557 | if (!rxcount) | |
558 | return; | |
559 | } | |
560 | ||
561 | reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); | |
562 | if (netif_msg_rx_status(db)) | |
563 | dev_dbg(db->dev, "receive header: %x\n", reg_val); | |
564 | if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { | |
565 | /* disable RX */ | |
566 | reg_val = readl(db->membase + EMAC_CTL_REG); | |
567 | writel(reg_val & ~EMAC_CTL_RX_EN, | |
568 | db->membase + EMAC_CTL_REG); | |
569 | ||
570 | /* Flush RX FIFO */ | |
571 | reg_val = readl(db->membase + EMAC_RX_CTL_REG); | |
572 | writel(reg_val | (1 << 3), | |
573 | db->membase + EMAC_RX_CTL_REG); | |
574 | ||
575 | do { | |
576 | reg_val = readl(db->membase + EMAC_RX_CTL_REG); | |
577 | } while (reg_val & (1 << 3)); | |
578 | ||
579 | /* enable RX */ | |
580 | reg_val = readl(db->membase + EMAC_CTL_REG); | |
581 | writel(reg_val | EMAC_CTL_RX_EN, | |
582 | db->membase + EMAC_CTL_REG); | |
583 | reg_val = readl(db->membase + EMAC_INT_CTL_REG); | |
584 | reg_val |= (0xf << 0) | (0x01 << 8); | |
585 | writel(reg_val, db->membase + EMAC_INT_CTL_REG); | |
586 | ||
587 | db->emacrx_completed_flag = 1; | |
588 | ||
589 | return; | |
590 | } | |
591 | ||
592 | /* A packet ready now & Get status/length */ | |
593 | good_packet = true; | |
594 | ||
934d0048 | 595 | rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG); |
49220505 SR |
596 | |
597 | if (netif_msg_rx_status(db)) | |
598 | dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr))); | |
599 | ||
600 | rxlen = EMAC_RX_IO_DATA_LEN(rxhdr); | |
601 | rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr); | |
602 | ||
603 | if (netif_msg_rx_status(db)) | |
604 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
605 | rxstatus, rxlen); | |
606 | ||
607 | /* Packet Status check */ | |
608 | if (rxlen < 0x40) { | |
609 | good_packet = false; | |
610 | if (netif_msg_rx_err(db)) | |
611 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
612 | } | |
613 | ||
614 | if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) { | |
615 | good_packet = false; | |
616 | ||
617 | if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) { | |
618 | if (netif_msg_rx_err(db)) | |
619 | dev_dbg(db->dev, "crc error\n"); | |
620 | dev->stats.rx_crc_errors++; | |
621 | } | |
622 | ||
623 | if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) { | |
624 | if (netif_msg_rx_err(db)) | |
625 | dev_dbg(db->dev, "length error\n"); | |
626 | dev->stats.rx_length_errors++; | |
627 | } | |
628 | } | |
629 | ||
630 | /* Move data from EMAC */ | |
2670cc69 MZ |
631 | if (good_packet) { |
632 | skb = netdev_alloc_skb(dev, rxlen + 4); | |
633 | if (!skb) | |
634 | continue; | |
49220505 | 635 | skb_reserve(skb, 2); |
4df864c1 | 636 | rdptr = skb_put(skb, rxlen - 4); |
49220505 SR |
637 | |
638 | /* Read received packet from RX SRAM */ | |
639 | if (netif_msg_rx_status(db)) | |
640 | dev_dbg(db->dev, "RxLen %x\n", rxlen); | |
641 | ||
642 | emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, | |
643 | rdptr, rxlen); | |
644 | dev->stats.rx_bytes += rxlen; | |
645 | ||
646 | /* Pass to upper layer */ | |
647 | skb->protocol = eth_type_trans(skb, dev); | |
648 | netif_rx(skb); | |
649 | dev->stats.rx_packets++; | |
650 | } | |
651 | } | |
652 | } | |
653 | ||
654 | static irqreturn_t emac_interrupt(int irq, void *dev_id) | |
655 | { | |
656 | struct net_device *dev = dev_id; | |
657 | struct emac_board_info *db = netdev_priv(dev); | |
658 | int int_status; | |
659 | unsigned long flags; | |
660 | unsigned int reg_val; | |
661 | ||
662 | /* A real interrupt coming */ | |
663 | ||
664 | /* holders of db->lock must always block IRQs */ | |
665 | spin_lock_irqsave(&db->lock, flags); | |
666 | ||
667 | /* Disable all interrupts */ | |
668 | writel(0, db->membase + EMAC_INT_CTL_REG); | |
669 | ||
670 | /* Got EMAC interrupt status */ | |
671 | /* Got ISR */ | |
672 | int_status = readl(db->membase + EMAC_INT_STA_REG); | |
673 | /* Clear ISR status */ | |
674 | writel(int_status, db->membase + EMAC_INT_STA_REG); | |
675 | ||
676 | if (netif_msg_intr(db)) | |
677 | dev_dbg(db->dev, "emac interrupt %02x\n", int_status); | |
678 | ||
679 | /* Received the coming packet */ | |
680 | if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) { | |
681 | /* carrier lost */ | |
682 | db->emacrx_completed_flag = 0; | |
683 | emac_rx(dev); | |
684 | } | |
685 | ||
686 | /* Transmit Interrupt check */ | |
687 | if (int_status & (0x01 | 0x02)) | |
688 | emac_tx_done(dev, db, int_status); | |
689 | ||
690 | if (int_status & (0x04 | 0x08)) | |
691 | netdev_info(dev, " ab : %x\n", int_status); | |
692 | ||
693 | /* Re-enable interrupt mask */ | |
694 | if (db->emacrx_completed_flag == 1) { | |
695 | reg_val = readl(db->membase + EMAC_INT_CTL_REG); | |
696 | reg_val |= (0xf << 0) | (0x01 << 8); | |
697 | writel(reg_val, db->membase + EMAC_INT_CTL_REG); | |
698 | } | |
699 | spin_unlock_irqrestore(&db->lock, flags); | |
700 | ||
701 | return IRQ_HANDLED; | |
702 | } | |
703 | ||
704 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
705 | /* | |
706 | * Used by netconsole | |
707 | */ | |
708 | static void emac_poll_controller(struct net_device *dev) | |
709 | { | |
710 | disable_irq(dev->irq); | |
711 | emac_interrupt(dev->irq, dev); | |
712 | enable_irq(dev->irq); | |
713 | } | |
714 | #endif | |
715 | ||
716 | /* Open the interface. | |
717 | * The interface is opened whenever "ifconfig" actives it. | |
718 | */ | |
719 | static int emac_open(struct net_device *dev) | |
720 | { | |
721 | struct emac_board_info *db = netdev_priv(dev); | |
722 | int ret; | |
723 | ||
724 | if (netif_msg_ifup(db)) | |
725 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
726 | ||
e9c56f8d | 727 | if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev)) |
49220505 SR |
728 | return -EAGAIN; |
729 | ||
730 | /* Initialize EMAC board */ | |
731 | emac_reset(db); | |
732 | emac_init_device(dev); | |
733 | ||
734 | ret = emac_mdio_probe(dev); | |
735 | if (ret < 0) { | |
b9111328 | 736 | free_irq(dev->irq, dev); |
49220505 SR |
737 | netdev_err(dev, "cannot probe MDIO bus\n"); |
738 | return ret; | |
739 | } | |
740 | ||
5427ccaf | 741 | phy_start(dev->phydev); |
49220505 SR |
742 | netif_start_queue(dev); |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | static void emac_shutdown(struct net_device *dev) | |
748 | { | |
749 | unsigned int reg_val; | |
750 | struct emac_board_info *db = netdev_priv(dev); | |
751 | ||
752 | /* Disable all interrupt */ | |
753 | writel(0, db->membase + EMAC_INT_CTL_REG); | |
754 | ||
dbedd44e | 755 | /* clear interrupt status */ |
49220505 SR |
756 | reg_val = readl(db->membase + EMAC_INT_STA_REG); |
757 | writel(reg_val, db->membase + EMAC_INT_STA_REG); | |
758 | ||
759 | /* Disable RX/TX */ | |
760 | reg_val = readl(db->membase + EMAC_CTL_REG); | |
761 | reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); | |
762 | writel(reg_val, db->membase + EMAC_CTL_REG); | |
763 | } | |
764 | ||
765 | /* Stop the interface. | |
766 | * The interface is stopped when it is brought. | |
767 | */ | |
768 | static int emac_stop(struct net_device *ndev) | |
769 | { | |
770 | struct emac_board_info *db = netdev_priv(ndev); | |
771 | ||
772 | if (netif_msg_ifdown(db)) | |
773 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
774 | ||
775 | netif_stop_queue(ndev); | |
776 | netif_carrier_off(ndev); | |
777 | ||
5427ccaf | 778 | phy_stop(ndev->phydev); |
49220505 SR |
779 | |
780 | emac_mdio_remove(ndev); | |
781 | ||
782 | emac_shutdown(ndev); | |
783 | ||
e9c56f8d MR |
784 | free_irq(ndev->irq, ndev); |
785 | ||
49220505 SR |
786 | return 0; |
787 | } | |
788 | ||
789 | static const struct net_device_ops emac_netdev_ops = { | |
790 | .ndo_open = emac_open, | |
791 | .ndo_stop = emac_stop, | |
792 | .ndo_start_xmit = emac_start_xmit, | |
793 | .ndo_tx_timeout = emac_timeout, | |
cec9ae50 | 794 | .ndo_set_rx_mode = emac_set_rx_mode, |
49220505 | 795 | .ndo_do_ioctl = emac_ioctl, |
49220505 SR |
796 | .ndo_validate_addr = eth_validate_addr, |
797 | .ndo_set_mac_address = emac_set_mac_address, | |
798 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
799 | .ndo_poll_controller = emac_poll_controller, | |
800 | #endif | |
801 | }; | |
802 | ||
803 | /* Search EMAC board, allocate space and register it | |
804 | */ | |
805 | static int emac_probe(struct platform_device *pdev) | |
806 | { | |
807 | struct device_node *np = pdev->dev.of_node; | |
808 | struct emac_board_info *db; | |
809 | struct net_device *ndev; | |
810 | int ret = 0; | |
811 | const char *mac_addr; | |
812 | ||
813 | ndev = alloc_etherdev(sizeof(struct emac_board_info)); | |
814 | if (!ndev) { | |
815 | dev_err(&pdev->dev, "could not allocate device.\n"); | |
816 | return -ENOMEM; | |
817 | } | |
818 | ||
819 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
820 | ||
821 | db = netdev_priv(ndev); | |
822 | memset(db, 0, sizeof(*db)); | |
823 | ||
824 | db->dev = &pdev->dev; | |
825 | db->ndev = ndev; | |
826 | db->pdev = pdev; | |
b8ca3387 | 827 | db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE); |
49220505 SR |
828 | |
829 | spin_lock_init(&db->lock); | |
830 | ||
831 | db->membase = of_iomap(np, 0); | |
832 | if (!db->membase) { | |
833 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
93baf4c6 | 834 | ret = -ENOMEM; |
49220505 SR |
835 | goto out; |
836 | } | |
837 | ||
838 | /* fill in parameters for net-dev structure */ | |
839 | ndev->base_addr = (unsigned long)db->membase; | |
840 | ndev->irq = irq_of_parse_and_map(np, 0); | |
841 | if (ndev->irq == -ENXIO) { | |
842 | netdev_err(ndev, "No irq resource\n"); | |
843 | ret = ndev->irq; | |
104eb270 | 844 | goto out_iounmap; |
49220505 SR |
845 | } |
846 | ||
847 | db->clk = devm_clk_get(&pdev->dev, NULL); | |
3d2232f5 JL |
848 | if (IS_ERR(db->clk)) { |
849 | ret = PTR_ERR(db->clk); | |
104eb270 | 850 | goto out_iounmap; |
3d2232f5 | 851 | } |
49220505 | 852 | |
104eb270 HG |
853 | ret = clk_prepare_enable(db->clk); |
854 | if (ret) { | |
855 | dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret); | |
856 | goto out_iounmap; | |
857 | } | |
49220505 | 858 | |
542a64c7 HG |
859 | ret = sunxi_sram_claim(&pdev->dev); |
860 | if (ret) { | |
861 | dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); | |
104eb270 | 862 | goto out_clk_disable_unprepare; |
542a64c7 HG |
863 | } |
864 | ||
49220505 SR |
865 | db->phy_node = of_parse_phandle(np, "phy", 0); |
866 | if (!db->phy_node) { | |
867 | dev_err(&pdev->dev, "no associated PHY\n"); | |
868 | ret = -ENODEV; | |
542a64c7 | 869 | goto out_release_sram; |
49220505 SR |
870 | } |
871 | ||
872 | /* Read MAC-address from DT */ | |
873 | mac_addr = of_get_mac_address(np); | |
874 | if (mac_addr) | |
875 | memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); | |
876 | ||
877 | /* Check if the MAC address is valid, if not get a random one */ | |
878 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
879 | eth_hw_addr_random(ndev); | |
880 | dev_warn(&pdev->dev, "using random MAC address %pM\n", | |
881 | ndev->dev_addr); | |
882 | } | |
883 | ||
884 | db->emacrx_completed_flag = 1; | |
885 | emac_powerup(ndev); | |
886 | emac_reset(db); | |
887 | ||
49220505 SR |
888 | ndev->netdev_ops = &emac_netdev_ops; |
889 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
890 | ndev->ethtool_ops = &emac_ethtool_ops; | |
891 | ||
49220505 SR |
892 | platform_set_drvdata(pdev, ndev); |
893 | ||
894 | /* Carrier starts down, phylib will bring it up */ | |
895 | netif_carrier_off(ndev); | |
896 | ||
897 | ret = register_netdev(ndev); | |
898 | if (ret) { | |
899 | dev_err(&pdev->dev, "Registering netdev failed!\n"); | |
900 | ret = -ENODEV; | |
542a64c7 | 901 | goto out_release_sram; |
49220505 SR |
902 | } |
903 | ||
904 | dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n", | |
905 | ndev->name, db->membase, ndev->irq, ndev->dev_addr); | |
906 | ||
907 | return 0; | |
908 | ||
542a64c7 HG |
909 | out_release_sram: |
910 | sunxi_sram_release(&pdev->dev); | |
104eb270 HG |
911 | out_clk_disable_unprepare: |
912 | clk_disable_unprepare(db->clk); | |
913 | out_iounmap: | |
914 | iounmap(db->membase); | |
49220505 SR |
915 | out: |
916 | dev_err(db->dev, "not found (%d).\n", ret); | |
917 | ||
918 | free_netdev(ndev); | |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
923 | static int emac_remove(struct platform_device *pdev) | |
924 | { | |
925 | struct net_device *ndev = platform_get_drvdata(pdev); | |
104eb270 | 926 | struct emac_board_info *db = netdev_priv(ndev); |
49220505 | 927 | |
49220505 | 928 | unregister_netdev(ndev); |
104eb270 HG |
929 | sunxi_sram_release(&pdev->dev); |
930 | clk_disable_unprepare(db->clk); | |
931 | iounmap(db->membase); | |
49220505 SR |
932 | free_netdev(ndev); |
933 | ||
934 | dev_dbg(&pdev->dev, "released and freed device\n"); | |
935 | return 0; | |
936 | } | |
937 | ||
938 | static int emac_suspend(struct platform_device *dev, pm_message_t state) | |
939 | { | |
940 | struct net_device *ndev = platform_get_drvdata(dev); | |
941 | ||
942 | netif_carrier_off(ndev); | |
943 | netif_device_detach(ndev); | |
944 | emac_shutdown(ndev); | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | static int emac_resume(struct platform_device *dev) | |
950 | { | |
951 | struct net_device *ndev = platform_get_drvdata(dev); | |
952 | struct emac_board_info *db = netdev_priv(ndev); | |
953 | ||
954 | emac_reset(db); | |
955 | emac_init_device(ndev); | |
956 | netif_device_attach(ndev); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static const struct of_device_id emac_of_match[] = { | |
4dae1686 MR |
962 | {.compatible = "allwinner,sun4i-a10-emac",}, |
963 | ||
964 | /* Deprecated */ | |
49220505 SR |
965 | {.compatible = "allwinner,sun4i-emac",}, |
966 | {}, | |
967 | }; | |
968 | ||
969 | MODULE_DEVICE_TABLE(of, emac_of_match); | |
970 | ||
971 | static struct platform_driver emac_driver = { | |
972 | .driver = { | |
973 | .name = "sun4i-emac", | |
974 | .of_match_table = emac_of_match, | |
975 | }, | |
976 | .probe = emac_probe, | |
977 | .remove = emac_remove, | |
978 | .suspend = emac_suspend, | |
979 | .resume = emac_resume, | |
980 | }; | |
981 | ||
982 | module_platform_driver(emac_driver); | |
983 | ||
984 | MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); | |
985 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); | |
986 | MODULE_DESCRIPTION("Allwinner A10 emac network driver"); | |
987 | MODULE_LICENSE("GPL"); |