]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/ethernet/amazon/ena/ena_netdev.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: ena: add support for out of order rx buffers refill
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
CommitLineData
1738cd3e
NB		 1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#ifdef CONFIG_RFS_ACCEL
36#include <linux/cpu_rmap.h>
37#endif /* CONFIG_RFS_ACCEL */
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/numa.h>
44#include <linux/pci.h>
45#include <linux/utsname.h>
46#include <linux/version.h>
47#include <linux/vmalloc.h>
48#include <net/ip.h>
49
50#include "ena_netdev.h"
51#include "ena_pci_id_tbl.h"
52
53static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56MODULE_DESCRIPTION(DEVICE_NAME);
57MODULE_LICENSE("GPL");
58MODULE_VERSION(DRV_MODULE_VERSION);
59
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (5 * HZ)
62
63#define ENA_NAPI_BUDGET 64
64
65#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67static int debug = -1;
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static struct ena_aenq_handlers aenq_handlers;
72
73static struct workqueue_struct *ena_wq;
74
75MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77static int ena_rss_init_default(struct ena_adapter *adapter);
78
79static void ena_tx_timeout(struct net_device *dev)
80{
81 struct ena_adapter *adapter = netdev_priv(dev);
82
3f6159db
NB		 83 /* Change the state of the device to trigger reset
84 * Check that we are not in the middle or a trigger already
85 */
86
87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
88 return;
89
e2eed0e3 90 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
1738cd3e
NB		 91 u64_stats_update_begin(&adapter->syncp);
92 adapter->dev_stats.tx_timeout++;
93 u64_stats_update_end(&adapter->syncp);
94
95 netif_err(adapter, tx_err, dev, "Transmit time out\n");
1738cd3e
NB		 96}
97
98static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
99{
100 int i;
101
102 for (i = 0; i < adapter->num_queues; i++)
103 adapter->rx_ring[i].mtu = mtu;
104}
105
106static int ena_change_mtu(struct net_device *dev, int new_mtu)
107{
108 struct ena_adapter *adapter = netdev_priv(dev);
109 int ret;
110
1738cd3e
NB		 111 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
112 if (!ret) {
113 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
114 update_rx_ring_mtu(adapter, new_mtu);
115 dev->mtu = new_mtu;
116 } else {
117 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
118 new_mtu);
119 }
120
121 return ret;
122}
123
124static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
125{
126#ifdef CONFIG_RFS_ACCEL
127 u32 i;
128 int rc;
129
130 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
131 if (!adapter->netdev->rx_cpu_rmap)
132 return -ENOMEM;
133 for (i = 0; i < adapter->num_queues; i++) {
134 int irq_idx = ENA_IO_IRQ_IDX(i);
135
136 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
da6f4cf5 137 pci_irq_vector(adapter->pdev, irq_idx));
1738cd3e
NB		 138 if (rc) {
139 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
140 adapter->netdev->rx_cpu_rmap = NULL;
141 return rc;
142 }
143 }
144#endif /* CONFIG_RFS_ACCEL */
145 return 0;
146}
147
148static void ena_init_io_rings_common(struct ena_adapter *adapter,
149 struct ena_ring *ring, u16 qid)
150{
151 ring->qid = qid;
152 ring->pdev = adapter->pdev;
153 ring->dev = &adapter->pdev->dev;
154 ring->netdev = adapter->netdev;
155 ring->napi = &adapter->ena_napi[qid].napi;
156 ring->adapter = adapter;
157 ring->ena_dev = adapter->ena_dev;
158 ring->per_napi_packets = 0;
159 ring->per_napi_bytes = 0;
160 ring->cpu = 0;
161 u64_stats_init(&ring->syncp);
162}
163
164static void ena_init_io_rings(struct ena_adapter *adapter)
165{
166 struct ena_com_dev *ena_dev;
167 struct ena_ring *txr, *rxr;
168 int i;
169
170 ena_dev = adapter->ena_dev;
171
172 for (i = 0; i < adapter->num_queues; i++) {
173 txr = &adapter->tx_ring[i];
174 rxr = &adapter->rx_ring[i];
175
176 /* TX/RX common ring state */
177 ena_init_io_rings_common(adapter, txr, i);
178 ena_init_io_rings_common(adapter, rxr, i);
179
180 /* TX specific ring state */
181 txr->ring_size = adapter->tx_ring_size;
182 txr->tx_max_header_size = ena_dev->tx_max_header_size;
183 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
184 txr->sgl_size = adapter->max_tx_sgl_size;
185 txr->smoothed_interval =
186 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
187
188 /* RX specific ring state */
189 rxr->ring_size = adapter->rx_ring_size;
190 rxr->rx_copybreak = adapter->rx_copybreak;
191 rxr->sgl_size = adapter->max_rx_sgl_size;
192 rxr->smoothed_interval =
193 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
a3af7c18 194 rxr->empty_rx_queue = 0;
1738cd3e
NB		 195 }
196}
197
198/* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
199 * @adapter: network interface device structure
200 * @qid: queue index
201 *
202 * Return 0 on success, negative on failure
203 */
204static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
205{
206 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
207 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
208 int size, i, node;
209
210 if (tx_ring->tx_buffer_info) {
211 netif_err(adapter, ifup,
212 adapter->netdev, "tx_buffer_info info is not NULL");
213 return -EEXIST;
214 }
215
216 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
217 node = cpu_to_node(ena_irq->cpu);
218
219 tx_ring->tx_buffer_info = vzalloc_node(size, node);
220 if (!tx_ring->tx_buffer_info) {
221 tx_ring->tx_buffer_info = vzalloc(size);
222 if (!tx_ring->tx_buffer_info)
223 return -ENOMEM;
224 }
225
226 size = sizeof(u16) * tx_ring->ring_size;
227 tx_ring->free_tx_ids = vzalloc_node(size, node);
228 if (!tx_ring->free_tx_ids) {
229 tx_ring->free_tx_ids = vzalloc(size);
230 if (!tx_ring->free_tx_ids) {
231 vfree(tx_ring->tx_buffer_info);
232 return -ENOMEM;
233 }
234 }
235
236 /* Req id ring for TX out of order completions */
237 for (i = 0; i < tx_ring->ring_size; i++)
238 tx_ring->free_tx_ids[i] = i;
239
240 /* Reset tx statistics */
241 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
242
243 tx_ring->next_to_use = 0;
244 tx_ring->next_to_clean = 0;
245 tx_ring->cpu = ena_irq->cpu;
246 return 0;
247}
248
249/* ena_free_tx_resources - Free I/O Tx Resources per Queue
250 * @adapter: network interface device structure
251 * @qid: queue index
252 *
253 * Free all transmit software resources
254 */
255static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
256{
257 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
258
259 vfree(tx_ring->tx_buffer_info);
260 tx_ring->tx_buffer_info = NULL;
261
262 vfree(tx_ring->free_tx_ids);
263 tx_ring->free_tx_ids = NULL;
264}
265
266/* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
267 * @adapter: private structure
268 *
269 * Return 0 on success, negative on failure
270 */
271static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
272{
273 int i, rc = 0;
274
275 for (i = 0; i < adapter->num_queues; i++) {
276 rc = ena_setup_tx_resources(adapter, i);
277 if (rc)
278 goto err_setup_tx;
279 }
280
281 return 0;
282
283err_setup_tx:
284
285 netif_err(adapter, ifup, adapter->netdev,
286 "Tx queue %d: allocation failed\n", i);
287
288 /* rewind the index freeing the rings as we go */
289 while (i--)
290 ena_free_tx_resources(adapter, i);
291 return rc;
292}
293
294/* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
295 * @adapter: board private structure
296 *
297 * Free all transmit software resources
298 */
299static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
300{
301 int i;
302
303 for (i = 0; i < adapter->num_queues; i++)
304 ena_free_tx_resources(adapter, i);
305}
306
ad974bae
NB		 307static inline int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id)
308{
309 if (likely(req_id < rx_ring->ring_size))
310 return 0;
311
312 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
313 "Invalid rx req_id: %hu\n", req_id);
314
315 u64_stats_update_begin(&rx_ring->syncp);
316 rx_ring->rx_stats.bad_req_id++;
317 u64_stats_update_end(&rx_ring->syncp);
318
319 /* Trigger device reset */
320 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
321 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags);
322 return -EFAULT;
323}
324
1738cd3e
NB		 325/* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
326 * @adapter: network interface device structure
327 * @qid: queue index
328 *
329 * Returns 0 on success, negative on failure
330 */
331static int ena_setup_rx_resources(struct ena_adapter *adapter,
332 u32 qid)
333{
334 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
335 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
ad974bae 336 int size, node, i;
1738cd3e
NB		 337
338 if (rx_ring->rx_buffer_info) {
339 netif_err(adapter, ifup, adapter->netdev,
340 "rx_buffer_info is not NULL");
341 return -EEXIST;
342 }
343
344 /* alloc extra element so in rx path
345 * we can always prefetch rx_info + 1
346 */
347 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
348 node = cpu_to_node(ena_irq->cpu);
349
350 rx_ring->rx_buffer_info = vzalloc_node(size, node);
351 if (!rx_ring->rx_buffer_info) {
352 rx_ring->rx_buffer_info = vzalloc(size);
353 if (!rx_ring->rx_buffer_info)
354 return -ENOMEM;
355 }
356
ad974bae
NB		 357 size = sizeof(u16) * rx_ring->ring_size;
358 rx_ring->free_rx_ids = vzalloc_node(size, node);
359 if (!rx_ring->free_rx_ids) {
360 rx_ring->free_rx_ids = vzalloc(size);
361 if (!rx_ring->free_rx_ids) {
362 vfree(rx_ring->rx_buffer_info);
363 return -ENOMEM;
364 }
365 }
366
367 /* Req id ring for receiving RX pkts out of order */
368 for (i = 0; i < rx_ring->ring_size; i++)
369 rx_ring->free_rx_ids[i] = i;
370
1738cd3e
NB		 371 /* Reset rx statistics */
372 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
373
374 rx_ring->next_to_clean = 0;
375 rx_ring->next_to_use = 0;
376 rx_ring->cpu = ena_irq->cpu;
377
378 return 0;
379}
380
381/* ena_free_rx_resources - Free I/O Rx Resources
382 * @adapter: network interface device structure
383 * @qid: queue index
384 *
385 * Free all receive software resources
386 */
387static void ena_free_rx_resources(struct ena_adapter *adapter,
388 u32 qid)
389{
390 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
391
392 vfree(rx_ring->rx_buffer_info);
393 rx_ring->rx_buffer_info = NULL;
ad974bae
NB		 394
395 vfree(rx_ring->free_rx_ids);
396 rx_ring->free_rx_ids = NULL;
1738cd3e
NB		 397}
398
399/* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
400 * @adapter: board private structure
401 *
402 * Return 0 on success, negative on failure
403 */
404static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
405{
406 int i, rc = 0;
407
408 for (i = 0; i < adapter->num_queues; i++) {
409 rc = ena_setup_rx_resources(adapter, i);
410 if (rc)
411 goto err_setup_rx;
412 }
413
414 return 0;
415
416err_setup_rx:
417
418 netif_err(adapter, ifup, adapter->netdev,
419 "Rx queue %d: allocation failed\n", i);
420
421 /* rewind the index freeing the rings as we go */
422 while (i--)
423 ena_free_rx_resources(adapter, i);
424 return rc;
425}
426
427/* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
428 * @adapter: board private structure
429 *
430 * Free all receive software resources
431 */
432static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
433{
434 int i;
435
436 for (i = 0; i < adapter->num_queues; i++)
437 ena_free_rx_resources(adapter, i);
438}
439
440static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
441 struct ena_rx_buffer *rx_info, gfp_t gfp)
442{
443 struct ena_com_buf *ena_buf;
444 struct page *page;
445 dma_addr_t dma;
446
447 /* if previous allocated page is not used */
448 if (unlikely(rx_info->page))
449 return 0;
450
451 page = alloc_page(gfp);
452 if (unlikely(!page)) {
453 u64_stats_update_begin(&rx_ring->syncp);
454 rx_ring->rx_stats.page_alloc_fail++;
455 u64_stats_update_end(&rx_ring->syncp);
456 return -ENOMEM;
457 }
458
459 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
460 DMA_FROM_DEVICE);
461 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
462 u64_stats_update_begin(&rx_ring->syncp);
463 rx_ring->rx_stats.dma_mapping_err++;
464 u64_stats_update_end(&rx_ring->syncp);
465
466 __free_page(page);
467 return -EIO;
468 }
469 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
470 "alloc page %p, rx_info %p\n", page, rx_info);
471
472 rx_info->page = page;
473 rx_info->page_offset = 0;
474 ena_buf = &rx_info->ena_buf;
475 ena_buf->paddr = dma;
476 ena_buf->len = PAGE_SIZE;
477
478 return 0;
479}
480
481static void ena_free_rx_page(struct ena_ring *rx_ring,
482 struct ena_rx_buffer *rx_info)
483{
484 struct page *page = rx_info->page;
485 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
486
487 if (unlikely(!page)) {
488 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
489 "Trying to free unallocated buffer\n");
490 return;
491 }
492
493 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
494 DMA_FROM_DEVICE);
495
496 __free_page(page);
497 rx_info->page = NULL;
498}
499
500static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
501{
ad974bae 502 u16 next_to_use, req_id;
1738cd3e
NB		 503 u32 i;
504 int rc;
505
506 next_to_use = rx_ring->next_to_use;
507
508 for (i = 0; i < num; i++) {
ad974bae
NB		 509 struct ena_rx_buffer *rx_info;
510
511 req_id = rx_ring->free_rx_ids[next_to_use];
512 rc = validate_rx_req_id(rx_ring, req_id);
513 if (unlikely(rc < 0))
514 break;
515
516 rx_info = &rx_ring->rx_buffer_info[req_id];
517
1738cd3e
NB		 518
519 rc = ena_alloc_rx_page(rx_ring, rx_info,
520 __GFP_COLD | GFP_ATOMIC | __GFP_COMP);
521 if (unlikely(rc < 0)) {
522 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
523 "failed to alloc buffer for rx queue %d\n",
524 rx_ring->qid);
525 break;
526 }
527 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
528 &rx_info->ena_buf,
ad974bae 529 req_id);
1738cd3e
NB		 530 if (unlikely(rc)) {
531 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
532 "failed to add buffer for rx queue %d\n",
533 rx_ring->qid);
534 break;
535 }
536 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
537 rx_ring->ring_size);
538 }
539
540 if (unlikely(i < num)) {
541 u64_stats_update_begin(&rx_ring->syncp);
542 rx_ring->rx_stats.refil_partial++;
543 u64_stats_update_end(&rx_ring->syncp);
544 netdev_warn(rx_ring->netdev,
545 "refilled rx qid %d with only %d buffers (from %d)\n",
546 rx_ring->qid, i, num);
547 }
548
549 if (likely(i)) {
550 /* Add memory barrier to make sure the desc were written before
551 * issue a doorbell
552 */
553 wmb();
554 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
555 }
556
557 rx_ring->next_to_use = next_to_use;
558
559 return i;
560}
561
562static void ena_free_rx_bufs(struct ena_adapter *adapter,
563 u32 qid)
564{
565 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
566 u32 i;
567
568 for (i = 0; i < rx_ring->ring_size; i++) {
569 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
570
571 if (rx_info->page)
572 ena_free_rx_page(rx_ring, rx_info);
573 }
574}
575
576/* ena_refill_all_rx_bufs - allocate all queues Rx buffers
577 * @adapter: board private structure
578 *
579 */
580static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
581{
582 struct ena_ring *rx_ring;
583 int i, rc, bufs_num;
584
585 for (i = 0; i < adapter->num_queues; i++) {
586 rx_ring = &adapter->rx_ring[i];
587 bufs_num = rx_ring->ring_size - 1;
588 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
589
590 if (unlikely(rc != bufs_num))
591 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
592 "refilling Queue %d failed. allocated %d buffers from: %d\n",
593 i, rc, bufs_num);
594 }
595}
596
597static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
598{
599 int i;
600
601 for (i = 0; i < adapter->num_queues; i++)
602 ena_free_rx_bufs(adapter, i);
603}
604
605/* ena_free_tx_bufs - Free Tx Buffers per Queue
606 * @tx_ring: TX ring for which buffers be freed
607 */
608static void ena_free_tx_bufs(struct ena_ring *tx_ring)
609{
5add6e4a 610 bool print_once = true;
1738cd3e
NB		 611 u32 i;
612
613 for (i = 0; i < tx_ring->ring_size; i++) {
614 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
615 struct ena_com_buf *ena_buf;
616 int nr_frags;
617 int j;
618
619 if (!tx_info->skb)
620 continue;
621
5add6e4a
NB		 622 if (print_once) {
623 netdev_notice(tx_ring->netdev,
624 "free uncompleted tx skb qid %d idx 0x%x\n",
625 tx_ring->qid, i);
626 print_once = false;
627 } else {
628 netdev_dbg(tx_ring->netdev,
629 "free uncompleted tx skb qid %d idx 0x%x\n",
630 tx_ring->qid, i);
631 }
1738cd3e
NB		 632
633 ena_buf = tx_info->bufs;
634 dma_unmap_single(tx_ring->dev,
635 ena_buf->paddr,
636 ena_buf->len,
637 DMA_TO_DEVICE);
638
639 /* unmap remaining mapped pages */
640 nr_frags = tx_info->num_of_bufs - 1;
641 for (j = 0; j < nr_frags; j++) {
642 ena_buf++;
643 dma_unmap_page(tx_ring->dev,
644 ena_buf->paddr,
645 ena_buf->len,
646 DMA_TO_DEVICE);
647 }
648
649 dev_kfree_skb_any(tx_info->skb);
650 }
651 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
652 tx_ring->qid));
653}
654
655static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
656{
657 struct ena_ring *tx_ring;
658 int i;
659
660 for (i = 0; i < adapter->num_queues; i++) {
661 tx_ring = &adapter->tx_ring[i];
662 ena_free_tx_bufs(tx_ring);
663 }
664}
665
666static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
667{
668 u16 ena_qid;
669 int i;
670
671 for (i = 0; i < adapter->num_queues; i++) {
672 ena_qid = ENA_IO_TXQ_IDX(i);
673 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
674 }
675}
676
677static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
678{
679 u16 ena_qid;
680 int i;
681
682 for (i = 0; i < adapter->num_queues; i++) {
683 ena_qid = ENA_IO_RXQ_IDX(i);
684 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
685 }
686}
687
688static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
689{
690 ena_destroy_all_tx_queues(adapter);
691 ena_destroy_all_rx_queues(adapter);
692}
693
694static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
695{
696 struct ena_tx_buffer *tx_info = NULL;
697
698 if (likely(req_id < tx_ring->ring_size)) {
699 tx_info = &tx_ring->tx_buffer_info[req_id];
700 if (likely(tx_info->skb))
701 return 0;
702 }
703
704 if (tx_info)
705 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
706 "tx_info doesn't have valid skb\n");
707 else
708 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
709 "Invalid req_id: %hu\n", req_id);
710
711 u64_stats_update_begin(&tx_ring->syncp);
712 tx_ring->tx_stats.bad_req_id++;
713 u64_stats_update_end(&tx_ring->syncp);
714
715 /* Trigger device reset */
e2eed0e3 716 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
1738cd3e
NB		 717 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
718 return -EFAULT;
719}
720
721static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
722{
723 struct netdev_queue *txq;
724 bool above_thresh;
725 u32 tx_bytes = 0;
726 u32 total_done = 0;
727 u16 next_to_clean;
728 u16 req_id;
729 int tx_pkts = 0;
730 int rc;
731
732 next_to_clean = tx_ring->next_to_clean;
733 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
734
735 while (tx_pkts < budget) {
736 struct ena_tx_buffer *tx_info;
737 struct sk_buff *skb;
738 struct ena_com_buf *ena_buf;
739 int i, nr_frags;
740
741 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
742 &req_id);
743 if (rc)
744 break;
745
746 rc = validate_tx_req_id(tx_ring, req_id);
747 if (rc)
748 break;
749
750 tx_info = &tx_ring->tx_buffer_info[req_id];
751 skb = tx_info->skb;
752
753 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
754 prefetch(&skb->end);
755
756 tx_info->skb = NULL;
757 tx_info->last_jiffies = 0;
758
759 if (likely(tx_info->num_of_bufs != 0)) {
760 ena_buf = tx_info->bufs;
761
762 dma_unmap_single(tx_ring->dev,
763 dma_unmap_addr(ena_buf, paddr),
764 dma_unmap_len(ena_buf, len),
765 DMA_TO_DEVICE);
766
767 /* unmap remaining mapped pages */
768 nr_frags = tx_info->num_of_bufs - 1;
769 for (i = 0; i < nr_frags; i++) {
770 ena_buf++;
771 dma_unmap_page(tx_ring->dev,
772 dma_unmap_addr(ena_buf, paddr),
773 dma_unmap_len(ena_buf, len),
774 DMA_TO_DEVICE);
775 }
776 }
777
778 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
779 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
780 skb);
781
782 tx_bytes += skb->len;
783 dev_kfree_skb(skb);
784 tx_pkts++;
785 total_done += tx_info->tx_descs;
786
787 tx_ring->free_tx_ids[next_to_clean] = req_id;
788 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
789 tx_ring->ring_size);
790 }
791
792 tx_ring->next_to_clean = next_to_clean;
793 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
794 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
795
796 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
797
798 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
799 "tx_poll: q %d done. total pkts: %d\n",
800 tx_ring->qid, tx_pkts);
801
802 /* need to make the rings circular update visible to
803 * ena_start_xmit() before checking for netif_queue_stopped().
804 */
805 smp_mb();
806
807 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
808 ENA_TX_WAKEUP_THRESH;
809 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
810 __netif_tx_lock(txq, smp_processor_id());
811 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
812 ENA_TX_WAKEUP_THRESH;
813 if (netif_tx_queue_stopped(txq) && above_thresh) {
814 netif_tx_wake_queue(txq);
815 u64_stats_update_begin(&tx_ring->syncp);
816 tx_ring->tx_stats.queue_wakeup++;
817 u64_stats_update_end(&tx_ring->syncp);
818 }
819 __netif_tx_unlock(txq);
820 }
821
822 tx_ring->per_napi_bytes += tx_bytes;
823 tx_ring->per_napi_packets += tx_pkts;
824
825 return tx_pkts;
826}
827
828static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
829 struct ena_com_rx_buf_info *ena_bufs,
830 u32 descs,
831 u16 *next_to_clean)
832{
833 struct sk_buff *skb;
ad974bae
NB		 834 struct ena_rx_buffer *rx_info;
835 u16 len, req_id, buf = 0;
1738cd3e
NB		 836 void *va;
837
ad974bae
NB		 838 len = ena_bufs[buf].len;
839 req_id = ena_bufs[buf].req_id;
840 rx_info = &rx_ring->rx_buffer_info[req_id];
841
1738cd3e
NB		 842 if (unlikely(!rx_info->page)) {
843 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
844 "Page is NULL\n");
845 return NULL;
846 }
847
848 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
849 "rx_info %p page %p\n",
850 rx_info, rx_info->page);
851
852 /* save virt address of first buffer */
853 va = page_address(rx_info->page) + rx_info->page_offset;
854 prefetch(va + NET_IP_ALIGN);
855
856 if (len <= rx_ring->rx_copybreak) {
857 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
858 rx_ring->rx_copybreak);
859 if (unlikely(!skb)) {
860 u64_stats_update_begin(&rx_ring->syncp);
861 rx_ring->rx_stats.skb_alloc_fail++;
862 u64_stats_update_end(&rx_ring->syncp);
863 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
864 "Failed to allocate skb\n");
865 return NULL;
866 }
867
868 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
869 "rx allocated small packet. len %d. data_len %d\n",
870 skb->len, skb->data_len);
871
872 /* sync this buffer for CPU use */
873 dma_sync_single_for_cpu(rx_ring->dev,
874 dma_unmap_addr(&rx_info->ena_buf, paddr),
875 len,
876 DMA_FROM_DEVICE);
877 skb_copy_to_linear_data(skb, va, len);
878 dma_sync_single_for_device(rx_ring->dev,
879 dma_unmap_addr(&rx_info->ena_buf, paddr),
880 len,
881 DMA_FROM_DEVICE);
882
883 skb_put(skb, len);
884 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
885 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
886 rx_ring->ring_size);
887 return skb;
888 }
889
890 skb = napi_get_frags(rx_ring->napi);
891 if (unlikely(!skb)) {
892 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
893 "Failed allocating skb\n");
894 u64_stats_update_begin(&rx_ring->syncp);
895 rx_ring->rx_stats.skb_alloc_fail++;
896 u64_stats_update_end(&rx_ring->syncp);
897 return NULL;
898 }
899
900 do {
901 dma_unmap_page(rx_ring->dev,
902 dma_unmap_addr(&rx_info->ena_buf, paddr),
903 PAGE_SIZE, DMA_FROM_DEVICE);
904
905 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
906 rx_info->page_offset, len, PAGE_SIZE);
907
908 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
909 "rx skb updated. len %d. data_len %d\n",
910 skb->len, skb->data_len);
911
912 rx_info->page = NULL;
ad974bae
NB		 913
914 rx_ring->free_rx_ids[*next_to_clean] = req_id;
1738cd3e
NB		 915 *next_to_clean =
916 ENA_RX_RING_IDX_NEXT(*next_to_clean,
917 rx_ring->ring_size);
918 if (likely(--descs == 0))
919 break;
ad974bae
NB		 920
921 buf++;
922 len = ena_bufs[buf].len;
923 req_id = ena_bufs[buf].req_id;
924 rx_info = &rx_ring->rx_buffer_info[req_id];
1738cd3e
NB		 925 } while (1);
926
927 return skb;
928}
929
930/* ena_rx_checksum - indicate in skb if hw indicated a good cksum
931 * @adapter: structure containing adapter specific data
932 * @ena_rx_ctx: received packet context/metadata
933 * @skb: skb currently being received and modified
934 */
935static inline void ena_rx_checksum(struct ena_ring *rx_ring,
936 struct ena_com_rx_ctx *ena_rx_ctx,
937 struct sk_buff *skb)
938{
939 /* Rx csum disabled */
940 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
941 skb->ip_summed = CHECKSUM_NONE;
942 return;
943 }
944
945 /* For fragmented packets the checksum isn't valid */
946 if (ena_rx_ctx->frag) {
947 skb->ip_summed = CHECKSUM_NONE;
948 return;
949 }
950
951 /* if IP and error */
952 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
953 (ena_rx_ctx->l3_csum_err))) {
954 /* ipv4 checksum error */
955 skb->ip_summed = CHECKSUM_NONE;
956 u64_stats_update_begin(&rx_ring->syncp);
957 rx_ring->rx_stats.bad_csum++;
958 u64_stats_update_end(&rx_ring->syncp);
959 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
960 "RX IPv4 header checksum error\n");
961 return;
962 }
963
964 /* if TCP/UDP */
965 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
966 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
967 if (unlikely(ena_rx_ctx->l4_csum_err)) {
968 /* TCP/UDP checksum error */
969 u64_stats_update_begin(&rx_ring->syncp);
970 rx_ring->rx_stats.bad_csum++;
971 u64_stats_update_end(&rx_ring->syncp);
972 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
973 "RX L4 checksum error\n");
974 skb->ip_summed = CHECKSUM_NONE;
975 return;
976 }
977
978 skb->ip_summed = CHECKSUM_UNNECESSARY;
979 }
980}
981
982static void ena_set_rx_hash(struct ena_ring *rx_ring,
983 struct ena_com_rx_ctx *ena_rx_ctx,
984 struct sk_buff *skb)
985{
986 enum pkt_hash_types hash_type;
987
988 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
989 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
990 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
991
992 hash_type = PKT_HASH_TYPE_L4;
993 else
994 hash_type = PKT_HASH_TYPE_NONE;
995
996 /* Override hash type if the packet is fragmented */
997 if (ena_rx_ctx->frag)
998 hash_type = PKT_HASH_TYPE_NONE;
999
1000 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
1001 }
1002}
1003
1004/* ena_clean_rx_irq - Cleanup RX irq
1005 * @rx_ring: RX ring to clean
1006 * @napi: napi handler
1007 * @budget: how many packets driver is allowed to clean
1008 *
1009 * Returns the number of cleaned buffers.
1010 */
1011static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
1012 u32 budget)
1013{
1014 u16 next_to_clean = rx_ring->next_to_clean;
1015 u32 res_budget, work_done;
1016
1017 struct ena_com_rx_ctx ena_rx_ctx;
1018 struct ena_adapter *adapter;
1019 struct sk_buff *skb;
1020 int refill_required;
1021 int refill_threshold;
1022 int rc = 0;
1023 int total_len = 0;
1024 int rx_copybreak_pkt = 0;
ad974bae 1025 int i;
1738cd3e
NB		 1026
1027 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1028 "%s qid %d\n", __func__, rx_ring->qid);
1029 res_budget = budget;
1030
1031 do {
1032 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1033 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1034 ena_rx_ctx.descs = 0;
1035 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1036 rx_ring->ena_com_io_sq,
1037 &ena_rx_ctx);
1038 if (unlikely(rc))
1039 goto error;
1040
1041 if (unlikely(ena_rx_ctx.descs == 0))
1042 break;
1043
1044 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1045 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
1046 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
1047 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
1048
1049 /* allocate skb and fill it */
1050 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1051 &next_to_clean);
1052
1053 /* exit if we failed to retrieve a buffer */
1054 if (unlikely(!skb)) {
ad974bae
NB		 1055 for (i = 0; i < ena_rx_ctx.descs; i++) {
1056 rx_ring->free_tx_ids[next_to_clean] =
1057 rx_ring->ena_bufs[i].req_id;
1058 next_to_clean =
1059 ENA_RX_RING_IDX_NEXT(next_to_clean,
1060 rx_ring->ring_size);
1061 }
1738cd3e
NB		 1062 break;
1063 }
1064
1065 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1066
1067 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1068
1069 skb_record_rx_queue(skb, rx_ring->qid);
1070
1071 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1072 total_len += rx_ring->ena_bufs[0].len;
1073 rx_copybreak_pkt++;
1074 napi_gro_receive(napi, skb);
1075 } else {
1076 total_len += skb->len;
1077 napi_gro_frags(napi);
1078 }
1079
1080 res_budget--;
1081 } while (likely(res_budget));
1082
1083 work_done = budget - res_budget;
1084 rx_ring->per_napi_bytes += total_len;
1085 rx_ring->per_napi_packets += work_done;
1086 u64_stats_update_begin(&rx_ring->syncp);
1087 rx_ring->rx_stats.bytes += total_len;
1088 rx_ring->rx_stats.cnt += work_done;
1089 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1090 u64_stats_update_end(&rx_ring->syncp);
1091
1092 rx_ring->next_to_clean = next_to_clean;
1093
1094 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1095 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1096
1097 /* Optimization, try to batch new rx buffers */
1098 if (refill_required > refill_threshold) {
1099 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1100 ena_refill_rx_bufs(rx_ring, refill_required);
1101 }
1102
1103 return work_done;
1104
1105error:
1106 adapter = netdev_priv(rx_ring->netdev);
1107
1108 u64_stats_update_begin(&rx_ring->syncp);
1109 rx_ring->rx_stats.bad_desc_num++;
1110 u64_stats_update_end(&rx_ring->syncp);
1111
1112 /* Too many desc from the device. Trigger reset */
e2eed0e3 1113 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1738cd3e
NB		 1114 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1115
1116 return 0;
1117}
1118
1119inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1120 struct ena_ring *tx_ring)
1121{
1122 /* We apply adaptive moderation on Rx path only.
1123 * Tx uses static interrupt moderation.
1124 */
1125 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1126 rx_ring->per_napi_packets,
1127 rx_ring->per_napi_bytes,
1128 &rx_ring->smoothed_interval,
1129 &rx_ring->moder_tbl_idx);
1130
1131 /* Reset per napi packets/bytes */
1132 tx_ring->per_napi_packets = 0;
1133 tx_ring->per_napi_bytes = 0;
1134 rx_ring->per_napi_packets = 0;
1135 rx_ring->per_napi_bytes = 0;
1136}
1137
418df30f
NB		 1138static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
1139 struct ena_ring *rx_ring)
1140{
1141 struct ena_eth_io_intr_reg intr_reg;
1142
1143 /* Update intr register: rx intr delay,
1144 * tx intr delay and interrupt unmask
1145 */
1146 ena_com_update_intr_reg(&intr_reg,
1147 rx_ring->smoothed_interval,
1148 tx_ring->smoothed_interval,
1149 true);
1150
1151 /* It is a shared MSI-X.
1152 * Tx and Rx CQ have pointer to it.
1153 * So we use one of them to reach the intr reg
1154 */
1155 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1156}
1157
1738cd3e
NB		 1158static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1159 struct ena_ring *rx_ring)
1160{
1161 int cpu = get_cpu();
1162 int numa_node;
1163
1164 /* Check only one ring since the 2 rings are running on the same cpu */
1165 if (likely(tx_ring->cpu == cpu))
1166 goto out;
1167
1168 numa_node = cpu_to_node(cpu);
1169 put_cpu();
1170
1171 if (numa_node != NUMA_NO_NODE) {
1172 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1173 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1174 }
1175
1176 tx_ring->cpu = cpu;
1177 rx_ring->cpu = cpu;
1178
1179 return;
1180out:
1181 put_cpu();
1182}
1183
1184static int ena_io_poll(struct napi_struct *napi, int budget)
1185{
1186 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1187 struct ena_ring *tx_ring, *rx_ring;
1738cd3e
NB		 1188
1189 u32 tx_work_done;
1190 u32 rx_work_done;
1191 int tx_budget;
1192 int napi_comp_call = 0;
1193 int ret;
1194
1195 tx_ring = ena_napi->tx_ring;
1196 rx_ring = ena_napi->rx_ring;
1197
1198 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1199
3f6159db
NB		 1200 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1201 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1738cd3e
NB		 1202 napi_complete_done(napi, 0);
1203 return 0;
1204 }
1205
1206 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1207 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1208
b1669c9f
NB		 1209 /* If the device is about to reset or down, avoid unmask
1210 * the interrupt and return 0 so NAPI won't reschedule
1211 */
1212 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1213 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1214 napi_complete_done(napi, 0);
1215 ret = 0;
1738cd3e 1216
b1669c9f 1217 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1738cd3e 1218 napi_comp_call = 1;
1738cd3e 1219
b1669c9f
NB		 1220 /* Update numa and unmask the interrupt only when schedule
1221 * from the interrupt context (vs from sk_busy_loop)
1738cd3e 1222 */
b1669c9f
NB		 1223 if (napi_complete_done(napi, rx_work_done)) {
1224 /* Tx and Rx share the same interrupt vector */
1225 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1226 ena_adjust_intr_moderation(rx_ring, tx_ring);
1227
418df30f 1228 ena_unmask_interrupt(tx_ring, rx_ring);
b1669c9f 1229 }
1738cd3e 1230
1738cd3e
NB		 1231 ena_update_ring_numa_node(tx_ring, rx_ring);
1232
1233 ret = rx_work_done;
1234 } else {
1235 ret = budget;
1236 }
1237
1238 u64_stats_update_begin(&tx_ring->syncp);
1239 tx_ring->tx_stats.napi_comp += napi_comp_call;
1240 tx_ring->tx_stats.tx_poll++;
1241 u64_stats_update_end(&tx_ring->syncp);
1242
1243 return ret;
1244}
1245
1246static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1247{
1248 struct ena_adapter *adapter = (struct ena_adapter *)data;
1249
1250 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1251
1252 /* Don't call the aenq handler before probe is done */
1253 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1254 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1255
1256 return IRQ_HANDLED;
1257}
1258
1259/* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1260 * @irq: interrupt number
1261 * @data: pointer to a network interface private napi device structure
1262 */
1263static irqreturn_t ena_intr_msix_io(int irq, void *data)
1264{
1265 struct ena_napi *ena_napi = data;
1266
1267 napi_schedule(&ena_napi->napi);
1268
1269 return IRQ_HANDLED;
1270}
1271
1272static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1273{
da6f4cf5 1274 int msix_vecs, rc;
1738cd3e
NB		 1275
1276 /* Reserved the max msix vectors we might need */
1277 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1278
1279 netif_dbg(adapter, probe, adapter->netdev,
1280 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1281
da6f4cf5
CH		 1282 rc = pci_alloc_irq_vectors(adapter->pdev, msix_vecs, msix_vecs,
1283 PCI_IRQ_MSIX);
1284 if (rc < 0) {
1738cd3e
NB		 1285 netif_err(adapter, probe, adapter->netdev,
1286 "Failed to enable MSI-X, vectors %d rc %d\n",
1287 msix_vecs, rc);
1288 return -ENOSPC;
1289 }
1290
1291 netif_dbg(adapter, probe, adapter->netdev, "enable MSI-X, vectors %d\n",
1292 msix_vecs);
1293
1294 if (msix_vecs >= 1) {
1295 if (ena_init_rx_cpu_rmap(adapter))
1296 netif_warn(adapter, probe, adapter->netdev,
1297 "Failed to map IRQs to CPUs\n");
1298 }
1299
1300 adapter->msix_vecs = msix_vecs;
1738cd3e
NB		 1301
1302 return 0;
1303}
1304
1305static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1306{
1307 u32 cpu;
1308
1309 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1310 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1311 pci_name(adapter->pdev));
1312 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1313 ena_intr_msix_mgmnt;
1314 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1315 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
da6f4cf5 1316 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1738cd3e
NB		 1317 cpu = cpumask_first(cpu_online_mask);
1318 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1319 cpumask_set_cpu(cpu,
1320 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1321}
1322
1323static void ena_setup_io_intr(struct ena_adapter *adapter)
1324{
1325 struct net_device *netdev;
1326 int irq_idx, i, cpu;
1327
1328 netdev = adapter->netdev;
1329
1330 for (i = 0; i < adapter->num_queues; i++) {
1331 irq_idx = ENA_IO_IRQ_IDX(i);
1332 cpu = i % num_online_cpus();
1333
1334 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1335 "%s-Tx-Rx-%d", netdev->name, i);
1336 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1337 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1338 adapter->irq_tbl[irq_idx].vector =
da6f4cf5 1339 pci_irq_vector(adapter->pdev, irq_idx);
1738cd3e
NB		 1340 adapter->irq_tbl[irq_idx].cpu = cpu;
1341
1342 cpumask_set_cpu(cpu,
1343 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1344 }
1345}
1346
1347static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1348{
1349 unsigned long flags = 0;
1350 struct ena_irq *irq;
1351 int rc;
1352
1353 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1354 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1355 irq->data);
1356 if (rc) {
1357 netif_err(adapter, probe, adapter->netdev,
1358 "failed to request admin irq\n");
1359 return rc;
1360 }
1361
1362 netif_dbg(adapter, probe, adapter->netdev,
1363 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1364 irq->affinity_hint_mask.bits[0], irq->vector);
1365
1366 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1367
1368 return rc;
1369}
1370
1371static int ena_request_io_irq(struct ena_adapter *adapter)
1372{
1373 unsigned long flags = 0;
1374 struct ena_irq *irq;
1375 int rc = 0, i, k;
1376
1738cd3e
NB		 1377 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1378 irq = &adapter->irq_tbl[i];
1379 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1380 irq->data);
1381 if (rc) {
1382 netif_err(adapter, ifup, adapter->netdev,
1383 "Failed to request I/O IRQ. index %d rc %d\n",
1384 i, rc);
1385 goto err;
1386 }
1387
1388 netif_dbg(adapter, ifup, adapter->netdev,
1389 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1390 i, irq->affinity_hint_mask.bits[0], irq->vector);
1391
1392 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1393 }
1394
1395 return rc;
1396
1397err:
1398 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1399 irq = &adapter->irq_tbl[k];
1400 free_irq(irq->vector, irq->data);
1401 }
1402
1403 return rc;
1404}
1405
1406static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1407{
1408 struct ena_irq *irq;
1409
1410 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1411 synchronize_irq(irq->vector);
1412 irq_set_affinity_hint(irq->vector, NULL);
1413 free_irq(irq->vector, irq->data);
1414}
1415
1416static void ena_free_io_irq(struct ena_adapter *adapter)
1417{
1418 struct ena_irq *irq;
1419 int i;
1420
1421#ifdef CONFIG_RFS_ACCEL
1422 if (adapter->msix_vecs >= 1) {
1423 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1424 adapter->netdev->rx_cpu_rmap = NULL;
1425 }
1426#endif /* CONFIG_RFS_ACCEL */
1427
1428 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1429 irq = &adapter->irq_tbl[i];
1430 irq_set_affinity_hint(irq->vector, NULL);
1431 free_irq(irq->vector, irq->data);
1432 }
1433}
1434
1738cd3e
NB		 1435static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1436{
1437 int i;
1438
1439 if (!netif_running(adapter->netdev))
1440 return;
1441
1442 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1443 synchronize_irq(adapter->irq_tbl[i].vector);
1444}
1445
1446static void ena_del_napi(struct ena_adapter *adapter)
1447{
1448 int i;
1449
1450 for (i = 0; i < adapter->num_queues; i++)
1451 netif_napi_del(&adapter->ena_napi[i].napi);
1452}
1453
1454static void ena_init_napi(struct ena_adapter *adapter)
1455{
1456 struct ena_napi *napi;
1457 int i;
1458
1459 for (i = 0; i < adapter->num_queues; i++) {
1460 napi = &adapter->ena_napi[i];
1461
1462 netif_napi_add(adapter->netdev,
1463 &adapter->ena_napi[i].napi,
1464 ena_io_poll,
1465 ENA_NAPI_BUDGET);
1466 napi->rx_ring = &adapter->rx_ring[i];
1467 napi->tx_ring = &adapter->tx_ring[i];
1468 napi->qid = i;
1469 }
1470}
1471
1472static void ena_napi_disable_all(struct ena_adapter *adapter)
1473{
1474 int i;
1475
1476 for (i = 0; i < adapter->num_queues; i++)
1477 napi_disable(&adapter->ena_napi[i].napi);
1478}
1479
1480static void ena_napi_enable_all(struct ena_adapter *adapter)
1481{
1482 int i;
1483
1484 for (i = 0; i < adapter->num_queues; i++)
1485 napi_enable(&adapter->ena_napi[i].napi);
1486}
1487
1488static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1489{
1490 adapter->tx_usecs = 0;
1491 adapter->rx_usecs = 0;
1492 adapter->tx_frames = 1;
1493 adapter->rx_frames = 1;
1494}
1495
1496/* Configure the Rx forwarding */
1497static int ena_rss_configure(struct ena_adapter *adapter)
1498{
1499 struct ena_com_dev *ena_dev = adapter->ena_dev;
1500 int rc;
1501
1502 /* In case the RSS table wasn't initialized by probe */
1503 if (!ena_dev->rss.tbl_log_size) {
1504 rc = ena_rss_init_default(adapter);
d1497638 1505 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 1506 netif_err(adapter, ifup, adapter->netdev,
1507 "Failed to init RSS rc: %d\n", rc);
1508 return rc;
1509 }
1510 }
1511
1512 /* Set indirect table */
1513 rc = ena_com_indirect_table_set(ena_dev);
d1497638 1514 if (unlikely(rc && rc != -EOPNOTSUPP))
1738cd3e
NB		 1515 return rc;
1516
1517 /* Configure hash function (if supported) */
1518 rc = ena_com_set_hash_function(ena_dev);
d1497638 1519 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1520 return rc;
1521
1522 /* Configure hash inputs (if supported) */
1523 rc = ena_com_set_hash_ctrl(ena_dev);
d1497638 1524 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1525 return rc;
1526
1527 return 0;
1528}
1529
1530static int ena_up_complete(struct ena_adapter *adapter)
1531{
1532 int rc, i;
1533
1534 rc = ena_rss_configure(adapter);
1535 if (rc)
1536 return rc;
1537
1538 ena_init_napi(adapter);
1539
1540 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1541
1542 ena_refill_all_rx_bufs(adapter);
1543
1544 /* enable transmits */
1545 netif_tx_start_all_queues(adapter->netdev);
1546
1547 ena_restore_ethtool_params(adapter);
1548
1549 ena_napi_enable_all(adapter);
1550
418df30f
NB		 1551 /* Enable completion queues interrupt */
1552 for (i = 0; i < adapter->num_queues; i++)
1553 ena_unmask_interrupt(&adapter->tx_ring[i],
1554 &adapter->rx_ring[i]);
1555
1738cd3e
NB		 1556 /* schedule napi in case we had pending packets
1557 * from the last time we disable napi
1558 */
1559 for (i = 0; i < adapter->num_queues; i++)
1560 napi_schedule(&adapter->ena_napi[i].napi);
1561
1562 return 0;
1563}
1564
1565static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1566{
1567 struct ena_com_create_io_ctx ctx = { 0 };
1568 struct ena_com_dev *ena_dev;
1569 struct ena_ring *tx_ring;
1570 u32 msix_vector;
1571 u16 ena_qid;
1572 int rc;
1573
1574 ena_dev = adapter->ena_dev;
1575
1576 tx_ring = &adapter->tx_ring[qid];
1577 msix_vector = ENA_IO_IRQ_IDX(qid);
1578 ena_qid = ENA_IO_TXQ_IDX(qid);
1579
1580 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1581 ctx.qid = ena_qid;
1582 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1583 ctx.msix_vector = msix_vector;
1584 ctx.queue_size = adapter->tx_ring_size;
1585 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1586
1587 rc = ena_com_create_io_queue(ena_dev, &ctx);
1588 if (rc) {
1589 netif_err(adapter, ifup, adapter->netdev,
1590 "Failed to create I/O TX queue num %d rc: %d\n",
1591 qid, rc);
1592 return rc;
1593 }
1594
1595 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1596 &tx_ring->ena_com_io_sq,
1597 &tx_ring->ena_com_io_cq);
1598 if (rc) {
1599 netif_err(adapter, ifup, adapter->netdev,
1600 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1601 qid, rc);
1602 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1603 return rc;
1738cd3e
NB		 1604 }
1605
1606 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1607 return rc;
1608}
1609
1610static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1611{
1612 struct ena_com_dev *ena_dev = adapter->ena_dev;
1613 int rc, i;
1614
1615 for (i = 0; i < adapter->num_queues; i++) {
1616 rc = ena_create_io_tx_queue(adapter, i);
1617 if (rc)
1618 goto create_err;
1619 }
1620
1621 return 0;
1622
1623create_err:
1624 while (i--)
1625 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1626
1627 return rc;
1628}
1629
1630static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1631{
1632 struct ena_com_dev *ena_dev;
1633 struct ena_com_create_io_ctx ctx = { 0 };
1634 struct ena_ring *rx_ring;
1635 u32 msix_vector;
1636 u16 ena_qid;
1637 int rc;
1638
1639 ena_dev = adapter->ena_dev;
1640
1641 rx_ring = &adapter->rx_ring[qid];
1642 msix_vector = ENA_IO_IRQ_IDX(qid);
1643 ena_qid = ENA_IO_RXQ_IDX(qid);
1644
1645 ctx.qid = ena_qid;
1646 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1647 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1648 ctx.msix_vector = msix_vector;
1649 ctx.queue_size = adapter->rx_ring_size;
1650 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1651
1652 rc = ena_com_create_io_queue(ena_dev, &ctx);
1653 if (rc) {
1654 netif_err(adapter, ifup, adapter->netdev,
1655 "Failed to create I/O RX queue num %d rc: %d\n",
1656 qid, rc);
1657 return rc;
1658 }
1659
1660 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1661 &rx_ring->ena_com_io_sq,
1662 &rx_ring->ena_com_io_cq);
1663 if (rc) {
1664 netif_err(adapter, ifup, adapter->netdev,
1665 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1666 qid, rc);
1667 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1668 return rc;
1738cd3e
NB		 1669 }
1670
1671 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1672
1673 return rc;
1674}
1675
1676static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1677{
1678 struct ena_com_dev *ena_dev = adapter->ena_dev;
1679 int rc, i;
1680
1681 for (i = 0; i < adapter->num_queues; i++) {
1682 rc = ena_create_io_rx_queue(adapter, i);
1683 if (rc)
1684 goto create_err;
1685 }
1686
1687 return 0;
1688
1689create_err:
1690 while (i--)
1691 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1692
1693 return rc;
1694}
1695
1696static int ena_up(struct ena_adapter *adapter)
1697{
1698 int rc;
1699
1700 netdev_dbg(adapter->netdev, "%s\n", __func__);
1701
1702 ena_setup_io_intr(adapter);
1703
1704 rc = ena_request_io_irq(adapter);
1705 if (rc)
1706 goto err_req_irq;
1707
1708 /* allocate transmit descriptors */
1709 rc = ena_setup_all_tx_resources(adapter);
1710 if (rc)
1711 goto err_setup_tx;
1712
1713 /* allocate receive descriptors */
1714 rc = ena_setup_all_rx_resources(adapter);
1715 if (rc)
1716 goto err_setup_rx;
1717
1718 /* Create TX queues */
1719 rc = ena_create_all_io_tx_queues(adapter);
1720 if (rc)
1721 goto err_create_tx_queues;
1722
1723 /* Create RX queues */
1724 rc = ena_create_all_io_rx_queues(adapter);
1725 if (rc)
1726 goto err_create_rx_queues;
1727
1728 rc = ena_up_complete(adapter);
1729 if (rc)
1730 goto err_up;
1731
1732 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1733 netif_carrier_on(adapter->netdev);
1734
1735 u64_stats_update_begin(&adapter->syncp);
1736 adapter->dev_stats.interface_up++;
1737 u64_stats_update_end(&adapter->syncp);
1738
1739 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1740
1741 return rc;
1742
1743err_up:
1744 ena_destroy_all_rx_queues(adapter);
1745err_create_rx_queues:
1746 ena_destroy_all_tx_queues(adapter);
1747err_create_tx_queues:
1748 ena_free_all_io_rx_resources(adapter);
1749err_setup_rx:
1750 ena_free_all_io_tx_resources(adapter);
1751err_setup_tx:
1752 ena_free_io_irq(adapter);
1753err_req_irq:
1754
1755 return rc;
1756}
1757
1758static void ena_down(struct ena_adapter *adapter)
1759{
1760 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1761
1762 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1763
1764 u64_stats_update_begin(&adapter->syncp);
1765 adapter->dev_stats.interface_down++;
1766 u64_stats_update_end(&adapter->syncp);
1767
1738cd3e
NB		 1768 netif_carrier_off(adapter->netdev);
1769 netif_tx_disable(adapter->netdev);
1770
3f6159db
NB		 1771 /* After this point the napi handler won't enable the tx queue */
1772 ena_napi_disable_all(adapter);
1773
1738cd3e 1774 /* After destroy the queue there won't be any new interrupts */
3f6159db
NB		 1775
1776 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1777 int rc;
1778
e2eed0e3 1779 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
3f6159db
NB		 1780 if (rc)
1781 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1782 }
1783
1738cd3e
NB		 1784 ena_destroy_all_io_queues(adapter);
1785
1786 ena_disable_io_intr_sync(adapter);
1787 ena_free_io_irq(adapter);
1788 ena_del_napi(adapter);
1789
1790 ena_free_all_tx_bufs(adapter);
1791 ena_free_all_rx_bufs(adapter);
1792 ena_free_all_io_tx_resources(adapter);
1793 ena_free_all_io_rx_resources(adapter);
1794}
1795
1796/* ena_open - Called when a network interface is made active
1797 * @netdev: network interface device structure
1798 *
1799 * Returns 0 on success, negative value on failure
1800 *
1801 * The open entry point is called when a network interface is made
1802 * active by the system (IFF_UP). At this point all resources needed
1803 * for transmit and receive operations are allocated, the interrupt
1804 * handler is registered with the OS, the watchdog timer is started,
1805 * and the stack is notified that the interface is ready.
1806 */
1807static int ena_open(struct net_device *netdev)
1808{
1809 struct ena_adapter *adapter = netdev_priv(netdev);
1810 int rc;
1811
1812 /* Notify the stack of the actual queue counts. */
1813 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1814 if (rc) {
1815 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1816 return rc;
1817 }
1818
1819 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1820 if (rc) {
1821 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1822 return rc;
1823 }
1824
1825 rc = ena_up(adapter);
1826 if (rc)
1827 return rc;
1828
1829 return rc;
1830}
1831
1832/* ena_close - Disables a network interface
1833 * @netdev: network interface device structure
1834 *
1835 * Returns 0, this is not allowed to fail
1836 *
1837 * The close entry point is called when an interface is de-activated
1838 * by the OS. The hardware is still under the drivers control, but
1839 * needs to be disabled. A global MAC reset is issued to stop the
1840 * hardware, and all transmit and receive resources are freed.
1841 */
1842static int ena_close(struct net_device *netdev)
1843{
1844 struct ena_adapter *adapter = netdev_priv(netdev);
1845
1846 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1847
1848 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1849 ena_down(adapter);
1850
1851 return 0;
1852}
1853
1854static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1855{
1856 u32 mss = skb_shinfo(skb)->gso_size;
1857 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1858 u8 l4_protocol = 0;
1859
1860 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1861 ena_tx_ctx->l4_csum_enable = 1;
1862 if (mss) {
1863 ena_tx_ctx->tso_enable = 1;
1864 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1865 ena_tx_ctx->l4_csum_partial = 0;
1866 } else {
1867 ena_tx_ctx->tso_enable = 0;
1868 ena_meta->l4_hdr_len = 0;
1869 ena_tx_ctx->l4_csum_partial = 1;
1870 }
1871
1872 switch (ip_hdr(skb)->version) {
1873 case IPVERSION:
1874 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1875 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1876 ena_tx_ctx->df = 1;
1877 if (mss)
1878 ena_tx_ctx->l3_csum_enable = 1;
1879 l4_protocol = ip_hdr(skb)->protocol;
1880 break;
1881 case 6:
1882 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1883 l4_protocol = ipv6_hdr(skb)->nexthdr;
1884 break;
1885 default:
1886 break;
1887 }
1888
1889 if (l4_protocol == IPPROTO_TCP)
1890 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1891 else
1892 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1893
1894 ena_meta->mss = mss;
1895 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1896 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1897 ena_tx_ctx->meta_valid = 1;
1898
1899 } else {
1900 ena_tx_ctx->meta_valid = 0;
1901 }
1902}
1903
1904static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1905 struct sk_buff *skb)
1906{
1907 int num_frags, header_len, rc;
1908
1909 num_frags = skb_shinfo(skb)->nr_frags;
1910 header_len = skb_headlen(skb);
1911
1912 if (num_frags < tx_ring->sgl_size)
1913 return 0;
1914
1915 if ((num_frags == tx_ring->sgl_size) &&
1916 (header_len < tx_ring->tx_max_header_size))
1917 return 0;
1918
1919 u64_stats_update_begin(&tx_ring->syncp);
1920 tx_ring->tx_stats.linearize++;
1921 u64_stats_update_end(&tx_ring->syncp);
1922
1923 rc = skb_linearize(skb);
1924 if (unlikely(rc)) {
1925 u64_stats_update_begin(&tx_ring->syncp);
1926 tx_ring->tx_stats.linearize_failed++;
1927 u64_stats_update_end(&tx_ring->syncp);
1928 }
1929
1930 return rc;
1931}
1932
1933/* Called with netif_tx_lock. */
1934static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1935{
1936 struct ena_adapter *adapter = netdev_priv(dev);
1937 struct ena_tx_buffer *tx_info;
1938 struct ena_com_tx_ctx ena_tx_ctx;
1939 struct ena_ring *tx_ring;
1940 struct netdev_queue *txq;
1941 struct ena_com_buf *ena_buf;
1942 void *push_hdr;
1943 u32 len, last_frag;
1944 u16 next_to_use;
1945 u16 req_id;
1946 u16 push_len;
1947 u16 header_len;
1948 dma_addr_t dma;
1949 int qid, rc, nb_hw_desc;
1950 int i = -1;
1951
1952 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
1953 /* Determine which tx ring we will be placed on */
1954 qid = skb_get_queue_mapping(skb);
1955 tx_ring = &adapter->tx_ring[qid];
1956 txq = netdev_get_tx_queue(dev, qid);
1957
1958 rc = ena_check_and_linearize_skb(tx_ring, skb);
1959 if (unlikely(rc))
1960 goto error_drop_packet;
1961
1962 skb_tx_timestamp(skb);
1963 len = skb_headlen(skb);
1964
1965 next_to_use = tx_ring->next_to_use;
1966 req_id = tx_ring->free_tx_ids[next_to_use];
1967 tx_info = &tx_ring->tx_buffer_info[req_id];
1968 tx_info->num_of_bufs = 0;
1969
1970 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
1971 ena_buf = tx_info->bufs;
1972 tx_info->skb = skb;
1973
1974 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1975 /* prepared the push buffer */
1976 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
1977 header_len = push_len;
1978 push_hdr = skb->data;
1979 } else {
1980 push_len = 0;
1981 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
1982 push_hdr = NULL;
1983 }
1984
1985 netif_dbg(adapter, tx_queued, dev,
1986 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
1987 push_hdr, push_len);
1988
1989 if (len > push_len) {
1990 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
1991 len - push_len, DMA_TO_DEVICE);
1992 if (dma_mapping_error(tx_ring->dev, dma))
1993 goto error_report_dma_error;
1994
1995 ena_buf->paddr = dma;
1996 ena_buf->len = len - push_len;
1997
1998 ena_buf++;
1999 tx_info->num_of_bufs++;
2000 }
2001
2002 last_frag = skb_shinfo(skb)->nr_frags;
2003
2004 for (i = 0; i < last_frag; i++) {
2005 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2006
2007 len = skb_frag_size(frag);
2008 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
2009 DMA_TO_DEVICE);
2010 if (dma_mapping_error(tx_ring->dev, dma))
2011 goto error_report_dma_error;
2012
2013 ena_buf->paddr = dma;
2014 ena_buf->len = len;
2015 ena_buf++;
2016 }
2017
2018 tx_info->num_of_bufs += last_frag;
2019
2020 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2021 ena_tx_ctx.ena_bufs = tx_info->bufs;
2022 ena_tx_ctx.push_header = push_hdr;
2023 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2024 ena_tx_ctx.req_id = req_id;
2025 ena_tx_ctx.header_len = header_len;
2026
2027 /* set flags and meta data */
2028 ena_tx_csum(&ena_tx_ctx, skb);
2029
2030 /* prepare the packet's descriptors to dma engine */
2031 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2032 &nb_hw_desc);
2033
2034 if (unlikely(rc)) {
2035 netif_err(adapter, tx_queued, dev,
2036 "failed to prepare tx bufs\n");
2037 u64_stats_update_begin(&tx_ring->syncp);
2038 tx_ring->tx_stats.queue_stop++;
2039 tx_ring->tx_stats.prepare_ctx_err++;
2040 u64_stats_update_end(&tx_ring->syncp);
2041 netif_tx_stop_queue(txq);
2042 goto error_unmap_dma;
2043 }
2044
2045 netdev_tx_sent_queue(txq, skb->len);
2046
2047 u64_stats_update_begin(&tx_ring->syncp);
2048 tx_ring->tx_stats.cnt++;
2049 tx_ring->tx_stats.bytes += skb->len;
2050 u64_stats_update_end(&tx_ring->syncp);
2051
2052 tx_info->tx_descs = nb_hw_desc;
2053 tx_info->last_jiffies = jiffies;
800c55cb 2054 tx_info->print_once = 0;
1738cd3e
NB		 2055
2056 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2057 tx_ring->ring_size);
2058
2059 /* This WMB is aimed to:
2060 * 1 - perform smp barrier before reading next_to_completion
2061 * 2 - make sure the desc were written before trigger DB
2062 */
2063 wmb();
2064
2065 /* stop the queue when no more space available, the packet can have up
2066 * to sgl_size + 2. one for the meta descriptor and one for header
2067 * (if the header is larger than tx_max_header_size).
2068 */
2069 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2070 (tx_ring->sgl_size + 2))) {
2071 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2072 __func__, qid);
2073
2074 netif_tx_stop_queue(txq);
2075 u64_stats_update_begin(&tx_ring->syncp);
2076 tx_ring->tx_stats.queue_stop++;
2077 u64_stats_update_end(&tx_ring->syncp);
2078
2079 /* There is a rare condition where this function decide to
2080 * stop the queue but meanwhile clean_tx_irq updates
2081 * next_to_completion and terminates.
2082 * The queue will remain stopped forever.
2083 * To solve this issue this function perform rmb, check
2084 * the wakeup condition and wake up the queue if needed.
2085 */
2086 smp_rmb();
2087
2088 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2089 > ENA_TX_WAKEUP_THRESH) {
2090 netif_tx_wake_queue(txq);
2091 u64_stats_update_begin(&tx_ring->syncp);
2092 tx_ring->tx_stats.queue_wakeup++;
2093 u64_stats_update_end(&tx_ring->syncp);
2094 }
2095 }
2096
2097 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2098 /* trigger the dma engine */
2099 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2100 u64_stats_update_begin(&tx_ring->syncp);
2101 tx_ring->tx_stats.doorbells++;
2102 u64_stats_update_end(&tx_ring->syncp);
2103 }
2104
2105 return NETDEV_TX_OK;
2106
2107error_report_dma_error:
2108 u64_stats_update_begin(&tx_ring->syncp);
2109 tx_ring->tx_stats.dma_mapping_err++;
2110 u64_stats_update_end(&tx_ring->syncp);
2111 netdev_warn(adapter->netdev, "failed to map skb\n");
2112
2113 tx_info->skb = NULL;
2114
2115error_unmap_dma:
2116 if (i >= 0) {
2117 /* save value of frag that failed */
2118 last_frag = i;
2119
2120 /* start back at beginning and unmap skb */
2121 tx_info->skb = NULL;
2122 ena_buf = tx_info->bufs;
2123 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2124 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2125
2126 /* unmap remaining mapped pages */
2127 for (i = 0; i < last_frag; i++) {
2128 ena_buf++;
2129 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2130 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2131 }
2132 }
2133
2134error_drop_packet:
2135
2136 dev_kfree_skb(skb);
2137 return NETDEV_TX_OK;
2138}
2139
2140#ifdef CONFIG_NET_POLL_CONTROLLER
2141static void ena_netpoll(struct net_device *netdev)
2142{
2143 struct ena_adapter *adapter = netdev_priv(netdev);
2144 int i;
2145
3f6159db
NB		 2146 /* Dont schedule NAPI if the driver is in the middle of reset
2147 * or netdev is down.
2148 */
2149
2150 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2151 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2152 return;
2153
1738cd3e
NB		 2154 for (i = 0; i < adapter->num_queues; i++)
2155 napi_schedule(&adapter->ena_napi[i].napi);
2156}
2157#endif /* CONFIG_NET_POLL_CONTROLLER */
2158
2159static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2160 void *accel_priv, select_queue_fallback_t fallback)
2161{
2162 u16 qid;
2163 /* we suspect that this is good for in--kernel network services that
2164 * want to loop incoming skb rx to tx in normal user generated traffic,
2165 * most probably we will not get to this
2166 */
2167 if (skb_rx_queue_recorded(skb))
2168 qid = skb_get_rx_queue(skb);
2169 else
2170 qid = fallback(dev, skb);
2171
2172 return qid;
2173}
2174
2175static void ena_config_host_info(struct ena_com_dev *ena_dev)
2176{
2177 struct ena_admin_host_info *host_info;
2178 int rc;
2179
2180 /* Allocate only the host info */
2181 rc = ena_com_allocate_host_info(ena_dev);
2182 if (rc) {
2183 pr_err("Cannot allocate host info\n");
2184 return;
2185 }
2186
2187 host_info = ena_dev->host_attr.host_info;
2188
2189 host_info->os_type = ENA_ADMIN_OS_LINUX;
2190 host_info->kernel_ver = LINUX_VERSION_CODE;
2191 strncpy(host_info->kernel_ver_str, utsname()->version,
2192 sizeof(host_info->kernel_ver_str) - 1);
2193 host_info->os_dist = 0;
2194 strncpy(host_info->os_dist_str, utsname()->release,
2195 sizeof(host_info->os_dist_str) - 1);
2196 host_info->driver_version =
2197 (DRV_MODULE_VER_MAJOR) |
2198 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2199 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2200
2201 rc = ena_com_set_host_attributes(ena_dev);
2202 if (rc) {
d1497638 2203 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2204 pr_warn("Cannot set host attributes\n");
2205 else
2206 pr_err("Cannot set host attributes\n");
2207
2208 goto err;
2209 }
2210
2211 return;
2212
2213err:
2214 ena_com_delete_host_info(ena_dev);
2215}
2216
2217static void ena_config_debug_area(struct ena_adapter *adapter)
2218{
2219 u32 debug_area_size;
2220 int rc, ss_count;
2221
2222 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2223 if (ss_count <= 0) {
2224 netif_err(adapter, drv, adapter->netdev,
2225 "SS count is negative\n");
2226 return;
2227 }
2228
2229 /* allocate 32 bytes for each string and 64bit for the value */
2230 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2231
2232 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2233 if (rc) {
2234 pr_err("Cannot allocate debug area\n");
2235 return;
2236 }
2237
2238 rc = ena_com_set_host_attributes(adapter->ena_dev);
2239 if (rc) {
d1497638 2240 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2241 netif_warn(adapter, drv, adapter->netdev,
2242 "Cannot set host attributes\n");
2243 else
2244 netif_err(adapter, drv, adapter->netdev,
2245 "Cannot set host attributes\n");
2246 goto err;
2247 }
2248
2249 return;
2250err:
2251 ena_com_delete_debug_area(adapter->ena_dev);
2252}
2253
bc1f4470 2254static void ena_get_stats64(struct net_device *netdev,
2255 struct rtnl_link_stats64 *stats)
1738cd3e
NB		 2256{
2257 struct ena_adapter *adapter = netdev_priv(netdev);
d81db240
NB		 2258 struct ena_ring *rx_ring, *tx_ring;
2259 unsigned int start;
2260 u64 rx_drops;
2261 int i;
1738cd3e
NB		 2262
2263 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
bc1f4470 2264 return;
1738cd3e 2265
d81db240
NB		 2266 for (i = 0; i < adapter->num_queues; i++) {
2267 u64 bytes, packets;
2268
2269 tx_ring = &adapter->tx_ring[i];
1738cd3e 2270
d81db240
NB		 2271 do {
2272 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2273 packets = tx_ring->tx_stats.cnt;
2274 bytes = tx_ring->tx_stats.bytes;
2275 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
1738cd3e 2276
d81db240
NB		 2277 stats->tx_packets += packets;
2278 stats->tx_bytes += bytes;
2279
2280 rx_ring = &adapter->rx_ring[i];
2281
2282 do {
2283 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2284 packets = rx_ring->rx_stats.cnt;
2285 bytes = rx_ring->rx_stats.bytes;
2286 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2287
2288 stats->rx_packets += packets;
2289 stats->rx_bytes += bytes;
2290 }
2291
2292 do {
2293 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2294 rx_drops = adapter->dev_stats.rx_drops;
2295 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
1738cd3e 2296
d81db240 2297 stats->rx_dropped = rx_drops;
1738cd3e
NB		 2298
2299 stats->multicast = 0;
2300 stats->collisions = 0;
2301
2302 stats->rx_length_errors = 0;
2303 stats->rx_crc_errors = 0;
2304 stats->rx_frame_errors = 0;
2305 stats->rx_fifo_errors = 0;
2306 stats->rx_missed_errors = 0;
2307 stats->tx_window_errors = 0;
2308
2309 stats->rx_errors = 0;
2310 stats->tx_errors = 0;
1738cd3e
NB		 2311}
2312
2313static const struct net_device_ops ena_netdev_ops = {
2314 .ndo_open = ena_open,
2315 .ndo_stop = ena_close,
2316 .ndo_start_xmit = ena_start_xmit,
2317 .ndo_select_queue = ena_select_queue,
2318 .ndo_get_stats64 = ena_get_stats64,
2319 .ndo_tx_timeout = ena_tx_timeout,
2320 .ndo_change_mtu = ena_change_mtu,
2321 .ndo_set_mac_address = NULL,
2322 .ndo_validate_addr = eth_validate_addr,
2323#ifdef CONFIG_NET_POLL_CONTROLLER
2324 .ndo_poll_controller = ena_netpoll,
2325#endif /* CONFIG_NET_POLL_CONTROLLER */
2326};
2327
2328static void ena_device_io_suspend(struct work_struct *work)
2329{
2330 struct ena_adapter *adapter =
2331 container_of(work, struct ena_adapter, suspend_io_task);
2332 struct net_device *netdev = adapter->netdev;
2333
2334 /* ena_napi_disable_all disables only the IO handling.
2335 * We are still subject to AENQ keep alive watchdog.
2336 */
2337 u64_stats_update_begin(&adapter->syncp);
2338 adapter->dev_stats.io_suspend++;
2339 u64_stats_update_begin(&adapter->syncp);
2340 ena_napi_disable_all(adapter);
2341 netif_tx_lock(netdev);
2342 netif_device_detach(netdev);
2343 netif_tx_unlock(netdev);
2344}
2345
2346static void ena_device_io_resume(struct work_struct *work)
2347{
2348 struct ena_adapter *adapter =
2349 container_of(work, struct ena_adapter, resume_io_task);
2350 struct net_device *netdev = adapter->netdev;
2351
2352 u64_stats_update_begin(&adapter->syncp);
2353 adapter->dev_stats.io_resume++;
2354 u64_stats_update_end(&adapter->syncp);
2355
2356 netif_device_attach(netdev);
2357 ena_napi_enable_all(adapter);
2358}
2359
2360static int ena_device_validate_params(struct ena_adapter *adapter,
2361 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2362{
2363 struct net_device *netdev = adapter->netdev;
2364 int rc;
2365
2366 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2367 adapter->mac_addr);
2368 if (!rc) {
2369 netif_err(adapter, drv, netdev,
2370 "Error, mac address are different\n");
2371 return -EINVAL;
2372 }
2373
2374 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2375 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2376 netif_err(adapter, drv, netdev,
2377 "Error, device doesn't support enough queues\n");
2378 return -EINVAL;
2379 }
2380
2381 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2382 netif_err(adapter, drv, netdev,
2383 "Error, device max mtu is smaller than netdev MTU\n");
2384 return -EINVAL;
2385 }
2386
2387 return 0;
2388}
2389
2390static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2391 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2392 bool *wd_state)
2393{
2394 struct device *dev = &pdev->dev;
2395 bool readless_supported;
2396 u32 aenq_groups;
2397 int dma_width;
2398 int rc;
2399
2400 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2401 if (rc) {
2402 dev_err(dev, "failed to init mmio read less\n");
2403 return rc;
2404 }
2405
2406 /* The PCIe configuration space revision id indicate if mmio reg
2407 * read is disabled
2408 */
2409 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2410 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2411
e2eed0e3 2412 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1738cd3e
NB		 2413 if (rc) {
2414 dev_err(dev, "Can not reset device\n");
2415 goto err_mmio_read_less;
2416 }
2417
2418 rc = ena_com_validate_version(ena_dev);
2419 if (rc) {
2420 dev_err(dev, "device version is too low\n");
2421 goto err_mmio_read_less;
2422 }
2423
2424 dma_width = ena_com_get_dma_width(ena_dev);
2425 if (dma_width < 0) {
2426 dev_err(dev, "Invalid dma width value %d", dma_width);
6e22066f 2427 rc = dma_width;
1738cd3e
NB		 2428 goto err_mmio_read_less;
2429 }
2430
2431 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2432 if (rc) {
2433 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2434 goto err_mmio_read_less;
2435 }
2436
2437 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2438 if (rc) {
2439 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2440 rc);
2441 goto err_mmio_read_less;
2442 }
2443
2444 /* ENA admin level init */
2445 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2446 if (rc) {
2447 dev_err(dev,
2448 "Can not initialize ena admin queue with device\n");
2449 goto err_mmio_read_less;
2450 }
2451
2452 /* To enable the msix interrupts the driver needs to know the number
2453 * of queues. So the driver uses polling mode to retrieve this
2454 * information
2455 */
2456 ena_com_set_admin_polling_mode(ena_dev, true);
2457
dd8427a7
NB		 2458 ena_config_host_info(ena_dev);
2459
1738cd3e
NB		 2460 /* Get Device Attributes*/
2461 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2462 if (rc) {
2463 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2464 goto err_admin_init;
2465 }
2466
2467 /* Try to turn all the available aenq groups */
2468 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2469 BIT(ENA_ADMIN_FATAL_ERROR) |
2470 BIT(ENA_ADMIN_WARNING) |
2471 BIT(ENA_ADMIN_NOTIFICATION) |
2472 BIT(ENA_ADMIN_KEEP_ALIVE);
2473
2474 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2475
2476 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2477 if (rc) {
2478 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2479 goto err_admin_init;
2480 }
2481
2482 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2483
1738cd3e
NB		 2484 return 0;
2485
2486err_admin_init:
dd8427a7 2487 ena_com_delete_host_info(ena_dev);
1738cd3e
NB		 2488 ena_com_admin_destroy(ena_dev);
2489err_mmio_read_less:
2490 ena_com_mmio_reg_read_request_destroy(ena_dev);
2491
2492 return rc;
2493}
2494
2495static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2496 int io_vectors)
2497{
2498 struct ena_com_dev *ena_dev = adapter->ena_dev;
2499 struct device *dev = &adapter->pdev->dev;
2500 int rc;
2501
2502 rc = ena_enable_msix(adapter, io_vectors);
2503 if (rc) {
2504 dev_err(dev, "Can not reserve msix vectors\n");
2505 return rc;
2506 }
2507
2508 ena_setup_mgmnt_intr(adapter);
2509
2510 rc = ena_request_mgmnt_irq(adapter);
2511 if (rc) {
2512 dev_err(dev, "Can not setup management interrupts\n");
2513 goto err_disable_msix;
2514 }
2515
2516 ena_com_set_admin_polling_mode(ena_dev, false);
2517
2518 ena_com_admin_aenq_enable(ena_dev);
2519
2520 return 0;
2521
2522err_disable_msix:
da6f4cf5 2523 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2524 return rc;
2525}
2526
2527static void ena_fw_reset_device(struct work_struct *work)
2528{
2529 struct ena_com_dev_get_features_ctx get_feat_ctx;
2530 struct ena_adapter *adapter =
2531 container_of(work, struct ena_adapter, reset_task);
2532 struct net_device *netdev = adapter->netdev;
2533 struct ena_com_dev *ena_dev = adapter->ena_dev;
2534 struct pci_dev *pdev = adapter->pdev;
2535 bool dev_up, wd_state;
2536 int rc;
2537
3f6159db
NB		 2538 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2539 dev_err(&pdev->dev,
2540 "device reset schedule while reset bit is off\n");
2541 return;
2542 }
2543
2544 netif_carrier_off(netdev);
2545
1738cd3e
NB		 2546 del_timer_sync(&adapter->timer_service);
2547
2548 rtnl_lock();
2549
2550 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2551 ena_com_set_admin_running_state(ena_dev, false);
2552
2553 /* After calling ena_close the tx queues and the napi
2554 * are disabled so no one can interfere or touch the
2555 * data structures
2556 */
2557 ena_close(netdev);
2558
1738cd3e
NB		 2559 ena_free_mgmnt_irq(adapter);
2560
da6f4cf5 2561 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2562
2563 ena_com_abort_admin_commands(ena_dev);
2564
2565 ena_com_wait_for_abort_completion(ena_dev);
2566
2567 ena_com_admin_destroy(ena_dev);
2568
2569 ena_com_mmio_reg_read_request_destroy(ena_dev);
2570
e2eed0e3 2571 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
3f6159db
NB		 2572 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2573
1738cd3e
NB		 2574 /* Finish with the destroy part. Start the init part */
2575
2576 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2577 if (rc) {
2578 dev_err(&pdev->dev, "Can not initialize device\n");
2579 goto err;
2580 }
2581 adapter->wd_state = wd_state;
2582
2583 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2584 if (rc) {
2585 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2586 goto err_device_destroy;
2587 }
2588
2589 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2590 adapter->num_queues);
2591 if (rc) {
2592 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2593 goto err_device_destroy;
2594 }
2595 /* If the interface was up before the reset bring it up */
2596 if (dev_up) {
2597 rc = ena_up(adapter);
2598 if (rc) {
2599 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2600 goto err_disable_msix;
2601 }
2602 }
2603
2604 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2605
2606 rtnl_unlock();
2607
2608 dev_err(&pdev->dev, "Device reset completed successfully\n");
2609
2610 return;
2611err_disable_msix:
2612 ena_free_mgmnt_irq(adapter);
da6f4cf5 2613 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 2614err_device_destroy:
2615 ena_com_admin_destroy(ena_dev);
2616err:
2617 rtnl_unlock();
2618
22b331c9
NB		 2619 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2620
1738cd3e
NB		 2621 dev_err(&pdev->dev,
2622 "Reset attempt failed. Can not reset the device\n");
2623}
2624
800c55cb
NB		 2625static int check_missing_comp_in_queue(struct ena_adapter *adapter,
2626 struct ena_ring *tx_ring)
1738cd3e
NB		 2627{
2628 struct ena_tx_buffer *tx_buf;
2629 unsigned long last_jiffies;
800c55cb
NB		 2630 u32 missed_tx = 0;
2631 int i;
2632
2633 for (i = 0; i < tx_ring->ring_size; i++) {
2634 tx_buf = &tx_ring->tx_buffer_info[i];
2635 last_jiffies = tx_buf->last_jiffies;
2636 if (unlikely(last_jiffies &&
82ef30f1 2637 time_is_before_jiffies(last_jiffies + adapter->missing_tx_completion_to))) {
800c55cb
NB		 2638 if (!tx_buf->print_once)
2639 netif_notice(adapter, tx_err, adapter->netdev,
2640 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2641 tx_ring->qid, i);
2642
2643 tx_buf->print_once = 1;
2644 missed_tx++;
2645
82ef30f1 2646 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) {
800c55cb
NB		 2647 netif_err(adapter, tx_err, adapter->netdev,
2648 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
82ef30f1
NB		 2649 missed_tx,
2650 adapter->missing_tx_completion_threshold);
e2eed0e3
NB		 2651 adapter->reset_reason =
2652 ENA_REGS_RESET_MISS_TX_CMPL;
800c55cb
NB		 2653 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2654 return -EIO;
2655 }
2656 }
2657 }
2658
2659 return 0;
2660}
2661
2662static void check_for_missing_tx_completions(struct ena_adapter *adapter)
2663{
1738cd3e 2664 struct ena_ring *tx_ring;
800c55cb 2665 int i, budget, rc;
1738cd3e
NB		 2666
2667 /* Make sure the driver doesn't turn the device in other process */
2668 smp_rmb();
2669
2670 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2671 return;
2672
3f6159db
NB		 2673 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2674 return;
2675
82ef30f1
NB		 2676 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
2677 return;
2678
1738cd3e
NB		 2679 budget = ENA_MONITORED_TX_QUEUES;
2680
2681 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2682 tx_ring = &adapter->tx_ring[i];
2683
800c55cb
NB		 2684 rc = check_missing_comp_in_queue(adapter, tx_ring);
2685 if (unlikely(rc))
2686 return;
1738cd3e
NB		 2687
2688 budget--;
2689 if (!budget)
2690 break;
2691 }
2692
2693 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2694}
2695
a3af7c18
NB		 2696/* trigger napi schedule after 2 consecutive detections */
2697#define EMPTY_RX_REFILL 2
2698/* For the rare case where the device runs out of Rx descriptors and the
2699 * napi handler failed to refill new Rx descriptors (due to a lack of memory
2700 * for example).
2701 * This case will lead to a deadlock:
2702 * The device won't send interrupts since all the new Rx packets will be dropped
2703 * The napi handler won't allocate new Rx descriptors so the device will be
2704 * able to send new packets.
2705 *
2706 * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
2707 * It is recommended to have at least 512MB, with a minimum of 128MB for
2708 * constrained environment).
2709 *
2710 * When such a situation is detected - Reschedule napi
2711 */
2712static void check_for_empty_rx_ring(struct ena_adapter *adapter)
2713{
2714 struct ena_ring *rx_ring;
2715 int i, refill_required;
2716
2717 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2718 return;
2719
2720 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2721 return;
2722
2723 for (i = 0; i < adapter->num_queues; i++) {
2724 rx_ring = &adapter->rx_ring[i];
2725
2726 refill_required =
2727 ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
2728 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
2729 rx_ring->empty_rx_queue++;
2730
2731 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
2732 u64_stats_update_begin(&rx_ring->syncp);
2733 rx_ring->rx_stats.empty_rx_ring++;
2734 u64_stats_update_end(&rx_ring->syncp);
2735
2736 netif_err(adapter, drv, adapter->netdev,
2737 "trigger refill for ring %d\n", i);
2738
2739 napi_schedule(rx_ring->napi);
2740 rx_ring->empty_rx_queue = 0;
2741 }
2742 } else {
2743 rx_ring->empty_rx_queue = 0;
2744 }
2745 }
2746}
2747
1738cd3e
NB		 2748/* Check for keep alive expiration */
2749static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2750{
2751 unsigned long keep_alive_expired;
2752
2753 if (!adapter->wd_state)
2754 return;
2755
82ef30f1
NB		 2756 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2757 return;
2758
2759 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies +
2760 adapter->keep_alive_timeout);
1738cd3e
NB		 2761 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2762 netif_err(adapter, drv, adapter->netdev,
2763 "Keep alive watchdog timeout.\n");
2764 u64_stats_update_begin(&adapter->syncp);
2765 adapter->dev_stats.wd_expired++;
2766 u64_stats_update_end(&adapter->syncp);
e2eed0e3 2767 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1738cd3e
NB		 2768 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2769 }
2770}
2771
2772static void check_for_admin_com_state(struct ena_adapter *adapter)
2773{
2774 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2775 netif_err(adapter, drv, adapter->netdev,
2776 "ENA admin queue is not in running state!\n");
2777 u64_stats_update_begin(&adapter->syncp);
2778 adapter->dev_stats.admin_q_pause++;
2779 u64_stats_update_end(&adapter->syncp);
e2eed0e3 2780 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1738cd3e
NB		 2781 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2782 }
2783}
2784
82ef30f1
NB		 2785static void ena_update_hints(struct ena_adapter *adapter,
2786 struct ena_admin_ena_hw_hints *hints)
2787{
2788 struct net_device *netdev = adapter->netdev;
2789
2790 if (hints->admin_completion_tx_timeout)
2791 adapter->ena_dev->admin_queue.completion_timeout =
2792 hints->admin_completion_tx_timeout * 1000;
2793
2794 if (hints->mmio_read_timeout)
2795 /* convert to usec */
2796 adapter->ena_dev->mmio_read.reg_read_to =
2797 hints->mmio_read_timeout * 1000;
2798
2799 if (hints->missed_tx_completion_count_threshold_to_reset)
2800 adapter->missing_tx_completion_threshold =
2801 hints->missed_tx_completion_count_threshold_to_reset;
2802
2803 if (hints->missing_tx_completion_timeout) {
2804 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2805 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT;
2806 else
2807 adapter->missing_tx_completion_to =
2808 msecs_to_jiffies(hints->missing_tx_completion_timeout);
2809 }
2810
2811 if (hints->netdev_wd_timeout)
2812 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout);
2813
2814 if (hints->driver_watchdog_timeout) {
2815 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2816 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2817 else
2818 adapter->keep_alive_timeout =
2819 msecs_to_jiffies(hints->driver_watchdog_timeout);
2820 }
2821}
2822
1738cd3e
NB		 2823static void ena_update_host_info(struct ena_admin_host_info *host_info,
2824 struct net_device *netdev)
2825{
2826 host_info->supported_network_features[0] =
2827 netdev->features & GENMASK_ULL(31, 0);
2828 host_info->supported_network_features[1] =
2829 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2830}
2831
2832static void ena_timer_service(unsigned long data)
2833{
2834 struct ena_adapter *adapter = (struct ena_adapter *)data;
2835 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2836 struct ena_admin_host_info *host_info =
2837 adapter->ena_dev->host_attr.host_info;
2838
2839 check_for_missing_keep_alive(adapter);
2840
2841 check_for_admin_com_state(adapter);
2842
2843 check_for_missing_tx_completions(adapter);
2844
a3af7c18
NB		 2845 check_for_empty_rx_ring(adapter);
2846
1738cd3e
NB		 2847 if (debug_area)
2848 ena_dump_stats_to_buf(adapter, debug_area);
2849
2850 if (host_info)
2851 ena_update_host_info(host_info, adapter->netdev);
2852
3f6159db 2853 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1738cd3e
NB		 2854 netif_err(adapter, drv, adapter->netdev,
2855 "Trigger reset is on\n");
2856 ena_dump_stats_to_dmesg(adapter);
2857 queue_work(ena_wq, &adapter->reset_task);
2858 return;
2859 }
2860
2861 /* Reset the timer */
2862 mod_timer(&adapter->timer_service, jiffies + HZ);
2863}
2864
2865static int ena_calc_io_queue_num(struct pci_dev *pdev,
2866 struct ena_com_dev *ena_dev,
2867 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2868{
2869 int io_sq_num, io_queue_num;
2870
2871 /* In case of LLQ use the llq number in the get feature cmd */
2872 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2873 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2874
2875 if (io_sq_num == 0) {
2876 dev_err(&pdev->dev,
2877 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2878
2879 ena_dev->tx_mem_queue_type =
2880 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2881 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2882 }
2883 } else {
2884 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2885 }
2886
6a1ce2fb 2887 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
1738cd3e
NB		 2888 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2889 io_queue_num = min_t(int, io_queue_num,
2890 get_feat_ctx->max_queues.max_cq_num);
2891 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2892 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2893 if (unlikely(!io_queue_num)) {
2894 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2895 return -EFAULT;
2896 }
2897
2898 return io_queue_num;
2899}
2900
184b49c8
RR		 2901static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
2902 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1738cd3e
NB		 2903{
2904 bool has_mem_bar;
2905
2906 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
2907
2908 /* Enable push mode if device supports LLQ */
2909 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
2910 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2911 else
2912 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1738cd3e
NB		 2913}
2914
2915static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
2916 struct net_device *netdev)
2917{
2918 netdev_features_t dev_features = 0;
2919
2920 /* Set offload features */
2921 if (feat->offload.tx &
2922 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2923 dev_features |= NETIF_F_IP_CSUM;
2924
2925 if (feat->offload.tx &
2926 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2927 dev_features |= NETIF_F_IPV6_CSUM;
2928
2929 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2930 dev_features |= NETIF_F_TSO;
2931
2932 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
2933 dev_features |= NETIF_F_TSO6;
2934
2935 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
2936 dev_features |= NETIF_F_TSO_ECN;
2937
2938 if (feat->offload.rx_supported &
2939 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2940 dev_features |= NETIF_F_RXCSUM;
2941
2942 if (feat->offload.rx_supported &
2943 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2944 dev_features |= NETIF_F_RXCSUM;
2945
2946 netdev->features =
2947 dev_features |
2948 NETIF_F_SG |
1738cd3e
NB		 2949 NETIF_F_RXHASH |
2950 NETIF_F_HIGHDMA;
2951
2952 netdev->hw_features |= netdev->features;
2953 netdev->vlan_features |= netdev->features;
2954}
2955
2956static void ena_set_conf_feat_params(struct ena_adapter *adapter,
2957 struct ena_com_dev_get_features_ctx *feat)
2958{
2959 struct net_device *netdev = adapter->netdev;
2960
2961 /* Copy mac address */
2962 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
2963 eth_hw_addr_random(netdev);
2964 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
2965 } else {
2966 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
2967 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
2968 }
2969
2970 /* Set offload features */
2971 ena_set_dev_offloads(feat, netdev);
2972
2973 adapter->max_mtu = feat->dev_attr.max_mtu;
d894be57
JW		 2974 netdev->max_mtu = adapter->max_mtu;
2975 netdev->min_mtu = ENA_MIN_MTU;
1738cd3e
NB		 2976}
2977
2978static int ena_rss_init_default(struct ena_adapter *adapter)
2979{
2980 struct ena_com_dev *ena_dev = adapter->ena_dev;
2981 struct device *dev = &adapter->pdev->dev;
2982 int rc, i;
2983 u32 val;
2984
2985 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2986 if (unlikely(rc)) {
2987 dev_err(dev, "Cannot init indirect table\n");
2988 goto err_rss_init;
2989 }
2990
2991 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
2992 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
2993 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
2994 ENA_IO_RXQ_IDX(val));
d1497638 2995 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 2996 dev_err(dev, "Cannot fill indirect table\n");
2997 goto err_fill_indir;
2998 }
2999 }
3000
3001 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
3002 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
d1497638 3003 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3004 dev_err(dev, "Cannot fill hash function\n");
3005 goto err_fill_indir;
3006 }
3007
3008 rc = ena_com_set_default_hash_ctrl(ena_dev);
d1497638 3009 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3010 dev_err(dev, "Cannot fill hash control\n");
3011 goto err_fill_indir;
3012 }
3013
3014 return 0;
3015
3016err_fill_indir:
3017 ena_com_rss_destroy(ena_dev);
3018err_rss_init:
3019
3020 return rc;
3021}
3022
3023static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
3024{
3025 int release_bars;
3026
0857d92f
NB		 3027 if (ena_dev->mem_bar)
3028 devm_iounmap(&pdev->dev, ena_dev->mem_bar);
3029
3030 devm_iounmap(&pdev->dev, ena_dev->reg_bar);
3031
1738cd3e
NB		 3032 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3033 pci_release_selected_regions(pdev, release_bars);
3034}
3035
3036static int ena_calc_queue_size(struct pci_dev *pdev,
3037 struct ena_com_dev *ena_dev,
3038 u16 *max_tx_sgl_size,
3039 u16 *max_rx_sgl_size,
3040 struct ena_com_dev_get_features_ctx *get_feat_ctx)
3041{
3042 u32 queue_size = ENA_DEFAULT_RING_SIZE;
3043
3044 queue_size = min_t(u32, queue_size,
3045 get_feat_ctx->max_queues.max_cq_depth);
3046 queue_size = min_t(u32, queue_size,
3047 get_feat_ctx->max_queues.max_sq_depth);
3048
3049 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3050 queue_size = min_t(u32, queue_size,
3051 get_feat_ctx->max_queues.max_llq_depth);
3052
3053 queue_size = rounddown_pow_of_two(queue_size);
3054
3055 if (unlikely(!queue_size)) {
3056 dev_err(&pdev->dev, "Invalid queue size\n");
3057 return -EFAULT;
3058 }
3059
3060 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3061 get_feat_ctx->max_queues.max_packet_tx_descs);
3062 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3063 get_feat_ctx->max_queues.max_packet_rx_descs);
3064
3065 return queue_size;
3066}
3067
3068/* ena_probe - Device Initialization Routine
3069 * @pdev: PCI device information struct
3070 * @ent: entry in ena_pci_tbl
3071 *
3072 * Returns 0 on success, negative on failure
3073 *
3074 * ena_probe initializes an adapter identified by a pci_dev structure.
3075 * The OS initialization, configuring of the adapter private structure,
3076 * and a hardware reset occur.
3077 */
3078static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3079{
3080 struct ena_com_dev_get_features_ctx get_feat_ctx;
3081 static int version_printed;
3082 struct net_device *netdev;
3083 struct ena_adapter *adapter;
3084 struct ena_com_dev *ena_dev = NULL;
3085 static int adapters_found;
3086 int io_queue_num, bars, rc;
3087 int queue_size;
3088 u16 tx_sgl_size = 0;
3089 u16 rx_sgl_size = 0;
3090 bool wd_state;
3091
3092 dev_dbg(&pdev->dev, "%s\n", __func__);
3093
3094 if (version_printed++ == 0)
3095 dev_info(&pdev->dev, "%s", version);
3096
3097 rc = pci_enable_device_mem(pdev);
3098 if (rc) {
3099 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
3100 return rc;
3101 }
3102
3103 pci_set_master(pdev);
3104
3105 ena_dev = vzalloc(sizeof(*ena_dev));
3106 if (!ena_dev) {
3107 rc = -ENOMEM;
3108 goto err_disable_device;
3109 }
3110
3111 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3112 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
3113 if (rc) {
3114 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3115 rc);
3116 goto err_free_ena_dev;
3117 }
3118
0857d92f
NB		 3119 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3120 pci_resource_start(pdev, ENA_REG_BAR),
3121 pci_resource_len(pdev, ENA_REG_BAR));
1738cd3e
NB		 3122 if (!ena_dev->reg_bar) {
3123 dev_err(&pdev->dev, "failed to remap regs bar\n");
3124 rc = -EFAULT;
3125 goto err_free_region;
3126 }
3127
3128 ena_dev->dmadev = &pdev->dev;
3129
3130 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3131 if (rc) {
3132 dev_err(&pdev->dev, "ena device init failed\n");
3133 if (rc == -ETIME)
3134 rc = -EPROBE_DEFER;
3135 goto err_free_region;
3136 }
3137
184b49c8 3138 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
1738cd3e
NB		 3139
3140 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
0857d92f
NB		 3141 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3142 pci_resource_start(pdev, ENA_MEM_BAR),
3143 pci_resource_len(pdev, ENA_MEM_BAR));
1738cd3e
NB		 3144 if (!ena_dev->mem_bar) {
3145 rc = -EFAULT;
3146 goto err_device_destroy;
3147 }
3148 }
3149
3150 /* initial Tx interrupt delay, Assumes 1 usec granularity.
3151 * Updated during device initialization with the real granularity
3152 */
3153 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
3154 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
3155 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
3156 &rx_sgl_size, &get_feat_ctx);
3157 if ((queue_size <= 0) || (io_queue_num <= 0)) {
3158 rc = -EFAULT;
3159 goto err_device_destroy;
3160 }
3161
3162 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
3163 io_queue_num, queue_size);
3164
3165 /* dev zeroed in init_etherdev */
3166 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3167 if (!netdev) {
3168 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3169 rc = -ENOMEM;
3170 goto err_device_destroy;
3171 }
3172
3173 SET_NETDEV_DEV(netdev, &pdev->dev);
3174
3175 adapter = netdev_priv(netdev);
3176 pci_set_drvdata(pdev, adapter);
3177
3178 adapter->ena_dev = ena_dev;
3179 adapter->netdev = netdev;
3180 adapter->pdev = pdev;
3181
3182 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3183
3184 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
e2eed0e3 3185 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
1738cd3e
NB		 3186
3187 adapter->tx_ring_size = queue_size;
3188 adapter->rx_ring_size = queue_size;
3189
3190 adapter->max_tx_sgl_size = tx_sgl_size;
3191 adapter->max_rx_sgl_size = rx_sgl_size;
3192
3193 adapter->num_queues = io_queue_num;
3194 adapter->last_monitored_tx_qid = 0;
3195
3196 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3197 adapter->wd_state = wd_state;
3198
3199 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3200
3201 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3202 if (rc) {
3203 dev_err(&pdev->dev,
3204 "Failed to query interrupt moderation feature\n");
3205 goto err_netdev_destroy;
3206 }
3207 ena_init_io_rings(adapter);
3208
3209 netdev->netdev_ops = &ena_netdev_ops;
3210 netdev->watchdog_timeo = TX_TIMEOUT;
3211 ena_set_ethtool_ops(netdev);
3212
3213 netdev->priv_flags |= IFF_UNICAST_FLT;
3214
3215 u64_stats_init(&adapter->syncp);
3216
3217 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3218 if (rc) {
3219 dev_err(&pdev->dev,
3220 "Failed to enable and set the admin interrupts\n");
3221 goto err_worker_destroy;
3222 }
3223 rc = ena_rss_init_default(adapter);
d1497638 3224 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 3225 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3226 goto err_free_msix;
3227 }
3228
3229 ena_config_debug_area(adapter);
3230
3231 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3232
3233 netif_carrier_off(netdev);
3234
3235 rc = register_netdev(netdev);
3236 if (rc) {
3237 dev_err(&pdev->dev, "Cannot register net device\n");
3238 goto err_rss;
3239 }
3240
3241 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend);
3242 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume);
3243 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3244
3245 adapter->last_keep_alive_jiffies = jiffies;
82ef30f1
NB		 3246 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
3247 adapter->missing_tx_completion_to = TX_TIMEOUT;
3248 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS;
3249
3250 ena_update_hints(adapter, &get_feat_ctx.hw_hints);
1738cd3e 3251
f850b4a7
WY		 3252 setup_timer(&adapter->timer_service, ena_timer_service,
3253 (unsigned long)adapter);
3254 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
1738cd3e
NB		 3255
3256 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3257 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3258 netdev->dev_addr, io_queue_num);
3259
3260 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3261
3262 adapters_found++;
3263
3264 return 0;
3265
3266err_rss:
3267 ena_com_delete_debug_area(ena_dev);
3268 ena_com_rss_destroy(ena_dev);
3269err_free_msix:
e2eed0e3 3270 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
1738cd3e 3271 ena_free_mgmnt_irq(adapter);
da6f4cf5 3272 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 3273err_worker_destroy:
3274 ena_com_destroy_interrupt_moderation(ena_dev);
3275 del_timer(&adapter->timer_service);
3276 cancel_work_sync(&adapter->suspend_io_task);
3277 cancel_work_sync(&adapter->resume_io_task);
3278err_netdev_destroy:
3279 free_netdev(netdev);
3280err_device_destroy:
3281 ena_com_delete_host_info(ena_dev);
3282 ena_com_admin_destroy(ena_dev);
3283err_free_region:
3284 ena_release_bars(ena_dev, pdev);
3285err_free_ena_dev:
1738cd3e
NB		 3286 vfree(ena_dev);
3287err_disable_device:
3288 pci_disable_device(pdev);
3289 return rc;
3290}
3291
3292/*****************************************************************************/
3293static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3294{
3295 int rc;
3296
3297 if (numvfs > 0) {
3298 rc = pci_enable_sriov(dev, numvfs);
3299 if (rc != 0) {
3300 dev_err(&dev->dev,
3301 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3302 numvfs, rc);
3303 return rc;
3304 }
3305
3306 return numvfs;
3307 }
3308
3309 if (numvfs == 0) {
3310 pci_disable_sriov(dev);
3311 return 0;
3312 }
3313
3314 return -EINVAL;
3315}
3316
3317/*****************************************************************************/
3318/*****************************************************************************/
3319
3320/* ena_remove - Device Removal Routine
3321 * @pdev: PCI device information struct
3322 *
3323 * ena_remove is called by the PCI subsystem to alert the driver
3324 * that it should release a PCI device.
3325 */
3326static void ena_remove(struct pci_dev *pdev)
3327{
3328 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3329 struct ena_com_dev *ena_dev;
3330 struct net_device *netdev;
3331
1738cd3e
NB		 3332 ena_dev = adapter->ena_dev;
3333 netdev = adapter->netdev;
3334
3335#ifdef CONFIG_RFS_ACCEL
3336 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3337 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3338 netdev->rx_cpu_rmap = NULL;
3339 }
3340#endif /* CONFIG_RFS_ACCEL */
3341
3342 unregister_netdev(netdev);
3343 del_timer_sync(&adapter->timer_service);
3344
3345 cancel_work_sync(&adapter->reset_task);
3346
3347 cancel_work_sync(&adapter->suspend_io_task);
3348
3349 cancel_work_sync(&adapter->resume_io_task);
3350
22b331c9
NB		 3351 /* Reset the device only if the device is running. */
3352 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
e2eed0e3 3353 ena_com_dev_reset(ena_dev, adapter->reset_reason);
1738cd3e
NB		 3354
3355 ena_free_mgmnt_irq(adapter);
3356
da6f4cf5 3357 pci_free_irq_vectors(adapter->pdev);
1738cd3e
NB		 3358
3359 free_netdev(netdev);
3360
3361 ena_com_mmio_reg_read_request_destroy(ena_dev);
3362
3363 ena_com_abort_admin_commands(ena_dev);
3364
3365 ena_com_wait_for_abort_completion(ena_dev);
3366
3367 ena_com_admin_destroy(ena_dev);
3368
3369 ena_com_rss_destroy(ena_dev);
3370
3371 ena_com_delete_debug_area(ena_dev);
3372
3373 ena_com_delete_host_info(ena_dev);
3374
3375 ena_release_bars(ena_dev, pdev);
3376
1738cd3e
NB		 3377 pci_disable_device(pdev);
3378
3379 ena_com_destroy_interrupt_moderation(ena_dev);
3380
3381 vfree(ena_dev);
3382}
3383
3384static struct pci_driver ena_pci_driver = {
3385 .name = DRV_MODULE_NAME,
3386 .id_table = ena_pci_tbl,
3387 .probe = ena_probe,
3388 .remove = ena_remove,
3389 .sriov_configure = ena_sriov_configure,
3390};
3391
3392static int __init ena_init(void)
3393{
3394 pr_info("%s", version);
3395
3396 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3397 if (!ena_wq) {
3398 pr_err("Failed to create workqueue\n");
3399 return -ENOMEM;
3400 }
3401
3402 return pci_register_driver(&ena_pci_driver);
3403}
3404
3405static void __exit ena_cleanup(void)
3406{
3407 pci_unregister_driver(&ena_pci_driver);
3408
3409 if (ena_wq) {
3410 destroy_workqueue(ena_wq);
3411 ena_wq = NULL;
3412 }
3413}
3414
3415/******************************************************************************
3416 ******************************** AENQ Handlers *******************************
3417 *****************************************************************************/
3418/* ena_update_on_link_change:
3419 * Notify the network interface about the change in link status
3420 */
3421static void ena_update_on_link_change(void *adapter_data,
3422 struct ena_admin_aenq_entry *aenq_e)
3423{
3424 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3425 struct ena_admin_aenq_link_change_desc *aenq_desc =
3426 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3427 int status = aenq_desc->flags &
3428 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3429
3430 if (status) {
3431 netdev_dbg(adapter->netdev, "%s\n", __func__);
3432 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3433 netif_carrier_on(adapter->netdev);
3434 } else {
3435 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3436 netif_carrier_off(adapter->netdev);
3437 }
3438}
3439
3440static void ena_keep_alive_wd(void *adapter_data,
3441 struct ena_admin_aenq_entry *aenq_e)
3442{
3443 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3444
3445 adapter->last_keep_alive_jiffies = jiffies;
3446}
3447
3448static void ena_notification(void *adapter_data,
3449 struct ena_admin_aenq_entry *aenq_e)
3450{
3451 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
82ef30f1 3452 struct ena_admin_ena_hw_hints *hints;
1738cd3e
NB		 3453
3454 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3455 "Invalid group(%x) expected %x\n",
3456 aenq_e->aenq_common_desc.group,
3457 ENA_ADMIN_NOTIFICATION);
3458
3459 switch (aenq_e->aenq_common_desc.syndrom) {
3460 case ENA_ADMIN_SUSPEND:
3461 /* Suspend just the IO queues.
3462 * We deliberately don't suspend admin so the timer and
3463 * the keep_alive events should remain.
3464 */
3465 queue_work(ena_wq, &adapter->suspend_io_task);
3466 break;
3467 case ENA_ADMIN_RESUME:
3468 queue_work(ena_wq, &adapter->resume_io_task);
3469 break;
82ef30f1
NB		 3470 case ENA_ADMIN_UPDATE_HINTS:
3471 hints = (struct ena_admin_ena_hw_hints *)
3472 (&aenq_e->inline_data_w4);
3473 ena_update_hints(adapter, hints);
3474 break;
1738cd3e
NB		 3475 default:
3476 netif_err(adapter, drv, adapter->netdev,
3477 "Invalid aenq notification link state %d\n",
3478 aenq_e->aenq_common_desc.syndrom);
3479 }
3480}
3481
3482/* This handler will called for unknown event group or unimplemented handlers*/
3483static void unimplemented_aenq_handler(void *data,
3484 struct ena_admin_aenq_entry *aenq_e)
3485{
3486 struct ena_adapter *adapter = (struct ena_adapter *)data;
3487
3488 netif_err(adapter, drv, adapter->netdev,
3489 "Unknown event was received or event with unimplemented handler\n");
3490}
3491
3492static struct ena_aenq_handlers aenq_handlers = {
3493 .handlers = {
3494 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3495 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3496 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3497 },
3498 .unimplemented_handler = unimplemented_aenq_handler
3499};
3500
3501module_init(ena_init);
3502module_exit(ena_cleanup);
Ubuntu Artful kernel mirror