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1 | /* |
2 | * Copyright 2015 Amazon.com, Inc. or its affiliates. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef ENA_H | |
34 | #define ENA_H | |
35 | ||
36 | #include <linux/bitops.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/inetdevice.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/netdevice.h> | |
41 | #include <linux/skbuff.h> | |
42 | ||
43 | #include "ena_com.h" | |
44 | #include "ena_eth_com.h" | |
45 | ||
46 | #define DRV_MODULE_VER_MAJOR 1 | |
47 | #define DRV_MODULE_VER_MINOR 0 | |
48 | #define DRV_MODULE_VER_SUBMINOR 2 | |
49 | ||
50 | #define DRV_MODULE_NAME "ena" | |
51 | #ifndef DRV_MODULE_VERSION | |
52 | #define DRV_MODULE_VERSION \ | |
53 | __stringify(DRV_MODULE_VER_MAJOR) "." \ | |
54 | __stringify(DRV_MODULE_VER_MINOR) "." \ | |
55 | __stringify(DRV_MODULE_VER_SUBMINOR) | |
56 | #endif | |
57 | ||
58 | #define DEVICE_NAME "Elastic Network Adapter (ENA)" | |
59 | ||
60 | /* 1 for AENQ + ADMIN */ | |
61 | #define ENA_MAX_MSIX_VEC(io_queues) (1 + (io_queues)) | |
62 | ||
63 | #define ENA_REG_BAR 0 | |
64 | #define ENA_MEM_BAR 2 | |
65 | #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) | |
66 | ||
67 | #define ENA_DEFAULT_RING_SIZE (1024) | |
68 | ||
69 | #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) | |
70 | #define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN) | |
71 | ||
72 | /* limit the buffer size to 600 bytes to handle MTU changes from very | |
73 | * small to very large, in which case the number of buffers per packet | |
74 | * could exceed ENA_PKT_MAX_BUFS | |
75 | */ | |
76 | #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 | |
77 | ||
78 | #define ENA_MIN_MTU 128 | |
79 | ||
80 | #define ENA_NAME_MAX_LEN 20 | |
81 | #define ENA_IRQNAME_SIZE 40 | |
82 | ||
83 | #define ENA_PKT_MAX_BUFS 19 | |
84 | ||
85 | #define ENA_RX_RSS_TABLE_LOG_SIZE 7 | |
86 | #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) | |
87 | ||
88 | #define ENA_HASH_KEY_SIZE 40 | |
89 | ||
90 | /* The number of tx packet completions that will be handled each NAPI poll | |
91 | * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. | |
92 | */ | |
93 | #define ENA_TX_POLL_BUDGET_DIVIDER 4 | |
94 | ||
95 | /* Refill Rx queue when number of available descriptors is below | |
96 | * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER | |
97 | */ | |
98 | #define ENA_RX_REFILL_THRESH_DIVIDER 8 | |
99 | ||
100 | /* Number of queues to check for missing queues per timer service */ | |
101 | #define ENA_MONITORED_TX_QUEUES 4 | |
102 | /* Max timeout packets before device reset */ | |
103 | #define MAX_NUM_OF_TIMEOUTED_PACKETS 32 | |
104 | ||
105 | #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) | |
106 | ||
107 | #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) | |
108 | #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ | |
109 | (((idx) + (n)) & ((ring_size) - 1)) | |
110 | ||
111 | #define ENA_IO_TXQ_IDX(q) (2 * (q)) | |
112 | #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) | |
113 | ||
114 | #define ENA_MGMNT_IRQ_IDX 0 | |
115 | #define ENA_IO_IRQ_FIRST_IDX 1 | |
116 | #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) | |
117 | ||
118 | /* ENA device should send keep alive msg every 1 sec. | |
119 | * We wait for 3 sec just to be on the safe side. | |
120 | */ | |
121 | #define ENA_DEVICE_KALIVE_TIMEOUT (3 * HZ) | |
122 | ||
123 | #define ENA_MMIO_DISABLE_REG_READ BIT(0) | |
124 | ||
125 | struct ena_irq { | |
126 | irq_handler_t handler; | |
127 | void *data; | |
128 | int cpu; | |
129 | u32 vector; | |
130 | cpumask_t affinity_hint_mask; | |
131 | char name[ENA_IRQNAME_SIZE]; | |
132 | }; | |
133 | ||
134 | struct ena_napi { | |
135 | struct napi_struct napi ____cacheline_aligned; | |
136 | struct ena_ring *tx_ring; | |
137 | struct ena_ring *rx_ring; | |
138 | u32 qid; | |
139 | }; | |
140 | ||
141 | struct ena_tx_buffer { | |
142 | struct sk_buff *skb; | |
143 | /* num of ena desc for this specific skb | |
144 | * (includes data desc and metadata desc) | |
145 | */ | |
146 | u32 tx_descs; | |
147 | /* num of buffers used by this skb */ | |
148 | u32 num_of_bufs; | |
149 | /* Save the last jiffies to detect missing tx packets */ | |
150 | unsigned long last_jiffies; | |
151 | struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; | |
152 | } ____cacheline_aligned; | |
153 | ||
154 | struct ena_rx_buffer { | |
155 | struct sk_buff *skb; | |
156 | struct page *page; | |
157 | u32 page_offset; | |
158 | struct ena_com_buf ena_buf; | |
159 | } ____cacheline_aligned; | |
160 | ||
161 | struct ena_stats_tx { | |
162 | u64 cnt; | |
163 | u64 bytes; | |
164 | u64 queue_stop; | |
165 | u64 prepare_ctx_err; | |
166 | u64 queue_wakeup; | |
167 | u64 dma_mapping_err; | |
168 | u64 linearize; | |
169 | u64 linearize_failed; | |
170 | u64 napi_comp; | |
171 | u64 tx_poll; | |
172 | u64 doorbells; | |
173 | u64 missing_tx_comp; | |
174 | u64 bad_req_id; | |
175 | }; | |
176 | ||
177 | struct ena_stats_rx { | |
178 | u64 cnt; | |
179 | u64 bytes; | |
180 | u64 refil_partial; | |
181 | u64 bad_csum; | |
182 | u64 page_alloc_fail; | |
183 | u64 skb_alloc_fail; | |
184 | u64 dma_mapping_err; | |
185 | u64 bad_desc_num; | |
186 | u64 rx_copybreak_pkt; | |
187 | }; | |
188 | ||
189 | struct ena_ring { | |
190 | /* Holds the empty requests for TX out of order completions */ | |
191 | u16 *free_tx_ids; | |
192 | union { | |
193 | struct ena_tx_buffer *tx_buffer_info; | |
194 | struct ena_rx_buffer *rx_buffer_info; | |
195 | }; | |
196 | ||
197 | /* cache ptr to avoid using the adapter */ | |
198 | struct device *dev; | |
199 | struct pci_dev *pdev; | |
200 | struct napi_struct *napi; | |
201 | struct net_device *netdev; | |
202 | struct ena_com_dev *ena_dev; | |
203 | struct ena_adapter *adapter; | |
204 | struct ena_com_io_cq *ena_com_io_cq; | |
205 | struct ena_com_io_sq *ena_com_io_sq; | |
206 | ||
207 | u16 next_to_use; | |
208 | u16 next_to_clean; | |
209 | u16 rx_copybreak; | |
210 | u16 qid; | |
211 | u16 mtu; | |
212 | u16 sgl_size; | |
213 | ||
214 | /* The maximum header length the device can handle */ | |
215 | u8 tx_max_header_size; | |
216 | ||
217 | /* cpu for TPH */ | |
218 | int cpu; | |
219 | /* number of tx/rx_buffer_info's entries */ | |
220 | int ring_size; | |
221 | ||
222 | enum ena_admin_placement_policy_type tx_mem_queue_type; | |
223 | ||
224 | struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; | |
225 | u32 smoothed_interval; | |
226 | u32 per_napi_packets; | |
227 | u32 per_napi_bytes; | |
228 | enum ena_intr_moder_level moder_tbl_idx; | |
229 | struct u64_stats_sync syncp; | |
230 | union { | |
231 | struct ena_stats_tx tx_stats; | |
232 | struct ena_stats_rx rx_stats; | |
233 | }; | |
234 | } ____cacheline_aligned; | |
235 | ||
236 | struct ena_stats_dev { | |
237 | u64 tx_timeout; | |
238 | u64 io_suspend; | |
239 | u64 io_resume; | |
240 | u64 wd_expired; | |
241 | u64 interface_up; | |
242 | u64 interface_down; | |
243 | u64 admin_q_pause; | |
244 | }; | |
245 | ||
246 | enum ena_flags_t { | |
247 | ENA_FLAG_DEVICE_RUNNING, | |
248 | ENA_FLAG_DEV_UP, | |
249 | ENA_FLAG_LINK_UP, | |
250 | ENA_FLAG_MSIX_ENABLED, | |
251 | ENA_FLAG_TRIGGER_RESET | |
252 | }; | |
253 | ||
254 | /* adapter specific private data structure */ | |
255 | struct ena_adapter { | |
256 | struct ena_com_dev *ena_dev; | |
257 | /* OS defined structs */ | |
258 | struct net_device *netdev; | |
259 | struct pci_dev *pdev; | |
260 | ||
261 | /* rx packets that shorter that this len will be copied to the skb | |
262 | * header | |
263 | */ | |
264 | u32 rx_copybreak; | |
265 | u32 max_mtu; | |
266 | ||
267 | int num_queues; | |
268 | ||
269 | struct msix_entry *msix_entries; | |
270 | int msix_vecs; | |
271 | ||
272 | u32 tx_usecs, rx_usecs; /* interrupt moderation */ | |
273 | u32 tx_frames, rx_frames; /* interrupt moderation */ | |
274 | ||
275 | u32 tx_ring_size; | |
276 | u32 rx_ring_size; | |
277 | ||
278 | u32 msg_enable; | |
279 | ||
280 | u16 max_tx_sgl_size; | |
281 | u16 max_rx_sgl_size; | |
282 | ||
283 | u8 mac_addr[ETH_ALEN]; | |
284 | ||
285 | char name[ENA_NAME_MAX_LEN]; | |
286 | ||
287 | unsigned long flags; | |
288 | /* TX */ | |
289 | struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] | |
290 | ____cacheline_aligned_in_smp; | |
291 | ||
292 | /* RX */ | |
293 | struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] | |
294 | ____cacheline_aligned_in_smp; | |
295 | ||
296 | struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; | |
297 | ||
298 | struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; | |
299 | ||
300 | /* timer service */ | |
301 | struct work_struct reset_task; | |
302 | struct work_struct suspend_io_task; | |
303 | struct work_struct resume_io_task; | |
304 | struct timer_list timer_service; | |
305 | ||
306 | bool wd_state; | |
307 | unsigned long last_keep_alive_jiffies; | |
308 | ||
309 | struct u64_stats_sync syncp; | |
310 | struct ena_stats_dev dev_stats; | |
311 | ||
312 | /* last queue index that was checked for uncompleted tx packets */ | |
313 | u32 last_monitored_tx_qid; | |
314 | }; | |
315 | ||
316 | void ena_set_ethtool_ops(struct net_device *netdev); | |
317 | ||
318 | void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); | |
319 | ||
320 | void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); | |
321 | ||
322 | int ena_get_sset_count(struct net_device *netdev, int sset); | |
323 | ||
324 | #endif /* !(ENA_H) */ |