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Commit | Line | Data |
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1ccea77e | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | |
6aa20a22 JG |
3 | /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver |
4 | * Copyright (C) 2004 Advanced Micro Devices | |
5 | * | |
1da177e4 LT |
6 | * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ] |
7 | * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c] | |
8 | * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ] | |
9 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. | |
10 | * Copyright 1993 United States Government as represented by the | |
11 | * Director, National Security Agency.[ pcnet32.c ] | |
12 | * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ] | |
13 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
14 | * | |
6aa20a22 | 15 | |
1da177e4 LT |
16 | Module Name: |
17 | ||
18 | amd8111e.c | |
19 | ||
20 | Abstract: | |
6aa20a22 JG |
21 | |
22 | AMD8111 based 10/100 Ethernet Controller Driver. | |
1da177e4 LT |
23 | |
24 | Environment: | |
25 | ||
26 | Kernel Mode | |
27 | ||
28 | Revision History: | |
29 | 3.0.0 | |
30 | Initial Revision. | |
31 | 3.0.1 | |
32 | 1. Dynamic interrupt coalescing. | |
33 | 2. Removed prev_stats. | |
34 | 3. MII support. | |
35 | 4. Dynamic IPG support | |
36 | 3.0.2 05/29/2003 | |
37 | 1. Bug fix: Fixed failure to send jumbo packets larger than 4k. | |
38 | 2. Bug fix: Fixed VLAN support failure. | |
39 | 3. Bug fix: Fixed receive interrupt coalescing bug. | |
40 | 4. Dynamic IPG support is disabled by default. | |
41 | 3.0.3 06/05/2003 | |
42 | 1. Bug fix: Fixed failure to close the interface if SMP is enabled. | |
43 | 3.0.4 12/09/2003 | |
44 | 1. Added set_mac_address routine for bonding driver support. | |
45 | 2. Tested the driver for bonding support | |
6aa20a22 | 46 | 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth |
1da177e4 | 47 | indicated to the h/w. |
6aa20a22 | 48 | 4. Modified amd8111e_rx() routine to receive all the received packets |
1da177e4 LT |
49 | in the first interrupt. |
50 | 5. Bug fix: Corrected rx_errors reported in get_stats() function. | |
51 | 3.0.5 03/22/2004 | |
6aa20a22 | 52 | 1. Added NAPI support |
1da177e4 LT |
53 | |
54 | */ | |
55 | ||
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/kernel.h> | |
59 | #include <linux/types.h> | |
60 | #include <linux/compiler.h> | |
1da177e4 | 61 | #include <linux/delay.h> |
a6b7a407 | 62 | #include <linux/interrupt.h> |
1da177e4 LT |
63 | #include <linux/ioport.h> |
64 | #include <linux/pci.h> | |
65 | #include <linux/netdevice.h> | |
66 | #include <linux/etherdevice.h> | |
67 | #include <linux/skbuff.h> | |
68 | #include <linux/ethtool.h> | |
69 | #include <linux/mii.h> | |
70 | #include <linux/if_vlan.h> | |
6aa20a22 | 71 | #include <linux/ctype.h> |
1da177e4 | 72 | #include <linux/crc32.h> |
cac8c81a | 73 | #include <linux/dma-mapping.h> |
1da177e4 | 74 | |
1da177e4 LT |
75 | #include <asm/io.h> |
76 | #include <asm/byteorder.h> | |
7c0f6ba6 | 77 | #include <linux/uaccess.h> |
1da177e4 | 78 | |
941992d2 | 79 | #if IS_ENABLED(CONFIG_VLAN_8021Q) |
1da177e4 LT |
80 | #define AMD8111E_VLAN_TAG_USED 1 |
81 | #else | |
82 | #define AMD8111E_VLAN_TAG_USED 0 | |
83 | #endif | |
84 | ||
85 | #include "amd8111e.h" | |
86 | #define MODULE_NAME "amd8111e" | |
6ba33ac8 | 87 | #define MODULE_VERS "3.0.7" |
1da177e4 | 88 | MODULE_AUTHOR("Advanced Micro Devices, Inc."); |
6ba33ac8 | 89 | MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS); |
1da177e4 | 90 | MODULE_LICENSE("GPL"); |
1da177e4 | 91 | module_param_array(speed_duplex, int, NULL, 0); |
983960b1 | 92 | MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex"); |
1da177e4 LT |
93 | module_param_array(coalesce, bool, NULL, 0); |
94 | MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable"); | |
95 | module_param_array(dynamic_ipg, bool, NULL, 0); | |
96 | MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable"); | |
97 | ||
13a4fa43 | 98 | /* This function will read the PHY registers. */ |
46c73ecc VB |
99 | static int amd8111e_read_phy(struct amd8111e_priv *lp, |
100 | int phy_id, int reg, u32 *val) | |
1da177e4 LT |
101 | { |
102 | void __iomem *mmio = lp->mmio; | |
103 | unsigned int reg_val; | |
104 | unsigned int repeat= REPEAT_CNT; | |
105 | ||
106 | reg_val = readl(mmio + PHY_ACCESS); | |
107 | while (reg_val & PHY_CMD_ACTIVE) | |
108 | reg_val = readl( mmio + PHY_ACCESS ); | |
109 | ||
110 | writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | | |
111 | ((reg & 0x1f) << 16), mmio +PHY_ACCESS); | |
112 | do{ | |
113 | reg_val = readl(mmio + PHY_ACCESS); | |
114 | udelay(30); /* It takes 30 us to read/write data */ | |
115 | } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); | |
116 | if(reg_val & PHY_RD_ERR) | |
117 | goto err_phy_read; | |
6aa20a22 | 118 | |
1da177e4 LT |
119 | *val = reg_val & 0xffff; |
120 | return 0; | |
6aa20a22 | 121 | err_phy_read: |
1da177e4 LT |
122 | *val = 0; |
123 | return -EINVAL; | |
6aa20a22 | 124 | |
1da177e4 LT |
125 | } |
126 | ||
13a4fa43 | 127 | /* This function will write into PHY registers. */ |
46c73ecc VB |
128 | static int amd8111e_write_phy(struct amd8111e_priv *lp, |
129 | int phy_id, int reg, u32 val) | |
1da177e4 | 130 | { |
632155e6 | 131 | unsigned int repeat = REPEAT_CNT; |
1da177e4 LT |
132 | void __iomem *mmio = lp->mmio; |
133 | unsigned int reg_val; | |
134 | ||
135 | reg_val = readl(mmio + PHY_ACCESS); | |
136 | while (reg_val & PHY_CMD_ACTIVE) | |
137 | reg_val = readl( mmio + PHY_ACCESS ); | |
138 | ||
139 | writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | | |
140 | ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); | |
141 | ||
142 | do{ | |
143 | reg_val = readl(mmio + PHY_ACCESS); | |
144 | udelay(30); /* It takes 30 us to read/write the data */ | |
145 | } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); | |
6aa20a22 | 146 | |
1da177e4 LT |
147 | if(reg_val & PHY_RD_ERR) |
148 | goto err_phy_write; | |
6aa20a22 | 149 | |
1da177e4 LT |
150 | return 0; |
151 | ||
6aa20a22 | 152 | err_phy_write: |
1da177e4 | 153 | return -EINVAL; |
6aa20a22 | 154 | |
1da177e4 | 155 | } |
13a4fa43 VB |
156 | |
157 | /* This is the mii register read function provided to the mii interface. */ | |
46c73ecc | 158 | static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num) |
1da177e4 | 159 | { |
46c73ecc | 160 | struct amd8111e_priv *lp = netdev_priv(dev); |
1da177e4 LT |
161 | unsigned int reg_val; |
162 | ||
163 | amd8111e_read_phy(lp,phy_id,reg_num,®_val); | |
164 | return reg_val; | |
6aa20a22 | 165 | |
1da177e4 LT |
166 | } |
167 | ||
13a4fa43 | 168 | /* This is the mii register write function provided to the mii interface. */ |
46c73ecc VB |
169 | static void amd8111e_mdio_write(struct net_device *dev, |
170 | int phy_id, int reg_num, int val) | |
1da177e4 | 171 | { |
46c73ecc | 172 | struct amd8111e_priv *lp = netdev_priv(dev); |
1da177e4 LT |
173 | |
174 | amd8111e_write_phy(lp, phy_id, reg_num, val); | |
175 | } | |
176 | ||
13a4fa43 VB |
177 | /* This function will set PHY speed. During initialization sets |
178 | * the original speed to 100 full | |
179 | */ | |
1da177e4 LT |
180 | static void amd8111e_set_ext_phy(struct net_device *dev) |
181 | { | |
182 | struct amd8111e_priv *lp = netdev_priv(dev); | |
183 | u32 bmcr,advert,tmp; | |
6aa20a22 | 184 | |
1da177e4 LT |
185 | /* Determine mii register values to set the speed */ |
186 | advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE); | |
187 | tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); | |
188 | switch (lp->ext_phy_option){ | |
189 | ||
190 | default: | |
191 | case SPEED_AUTONEG: /* advertise all values */ | |
192 | tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL| | |
193 | ADVERTISE_100HALF|ADVERTISE_100FULL) ; | |
194 | break; | |
195 | case SPEED10_HALF: | |
196 | tmp |= ADVERTISE_10HALF; | |
197 | break; | |
198 | case SPEED10_FULL: | |
199 | tmp |= ADVERTISE_10FULL; | |
200 | break; | |
6aa20a22 | 201 | case SPEED100_HALF: |
1da177e4 LT |
202 | tmp |= ADVERTISE_100HALF; |
203 | break; | |
204 | case SPEED100_FULL: | |
205 | tmp |= ADVERTISE_100FULL; | |
206 | break; | |
207 | } | |
208 | ||
209 | if(advert != tmp) | |
210 | amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp); | |
211 | /* Restart auto negotiation */ | |
212 | bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR); | |
213 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
214 | amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr); | |
215 | ||
216 | } | |
217 | ||
13a4fa43 VB |
218 | /* This function will unmap skb->data space and will free |
219 | * all transmit and receive skbuffs. | |
220 | */ | |
1da177e4 LT |
221 | static int amd8111e_free_skbs(struct net_device *dev) |
222 | { | |
223 | struct amd8111e_priv *lp = netdev_priv(dev); | |
46c73ecc | 224 | struct sk_buff *rx_skbuff; |
1da177e4 LT |
225 | int i; |
226 | ||
227 | /* Freeing transmit skbs */ | |
228 | for(i = 0; i < NUM_TX_BUFFERS; i++){ | |
229 | if(lp->tx_skbuff[i]){ | |
230 | pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE); | |
231 | dev_kfree_skb (lp->tx_skbuff[i]); | |
232 | lp->tx_skbuff[i] = NULL; | |
233 | lp->tx_dma_addr[i] = 0; | |
234 | } | |
235 | } | |
236 | /* Freeing previously allocated receive buffers */ | |
237 | for (i = 0; i < NUM_RX_BUFFERS; i++){ | |
238 | rx_skbuff = lp->rx_skbuff[i]; | |
239 | if(rx_skbuff != NULL){ | |
240 | pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i], | |
241 | lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE); | |
242 | dev_kfree_skb(lp->rx_skbuff[i]); | |
243 | lp->rx_skbuff[i] = NULL; | |
244 | lp->rx_dma_addr[i] = 0; | |
245 | } | |
246 | } | |
6aa20a22 | 247 | |
1da177e4 LT |
248 | return 0; |
249 | } | |
250 | ||
13a4fa43 VB |
251 | /* This will set the receive buffer length corresponding |
252 | * to the mtu size of networkinterface. | |
253 | */ | |
46c73ecc | 254 | static inline void amd8111e_set_rx_buff_len(struct net_device *dev) |
1da177e4 | 255 | { |
46c73ecc | 256 | struct amd8111e_priv *lp = netdev_priv(dev); |
1da177e4 | 257 | unsigned int mtu = dev->mtu; |
6aa20a22 | 258 | |
1da177e4 LT |
259 | if (mtu > ETH_DATA_LEN){ |
260 | /* MTU + ethernet header + FCS | |
13a4fa43 VB |
261 | * + optional VLAN tag + skb reserve space 2 |
262 | */ | |
1da177e4 LT |
263 | lp->rx_buff_len = mtu + ETH_HLEN + 10; |
264 | lp->options |= OPTION_JUMBO_ENABLE; | |
265 | } else{ | |
266 | lp->rx_buff_len = PKT_BUFF_SZ; | |
267 | lp->options &= ~OPTION_JUMBO_ENABLE; | |
268 | } | |
269 | } | |
270 | ||
13a4fa43 VB |
271 | /* This function will free all the previously allocated buffers, |
272 | * determine new receive buffer length and will allocate new receive buffers. | |
273 | * This function also allocates and initializes both the transmitter | |
274 | * and receive hardware descriptors. | |
1da177e4 LT |
275 | */ |
276 | static int amd8111e_init_ring(struct net_device *dev) | |
277 | { | |
278 | struct amd8111e_priv *lp = netdev_priv(dev); | |
279 | int i; | |
280 | ||
281 | lp->rx_idx = lp->tx_idx = 0; | |
282 | lp->tx_complete_idx = 0; | |
283 | lp->tx_ring_idx = 0; | |
6aa20a22 | 284 | |
1da177e4 LT |
285 | |
286 | if(lp->opened) | |
287 | /* Free previously allocated transmit and receive skbs */ | |
6aa20a22 | 288 | amd8111e_free_skbs(dev); |
1da177e4 LT |
289 | |
290 | else{ | |
291 | /* allocate the tx and rx descriptors */ | |
6aa20a22 | 292 | if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1da177e4 LT |
293 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, |
294 | &lp->tx_ring_dma_addr)) == NULL) | |
6aa20a22 | 295 | |
1da177e4 | 296 | goto err_no_mem; |
6aa20a22 JG |
297 | |
298 | if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, | |
1da177e4 LT |
299 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, |
300 | &lp->rx_ring_dma_addr)) == NULL) | |
6aa20a22 | 301 | |
1da177e4 LT |
302 | goto err_free_tx_ring; |
303 | ||
304 | } | |
305 | /* Set new receive buff size */ | |
306 | amd8111e_set_rx_buff_len(dev); | |
307 | ||
308 | /* Allocating receive skbs */ | |
309 | for (i = 0; i < NUM_RX_BUFFERS; i++) { | |
310 | ||
1d266430 PD |
311 | lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len); |
312 | if (!lp->rx_skbuff[i]) { | |
1da177e4 LT |
313 | /* Release previos allocated skbs */ |
314 | for(--i; i >= 0 ;i--) | |
315 | dev_kfree_skb(lp->rx_skbuff[i]); | |
316 | goto err_free_rx_ring; | |
317 | } | |
318 | skb_reserve(lp->rx_skbuff[i],2); | |
319 | } | |
320 | /* Initilaizing receive descriptors */ | |
321 | for (i = 0; i < NUM_RX_BUFFERS; i++) { | |
6aa20a22 | 322 | lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, |
1da177e4 LT |
323 | lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); |
324 | ||
325 | lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]); | |
326 | lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2); | |
327 | wmb(); | |
328 | lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT); | |
329 | } | |
330 | ||
331 | /* Initializing transmit descriptors */ | |
332 | for (i = 0; i < NUM_TX_RING_DR; i++) { | |
333 | lp->tx_ring[i].buff_phy_addr = 0; | |
334 | lp->tx_ring[i].tx_flags = 0; | |
335 | lp->tx_ring[i].buff_count = 0; | |
336 | } | |
337 | ||
338 | return 0; | |
339 | ||
340 | err_free_rx_ring: | |
6aa20a22 JG |
341 | |
342 | pci_free_consistent(lp->pci_dev, | |
1da177e4 LT |
343 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring, |
344 | lp->rx_ring_dma_addr); | |
345 | ||
346 | err_free_tx_ring: | |
6aa20a22 | 347 | |
1da177e4 | 348 | pci_free_consistent(lp->pci_dev, |
6aa20a22 | 349 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring, |
1da177e4 LT |
350 | lp->tx_ring_dma_addr); |
351 | ||
352 | err_no_mem: | |
353 | return -ENOMEM; | |
354 | } | |
13a4fa43 VB |
355 | |
356 | /* This function will set the interrupt coalescing according | |
357 | * to the input arguments | |
358 | */ | |
46c73ecc | 359 | static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod) |
1da177e4 LT |
360 | { |
361 | unsigned int timeout; | |
362 | unsigned int event_count; | |
363 | ||
364 | struct amd8111e_priv *lp = netdev_priv(dev); | |
365 | void __iomem *mmio = lp->mmio; | |
46c73ecc | 366 | struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf; |
1da177e4 LT |
367 | |
368 | ||
369 | switch(cmod) | |
370 | { | |
371 | case RX_INTR_COAL : | |
372 | timeout = coal_conf->rx_timeout; | |
373 | event_count = coal_conf->rx_event_count; | |
6aa20a22 JG |
374 | if( timeout > MAX_TIMEOUT || |
375 | event_count > MAX_EVENT_COUNT ) | |
022484c1 | 376 | return -EINVAL; |
1da177e4 | 377 | |
6aa20a22 | 378 | timeout = timeout * DELAY_TIMER_CONV; |
1da177e4 LT |
379 | writel(VAL0|STINTEN, mmio+INTEN0); |
380 | writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, | |
381 | mmio+DLY_INT_A); | |
382 | break; | |
383 | ||
384 | case TX_INTR_COAL : | |
385 | timeout = coal_conf->tx_timeout; | |
386 | event_count = coal_conf->tx_event_count; | |
6aa20a22 JG |
387 | if( timeout > MAX_TIMEOUT || |
388 | event_count > MAX_EVENT_COUNT ) | |
022484c1 | 389 | return -EINVAL; |
1da177e4 | 390 | |
6aa20a22 JG |
391 | |
392 | timeout = timeout * DELAY_TIMER_CONV; | |
1da177e4 LT |
393 | writel(VAL0|STINTEN,mmio+INTEN0); |
394 | writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, | |
395 | mmio+DLY_INT_B); | |
396 | break; | |
397 | ||
398 | case DISABLE_COAL: | |
399 | writel(0,mmio+STVAL); | |
400 | writel(STINTEN, mmio+INTEN0); | |
401 | writel(0, mmio +DLY_INT_B); | |
402 | writel(0, mmio+DLY_INT_A); | |
403 | break; | |
6aa20a22 | 404 | case ENABLE_COAL: |
1da177e4 LT |
405 | /* Start the timer */ |
406 | writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */ | |
407 | writel(VAL0|STINTEN, mmio+INTEN0); | |
408 | break; | |
409 | default: | |
410 | break; | |
411 | ||
412 | } | |
413 | return 0; | |
414 | ||
415 | } | |
416 | ||
13a4fa43 | 417 | /* This function initializes the device registers and starts the device. */ |
1da177e4 LT |
418 | static int amd8111e_restart(struct net_device *dev) |
419 | { | |
420 | struct amd8111e_priv *lp = netdev_priv(dev); | |
421 | void __iomem *mmio = lp->mmio; | |
422 | int i,reg_val; | |
423 | ||
424 | /* stop the chip */ | |
843ef94e | 425 | writel(RUN, mmio + CMD0); |
1da177e4 LT |
426 | |
427 | if(amd8111e_init_ring(dev)) | |
428 | return -ENOMEM; | |
429 | ||
430 | /* enable the port manager and set auto negotiation always */ | |
431 | writel((u32) VAL1|EN_PMGR, mmio + CMD3 ); | |
6aa20a22 JG |
432 | writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); |
433 | ||
1da177e4 LT |
434 | amd8111e_set_ext_phy(dev); |
435 | ||
436 | /* set control registers */ | |
437 | reg_val = readl(mmio + CTRL1); | |
438 | reg_val &= ~XMTSP_MASK; | |
439 | writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); | |
440 | ||
441 | /* enable interrupt */ | |
6aa20a22 | 442 | writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | |
1da177e4 LT |
443 | APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN | |
444 | SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); | |
445 | ||
446 | writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); | |
447 | ||
448 | /* initialize tx and rx ring base addresses */ | |
449 | writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0); | |
450 | writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0); | |
451 | ||
452 | writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0); | |
453 | writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0); | |
6aa20a22 | 454 | |
1da177e4 LT |
455 | /* set default IPG to 96 */ |
456 | writew((u32)DEFAULT_IPG,mmio+IPG); | |
6aa20a22 | 457 | writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1); |
1da177e4 LT |
458 | |
459 | if(lp->options & OPTION_JUMBO_ENABLE){ | |
460 | writel((u32)VAL2|JUMBO, mmio + CMD3); | |
461 | /* Reset REX_UFLO */ | |
462 | writel( REX_UFLO, mmio + CMD2); | |
463 | /* Should not set REX_UFLO for jumbo frames */ | |
464 | writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); | |
465 | }else{ | |
466 | writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); | |
467 | writel((u32)JUMBO, mmio + CMD3); | |
468 | } | |
469 | ||
470 | #if AMD8111E_VLAN_TAG_USED | |
471 | writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3); | |
472 | #endif | |
473 | writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); | |
6aa20a22 | 474 | |
1da177e4 | 475 | /* Setting the MAC address to the device */ |
c857ff6e | 476 | for (i = 0; i < ETH_ALEN; i++) |
6aa20a22 | 477 | writeb( dev->dev_addr[i], mmio + PADR + i ); |
1da177e4 LT |
478 | |
479 | /* Enable interrupt coalesce */ | |
480 | if(lp->options & OPTION_INTR_COAL_ENABLE){ | |
f7afbaa5 | 481 | netdev_info(dev, "Interrupt Coalescing Enabled.\n"); |
1da177e4 LT |
482 | amd8111e_set_coalesce(dev,ENABLE_COAL); |
483 | } | |
6aa20a22 | 484 | |
1da177e4 LT |
485 | /* set RUN bit to start the chip */ |
486 | writel(VAL2 | RDMD0, mmio + CMD0); | |
487 | writel(VAL0 | INTREN | RUN, mmio + CMD0); | |
6aa20a22 | 488 | |
1da177e4 LT |
489 | /* To avoid PCI posting bug */ |
490 | readl(mmio+CMD0); | |
491 | return 0; | |
492 | } | |
13a4fa43 VB |
493 | |
494 | /* This function clears necessary the device registers. */ | |
46c73ecc | 495 | static void amd8111e_init_hw_default(struct amd8111e_priv *lp) |
1da177e4 LT |
496 | { |
497 | unsigned int reg_val; | |
498 | unsigned int logic_filter[2] ={0,}; | |
499 | void __iomem *mmio = lp->mmio; | |
500 | ||
501 | ||
502 | /* stop the chip */ | |
503 | writel(RUN, mmio + CMD0); | |
504 | ||
505 | /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */ | |
506 | writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0); | |
507 | ||
508 | /* Clear RCV_RING_BASE_ADDR */ | |
509 | writel(0, mmio + RCV_RING_BASE_ADDR0); | |
510 | ||
511 | /* Clear XMT_RING_BASE_ADDR */ | |
512 | writel(0, mmio + XMT_RING_BASE_ADDR0); | |
513 | writel(0, mmio + XMT_RING_BASE_ADDR1); | |
514 | writel(0, mmio + XMT_RING_BASE_ADDR2); | |
515 | writel(0, mmio + XMT_RING_BASE_ADDR3); | |
516 | ||
517 | /* Clear CMD0 */ | |
518 | writel(CMD0_CLEAR,mmio + CMD0); | |
6aa20a22 | 519 | |
1da177e4 LT |
520 | /* Clear CMD2 */ |
521 | writel(CMD2_CLEAR, mmio +CMD2); | |
522 | ||
523 | /* Clear CMD7 */ | |
524 | writel(CMD7_CLEAR , mmio + CMD7); | |
525 | ||
526 | /* Clear DLY_INT_A and DLY_INT_B */ | |
527 | writel(0x0, mmio + DLY_INT_A); | |
528 | writel(0x0, mmio + DLY_INT_B); | |
529 | ||
530 | /* Clear FLOW_CONTROL */ | |
531 | writel(0x0, mmio + FLOW_CONTROL); | |
532 | ||
533 | /* Clear INT0 write 1 to clear register */ | |
534 | reg_val = readl(mmio + INT0); | |
535 | writel(reg_val, mmio + INT0); | |
536 | ||
537 | /* Clear STVAL */ | |
538 | writel(0x0, mmio + STVAL); | |
539 | ||
540 | /* Clear INTEN0 */ | |
541 | writel( INTEN0_CLEAR, mmio + INTEN0); | |
542 | ||
543 | /* Clear LADRF */ | |
544 | writel(0x0 , mmio + LADRF); | |
545 | ||
546 | /* Set SRAM_SIZE & SRAM_BOUNDARY registers */ | |
547 | writel( 0x80010,mmio + SRAM_SIZE); | |
548 | ||
549 | /* Clear RCV_RING0_LEN */ | |
550 | writel(0x0, mmio + RCV_RING_LEN0); | |
551 | ||
552 | /* Clear XMT_RING0/1/2/3_LEN */ | |
553 | writel(0x0, mmio + XMT_RING_LEN0); | |
554 | writel(0x0, mmio + XMT_RING_LEN1); | |
555 | writel(0x0, mmio + XMT_RING_LEN2); | |
556 | writel(0x0, mmio + XMT_RING_LEN3); | |
557 | ||
558 | /* Clear XMT_RING_LIMIT */ | |
559 | writel(0x0, mmio + XMT_RING_LIMIT); | |
560 | ||
561 | /* Clear MIB */ | |
562 | writew(MIB_CLEAR, mmio + MIB_ADDR); | |
563 | ||
564 | /* Clear LARF */ | |
46c73ecc | 565 | amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF); |
1da177e4 LT |
566 | |
567 | /* SRAM_SIZE register */ | |
568 | reg_val = readl(mmio + SRAM_SIZE); | |
6aa20a22 | 569 | |
1da177e4 LT |
570 | if(lp->options & OPTION_JUMBO_ENABLE) |
571 | writel( VAL2|JUMBO, mmio + CMD3); | |
572 | #if AMD8111E_VLAN_TAG_USED | |
573 | writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 ); | |
574 | #endif | |
575 | /* Set default value to CTRL1 Register */ | |
576 | writel(CTRL1_DEFAULT, mmio + CTRL1); | |
577 | ||
578 | /* To avoid PCI posting bug */ | |
579 | readl(mmio + CMD2); | |
580 | ||
581 | } | |
582 | ||
13a4fa43 VB |
583 | /* This function disables the interrupt and clears all the pending |
584 | * interrupts in INT0 | |
1da177e4 | 585 | */ |
46c73ecc | 586 | static void amd8111e_disable_interrupt(struct amd8111e_priv *lp) |
6aa20a22 | 587 | { |
1da177e4 LT |
588 | u32 intr0; |
589 | ||
590 | /* Disable interrupt */ | |
591 | writel(INTREN, lp->mmio + CMD0); | |
6aa20a22 | 592 | |
1da177e4 LT |
593 | /* Clear INT0 */ |
594 | intr0 = readl(lp->mmio + INT0); | |
595 | writel(intr0, lp->mmio + INT0); | |
6aa20a22 | 596 | |
1da177e4 LT |
597 | /* To avoid PCI posting bug */ |
598 | readl(lp->mmio + INT0); | |
599 | ||
600 | } | |
601 | ||
13a4fa43 | 602 | /* This function stops the chip. */ |
46c73ecc | 603 | static void amd8111e_stop_chip(struct amd8111e_priv *lp) |
1da177e4 LT |
604 | { |
605 | writel(RUN, lp->mmio + CMD0); | |
6aa20a22 | 606 | |
1da177e4 LT |
607 | /* To avoid PCI posting bug */ |
608 | readl(lp->mmio + CMD0); | |
609 | } | |
610 | ||
13a4fa43 | 611 | /* This function frees the transmiter and receiver descriptor rings. */ |
46c73ecc | 612 | static void amd8111e_free_ring(struct amd8111e_priv *lp) |
6aa20a22 | 613 | { |
1da177e4 LT |
614 | /* Free transmit and receive descriptor rings */ |
615 | if(lp->rx_ring){ | |
6aa20a22 | 616 | pci_free_consistent(lp->pci_dev, |
1da177e4 LT |
617 | sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, |
618 | lp->rx_ring, lp->rx_ring_dma_addr); | |
619 | lp->rx_ring = NULL; | |
620 | } | |
6aa20a22 | 621 | |
1da177e4 | 622 | if(lp->tx_ring){ |
6aa20a22 | 623 | pci_free_consistent(lp->pci_dev, |
1da177e4 LT |
624 | sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, |
625 | lp->tx_ring, lp->tx_ring_dma_addr); | |
626 | ||
627 | lp->tx_ring = NULL; | |
628 | } | |
629 | ||
630 | } | |
1da177e4 | 631 | |
13a4fa43 VB |
632 | /* This function will free all the transmit skbs that are actually |
633 | * transmitted by the device. It will check the ownership of the | |
634 | * skb before freeing the skb. | |
635 | */ | |
1da177e4 LT |
636 | static int amd8111e_tx(struct net_device *dev) |
637 | { | |
46c73ecc | 638 | struct amd8111e_priv *lp = netdev_priv(dev); |
129fbeec | 639 | int tx_index; |
1da177e4 LT |
640 | int status; |
641 | /* Complete all the transmit packet */ | |
642 | while (lp->tx_complete_idx != lp->tx_idx){ | |
643 | tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; | |
644 | status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags); | |
645 | ||
646 | if(status & OWN_BIT) | |
647 | break; /* It still hasn't been Txed */ | |
648 | ||
649 | lp->tx_ring[tx_index].buff_phy_addr = 0; | |
650 | ||
651 | /* We must free the original skb */ | |
652 | if (lp->tx_skbuff[tx_index]) { | |
653 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index], | |
654 | lp->tx_skbuff[tx_index]->len, | |
655 | PCI_DMA_TODEVICE); | |
3afa73dd | 656 | dev_consume_skb_irq(lp->tx_skbuff[tx_index]); |
1da177e4 LT |
657 | lp->tx_skbuff[tx_index] = NULL; |
658 | lp->tx_dma_addr[tx_index] = 0; | |
659 | } | |
660 | lp->tx_complete_idx++; | |
661 | /*COAL update tx coalescing parameters */ | |
662 | lp->coal_conf.tx_packets++; | |
05d2fec9 AV |
663 | lp->coal_conf.tx_bytes += |
664 | le16_to_cpu(lp->tx_ring[tx_index].buff_count); | |
1da177e4 LT |
665 | |
666 | if (netif_queue_stopped(dev) && | |
667 | lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){ | |
668 | /* The ring is no longer full, clear tbusy. */ | |
669 | /* lp->tx_full = 0; */ | |
670 | netif_wake_queue (dev); | |
671 | } | |
672 | } | |
673 | return 0; | |
674 | } | |
675 | ||
1da177e4 | 676 | /* This function handles the driver receive operation in polling mode */ |
bea3348e | 677 | static int amd8111e_rx_poll(struct napi_struct *napi, int budget) |
1da177e4 | 678 | { |
bea3348e SH |
679 | struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi); |
680 | struct net_device *dev = lp->amd8111e_net_dev; | |
1da177e4 LT |
681 | int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK; |
682 | void __iomem *mmio = lp->mmio; | |
683 | struct sk_buff *skb,*new_skb; | |
684 | int min_pkt_len, status; | |
1da177e4 | 685 | int num_rx_pkt = 0; |
1da177e4 | 686 | short pkt_len; |
6aa20a22 | 687 | #if AMD8111E_VLAN_TAG_USED |
1da177e4 LT |
688 | short vtag; |
689 | #endif | |
6aa20a22 | 690 | |
c46e9907 ED |
691 | while (num_rx_pkt < budget) { |
692 | status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags); | |
693 | if (status & OWN_BIT) | |
694 | break; | |
278d5385 | 695 | |
c46e9907 ED |
696 | /* There is a tricky error noted by John Murphy, |
697 | * <murf@perftech.com> to Russ Nelson: Even with | |
698 | * full-sized * buffers it's possible for a | |
699 | * jabber packet to use two buffers, with only | |
700 | * the last correctly noting the error. | |
13a4fa43 | 701 | */ |
c46e9907 ED |
702 | if (status & ERR_BIT) { |
703 | /* resetting flags */ | |
704 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; | |
705 | goto err_next_pkt; | |
706 | } | |
707 | /* check for STP and ENP */ | |
708 | if (!((status & STP_BIT) && (status & ENP_BIT))){ | |
709 | /* resetting flags */ | |
710 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; | |
711 | goto err_next_pkt; | |
712 | } | |
713 | pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4; | |
1da177e4 | 714 | |
6aa20a22 | 715 | #if AMD8111E_VLAN_TAG_USED |
c46e9907 ED |
716 | vtag = status & TT_MASK; |
717 | /* MAC will strip vlan tag */ | |
718 | if (vtag != 0) | |
719 | min_pkt_len = MIN_PKT_LEN - 4; | |
1da177e4 LT |
720 | else |
721 | #endif | |
c46e9907 ED |
722 | min_pkt_len = MIN_PKT_LEN; |
723 | ||
724 | if (pkt_len < min_pkt_len) { | |
725 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; | |
726 | lp->drv_rx_errors++; | |
727 | goto err_next_pkt; | |
728 | } | |
729 | new_skb = netdev_alloc_skb(dev, lp->rx_buff_len); | |
730 | if (!new_skb) { | |
731 | /* if allocation fail, | |
732 | * ignore that pkt and go to next one | |
733 | */ | |
734 | lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; | |
735 | lp->drv_rx_errors++; | |
736 | goto err_next_pkt; | |
737 | } | |
738 | ||
739 | skb_reserve(new_skb, 2); | |
740 | skb = lp->rx_skbuff[rx_index]; | |
741 | pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index], | |
742 | lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); | |
743 | skb_put(skb, pkt_len); | |
744 | lp->rx_skbuff[rx_index] = new_skb; | |
745 | lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev, | |
746 | new_skb->data, | |
747 | lp->rx_buff_len-2, | |
748 | PCI_DMA_FROMDEVICE); | |
749 | ||
750 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 751 | |
6aa20a22 | 752 | #if AMD8111E_VLAN_TAG_USED |
c46e9907 ED |
753 | if (vtag == TT_VLAN_TAGGED){ |
754 | u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); | |
755 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
1da177e4 | 756 | } |
c46e9907 ED |
757 | #endif |
758 | napi_gro_receive(napi, skb); | |
759 | /* COAL update rx coalescing parameters */ | |
760 | lp->coal_conf.rx_packets++; | |
761 | lp->coal_conf.rx_bytes += pkt_len; | |
762 | num_rx_pkt++; | |
763 | ||
764 | err_next_pkt: | |
765 | lp->rx_ring[rx_index].buff_phy_addr | |
766 | = cpu_to_le32(lp->rx_dma_addr[rx_index]); | |
767 | lp->rx_ring[rx_index].buff_count = | |
768 | cpu_to_le16(lp->rx_buff_len-2); | |
769 | wmb(); | |
770 | lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT); | |
771 | rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK; | |
772 | } | |
1da177e4 | 773 | |
c46e9907 ED |
774 | if (num_rx_pkt < budget && napi_complete_done(napi, num_rx_pkt)) { |
775 | unsigned long flags; | |
1da177e4 | 776 | |
48e5ecae CF |
777 | /* Receive descriptor is empty now */ |
778 | spin_lock_irqsave(&lp->lock, flags); | |
48e5ecae CF |
779 | writel(VAL0|RINTEN0, mmio + INTEN0); |
780 | writel(VAL2 | RDMD0, mmio + CMD0); | |
781 | spin_unlock_irqrestore(&lp->lock, flags); | |
782 | } | |
dfa1b73f | 783 | |
bea3348e | 784 | return num_rx_pkt; |
1da177e4 LT |
785 | } |
786 | ||
13a4fa43 | 787 | /* This function will indicate the link status to the kernel. */ |
46c73ecc | 788 | static int amd8111e_link_change(struct net_device *dev) |
6aa20a22 | 789 | { |
1da177e4 LT |
790 | struct amd8111e_priv *lp = netdev_priv(dev); |
791 | int status0,speed; | |
792 | ||
793 | /* read the link change */ | |
794 | status0 = readl(lp->mmio + STAT0); | |
6aa20a22 | 795 | |
1da177e4 LT |
796 | if(status0 & LINK_STATS){ |
797 | if(status0 & AUTONEG_COMPLETE) | |
798 | lp->link_config.autoneg = AUTONEG_ENABLE; | |
6aa20a22 | 799 | else |
1da177e4 LT |
800 | lp->link_config.autoneg = AUTONEG_DISABLE; |
801 | ||
802 | if(status0 & FULL_DPLX) | |
803 | lp->link_config.duplex = DUPLEX_FULL; | |
6aa20a22 | 804 | else |
1da177e4 LT |
805 | lp->link_config.duplex = DUPLEX_HALF; |
806 | speed = (status0 & SPEED_MASK) >> 7; | |
807 | if(speed == PHY_SPEED_10) | |
808 | lp->link_config.speed = SPEED_10; | |
809 | else if(speed == PHY_SPEED_100) | |
810 | lp->link_config.speed = SPEED_100; | |
811 | ||
f7afbaa5 VB |
812 | netdev_info(dev, "Link is Up. Speed is %s Mbps %s Duplex\n", |
813 | (lp->link_config.speed == SPEED_100) ? | |
814 | "100" : "10", | |
815 | (lp->link_config.duplex == DUPLEX_FULL) ? | |
816 | "Full" : "Half"); | |
817 | ||
1da177e4 LT |
818 | netif_carrier_on(dev); |
819 | } | |
6aa20a22 | 820 | else{ |
1da177e4 LT |
821 | lp->link_config.speed = SPEED_INVALID; |
822 | lp->link_config.duplex = DUPLEX_INVALID; | |
823 | lp->link_config.autoneg = AUTONEG_INVALID; | |
f7afbaa5 | 824 | netdev_info(dev, "Link is Down.\n"); |
1da177e4 LT |
825 | netif_carrier_off(dev); |
826 | } | |
6aa20a22 | 827 | |
1da177e4 LT |
828 | return 0; |
829 | } | |
13a4fa43 VB |
830 | |
831 | /* This function reads the mib counters. */ | |
1da177e4 LT |
832 | static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) |
833 | { | |
834 | unsigned int status; | |
835 | unsigned int data; | |
836 | unsigned int repeat = REPEAT_CNT; | |
837 | ||
838 | writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR); | |
839 | do { | |
840 | status = readw(mmio + MIB_ADDR); | |
841 | udelay(2); /* controller takes MAX 2 us to get mib data */ | |
842 | } | |
843 | while (--repeat && (status & MIB_CMD_ACTIVE)); | |
844 | ||
845 | data = readl(mmio + MIB_DATA); | |
846 | return data; | |
847 | } | |
848 | ||
13a4fa43 | 849 | /* This function reads the mib registers and returns the hardware statistics. |
c3227e54 ED |
850 | * It updates previous internal driver statistics with new values. |
851 | */ | |
852 | static struct net_device_stats *amd8111e_get_stats(struct net_device *dev) | |
1da177e4 LT |
853 | { |
854 | struct amd8111e_priv *lp = netdev_priv(dev); | |
855 | void __iomem *mmio = lp->mmio; | |
856 | unsigned long flags; | |
c3227e54 | 857 | struct net_device_stats *new_stats = &dev->stats; |
6aa20a22 | 858 | |
c3227e54 ED |
859 | if (!lp->opened) |
860 | return new_stats; | |
1da177e4 LT |
861 | spin_lock_irqsave (&lp->lock, flags); |
862 | ||
863 | /* stats.rx_packets */ | |
864 | new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+ | |
865 | amd8111e_read_mib(mmio, rcv_multicast_pkts)+ | |
866 | amd8111e_read_mib(mmio, rcv_unicast_pkts); | |
867 | ||
868 | /* stats.tx_packets */ | |
869 | new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets); | |
870 | ||
871 | /*stats.rx_bytes */ | |
872 | new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets); | |
873 | ||
874 | /* stats.tx_bytes */ | |
875 | new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets); | |
876 | ||
877 | /* stats.rx_errors */ | |
878 | /* hw errors + errors driver reported */ | |
879 | new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+ | |
880 | amd8111e_read_mib(mmio, rcv_fragments)+ | |
881 | amd8111e_read_mib(mmio, rcv_jabbers)+ | |
882 | amd8111e_read_mib(mmio, rcv_alignment_errors)+ | |
883 | amd8111e_read_mib(mmio, rcv_fcs_errors)+ | |
884 | amd8111e_read_mib(mmio, rcv_miss_pkts)+ | |
885 | lp->drv_rx_errors; | |
886 | ||
887 | /* stats.tx_errors */ | |
888 | new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); | |
889 | ||
890 | /* stats.rx_dropped*/ | |
891 | new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts); | |
892 | ||
893 | /* stats.tx_dropped*/ | |
894 | new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts); | |
895 | ||
896 | /* stats.multicast*/ | |
897 | new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts); | |
898 | ||
899 | /* stats.collisions*/ | |
900 | new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions); | |
901 | ||
902 | /* stats.rx_length_errors*/ | |
6aa20a22 | 903 | new_stats->rx_length_errors = |
1da177e4 LT |
904 | amd8111e_read_mib(mmio, rcv_undersize_pkts)+ |
905 | amd8111e_read_mib(mmio, rcv_oversize_pkts); | |
906 | ||
907 | /* stats.rx_over_errors*/ | |
908 | new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); | |
909 | ||
910 | /* stats.rx_crc_errors*/ | |
911 | new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors); | |
912 | ||
913 | /* stats.rx_frame_errors*/ | |
914 | new_stats->rx_frame_errors = | |
915 | amd8111e_read_mib(mmio, rcv_alignment_errors); | |
916 | ||
917 | /* stats.rx_fifo_errors */ | |
918 | new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); | |
919 | ||
920 | /* stats.rx_missed_errors */ | |
921 | new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); | |
922 | ||
923 | /* stats.tx_aborted_errors*/ | |
6aa20a22 | 924 | new_stats->tx_aborted_errors = |
1da177e4 LT |
925 | amd8111e_read_mib(mmio, xmt_excessive_collision); |
926 | ||
927 | /* stats.tx_carrier_errors*/ | |
6aa20a22 | 928 | new_stats->tx_carrier_errors = |
1da177e4 LT |
929 | amd8111e_read_mib(mmio, xmt_loss_carrier); |
930 | ||
931 | /* stats.tx_fifo_errors*/ | |
932 | new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); | |
933 | ||
934 | /* stats.tx_window_errors*/ | |
935 | new_stats->tx_window_errors = | |
936 | amd8111e_read_mib(mmio, xmt_late_collision); | |
937 | ||
938 | /* Reset the mibs for collecting new statistics */ | |
939 | /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/ | |
6aa20a22 | 940 | |
1da177e4 LT |
941 | spin_unlock_irqrestore (&lp->lock, flags); |
942 | ||
943 | return new_stats; | |
944 | } | |
13a4fa43 | 945 | |
3a4fa0a2 | 946 | /* This function recalculate the interrupt coalescing mode on every interrupt |
13a4fa43 VB |
947 | * according to the datarate and the packet rate. |
948 | */ | |
1da177e4 LT |
949 | static int amd8111e_calc_coalesce(struct net_device *dev) |
950 | { | |
951 | struct amd8111e_priv *lp = netdev_priv(dev); | |
46c73ecc | 952 | struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf; |
1da177e4 LT |
953 | int tx_pkt_rate; |
954 | int rx_pkt_rate; | |
955 | int tx_data_rate; | |
956 | int rx_data_rate; | |
957 | int rx_pkt_size; | |
958 | int tx_pkt_size; | |
959 | ||
960 | tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets; | |
961 | coal_conf->tx_prev_packets = coal_conf->tx_packets; | |
6aa20a22 | 962 | |
1da177e4 LT |
963 | tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes; |
964 | coal_conf->tx_prev_bytes = coal_conf->tx_bytes; | |
6aa20a22 | 965 | |
1da177e4 LT |
966 | rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets; |
967 | coal_conf->rx_prev_packets = coal_conf->rx_packets; | |
6aa20a22 | 968 | |
1da177e4 LT |
969 | rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes; |
970 | coal_conf->rx_prev_bytes = coal_conf->rx_bytes; | |
6aa20a22 | 971 | |
1da177e4 LT |
972 | if(rx_pkt_rate < 800){ |
973 | if(coal_conf->rx_coal_type != NO_COALESCE){ | |
6aa20a22 | 974 | |
1da177e4 LT |
975 | coal_conf->rx_timeout = 0x0; |
976 | coal_conf->rx_event_count = 0; | |
977 | amd8111e_set_coalesce(dev,RX_INTR_COAL); | |
978 | coal_conf->rx_coal_type = NO_COALESCE; | |
979 | } | |
980 | } | |
981 | else{ | |
6aa20a22 | 982 | |
1da177e4 LT |
983 | rx_pkt_size = rx_data_rate/rx_pkt_rate; |
984 | if (rx_pkt_size < 128){ | |
985 | if(coal_conf->rx_coal_type != NO_COALESCE){ | |
6aa20a22 | 986 | |
1da177e4 LT |
987 | coal_conf->rx_timeout = 0; |
988 | coal_conf->rx_event_count = 0; | |
989 | amd8111e_set_coalesce(dev,RX_INTR_COAL); | |
990 | coal_conf->rx_coal_type = NO_COALESCE; | |
991 | } | |
992 | ||
993 | } | |
994 | else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){ | |
6aa20a22 | 995 | |
1da177e4 LT |
996 | if(coal_conf->rx_coal_type != LOW_COALESCE){ |
997 | coal_conf->rx_timeout = 1; | |
998 | coal_conf->rx_event_count = 4; | |
999 | amd8111e_set_coalesce(dev,RX_INTR_COAL); | |
1000 | coal_conf->rx_coal_type = LOW_COALESCE; | |
1001 | } | |
1002 | } | |
1003 | else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){ | |
6aa20a22 | 1004 | |
1da177e4 LT |
1005 | if(coal_conf->rx_coal_type != MEDIUM_COALESCE){ |
1006 | coal_conf->rx_timeout = 1; | |
1007 | coal_conf->rx_event_count = 4; | |
1008 | amd8111e_set_coalesce(dev,RX_INTR_COAL); | |
1009 | coal_conf->rx_coal_type = MEDIUM_COALESCE; | |
6aa20a22 JG |
1010 | } |
1011 | ||
1da177e4 LT |
1012 | } |
1013 | else if(rx_pkt_size >= 1024){ | |
1014 | if(coal_conf->rx_coal_type != HIGH_COALESCE){ | |
1015 | coal_conf->rx_timeout = 2; | |
1016 | coal_conf->rx_event_count = 3; | |
1017 | amd8111e_set_coalesce(dev,RX_INTR_COAL); | |
1018 | coal_conf->rx_coal_type = HIGH_COALESCE; | |
6aa20a22 | 1019 | } |
1da177e4 LT |
1020 | } |
1021 | } | |
1022 | /* NOW FOR TX INTR COALESC */ | |
1023 | if(tx_pkt_rate < 800){ | |
1024 | if(coal_conf->tx_coal_type != NO_COALESCE){ | |
6aa20a22 | 1025 | |
1da177e4 LT |
1026 | coal_conf->tx_timeout = 0x0; |
1027 | coal_conf->tx_event_count = 0; | |
1028 | amd8111e_set_coalesce(dev,TX_INTR_COAL); | |
1029 | coal_conf->tx_coal_type = NO_COALESCE; | |
1030 | } | |
1031 | } | |
1032 | else{ | |
6aa20a22 | 1033 | |
1da177e4 LT |
1034 | tx_pkt_size = tx_data_rate/tx_pkt_rate; |
1035 | if (tx_pkt_size < 128){ | |
6aa20a22 | 1036 | |
1da177e4 | 1037 | if(coal_conf->tx_coal_type != NO_COALESCE){ |
6aa20a22 | 1038 | |
1da177e4 LT |
1039 | coal_conf->tx_timeout = 0; |
1040 | coal_conf->tx_event_count = 0; | |
1041 | amd8111e_set_coalesce(dev,TX_INTR_COAL); | |
1042 | coal_conf->tx_coal_type = NO_COALESCE; | |
1043 | } | |
1044 | ||
1045 | } | |
1046 | else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){ | |
6aa20a22 | 1047 | |
1da177e4 LT |
1048 | if(coal_conf->tx_coal_type != LOW_COALESCE){ |
1049 | coal_conf->tx_timeout = 1; | |
1050 | coal_conf->tx_event_count = 2; | |
1051 | amd8111e_set_coalesce(dev,TX_INTR_COAL); | |
1052 | coal_conf->tx_coal_type = LOW_COALESCE; | |
1053 | ||
1054 | } | |
1055 | } | |
1056 | else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){ | |
6aa20a22 | 1057 | |
1da177e4 LT |
1058 | if(coal_conf->tx_coal_type != MEDIUM_COALESCE){ |
1059 | coal_conf->tx_timeout = 2; | |
1060 | coal_conf->tx_event_count = 5; | |
1061 | amd8111e_set_coalesce(dev,TX_INTR_COAL); | |
1062 | coal_conf->tx_coal_type = MEDIUM_COALESCE; | |
6aa20a22 | 1063 | } |
4d7b4483 CIK |
1064 | } else if (tx_pkt_size >= 1024) { |
1065 | if (coal_conf->tx_coal_type != HIGH_COALESCE) { | |
1066 | coal_conf->tx_timeout = 4; | |
1067 | coal_conf->tx_event_count = 8; | |
1068 | amd8111e_set_coalesce(dev, TX_INTR_COAL); | |
1069 | coal_conf->tx_coal_type = HIGH_COALESCE; | |
1da177e4 LT |
1070 | } |
1071 | } | |
1072 | } | |
1073 | return 0; | |
1074 | ||
1075 | } | |
13a4fa43 VB |
1076 | |
1077 | /* This is device interrupt function. It handles transmit, | |
1078 | * receive,link change and hardware timer interrupts. | |
1079 | */ | |
7d12e780 | 1080 | static irqreturn_t amd8111e_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1081 | { |
1082 | ||
46c73ecc | 1083 | struct net_device *dev = (struct net_device *)dev_id; |
1da177e4 LT |
1084 | struct amd8111e_priv *lp = netdev_priv(dev); |
1085 | void __iomem *mmio = lp->mmio; | |
dfa1b73f | 1086 | unsigned int intr0, intren0; |
1da177e4 LT |
1087 | unsigned int handled = 1; |
1088 | ||
dfa1b73f | 1089 | if(unlikely(dev == NULL)) |
1da177e4 LT |
1090 | return IRQ_NONE; |
1091 | ||
dfa1b73f LT |
1092 | spin_lock(&lp->lock); |
1093 | ||
1da177e4 LT |
1094 | /* disabling interrupt */ |
1095 | writel(INTREN, mmio + CMD0); | |
1096 | ||
1097 | /* Read interrupt status */ | |
1098 | intr0 = readl(mmio + INT0); | |
dfa1b73f | 1099 | intren0 = readl(mmio + INTEN0); |
1da177e4 LT |
1100 | |
1101 | /* Process all the INT event until INTR bit is clear. */ | |
1102 | ||
1103 | if (!(intr0 & INTR)){ | |
1104 | handled = 0; | |
1105 | goto err_no_interrupt; | |
1106 | } | |
6aa20a22 | 1107 | |
1da177e4 LT |
1108 | /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */ |
1109 | writel(intr0, mmio + INT0); | |
1110 | ||
1111 | /* Check if Receive Interrupt has occurred. */ | |
6ba33ac8 | 1112 | if (intr0 & RINT0) { |
288379f0 | 1113 | if (napi_schedule_prep(&lp->napi)) { |
1da177e4 LT |
1114 | /* Disable receive interupts */ |
1115 | writel(RINTEN0, mmio + INTEN0); | |
1116 | /* Schedule a polling routine */ | |
288379f0 | 1117 | __napi_schedule(&lp->napi); |
6ba33ac8 | 1118 | } else if (intren0 & RINTEN0) { |
f7afbaa5 | 1119 | netdev_dbg(dev, "************Driver bug! interrupt while in poll\n"); |
dfa1b73f LT |
1120 | /* Fix by disable receive interrupts */ |
1121 | writel(RINTEN0, mmio + INTEN0); | |
1da177e4 LT |
1122 | } |
1123 | } | |
6ba33ac8 | 1124 | |
1da177e4 | 1125 | /* Check if Transmit Interrupt has occurred. */ |
6ba33ac8 | 1126 | if (intr0 & TINT0) |
1da177e4 | 1127 | amd8111e_tx(dev); |
6aa20a22 | 1128 | |
1da177e4 LT |
1129 | /* Check if Link Change Interrupt has occurred. */ |
1130 | if (intr0 & LCINT) | |
1131 | amd8111e_link_change(dev); | |
1132 | ||
1133 | /* Check if Hardware Timer Interrupt has occurred. */ | |
1134 | if (intr0 & STINT) | |
1135 | amd8111e_calc_coalesce(dev); | |
1136 | ||
1137 | err_no_interrupt: | |
1138 | writel( VAL0 | INTREN,mmio + CMD0); | |
6aa20a22 | 1139 | |
dfa1b73f | 1140 | spin_unlock(&lp->lock); |
6aa20a22 | 1141 | |
1da177e4 LT |
1142 | return IRQ_RETVAL(handled); |
1143 | } | |
1144 | ||
1145 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1146 | static void amd8111e_poll(struct net_device *dev) | |
6aa20a22 | 1147 | { |
1da177e4 | 1148 | unsigned long flags; |
b7e36bfa | 1149 | local_irq_save(flags); |
7d12e780 | 1150 | amd8111e_interrupt(0, dev); |
6aa20a22 JG |
1151 | local_irq_restore(flags); |
1152 | } | |
1da177e4 LT |
1153 | #endif |
1154 | ||
1155 | ||
13a4fa43 VB |
1156 | /* This function closes the network interface and updates |
1157 | * the statistics so that most recent statistics will be | |
1158 | * available after the interface is down. | |
1159 | */ | |
46c73ecc | 1160 | static int amd8111e_close(struct net_device *dev) |
1da177e4 LT |
1161 | { |
1162 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1163 | netif_stop_queue(dev); | |
6aa20a22 | 1164 | |
bea3348e SH |
1165 | napi_disable(&lp->napi); |
1166 | ||
1da177e4 | 1167 | spin_lock_irq(&lp->lock); |
6aa20a22 | 1168 | |
1da177e4 LT |
1169 | amd8111e_disable_interrupt(lp); |
1170 | amd8111e_stop_chip(lp); | |
e83603fd CL |
1171 | |
1172 | /* Free transmit and receive skbs */ | |
1173 | amd8111e_free_skbs(lp->amd8111e_net_dev); | |
6aa20a22 | 1174 | |
1da177e4 LT |
1175 | netif_carrier_off(lp->amd8111e_net_dev); |
1176 | ||
1177 | /* Delete ipg timer */ | |
6aa20a22 | 1178 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
1da177e4 LT |
1179 | del_timer_sync(&lp->ipg_data.ipg_timer); |
1180 | ||
1181 | spin_unlock_irq(&lp->lock); | |
1182 | free_irq(dev->irq, dev); | |
e83603fd | 1183 | amd8111e_free_ring(lp); |
6aa20a22 | 1184 | |
1da177e4 LT |
1185 | /* Update the statistics before closing */ |
1186 | amd8111e_get_stats(dev); | |
1187 | lp->opened = 0; | |
1188 | return 0; | |
1189 | } | |
13a4fa43 VB |
1190 | |
1191 | /* This function opens new interface.It requests irq for the device, | |
1192 | * initializes the device,buffers and descriptors, and starts the device. | |
1193 | */ | |
46c73ecc | 1194 | static int amd8111e_open(struct net_device *dev) |
1da177e4 LT |
1195 | { |
1196 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1197 | ||
1fb9df5d | 1198 | if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED, |
6aa20a22 | 1199 | dev->name, dev)) |
1da177e4 LT |
1200 | return -EAGAIN; |
1201 | ||
bea3348e SH |
1202 | napi_enable(&lp->napi); |
1203 | ||
1da177e4 LT |
1204 | spin_lock_irq(&lp->lock); |
1205 | ||
1206 | amd8111e_init_hw_default(lp); | |
1207 | ||
1208 | if(amd8111e_restart(dev)){ | |
1209 | spin_unlock_irq(&lp->lock); | |
bea3348e | 1210 | napi_disable(&lp->napi); |
1da177e4 LT |
1211 | if (dev->irq) |
1212 | free_irq(dev->irq, dev); | |
1213 | return -ENOMEM; | |
1214 | } | |
1215 | /* Start ipg timer */ | |
6aa20a22 | 1216 | if(lp->options & OPTION_DYN_IPG_ENABLE){ |
1da177e4 | 1217 | add_timer(&lp->ipg_data.ipg_timer); |
f7afbaa5 | 1218 | netdev_info(dev, "Dynamic IPG Enabled\n"); |
1da177e4 LT |
1219 | } |
1220 | ||
1221 | lp->opened = 1; | |
1222 | ||
1223 | spin_unlock_irq(&lp->lock); | |
1224 | ||
1225 | netif_start_queue(dev); | |
1226 | ||
6aa20a22 | 1227 | return 0; |
1da177e4 | 1228 | } |
13a4fa43 VB |
1229 | |
1230 | /* This function checks if there is any transmit descriptors | |
1231 | * available to queue more packet. | |
1232 | */ | |
46c73ecc | 1233 | static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp) |
6aa20a22 | 1234 | { |
1da177e4 | 1235 | int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK; |
ee41a82f | 1236 | if (lp->tx_skbuff[tx_index]) |
1da177e4 LT |
1237 | return -1; |
1238 | else | |
1239 | return 0; | |
6aa20a22 | 1240 | |
1da177e4 | 1241 | } |
1da177e4 | 1242 | |
13a4fa43 VB |
1243 | /* This function will queue the transmit packets to the |
1244 | * descriptors and will trigger the send operation. It also | |
1245 | * initializes the transmit descriptors with buffer physical address, | |
1246 | * byte count, ownership to hardware etc. | |
1247 | */ | |
61357325 | 1248 | static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb, |
46c73ecc | 1249 | struct net_device *dev) |
1da177e4 LT |
1250 | { |
1251 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1252 | int tx_index; | |
1253 | unsigned long flags; | |
1254 | ||
1255 | spin_lock_irqsave(&lp->lock, flags); | |
1256 | ||
1257 | tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK; | |
1258 | ||
1259 | lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len); | |
1260 | ||
1261 | lp->tx_skbuff[tx_index] = skb; | |
1262 | lp->tx_ring[tx_index].tx_flags = 0; | |
1263 | ||
1264 | #if AMD8111E_VLAN_TAG_USED | |
df8a39de | 1265 | if (skb_vlan_tag_present(skb)) { |
6aa20a22 JG |
1266 | lp->tx_ring[tx_index].tag_ctrl_cmd |= |
1267 | cpu_to_le16(TCC_VLAN_INSERT); | |
1268 | lp->tx_ring[tx_index].tag_ctrl_info = | |
df8a39de | 1269 | cpu_to_le16(skb_vlan_tag_get(skb)); |
1da177e4 LT |
1270 | |
1271 | } | |
1272 | #endif | |
1273 | lp->tx_dma_addr[tx_index] = | |
1274 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
1275 | lp->tx_ring[tx_index].buff_phy_addr = | |
ee41a82f | 1276 | cpu_to_le32(lp->tx_dma_addr[tx_index]); |
1da177e4 LT |
1277 | |
1278 | /* Set FCS and LTINT bits */ | |
1279 | wmb(); | |
1280 | lp->tx_ring[tx_index].tx_flags |= | |
1281 | cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT); | |
1282 | ||
1283 | lp->tx_idx++; | |
1284 | ||
1285 | /* Trigger an immediate send poll. */ | |
1286 | writel( VAL1 | TDMD0, lp->mmio + CMD0); | |
1287 | writel( VAL2 | RDMD0,lp->mmio + CMD0); | |
1288 | ||
1da177e4 LT |
1289 | if(amd8111e_tx_queue_avail(lp) < 0){ |
1290 | netif_stop_queue(dev); | |
1291 | } | |
1292 | spin_unlock_irqrestore(&lp->lock, flags); | |
6ed10654 | 1293 | return NETDEV_TX_OK; |
1da177e4 | 1294 | } |
13a4fa43 | 1295 | /* This function returns all the memory mapped registers of the device. */ |
1da177e4 LT |
1296 | static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf) |
1297 | { | |
1298 | void __iomem *mmio = lp->mmio; | |
1299 | /* Read only necessary registers */ | |
1300 | buf[0] = readl(mmio + XMT_RING_BASE_ADDR0); | |
1301 | buf[1] = readl(mmio + XMT_RING_LEN0); | |
1302 | buf[2] = readl(mmio + RCV_RING_BASE_ADDR0); | |
1303 | buf[3] = readl(mmio + RCV_RING_LEN0); | |
1304 | buf[4] = readl(mmio + CMD0); | |
1305 | buf[5] = readl(mmio + CMD2); | |
1306 | buf[6] = readl(mmio + CMD3); | |
1307 | buf[7] = readl(mmio + CMD7); | |
1308 | buf[8] = readl(mmio + INT0); | |
1309 | buf[9] = readl(mmio + INTEN0); | |
1310 | buf[10] = readl(mmio + LADRF); | |
1311 | buf[11] = readl(mmio + LADRF+4); | |
1312 | buf[12] = readl(mmio + STAT0); | |
1313 | } | |
1314 | ||
6aa20a22 | 1315 | |
13a4fa43 VB |
1316 | /* This function sets promiscuos mode, all-multi mode or the multicast address |
1317 | * list to the device. | |
1318 | */ | |
1da177e4 LT |
1319 | static void amd8111e_set_multicast_list(struct net_device *dev) |
1320 | { | |
22bedad3 | 1321 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1322 | struct amd8111e_priv *lp = netdev_priv(dev); |
1323 | u32 mc_filter[2] ; | |
0ddf477b JP |
1324 | int bit_num; |
1325 | ||
1da177e4 | 1326 | if(dev->flags & IFF_PROMISC){ |
1da177e4 LT |
1327 | writel( VAL2 | PROM, lp->mmio + CMD2); |
1328 | return; | |
1329 | } | |
1330 | else | |
1331 | writel( PROM, lp->mmio + CMD2); | |
4cd24eaf JP |
1332 | if (dev->flags & IFF_ALLMULTI || |
1333 | netdev_mc_count(dev) > MAX_FILTER_SIZE) { | |
1da177e4 LT |
1334 | /* get all multicast packet */ |
1335 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1da177e4 | 1336 | lp->options |= OPTION_MULTICAST_ENABLE; |
46c73ecc | 1337 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
1da177e4 LT |
1338 | return; |
1339 | } | |
4cd24eaf | 1340 | if (netdev_mc_empty(dev)) { |
1da177e4 LT |
1341 | /* get only own packets */ |
1342 | mc_filter[1] = mc_filter[0] = 0; | |
1da177e4 | 1343 | lp->options &= ~OPTION_MULTICAST_ENABLE; |
46c73ecc | 1344 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
25985edc | 1345 | /* disable promiscuous mode */ |
1da177e4 LT |
1346 | writel(PROM, lp->mmio + CMD2); |
1347 | return; | |
1348 | } | |
1349 | /* load all the multicast addresses in the logic filter */ | |
1350 | lp->options |= OPTION_MULTICAST_ENABLE; | |
1da177e4 | 1351 | mc_filter[1] = mc_filter[0] = 0; |
22bedad3 JP |
1352 | netdev_for_each_mc_addr(ha, dev) { |
1353 | bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f; | |
1da177e4 | 1354 | mc_filter[bit_num >> 5] |= 1 << (bit_num & 31); |
6aa20a22 | 1355 | } |
46c73ecc | 1356 | amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF); |
1da177e4 LT |
1357 | |
1358 | /* To eliminate PCI posting bug */ | |
1359 | readl(lp->mmio + CMD2); | |
1360 | ||
1361 | } | |
1362 | ||
46c73ecc VB |
1363 | static void amd8111e_get_drvinfo(struct net_device *dev, |
1364 | struct ethtool_drvinfo *info) | |
1da177e4 LT |
1365 | { |
1366 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1367 | struct pci_dev *pci_dev = lp->pci_dev; | |
23020ab3 RJ |
1368 | strlcpy(info->driver, MODULE_NAME, sizeof(info->driver)); |
1369 | strlcpy(info->version, MODULE_VERS, sizeof(info->version)); | |
1370 | snprintf(info->fw_version, sizeof(info->fw_version), | |
1371 | "%u", chip_version); | |
1372 | strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1373 | } |
1374 | ||
1375 | static int amd8111e_get_regs_len(struct net_device *dev) | |
1376 | { | |
1377 | return AMD8111E_REG_DUMP_LEN; | |
1378 | } | |
1379 | ||
1380 | static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
1381 | { | |
1382 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1383 | regs->version = 0; | |
1384 | amd8111e_read_regs(lp, buf); | |
1385 | } | |
1386 | ||
1435003c PR |
1387 | static int amd8111e_get_link_ksettings(struct net_device *dev, |
1388 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1389 | { |
1390 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1391 | spin_lock_irq(&lp->lock); | |
1435003c | 1392 | mii_ethtool_get_link_ksettings(&lp->mii_if, cmd); |
1da177e4 LT |
1393 | spin_unlock_irq(&lp->lock); |
1394 | return 0; | |
1395 | } | |
1396 | ||
1435003c PR |
1397 | static int amd8111e_set_link_ksettings(struct net_device *dev, |
1398 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1399 | { |
1400 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1401 | int res; | |
1402 | spin_lock_irq(&lp->lock); | |
1435003c | 1403 | res = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd); |
1da177e4 LT |
1404 | spin_unlock_irq(&lp->lock); |
1405 | return res; | |
1406 | } | |
1407 | ||
1408 | static int amd8111e_nway_reset(struct net_device *dev) | |
1409 | { | |
1410 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1411 | return mii_nway_restart(&lp->mii_if); | |
1412 | } | |
1413 | ||
1414 | static u32 amd8111e_get_link(struct net_device *dev) | |
1415 | { | |
1416 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1417 | return mii_link_ok(&lp->mii_if); | |
1418 | } | |
1419 | ||
1420 | static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) | |
1421 | { | |
1422 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1423 | wol_info->supported = WAKE_MAGIC|WAKE_PHY; | |
1424 | if (lp->options & OPTION_WOL_ENABLE) | |
1425 | wol_info->wolopts = WAKE_MAGIC; | |
1426 | } | |
1427 | ||
1428 | static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) | |
1429 | { | |
1430 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1431 | if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY)) | |
1432 | return -EINVAL; | |
1433 | spin_lock_irq(&lp->lock); | |
1434 | if (wol_info->wolopts & WAKE_MAGIC) | |
6aa20a22 | 1435 | lp->options |= |
1da177e4 LT |
1436 | (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE); |
1437 | else if(wol_info->wolopts & WAKE_PHY) | |
6aa20a22 | 1438 | lp->options |= |
1da177e4 LT |
1439 | (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE); |
1440 | else | |
6aa20a22 | 1441 | lp->options &= ~OPTION_WOL_ENABLE; |
1da177e4 LT |
1442 | spin_unlock_irq(&lp->lock); |
1443 | return 0; | |
1444 | } | |
1445 | ||
7282d491 | 1446 | static const struct ethtool_ops ops = { |
1da177e4 LT |
1447 | .get_drvinfo = amd8111e_get_drvinfo, |
1448 | .get_regs_len = amd8111e_get_regs_len, | |
1449 | .get_regs = amd8111e_get_regs, | |
1da177e4 LT |
1450 | .nway_reset = amd8111e_nway_reset, |
1451 | .get_link = amd8111e_get_link, | |
1452 | .get_wol = amd8111e_get_wol, | |
1453 | .set_wol = amd8111e_set_wol, | |
1435003c PR |
1454 | .get_link_ksettings = amd8111e_get_link_ksettings, |
1455 | .set_link_ksettings = amd8111e_set_link_ksettings, | |
1da177e4 LT |
1456 | }; |
1457 | ||
13a4fa43 VB |
1458 | /* This function handles all the ethtool ioctls. It gives driver info, |
1459 | * gets/sets driver speed, gets memory mapped register values, forces | |
1460 | * auto negotiation, sets/gets WOL options for ethtool application. | |
1461 | */ | |
46c73ecc | 1462 | static int amd8111e_ioctl(struct net_device *dev , struct ifreq *ifr, int cmd) |
1da177e4 LT |
1463 | { |
1464 | struct mii_ioctl_data *data = if_mii(ifr); | |
1465 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1466 | int err; | |
1467 | u32 mii_regval; | |
1468 | ||
1da177e4 LT |
1469 | switch(cmd) { |
1470 | case SIOCGMIIPHY: | |
1471 | data->phy_id = lp->ext_phy_addr; | |
1472 | ||
1473 | /* fallthru */ | |
6aa20a22 | 1474 | case SIOCGMIIREG: |
1da177e4 LT |
1475 | |
1476 | spin_lock_irq(&lp->lock); | |
1477 | err = amd8111e_read_phy(lp, data->phy_id, | |
1478 | data->reg_num & PHY_REG_ADDR_MASK, &mii_regval); | |
1479 | spin_unlock_irq(&lp->lock); | |
1480 | ||
1481 | data->val_out = mii_regval; | |
1482 | return err; | |
1483 | ||
1484 | case SIOCSMIIREG: | |
1485 | ||
1486 | spin_lock_irq(&lp->lock); | |
1487 | err = amd8111e_write_phy(lp, data->phy_id, | |
1488 | data->reg_num & PHY_REG_ADDR_MASK, data->val_in); | |
1489 | spin_unlock_irq(&lp->lock); | |
1490 | ||
1491 | return err; | |
1492 | ||
1493 | default: | |
1494 | /* do nothing */ | |
1495 | break; | |
1496 | } | |
1497 | return -EOPNOTSUPP; | |
1498 | } | |
1499 | static int amd8111e_set_mac_address(struct net_device *dev, void *p) | |
1500 | { | |
1501 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1502 | int i; | |
1503 | struct sockaddr *addr = p; | |
1504 | ||
1505 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1506 | spin_lock_irq(&lp->lock); | |
1507 | /* Setting the MAC address to the device */ | |
c857ff6e | 1508 | for (i = 0; i < ETH_ALEN; i++) |
6aa20a22 JG |
1509 | writeb( dev->dev_addr[i], lp->mmio + PADR + i ); |
1510 | ||
1da177e4 LT |
1511 | spin_unlock_irq(&lp->lock); |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
13a4fa43 VB |
1516 | /* This function changes the mtu of the device. It restarts the device to |
1517 | * initialize the descriptor with new receive buffers. | |
1518 | */ | |
1da177e4 LT |
1519 | static int amd8111e_change_mtu(struct net_device *dev, int new_mtu) |
1520 | { | |
1521 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1522 | int err; | |
1523 | ||
1da177e4 LT |
1524 | if (!netif_running(dev)) { |
1525 | /* new_mtu will be used | |
13a4fa43 VB |
1526 | * when device starts netxt time |
1527 | */ | |
1da177e4 LT |
1528 | dev->mtu = new_mtu; |
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | spin_lock_irq(&lp->lock); | |
1533 | ||
1534 | /* stop the chip */ | |
1535 | writel(RUN, lp->mmio + CMD0); | |
1536 | ||
1537 | dev->mtu = new_mtu; | |
1538 | ||
1539 | err = amd8111e_restart(dev); | |
1540 | spin_unlock_irq(&lp->lock); | |
1541 | if(!err) | |
1542 | netif_start_queue(dev); | |
1543 | return err; | |
1544 | } | |
1545 | ||
46c73ecc | 1546 | static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp) |
1da177e4 LT |
1547 | { |
1548 | writel( VAL1|MPPLBA, lp->mmio + CMD3); | |
1549 | writel( VAL0|MPEN_SW, lp->mmio + CMD7); | |
1550 | ||
1551 | /* To eliminate PCI posting bug */ | |
1552 | readl(lp->mmio + CMD7); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
46c73ecc | 1556 | static int amd8111e_enable_link_change(struct amd8111e_priv *lp) |
1da177e4 LT |
1557 | { |
1558 | ||
1559 | /* Adapter is already stoped/suspended/interrupt-disabled */ | |
1560 | writel(VAL0|LCMODE_SW,lp->mmio + CMD7); | |
6aa20a22 | 1561 | |
1da177e4 LT |
1562 | /* To eliminate PCI posting bug */ |
1563 | readl(lp->mmio + CMD7); | |
1564 | return 0; | |
6aa20a22 | 1565 | } |
1da177e4 | 1566 | |
13a4fa43 | 1567 | /* This function is called when a packet transmission fails to complete |
af901ca1 AGR |
1568 | * within a reasonable period, on the assumption that an interrupt have |
1569 | * failed or the interface is locked up. This function will reinitialize | |
1570 | * the hardware. | |
1571 | */ | |
1da177e4 LT |
1572 | static void amd8111e_tx_timeout(struct net_device *dev) |
1573 | { | |
46c73ecc | 1574 | struct amd8111e_priv *lp = netdev_priv(dev); |
1da177e4 LT |
1575 | int err; |
1576 | ||
f7afbaa5 VB |
1577 | netdev_err(dev, "transmit timed out, resetting\n"); |
1578 | ||
1da177e4 LT |
1579 | spin_lock_irq(&lp->lock); |
1580 | err = amd8111e_restart(dev); | |
1581 | spin_unlock_irq(&lp->lock); | |
1582 | if(!err) | |
1583 | netif_wake_queue(dev); | |
1584 | } | |
1585 | static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state) | |
6aa20a22 | 1586 | { |
1da177e4 LT |
1587 | struct net_device *dev = pci_get_drvdata(pci_dev); |
1588 | struct amd8111e_priv *lp = netdev_priv(dev); | |
6aa20a22 | 1589 | |
1da177e4 LT |
1590 | if (!netif_running(dev)) |
1591 | return 0; | |
1592 | ||
1593 | /* disable the interrupt */ | |
1594 | spin_lock_irq(&lp->lock); | |
1595 | amd8111e_disable_interrupt(lp); | |
1596 | spin_unlock_irq(&lp->lock); | |
1597 | ||
1598 | netif_device_detach(dev); | |
6aa20a22 | 1599 | |
1da177e4 LT |
1600 | /* stop chip */ |
1601 | spin_lock_irq(&lp->lock); | |
6aa20a22 | 1602 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
1da177e4 LT |
1603 | del_timer_sync(&lp->ipg_data.ipg_timer); |
1604 | amd8111e_stop_chip(lp); | |
1605 | spin_unlock_irq(&lp->lock); | |
1606 | ||
1607 | if(lp->options & OPTION_WOL_ENABLE){ | |
1608 | /* enable wol */ | |
1609 | if(lp->options & OPTION_WAKE_MAGIC_ENABLE) | |
6aa20a22 | 1610 | amd8111e_enable_magicpkt(lp); |
1da177e4 | 1611 | if(lp->options & OPTION_WAKE_PHY_ENABLE) |
6aa20a22 JG |
1612 | amd8111e_enable_link_change(lp); |
1613 | ||
1da177e4 LT |
1614 | pci_enable_wake(pci_dev, PCI_D3hot, 1); |
1615 | pci_enable_wake(pci_dev, PCI_D3cold, 1); | |
1616 | ||
1617 | } | |
6aa20a22 | 1618 | else{ |
1da177e4 LT |
1619 | pci_enable_wake(pci_dev, PCI_D3hot, 0); |
1620 | pci_enable_wake(pci_dev, PCI_D3cold, 0); | |
1621 | } | |
6aa20a22 | 1622 | |
1da177e4 LT |
1623 | pci_save_state(pci_dev); |
1624 | pci_set_power_state(pci_dev, PCI_D3hot); | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | static int amd8111e_resume(struct pci_dev *pci_dev) | |
1629 | { | |
1630 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
1631 | struct amd8111e_priv *lp = netdev_priv(dev); | |
6aa20a22 | 1632 | |
1da177e4 LT |
1633 | if (!netif_running(dev)) |
1634 | return 0; | |
1635 | ||
1636 | pci_set_power_state(pci_dev, PCI_D0); | |
1637 | pci_restore_state(pci_dev); | |
1638 | ||
1639 | pci_enable_wake(pci_dev, PCI_D3hot, 0); | |
1640 | pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */ | |
1641 | ||
1642 | netif_device_attach(dev); | |
1643 | ||
1644 | spin_lock_irq(&lp->lock); | |
1645 | amd8111e_restart(dev); | |
1646 | /* Restart ipg timer */ | |
6aa20a22 JG |
1647 | if(lp->options & OPTION_DYN_IPG_ENABLE) |
1648 | mod_timer(&lp->ipg_data.ipg_timer, | |
1da177e4 LT |
1649 | jiffies + IPG_CONVERGE_JIFFIES); |
1650 | spin_unlock_irq(&lp->lock); | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
495ad986 | 1655 | static void amd8111e_config_ipg(struct timer_list *t) |
1da177e4 | 1656 | { |
495ad986 | 1657 | struct amd8111e_priv *lp = from_timer(lp, t, ipg_data.ipg_timer); |
46c73ecc | 1658 | struct ipg_info *ipg_data = &lp->ipg_data; |
1da177e4 LT |
1659 | void __iomem *mmio = lp->mmio; |
1660 | unsigned int prev_col_cnt = ipg_data->col_cnt; | |
1661 | unsigned int total_col_cnt; | |
1662 | unsigned int tmp_ipg; | |
6aa20a22 | 1663 | |
1da177e4 LT |
1664 | if(lp->link_config.duplex == DUPLEX_FULL){ |
1665 | ipg_data->ipg = DEFAULT_IPG; | |
1666 | return; | |
1667 | } | |
1668 | ||
1669 | if(ipg_data->ipg_state == SSTATE){ | |
6aa20a22 | 1670 | |
1da177e4 | 1671 | if(ipg_data->timer_tick == IPG_STABLE_TIME){ |
6aa20a22 | 1672 | |
1da177e4 LT |
1673 | ipg_data->timer_tick = 0; |
1674 | ipg_data->ipg = MIN_IPG - IPG_STEP; | |
1675 | ipg_data->current_ipg = MIN_IPG; | |
1676 | ipg_data->diff_col_cnt = 0xFFFFFFFF; | |
1677 | ipg_data->ipg_state = CSTATE; | |
1678 | } | |
1679 | else | |
1680 | ipg_data->timer_tick++; | |
1681 | } | |
1682 | ||
1683 | if(ipg_data->ipg_state == CSTATE){ | |
6aa20a22 | 1684 | |
1da177e4 LT |
1685 | /* Get the current collision count */ |
1686 | ||
6aa20a22 | 1687 | total_col_cnt = ipg_data->col_cnt = |
1da177e4 LT |
1688 | amd8111e_read_mib(mmio, xmt_collisions); |
1689 | ||
6aa20a22 | 1690 | if ((total_col_cnt - prev_col_cnt) < |
1da177e4 | 1691 | (ipg_data->diff_col_cnt)){ |
6aa20a22 | 1692 | |
1da177e4 LT |
1693 | ipg_data->diff_col_cnt = |
1694 | total_col_cnt - prev_col_cnt ; | |
1695 | ||
1696 | ipg_data->ipg = ipg_data->current_ipg; | |
1697 | } | |
1698 | ||
1699 | ipg_data->current_ipg += IPG_STEP; | |
1700 | ||
1701 | if (ipg_data->current_ipg <= MAX_IPG) | |
1702 | tmp_ipg = ipg_data->current_ipg; | |
1703 | else{ | |
1704 | tmp_ipg = ipg_data->ipg; | |
1705 | ipg_data->ipg_state = SSTATE; | |
1706 | } | |
6aa20a22 JG |
1707 | writew((u32)tmp_ipg, mmio + IPG); |
1708 | writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1); | |
1da177e4 | 1709 | } |
843ef94e | 1710 | mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES); |
1da177e4 LT |
1711 | return; |
1712 | ||
1713 | } | |
1714 | ||
0cb0568d | 1715 | static void amd8111e_probe_ext_phy(struct net_device *dev) |
1da177e4 LT |
1716 | { |
1717 | struct amd8111e_priv *lp = netdev_priv(dev); | |
1718 | int i; | |
1719 | ||
1720 | for (i = 0x1e; i >= 0; i--) { | |
1721 | u32 id1, id2; | |
1722 | ||
1723 | if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1)) | |
1724 | continue; | |
1725 | if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2)) | |
1726 | continue; | |
1727 | lp->ext_phy_id = (id1 << 16) | id2; | |
1728 | lp->ext_phy_addr = i; | |
1729 | return; | |
1730 | } | |
1731 | lp->ext_phy_id = 0; | |
1732 | lp->ext_phy_addr = 1; | |
1733 | } | |
1734 | ||
887e53d2 SH |
1735 | static const struct net_device_ops amd8111e_netdev_ops = { |
1736 | .ndo_open = amd8111e_open, | |
1737 | .ndo_stop = amd8111e_close, | |
1738 | .ndo_start_xmit = amd8111e_start_xmit, | |
1739 | .ndo_tx_timeout = amd8111e_tx_timeout, | |
1740 | .ndo_get_stats = amd8111e_get_stats, | |
afc4b13d | 1741 | .ndo_set_rx_mode = amd8111e_set_multicast_list, |
887e53d2 SH |
1742 | .ndo_validate_addr = eth_validate_addr, |
1743 | .ndo_set_mac_address = amd8111e_set_mac_address, | |
1744 | .ndo_do_ioctl = amd8111e_ioctl, | |
1745 | .ndo_change_mtu = amd8111e_change_mtu, | |
887e53d2 SH |
1746 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1747 | .ndo_poll_controller = amd8111e_poll, | |
1748 | #endif | |
1749 | }; | |
1750 | ||
0cb0568d | 1751 | static int amd8111e_probe_one(struct pci_dev *pdev, |
1da177e4 LT |
1752 | const struct pci_device_id *ent) |
1753 | { | |
f9c7da5e | 1754 | int err, i; |
1da177e4 | 1755 | unsigned long reg_addr,reg_len; |
46c73ecc VB |
1756 | struct amd8111e_priv *lp; |
1757 | struct net_device *dev; | |
1da177e4 LT |
1758 | |
1759 | err = pci_enable_device(pdev); | |
1760 | if(err){ | |
f7afbaa5 | 1761 | dev_err(&pdev->dev, "Cannot enable new PCI device\n"); |
1da177e4 LT |
1762 | return err; |
1763 | } | |
1764 | ||
1765 | if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){ | |
f7afbaa5 | 1766 | dev_err(&pdev->dev, "Cannot find PCI base address\n"); |
1da177e4 LT |
1767 | err = -ENODEV; |
1768 | goto err_disable_pdev; | |
1769 | } | |
1770 | ||
1771 | err = pci_request_regions(pdev, MODULE_NAME); | |
1772 | if(err){ | |
f7afbaa5 | 1773 | dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); |
1da177e4 LT |
1774 | goto err_disable_pdev; |
1775 | } | |
1776 | ||
1777 | pci_set_master(pdev); | |
1778 | ||
1779 | /* Find power-management capability. */ | |
f9c7da5e | 1780 | if (!pdev->pm_cap) { |
f7afbaa5 | 1781 | dev_err(&pdev->dev, "No Power Management capability\n"); |
86e506e3 | 1782 | err = -ENODEV; |
1da177e4 LT |
1783 | goto err_free_reg; |
1784 | } | |
1785 | ||
1786 | /* Initialize DMA */ | |
284901a9 | 1787 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) { |
f7afbaa5 | 1788 | dev_err(&pdev->dev, "DMA not supported\n"); |
86e506e3 | 1789 | err = -ENODEV; |
cac8c81a TK |
1790 | goto err_free_reg; |
1791 | } | |
6aa20a22 | 1792 | |
1da177e4 LT |
1793 | reg_addr = pci_resource_start(pdev, 0); |
1794 | reg_len = pci_resource_len(pdev, 0); | |
1795 | ||
1796 | dev = alloc_etherdev(sizeof(struct amd8111e_priv)); | |
1797 | if (!dev) { | |
1da177e4 LT |
1798 | err = -ENOMEM; |
1799 | goto err_free_reg; | |
1800 | } | |
1801 | ||
1da177e4 LT |
1802 | SET_NETDEV_DEV(dev, &pdev->dev); |
1803 | ||
1804 | #if AMD8111E_VLAN_TAG_USED | |
f646968f | 1805 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX ; |
6aa20a22 JG |
1806 | #endif |
1807 | ||
1da177e4 LT |
1808 | lp = netdev_priv(dev); |
1809 | lp->pci_dev = pdev; | |
1810 | lp->amd8111e_net_dev = dev; | |
f9c7da5e | 1811 | lp->pm_cap = pdev->pm_cap; |
1da177e4 LT |
1812 | |
1813 | spin_lock_init(&lp->lock); | |
1814 | ||
711fec5d | 1815 | lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len); |
ee41a82f | 1816 | if (!lp->mmio) { |
f7afbaa5 | 1817 | dev_err(&pdev->dev, "Cannot map device registers\n"); |
1da177e4 LT |
1818 | err = -ENOMEM; |
1819 | goto err_free_dev; | |
1820 | } | |
6aa20a22 | 1821 | |
1da177e4 | 1822 | /* Initializing MAC address */ |
c857ff6e | 1823 | for (i = 0; i < ETH_ALEN; i++) |
0795af57 | 1824 | dev->dev_addr[i] = readb(lp->mmio + PADR + i); |
6aa20a22 | 1825 | |
1da177e4 LT |
1826 | /* Setting user defined parametrs */ |
1827 | lp->ext_phy_option = speed_duplex[card_idx]; | |
1828 | if(coalesce[card_idx]) | |
6aa20a22 | 1829 | lp->options |= OPTION_INTR_COAL_ENABLE; |
1da177e4 | 1830 | if(dynamic_ipg[card_idx++]) |
6aa20a22 | 1831 | lp->options |= OPTION_DYN_IPG_ENABLE; |
1da177e4 | 1832 | |
887e53d2 | 1833 | |
1da177e4 | 1834 | /* Initialize driver entry points */ |
887e53d2 | 1835 | dev->netdev_ops = &amd8111e_netdev_ops; |
7ad24ea4 | 1836 | dev->ethtool_ops = &ops; |
1da177e4 | 1837 | dev->irq =pdev->irq; |
6aa20a22 | 1838 | dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; |
44770e11 JW |
1839 | dev->min_mtu = AMD8111E_MIN_MTU; |
1840 | dev->max_mtu = AMD8111E_MAX_MTU; | |
bea3348e | 1841 | netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); |
1da177e4 LT |
1842 | |
1843 | #if AMD8111E_VLAN_TAG_USED | |
f646968f | 1844 | dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
6aa20a22 | 1845 | #endif |
1da177e4 LT |
1846 | /* Probe the external PHY */ |
1847 | amd8111e_probe_ext_phy(dev); | |
1848 | ||
1849 | /* setting mii default values */ | |
1850 | lp->mii_if.dev = dev; | |
1851 | lp->mii_if.mdio_read = amd8111e_mdio_read; | |
1852 | lp->mii_if.mdio_write = amd8111e_mdio_write; | |
1853 | lp->mii_if.phy_id = lp->ext_phy_addr; | |
1854 | ||
1855 | /* Set receive buffer length and set jumbo option*/ | |
1856 | amd8111e_set_rx_buff_len(dev); | |
1857 | ||
1858 | ||
1859 | err = register_netdev(dev); | |
1860 | if (err) { | |
f7afbaa5 | 1861 | dev_err(&pdev->dev, "Cannot register net device\n"); |
711fec5d | 1862 | goto err_free_dev; |
1da177e4 LT |
1863 | } |
1864 | ||
1865 | pci_set_drvdata(pdev, dev); | |
6aa20a22 | 1866 | |
1da177e4 | 1867 | /* Initialize software ipg timer */ |
6aa20a22 | 1868 | if(lp->options & OPTION_DYN_IPG_ENABLE){ |
495ad986 | 1869 | timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0); |
6aa20a22 | 1870 | lp->ipg_data.ipg_timer.expires = jiffies + |
1da177e4 LT |
1871 | IPG_CONVERGE_JIFFIES; |
1872 | lp->ipg_data.ipg = DEFAULT_IPG; | |
1873 | lp->ipg_data.ipg_state = CSTATE; | |
6403eab1 | 1874 | } |
1da177e4 LT |
1875 | |
1876 | /* display driver and device information */ | |
1da177e4 | 1877 | chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28; |
f7afbaa5 VB |
1878 | dev_info(&pdev->dev, "AMD-8111e Driver Version: %s\n", MODULE_VERS); |
1879 | dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n", | |
1880 | chip_version, dev->dev_addr); | |
1da177e4 | 1881 | if (lp->ext_phy_id) |
f7afbaa5 VB |
1882 | dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n", |
1883 | lp->ext_phy_id, lp->ext_phy_addr); | |
1da177e4 | 1884 | else |
f7afbaa5 VB |
1885 | dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n"); |
1886 | ||
1da177e4 | 1887 | return 0; |
1da177e4 LT |
1888 | |
1889 | err_free_dev: | |
1890 | free_netdev(dev); | |
1891 | ||
1892 | err_free_reg: | |
1893 | pci_release_regions(pdev); | |
1894 | ||
1895 | err_disable_pdev: | |
1896 | pci_disable_device(pdev); | |
1da177e4 LT |
1897 | return err; |
1898 | ||
1899 | } | |
1900 | ||
43519e60 VB |
1901 | static void amd8111e_remove_one(struct pci_dev *pdev) |
1902 | { | |
1903 | struct net_device *dev = pci_get_drvdata(pdev); | |
1904 | ||
1905 | if (dev) { | |
1906 | unregister_netdev(dev); | |
43519e60 VB |
1907 | free_netdev(dev); |
1908 | pci_release_regions(pdev); | |
1909 | pci_disable_device(pdev); | |
1910 | } | |
1911 | } | |
1912 | ||
ba69a3d7 VB |
1913 | static const struct pci_device_id amd8111e_pci_tbl[] = { |
1914 | { | |
1915 | .vendor = PCI_VENDOR_ID_AMD, | |
1916 | .device = PCI_DEVICE_ID_AMD8111E_7462, | |
1917 | }, | |
1918 | { | |
1919 | .vendor = 0, | |
1920 | } | |
1921 | }; | |
1922 | MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl); | |
1923 | ||
1da177e4 LT |
1924 | static struct pci_driver amd8111e_driver = { |
1925 | .name = MODULE_NAME, | |
1926 | .id_table = amd8111e_pci_tbl, | |
1927 | .probe = amd8111e_probe_one, | |
0cb0568d | 1928 | .remove = amd8111e_remove_one, |
1da177e4 LT |
1929 | .suspend = amd8111e_suspend, |
1930 | .resume = amd8111e_resume | |
1931 | }; | |
1932 | ||
a46e6ccd | 1933 | module_pci_driver(amd8111e_driver); |