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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 | 15 | * Author: MontaVista Software, Inc. |
ec7eabdd | 16 | * ppopov@mvista.com or source@mvista.com |
1da177e4 LT |
17 | * |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
0ab75ae8 | 30 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
31 | * |
32 | * ######################################################################## | |
33 | * | |
6aa20a22 | 34 | * |
1da177e4 | 35 | */ |
215e17be FF |
36 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
37 | ||
bc36b428 | 38 | #include <linux/capability.h> |
d791c2bd | 39 | #include <linux/dma-mapping.h> |
1da177e4 LT |
40 | #include <linux/module.h> |
41 | #include <linux/kernel.h> | |
1da177e4 LT |
42 | #include <linux/string.h> |
43 | #include <linux/timer.h> | |
44 | #include <linux/errno.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/bitops.h> | |
48 | #include <linux/slab.h> | |
49 | #include <linux/interrupt.h> | |
1da177e4 LT |
50 | #include <linux/netdevice.h> |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
bd2302c2 | 58 | #include <linux/platform_device.h> |
49a42c08 FF |
59 | #include <linux/cpu.h> |
60 | #include <linux/io.h> | |
25b31cb1 | 61 | |
1da177e4 LT |
62 | #include <asm/mipsregs.h> |
63 | #include <asm/irq.h> | |
1da177e4 LT |
64 | #include <asm/processor.h> |
65 | ||
25b31cb1 | 66 | #include <au1000.h> |
bd2302c2 | 67 | #include <au1xxx_eth.h> |
25b31cb1 YY |
68 | #include <prom.h> |
69 | ||
1da177e4 LT |
70 | #include "au1000_eth.h" |
71 | ||
72 | #ifdef AU1000_ETH_DEBUG | |
73 | static int au1000_debug = 5; | |
74 | #else | |
75 | static int au1000_debug = 3; | |
76 | #endif | |
77 | ||
7cd2e6e3 FF |
78 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK) | |
81 | ||
89be0501 | 82 | #define DRV_NAME "au1000_eth" |
8020eb82 | 83 | #define DRV_VERSION "1.7" |
1da177e4 LT |
84 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
85 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
86 | ||
87 | MODULE_AUTHOR(DRV_AUTHOR); | |
88 | MODULE_DESCRIPTION(DRV_DESC); | |
89 | MODULE_LICENSE("GPL"); | |
13130c7a | 90 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 91 | |
fb1a7602 ML |
92 | /* AU1000 MAC registers and bits */ |
93 | #define MAC_CONTROL 0x0 | |
94 | # define MAC_RX_ENABLE (1 << 2) | |
95 | # define MAC_TX_ENABLE (1 << 3) | |
96 | # define MAC_DEF_CHECK (1 << 5) | |
97 | # define MAC_SET_BL(X) (((X) & 0x3) << 6) | |
98 | # define MAC_AUTO_PAD (1 << 8) | |
99 | # define MAC_DISABLE_RETRY (1 << 10) | |
100 | # define MAC_DISABLE_BCAST (1 << 11) | |
101 | # define MAC_LATE_COL (1 << 12) | |
102 | # define MAC_HASH_MODE (1 << 13) | |
103 | # define MAC_HASH_ONLY (1 << 15) | |
104 | # define MAC_PASS_ALL (1 << 16) | |
105 | # define MAC_INVERSE_FILTER (1 << 17) | |
106 | # define MAC_PROMISCUOUS (1 << 18) | |
107 | # define MAC_PASS_ALL_MULTI (1 << 19) | |
108 | # define MAC_FULL_DUPLEX (1 << 20) | |
109 | # define MAC_NORMAL_MODE 0 | |
110 | # define MAC_INT_LOOPBACK (1 << 21) | |
111 | # define MAC_EXT_LOOPBACK (1 << 22) | |
112 | # define MAC_DISABLE_RX_OWN (1 << 23) | |
113 | # define MAC_BIG_ENDIAN (1 << 30) | |
114 | # define MAC_RX_ALL (1 << 31) | |
115 | #define MAC_ADDRESS_HIGH 0x4 | |
116 | #define MAC_ADDRESS_LOW 0x8 | |
117 | #define MAC_MCAST_HIGH 0xC | |
118 | #define MAC_MCAST_LOW 0x10 | |
119 | #define MAC_MII_CNTRL 0x14 | |
120 | # define MAC_MII_BUSY (1 << 0) | |
121 | # define MAC_MII_READ 0 | |
122 | # define MAC_MII_WRITE (1 << 1) | |
123 | # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) | |
124 | # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) | |
125 | #define MAC_MII_DATA 0x18 | |
126 | #define MAC_FLOW_CNTRL 0x1C | |
127 | # define MAC_FLOW_CNTRL_BUSY (1 << 0) | |
128 | # define MAC_FLOW_CNTRL_ENABLE (1 << 1) | |
129 | # define MAC_PASS_CONTROL (1 << 2) | |
130 | # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) | |
131 | #define MAC_VLAN1_TAG 0x20 | |
132 | #define MAC_VLAN2_TAG 0x24 | |
133 | ||
134 | /* Ethernet Controller Enable */ | |
135 | # define MAC_EN_CLOCK_ENABLE (1 << 0) | |
136 | # define MAC_EN_RESET0 (1 << 1) | |
137 | # define MAC_EN_TOSS (0 << 2) | |
138 | # define MAC_EN_CACHEABLE (1 << 3) | |
139 | # define MAC_EN_RESET1 (1 << 4) | |
140 | # define MAC_EN_RESET2 (1 << 5) | |
141 | # define MAC_DMA_RESET (1 << 6) | |
142 | ||
143 | /* Ethernet Controller DMA Channels */ | |
144 | /* offsets from MAC_TX_RING_ADDR address */ | |
145 | #define MAC_TX_BUFF0_STATUS 0x0 | |
146 | # define TX_FRAME_ABORTED (1 << 0) | |
147 | # define TX_JAB_TIMEOUT (1 << 1) | |
148 | # define TX_NO_CARRIER (1 << 2) | |
149 | # define TX_LOSS_CARRIER (1 << 3) | |
150 | # define TX_EXC_DEF (1 << 4) | |
151 | # define TX_LATE_COLL_ABORT (1 << 5) | |
152 | # define TX_EXC_COLL (1 << 6) | |
153 | # define TX_UNDERRUN (1 << 7) | |
154 | # define TX_DEFERRED (1 << 8) | |
155 | # define TX_LATE_COLL (1 << 9) | |
156 | # define TX_COLL_CNT_MASK (0xF << 10) | |
157 | # define TX_PKT_RETRY (1 << 31) | |
158 | #define MAC_TX_BUFF0_ADDR 0x4 | |
159 | # define TX_DMA_ENABLE (1 << 0) | |
160 | # define TX_T_DONE (1 << 1) | |
161 | # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
162 | #define MAC_TX_BUFF0_LEN 0x8 | |
163 | #define MAC_TX_BUFF1_STATUS 0x10 | |
164 | #define MAC_TX_BUFF1_ADDR 0x14 | |
165 | #define MAC_TX_BUFF1_LEN 0x18 | |
166 | #define MAC_TX_BUFF2_STATUS 0x20 | |
167 | #define MAC_TX_BUFF2_ADDR 0x24 | |
168 | #define MAC_TX_BUFF2_LEN 0x28 | |
169 | #define MAC_TX_BUFF3_STATUS 0x30 | |
170 | #define MAC_TX_BUFF3_ADDR 0x34 | |
171 | #define MAC_TX_BUFF3_LEN 0x38 | |
172 | ||
173 | /* offsets from MAC_RX_RING_ADDR */ | |
174 | #define MAC_RX_BUFF0_STATUS 0x0 | |
175 | # define RX_FRAME_LEN_MASK 0x3fff | |
176 | # define RX_WDOG_TIMER (1 << 14) | |
177 | # define RX_RUNT (1 << 15) | |
178 | # define RX_OVERLEN (1 << 16) | |
179 | # define RX_COLL (1 << 17) | |
180 | # define RX_ETHER (1 << 18) | |
181 | # define RX_MII_ERROR (1 << 19) | |
182 | # define RX_DRIBBLING (1 << 20) | |
183 | # define RX_CRC_ERROR (1 << 21) | |
184 | # define RX_VLAN1 (1 << 22) | |
185 | # define RX_VLAN2 (1 << 23) | |
186 | # define RX_LEN_ERROR (1 << 24) | |
187 | # define RX_CNTRL_FRAME (1 << 25) | |
188 | # define RX_U_CNTRL_FRAME (1 << 26) | |
189 | # define RX_MCAST_FRAME (1 << 27) | |
190 | # define RX_BCAST_FRAME (1 << 28) | |
191 | # define RX_FILTER_FAIL (1 << 29) | |
192 | # define RX_PACKET_FILTER (1 << 30) | |
193 | # define RX_MISSED_FRAME (1 << 31) | |
194 | ||
195 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
196 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | |
197 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
198 | #define MAC_RX_BUFF0_ADDR 0x4 | |
199 | # define RX_DMA_ENABLE (1 << 0) | |
200 | # define RX_T_DONE (1 << 1) | |
201 | # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
202 | # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) | |
203 | #define MAC_RX_BUFF1_STATUS 0x10 | |
204 | #define MAC_RX_BUFF1_ADDR 0x14 | |
205 | #define MAC_RX_BUFF2_STATUS 0x20 | |
206 | #define MAC_RX_BUFF2_ADDR 0x24 | |
207 | #define MAC_RX_BUFF3_STATUS 0x30 | |
208 | #define MAC_RX_BUFF3_ADDR 0x34 | |
209 | ||
1da177e4 LT |
210 | /* |
211 | * Theory of operation | |
212 | * | |
6aa20a22 JG |
213 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
214 | * There are four receive and four transmit descriptors. These | |
215 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
216 | * hardware registers. |
217 | * | |
218 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 219 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
220 | * hardware registers, however, are still mapped at KSEG1 to |
221 | * make sure there's no out-of-order writes, and that all writes | |
222 | * complete immediately. | |
223 | */ | |
224 | ||
0638dec0 HVR |
225 | /* |
226 | * board-specific configurations | |
227 | * | |
228 | * PHY detection algorithm | |
229 | * | |
bd2302c2 | 230 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
231 | * autodetected: |
232 | * | |
233 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 234 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
235 | * defined) PHY address not already claimed by another netdev. |
236 | * | |
237 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 238 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
239 | * the first MII bus is searched as well for an unclaimed PHY; this is |
240 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
241 | * bus. | |
242 | * | |
243 | * Finally, if no PHY is found, then the corresponding ethernet | |
244 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
245 | */ |
246 | ||
bd2302c2 | 247 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 248 | |
0638dec0 HVR |
249 | /* static PHY setup |
250 | * | |
251 | * most boards PHY setup should be detectable properly with the | |
252 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
253 | * you have a switch attached, or want to use the PHY's interrupt | |
254 | * notification capabilities) you can provide a static PHY | |
255 | * configuration here | |
256 | * | |
257 | * IRQs may only be set, if a PHY address was configured | |
258 | * If a PHY address is given, also a bus id is required to be set | |
259 | * | |
260 | * ps: make sure the used irqs are configured properly in the board | |
261 | * specific irq-map | |
262 | */ | |
1da177e4 | 263 | |
eb049630 | 264 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
265 | { |
266 | unsigned long flags; | |
267 | struct au1000_private *aup = netdev_priv(dev); | |
268 | ||
269 | spin_lock_irqsave(&aup->lock, flags); | |
270 | ||
ec7eabdd | 271 | if (force_reset || (!aup->mac_enabled)) { |
462ca99c | 272 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
2f73bfbe ML |
273 | wmb(); /* drain writebuffer */ |
274 | mdelay(2); | |
d0e7cb5d | 275 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
462ca99c | 276 | | MAC_EN_CLOCK_ENABLE), aup->enable); |
2f73bfbe ML |
277 | wmb(); /* drain writebuffer */ |
278 | mdelay(2); | |
5ef3041e FF |
279 | |
280 | aup->mac_enabled = 1; | |
281 | } | |
282 | ||
283 | spin_unlock_irqrestore(&aup->lock, flags); | |
284 | } | |
285 | ||
0638dec0 HVR |
286 | /* |
287 | * MII operations | |
288 | */ | |
1210dde7 | 289 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 290 | { |
454d7c9b | 291 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
292 | u32 *const mii_control_reg = &aup->mac->mii_control; |
293 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
294 | u32 timedout = 20; |
295 | u32 mii_control; | |
296 | ||
d0e7cb5d | 297 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
298 | mdelay(1); |
299 | if (--timedout == 0) { | |
5368c726 | 300 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
301 | return -1; |
302 | } | |
303 | } | |
304 | ||
6aa20a22 | 305 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 306 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 | 307 | |
d0e7cb5d | 308 | writel(mii_control, mii_control_reg); |
1da177e4 LT |
309 | |
310 | timedout = 20; | |
d0e7cb5d | 311 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
312 | mdelay(1); |
313 | if (--timedout == 0) { | |
5368c726 | 314 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
315 | return -1; |
316 | } | |
317 | } | |
d0e7cb5d | 318 | return readl(mii_data_reg); |
1da177e4 LT |
319 | } |
320 | ||
1210dde7 AB |
321 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
322 | int reg, u16 value) | |
1da177e4 | 323 | { |
454d7c9b | 324 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
325 | u32 *const mii_control_reg = &aup->mac->mii_control; |
326 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
327 | u32 timedout = 20; |
328 | u32 mii_control; | |
329 | ||
d0e7cb5d | 330 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
331 | mdelay(1); |
332 | if (--timedout == 0) { | |
5368c726 | 333 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
334 | return; |
335 | } | |
336 | } | |
337 | ||
6aa20a22 | 338 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 339 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 | 340 | |
d0e7cb5d FF |
341 | writel(value, mii_data_reg); |
342 | writel(mii_control, mii_control_reg); | |
1da177e4 LT |
343 | } |
344 | ||
1210dde7 | 345 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
346 | { |
347 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
dc99839c FF |
348 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) |
349 | */ | |
0638dec0 HVR |
350 | struct net_device *const dev = bus->priv; |
351 | ||
dc99839c FF |
352 | /* make sure the MAC associated with this |
353 | * mii_bus is enabled | |
354 | */ | |
355 | au1000_enable_mac(dev, 0); | |
356 | ||
1210dde7 | 357 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 358 | } |
1da177e4 | 359 | |
1210dde7 AB |
360 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
361 | u16 value) | |
1da177e4 | 362 | { |
0638dec0 | 363 | struct net_device *const dev = bus->priv; |
1da177e4 | 364 | |
dc99839c FF |
365 | /* make sure the MAC associated with this |
366 | * mii_bus is enabled | |
367 | */ | |
368 | au1000_enable_mac(dev, 0); | |
369 | ||
1210dde7 | 370 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 371 | return 0; |
1da177e4 LT |
372 | } |
373 | ||
1210dde7 | 374 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 375 | { |
0638dec0 | 376 | struct net_device *const dev = bus->priv; |
1da177e4 | 377 | |
dc99839c FF |
378 | /* make sure the MAC associated with this |
379 | * mii_bus is enabled | |
380 | */ | |
381 | au1000_enable_mac(dev, 0); | |
382 | ||
0638dec0 HVR |
383 | return 0; |
384 | } | |
1da177e4 | 385 | |
eb049630 | 386 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
387 | { |
388 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 389 | u32 reg; |
5ef3041e | 390 | |
5368c726 | 391 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e | 392 | |
d0e7cb5d FF |
393 | reg = readl(&aup->mac->control); |
394 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
395 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
396 | wmb(); /* drain writebuffer */ |
397 | mdelay(10); | |
5ef3041e FF |
398 | } |
399 | ||
eb049630 | 400 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
401 | { |
402 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 403 | u32 reg; |
5ef3041e | 404 | |
5368c726 | 405 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e | 406 | |
d0e7cb5d FF |
407 | reg = readl(&aup->mac->control); |
408 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
409 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
410 | wmb(); /* drain writebuffer */ |
411 | mdelay(10); | |
5ef3041e FF |
412 | } |
413 | ||
414 | static void | |
415 | au1000_adjust_link(struct net_device *dev) | |
416 | { | |
417 | struct au1000_private *aup = netdev_priv(dev); | |
418 | struct phy_device *phydev = aup->phy_dev; | |
419 | unsigned long flags; | |
d0e7cb5d | 420 | u32 reg; |
5ef3041e FF |
421 | |
422 | int status_change = 0; | |
423 | ||
424 | BUG_ON(!aup->phy_dev); | |
425 | ||
426 | spin_lock_irqsave(&aup->lock, flags); | |
427 | ||
428 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 429 | /* speed changed */ |
5ef3041e | 430 | |
2cc3c6b1 | 431 | switch (phydev->speed) { |
5ef3041e FF |
432 | case SPEED_10: |
433 | case SPEED_100: | |
434 | break; | |
435 | default: | |
5368c726 FF |
436 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
437 | phydev->speed); | |
5ef3041e FF |
438 | break; |
439 | } | |
440 | ||
441 | aup->old_speed = phydev->speed; | |
442 | ||
443 | status_change = 1; | |
444 | } | |
445 | ||
446 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 447 | /* duplex mode changed */ |
5ef3041e FF |
448 | |
449 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 450 | au1000_hard_stop(dev); |
5ef3041e | 451 | |
d0e7cb5d FF |
452 | reg = readl(&aup->mac->control); |
453 | if (DUPLEX_FULL == phydev->duplex) { | |
454 | reg |= MAC_FULL_DUPLEX; | |
455 | reg &= ~MAC_DISABLE_RX_OWN; | |
456 | } else { | |
457 | reg &= ~MAC_FULL_DUPLEX; | |
458 | reg |= MAC_DISABLE_RX_OWN; | |
459 | } | |
460 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
461 | wmb(); /* drain writebuffer */ |
462 | mdelay(1); | |
5ef3041e | 463 | |
eb049630 | 464 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
465 | aup->old_duplex = phydev->duplex; |
466 | ||
467 | status_change = 1; | |
468 | } | |
469 | ||
2cc3c6b1 FF |
470 | if (phydev->link != aup->old_link) { |
471 | /* link state changed */ | |
5ef3041e FF |
472 | |
473 | if (!phydev->link) { | |
474 | /* link went down */ | |
475 | aup->old_speed = 0; | |
476 | aup->old_duplex = -1; | |
477 | } | |
478 | ||
479 | aup->old_link = phydev->link; | |
480 | status_change = 1; | |
481 | } | |
482 | ||
483 | spin_unlock_irqrestore(&aup->lock, flags); | |
484 | ||
485 | if (status_change) { | |
486 | if (phydev->link) | |
5368c726 FF |
487 | netdev_info(dev, "link up (%d/%s)\n", |
488 | phydev->speed, | |
5ef3041e FF |
489 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
490 | else | |
5368c726 | 491 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
492 | } |
493 | } | |
494 | ||
ec7eabdd | 495 | static int au1000_mii_probe(struct net_device *dev) |
0638dec0 | 496 | { |
454d7c9b | 497 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 | 498 | struct phy_device *phydev = NULL; |
18b8e15b | 499 | int phy_addr; |
0638dec0 | 500 | |
bd2302c2 FF |
501 | if (aup->phy_static_config) { |
502 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 503 | |
bd2302c2 | 504 | if (aup->phy_addr) |
7f854420 | 505 | phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); |
bd2302c2 | 506 | else |
5368c726 | 507 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 508 | return 0; |
18b8e15b | 509 | } |
0638dec0 | 510 | |
18b8e15b | 511 | /* find the first (lowest address) PHY |
dc99839c FF |
512 | * on the current MAC's MII bus |
513 | */ | |
18b8e15b | 514 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) |
7f854420 AL |
515 | if (mdiobus_get_phy(aup->mii_bus, aup->phy_addr)) { |
516 | phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); | |
18b8e15b FF |
517 | if (!aup->phy_search_highest_addr) |
518 | /* break out with first one found */ | |
519 | break; | |
520 | } | |
0638dec0 | 521 | |
18b8e15b FF |
522 | if (aup->phy1_search_mac0) { |
523 | /* try harder to find a PHY */ | |
524 | if (!phydev && (aup->mac_id == 1)) { | |
525 | /* no PHY found, maybe we have a dual PHY? */ | |
526 | dev_info(&dev->dev, ": no PHY found on MAC1, " | |
527 | "let's see if it's attached to MAC0...\n"); | |
528 | ||
529 | /* find the first (lowest address) non-attached | |
530 | * PHY on the MAC0 MII bus | |
531 | */ | |
532 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
533 | struct phy_device *const tmp_phydev = | |
7f854420 AL |
534 | mdiobus_get_phy(aup->mii_bus, |
535 | phy_addr); | |
18b8e15b FF |
536 | |
537 | if (aup->mac_id == 1) | |
538 | break; | |
539 | ||
540 | /* no PHY here... */ | |
541 | if (!tmp_phydev) | |
542 | continue; | |
543 | ||
544 | /* already claimed by MAC0 */ | |
545 | if (tmp_phydev->attached_dev) | |
546 | continue; | |
547 | ||
548 | phydev = tmp_phydev; | |
549 | break; /* found it */ | |
bd2302c2 | 550 | } |
1da177e4 LT |
551 | } |
552 | } | |
1da177e4 | 553 | |
0638dec0 | 554 | if (!phydev) { |
5368c726 | 555 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
556 | return -1; |
557 | } | |
558 | ||
0638dec0 | 559 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
560 | BUG_ON(phydev->attached_dev); |
561 | ||
84eff6d1 | 562 | phydev = phy_connect(dev, phydev_name(phydev), |
f9a8f83b | 563 | &au1000_adjust_link, PHY_INTERFACE_MODE_MII); |
0638dec0 HVR |
564 | |
565 | if (IS_ERR(phydev)) { | |
5368c726 | 566 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
567 | return PTR_ERR(phydev); |
568 | } | |
569 | ||
570 | /* mask with MAC supported features */ | |
571 | phydev->supported &= (SUPPORTED_10baseT_Half | |
572 | | SUPPORTED_10baseT_Full | |
573 | | SUPPORTED_100baseT_Half | |
574 | | SUPPORTED_100baseT_Full | |
575 | | SUPPORTED_Autoneg | |
576 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
577 | | SUPPORTED_MII | |
578 | | SUPPORTED_TP); | |
579 | ||
580 | phydev->advertising = phydev->supported; | |
581 | ||
582 | aup->old_link = 0; | |
583 | aup->old_speed = 0; | |
584 | aup->old_duplex = -1; | |
585 | aup->phy_dev = phydev; | |
586 | ||
2220943a | 587 | phy_attached_info(phydev); |
1da177e4 LT |
588 | |
589 | return 0; | |
590 | } | |
591 | ||
592 | ||
593 | /* | |
594 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 595 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
596 | * both, receive and transmit operations. |
597 | */ | |
3441592b | 598 | static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 | 599 | { |
3441592b | 600 | struct db_dest *pDB; |
1da177e4 LT |
601 | pDB = aup->pDBfree; |
602 | ||
ec7eabdd | 603 | if (pDB) |
1da177e4 | 604 | aup->pDBfree = pDB->pnext; |
ec7eabdd | 605 | |
1da177e4 LT |
606 | return pDB; |
607 | } | |
608 | ||
3441592b | 609 | void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) |
1da177e4 | 610 | { |
3441592b | 611 | struct db_dest *pDBfree = aup->pDBfree; |
1da177e4 LT |
612 | if (pDBfree) |
613 | pDBfree->pnext = pDB; | |
614 | aup->pDBfree = pDB; | |
615 | } | |
616 | ||
eb049630 | 617 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 618 | { |
454d7c9b | 619 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
620 | int i; |
621 | ||
eb049630 | 622 | au1000_hard_stop(dev); |
0638dec0 | 623 | |
462ca99c | 624 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
2f73bfbe ML |
625 | wmb(); /* drain writebuffer */ |
626 | mdelay(2); | |
462ca99c | 627 | writel(0, aup->enable); |
2f73bfbe ML |
628 | wmb(); /* drain writebuffer */ |
629 | mdelay(2); | |
0638dec0 | 630 | |
1da177e4 LT |
631 | aup->tx_full = 0; |
632 | for (i = 0; i < NUM_RX_DMA; i++) { | |
633 | /* reset control bits */ | |
634 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
635 | } | |
636 | for (i = 0; i < NUM_TX_DMA; i++) { | |
637 | /* reset control bits */ | |
638 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
639 | } | |
0638dec0 HVR |
640 | |
641 | aup->mac_enabled = 0; | |
642 | ||
1da177e4 LT |
643 | } |
644 | ||
eb049630 | 645 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 646 | { |
454d7c9b | 647 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
648 | unsigned long flags; |
649 | ||
5368c726 FF |
650 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
651 | (unsigned)aup); | |
0638dec0 HVR |
652 | |
653 | spin_lock_irqsave(&aup->lock, flags); | |
654 | ||
ec7eabdd | 655 | au1000_reset_mac_unlocked(dev); |
0638dec0 HVR |
656 | |
657 | spin_unlock_irqrestore(&aup->lock, flags); | |
658 | } | |
1da177e4 | 659 | |
6aa20a22 | 660 | /* |
1da177e4 LT |
661 | * Setup the receive and transmit "rings". These pointers are the addresses |
662 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
663 | * these are not descriptors sitting in memory. | |
664 | */ | |
6aa20a22 | 665 | static void |
553737aa | 666 | au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) |
1da177e4 LT |
667 | { |
668 | int i; | |
669 | ||
670 | for (i = 0; i < NUM_RX_DMA; i++) { | |
553737aa ML |
671 | aup->rx_dma_ring[i] = (struct rx_dma *) |
672 | (tx_base + 0x100 + sizeof(struct rx_dma) * i); | |
1da177e4 LT |
673 | } |
674 | for (i = 0; i < NUM_TX_DMA; i++) { | |
553737aa ML |
675 | aup->tx_dma_ring[i] = (struct tx_dma *) |
676 | (tx_base + sizeof(struct tx_dma) * i); | |
1da177e4 LT |
677 | } |
678 | } | |
679 | ||
0638dec0 HVR |
680 | /* |
681 | * ethtool operations | |
682 | */ | |
1da177e4 | 683 | |
0638dec0 | 684 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 685 | { |
454d7c9b | 686 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 687 | |
0638dec0 HVR |
688 | if (aup->phy_dev) |
689 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 690 | |
0638dec0 | 691 | return -EINVAL; |
1da177e4 LT |
692 | } |
693 | ||
0638dec0 | 694 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 695 | { |
454d7c9b | 696 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 697 | |
0638dec0 HVR |
698 | if (!capable(CAP_NET_ADMIN)) |
699 | return -EPERM; | |
1da177e4 | 700 | |
0638dec0 HVR |
701 | if (aup->phy_dev) |
702 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 703 | |
0638dec0 | 704 | return -EINVAL; |
1da177e4 LT |
705 | } |
706 | ||
707 | static void | |
708 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
709 | { | |
454d7c9b | 710 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 711 | |
7826d43f JP |
712 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
713 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
714 | snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME, | |
715 | aup->mac_id); | |
1da177e4 LT |
716 | } |
717 | ||
7cd2e6e3 FF |
718 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
719 | { | |
720 | struct au1000_private *aup = netdev_priv(dev); | |
721 | aup->msg_enable = value; | |
722 | } | |
723 | ||
724 | static u32 au1000_get_msglevel(struct net_device *dev) | |
725 | { | |
726 | struct au1000_private *aup = netdev_priv(dev); | |
727 | return aup->msg_enable; | |
728 | } | |
729 | ||
7282d491 | 730 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
731 | .get_settings = au1000_get_settings, |
732 | .set_settings = au1000_set_settings, | |
733 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 734 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
735 | .get_msglevel = au1000_get_msglevel, |
736 | .set_msglevel = au1000_set_msglevel, | |
1da177e4 LT |
737 | }; |
738 | ||
5ef3041e FF |
739 | |
740 | /* | |
741 | * Initialize the interface. | |
742 | * | |
743 | * When the device powers up, the clocks are disabled and the | |
744 | * mac is in reset state. When the interface is closed, we | |
745 | * do the same -- reset the device and disable the clocks to | |
746 | * conserve power. Thus, whenever au1000_init() is called, | |
747 | * the device should already be in reset state. | |
748 | */ | |
749 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 750 | { |
5ef3041e FF |
751 | struct au1000_private *aup = netdev_priv(dev); |
752 | unsigned long flags; | |
753 | int i; | |
754 | u32 control; | |
89be0501 | 755 | |
5368c726 | 756 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 757 | |
5ef3041e | 758 | /* bring the device out of reset */ |
eb049630 | 759 | au1000_enable_mac(dev, 1); |
89be0501 | 760 | |
5ef3041e | 761 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 762 | |
d0e7cb5d | 763 | writel(0, &aup->mac->control); |
5ef3041e FF |
764 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; |
765 | aup->tx_tail = aup->tx_head; | |
766 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 767 | |
d0e7cb5d FF |
768 | writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], |
769 | &aup->mac->mac_addr_high); | |
770 | writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
771 | dev->dev_addr[1]<<8 | dev->dev_addr[0], | |
772 | &aup->mac->mac_addr_low); | |
5ef3041e | 773 | |
18b8e15b | 774 | |
ec7eabdd | 775 | for (i = 0; i < NUM_RX_DMA; i++) |
5ef3041e | 776 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
ec7eabdd | 777 | |
2f73bfbe | 778 | wmb(); /* drain writebuffer */ |
1da177e4 | 779 | |
5ef3041e FF |
780 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
781 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
782 | control |= MAC_BIG_ENDIAN; | |
783 | #endif | |
784 | if (aup->phy_dev) { | |
785 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
786 | control |= MAC_FULL_DUPLEX; | |
787 | else | |
788 | control |= MAC_DISABLE_RX_OWN; | |
789 | } else { /* PHY-less op, assume full-duplex */ | |
790 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
791 | } |
792 | ||
d0e7cb5d FF |
793 | writel(control, &aup->mac->control); |
794 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ | |
2f73bfbe | 795 | wmb(); /* drain writebuffer */ |
1da177e4 | 796 | |
5ef3041e FF |
797 | spin_unlock_irqrestore(&aup->lock, flags); |
798 | return 0; | |
799 | } | |
1da177e4 | 800 | |
eb049630 | 801 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 802 | { |
5ef3041e | 803 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 804 | |
5ef3041e FF |
805 | ps->rx_packets++; |
806 | if (status & RX_MCAST_FRAME) | |
807 | ps->multicast++; | |
1da177e4 | 808 | |
5ef3041e FF |
809 | if (status & RX_ERROR) { |
810 | ps->rx_errors++; | |
811 | if (status & RX_MISSED_FRAME) | |
812 | ps->rx_missed_errors++; | |
4989ccb2 | 813 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
814 | ps->rx_length_errors++; |
815 | if (status & RX_CRC_ERROR) | |
816 | ps->rx_crc_errors++; | |
817 | if (status & RX_COLL) | |
818 | ps->collisions++; | |
2cc3c6b1 | 819 | } else |
5ef3041e | 820 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 821 | |
1da177e4 LT |
822 | } |
823 | ||
6aa20a22 | 824 | /* |
5ef3041e | 825 | * Au1000 receive routine. |
1da177e4 | 826 | */ |
5ef3041e | 827 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 828 | { |
454d7c9b | 829 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 830 | struct sk_buff *skb; |
d0e7cb5d | 831 | struct rx_dma *prxd; |
5ef3041e | 832 | u32 buff_stat, status; |
3441592b | 833 | struct db_dest *pDB; |
5ef3041e | 834 | u32 frmlen; |
1da177e4 | 835 | |
5368c726 | 836 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 837 | |
5ef3041e FF |
838 | prxd = aup->rx_dma_ring[aup->rx_head]; |
839 | buff_stat = prxd->buff_stat; | |
840 | while (buff_stat & RX_T_DONE) { | |
841 | status = prxd->status; | |
842 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 843 | au1000_update_rx_stats(dev, status); |
5ef3041e | 844 | if (!(status & RX_ERROR)) { |
1da177e4 | 845 | |
5ef3041e FF |
846 | /* good frame */ |
847 | frmlen = (status & RX_FRAME_LEN_MASK); | |
848 | frmlen -= 4; /* Remove FCS */ | |
1d266430 | 849 | skb = netdev_alloc_skb(dev, frmlen + 2); |
5ef3041e | 850 | if (skb == NULL) { |
5ef3041e FF |
851 | dev->stats.rx_dropped++; |
852 | continue; | |
853 | } | |
854 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
855 | skb_copy_to_linear_data(skb, | |
856 | (unsigned char *)pDB->vaddr, frmlen); | |
857 | skb_put(skb, frmlen); | |
858 | skb->protocol = eth_type_trans(skb, dev); | |
859 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 860 | } else { |
5ef3041e | 861 | if (au1000_debug > 4) { |
215e17be | 862 | pr_err("rx_error(s):"); |
5ef3041e | 863 | if (status & RX_MISSED_FRAME) |
215e17be | 864 | pr_cont(" miss"); |
5ef3041e | 865 | if (status & RX_WDOG_TIMER) |
215e17be | 866 | pr_cont(" wdog"); |
5ef3041e | 867 | if (status & RX_RUNT) |
215e17be | 868 | pr_cont(" runt"); |
5ef3041e | 869 | if (status & RX_OVERLEN) |
215e17be | 870 | pr_cont(" overlen"); |
5ef3041e | 871 | if (status & RX_COLL) |
215e17be | 872 | pr_cont(" coll"); |
5ef3041e | 873 | if (status & RX_MII_ERROR) |
215e17be | 874 | pr_cont(" mii error"); |
5ef3041e | 875 | if (status & RX_CRC_ERROR) |
215e17be | 876 | pr_cont(" crc error"); |
5ef3041e | 877 | if (status & RX_LEN_ERROR) |
215e17be | 878 | pr_cont(" len error"); |
5ef3041e | 879 | if (status & RX_U_CNTRL_FRAME) |
215e17be FF |
880 | pr_cont(" u control frame"); |
881 | pr_cont("\n"); | |
5ef3041e FF |
882 | } |
883 | } | |
884 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
885 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
2f73bfbe | 886 | wmb(); /* drain writebuffer */ |
1da177e4 | 887 | |
5ef3041e FF |
888 | /* next descriptor */ |
889 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
890 | buff_stat = prxd->buff_stat; | |
1da177e4 | 891 | } |
1da177e4 LT |
892 | return 0; |
893 | } | |
894 | ||
eb049630 | 895 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 896 | { |
454d7c9b | 897 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 898 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 899 | |
5ef3041e FF |
900 | if (status & TX_FRAME_ABORTED) { |
901 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
902 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
903 | /* any other tx errors are only valid | |
dc99839c FF |
904 | * in half duplex mode |
905 | */ | |
5ef3041e FF |
906 | ps->tx_errors++; |
907 | ps->tx_aborted_errors++; | |
908 | } | |
2cc3c6b1 | 909 | } else { |
5ef3041e FF |
910 | ps->tx_errors++; |
911 | ps->tx_aborted_errors++; | |
912 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
913 | ps->tx_carrier_errors++; | |
914 | } | |
915 | } | |
916 | } | |
0638dec0 | 917 | |
5ef3041e FF |
918 | /* |
919 | * Called from the interrupt service routine to acknowledge | |
920 | * the TX DONE bits. This is a must if the irq is setup as | |
921 | * edge triggered. | |
922 | */ | |
923 | static void au1000_tx_ack(struct net_device *dev) | |
924 | { | |
925 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 926 | struct tx_dma *ptxd; |
0638dec0 | 927 | |
5ef3041e | 928 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 929 | |
5ef3041e | 930 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 931 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
932 | ptxd->buff_stat &= ~TX_T_DONE; |
933 | ptxd->len = 0; | |
2f73bfbe | 934 | wmb(); /* drain writebuffer */ |
0638dec0 | 935 | |
5ef3041e FF |
936 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
937 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 938 | |
5ef3041e FF |
939 | if (aup->tx_full) { |
940 | aup->tx_full = 0; | |
941 | netif_wake_queue(dev); | |
942 | } | |
1da177e4 | 943 | } |
5ef3041e | 944 | } |
1da177e4 | 945 | |
5ef3041e FF |
946 | /* |
947 | * Au1000 interrupt service routine. | |
948 | */ | |
949 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
950 | { | |
951 | struct net_device *dev = dev_id; | |
1da177e4 | 952 | |
5ef3041e FF |
953 | /* Handle RX interrupts first to minimize chance of overrun */ |
954 | ||
955 | au1000_rx(dev); | |
956 | au1000_tx_ack(dev); | |
957 | return IRQ_RETVAL(1); | |
1da177e4 LT |
958 | } |
959 | ||
960 | static int au1000_open(struct net_device *dev) | |
961 | { | |
962 | int retval; | |
454d7c9b | 963 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 964 | |
5368c726 | 965 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 966 | |
2cc3c6b1 FF |
967 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
968 | dev->name, dev); | |
969 | if (retval) { | |
5368c726 | 970 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
971 | return retval; |
972 | } | |
973 | ||
2cc3c6b1 FF |
974 | retval = au1000_init(dev); |
975 | if (retval) { | |
5368c726 | 976 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
977 | free_irq(dev->irq, dev); |
978 | return retval; | |
979 | } | |
1da177e4 | 980 | |
0638dec0 HVR |
981 | if (aup->phy_dev) { |
982 | /* cause the PHY state machine to schedule a link state check */ | |
983 | aup->phy_dev->state = PHY_CHANGELINK; | |
984 | phy_start(aup->phy_dev); | |
1da177e4 LT |
985 | } |
986 | ||
0638dec0 | 987 | netif_start_queue(dev); |
1da177e4 | 988 | |
5368c726 | 989 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
990 | |
991 | return 0; | |
992 | } | |
993 | ||
994 | static int au1000_close(struct net_device *dev) | |
995 | { | |
0638dec0 | 996 | unsigned long flags; |
454d7c9b | 997 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 998 | |
5368c726 | 999 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 1000 | |
0638dec0 HVR |
1001 | if (aup->phy_dev) |
1002 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
1003 | |
1004 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 1005 | |
ec7eabdd | 1006 | au1000_reset_mac_unlocked(dev); |
0638dec0 | 1007 | |
1da177e4 LT |
1008 | /* stop the device */ |
1009 | netif_stop_queue(dev); | |
1010 | ||
1011 | /* disable the interrupt */ | |
1012 | free_irq(dev->irq, dev); | |
1013 | spin_unlock_irqrestore(&aup->lock, flags); | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
1da177e4 LT |
1018 | /* |
1019 | * Au1000 transmit routine. | |
1020 | */ | |
61357325 | 1021 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1022 | { |
454d7c9b | 1023 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 1024 | struct net_device_stats *ps = &dev->stats; |
d0e7cb5d | 1025 | struct tx_dma *ptxd; |
1da177e4 | 1026 | u32 buff_stat; |
3441592b | 1027 | struct db_dest *pDB; |
1da177e4 LT |
1028 | int i; |
1029 | ||
5368c726 FF |
1030 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
1031 | (unsigned)aup, skb->len, | |
1da177e4 LT |
1032 | skb->data, aup->tx_head); |
1033 | ||
1034 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
1035 | buff_stat = ptxd->buff_stat; | |
1036 | if (buff_stat & TX_DMA_ENABLE) { | |
1037 | /* We've wrapped around and the transmitter is still busy */ | |
1038 | netif_stop_queue(dev); | |
1039 | aup->tx_full = 1; | |
5b548140 | 1040 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 1041 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 1042 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
1043 | ptxd->len = 0; |
1044 | } | |
1045 | ||
1046 | if (aup->tx_full) { | |
1047 | aup->tx_full = 0; | |
1048 | netif_wake_queue(dev); | |
1049 | } | |
1050 | ||
1051 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 1052 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 1053 | if (skb->len < ETH_ZLEN) { |
ec7eabdd | 1054 | for (i = skb->len; i < ETH_ZLEN; i++) |
1da177e4 | 1055 | ((char *)pDB->vaddr)[i] = 0; |
ec7eabdd | 1056 | |
1da177e4 | 1057 | ptxd->len = ETH_ZLEN; |
2cc3c6b1 | 1058 | } else |
5ef3041e | 1059 | ptxd->len = skb->len; |
1da177e4 | 1060 | |
5ef3041e FF |
1061 | ps->tx_packets++; |
1062 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 1063 | |
5ef3041e | 1064 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
2f73bfbe | 1065 | wmb(); /* drain writebuffer */ |
5ef3041e FF |
1066 | dev_kfree_skb(skb); |
1067 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 1068 | return NETDEV_TX_OK; |
1da177e4 LT |
1069 | } |
1070 | ||
1da177e4 LT |
1071 | /* |
1072 | * The Tx ring has been full longer than the watchdog timeout | |
1073 | * value. The transmitter must be hung? | |
1074 | */ | |
1075 | static void au1000_tx_timeout(struct net_device *dev) | |
1076 | { | |
5368c726 | 1077 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 1078 | au1000_reset_mac(dev); |
1da177e4 | 1079 | au1000_init(dev); |
1ae5dc34 | 1080 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
1081 | netif_wake_queue(dev); |
1082 | } | |
1083 | ||
d9a92cee | 1084 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 1085 | { |
454d7c9b | 1086 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d | 1087 | u32 reg; |
1da177e4 | 1088 | |
18b8e15b | 1089 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
d0e7cb5d | 1090 | reg = readl(&aup->mac->control); |
1da177e4 | 1091 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
d0e7cb5d | 1092 | reg |= MAC_PROMISCUOUS; |
1da177e4 | 1093 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1094 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
d0e7cb5d FF |
1095 | reg |= MAC_PASS_ALL_MULTI; |
1096 | reg &= ~MAC_PROMISCUOUS; | |
5368c726 | 1097 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 1098 | } else { |
22bedad3 | 1099 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1100 | u32 mc_filter[2]; /* Multicast hash filter */ |
1101 | ||
1102 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
1103 | netdev_for_each_mc_addr(ha, dev) |
1104 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 1105 | (long *)mc_filter); |
d0e7cb5d FF |
1106 | writel(mc_filter[1], &aup->mac->multi_hash_high); |
1107 | writel(mc_filter[0], &aup->mac->multi_hash_low); | |
1108 | reg &= ~MAC_PROMISCUOUS; | |
1109 | reg |= MAC_HASH_MODE; | |
1da177e4 | 1110 | } |
d0e7cb5d | 1111 | writel(reg, &aup->mac->control); |
1da177e4 LT |
1112 | } |
1113 | ||
1da177e4 LT |
1114 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1115 | { | |
454d7c9b | 1116 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1117 | |
2cc3c6b1 FF |
1118 | if (!netif_running(dev)) |
1119 | return -EINVAL; | |
1da177e4 | 1120 | |
2cc3c6b1 FF |
1121 | if (!aup->phy_dev) |
1122 | return -EINVAL; /* PHY not controllable */ | |
1da177e4 | 1123 | |
28b04113 | 1124 | return phy_mii_ioctl(aup->phy_dev, rq, cmd); |
1da177e4 LT |
1125 | } |
1126 | ||
d9a92cee AB |
1127 | static const struct net_device_ops au1000_netdev_ops = { |
1128 | .ndo_open = au1000_open, | |
1129 | .ndo_stop = au1000_close, | |
1130 | .ndo_start_xmit = au1000_tx, | |
afc4b13d | 1131 | .ndo_set_rx_mode = au1000_multicast_list, |
d9a92cee AB |
1132 | .ndo_do_ioctl = au1000_ioctl, |
1133 | .ndo_tx_timeout = au1000_tx_timeout, | |
1134 | .ndo_set_mac_address = eth_mac_addr, | |
1135 | .ndo_validate_addr = eth_validate_addr, | |
1136 | .ndo_change_mtu = eth_change_mtu, | |
1137 | }; | |
1138 | ||
0cb0568d | 1139 | static int au1000_probe(struct platform_device *pdev) |
5ef3041e | 1140 | { |
5ef3041e | 1141 | struct au1000_private *aup = NULL; |
bd2302c2 | 1142 | struct au1000_eth_platform_data *pd; |
5ef3041e | 1143 | struct net_device *dev = NULL; |
3441592b | 1144 | struct db_dest *pDB, *pDBfree; |
bd2302c2 | 1145 | int irq, i, err = 0; |
553737aa | 1146 | struct resource *base, *macen, *macdma; |
5ef3041e | 1147 | |
bd2302c2 FF |
1148 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1149 | if (!base) { | |
5368c726 | 1150 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1151 | err = -ENODEV; |
1152 | goto out; | |
1153 | } | |
5ef3041e | 1154 | |
bd2302c2 FF |
1155 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1156 | if (!macen) { | |
5368c726 | 1157 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1158 | err = -ENODEV; |
1159 | goto out; | |
1160 | } | |
5ef3041e | 1161 | |
bd2302c2 FF |
1162 | irq = platform_get_irq(pdev, 0); |
1163 | if (irq < 0) { | |
5368c726 | 1164 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1165 | err = -ENODEV; |
1166 | goto out; | |
1167 | } | |
5ef3041e | 1168 | |
553737aa ML |
1169 | macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1170 | if (!macdma) { | |
1171 | dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); | |
1172 | err = -ENODEV; | |
1173 | goto out; | |
1174 | } | |
1175 | ||
18b8e15b FF |
1176 | if (!request_mem_region(base->start, resource_size(base), |
1177 | pdev->name)) { | |
5368c726 | 1178 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1179 | err = -ENXIO; |
1180 | goto out; | |
1181 | } | |
1182 | ||
18b8e15b FF |
1183 | if (!request_mem_region(macen->start, resource_size(macen), |
1184 | pdev->name)) { | |
5368c726 | 1185 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1186 | err = -ENXIO; |
1187 | goto err_request; | |
1188 | } | |
5ef3041e | 1189 | |
553737aa ML |
1190 | if (!request_mem_region(macdma->start, resource_size(macdma), |
1191 | pdev->name)) { | |
1192 | dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); | |
1193 | err = -ENXIO; | |
1194 | goto err_macdma; | |
1195 | } | |
1196 | ||
5ef3041e FF |
1197 | dev = alloc_etherdev(sizeof(struct au1000_private)); |
1198 | if (!dev) { | |
bd2302c2 FF |
1199 | err = -ENOMEM; |
1200 | goto err_alloc; | |
5ef3041e FF |
1201 | } |
1202 | ||
bd2302c2 FF |
1203 | SET_NETDEV_DEV(dev, &pdev->dev); |
1204 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1205 | aup = netdev_priv(dev); |
1206 | ||
1207 | spin_lock_init(&aup->lock); | |
18b8e15b FF |
1208 | aup->msg_enable = (au1000_debug < 4 ? |
1209 | AU1000_DEF_MSG_ENABLE : au1000_debug); | |
5ef3041e | 1210 | |
dc99839c FF |
1211 | /* Allocate the data buffers |
1212 | * Snooping works fine with eth on all au1xxx | |
1213 | */ | |
5ef3041e FF |
1214 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * |
1215 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1216 | &aup->dma_addr, 0); | |
1217 | if (!aup->vaddr) { | |
5368c726 | 1218 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1219 | err = -ENOMEM; |
1220 | goto err_vaddr; | |
5ef3041e FF |
1221 | } |
1222 | ||
1223 | /* aup->mac is the base address of the MAC's registers */ | |
d0e7cb5d | 1224 | aup->mac = (struct mac_reg *) |
18b8e15b | 1225 | ioremap_nocache(base->start, resource_size(base)); |
bd2302c2 | 1226 | if (!aup->mac) { |
5368c726 | 1227 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1228 | err = -ENXIO; |
1229 | goto err_remap1; | |
1230 | } | |
5ef3041e | 1231 | |
ec7eabdd | 1232 | /* Setup some variables for quick register address access */ |
d0e7cb5d | 1233 | aup->enable = (u32 *)ioremap_nocache(macen->start, |
18b8e15b | 1234 | resource_size(macen)); |
bd2302c2 | 1235 | if (!aup->enable) { |
5368c726 | 1236 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1237 | err = -ENXIO; |
1238 | goto err_remap2; | |
1239 | } | |
1240 | aup->mac_id = pdev->id; | |
5ef3041e | 1241 | |
553737aa ML |
1242 | aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma)); |
1243 | if (!aup->macdma) { | |
1244 | dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); | |
1245 | err = -ENXIO; | |
1246 | goto err_remap3; | |
1247 | } | |
1248 | ||
1249 | au1000_setup_hw_rings(aup, aup->macdma); | |
5ef3041e | 1250 | |
462ca99c | 1251 | writel(0, aup->enable); |
5ef3041e FF |
1252 | aup->mac_enabled = 0; |
1253 | ||
1fc2c469 | 1254 | pd = dev_get_platdata(&pdev->dev); |
bd2302c2 | 1255 | if (!pd) { |
18b8e15b FF |
1256 | dev_info(&pdev->dev, "no platform_data passed," |
1257 | " PHY search on MAC0\n"); | |
bd2302c2 FF |
1258 | aup->phy1_search_mac0 = 1; |
1259 | } else { | |
7718f2c2 | 1260 | if (is_valid_ether_addr(pd->mac)) { |
d458cdf7 | 1261 | memcpy(dev->dev_addr, pd->mac, ETH_ALEN); |
7718f2c2 DK |
1262 | } else { |
1263 | /* Set a random MAC since no valid provided by platform_data. */ | |
1264 | eth_hw_addr_random(dev); | |
1265 | } | |
f6673653 | 1266 | |
bd2302c2 FF |
1267 | aup->phy_static_config = pd->phy_static_config; |
1268 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1269 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1270 | aup->phy_addr = pd->phy_addr; | |
1271 | aup->phy_busid = pd->phy_busid; | |
1272 | aup->phy_irq = pd->phy_irq; | |
1273 | } | |
1274 | ||
1275 | if (aup->phy_busid && aup->phy_busid > 0) { | |
18b8e15b | 1276 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); |
bd2302c2 FF |
1277 | err = -ENODEV; |
1278 | goto err_mdiobus_alloc; | |
1279 | } | |
1280 | ||
5ef3041e | 1281 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1282 | if (aup->mii_bus == NULL) { |
5368c726 | 1283 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1284 | err = -ENOMEM; |
1285 | goto err_mdiobus_alloc; | |
1286 | } | |
5ef3041e FF |
1287 | |
1288 | aup->mii_bus->priv = dev; | |
1289 | aup->mii_bus->read = au1000_mdiobus_read; | |
1290 | aup->mii_bus->write = au1000_mdiobus_write; | |
1291 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1292 | aup->mii_bus->name = "au1000_eth_mii"; | |
f74299b6 FF |
1293 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1294 | pdev->name, aup->mac_id); | |
dcbfef82 | 1295 | |
5ef3041e | 1296 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1297 | if (aup->phy_static_config) |
1298 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1299 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1300 | ||
1301 | err = mdiobus_register(aup->mii_bus); | |
1302 | if (err) { | |
5368c726 | 1303 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1304 | goto err_mdiobus_reg; |
1305 | } | |
5ef3041e | 1306 | |
69129920 PST |
1307 | err = au1000_mii_probe(dev); |
1308 | if (err != 0) | |
5ef3041e | 1309 | goto err_out; |
5ef3041e FF |
1310 | |
1311 | pDBfree = NULL; | |
1312 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1313 | pDB = aup->db; | |
1314 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1315 | pDB->pnext = pDBfree; | |
1316 | pDBfree = pDB; | |
1317 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1318 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1319 | pDB++; | |
1320 | } | |
1321 | aup->pDBfree = pDBfree; | |
1322 | ||
69129920 | 1323 | err = -ENODEV; |
5ef3041e | 1324 | for (i = 0; i < NUM_RX_DMA; i++) { |
eb049630 | 1325 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1326 | if (!pDB) |
5ef3041e | 1327 | goto err_out; |
ec7eabdd | 1328 | |
5ef3041e FF |
1329 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1330 | aup->rx_db_inuse[i] = pDB; | |
1331 | } | |
69129920 PST |
1332 | |
1333 | err = -ENODEV; | |
5ef3041e | 1334 | for (i = 0; i < NUM_TX_DMA; i++) { |
eb049630 | 1335 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1336 | if (!pDB) |
5ef3041e | 1337 | goto err_out; |
ec7eabdd | 1338 | |
5ef3041e FF |
1339 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1340 | aup->tx_dma_ring[i]->len = 0; | |
1341 | aup->tx_db_inuse[i] = pDB; | |
1342 | } | |
1343 | ||
bd2302c2 FF |
1344 | dev->base_addr = base->start; |
1345 | dev->irq = irq; | |
1346 | dev->netdev_ops = &au1000_netdev_ops; | |
7ad24ea4 | 1347 | dev->ethtool_ops = &au1000_ethtool_ops; |
bd2302c2 FF |
1348 | dev->watchdog_timeo = ETH_TX_TIMEOUT; |
1349 | ||
5ef3041e FF |
1350 | /* |
1351 | * The boot code uses the ethernet controller, so reset it to start | |
1352 | * fresh. au1000_init() expects that the device is in reset state. | |
1353 | */ | |
eb049630 | 1354 | au1000_reset_mac(dev); |
5ef3041e | 1355 | |
bd2302c2 FF |
1356 | err = register_netdev(dev); |
1357 | if (err) { | |
5368c726 | 1358 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1359 | goto err_out; |
1360 | } | |
1361 | ||
5368c726 FF |
1362 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1363 | (unsigned long)base->start, irq); | |
e9c3f99f VB |
1364 | |
1365 | pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
bd2302c2 FF |
1366 | |
1367 | return 0; | |
5ef3041e FF |
1368 | |
1369 | err_out: | |
bd2302c2 | 1370 | if (aup->mii_bus != NULL) |
5ef3041e | 1371 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1372 | |
1373 | /* here we should have a valid dev plus aup-> register addresses | |
dc99839c FF |
1374 | * so we can reset the mac properly. |
1375 | */ | |
eb049630 | 1376 | au1000_reset_mac(dev); |
5ef3041e FF |
1377 | |
1378 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1379 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1380 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1381 | } |
1382 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1383 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1384 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1385 | } |
bd2302c2 FF |
1386 | err_mdiobus_reg: |
1387 | mdiobus_free(aup->mii_bus); | |
1388 | err_mdiobus_alloc: | |
553737aa ML |
1389 | iounmap(aup->macdma); |
1390 | err_remap3: | |
bd2302c2 FF |
1391 | iounmap(aup->enable); |
1392 | err_remap2: | |
1393 | iounmap(aup->mac); | |
1394 | err_remap1: | |
5ef3041e FF |
1395 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1396 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1397 | err_vaddr: |
5ef3041e | 1398 | free_netdev(dev); |
bd2302c2 | 1399 | err_alloc: |
553737aa ML |
1400 | release_mem_region(macdma->start, resource_size(macdma)); |
1401 | err_macdma: | |
bd2302c2 FF |
1402 | release_mem_region(macen->start, resource_size(macen)); |
1403 | err_request: | |
1404 | release_mem_region(base->start, resource_size(base)); | |
1405 | out: | |
1406 | return err; | |
5ef3041e FF |
1407 | } |
1408 | ||
0cb0568d | 1409 | static int au1000_remove(struct platform_device *pdev) |
5ef3041e | 1410 | { |
bd2302c2 FF |
1411 | struct net_device *dev = platform_get_drvdata(pdev); |
1412 | struct au1000_private *aup = netdev_priv(dev); | |
1413 | int i; | |
1414 | struct resource *base, *macen; | |
5ef3041e | 1415 | |
bd2302c2 FF |
1416 | unregister_netdev(dev); |
1417 | mdiobus_unregister(aup->mii_bus); | |
1418 | mdiobus_free(aup->mii_bus); | |
1419 | ||
1420 | for (i = 0; i < NUM_RX_DMA; i++) | |
1421 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1422 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1423 | |
1424 | for (i = 0; i < NUM_TX_DMA; i++) | |
1425 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1426 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1427 | |
1428 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1429 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1430 | (void *)aup->vaddr, aup->dma_addr); | |
1431 | ||
553737aa | 1432 | iounmap(aup->macdma); |
bd2302c2 FF |
1433 | iounmap(aup->mac); |
1434 | iounmap(aup->enable); | |
1435 | ||
553737aa ML |
1436 | base = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1437 | release_mem_region(base->start, resource_size(base)); | |
1438 | ||
bd2302c2 FF |
1439 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1440 | release_mem_region(base->start, resource_size(base)); | |
1441 | ||
1442 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1443 | release_mem_region(macen->start, resource_size(macen)); | |
1444 | ||
1445 | free_netdev(dev); | |
5ef3041e | 1446 | |
5ef3041e FF |
1447 | return 0; |
1448 | } | |
1449 | ||
bd2302c2 FF |
1450 | static struct platform_driver au1000_eth_driver = { |
1451 | .probe = au1000_probe, | |
0cb0568d | 1452 | .remove = au1000_remove, |
bd2302c2 FF |
1453 | .driver = { |
1454 | .name = "au1000-eth", | |
bd2302c2 FF |
1455 | }, |
1456 | }; | |
bd2302c2 | 1457 | |
db62f684 | 1458 | module_platform_driver(au1000_eth_driver); |
5ef3041e | 1459 | |
db62f684 | 1460 | MODULE_ALIAS("platform:au1000-eth"); |