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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 | 15 | * Author: MontaVista Software, Inc. |
ec7eabdd | 16 | * ppopov@mvista.com or source@mvista.com |
1da177e4 LT |
17 | * |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
0ab75ae8 | 30 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
31 | * |
32 | * ######################################################################## | |
33 | * | |
6aa20a22 | 34 | * |
1da177e4 | 35 | */ |
215e17be FF |
36 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
37 | ||
bc36b428 | 38 | #include <linux/capability.h> |
d791c2bd | 39 | #include <linux/dma-mapping.h> |
1da177e4 LT |
40 | #include <linux/module.h> |
41 | #include <linux/kernel.h> | |
1da177e4 LT |
42 | #include <linux/string.h> |
43 | #include <linux/timer.h> | |
44 | #include <linux/errno.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/bitops.h> | |
48 | #include <linux/slab.h> | |
49 | #include <linux/interrupt.h> | |
1da177e4 LT |
50 | #include <linux/netdevice.h> |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
bd2302c2 | 58 | #include <linux/platform_device.h> |
49a42c08 FF |
59 | #include <linux/cpu.h> |
60 | #include <linux/io.h> | |
25b31cb1 | 61 | |
1da177e4 LT |
62 | #include <asm/mipsregs.h> |
63 | #include <asm/irq.h> | |
1da177e4 LT |
64 | #include <asm/processor.h> |
65 | ||
25b31cb1 | 66 | #include <au1000.h> |
bd2302c2 | 67 | #include <au1xxx_eth.h> |
25b31cb1 YY |
68 | #include <prom.h> |
69 | ||
1da177e4 LT |
70 | #include "au1000_eth.h" |
71 | ||
72 | #ifdef AU1000_ETH_DEBUG | |
73 | static int au1000_debug = 5; | |
74 | #else | |
75 | static int au1000_debug = 3; | |
76 | #endif | |
77 | ||
7cd2e6e3 FF |
78 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK) | |
81 | ||
89be0501 | 82 | #define DRV_NAME "au1000_eth" |
8020eb82 | 83 | #define DRV_VERSION "1.7" |
1da177e4 LT |
84 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
85 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
86 | ||
87 | MODULE_AUTHOR(DRV_AUTHOR); | |
88 | MODULE_DESCRIPTION(DRV_DESC); | |
89 | MODULE_LICENSE("GPL"); | |
13130c7a | 90 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 91 | |
fb1a7602 ML |
92 | /* AU1000 MAC registers and bits */ |
93 | #define MAC_CONTROL 0x0 | |
94 | # define MAC_RX_ENABLE (1 << 2) | |
95 | # define MAC_TX_ENABLE (1 << 3) | |
96 | # define MAC_DEF_CHECK (1 << 5) | |
97 | # define MAC_SET_BL(X) (((X) & 0x3) << 6) | |
98 | # define MAC_AUTO_PAD (1 << 8) | |
99 | # define MAC_DISABLE_RETRY (1 << 10) | |
100 | # define MAC_DISABLE_BCAST (1 << 11) | |
101 | # define MAC_LATE_COL (1 << 12) | |
102 | # define MAC_HASH_MODE (1 << 13) | |
103 | # define MAC_HASH_ONLY (1 << 15) | |
104 | # define MAC_PASS_ALL (1 << 16) | |
105 | # define MAC_INVERSE_FILTER (1 << 17) | |
106 | # define MAC_PROMISCUOUS (1 << 18) | |
107 | # define MAC_PASS_ALL_MULTI (1 << 19) | |
108 | # define MAC_FULL_DUPLEX (1 << 20) | |
109 | # define MAC_NORMAL_MODE 0 | |
110 | # define MAC_INT_LOOPBACK (1 << 21) | |
111 | # define MAC_EXT_LOOPBACK (1 << 22) | |
112 | # define MAC_DISABLE_RX_OWN (1 << 23) | |
113 | # define MAC_BIG_ENDIAN (1 << 30) | |
114 | # define MAC_RX_ALL (1 << 31) | |
115 | #define MAC_ADDRESS_HIGH 0x4 | |
116 | #define MAC_ADDRESS_LOW 0x8 | |
117 | #define MAC_MCAST_HIGH 0xC | |
118 | #define MAC_MCAST_LOW 0x10 | |
119 | #define MAC_MII_CNTRL 0x14 | |
120 | # define MAC_MII_BUSY (1 << 0) | |
121 | # define MAC_MII_READ 0 | |
122 | # define MAC_MII_WRITE (1 << 1) | |
123 | # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) | |
124 | # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) | |
125 | #define MAC_MII_DATA 0x18 | |
126 | #define MAC_FLOW_CNTRL 0x1C | |
127 | # define MAC_FLOW_CNTRL_BUSY (1 << 0) | |
128 | # define MAC_FLOW_CNTRL_ENABLE (1 << 1) | |
129 | # define MAC_PASS_CONTROL (1 << 2) | |
130 | # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) | |
131 | #define MAC_VLAN1_TAG 0x20 | |
132 | #define MAC_VLAN2_TAG 0x24 | |
133 | ||
134 | /* Ethernet Controller Enable */ | |
135 | # define MAC_EN_CLOCK_ENABLE (1 << 0) | |
136 | # define MAC_EN_RESET0 (1 << 1) | |
137 | # define MAC_EN_TOSS (0 << 2) | |
138 | # define MAC_EN_CACHEABLE (1 << 3) | |
139 | # define MAC_EN_RESET1 (1 << 4) | |
140 | # define MAC_EN_RESET2 (1 << 5) | |
141 | # define MAC_DMA_RESET (1 << 6) | |
142 | ||
143 | /* Ethernet Controller DMA Channels */ | |
144 | /* offsets from MAC_TX_RING_ADDR address */ | |
145 | #define MAC_TX_BUFF0_STATUS 0x0 | |
146 | # define TX_FRAME_ABORTED (1 << 0) | |
147 | # define TX_JAB_TIMEOUT (1 << 1) | |
148 | # define TX_NO_CARRIER (1 << 2) | |
149 | # define TX_LOSS_CARRIER (1 << 3) | |
150 | # define TX_EXC_DEF (1 << 4) | |
151 | # define TX_LATE_COLL_ABORT (1 << 5) | |
152 | # define TX_EXC_COLL (1 << 6) | |
153 | # define TX_UNDERRUN (1 << 7) | |
154 | # define TX_DEFERRED (1 << 8) | |
155 | # define TX_LATE_COLL (1 << 9) | |
156 | # define TX_COLL_CNT_MASK (0xF << 10) | |
157 | # define TX_PKT_RETRY (1 << 31) | |
158 | #define MAC_TX_BUFF0_ADDR 0x4 | |
159 | # define TX_DMA_ENABLE (1 << 0) | |
160 | # define TX_T_DONE (1 << 1) | |
161 | # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
162 | #define MAC_TX_BUFF0_LEN 0x8 | |
163 | #define MAC_TX_BUFF1_STATUS 0x10 | |
164 | #define MAC_TX_BUFF1_ADDR 0x14 | |
165 | #define MAC_TX_BUFF1_LEN 0x18 | |
166 | #define MAC_TX_BUFF2_STATUS 0x20 | |
167 | #define MAC_TX_BUFF2_ADDR 0x24 | |
168 | #define MAC_TX_BUFF2_LEN 0x28 | |
169 | #define MAC_TX_BUFF3_STATUS 0x30 | |
170 | #define MAC_TX_BUFF3_ADDR 0x34 | |
171 | #define MAC_TX_BUFF3_LEN 0x38 | |
172 | ||
173 | /* offsets from MAC_RX_RING_ADDR */ | |
174 | #define MAC_RX_BUFF0_STATUS 0x0 | |
175 | # define RX_FRAME_LEN_MASK 0x3fff | |
176 | # define RX_WDOG_TIMER (1 << 14) | |
177 | # define RX_RUNT (1 << 15) | |
178 | # define RX_OVERLEN (1 << 16) | |
179 | # define RX_COLL (1 << 17) | |
180 | # define RX_ETHER (1 << 18) | |
181 | # define RX_MII_ERROR (1 << 19) | |
182 | # define RX_DRIBBLING (1 << 20) | |
183 | # define RX_CRC_ERROR (1 << 21) | |
184 | # define RX_VLAN1 (1 << 22) | |
185 | # define RX_VLAN2 (1 << 23) | |
186 | # define RX_LEN_ERROR (1 << 24) | |
187 | # define RX_CNTRL_FRAME (1 << 25) | |
188 | # define RX_U_CNTRL_FRAME (1 << 26) | |
189 | # define RX_MCAST_FRAME (1 << 27) | |
190 | # define RX_BCAST_FRAME (1 << 28) | |
191 | # define RX_FILTER_FAIL (1 << 29) | |
192 | # define RX_PACKET_FILTER (1 << 30) | |
193 | # define RX_MISSED_FRAME (1 << 31) | |
194 | ||
195 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
196 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | |
197 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
198 | #define MAC_RX_BUFF0_ADDR 0x4 | |
199 | # define RX_DMA_ENABLE (1 << 0) | |
200 | # define RX_T_DONE (1 << 1) | |
201 | # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
202 | # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) | |
203 | #define MAC_RX_BUFF1_STATUS 0x10 | |
204 | #define MAC_RX_BUFF1_ADDR 0x14 | |
205 | #define MAC_RX_BUFF2_STATUS 0x20 | |
206 | #define MAC_RX_BUFF2_ADDR 0x24 | |
207 | #define MAC_RX_BUFF3_STATUS 0x30 | |
208 | #define MAC_RX_BUFF3_ADDR 0x34 | |
209 | ||
1da177e4 LT |
210 | /* |
211 | * Theory of operation | |
212 | * | |
6aa20a22 JG |
213 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
214 | * There are four receive and four transmit descriptors. These | |
215 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
216 | * hardware registers. |
217 | * | |
218 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 219 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
220 | * hardware registers, however, are still mapped at KSEG1 to |
221 | * make sure there's no out-of-order writes, and that all writes | |
222 | * complete immediately. | |
223 | */ | |
224 | ||
0638dec0 HVR |
225 | /* |
226 | * board-specific configurations | |
227 | * | |
228 | * PHY detection algorithm | |
229 | * | |
bd2302c2 | 230 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
231 | * autodetected: |
232 | * | |
233 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 234 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
235 | * defined) PHY address not already claimed by another netdev. |
236 | * | |
237 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 238 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
239 | * the first MII bus is searched as well for an unclaimed PHY; this is |
240 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
241 | * bus. | |
242 | * | |
243 | * Finally, if no PHY is found, then the corresponding ethernet | |
244 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
245 | */ |
246 | ||
bd2302c2 | 247 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 248 | |
0638dec0 HVR |
249 | /* static PHY setup |
250 | * | |
251 | * most boards PHY setup should be detectable properly with the | |
252 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
253 | * you have a switch attached, or want to use the PHY's interrupt | |
254 | * notification capabilities) you can provide a static PHY | |
255 | * configuration here | |
256 | * | |
257 | * IRQs may only be set, if a PHY address was configured | |
258 | * If a PHY address is given, also a bus id is required to be set | |
259 | * | |
260 | * ps: make sure the used irqs are configured properly in the board | |
261 | * specific irq-map | |
262 | */ | |
1da177e4 | 263 | |
eb049630 | 264 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
265 | { |
266 | unsigned long flags; | |
267 | struct au1000_private *aup = netdev_priv(dev); | |
268 | ||
269 | spin_lock_irqsave(&aup->lock, flags); | |
270 | ||
ec7eabdd | 271 | if (force_reset || (!aup->mac_enabled)) { |
462ca99c | 272 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
2f73bfbe ML |
273 | wmb(); /* drain writebuffer */ |
274 | mdelay(2); | |
d0e7cb5d | 275 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
462ca99c | 276 | | MAC_EN_CLOCK_ENABLE), aup->enable); |
2f73bfbe ML |
277 | wmb(); /* drain writebuffer */ |
278 | mdelay(2); | |
5ef3041e FF |
279 | |
280 | aup->mac_enabled = 1; | |
281 | } | |
282 | ||
283 | spin_unlock_irqrestore(&aup->lock, flags); | |
284 | } | |
285 | ||
0638dec0 HVR |
286 | /* |
287 | * MII operations | |
288 | */ | |
1210dde7 | 289 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 290 | { |
454d7c9b | 291 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
292 | u32 *const mii_control_reg = &aup->mac->mii_control; |
293 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
294 | u32 timedout = 20; |
295 | u32 mii_control; | |
296 | ||
d0e7cb5d | 297 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
298 | mdelay(1); |
299 | if (--timedout == 0) { | |
5368c726 | 300 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
301 | return -1; |
302 | } | |
303 | } | |
304 | ||
6aa20a22 | 305 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 306 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 | 307 | |
d0e7cb5d | 308 | writel(mii_control, mii_control_reg); |
1da177e4 LT |
309 | |
310 | timedout = 20; | |
d0e7cb5d | 311 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
312 | mdelay(1); |
313 | if (--timedout == 0) { | |
5368c726 | 314 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
315 | return -1; |
316 | } | |
317 | } | |
d0e7cb5d | 318 | return readl(mii_data_reg); |
1da177e4 LT |
319 | } |
320 | ||
1210dde7 AB |
321 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
322 | int reg, u16 value) | |
1da177e4 | 323 | { |
454d7c9b | 324 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
325 | u32 *const mii_control_reg = &aup->mac->mii_control; |
326 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
327 | u32 timedout = 20; |
328 | u32 mii_control; | |
329 | ||
d0e7cb5d | 330 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
331 | mdelay(1); |
332 | if (--timedout == 0) { | |
5368c726 | 333 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
334 | return; |
335 | } | |
336 | } | |
337 | ||
6aa20a22 | 338 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 339 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 | 340 | |
d0e7cb5d FF |
341 | writel(value, mii_data_reg); |
342 | writel(mii_control, mii_control_reg); | |
1da177e4 LT |
343 | } |
344 | ||
1210dde7 | 345 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 | 346 | { |
0638dec0 HVR |
347 | struct net_device *const dev = bus->priv; |
348 | ||
dc99839c FF |
349 | /* make sure the MAC associated with this |
350 | * mii_bus is enabled | |
351 | */ | |
352 | au1000_enable_mac(dev, 0); | |
353 | ||
1210dde7 | 354 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 355 | } |
1da177e4 | 356 | |
1210dde7 AB |
357 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
358 | u16 value) | |
1da177e4 | 359 | { |
0638dec0 | 360 | struct net_device *const dev = bus->priv; |
1da177e4 | 361 | |
dc99839c FF |
362 | /* make sure the MAC associated with this |
363 | * mii_bus is enabled | |
364 | */ | |
365 | au1000_enable_mac(dev, 0); | |
366 | ||
1210dde7 | 367 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 368 | return 0; |
1da177e4 LT |
369 | } |
370 | ||
1210dde7 | 371 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 372 | { |
0638dec0 | 373 | struct net_device *const dev = bus->priv; |
1da177e4 | 374 | |
dc99839c FF |
375 | /* make sure the MAC associated with this |
376 | * mii_bus is enabled | |
377 | */ | |
378 | au1000_enable_mac(dev, 0); | |
379 | ||
0638dec0 HVR |
380 | return 0; |
381 | } | |
1da177e4 | 382 | |
eb049630 | 383 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
384 | { |
385 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 386 | u32 reg; |
5ef3041e | 387 | |
5368c726 | 388 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e | 389 | |
d0e7cb5d FF |
390 | reg = readl(&aup->mac->control); |
391 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
392 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
393 | wmb(); /* drain writebuffer */ |
394 | mdelay(10); | |
5ef3041e FF |
395 | } |
396 | ||
eb049630 | 397 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
398 | { |
399 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 400 | u32 reg; |
5ef3041e | 401 | |
5368c726 | 402 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e | 403 | |
d0e7cb5d FF |
404 | reg = readl(&aup->mac->control); |
405 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
406 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
407 | wmb(); /* drain writebuffer */ |
408 | mdelay(10); | |
5ef3041e FF |
409 | } |
410 | ||
411 | static void | |
412 | au1000_adjust_link(struct net_device *dev) | |
413 | { | |
414 | struct au1000_private *aup = netdev_priv(dev); | |
1e8b7389 | 415 | struct phy_device *phydev = dev->phydev; |
5ef3041e | 416 | unsigned long flags; |
d0e7cb5d | 417 | u32 reg; |
5ef3041e FF |
418 | |
419 | int status_change = 0; | |
420 | ||
1e8b7389 | 421 | BUG_ON(!phydev); |
5ef3041e FF |
422 | |
423 | spin_lock_irqsave(&aup->lock, flags); | |
424 | ||
425 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 426 | /* speed changed */ |
5ef3041e | 427 | |
2cc3c6b1 | 428 | switch (phydev->speed) { |
5ef3041e FF |
429 | case SPEED_10: |
430 | case SPEED_100: | |
431 | break; | |
432 | default: | |
5368c726 FF |
433 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
434 | phydev->speed); | |
5ef3041e FF |
435 | break; |
436 | } | |
437 | ||
438 | aup->old_speed = phydev->speed; | |
439 | ||
440 | status_change = 1; | |
441 | } | |
442 | ||
443 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 444 | /* duplex mode changed */ |
5ef3041e FF |
445 | |
446 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 447 | au1000_hard_stop(dev); |
5ef3041e | 448 | |
d0e7cb5d FF |
449 | reg = readl(&aup->mac->control); |
450 | if (DUPLEX_FULL == phydev->duplex) { | |
451 | reg |= MAC_FULL_DUPLEX; | |
452 | reg &= ~MAC_DISABLE_RX_OWN; | |
453 | } else { | |
454 | reg &= ~MAC_FULL_DUPLEX; | |
455 | reg |= MAC_DISABLE_RX_OWN; | |
456 | } | |
457 | writel(reg, &aup->mac->control); | |
2f73bfbe ML |
458 | wmb(); /* drain writebuffer */ |
459 | mdelay(1); | |
5ef3041e | 460 | |
eb049630 | 461 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
462 | aup->old_duplex = phydev->duplex; |
463 | ||
464 | status_change = 1; | |
465 | } | |
466 | ||
2cc3c6b1 FF |
467 | if (phydev->link != aup->old_link) { |
468 | /* link state changed */ | |
5ef3041e FF |
469 | |
470 | if (!phydev->link) { | |
471 | /* link went down */ | |
472 | aup->old_speed = 0; | |
473 | aup->old_duplex = -1; | |
474 | } | |
475 | ||
476 | aup->old_link = phydev->link; | |
477 | status_change = 1; | |
478 | } | |
479 | ||
480 | spin_unlock_irqrestore(&aup->lock, flags); | |
481 | ||
482 | if (status_change) { | |
483 | if (phydev->link) | |
5368c726 FF |
484 | netdev_info(dev, "link up (%d/%s)\n", |
485 | phydev->speed, | |
5ef3041e FF |
486 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
487 | else | |
5368c726 | 488 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
489 | } |
490 | } | |
491 | ||
ec7eabdd | 492 | static int au1000_mii_probe(struct net_device *dev) |
0638dec0 | 493 | { |
454d7c9b | 494 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 | 495 | struct phy_device *phydev = NULL; |
18b8e15b | 496 | int phy_addr; |
0638dec0 | 497 | |
bd2302c2 FF |
498 | if (aup->phy_static_config) { |
499 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 500 | |
bd2302c2 | 501 | if (aup->phy_addr) |
7f854420 | 502 | phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); |
bd2302c2 | 503 | else |
5368c726 | 504 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 505 | return 0; |
18b8e15b | 506 | } |
0638dec0 | 507 | |
18b8e15b | 508 | /* find the first (lowest address) PHY |
dc99839c FF |
509 | * on the current MAC's MII bus |
510 | */ | |
86c5fe4c | 511 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) |
92ca8241 ML |
512 | if (mdiobus_get_phy(aup->mii_bus, phy_addr)) { |
513 | phydev = mdiobus_get_phy(aup->mii_bus, phy_addr); | |
86c5fe4c DM |
514 | if (!aup->phy_search_highest_addr) |
515 | /* break out with first one found */ | |
516 | break; | |
517 | } | |
0638dec0 | 518 | |
18b8e15b FF |
519 | if (aup->phy1_search_mac0) { |
520 | /* try harder to find a PHY */ | |
521 | if (!phydev && (aup->mac_id == 1)) { | |
522 | /* no PHY found, maybe we have a dual PHY? */ | |
523 | dev_info(&dev->dev, ": no PHY found on MAC1, " | |
524 | "let's see if it's attached to MAC0...\n"); | |
525 | ||
526 | /* find the first (lowest address) non-attached | |
527 | * PHY on the MAC0 MII bus | |
528 | */ | |
529 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
530 | struct phy_device *const tmp_phydev = | |
7f854420 AL |
531 | mdiobus_get_phy(aup->mii_bus, |
532 | phy_addr); | |
18b8e15b FF |
533 | |
534 | if (aup->mac_id == 1) | |
535 | break; | |
536 | ||
537 | /* no PHY here... */ | |
538 | if (!tmp_phydev) | |
539 | continue; | |
540 | ||
541 | /* already claimed by MAC0 */ | |
542 | if (tmp_phydev->attached_dev) | |
543 | continue; | |
544 | ||
545 | phydev = tmp_phydev; | |
546 | break; /* found it */ | |
bd2302c2 | 547 | } |
1da177e4 LT |
548 | } |
549 | } | |
1da177e4 | 550 | |
0638dec0 | 551 | if (!phydev) { |
5368c726 | 552 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
553 | return -1; |
554 | } | |
555 | ||
0638dec0 | 556 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
557 | BUG_ON(phydev->attached_dev); |
558 | ||
84eff6d1 | 559 | phydev = phy_connect(dev, phydev_name(phydev), |
f9a8f83b | 560 | &au1000_adjust_link, PHY_INTERFACE_MODE_MII); |
0638dec0 HVR |
561 | |
562 | if (IS_ERR(phydev)) { | |
5368c726 | 563 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
564 | return PTR_ERR(phydev); |
565 | } | |
566 | ||
567 | /* mask with MAC supported features */ | |
568 | phydev->supported &= (SUPPORTED_10baseT_Half | |
569 | | SUPPORTED_10baseT_Full | |
570 | | SUPPORTED_100baseT_Half | |
571 | | SUPPORTED_100baseT_Full | |
572 | | SUPPORTED_Autoneg | |
573 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
574 | | SUPPORTED_MII | |
575 | | SUPPORTED_TP); | |
576 | ||
577 | phydev->advertising = phydev->supported; | |
578 | ||
579 | aup->old_link = 0; | |
580 | aup->old_speed = 0; | |
581 | aup->old_duplex = -1; | |
0638dec0 | 582 | |
2220943a | 583 | phy_attached_info(phydev); |
1da177e4 LT |
584 | |
585 | return 0; | |
586 | } | |
587 | ||
588 | ||
589 | /* | |
590 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 591 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
592 | * both, receive and transmit operations. |
593 | */ | |
3441592b | 594 | static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 | 595 | { |
3441592b | 596 | struct db_dest *pDB; |
1da177e4 LT |
597 | pDB = aup->pDBfree; |
598 | ||
ec7eabdd | 599 | if (pDB) |
1da177e4 | 600 | aup->pDBfree = pDB->pnext; |
ec7eabdd | 601 | |
1da177e4 LT |
602 | return pDB; |
603 | } | |
604 | ||
3441592b | 605 | void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) |
1da177e4 | 606 | { |
3441592b | 607 | struct db_dest *pDBfree = aup->pDBfree; |
1da177e4 LT |
608 | if (pDBfree) |
609 | pDBfree->pnext = pDB; | |
610 | aup->pDBfree = pDB; | |
611 | } | |
612 | ||
eb049630 | 613 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 614 | { |
454d7c9b | 615 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
616 | int i; |
617 | ||
eb049630 | 618 | au1000_hard_stop(dev); |
0638dec0 | 619 | |
462ca99c | 620 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
2f73bfbe ML |
621 | wmb(); /* drain writebuffer */ |
622 | mdelay(2); | |
462ca99c | 623 | writel(0, aup->enable); |
2f73bfbe ML |
624 | wmb(); /* drain writebuffer */ |
625 | mdelay(2); | |
0638dec0 | 626 | |
1da177e4 LT |
627 | aup->tx_full = 0; |
628 | for (i = 0; i < NUM_RX_DMA; i++) { | |
629 | /* reset control bits */ | |
630 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
631 | } | |
632 | for (i = 0; i < NUM_TX_DMA; i++) { | |
633 | /* reset control bits */ | |
634 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
635 | } | |
0638dec0 HVR |
636 | |
637 | aup->mac_enabled = 0; | |
638 | ||
1da177e4 LT |
639 | } |
640 | ||
eb049630 | 641 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 642 | { |
454d7c9b | 643 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
644 | unsigned long flags; |
645 | ||
5368c726 FF |
646 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
647 | (unsigned)aup); | |
0638dec0 HVR |
648 | |
649 | spin_lock_irqsave(&aup->lock, flags); | |
650 | ||
ec7eabdd | 651 | au1000_reset_mac_unlocked(dev); |
0638dec0 HVR |
652 | |
653 | spin_unlock_irqrestore(&aup->lock, flags); | |
654 | } | |
1da177e4 | 655 | |
6aa20a22 | 656 | /* |
1da177e4 LT |
657 | * Setup the receive and transmit "rings". These pointers are the addresses |
658 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
659 | * these are not descriptors sitting in memory. | |
660 | */ | |
6aa20a22 | 661 | static void |
553737aa | 662 | au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) |
1da177e4 LT |
663 | { |
664 | int i; | |
665 | ||
666 | for (i = 0; i < NUM_RX_DMA; i++) { | |
553737aa ML |
667 | aup->rx_dma_ring[i] = (struct rx_dma *) |
668 | (tx_base + 0x100 + sizeof(struct rx_dma) * i); | |
1da177e4 LT |
669 | } |
670 | for (i = 0; i < NUM_TX_DMA; i++) { | |
553737aa ML |
671 | aup->tx_dma_ring[i] = (struct tx_dma *) |
672 | (tx_base + sizeof(struct tx_dma) * i); | |
1da177e4 LT |
673 | } |
674 | } | |
675 | ||
0638dec0 HVR |
676 | /* |
677 | * ethtool operations | |
678 | */ | |
1da177e4 | 679 | |
1da177e4 LT |
680 | static void |
681 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
682 | { | |
454d7c9b | 683 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 684 | |
7826d43f JP |
685 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
686 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
687 | snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME, | |
688 | aup->mac_id); | |
1da177e4 LT |
689 | } |
690 | ||
7cd2e6e3 FF |
691 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
692 | { | |
693 | struct au1000_private *aup = netdev_priv(dev); | |
694 | aup->msg_enable = value; | |
695 | } | |
696 | ||
697 | static u32 au1000_get_msglevel(struct net_device *dev) | |
698 | { | |
699 | struct au1000_private *aup = netdev_priv(dev); | |
700 | return aup->msg_enable; | |
701 | } | |
702 | ||
7282d491 | 703 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 | 704 | .get_drvinfo = au1000_get_drvinfo, |
0638dec0 | 705 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
706 | .get_msglevel = au1000_get_msglevel, |
707 | .set_msglevel = au1000_set_msglevel, | |
b4cafd8c PR |
708 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
709 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
1da177e4 LT |
710 | }; |
711 | ||
5ef3041e FF |
712 | |
713 | /* | |
714 | * Initialize the interface. | |
715 | * | |
716 | * When the device powers up, the clocks are disabled and the | |
717 | * mac is in reset state. When the interface is closed, we | |
718 | * do the same -- reset the device and disable the clocks to | |
719 | * conserve power. Thus, whenever au1000_init() is called, | |
720 | * the device should already be in reset state. | |
721 | */ | |
722 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 723 | { |
5ef3041e FF |
724 | struct au1000_private *aup = netdev_priv(dev); |
725 | unsigned long flags; | |
726 | int i; | |
727 | u32 control; | |
89be0501 | 728 | |
5368c726 | 729 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 730 | |
5ef3041e | 731 | /* bring the device out of reset */ |
eb049630 | 732 | au1000_enable_mac(dev, 1); |
89be0501 | 733 | |
5ef3041e | 734 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 735 | |
d0e7cb5d | 736 | writel(0, &aup->mac->control); |
5ef3041e FF |
737 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; |
738 | aup->tx_tail = aup->tx_head; | |
739 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 740 | |
d0e7cb5d FF |
741 | writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], |
742 | &aup->mac->mac_addr_high); | |
743 | writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
744 | dev->dev_addr[1]<<8 | dev->dev_addr[0], | |
745 | &aup->mac->mac_addr_low); | |
5ef3041e | 746 | |
18b8e15b | 747 | |
ec7eabdd | 748 | for (i = 0; i < NUM_RX_DMA; i++) |
5ef3041e | 749 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
ec7eabdd | 750 | |
2f73bfbe | 751 | wmb(); /* drain writebuffer */ |
1da177e4 | 752 | |
5ef3041e FF |
753 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
754 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
755 | control |= MAC_BIG_ENDIAN; | |
756 | #endif | |
1e8b7389 PR |
757 | if (dev->phydev) { |
758 | if (dev->phydev->link && (DUPLEX_FULL == dev->phydev->duplex)) | |
5ef3041e FF |
759 | control |= MAC_FULL_DUPLEX; |
760 | else | |
761 | control |= MAC_DISABLE_RX_OWN; | |
762 | } else { /* PHY-less op, assume full-duplex */ | |
763 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
764 | } |
765 | ||
d0e7cb5d FF |
766 | writel(control, &aup->mac->control); |
767 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ | |
2f73bfbe | 768 | wmb(); /* drain writebuffer */ |
1da177e4 | 769 | |
5ef3041e FF |
770 | spin_unlock_irqrestore(&aup->lock, flags); |
771 | return 0; | |
772 | } | |
1da177e4 | 773 | |
eb049630 | 774 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 775 | { |
5ef3041e | 776 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 777 | |
5ef3041e FF |
778 | ps->rx_packets++; |
779 | if (status & RX_MCAST_FRAME) | |
780 | ps->multicast++; | |
1da177e4 | 781 | |
5ef3041e FF |
782 | if (status & RX_ERROR) { |
783 | ps->rx_errors++; | |
784 | if (status & RX_MISSED_FRAME) | |
785 | ps->rx_missed_errors++; | |
4989ccb2 | 786 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
787 | ps->rx_length_errors++; |
788 | if (status & RX_CRC_ERROR) | |
789 | ps->rx_crc_errors++; | |
790 | if (status & RX_COLL) | |
791 | ps->collisions++; | |
2cc3c6b1 | 792 | } else |
5ef3041e | 793 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 794 | |
1da177e4 LT |
795 | } |
796 | ||
6aa20a22 | 797 | /* |
5ef3041e | 798 | * Au1000 receive routine. |
1da177e4 | 799 | */ |
5ef3041e | 800 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 801 | { |
454d7c9b | 802 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 803 | struct sk_buff *skb; |
d0e7cb5d | 804 | struct rx_dma *prxd; |
5ef3041e | 805 | u32 buff_stat, status; |
3441592b | 806 | struct db_dest *pDB; |
5ef3041e | 807 | u32 frmlen; |
1da177e4 | 808 | |
5368c726 | 809 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 810 | |
5ef3041e FF |
811 | prxd = aup->rx_dma_ring[aup->rx_head]; |
812 | buff_stat = prxd->buff_stat; | |
813 | while (buff_stat & RX_T_DONE) { | |
814 | status = prxd->status; | |
815 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 816 | au1000_update_rx_stats(dev, status); |
5ef3041e | 817 | if (!(status & RX_ERROR)) { |
1da177e4 | 818 | |
5ef3041e FF |
819 | /* good frame */ |
820 | frmlen = (status & RX_FRAME_LEN_MASK); | |
821 | frmlen -= 4; /* Remove FCS */ | |
1d266430 | 822 | skb = netdev_alloc_skb(dev, frmlen + 2); |
5ef3041e | 823 | if (skb == NULL) { |
5ef3041e FF |
824 | dev->stats.rx_dropped++; |
825 | continue; | |
826 | } | |
827 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
828 | skb_copy_to_linear_data(skb, | |
829 | (unsigned char *)pDB->vaddr, frmlen); | |
830 | skb_put(skb, frmlen); | |
831 | skb->protocol = eth_type_trans(skb, dev); | |
832 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 833 | } else { |
5ef3041e | 834 | if (au1000_debug > 4) { |
215e17be | 835 | pr_err("rx_error(s):"); |
5ef3041e | 836 | if (status & RX_MISSED_FRAME) |
215e17be | 837 | pr_cont(" miss"); |
5ef3041e | 838 | if (status & RX_WDOG_TIMER) |
215e17be | 839 | pr_cont(" wdog"); |
5ef3041e | 840 | if (status & RX_RUNT) |
215e17be | 841 | pr_cont(" runt"); |
5ef3041e | 842 | if (status & RX_OVERLEN) |
215e17be | 843 | pr_cont(" overlen"); |
5ef3041e | 844 | if (status & RX_COLL) |
215e17be | 845 | pr_cont(" coll"); |
5ef3041e | 846 | if (status & RX_MII_ERROR) |
215e17be | 847 | pr_cont(" mii error"); |
5ef3041e | 848 | if (status & RX_CRC_ERROR) |
215e17be | 849 | pr_cont(" crc error"); |
5ef3041e | 850 | if (status & RX_LEN_ERROR) |
215e17be | 851 | pr_cont(" len error"); |
5ef3041e | 852 | if (status & RX_U_CNTRL_FRAME) |
215e17be FF |
853 | pr_cont(" u control frame"); |
854 | pr_cont("\n"); | |
5ef3041e FF |
855 | } |
856 | } | |
857 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
858 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
2f73bfbe | 859 | wmb(); /* drain writebuffer */ |
1da177e4 | 860 | |
5ef3041e FF |
861 | /* next descriptor */ |
862 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
863 | buff_stat = prxd->buff_stat; | |
1da177e4 | 864 | } |
1da177e4 LT |
865 | return 0; |
866 | } | |
867 | ||
eb049630 | 868 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 869 | { |
5ef3041e | 870 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 871 | |
5ef3041e | 872 | if (status & TX_FRAME_ABORTED) { |
1e8b7389 | 873 | if (!dev->phydev || (DUPLEX_FULL == dev->phydev->duplex)) { |
5ef3041e FF |
874 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { |
875 | /* any other tx errors are only valid | |
dc99839c FF |
876 | * in half duplex mode |
877 | */ | |
5ef3041e FF |
878 | ps->tx_errors++; |
879 | ps->tx_aborted_errors++; | |
880 | } | |
2cc3c6b1 | 881 | } else { |
5ef3041e FF |
882 | ps->tx_errors++; |
883 | ps->tx_aborted_errors++; | |
884 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
885 | ps->tx_carrier_errors++; | |
886 | } | |
887 | } | |
888 | } | |
0638dec0 | 889 | |
5ef3041e FF |
890 | /* |
891 | * Called from the interrupt service routine to acknowledge | |
892 | * the TX DONE bits. This is a must if the irq is setup as | |
893 | * edge triggered. | |
894 | */ | |
895 | static void au1000_tx_ack(struct net_device *dev) | |
896 | { | |
897 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 898 | struct tx_dma *ptxd; |
0638dec0 | 899 | |
5ef3041e | 900 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 901 | |
5ef3041e | 902 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 903 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
904 | ptxd->buff_stat &= ~TX_T_DONE; |
905 | ptxd->len = 0; | |
2f73bfbe | 906 | wmb(); /* drain writebuffer */ |
0638dec0 | 907 | |
5ef3041e FF |
908 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
909 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 910 | |
5ef3041e FF |
911 | if (aup->tx_full) { |
912 | aup->tx_full = 0; | |
913 | netif_wake_queue(dev); | |
914 | } | |
1da177e4 | 915 | } |
5ef3041e | 916 | } |
1da177e4 | 917 | |
5ef3041e FF |
918 | /* |
919 | * Au1000 interrupt service routine. | |
920 | */ | |
921 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
922 | { | |
923 | struct net_device *dev = dev_id; | |
1da177e4 | 924 | |
5ef3041e FF |
925 | /* Handle RX interrupts first to minimize chance of overrun */ |
926 | ||
927 | au1000_rx(dev); | |
928 | au1000_tx_ack(dev); | |
929 | return IRQ_RETVAL(1); | |
1da177e4 LT |
930 | } |
931 | ||
932 | static int au1000_open(struct net_device *dev) | |
933 | { | |
934 | int retval; | |
454d7c9b | 935 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 936 | |
5368c726 | 937 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 938 | |
2cc3c6b1 FF |
939 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
940 | dev->name, dev); | |
941 | if (retval) { | |
5368c726 | 942 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
943 | return retval; |
944 | } | |
945 | ||
2cc3c6b1 FF |
946 | retval = au1000_init(dev); |
947 | if (retval) { | |
5368c726 | 948 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
949 | free_irq(dev->irq, dev); |
950 | return retval; | |
951 | } | |
1da177e4 | 952 | |
1e8b7389 | 953 | if (dev->phydev) { |
0638dec0 | 954 | /* cause the PHY state machine to schedule a link state check */ |
1e8b7389 PR |
955 | dev->phydev->state = PHY_CHANGELINK; |
956 | phy_start(dev->phydev); | |
1da177e4 LT |
957 | } |
958 | ||
0638dec0 | 959 | netif_start_queue(dev); |
1da177e4 | 960 | |
5368c726 | 961 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
962 | |
963 | return 0; | |
964 | } | |
965 | ||
966 | static int au1000_close(struct net_device *dev) | |
967 | { | |
0638dec0 | 968 | unsigned long flags; |
454d7c9b | 969 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 970 | |
5368c726 | 971 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 972 | |
1e8b7389 PR |
973 | if (dev->phydev) |
974 | phy_stop(dev->phydev); | |
1da177e4 LT |
975 | |
976 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 977 | |
ec7eabdd | 978 | au1000_reset_mac_unlocked(dev); |
0638dec0 | 979 | |
1da177e4 LT |
980 | /* stop the device */ |
981 | netif_stop_queue(dev); | |
982 | ||
983 | /* disable the interrupt */ | |
984 | free_irq(dev->irq, dev); | |
985 | spin_unlock_irqrestore(&aup->lock, flags); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
1da177e4 LT |
990 | /* |
991 | * Au1000 transmit routine. | |
992 | */ | |
61357325 | 993 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 994 | { |
454d7c9b | 995 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 996 | struct net_device_stats *ps = &dev->stats; |
d0e7cb5d | 997 | struct tx_dma *ptxd; |
1da177e4 | 998 | u32 buff_stat; |
3441592b | 999 | struct db_dest *pDB; |
1da177e4 LT |
1000 | int i; |
1001 | ||
5368c726 FF |
1002 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
1003 | (unsigned)aup, skb->len, | |
1da177e4 LT |
1004 | skb->data, aup->tx_head); |
1005 | ||
1006 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
1007 | buff_stat = ptxd->buff_stat; | |
1008 | if (buff_stat & TX_DMA_ENABLE) { | |
1009 | /* We've wrapped around and the transmitter is still busy */ | |
1010 | netif_stop_queue(dev); | |
1011 | aup->tx_full = 1; | |
5b548140 | 1012 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 1013 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 1014 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
1015 | ptxd->len = 0; |
1016 | } | |
1017 | ||
1018 | if (aup->tx_full) { | |
1019 | aup->tx_full = 0; | |
1020 | netif_wake_queue(dev); | |
1021 | } | |
1022 | ||
1023 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 1024 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 1025 | if (skb->len < ETH_ZLEN) { |
ec7eabdd | 1026 | for (i = skb->len; i < ETH_ZLEN; i++) |
1da177e4 | 1027 | ((char *)pDB->vaddr)[i] = 0; |
ec7eabdd | 1028 | |
1da177e4 | 1029 | ptxd->len = ETH_ZLEN; |
2cc3c6b1 | 1030 | } else |
5ef3041e | 1031 | ptxd->len = skb->len; |
1da177e4 | 1032 | |
5ef3041e FF |
1033 | ps->tx_packets++; |
1034 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 1035 | |
5ef3041e | 1036 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
2f73bfbe | 1037 | wmb(); /* drain writebuffer */ |
5ef3041e FF |
1038 | dev_kfree_skb(skb); |
1039 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 1040 | return NETDEV_TX_OK; |
1da177e4 LT |
1041 | } |
1042 | ||
1da177e4 LT |
1043 | /* |
1044 | * The Tx ring has been full longer than the watchdog timeout | |
1045 | * value. The transmitter must be hung? | |
1046 | */ | |
1047 | static void au1000_tx_timeout(struct net_device *dev) | |
1048 | { | |
5368c726 | 1049 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 1050 | au1000_reset_mac(dev); |
1da177e4 | 1051 | au1000_init(dev); |
860e9538 | 1052 | netif_trans_update(dev); /* prevent tx timeout */ |
1da177e4 LT |
1053 | netif_wake_queue(dev); |
1054 | } | |
1055 | ||
d9a92cee | 1056 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 1057 | { |
454d7c9b | 1058 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d | 1059 | u32 reg; |
1da177e4 | 1060 | |
18b8e15b | 1061 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
d0e7cb5d | 1062 | reg = readl(&aup->mac->control); |
1da177e4 | 1063 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
d0e7cb5d | 1064 | reg |= MAC_PROMISCUOUS; |
1da177e4 | 1065 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1066 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
d0e7cb5d FF |
1067 | reg |= MAC_PASS_ALL_MULTI; |
1068 | reg &= ~MAC_PROMISCUOUS; | |
5368c726 | 1069 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 1070 | } else { |
22bedad3 | 1071 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1072 | u32 mc_filter[2]; /* Multicast hash filter */ |
1073 | ||
1074 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
1075 | netdev_for_each_mc_addr(ha, dev) |
1076 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 1077 | (long *)mc_filter); |
d0e7cb5d FF |
1078 | writel(mc_filter[1], &aup->mac->multi_hash_high); |
1079 | writel(mc_filter[0], &aup->mac->multi_hash_low); | |
1080 | reg &= ~MAC_PROMISCUOUS; | |
1081 | reg |= MAC_HASH_MODE; | |
1da177e4 | 1082 | } |
d0e7cb5d | 1083 | writel(reg, &aup->mac->control); |
1da177e4 LT |
1084 | } |
1085 | ||
1da177e4 LT |
1086 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1087 | { | |
2cc3c6b1 FF |
1088 | if (!netif_running(dev)) |
1089 | return -EINVAL; | |
1da177e4 | 1090 | |
1e8b7389 | 1091 | if (!dev->phydev) |
2cc3c6b1 | 1092 | return -EINVAL; /* PHY not controllable */ |
1da177e4 | 1093 | |
1e8b7389 | 1094 | return phy_mii_ioctl(dev->phydev, rq, cmd); |
1da177e4 LT |
1095 | } |
1096 | ||
d9a92cee AB |
1097 | static const struct net_device_ops au1000_netdev_ops = { |
1098 | .ndo_open = au1000_open, | |
1099 | .ndo_stop = au1000_close, | |
1100 | .ndo_start_xmit = au1000_tx, | |
afc4b13d | 1101 | .ndo_set_rx_mode = au1000_multicast_list, |
d9a92cee AB |
1102 | .ndo_do_ioctl = au1000_ioctl, |
1103 | .ndo_tx_timeout = au1000_tx_timeout, | |
1104 | .ndo_set_mac_address = eth_mac_addr, | |
1105 | .ndo_validate_addr = eth_validate_addr, | |
d9a92cee AB |
1106 | }; |
1107 | ||
0cb0568d | 1108 | static int au1000_probe(struct platform_device *pdev) |
5ef3041e | 1109 | { |
5ef3041e | 1110 | struct au1000_private *aup = NULL; |
bd2302c2 | 1111 | struct au1000_eth_platform_data *pd; |
5ef3041e | 1112 | struct net_device *dev = NULL; |
3441592b | 1113 | struct db_dest *pDB, *pDBfree; |
bd2302c2 | 1114 | int irq, i, err = 0; |
553737aa | 1115 | struct resource *base, *macen, *macdma; |
5ef3041e | 1116 | |
bd2302c2 FF |
1117 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1118 | if (!base) { | |
5368c726 | 1119 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1120 | err = -ENODEV; |
1121 | goto out; | |
1122 | } | |
5ef3041e | 1123 | |
bd2302c2 FF |
1124 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1125 | if (!macen) { | |
5368c726 | 1126 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1127 | err = -ENODEV; |
1128 | goto out; | |
1129 | } | |
5ef3041e | 1130 | |
bd2302c2 FF |
1131 | irq = platform_get_irq(pdev, 0); |
1132 | if (irq < 0) { | |
5368c726 | 1133 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1134 | err = -ENODEV; |
1135 | goto out; | |
1136 | } | |
5ef3041e | 1137 | |
553737aa ML |
1138 | macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1139 | if (!macdma) { | |
1140 | dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); | |
1141 | err = -ENODEV; | |
1142 | goto out; | |
1143 | } | |
1144 | ||
18b8e15b FF |
1145 | if (!request_mem_region(base->start, resource_size(base), |
1146 | pdev->name)) { | |
5368c726 | 1147 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1148 | err = -ENXIO; |
1149 | goto out; | |
1150 | } | |
1151 | ||
18b8e15b FF |
1152 | if (!request_mem_region(macen->start, resource_size(macen), |
1153 | pdev->name)) { | |
5368c726 | 1154 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1155 | err = -ENXIO; |
1156 | goto err_request; | |
1157 | } | |
5ef3041e | 1158 | |
553737aa ML |
1159 | if (!request_mem_region(macdma->start, resource_size(macdma), |
1160 | pdev->name)) { | |
1161 | dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); | |
1162 | err = -ENXIO; | |
1163 | goto err_macdma; | |
1164 | } | |
1165 | ||
5ef3041e FF |
1166 | dev = alloc_etherdev(sizeof(struct au1000_private)); |
1167 | if (!dev) { | |
bd2302c2 FF |
1168 | err = -ENOMEM; |
1169 | goto err_alloc; | |
5ef3041e FF |
1170 | } |
1171 | ||
bd2302c2 FF |
1172 | SET_NETDEV_DEV(dev, &pdev->dev); |
1173 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1174 | aup = netdev_priv(dev); |
1175 | ||
1176 | spin_lock_init(&aup->lock); | |
18b8e15b FF |
1177 | aup->msg_enable = (au1000_debug < 4 ? |
1178 | AU1000_DEF_MSG_ENABLE : au1000_debug); | |
5ef3041e | 1179 | |
dc99839c FF |
1180 | /* Allocate the data buffers |
1181 | * Snooping works fine with eth on all au1xxx | |
1182 | */ | |
5ef3041e FF |
1183 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * |
1184 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1185 | &aup->dma_addr, 0); | |
1186 | if (!aup->vaddr) { | |
5368c726 | 1187 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1188 | err = -ENOMEM; |
1189 | goto err_vaddr; | |
5ef3041e FF |
1190 | } |
1191 | ||
1192 | /* aup->mac is the base address of the MAC's registers */ | |
d0e7cb5d | 1193 | aup->mac = (struct mac_reg *) |
18b8e15b | 1194 | ioremap_nocache(base->start, resource_size(base)); |
bd2302c2 | 1195 | if (!aup->mac) { |
5368c726 | 1196 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1197 | err = -ENXIO; |
1198 | goto err_remap1; | |
1199 | } | |
5ef3041e | 1200 | |
ec7eabdd | 1201 | /* Setup some variables for quick register address access */ |
d0e7cb5d | 1202 | aup->enable = (u32 *)ioremap_nocache(macen->start, |
18b8e15b | 1203 | resource_size(macen)); |
bd2302c2 | 1204 | if (!aup->enable) { |
5368c726 | 1205 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1206 | err = -ENXIO; |
1207 | goto err_remap2; | |
1208 | } | |
1209 | aup->mac_id = pdev->id; | |
5ef3041e | 1210 | |
553737aa ML |
1211 | aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma)); |
1212 | if (!aup->macdma) { | |
1213 | dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); | |
1214 | err = -ENXIO; | |
1215 | goto err_remap3; | |
1216 | } | |
1217 | ||
1218 | au1000_setup_hw_rings(aup, aup->macdma); | |
5ef3041e | 1219 | |
462ca99c | 1220 | writel(0, aup->enable); |
5ef3041e FF |
1221 | aup->mac_enabled = 0; |
1222 | ||
1fc2c469 | 1223 | pd = dev_get_platdata(&pdev->dev); |
bd2302c2 | 1224 | if (!pd) { |
18b8e15b FF |
1225 | dev_info(&pdev->dev, "no platform_data passed," |
1226 | " PHY search on MAC0\n"); | |
bd2302c2 FF |
1227 | aup->phy1_search_mac0 = 1; |
1228 | } else { | |
7718f2c2 | 1229 | if (is_valid_ether_addr(pd->mac)) { |
d458cdf7 | 1230 | memcpy(dev->dev_addr, pd->mac, ETH_ALEN); |
7718f2c2 DK |
1231 | } else { |
1232 | /* Set a random MAC since no valid provided by platform_data. */ | |
1233 | eth_hw_addr_random(dev); | |
1234 | } | |
f6673653 | 1235 | |
bd2302c2 FF |
1236 | aup->phy_static_config = pd->phy_static_config; |
1237 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1238 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1239 | aup->phy_addr = pd->phy_addr; | |
1240 | aup->phy_busid = pd->phy_busid; | |
1241 | aup->phy_irq = pd->phy_irq; | |
1242 | } | |
1243 | ||
074ba1e2 | 1244 | if (aup->phy_busid > 0) { |
18b8e15b | 1245 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); |
bd2302c2 FF |
1246 | err = -ENODEV; |
1247 | goto err_mdiobus_alloc; | |
1248 | } | |
1249 | ||
5ef3041e | 1250 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1251 | if (aup->mii_bus == NULL) { |
5368c726 | 1252 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1253 | err = -ENOMEM; |
1254 | goto err_mdiobus_alloc; | |
1255 | } | |
5ef3041e FF |
1256 | |
1257 | aup->mii_bus->priv = dev; | |
1258 | aup->mii_bus->read = au1000_mdiobus_read; | |
1259 | aup->mii_bus->write = au1000_mdiobus_write; | |
1260 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1261 | aup->mii_bus->name = "au1000_eth_mii"; | |
f74299b6 FF |
1262 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1263 | pdev->name, aup->mac_id); | |
dcbfef82 | 1264 | |
5ef3041e | 1265 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1266 | if (aup->phy_static_config) |
1267 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1268 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1269 | ||
1270 | err = mdiobus_register(aup->mii_bus); | |
1271 | if (err) { | |
5368c726 | 1272 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1273 | goto err_mdiobus_reg; |
1274 | } | |
5ef3041e | 1275 | |
69129920 PST |
1276 | err = au1000_mii_probe(dev); |
1277 | if (err != 0) | |
5ef3041e | 1278 | goto err_out; |
5ef3041e FF |
1279 | |
1280 | pDBfree = NULL; | |
1281 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1282 | pDB = aup->db; | |
1283 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1284 | pDB->pnext = pDBfree; | |
1285 | pDBfree = pDB; | |
1286 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1287 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1288 | pDB++; | |
1289 | } | |
1290 | aup->pDBfree = pDBfree; | |
1291 | ||
69129920 | 1292 | err = -ENODEV; |
5ef3041e | 1293 | for (i = 0; i < NUM_RX_DMA; i++) { |
eb049630 | 1294 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1295 | if (!pDB) |
5ef3041e | 1296 | goto err_out; |
ec7eabdd | 1297 | |
5ef3041e FF |
1298 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1299 | aup->rx_db_inuse[i] = pDB; | |
1300 | } | |
69129920 PST |
1301 | |
1302 | err = -ENODEV; | |
5ef3041e | 1303 | for (i = 0; i < NUM_TX_DMA; i++) { |
eb049630 | 1304 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1305 | if (!pDB) |
5ef3041e | 1306 | goto err_out; |
ec7eabdd | 1307 | |
5ef3041e FF |
1308 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1309 | aup->tx_dma_ring[i]->len = 0; | |
1310 | aup->tx_db_inuse[i] = pDB; | |
1311 | } | |
1312 | ||
bd2302c2 FF |
1313 | dev->base_addr = base->start; |
1314 | dev->irq = irq; | |
1315 | dev->netdev_ops = &au1000_netdev_ops; | |
7ad24ea4 | 1316 | dev->ethtool_ops = &au1000_ethtool_ops; |
bd2302c2 FF |
1317 | dev->watchdog_timeo = ETH_TX_TIMEOUT; |
1318 | ||
5ef3041e FF |
1319 | /* |
1320 | * The boot code uses the ethernet controller, so reset it to start | |
1321 | * fresh. au1000_init() expects that the device is in reset state. | |
1322 | */ | |
eb049630 | 1323 | au1000_reset_mac(dev); |
5ef3041e | 1324 | |
bd2302c2 FF |
1325 | err = register_netdev(dev); |
1326 | if (err) { | |
5368c726 | 1327 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1328 | goto err_out; |
1329 | } | |
1330 | ||
5368c726 FF |
1331 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1332 | (unsigned long)base->start, irq); | |
e9c3f99f VB |
1333 | |
1334 | pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
bd2302c2 FF |
1335 | |
1336 | return 0; | |
5ef3041e FF |
1337 | |
1338 | err_out: | |
bd2302c2 | 1339 | if (aup->mii_bus != NULL) |
5ef3041e | 1340 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1341 | |
1342 | /* here we should have a valid dev plus aup-> register addresses | |
dc99839c FF |
1343 | * so we can reset the mac properly. |
1344 | */ | |
eb049630 | 1345 | au1000_reset_mac(dev); |
5ef3041e FF |
1346 | |
1347 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1348 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1349 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1350 | } |
1351 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1352 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1353 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1354 | } |
bd2302c2 FF |
1355 | err_mdiobus_reg: |
1356 | mdiobus_free(aup->mii_bus); | |
1357 | err_mdiobus_alloc: | |
553737aa ML |
1358 | iounmap(aup->macdma); |
1359 | err_remap3: | |
bd2302c2 FF |
1360 | iounmap(aup->enable); |
1361 | err_remap2: | |
1362 | iounmap(aup->mac); | |
1363 | err_remap1: | |
5ef3041e FF |
1364 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1365 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1366 | err_vaddr: |
5ef3041e | 1367 | free_netdev(dev); |
bd2302c2 | 1368 | err_alloc: |
553737aa ML |
1369 | release_mem_region(macdma->start, resource_size(macdma)); |
1370 | err_macdma: | |
bd2302c2 FF |
1371 | release_mem_region(macen->start, resource_size(macen)); |
1372 | err_request: | |
1373 | release_mem_region(base->start, resource_size(base)); | |
1374 | out: | |
1375 | return err; | |
5ef3041e FF |
1376 | } |
1377 | ||
0cb0568d | 1378 | static int au1000_remove(struct platform_device *pdev) |
5ef3041e | 1379 | { |
bd2302c2 FF |
1380 | struct net_device *dev = platform_get_drvdata(pdev); |
1381 | struct au1000_private *aup = netdev_priv(dev); | |
1382 | int i; | |
1383 | struct resource *base, *macen; | |
5ef3041e | 1384 | |
bd2302c2 FF |
1385 | unregister_netdev(dev); |
1386 | mdiobus_unregister(aup->mii_bus); | |
1387 | mdiobus_free(aup->mii_bus); | |
1388 | ||
1389 | for (i = 0; i < NUM_RX_DMA; i++) | |
1390 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1391 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1392 | |
1393 | for (i = 0; i < NUM_TX_DMA; i++) | |
1394 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1395 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1396 | |
1397 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1398 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1399 | (void *)aup->vaddr, aup->dma_addr); | |
1400 | ||
553737aa | 1401 | iounmap(aup->macdma); |
bd2302c2 FF |
1402 | iounmap(aup->mac); |
1403 | iounmap(aup->enable); | |
1404 | ||
553737aa ML |
1405 | base = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1406 | release_mem_region(base->start, resource_size(base)); | |
1407 | ||
bd2302c2 FF |
1408 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1409 | release_mem_region(base->start, resource_size(base)); | |
1410 | ||
1411 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1412 | release_mem_region(macen->start, resource_size(macen)); | |
1413 | ||
1414 | free_netdev(dev); | |
5ef3041e | 1415 | |
5ef3041e FF |
1416 | return 0; |
1417 | } | |
1418 | ||
bd2302c2 FF |
1419 | static struct platform_driver au1000_eth_driver = { |
1420 | .probe = au1000_probe, | |
0cb0568d | 1421 | .remove = au1000_remove, |
bd2302c2 FF |
1422 | .driver = { |
1423 | .name = "au1000-eth", | |
bd2302c2 FF |
1424 | }, |
1425 | }; | |
bd2302c2 | 1426 | |
db62f684 | 1427 | module_platform_driver(au1000_eth_driver); |
5ef3041e | 1428 | |
db62f684 | 1429 | MODULE_ALIAS("platform:au1000-eth"); |