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1da177e4 LT |
1 | /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ |
2 | /* | |
3 | * Copyright 1996-1999 Thomas Bogendoerfer | |
4 | * | |
5 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. | |
6 | * | |
7 | * Copyright 1993 United States Government as represented by the | |
8 | * Director, National Security Agency. | |
9 | * | |
10 | * This software may be used and distributed according to the terms | |
11 | * of the GNU General Public License, incorporated herein by reference. | |
12 | * | |
13 | * This driver is for PCnet32 and PCnetPCI based ethercards | |
14 | */ | |
15 | /************************************************************************** | |
16 | * 23 Oct, 2000. | |
17 | * Fixed a few bugs, related to running the controller in 32bit mode. | |
18 | * | |
19 | * Carsten Langgaard, carstenl@mips.com | |
20 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
21 | * | |
22 | *************************************************************************/ | |
23 | ||
13ff83b9 JP |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | ||
1da177e4 | 26 | #define DRV_NAME "pcnet32" |
01935d7d DF |
27 | #define DRV_VERSION "1.35" |
28 | #define DRV_RELDATE "21.Apr.2008" | |
1da177e4 LT |
29 | #define PFX DRV_NAME ": " |
30 | ||
4a5e8e29 JG |
31 | static const char *const version = |
32 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; | |
1da177e4 LT |
33 | |
34 | #include <linux/module.h> | |
35 | #include <linux/kernel.h> | |
d43c36dc | 36 | #include <linux/sched.h> |
1da177e4 LT |
37 | #include <linux/string.h> |
38 | #include <linux/errno.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/pci.h> | |
43 | #include <linux/delay.h> | |
44 | #include <linux/init.h> | |
45 | #include <linux/ethtool.h> | |
46 | #include <linux/mii.h> | |
47 | #include <linux/crc32.h> | |
48 | #include <linux/netdevice.h> | |
49 | #include <linux/etherdevice.h> | |
1f044931 | 50 | #include <linux/if_ether.h> |
1da177e4 LT |
51 | #include <linux/skbuff.h> |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/moduleparam.h> | |
54 | #include <linux/bitops.h> | |
9e3f8063 JP |
55 | #include <linux/io.h> |
56 | #include <linux/uaccess.h> | |
1da177e4 LT |
57 | |
58 | #include <asm/dma.h> | |
1da177e4 LT |
59 | #include <asm/irq.h> |
60 | ||
61 | /* | |
62 | * PCI device identifiers for "new style" Linux PCI Device Drivers | |
63 | */ | |
a3aa1884 | 64 | static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = { |
f2622a2b DF |
65 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, |
66 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, | |
4a5e8e29 JG |
67 | |
68 | /* | |
69 | * Adapters that were sold with IBM's RS/6000 or pSeries hardware have | |
70 | * the incorrect vendor id. | |
71 | */ | |
f2622a2b DF |
72 | { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), |
73 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, | |
4a5e8e29 JG |
74 | |
75 | { } /* terminate list */ | |
1da177e4 LT |
76 | }; |
77 | ||
4a5e8e29 | 78 | MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); |
1da177e4 LT |
79 | |
80 | static int cards_found; | |
81 | ||
82 | /* | |
83 | * VLB I/O addresses | |
84 | */ | |
aa02bc70 | 85 | static unsigned int pcnet32_portlist[] = |
4a5e8e29 | 86 | { 0x300, 0x320, 0x340, 0x360, 0 }; |
1da177e4 | 87 | |
9e3f8063 | 88 | static int pcnet32_debug; |
4a5e8e29 JG |
89 | static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ |
90 | static int pcnet32vlb; /* check for VLB cards ? */ | |
1da177e4 LT |
91 | |
92 | static struct net_device *pcnet32_dev; | |
93 | ||
94 | static int max_interrupt_work = 2; | |
95 | static int rx_copybreak = 200; | |
96 | ||
97 | #define PCNET32_PORT_AUI 0x00 | |
98 | #define PCNET32_PORT_10BT 0x01 | |
99 | #define PCNET32_PORT_GPSI 0x02 | |
100 | #define PCNET32_PORT_MII 0x03 | |
101 | ||
102 | #define PCNET32_PORT_PORTSEL 0x03 | |
103 | #define PCNET32_PORT_ASEL 0x04 | |
104 | #define PCNET32_PORT_100 0x40 | |
105 | #define PCNET32_PORT_FD 0x80 | |
106 | ||
107 | #define PCNET32_DMA_MASK 0xffffffff | |
108 | ||
109 | #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) | |
110 | #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) | |
111 | ||
112 | /* | |
113 | * table to translate option values from tulip | |
114 | * to internal options | |
115 | */ | |
f71e1309 | 116 | static const unsigned char options_mapping[] = { |
4a5e8e29 JG |
117 | PCNET32_PORT_ASEL, /* 0 Auto-select */ |
118 | PCNET32_PORT_AUI, /* 1 BNC/AUI */ | |
119 | PCNET32_PORT_AUI, /* 2 AUI/BNC */ | |
120 | PCNET32_PORT_ASEL, /* 3 not supported */ | |
121 | PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ | |
122 | PCNET32_PORT_ASEL, /* 5 not supported */ | |
123 | PCNET32_PORT_ASEL, /* 6 not supported */ | |
124 | PCNET32_PORT_ASEL, /* 7 not supported */ | |
125 | PCNET32_PORT_ASEL, /* 8 not supported */ | |
126 | PCNET32_PORT_MII, /* 9 MII 10baseT */ | |
127 | PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ | |
128 | PCNET32_PORT_MII, /* 11 MII (autosel) */ | |
129 | PCNET32_PORT_10BT, /* 12 10BaseT */ | |
130 | PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ | |
131 | /* 14 MII 100BaseTx-FD */ | |
132 | PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, | |
133 | PCNET32_PORT_ASEL /* 15 not supported */ | |
1da177e4 LT |
134 | }; |
135 | ||
136 | static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { | |
4a5e8e29 | 137 | "Loopback test (offline)" |
1da177e4 | 138 | }; |
4a5e8e29 | 139 | |
4c3616cd | 140 | #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) |
1da177e4 | 141 | |
ac62ef04 | 142 | #define PCNET32_NUM_REGS 136 |
1da177e4 | 143 | |
4a5e8e29 | 144 | #define MAX_UNITS 8 /* More are supported, limit only on options */ |
1da177e4 LT |
145 | static int options[MAX_UNITS]; |
146 | static int full_duplex[MAX_UNITS]; | |
147 | static int homepna[MAX_UNITS]; | |
148 | ||
149 | /* | |
150 | * Theory of Operation | |
151 | * | |
152 | * This driver uses the same software structure as the normal lance | |
153 | * driver. So look for a verbose description in lance.c. The differences | |
154 | * to the normal lance driver is the use of the 32bit mode of PCnet32 | |
155 | * and PCnetPCI chips. Because these chips are 32bit chips, there is no | |
156 | * 16MB limitation and we don't need bounce buffers. | |
157 | */ | |
158 | ||
1da177e4 LT |
159 | /* |
160 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
161 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
162 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
163 | */ | |
164 | #ifndef PCNET32_LOG_TX_BUFFERS | |
eabf0415 HWL |
165 | #define PCNET32_LOG_TX_BUFFERS 4 |
166 | #define PCNET32_LOG_RX_BUFFERS 5 | |
167 | #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ | |
168 | #define PCNET32_LOG_MAX_RX_BUFFERS 9 | |
1da177e4 LT |
169 | #endif |
170 | ||
171 | #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) | |
eabf0415 | 172 | #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) |
1da177e4 LT |
173 | |
174 | #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) | |
eabf0415 | 175 | #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) |
1da177e4 | 176 | |
232c5640 DF |
177 | #define PKT_BUF_SKB 1544 |
178 | /* actual buffer length after being aligned */ | |
179 | #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) | |
180 | /* chip wants twos complement of the (aligned) buffer length */ | |
181 | #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) | |
1da177e4 LT |
182 | |
183 | /* Offsets from base I/O address. */ | |
184 | #define PCNET32_WIO_RDP 0x10 | |
185 | #define PCNET32_WIO_RAP 0x12 | |
186 | #define PCNET32_WIO_RESET 0x14 | |
187 | #define PCNET32_WIO_BDP 0x16 | |
188 | ||
189 | #define PCNET32_DWIO_RDP 0x10 | |
190 | #define PCNET32_DWIO_RAP 0x14 | |
191 | #define PCNET32_DWIO_RESET 0x18 | |
192 | #define PCNET32_DWIO_BDP 0x1C | |
193 | ||
194 | #define PCNET32_TOTAL_SIZE 0x20 | |
195 | ||
06c87850 DF |
196 | #define CSR0 0 |
197 | #define CSR0_INIT 0x1 | |
198 | #define CSR0_START 0x2 | |
199 | #define CSR0_STOP 0x4 | |
200 | #define CSR0_TXPOLL 0x8 | |
201 | #define CSR0_INTEN 0x40 | |
202 | #define CSR0_IDON 0x0100 | |
203 | #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) | |
204 | #define PCNET32_INIT_LOW 1 | |
205 | #define PCNET32_INIT_HIGH 2 | |
206 | #define CSR3 3 | |
207 | #define CSR4 4 | |
208 | #define CSR5 5 | |
209 | #define CSR5_SUSPEND 0x0001 | |
210 | #define CSR15 15 | |
211 | #define PCNET32_MC_FILTER 8 | |
212 | ||
8d916266 DF |
213 | #define PCNET32_79C970A 0x2621 |
214 | ||
1da177e4 LT |
215 | /* The PCNET32 Rx and Tx ring descriptors. */ |
216 | struct pcnet32_rx_head { | |
3e33545b AV |
217 | __le32 base; |
218 | __le16 buf_length; /* two`s complement of length */ | |
219 | __le16 status; | |
220 | __le32 msg_length; | |
221 | __le32 reserved; | |
1da177e4 LT |
222 | }; |
223 | ||
224 | struct pcnet32_tx_head { | |
3e33545b AV |
225 | __le32 base; |
226 | __le16 length; /* two`s complement of length */ | |
227 | __le16 status; | |
228 | __le32 misc; | |
229 | __le32 reserved; | |
1da177e4 LT |
230 | }; |
231 | ||
232 | /* The PCNET32 32-Bit initialization block, described in databook. */ | |
233 | struct pcnet32_init_block { | |
3e33545b AV |
234 | __le16 mode; |
235 | __le16 tlen_rlen; | |
0b5bf225 | 236 | u8 phys_addr[6]; |
3e33545b AV |
237 | __le16 reserved; |
238 | __le32 filter[2]; | |
4a5e8e29 | 239 | /* Receive and transmit ring base, along with extra bits. */ |
3e33545b AV |
240 | __le32 rx_ring; |
241 | __le32 tx_ring; | |
1da177e4 LT |
242 | }; |
243 | ||
244 | /* PCnet32 access functions */ | |
245 | struct pcnet32_access { | |
4a5e8e29 JG |
246 | u16 (*read_csr) (unsigned long, int); |
247 | void (*write_csr) (unsigned long, int, u16); | |
248 | u16 (*read_bcr) (unsigned long, int); | |
249 | void (*write_bcr) (unsigned long, int, u16); | |
250 | u16 (*read_rap) (unsigned long); | |
251 | void (*write_rap) (unsigned long, u16); | |
252 | void (*reset) (unsigned long); | |
1da177e4 LT |
253 | }; |
254 | ||
255 | /* | |
76209926 HWL |
256 | * The first field of pcnet32_private is read by the ethernet device |
257 | * so the structure should be allocated using pci_alloc_consistent(). | |
1da177e4 LT |
258 | */ |
259 | struct pcnet32_private { | |
6ecb7667 | 260 | struct pcnet32_init_block *init_block; |
4a5e8e29 | 261 | /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ |
0b5bf225 JG |
262 | struct pcnet32_rx_head *rx_ring; |
263 | struct pcnet32_tx_head *tx_ring; | |
6ecb7667 DF |
264 | dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, |
265 | returned by pci_alloc_consistent */ | |
0b5bf225 JG |
266 | struct pci_dev *pci_dev; |
267 | const char *name; | |
4a5e8e29 | 268 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
0b5bf225 JG |
269 | struct sk_buff **tx_skbuff; |
270 | struct sk_buff **rx_skbuff; | |
271 | dma_addr_t *tx_dma_addr; | |
272 | dma_addr_t *rx_dma_addr; | |
1d70cb06 | 273 | const struct pcnet32_access *a; |
0b5bf225 JG |
274 | spinlock_t lock; /* Guard lock */ |
275 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
276 | unsigned int rx_ring_size; /* current rx ring size */ | |
277 | unsigned int tx_ring_size; /* current tx ring size */ | |
278 | unsigned int rx_mod_mask; /* rx ring modular mask */ | |
279 | unsigned int tx_mod_mask; /* tx ring modular mask */ | |
280 | unsigned short rx_len_bits; | |
281 | unsigned short tx_len_bits; | |
282 | dma_addr_t rx_ring_dma_addr; | |
283 | dma_addr_t tx_ring_dma_addr; | |
284 | unsigned int dirty_rx, /* ring entries to be freed. */ | |
285 | dirty_tx; | |
286 | ||
bea3348e SH |
287 | struct net_device *dev; |
288 | struct napi_struct napi; | |
0b5bf225 JG |
289 | char tx_full; |
290 | char phycount; /* number of phys found */ | |
291 | int options; | |
292 | unsigned int shared_irq:1, /* shared irq possible */ | |
293 | dxsuflo:1, /* disable transmit stop on uflo */ | |
294 | mii:1; /* mii port available */ | |
295 | struct net_device *next; | |
296 | struct mii_if_info mii_if; | |
297 | struct timer_list watchdog_timer; | |
0b5bf225 | 298 | u32 msg_enable; /* debug message level */ |
4a5e8e29 JG |
299 | |
300 | /* each bit indicates an available PHY */ | |
0b5bf225 | 301 | u32 phymask; |
8d916266 | 302 | unsigned short chip_version; /* which variant this is */ |
9871acf6 | 303 | |
304 | /* saved registers during ethtool blink */ | |
305 | u16 save_regs[4]; | |
1da177e4 LT |
306 | }; |
307 | ||
4a5e8e29 JG |
308 | static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); |
309 | static int pcnet32_probe1(unsigned long, int, struct pci_dev *); | |
310 | static int pcnet32_open(struct net_device *); | |
311 | static int pcnet32_init_ring(struct net_device *); | |
61357325 SH |
312 | static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, |
313 | struct net_device *); | |
4a5e8e29 | 314 | static void pcnet32_tx_timeout(struct net_device *dev); |
7d12e780 | 315 | static irqreturn_t pcnet32_interrupt(int, void *); |
4a5e8e29 | 316 | static int pcnet32_close(struct net_device *); |
1da177e4 LT |
317 | static struct net_device_stats *pcnet32_get_stats(struct net_device *); |
318 | static void pcnet32_load_multicast(struct net_device *dev); | |
319 | static void pcnet32_set_multicast_list(struct net_device *); | |
4a5e8e29 | 320 | static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); |
1da177e4 LT |
321 | static void pcnet32_watchdog(struct net_device *); |
322 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num); | |
4a5e8e29 JG |
323 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, |
324 | int val); | |
1da177e4 LT |
325 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); |
326 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 JG |
327 | struct ethtool_test *eth_test, u64 * data); |
328 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); | |
1da177e4 LT |
329 | static int pcnet32_get_regs_len(struct net_device *dev); |
330 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 331 | void *ptr); |
1bcd3153 | 332 | static void pcnet32_purge_tx_ring(struct net_device *dev); |
b166cfba | 333 | static int pcnet32_alloc_ring(struct net_device *dev, const char *name); |
eabf0415 | 334 | static void pcnet32_free_ring(struct net_device *dev); |
ac62ef04 | 335 | static void pcnet32_check_media(struct net_device *dev, int verbose); |
eabf0415 | 336 | |
4a5e8e29 | 337 | static u16 pcnet32_wio_read_csr(unsigned long addr, int index) |
1da177e4 | 338 | { |
4a5e8e29 JG |
339 | outw(index, addr + PCNET32_WIO_RAP); |
340 | return inw(addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
341 | } |
342 | ||
4a5e8e29 | 343 | static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 344 | { |
4a5e8e29 JG |
345 | outw(index, addr + PCNET32_WIO_RAP); |
346 | outw(val, addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
347 | } |
348 | ||
4a5e8e29 | 349 | static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) |
1da177e4 | 350 | { |
4a5e8e29 JG |
351 | outw(index, addr + PCNET32_WIO_RAP); |
352 | return inw(addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
353 | } |
354 | ||
4a5e8e29 | 355 | static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 356 | { |
4a5e8e29 JG |
357 | outw(index, addr + PCNET32_WIO_RAP); |
358 | outw(val, addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
359 | } |
360 | ||
4a5e8e29 | 361 | static u16 pcnet32_wio_read_rap(unsigned long addr) |
1da177e4 | 362 | { |
4a5e8e29 | 363 | return inw(addr + PCNET32_WIO_RAP); |
1da177e4 LT |
364 | } |
365 | ||
4a5e8e29 | 366 | static void pcnet32_wio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 367 | { |
4a5e8e29 | 368 | outw(val, addr + PCNET32_WIO_RAP); |
1da177e4 LT |
369 | } |
370 | ||
4a5e8e29 | 371 | static void pcnet32_wio_reset(unsigned long addr) |
1da177e4 | 372 | { |
4a5e8e29 | 373 | inw(addr + PCNET32_WIO_RESET); |
1da177e4 LT |
374 | } |
375 | ||
4a5e8e29 | 376 | static int pcnet32_wio_check(unsigned long addr) |
1da177e4 | 377 | { |
4a5e8e29 | 378 | outw(88, addr + PCNET32_WIO_RAP); |
807540ba | 379 | return inw(addr + PCNET32_WIO_RAP) == 88; |
1da177e4 LT |
380 | } |
381 | ||
1d70cb06 | 382 | static const struct pcnet32_access pcnet32_wio = { |
4a5e8e29 JG |
383 | .read_csr = pcnet32_wio_read_csr, |
384 | .write_csr = pcnet32_wio_write_csr, | |
385 | .read_bcr = pcnet32_wio_read_bcr, | |
386 | .write_bcr = pcnet32_wio_write_bcr, | |
387 | .read_rap = pcnet32_wio_read_rap, | |
388 | .write_rap = pcnet32_wio_write_rap, | |
389 | .reset = pcnet32_wio_reset | |
1da177e4 LT |
390 | }; |
391 | ||
4a5e8e29 | 392 | static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) |
1da177e4 | 393 | { |
4a5e8e29 | 394 | outl(index, addr + PCNET32_DWIO_RAP); |
9e3f8063 | 395 | return inl(addr + PCNET32_DWIO_RDP) & 0xffff; |
1da177e4 LT |
396 | } |
397 | ||
4a5e8e29 | 398 | static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 399 | { |
4a5e8e29 JG |
400 | outl(index, addr + PCNET32_DWIO_RAP); |
401 | outl(val, addr + PCNET32_DWIO_RDP); | |
1da177e4 LT |
402 | } |
403 | ||
4a5e8e29 | 404 | static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) |
1da177e4 | 405 | { |
4a5e8e29 | 406 | outl(index, addr + PCNET32_DWIO_RAP); |
9e3f8063 | 407 | return inl(addr + PCNET32_DWIO_BDP) & 0xffff; |
1da177e4 LT |
408 | } |
409 | ||
4a5e8e29 | 410 | static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 411 | { |
4a5e8e29 JG |
412 | outl(index, addr + PCNET32_DWIO_RAP); |
413 | outl(val, addr + PCNET32_DWIO_BDP); | |
1da177e4 LT |
414 | } |
415 | ||
4a5e8e29 | 416 | static u16 pcnet32_dwio_read_rap(unsigned long addr) |
1da177e4 | 417 | { |
9e3f8063 | 418 | return inl(addr + PCNET32_DWIO_RAP) & 0xffff; |
1da177e4 LT |
419 | } |
420 | ||
4a5e8e29 | 421 | static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 422 | { |
4a5e8e29 | 423 | outl(val, addr + PCNET32_DWIO_RAP); |
1da177e4 LT |
424 | } |
425 | ||
4a5e8e29 | 426 | static void pcnet32_dwio_reset(unsigned long addr) |
1da177e4 | 427 | { |
4a5e8e29 | 428 | inl(addr + PCNET32_DWIO_RESET); |
1da177e4 LT |
429 | } |
430 | ||
4a5e8e29 | 431 | static int pcnet32_dwio_check(unsigned long addr) |
1da177e4 | 432 | { |
4a5e8e29 | 433 | outl(88, addr + PCNET32_DWIO_RAP); |
807540ba | 434 | return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; |
1da177e4 LT |
435 | } |
436 | ||
1d70cb06 | 437 | static const struct pcnet32_access pcnet32_dwio = { |
4a5e8e29 JG |
438 | .read_csr = pcnet32_dwio_read_csr, |
439 | .write_csr = pcnet32_dwio_write_csr, | |
440 | .read_bcr = pcnet32_dwio_read_bcr, | |
441 | .write_bcr = pcnet32_dwio_write_bcr, | |
442 | .read_rap = pcnet32_dwio_read_rap, | |
443 | .write_rap = pcnet32_dwio_write_rap, | |
444 | .reset = pcnet32_dwio_reset | |
1da177e4 LT |
445 | }; |
446 | ||
06c87850 DF |
447 | static void pcnet32_netif_stop(struct net_device *dev) |
448 | { | |
bea3348e | 449 | struct pcnet32_private *lp = netdev_priv(dev); |
01935d7d | 450 | |
1ae5dc34 | 451 | dev->trans_start = jiffies; /* prevent tx timeout */ |
bea3348e | 452 | napi_disable(&lp->napi); |
06c87850 DF |
453 | netif_tx_disable(dev); |
454 | } | |
455 | ||
456 | static void pcnet32_netif_start(struct net_device *dev) | |
457 | { | |
bea3348e | 458 | struct pcnet32_private *lp = netdev_priv(dev); |
d1d08d12 DM |
459 | ulong ioaddr = dev->base_addr; |
460 | u16 val; | |
01935d7d | 461 | |
06c87850 | 462 | netif_wake_queue(dev); |
1d70cb06 | 463 | val = lp->a->read_csr(ioaddr, CSR3); |
d1d08d12 | 464 | val &= 0x00ff; |
1d70cb06 | 465 | lp->a->write_csr(ioaddr, CSR3, val); |
bea3348e | 466 | napi_enable(&lp->napi); |
06c87850 DF |
467 | } |
468 | ||
469 | /* | |
470 | * Allocate space for the new sized tx ring. | |
471 | * Free old resources | |
472 | * Save new resources. | |
473 | * Any failure keeps old resources. | |
474 | * Must be called with lp->lock held. | |
475 | */ | |
476 | static void pcnet32_realloc_tx_ring(struct net_device *dev, | |
477 | struct pcnet32_private *lp, | |
478 | unsigned int size) | |
479 | { | |
480 | dma_addr_t new_ring_dma_addr; | |
481 | dma_addr_t *new_dma_addr_list; | |
482 | struct pcnet32_tx_head *new_tx_ring; | |
483 | struct sk_buff **new_skb_list; | |
484 | ||
485 | pcnet32_purge_tx_ring(dev); | |
486 | ||
487 | new_tx_ring = pci_alloc_consistent(lp->pci_dev, | |
488 | sizeof(struct pcnet32_tx_head) * | |
489 | (1 << size), | |
490 | &new_ring_dma_addr); | |
491 | if (new_tx_ring == NULL) { | |
13ff83b9 | 492 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
06c87850 DF |
493 | return; |
494 | } | |
495 | memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size)); | |
496 | ||
497 | new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), | |
498 | GFP_ATOMIC); | |
499 | if (!new_dma_addr_list) { | |
13ff83b9 | 500 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
06c87850 DF |
501 | goto free_new_tx_ring; |
502 | } | |
503 | ||
504 | new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), | |
505 | GFP_ATOMIC); | |
506 | if (!new_skb_list) { | |
13ff83b9 | 507 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
06c87850 DF |
508 | goto free_new_lists; |
509 | } | |
510 | ||
511 | kfree(lp->tx_skbuff); | |
512 | kfree(lp->tx_dma_addr); | |
513 | pci_free_consistent(lp->pci_dev, | |
514 | sizeof(struct pcnet32_tx_head) * | |
515 | lp->tx_ring_size, lp->tx_ring, | |
516 | lp->tx_ring_dma_addr); | |
517 | ||
518 | lp->tx_ring_size = (1 << size); | |
519 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
520 | lp->tx_len_bits = (size << 12); | |
521 | lp->tx_ring = new_tx_ring; | |
522 | lp->tx_ring_dma_addr = new_ring_dma_addr; | |
523 | lp->tx_dma_addr = new_dma_addr_list; | |
524 | lp->tx_skbuff = new_skb_list; | |
525 | return; | |
526 | ||
9e3f8063 | 527 | free_new_lists: |
06c87850 | 528 | kfree(new_dma_addr_list); |
9e3f8063 | 529 | free_new_tx_ring: |
06c87850 DF |
530 | pci_free_consistent(lp->pci_dev, |
531 | sizeof(struct pcnet32_tx_head) * | |
532 | (1 << size), | |
533 | new_tx_ring, | |
534 | new_ring_dma_addr); | |
06c87850 DF |
535 | } |
536 | ||
537 | /* | |
538 | * Allocate space for the new sized rx ring. | |
539 | * Re-use old receive buffers. | |
540 | * alloc extra buffers | |
541 | * free unneeded buffers | |
542 | * free unneeded buffers | |
543 | * Save new resources. | |
544 | * Any failure keeps old resources. | |
545 | * Must be called with lp->lock held. | |
546 | */ | |
547 | static void pcnet32_realloc_rx_ring(struct net_device *dev, | |
548 | struct pcnet32_private *lp, | |
549 | unsigned int size) | |
550 | { | |
551 | dma_addr_t new_ring_dma_addr; | |
552 | dma_addr_t *new_dma_addr_list; | |
553 | struct pcnet32_rx_head *new_rx_ring; | |
554 | struct sk_buff **new_skb_list; | |
555 | int new, overlap; | |
556 | ||
557 | new_rx_ring = pci_alloc_consistent(lp->pci_dev, | |
558 | sizeof(struct pcnet32_rx_head) * | |
559 | (1 << size), | |
560 | &new_ring_dma_addr); | |
561 | if (new_rx_ring == NULL) { | |
13ff83b9 | 562 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
06c87850 DF |
563 | return; |
564 | } | |
565 | memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size)); | |
566 | ||
567 | new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t), | |
568 | GFP_ATOMIC); | |
569 | if (!new_dma_addr_list) { | |
13ff83b9 | 570 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
06c87850 DF |
571 | goto free_new_rx_ring; |
572 | } | |
573 | ||
574 | new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *), | |
575 | GFP_ATOMIC); | |
576 | if (!new_skb_list) { | |
13ff83b9 | 577 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
06c87850 DF |
578 | goto free_new_lists; |
579 | } | |
580 | ||
581 | /* first copy the current receive buffers */ | |
582 | overlap = min(size, lp->rx_ring_size); | |
583 | for (new = 0; new < overlap; new++) { | |
584 | new_rx_ring[new] = lp->rx_ring[new]; | |
585 | new_dma_addr_list[new] = lp->rx_dma_addr[new]; | |
586 | new_skb_list[new] = lp->rx_skbuff[new]; | |
587 | } | |
588 | /* now allocate any new buffers needed */ | |
9e3f8063 | 589 | for (; new < size; new++) { |
06c87850 | 590 | struct sk_buff *rx_skbuff; |
232c5640 | 591 | new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB); |
9e3f8063 JP |
592 | rx_skbuff = new_skb_list[new]; |
593 | if (!rx_skbuff) { | |
06c87850 | 594 | /* keep the original lists and buffers */ |
13ff83b9 JP |
595 | netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", |
596 | __func__); | |
06c87850 DF |
597 | goto free_all_new; |
598 | } | |
232c5640 | 599 | skb_reserve(rx_skbuff, NET_IP_ALIGN); |
06c87850 DF |
600 | |
601 | new_dma_addr_list[new] = | |
602 | pci_map_single(lp->pci_dev, rx_skbuff->data, | |
232c5640 | 603 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
3e33545b | 604 | new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); |
232c5640 | 605 | new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); |
3e33545b | 606 | new_rx_ring[new].status = cpu_to_le16(0x8000); |
06c87850 DF |
607 | } |
608 | /* and free any unneeded buffers */ | |
609 | for (; new < lp->rx_ring_size; new++) { | |
610 | if (lp->rx_skbuff[new]) { | |
611 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new], | |
232c5640 | 612 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
06c87850 DF |
613 | dev_kfree_skb(lp->rx_skbuff[new]); |
614 | } | |
615 | } | |
616 | ||
617 | kfree(lp->rx_skbuff); | |
618 | kfree(lp->rx_dma_addr); | |
619 | pci_free_consistent(lp->pci_dev, | |
620 | sizeof(struct pcnet32_rx_head) * | |
621 | lp->rx_ring_size, lp->rx_ring, | |
622 | lp->rx_ring_dma_addr); | |
623 | ||
624 | lp->rx_ring_size = (1 << size); | |
625 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
626 | lp->rx_len_bits = (size << 4); | |
627 | lp->rx_ring = new_rx_ring; | |
628 | lp->rx_ring_dma_addr = new_ring_dma_addr; | |
629 | lp->rx_dma_addr = new_dma_addr_list; | |
630 | lp->rx_skbuff = new_skb_list; | |
631 | return; | |
632 | ||
9e3f8063 JP |
633 | free_all_new: |
634 | while (--new >= lp->rx_ring_size) { | |
06c87850 DF |
635 | if (new_skb_list[new]) { |
636 | pci_unmap_single(lp->pci_dev, new_dma_addr_list[new], | |
232c5640 | 637 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
06c87850 DF |
638 | dev_kfree_skb(new_skb_list[new]); |
639 | } | |
640 | } | |
641 | kfree(new_skb_list); | |
9e3f8063 | 642 | free_new_lists: |
06c87850 | 643 | kfree(new_dma_addr_list); |
9e3f8063 | 644 | free_new_rx_ring: |
06c87850 DF |
645 | pci_free_consistent(lp->pci_dev, |
646 | sizeof(struct pcnet32_rx_head) * | |
647 | (1 << size), | |
648 | new_rx_ring, | |
649 | new_ring_dma_addr); | |
06c87850 DF |
650 | } |
651 | ||
ac5bfe40 DF |
652 | static void pcnet32_purge_rx_ring(struct net_device *dev) |
653 | { | |
1e56a4b4 | 654 | struct pcnet32_private *lp = netdev_priv(dev); |
ac5bfe40 DF |
655 | int i; |
656 | ||
657 | /* free all allocated skbuffs */ | |
658 | for (i = 0; i < lp->rx_ring_size; i++) { | |
659 | lp->rx_ring[i].status = 0; /* CPU owns buffer */ | |
660 | wmb(); /* Make sure adapter sees owner change */ | |
661 | if (lp->rx_skbuff[i]) { | |
662 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], | |
232c5640 | 663 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
ac5bfe40 DF |
664 | dev_kfree_skb_any(lp->rx_skbuff[i]); |
665 | } | |
666 | lp->rx_skbuff[i] = NULL; | |
667 | lp->rx_dma_addr[i] = 0; | |
668 | } | |
669 | } | |
670 | ||
1da177e4 LT |
671 | #ifdef CONFIG_NET_POLL_CONTROLLER |
672 | static void pcnet32_poll_controller(struct net_device *dev) | |
673 | { | |
4a5e8e29 | 674 | disable_irq(dev->irq); |
7d12e780 | 675 | pcnet32_interrupt(0, dev); |
4a5e8e29 | 676 | enable_irq(dev->irq); |
1da177e4 LT |
677 | } |
678 | #endif | |
679 | ||
1da177e4 LT |
680 | static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
681 | { | |
1e56a4b4 | 682 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
683 | unsigned long flags; |
684 | int r = -EOPNOTSUPP; | |
1da177e4 | 685 | |
4a5e8e29 JG |
686 | if (lp->mii) { |
687 | spin_lock_irqsave(&lp->lock, flags); | |
688 | mii_ethtool_gset(&lp->mii_if, cmd); | |
689 | spin_unlock_irqrestore(&lp->lock, flags); | |
690 | r = 0; | |
691 | } | |
692 | return r; | |
1da177e4 LT |
693 | } |
694 | ||
695 | static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
696 | { | |
1e56a4b4 | 697 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
698 | unsigned long flags; |
699 | int r = -EOPNOTSUPP; | |
1da177e4 | 700 | |
4a5e8e29 JG |
701 | if (lp->mii) { |
702 | spin_lock_irqsave(&lp->lock, flags); | |
703 | r = mii_ethtool_sset(&lp->mii_if, cmd); | |
704 | spin_unlock_irqrestore(&lp->lock, flags); | |
705 | } | |
706 | return r; | |
1da177e4 LT |
707 | } |
708 | ||
4a5e8e29 JG |
709 | static void pcnet32_get_drvinfo(struct net_device *dev, |
710 | struct ethtool_drvinfo *info) | |
1da177e4 | 711 | { |
1e56a4b4 | 712 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 713 | |
23020ab3 RJ |
714 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
715 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
4a5e8e29 | 716 | if (lp->pci_dev) |
23020ab3 RJ |
717 | strlcpy(info->bus_info, pci_name(lp->pci_dev), |
718 | sizeof(info->bus_info)); | |
4a5e8e29 | 719 | else |
23020ab3 RJ |
720 | snprintf(info->bus_info, sizeof(info->bus_info), |
721 | "VLB 0x%lx", dev->base_addr); | |
1da177e4 LT |
722 | } |
723 | ||
724 | static u32 pcnet32_get_link(struct net_device *dev) | |
725 | { | |
1e56a4b4 | 726 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
727 | unsigned long flags; |
728 | int r; | |
1da177e4 | 729 | |
4a5e8e29 JG |
730 | spin_lock_irqsave(&lp->lock, flags); |
731 | if (lp->mii) { | |
732 | r = mii_link_ok(&lp->mii_if); | |
8d916266 | 733 | } else if (lp->chip_version >= PCNET32_79C970A) { |
4a5e8e29 | 734 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
1d70cb06 | 735 | r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); |
8d916266 DF |
736 | } else { /* can not detect link on really old chips */ |
737 | r = 1; | |
4a5e8e29 JG |
738 | } |
739 | spin_unlock_irqrestore(&lp->lock, flags); | |
740 | ||
741 | return r; | |
1da177e4 LT |
742 | } |
743 | ||
744 | static u32 pcnet32_get_msglevel(struct net_device *dev) | |
745 | { | |
1e56a4b4 | 746 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 747 | return lp->msg_enable; |
1da177e4 LT |
748 | } |
749 | ||
750 | static void pcnet32_set_msglevel(struct net_device *dev, u32 value) | |
751 | { | |
1e56a4b4 | 752 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 753 | lp->msg_enable = value; |
1da177e4 LT |
754 | } |
755 | ||
756 | static int pcnet32_nway_reset(struct net_device *dev) | |
757 | { | |
1e56a4b4 | 758 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
759 | unsigned long flags; |
760 | int r = -EOPNOTSUPP; | |
1da177e4 | 761 | |
4a5e8e29 JG |
762 | if (lp->mii) { |
763 | spin_lock_irqsave(&lp->lock, flags); | |
764 | r = mii_nway_restart(&lp->mii_if); | |
765 | spin_unlock_irqrestore(&lp->lock, flags); | |
766 | } | |
767 | return r; | |
1da177e4 LT |
768 | } |
769 | ||
4a5e8e29 JG |
770 | static void pcnet32_get_ringparam(struct net_device *dev, |
771 | struct ethtool_ringparam *ering) | |
1da177e4 | 772 | { |
1e56a4b4 | 773 | struct pcnet32_private *lp = netdev_priv(dev); |
1da177e4 | 774 | |
6dcd60c2 DF |
775 | ering->tx_max_pending = TX_MAX_RING_SIZE; |
776 | ering->tx_pending = lp->tx_ring_size; | |
777 | ering->rx_max_pending = RX_MAX_RING_SIZE; | |
778 | ering->rx_pending = lp->rx_ring_size; | |
eabf0415 HWL |
779 | } |
780 | ||
4a5e8e29 JG |
781 | static int pcnet32_set_ringparam(struct net_device *dev, |
782 | struct ethtool_ringparam *ering) | |
eabf0415 | 783 | { |
1e56a4b4 | 784 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 785 | unsigned long flags; |
06c87850 DF |
786 | unsigned int size; |
787 | ulong ioaddr = dev->base_addr; | |
4a5e8e29 JG |
788 | int i; |
789 | ||
790 | if (ering->rx_mini_pending || ering->rx_jumbo_pending) | |
791 | return -EINVAL; | |
792 | ||
793 | if (netif_running(dev)) | |
06c87850 | 794 | pcnet32_netif_stop(dev); |
4a5e8e29 JG |
795 | |
796 | spin_lock_irqsave(&lp->lock, flags); | |
1d70cb06 | 797 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ |
06c87850 DF |
798 | |
799 | size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); | |
4a5e8e29 JG |
800 | |
801 | /* set the minimum ring size to 4, to allow the loopback test to work | |
802 | * unchanged. | |
803 | */ | |
804 | for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { | |
06c87850 | 805 | if (size <= (1 << i)) |
4a5e8e29 JG |
806 | break; |
807 | } | |
06c87850 DF |
808 | if ((1 << i) != lp->tx_ring_size) |
809 | pcnet32_realloc_tx_ring(dev, lp, i); | |
b368a3fb | 810 | |
06c87850 | 811 | size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); |
4a5e8e29 | 812 | for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { |
06c87850 | 813 | if (size <= (1 << i)) |
4a5e8e29 JG |
814 | break; |
815 | } | |
06c87850 DF |
816 | if ((1 << i) != lp->rx_ring_size) |
817 | pcnet32_realloc_rx_ring(dev, lp, i); | |
b368a3fb | 818 | |
bea3348e | 819 | lp->napi.weight = lp->rx_ring_size / 2; |
06c87850 DF |
820 | |
821 | if (netif_running(dev)) { | |
822 | pcnet32_netif_start(dev); | |
823 | pcnet32_restart(dev, CSR0_NORMAL); | |
4a5e8e29 | 824 | } |
eabf0415 | 825 | |
4a5e8e29 | 826 | spin_unlock_irqrestore(&lp->lock, flags); |
eabf0415 | 827 | |
13ff83b9 JP |
828 | netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", |
829 | lp->rx_ring_size, lp->tx_ring_size); | |
eabf0415 | 830 | |
4a5e8e29 | 831 | return 0; |
1da177e4 LT |
832 | } |
833 | ||
4a5e8e29 | 834 | static void pcnet32_get_strings(struct net_device *dev, u32 stringset, |
9e3f8063 | 835 | u8 *data) |
1da177e4 | 836 | { |
4a5e8e29 | 837 | memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); |
1da177e4 LT |
838 | } |
839 | ||
b9f2c044 | 840 | static int pcnet32_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 841 | { |
b9f2c044 JG |
842 | switch (sset) { |
843 | case ETH_SS_TEST: | |
844 | return PCNET32_TEST_LEN; | |
845 | default: | |
846 | return -EOPNOTSUPP; | |
847 | } | |
1da177e4 LT |
848 | } |
849 | ||
850 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 | 851 | struct ethtool_test *test, u64 * data) |
1da177e4 | 852 | { |
1e56a4b4 | 853 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
854 | int rc; |
855 | ||
856 | if (test->flags == ETH_TEST_FL_OFFLINE) { | |
857 | rc = pcnet32_loopback_test(dev, data); | |
858 | if (rc) { | |
13ff83b9 JP |
859 | netif_printk(lp, hw, KERN_DEBUG, dev, |
860 | "Loopback test failed\n"); | |
4a5e8e29 | 861 | test->flags |= ETH_TEST_FL_FAILED; |
13ff83b9 JP |
862 | } else |
863 | netif_printk(lp, hw, KERN_DEBUG, dev, | |
864 | "Loopback test passed\n"); | |
865 | } else | |
866 | netif_printk(lp, hw, KERN_DEBUG, dev, | |
867 | "No tests to run (specify 'Offline' on ethtool)\n"); | |
4a5e8e29 | 868 | } /* end pcnet32_ethtool_test */ |
1da177e4 | 869 | |
4a5e8e29 | 870 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) |
1da177e4 | 871 | { |
1e56a4b4 | 872 | struct pcnet32_private *lp = netdev_priv(dev); |
1d70cb06 | 873 | const struct pcnet32_access *a = lp->a; /* access to registers */ |
4a5e8e29 JG |
874 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
875 | struct sk_buff *skb; /* sk buff */ | |
876 | int x, i; /* counters */ | |
877 | int numbuffs = 4; /* number of TX/RX buffers and descs */ | |
878 | u16 status = 0x8300; /* TX ring status */ | |
3e33545b | 879 | __le16 teststatus; /* test of ring status */ |
4a5e8e29 JG |
880 | int rc; /* return code */ |
881 | int size; /* size of packets */ | |
882 | unsigned char *packet; /* source packet data */ | |
883 | static const int data_len = 60; /* length of source packets */ | |
884 | unsigned long flags; | |
885 | unsigned long ticks; | |
886 | ||
4a5e8e29 JG |
887 | rc = 1; /* default to fail */ |
888 | ||
889 | if (netif_running(dev)) | |
7de745e5 | 890 | pcnet32_netif_stop(dev); |
4a5e8e29 JG |
891 | |
892 | spin_lock_irqsave(&lp->lock, flags); | |
1d70cb06 | 893 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ |
ac5bfe40 DF |
894 | |
895 | numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); | |
4a5e8e29 JG |
896 | |
897 | /* Reset the PCNET32 */ | |
1d70cb06 | 898 | lp->a->reset(ioaddr); |
899 | lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ | |
4a5e8e29 JG |
900 | |
901 | /* switch pcnet32 to 32bit mode */ | |
1d70cb06 | 902 | lp->a->write_bcr(ioaddr, 20, 2); |
4a5e8e29 | 903 | |
4a5e8e29 JG |
904 | /* purge & init rings but don't actually restart */ |
905 | pcnet32_restart(dev, 0x0000); | |
906 | ||
1d70cb06 | 907 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ |
4a5e8e29 JG |
908 | |
909 | /* Initialize Transmit buffers. */ | |
910 | size = data_len + 15; | |
911 | for (x = 0; x < numbuffs; x++) { | |
9e3f8063 JP |
912 | skb = dev_alloc_skb(size); |
913 | if (!skb) { | |
13ff83b9 JP |
914 | netif_printk(lp, hw, KERN_DEBUG, dev, |
915 | "Cannot allocate skb at line: %d!\n", | |
916 | __LINE__); | |
4a5e8e29 | 917 | goto clean_up; |
4a5e8e29 | 918 | } |
9e3f8063 JP |
919 | packet = skb->data; |
920 | skb_put(skb, size); /* create space for data */ | |
921 | lp->tx_skbuff[x] = skb; | |
922 | lp->tx_ring[x].length = cpu_to_le16(-skb->len); | |
923 | lp->tx_ring[x].misc = 0; | |
924 | ||
925 | /* put DA and SA into the skb */ | |
926 | for (i = 0; i < 6; i++) | |
927 | *packet++ = dev->dev_addr[i]; | |
928 | for (i = 0; i < 6; i++) | |
929 | *packet++ = dev->dev_addr[i]; | |
930 | /* type */ | |
931 | *packet++ = 0x08; | |
932 | *packet++ = 0x06; | |
933 | /* packet number */ | |
934 | *packet++ = x; | |
935 | /* fill packet with data */ | |
936 | for (i = 0; i < data_len; i++) | |
937 | *packet++ = i; | |
938 | ||
939 | lp->tx_dma_addr[x] = | |
940 | pci_map_single(lp->pci_dev, skb->data, skb->len, | |
941 | PCI_DMA_TODEVICE); | |
942 | lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); | |
943 | wmb(); /* Make sure owner changes after all others are visible */ | |
944 | lp->tx_ring[x].status = cpu_to_le16(status); | |
1da177e4 | 945 | } |
1da177e4 | 946 | |
ac5bfe40 DF |
947 | x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ |
948 | a->write_bcr(ioaddr, 32, x | 0x0002); | |
4a5e8e29 | 949 | |
ac5bfe40 DF |
950 | /* set int loopback in CSR15 */ |
951 | x = a->read_csr(ioaddr, CSR15) & 0xfffc; | |
1d70cb06 | 952 | lp->a->write_csr(ioaddr, CSR15, x | 0x0044); |
4a5e8e29 | 953 | |
3e33545b | 954 | teststatus = cpu_to_le16(0x8000); |
1d70cb06 | 955 | lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ |
4a5e8e29 JG |
956 | |
957 | /* Check status of descriptors */ | |
958 | for (x = 0; x < numbuffs; x++) { | |
959 | ticks = 0; | |
960 | rmb(); | |
961 | while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { | |
962 | spin_unlock_irqrestore(&lp->lock, flags); | |
ac5bfe40 | 963 | msleep(1); |
4a5e8e29 JG |
964 | spin_lock_irqsave(&lp->lock, flags); |
965 | rmb(); | |
966 | ticks++; | |
967 | } | |
968 | if (ticks == 200) { | |
13ff83b9 | 969 | netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); |
4a5e8e29 JG |
970 | break; |
971 | } | |
972 | } | |
973 | ||
1d70cb06 | 974 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ |
4a5e8e29 JG |
975 | wmb(); |
976 | if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { | |
13ff83b9 | 977 | netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); |
4a5e8e29 JG |
978 | |
979 | for (x = 0; x < numbuffs; x++) { | |
13ff83b9 | 980 | netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); |
4a5e8e29 | 981 | skb = lp->rx_skbuff[x]; |
9e3f8063 | 982 | for (i = 0; i < size; i++) |
13ff83b9 | 983 | pr_cont(" %02x", *(skb->data + i)); |
13ff83b9 | 984 | pr_cont("\n"); |
4a5e8e29 JG |
985 | } |
986 | } | |
1da177e4 | 987 | |
4a5e8e29 JG |
988 | x = 0; |
989 | rc = 0; | |
990 | while (x < numbuffs && !rc) { | |
991 | skb = lp->rx_skbuff[x]; | |
992 | packet = lp->tx_skbuff[x]->data; | |
993 | for (i = 0; i < size; i++) { | |
994 | if (*(skb->data + i) != packet[i]) { | |
13ff83b9 JP |
995 | netif_printk(lp, hw, KERN_DEBUG, dev, |
996 | "Error in compare! %2x - %02x %02x\n", | |
997 | i, *(skb->data + i), packet[i]); | |
4a5e8e29 JG |
998 | rc = 1; |
999 | break; | |
1000 | } | |
1001 | } | |
1002 | x++; | |
1003 | } | |
1da177e4 | 1004 | |
9e3f8063 | 1005 | clean_up: |
ac5bfe40 | 1006 | *data1 = rc; |
4a5e8e29 | 1007 | pcnet32_purge_tx_ring(dev); |
1da177e4 | 1008 | |
ac5bfe40 DF |
1009 | x = a->read_csr(ioaddr, CSR15); |
1010 | a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ | |
1da177e4 | 1011 | |
ac5bfe40 DF |
1012 | x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ |
1013 | a->write_bcr(ioaddr, 32, (x & ~0x0002)); | |
4a5e8e29 | 1014 | |
7de745e5 DF |
1015 | if (netif_running(dev)) { |
1016 | pcnet32_netif_start(dev); | |
1017 | pcnet32_restart(dev, CSR0_NORMAL); | |
1018 | } else { | |
1019 | pcnet32_purge_rx_ring(dev); | |
1d70cb06 | 1020 | lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ |
7de745e5 DF |
1021 | } |
1022 | spin_unlock_irqrestore(&lp->lock, flags); | |
4a5e8e29 | 1023 | |
9e3f8063 | 1024 | return rc; |
4a5e8e29 | 1025 | } /* end pcnet32_loopback_test */ |
1da177e4 | 1026 | |
9871acf6 | 1027 | static int pcnet32_set_phys_id(struct net_device *dev, |
1028 | enum ethtool_phys_id_state state) | |
1da177e4 | 1029 | { |
1e56a4b4 | 1030 | struct pcnet32_private *lp = netdev_priv(dev); |
1d70cb06 | 1031 | const struct pcnet32_access *a = lp->a; |
4a5e8e29 JG |
1032 | ulong ioaddr = dev->base_addr; |
1033 | unsigned long flags; | |
1034 | int i; | |
1035 | ||
9871acf6 | 1036 | switch (state) { |
1037 | case ETHTOOL_ID_ACTIVE: | |
1038 | /* Save the current value of the bcrs */ | |
1039 | spin_lock_irqsave(&lp->lock, flags); | |
1040 | for (i = 4; i < 8; i++) | |
1041 | lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); | |
1042 | spin_unlock_irqrestore(&lp->lock, flags); | |
fce55922 | 1043 | return 2; /* cycle on/off twice per second */ |
1da177e4 | 1044 | |
9871acf6 | 1045 | case ETHTOOL_ID_ON: |
1046 | case ETHTOOL_ID_OFF: | |
1047 | /* Blink the led */ | |
1048 | spin_lock_irqsave(&lp->lock, flags); | |
1049 | for (i = 4; i < 8; i++) | |
1050 | a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); | |
1051 | spin_unlock_irqrestore(&lp->lock, flags); | |
1052 | break; | |
4a5e8e29 | 1053 | |
9871acf6 | 1054 | case ETHTOOL_ID_INACTIVE: |
1055 | /* Restore the original value of the bcrs */ | |
1056 | spin_lock_irqsave(&lp->lock, flags); | |
1057 | for (i = 4; i < 8; i++) | |
1058 | a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); | |
1059 | spin_unlock_irqrestore(&lp->lock, flags); | |
4a5e8e29 | 1060 | } |
4a5e8e29 | 1061 | return 0; |
1da177e4 LT |
1062 | } |
1063 | ||
df27f4a6 DF |
1064 | /* |
1065 | * lp->lock must be held. | |
1066 | */ | |
1067 | static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, | |
1068 | int can_sleep) | |
1069 | { | |
1070 | int csr5; | |
1e56a4b4 | 1071 | struct pcnet32_private *lp = netdev_priv(dev); |
1d70cb06 | 1072 | const struct pcnet32_access *a = lp->a; |
df27f4a6 DF |
1073 | ulong ioaddr = dev->base_addr; |
1074 | int ticks; | |
1075 | ||
8d916266 DF |
1076 | /* really old chips have to be stopped. */ |
1077 | if (lp->chip_version < PCNET32_79C970A) | |
1078 | return 0; | |
1079 | ||
df27f4a6 DF |
1080 | /* set SUSPEND (SPND) - CSR5 bit 0 */ |
1081 | csr5 = a->read_csr(ioaddr, CSR5); | |
1082 | a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); | |
1083 | ||
1084 | /* poll waiting for bit to be set */ | |
1085 | ticks = 0; | |
1086 | while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { | |
1087 | spin_unlock_irqrestore(&lp->lock, *flags); | |
1088 | if (can_sleep) | |
1089 | msleep(1); | |
1090 | else | |
1091 | mdelay(1); | |
1092 | spin_lock_irqsave(&lp->lock, *flags); | |
1093 | ticks++; | |
1094 | if (ticks > 200) { | |
13ff83b9 JP |
1095 | netif_printk(lp, hw, KERN_DEBUG, dev, |
1096 | "Error getting into suspend!\n"); | |
df27f4a6 DF |
1097 | return 0; |
1098 | } | |
1099 | } | |
1100 | return 1; | |
1101 | } | |
1102 | ||
3904c324 DF |
1103 | /* |
1104 | * process one receive descriptor entry | |
1105 | */ | |
1106 | ||
1107 | static void pcnet32_rx_entry(struct net_device *dev, | |
1108 | struct pcnet32_private *lp, | |
1109 | struct pcnet32_rx_head *rxp, | |
1110 | int entry) | |
1111 | { | |
1112 | int status = (short)le16_to_cpu(rxp->status) >> 8; | |
1113 | int rx_in_place = 0; | |
1114 | struct sk_buff *skb; | |
1115 | short pkt_len; | |
1116 | ||
1117 | if (status != 0x03) { /* There was an error. */ | |
1118 | /* | |
1119 | * There is a tricky error noted by John Murphy, | |
1120 | * <murf@perftech.com> to Russ Nelson: Even with full-sized | |
1121 | * buffers it's possible for a jabber packet to use two | |
1122 | * buffers, with only the last correctly noting the error. | |
1123 | */ | |
1124 | if (status & 0x01) /* Only count a general error at the */ | |
4f1e5ba0 | 1125 | dev->stats.rx_errors++; /* end of a packet. */ |
3904c324 | 1126 | if (status & 0x20) |
4f1e5ba0 | 1127 | dev->stats.rx_frame_errors++; |
3904c324 | 1128 | if (status & 0x10) |
4f1e5ba0 | 1129 | dev->stats.rx_over_errors++; |
3904c324 | 1130 | if (status & 0x08) |
4f1e5ba0 | 1131 | dev->stats.rx_crc_errors++; |
3904c324 | 1132 | if (status & 0x04) |
4f1e5ba0 | 1133 | dev->stats.rx_fifo_errors++; |
3904c324 DF |
1134 | return; |
1135 | } | |
1136 | ||
1137 | pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; | |
1138 | ||
1139 | /* Discard oversize frames. */ | |
232c5640 | 1140 | if (unlikely(pkt_len > PKT_BUF_SIZE)) { |
13ff83b9 JP |
1141 | netif_err(lp, drv, dev, "Impossible packet size %d!\n", |
1142 | pkt_len); | |
4f1e5ba0 | 1143 | dev->stats.rx_errors++; |
3904c324 DF |
1144 | return; |
1145 | } | |
1146 | if (pkt_len < 60) { | |
13ff83b9 | 1147 | netif_err(lp, rx_err, dev, "Runt packet!\n"); |
4f1e5ba0 | 1148 | dev->stats.rx_errors++; |
3904c324 DF |
1149 | return; |
1150 | } | |
1151 | ||
1152 | if (pkt_len > rx_copybreak) { | |
1153 | struct sk_buff *newskb; | |
1154 | ||
9e3f8063 JP |
1155 | newskb = dev_alloc_skb(PKT_BUF_SKB); |
1156 | if (newskb) { | |
232c5640 | 1157 | skb_reserve(newskb, NET_IP_ALIGN); |
3904c324 DF |
1158 | skb = lp->rx_skbuff[entry]; |
1159 | pci_unmap_single(lp->pci_dev, | |
1160 | lp->rx_dma_addr[entry], | |
232c5640 | 1161 | PKT_BUF_SIZE, |
3904c324 DF |
1162 | PCI_DMA_FROMDEVICE); |
1163 | skb_put(skb, pkt_len); | |
1164 | lp->rx_skbuff[entry] = newskb; | |
3904c324 DF |
1165 | lp->rx_dma_addr[entry] = |
1166 | pci_map_single(lp->pci_dev, | |
1167 | newskb->data, | |
232c5640 | 1168 | PKT_BUF_SIZE, |
3904c324 | 1169 | PCI_DMA_FROMDEVICE); |
3e33545b | 1170 | rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]); |
3904c324 DF |
1171 | rx_in_place = 1; |
1172 | } else | |
1173 | skb = NULL; | |
9e3f8063 | 1174 | } else |
232c5640 | 1175 | skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN); |
3904c324 DF |
1176 | |
1177 | if (skb == NULL) { | |
13ff83b9 | 1178 | netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); |
4f1e5ba0 | 1179 | dev->stats.rx_dropped++; |
3904c324 DF |
1180 | return; |
1181 | } | |
3904c324 | 1182 | if (!rx_in_place) { |
232c5640 | 1183 | skb_reserve(skb, NET_IP_ALIGN); |
3904c324 DF |
1184 | skb_put(skb, pkt_len); /* Make room */ |
1185 | pci_dma_sync_single_for_cpu(lp->pci_dev, | |
1186 | lp->rx_dma_addr[entry], | |
b2cbbd8e | 1187 | pkt_len, |
3904c324 | 1188 | PCI_DMA_FROMDEVICE); |
8c7b7faa | 1189 | skb_copy_to_linear_data(skb, |
3904c324 | 1190 | (unsigned char *)(lp->rx_skbuff[entry]->data), |
8c7b7faa | 1191 | pkt_len); |
3904c324 DF |
1192 | pci_dma_sync_single_for_device(lp->pci_dev, |
1193 | lp->rx_dma_addr[entry], | |
b2cbbd8e | 1194 | pkt_len, |
3904c324 DF |
1195 | PCI_DMA_FROMDEVICE); |
1196 | } | |
4f1e5ba0 | 1197 | dev->stats.rx_bytes += skb->len; |
3904c324 | 1198 | skb->protocol = eth_type_trans(skb, dev); |
7de745e5 | 1199 | netif_receive_skb(skb); |
4f1e5ba0 | 1200 | dev->stats.rx_packets++; |
3904c324 DF |
1201 | } |
1202 | ||
bea3348e | 1203 | static int pcnet32_rx(struct net_device *dev, int budget) |
9691edd2 | 1204 | { |
1e56a4b4 | 1205 | struct pcnet32_private *lp = netdev_priv(dev); |
9691edd2 | 1206 | int entry = lp->cur_rx & lp->rx_mod_mask; |
3904c324 DF |
1207 | struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; |
1208 | int npackets = 0; | |
9691edd2 DF |
1209 | |
1210 | /* If we own the next entry, it's a new packet. Send it up. */ | |
bea3348e | 1211 | while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { |
3904c324 DF |
1212 | pcnet32_rx_entry(dev, lp, rxp, entry); |
1213 | npackets += 1; | |
9691edd2 | 1214 | /* |
3904c324 DF |
1215 | * The docs say that the buffer length isn't touched, but Andrew |
1216 | * Boyd of QNX reports that some revs of the 79C965 clear it. | |
9691edd2 | 1217 | */ |
232c5640 | 1218 | rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); |
3904c324 | 1219 | wmb(); /* Make sure owner changes after others are visible */ |
3e33545b | 1220 | rxp->status = cpu_to_le16(0x8000); |
9691edd2 | 1221 | entry = (++lp->cur_rx) & lp->rx_mod_mask; |
3904c324 | 1222 | rxp = &lp->rx_ring[entry]; |
9691edd2 DF |
1223 | } |
1224 | ||
7de745e5 | 1225 | return npackets; |
9691edd2 DF |
1226 | } |
1227 | ||
7de745e5 | 1228 | static int pcnet32_tx(struct net_device *dev) |
9691edd2 | 1229 | { |
1e56a4b4 | 1230 | struct pcnet32_private *lp = netdev_priv(dev); |
9691edd2 DF |
1231 | unsigned int dirty_tx = lp->dirty_tx; |
1232 | int delta; | |
1233 | int must_restart = 0; | |
1234 | ||
1235 | while (dirty_tx != lp->cur_tx) { | |
1236 | int entry = dirty_tx & lp->tx_mod_mask; | |
1237 | int status = (short)le16_to_cpu(lp->tx_ring[entry].status); | |
1238 | ||
1239 | if (status < 0) | |
1240 | break; /* It still hasn't been Txed */ | |
1241 | ||
1242 | lp->tx_ring[entry].base = 0; | |
1243 | ||
1244 | if (status & 0x4000) { | |
3904c324 | 1245 | /* There was a major error, log it. */ |
9691edd2 | 1246 | int err_status = le32_to_cpu(lp->tx_ring[entry].misc); |
4f1e5ba0 | 1247 | dev->stats.tx_errors++; |
13ff83b9 JP |
1248 | netif_err(lp, tx_err, dev, |
1249 | "Tx error status=%04x err_status=%08x\n", | |
1250 | status, err_status); | |
9691edd2 | 1251 | if (err_status & 0x04000000) |
4f1e5ba0 | 1252 | dev->stats.tx_aborted_errors++; |
9691edd2 | 1253 | if (err_status & 0x08000000) |
4f1e5ba0 | 1254 | dev->stats.tx_carrier_errors++; |
9691edd2 | 1255 | if (err_status & 0x10000000) |
4f1e5ba0 | 1256 | dev->stats.tx_window_errors++; |
9691edd2 DF |
1257 | #ifndef DO_DXSUFLO |
1258 | if (err_status & 0x40000000) { | |
4f1e5ba0 | 1259 | dev->stats.tx_fifo_errors++; |
9691edd2 DF |
1260 | /* Ackk! On FIFO errors the Tx unit is turned off! */ |
1261 | /* Remove this verbosity later! */ | |
13ff83b9 | 1262 | netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); |
9691edd2 DF |
1263 | must_restart = 1; |
1264 | } | |
1265 | #else | |
1266 | if (err_status & 0x40000000) { | |
4f1e5ba0 | 1267 | dev->stats.tx_fifo_errors++; |
9691edd2 DF |
1268 | if (!lp->dxsuflo) { /* If controller doesn't recover ... */ |
1269 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
1270 | /* Remove this verbosity later! */ | |
13ff83b9 | 1271 | netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); |
9691edd2 DF |
1272 | must_restart = 1; |
1273 | } | |
1274 | } | |
1275 | #endif | |
1276 | } else { | |
1277 | if (status & 0x1800) | |
4f1e5ba0 DF |
1278 | dev->stats.collisions++; |
1279 | dev->stats.tx_packets++; | |
9691edd2 DF |
1280 | } |
1281 | ||
1282 | /* We must free the original skb */ | |
1283 | if (lp->tx_skbuff[entry]) { | |
1284 | pci_unmap_single(lp->pci_dev, | |
1285 | lp->tx_dma_addr[entry], | |
1286 | lp->tx_skbuff[entry]-> | |
1287 | len, PCI_DMA_TODEVICE); | |
3904c324 | 1288 | dev_kfree_skb_any(lp->tx_skbuff[entry]); |
9691edd2 DF |
1289 | lp->tx_skbuff[entry] = NULL; |
1290 | lp->tx_dma_addr[entry] = 0; | |
1291 | } | |
1292 | dirty_tx++; | |
1293 | } | |
1294 | ||
3904c324 | 1295 | delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); |
9691edd2 | 1296 | if (delta > lp->tx_ring_size) { |
13ff83b9 JP |
1297 | netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", |
1298 | dirty_tx, lp->cur_tx, lp->tx_full); | |
9691edd2 DF |
1299 | dirty_tx += lp->tx_ring_size; |
1300 | delta -= lp->tx_ring_size; | |
1301 | } | |
1302 | ||
1303 | if (lp->tx_full && | |
1304 | netif_queue_stopped(dev) && | |
1305 | delta < lp->tx_ring_size - 2) { | |
1306 | /* The ring is no longer full, clear tbusy. */ | |
1307 | lp->tx_full = 0; | |
1308 | netif_wake_queue(dev); | |
1309 | } | |
1310 | lp->dirty_tx = dirty_tx; | |
1311 | ||
1312 | return must_restart; | |
1313 | } | |
1314 | ||
bea3348e | 1315 | static int pcnet32_poll(struct napi_struct *napi, int budget) |
7de745e5 | 1316 | { |
bea3348e SH |
1317 | struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); |
1318 | struct net_device *dev = lp->dev; | |
7de745e5 DF |
1319 | unsigned long ioaddr = dev->base_addr; |
1320 | unsigned long flags; | |
bea3348e | 1321 | int work_done; |
7de745e5 DF |
1322 | u16 val; |
1323 | ||
bea3348e | 1324 | work_done = pcnet32_rx(dev, budget); |
7de745e5 DF |
1325 | |
1326 | spin_lock_irqsave(&lp->lock, flags); | |
1327 | if (pcnet32_tx(dev)) { | |
1328 | /* reset the chip to clear the error condition, then restart */ | |
1d70cb06 | 1329 | lp->a->reset(ioaddr); |
1330 | lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ | |
7de745e5 DF |
1331 | pcnet32_restart(dev, CSR0_START); |
1332 | netif_wake_queue(dev); | |
1333 | } | |
1334 | spin_unlock_irqrestore(&lp->lock, flags); | |
1335 | ||
bea3348e SH |
1336 | if (work_done < budget) { |
1337 | spin_lock_irqsave(&lp->lock, flags); | |
7de745e5 | 1338 | |
288379f0 | 1339 | __napi_complete(napi); |
7de745e5 | 1340 | |
bea3348e | 1341 | /* clear interrupt masks */ |
1d70cb06 | 1342 | val = lp->a->read_csr(ioaddr, CSR3); |
bea3348e | 1343 | val &= 0x00ff; |
1d70cb06 | 1344 | lp->a->write_csr(ioaddr, CSR3, val); |
7de745e5 | 1345 | |
bea3348e | 1346 | /* Set interrupt enable. */ |
1d70cb06 | 1347 | lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); |
ce105a08 | 1348 | |
bea3348e SH |
1349 | spin_unlock_irqrestore(&lp->lock, flags); |
1350 | } | |
1351 | return work_done; | |
7de745e5 | 1352 | } |
7de745e5 | 1353 | |
ac62ef04 DF |
1354 | #define PCNET32_REGS_PER_PHY 32 |
1355 | #define PCNET32_MAX_PHYS 32 | |
1da177e4 LT |
1356 | static int pcnet32_get_regs_len(struct net_device *dev) |
1357 | { | |
1e56a4b4 | 1358 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 1359 | int j = lp->phycount * PCNET32_REGS_PER_PHY; |
ac62ef04 | 1360 | |
9e3f8063 | 1361 | return (PCNET32_NUM_REGS + j) * sizeof(u16); |
1da177e4 LT |
1362 | } |
1363 | ||
1364 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 1365 | void *ptr) |
1da177e4 | 1366 | { |
4a5e8e29 JG |
1367 | int i, csr0; |
1368 | u16 *buff = ptr; | |
1e56a4b4 | 1369 | struct pcnet32_private *lp = netdev_priv(dev); |
1d70cb06 | 1370 | const struct pcnet32_access *a = lp->a; |
4a5e8e29 | 1371 | ulong ioaddr = dev->base_addr; |
4a5e8e29 JG |
1372 | unsigned long flags; |
1373 | ||
1374 | spin_lock_irqsave(&lp->lock, flags); | |
1375 | ||
df27f4a6 DF |
1376 | csr0 = a->read_csr(ioaddr, CSR0); |
1377 | if (!(csr0 & CSR0_STOP)) /* If not stopped */ | |
1378 | pcnet32_suspend(dev, &flags, 1); | |
1da177e4 | 1379 | |
4a5e8e29 JG |
1380 | /* read address PROM */ |
1381 | for (i = 0; i < 16; i += 2) | |
1382 | *buff++ = inw(ioaddr + i); | |
1383 | ||
1384 | /* read control and status registers */ | |
9e3f8063 | 1385 | for (i = 0; i < 90; i++) |
4a5e8e29 | 1386 | *buff++ = a->read_csr(ioaddr, i); |
4a5e8e29 JG |
1387 | |
1388 | *buff++ = a->read_csr(ioaddr, 112); | |
1389 | *buff++ = a->read_csr(ioaddr, 114); | |
1da177e4 | 1390 | |
4a5e8e29 | 1391 | /* read bus configuration registers */ |
9e3f8063 | 1392 | for (i = 0; i < 30; i++) |
4a5e8e29 | 1393 | *buff++ = a->read_bcr(ioaddr, i); |
9e3f8063 | 1394 | |
4a5e8e29 | 1395 | *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ |
9e3f8063 JP |
1396 | |
1397 | for (i = 31; i < 36; i++) | |
4a5e8e29 | 1398 | *buff++ = a->read_bcr(ioaddr, i); |
4a5e8e29 JG |
1399 | |
1400 | /* read mii phy registers */ | |
1401 | if (lp->mii) { | |
1402 | int j; | |
1403 | for (j = 0; j < PCNET32_MAX_PHYS; j++) { | |
1404 | if (lp->phymask & (1 << j)) { | |
1405 | for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { | |
1d70cb06 | 1406 | lp->a->write_bcr(ioaddr, 33, |
4a5e8e29 | 1407 | (j << 5) | i); |
1d70cb06 | 1408 | *buff++ = lp->a->read_bcr(ioaddr, 34); |
4a5e8e29 JG |
1409 | } |
1410 | } | |
1411 | } | |
1412 | } | |
1413 | ||
df27f4a6 DF |
1414 | if (!(csr0 & CSR0_STOP)) { /* If not stopped */ |
1415 | int csr5; | |
1416 | ||
4a5e8e29 | 1417 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ |
df27f4a6 DF |
1418 | csr5 = a->read_csr(ioaddr, CSR5); |
1419 | a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); | |
4a5e8e29 JG |
1420 | } |
1421 | ||
1422 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
1423 | } |
1424 | ||
7282d491 | 1425 | static const struct ethtool_ops pcnet32_ethtool_ops = { |
4a5e8e29 JG |
1426 | .get_settings = pcnet32_get_settings, |
1427 | .set_settings = pcnet32_set_settings, | |
1428 | .get_drvinfo = pcnet32_get_drvinfo, | |
1429 | .get_msglevel = pcnet32_get_msglevel, | |
1430 | .set_msglevel = pcnet32_set_msglevel, | |
1431 | .nway_reset = pcnet32_nway_reset, | |
1432 | .get_link = pcnet32_get_link, | |
1433 | .get_ringparam = pcnet32_get_ringparam, | |
1434 | .set_ringparam = pcnet32_set_ringparam, | |
4a5e8e29 | 1435 | .get_strings = pcnet32_get_strings, |
4a5e8e29 | 1436 | .self_test = pcnet32_ethtool_test, |
9871acf6 | 1437 | .set_phys_id = pcnet32_set_phys_id, |
4a5e8e29 JG |
1438 | .get_regs_len = pcnet32_get_regs_len, |
1439 | .get_regs = pcnet32_get_regs, | |
b9f2c044 | 1440 | .get_sset_count = pcnet32_get_sset_count, |
1da177e4 LT |
1441 | }; |
1442 | ||
1443 | /* only probes for non-PCI devices, the rest are handled by | |
1444 | * pci_register_driver via pcnet32_probe_pci */ | |
1445 | ||
dcaf9769 | 1446 | static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) |
1da177e4 | 1447 | { |
4a5e8e29 JG |
1448 | unsigned int *port, ioaddr; |
1449 | ||
1450 | /* search for PCnet32 VLB cards at known addresses */ | |
1451 | for (port = pcnet32_portlist; (ioaddr = *port); port++) { | |
1452 | if (request_region | |
1453 | (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { | |
1454 | /* check if there is really a pcnet chip on that ioaddr */ | |
8e95a202 JP |
1455 | if ((inb(ioaddr + 14) == 0x57) && |
1456 | (inb(ioaddr + 15) == 0x57)) { | |
4a5e8e29 JG |
1457 | pcnet32_probe1(ioaddr, 0, NULL); |
1458 | } else { | |
1459 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
1460 | } | |
1461 | } | |
1462 | } | |
1da177e4 LT |
1463 | } |
1464 | ||
1da177e4 LT |
1465 | static int __devinit |
1466 | pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1467 | { | |
4a5e8e29 JG |
1468 | unsigned long ioaddr; |
1469 | int err; | |
1470 | ||
1471 | err = pci_enable_device(pdev); | |
1472 | if (err < 0) { | |
1473 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1474 | pr_err("failed to enable device -- err=%d\n", err); |
4a5e8e29 JG |
1475 | return err; |
1476 | } | |
1477 | pci_set_master(pdev); | |
1478 | ||
1479 | ioaddr = pci_resource_start(pdev, 0); | |
1480 | if (!ioaddr) { | |
1481 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1482 | pr_err("card has no PCI IO resources, aborting\n"); |
4a5e8e29 JG |
1483 | return -ENODEV; |
1484 | } | |
1da177e4 | 1485 | |
4a5e8e29 JG |
1486 | if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { |
1487 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1488 | pr_err("architecture does not support 32bit PCI busmaster DMA\n"); |
4a5e8e29 JG |
1489 | return -ENODEV; |
1490 | } | |
9e3f8063 | 1491 | if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { |
4a5e8e29 | 1492 | if (pcnet32_debug & NETIF_MSG_PROBE) |
13ff83b9 | 1493 | pr_err("io address range already allocated\n"); |
4a5e8e29 JG |
1494 | return -EBUSY; |
1495 | } | |
1da177e4 | 1496 | |
4a5e8e29 | 1497 | err = pcnet32_probe1(ioaddr, 1, pdev); |
9e3f8063 | 1498 | if (err < 0) |
4a5e8e29 | 1499 | pci_disable_device(pdev); |
9e3f8063 | 1500 | |
4a5e8e29 | 1501 | return err; |
1da177e4 LT |
1502 | } |
1503 | ||
3bc124dd SH |
1504 | static const struct net_device_ops pcnet32_netdev_ops = { |
1505 | .ndo_open = pcnet32_open, | |
1506 | .ndo_stop = pcnet32_close, | |
1507 | .ndo_start_xmit = pcnet32_start_xmit, | |
1508 | .ndo_tx_timeout = pcnet32_tx_timeout, | |
1509 | .ndo_get_stats = pcnet32_get_stats, | |
afc4b13d | 1510 | .ndo_set_rx_mode = pcnet32_set_multicast_list, |
3bc124dd SH |
1511 | .ndo_do_ioctl = pcnet32_ioctl, |
1512 | .ndo_change_mtu = eth_change_mtu, | |
1513 | .ndo_set_mac_address = eth_mac_addr, | |
1514 | .ndo_validate_addr = eth_validate_addr, | |
1515 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1516 | .ndo_poll_controller = pcnet32_poll_controller, | |
1517 | #endif | |
1518 | }; | |
1519 | ||
1da177e4 LT |
1520 | /* pcnet32_probe1 |
1521 | * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. | |
1522 | * pdev will be NULL when called from pcnet32_probe_vlbus. | |
1523 | */ | |
1524 | static int __devinit | |
1525 | pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) | |
1526 | { | |
4a5e8e29 | 1527 | struct pcnet32_private *lp; |
4a5e8e29 JG |
1528 | int i, media; |
1529 | int fdx, mii, fset, dxsuflo; | |
1530 | int chip_version; | |
1531 | char *chipname; | |
1532 | struct net_device *dev; | |
1d70cb06 | 1533 | const struct pcnet32_access *a = NULL; |
4a5e8e29 JG |
1534 | u8 promaddr[6]; |
1535 | int ret = -ENODEV; | |
1536 | ||
1537 | /* reset the chip */ | |
1538 | pcnet32_wio_reset(ioaddr); | |
1539 | ||
1540 | /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ | |
1541 | if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { | |
1542 | a = &pcnet32_wio; | |
1543 | } else { | |
1544 | pcnet32_dwio_reset(ioaddr); | |
8e95a202 JP |
1545 | if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && |
1546 | pcnet32_dwio_check(ioaddr)) { | |
4a5e8e29 | 1547 | a = &pcnet32_dwio; |
df4e7f72 DF |
1548 | } else { |
1549 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1550 | pr_err("No access methods\n"); |
4a5e8e29 | 1551 | goto err_release_region; |
df4e7f72 | 1552 | } |
4a5e8e29 JG |
1553 | } |
1554 | ||
1555 | chip_version = | |
1556 | a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); | |
1557 | if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) | |
13ff83b9 | 1558 | pr_info(" PCnet chip version is %#x\n", chip_version); |
4a5e8e29 JG |
1559 | if ((chip_version & 0xfff) != 0x003) { |
1560 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1561 | pr_info("Unsupported chip version\n"); |
4a5e8e29 JG |
1562 | goto err_release_region; |
1563 | } | |
1564 | ||
1565 | /* initialize variables */ | |
1566 | fdx = mii = fset = dxsuflo = 0; | |
1567 | chip_version = (chip_version >> 12) & 0xffff; | |
1568 | ||
1569 | switch (chip_version) { | |
1570 | case 0x2420: | |
1571 | chipname = "PCnet/PCI 79C970"; /* PCI */ | |
1572 | break; | |
1573 | case 0x2430: | |
1574 | if (shared) | |
1575 | chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ | |
1576 | else | |
1577 | chipname = "PCnet/32 79C965"; /* 486/VL bus */ | |
1578 | break; | |
1579 | case 0x2621: | |
1580 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
1581 | fdx = 1; | |
1582 | break; | |
1583 | case 0x2623: | |
1584 | chipname = "PCnet/FAST 79C971"; /* PCI */ | |
1585 | fdx = 1; | |
1586 | mii = 1; | |
1587 | fset = 1; | |
1588 | break; | |
1589 | case 0x2624: | |
1590 | chipname = "PCnet/FAST+ 79C972"; /* PCI */ | |
1591 | fdx = 1; | |
1592 | mii = 1; | |
1593 | fset = 1; | |
1594 | break; | |
1595 | case 0x2625: | |
1596 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
1597 | fdx = 1; | |
1598 | mii = 1; | |
1599 | break; | |
1600 | case 0x2626: | |
1601 | chipname = "PCnet/Home 79C978"; /* PCI */ | |
1602 | fdx = 1; | |
1603 | /* | |
1604 | * This is based on specs published at www.amd.com. This section | |
1605 | * assumes that a card with a 79C978 wants to go into standard | |
1606 | * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, | |
1607 | * and the module option homepna=1 can select this instead. | |
1608 | */ | |
1609 | media = a->read_bcr(ioaddr, 49); | |
1610 | media &= ~3; /* default to 10Mb ethernet */ | |
1611 | if (cards_found < MAX_UNITS && homepna[cards_found]) | |
1612 | media |= 1; /* switch to home wiring mode */ | |
1613 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1614 | printk(KERN_DEBUG PFX "media set to %sMbit mode\n", |
4a5e8e29 JG |
1615 | (media & 1) ? "1" : "10"); |
1616 | a->write_bcr(ioaddr, 49, media); | |
1617 | break; | |
1618 | case 0x2627: | |
1619 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
1620 | fdx = 1; | |
1621 | mii = 1; | |
1622 | break; | |
1623 | case 0x2628: | |
1624 | chipname = "PCnet/PRO 79C976"; | |
1625 | fdx = 1; | |
1626 | mii = 1; | |
1627 | break; | |
1628 | default: | |
1629 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 JP |
1630 | pr_info("PCnet version %#x, no PCnet32 chip\n", |
1631 | chip_version); | |
4a5e8e29 JG |
1632 | goto err_release_region; |
1633 | } | |
1634 | ||
1da177e4 | 1635 | /* |
4a5e8e29 JG |
1636 | * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit |
1637 | * starting until the packet is loaded. Strike one for reliability, lose | |
25985edc | 1638 | * one for latency - although on PCI this isn't a big loss. Older chips |
4a5e8e29 JG |
1639 | * have FIFO's smaller than a packet, so you can't do this. |
1640 | * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. | |
1da177e4 | 1641 | */ |
4a5e8e29 JG |
1642 | |
1643 | if (fset) { | |
1644 | a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); | |
1645 | a->write_csr(ioaddr, 80, | |
1646 | (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); | |
1647 | dxsuflo = 1; | |
1648 | } | |
1649 | ||
6ecb7667 | 1650 | dev = alloc_etherdev(sizeof(*lp)); |
4a5e8e29 | 1651 | if (!dev) { |
4a5e8e29 JG |
1652 | ret = -ENOMEM; |
1653 | goto err_release_region; | |
1654 | } | |
63097b3a DF |
1655 | |
1656 | if (pdev) | |
1657 | SET_NETDEV_DEV(dev, &pdev->dev); | |
4a5e8e29 | 1658 | |
1da177e4 | 1659 | if (pcnet32_debug & NETIF_MSG_PROBE) |
13ff83b9 | 1660 | pr_info("%s at %#3lx,", chipname, ioaddr); |
4a5e8e29 JG |
1661 | |
1662 | /* In most chips, after a chip reset, the ethernet address is read from the | |
1663 | * station address PROM at the base address and programmed into the | |
1664 | * "Physical Address Registers" CSR12-14. | |
1665 | * As a precautionary measure, we read the PROM values and complain if | |
bc0e1fc9 LV |
1666 | * they disagree with the CSRs. If they miscompare, and the PROM addr |
1667 | * is valid, then the PROM addr is used. | |
4a5e8e29 JG |
1668 | */ |
1669 | for (i = 0; i < 3; i++) { | |
1670 | unsigned int val; | |
1671 | val = a->read_csr(ioaddr, i + 12) & 0x0ffff; | |
1672 | /* There may be endianness issues here. */ | |
1673 | dev->dev_addr[2 * i] = val & 0x0ff; | |
1674 | dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; | |
1675 | } | |
1676 | ||
1677 | /* read PROM address and compare with CSR address */ | |
1da177e4 | 1678 | for (i = 0; i < 6; i++) |
4a5e8e29 JG |
1679 | promaddr[i] = inb(ioaddr + i); |
1680 | ||
8e95a202 JP |
1681 | if (memcmp(promaddr, dev->dev_addr, 6) || |
1682 | !is_valid_ether_addr(dev->dev_addr)) { | |
4a5e8e29 JG |
1683 | if (is_valid_ether_addr(promaddr)) { |
1684 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
13ff83b9 JP |
1685 | pr_cont(" warning: CSR address invalid,\n"); |
1686 | pr_info(" using instead PROM address of"); | |
4a5e8e29 JG |
1687 | } |
1688 | memcpy(dev->dev_addr, promaddr, 6); | |
1689 | } | |
1690 | } | |
1691 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
1692 | ||
1693 | /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ | |
1694 | if (!is_valid_ether_addr(dev->perm_addr)) | |
1f044931 | 1695 | memset(dev->dev_addr, 0, ETH_ALEN); |
4a5e8e29 JG |
1696 | |
1697 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
13ff83b9 | 1698 | pr_cont(" %pM", dev->dev_addr); |
4a5e8e29 JG |
1699 | |
1700 | /* Version 0x2623 and 0x2624 */ | |
1701 | if (((chip_version + 1) & 0xfffe) == 0x2624) { | |
1702 | i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ | |
13ff83b9 | 1703 | pr_info(" tx_start_pt(0x%04x):", i); |
4a5e8e29 JG |
1704 | switch (i >> 10) { |
1705 | case 0: | |
13ff83b9 | 1706 | pr_cont(" 20 bytes,"); |
4a5e8e29 JG |
1707 | break; |
1708 | case 1: | |
13ff83b9 | 1709 | pr_cont(" 64 bytes,"); |
4a5e8e29 JG |
1710 | break; |
1711 | case 2: | |
13ff83b9 | 1712 | pr_cont(" 128 bytes,"); |
4a5e8e29 JG |
1713 | break; |
1714 | case 3: | |
13ff83b9 | 1715 | pr_cont("~220 bytes,"); |
4a5e8e29 JG |
1716 | break; |
1717 | } | |
1718 | i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ | |
13ff83b9 | 1719 | pr_cont(" BCR18(%x):", i & 0xffff); |
4a5e8e29 | 1720 | if (i & (1 << 5)) |
13ff83b9 | 1721 | pr_cont("BurstWrEn "); |
4a5e8e29 | 1722 | if (i & (1 << 6)) |
13ff83b9 | 1723 | pr_cont("BurstRdEn "); |
4a5e8e29 | 1724 | if (i & (1 << 7)) |
13ff83b9 | 1725 | pr_cont("DWordIO "); |
4a5e8e29 | 1726 | if (i & (1 << 11)) |
13ff83b9 | 1727 | pr_cont("NoUFlow "); |
4a5e8e29 | 1728 | i = a->read_bcr(ioaddr, 25); |
13ff83b9 | 1729 | pr_info(" SRAMSIZE=0x%04x,", i << 8); |
4a5e8e29 | 1730 | i = a->read_bcr(ioaddr, 26); |
13ff83b9 | 1731 | pr_cont(" SRAM_BND=0x%04x,", i << 8); |
4a5e8e29 JG |
1732 | i = a->read_bcr(ioaddr, 27); |
1733 | if (i & (1 << 14)) | |
13ff83b9 | 1734 | pr_cont("LowLatRx"); |
4a5e8e29 JG |
1735 | } |
1736 | } | |
1737 | ||
1738 | dev->base_addr = ioaddr; | |
1e56a4b4 | 1739 | lp = netdev_priv(dev); |
4a5e8e29 | 1740 | /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ |
9e3f8063 JP |
1741 | lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), |
1742 | &lp->init_dma_addr); | |
1743 | if (!lp->init_block) { | |
4a5e8e29 | 1744 | if (pcnet32_debug & NETIF_MSG_PROBE) |
13ff83b9 | 1745 | pr_err("Consistent memory allocation failed\n"); |
4a5e8e29 JG |
1746 | ret = -ENOMEM; |
1747 | goto err_free_netdev; | |
1748 | } | |
4a5e8e29 JG |
1749 | lp->pci_dev = pdev; |
1750 | ||
bea3348e SH |
1751 | lp->dev = dev; |
1752 | ||
4a5e8e29 JG |
1753 | spin_lock_init(&lp->lock); |
1754 | ||
4a5e8e29 JG |
1755 | lp->name = chipname; |
1756 | lp->shared_irq = shared; | |
1757 | lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ | |
1758 | lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ | |
1759 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
1760 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
1761 | lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); | |
1762 | lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); | |
1763 | lp->mii_if.full_duplex = fdx; | |
1764 | lp->mii_if.phy_id_mask = 0x1f; | |
1765 | lp->mii_if.reg_num_mask = 0x1f; | |
1766 | lp->dxsuflo = dxsuflo; | |
1767 | lp->mii = mii; | |
8d916266 | 1768 | lp->chip_version = chip_version; |
4a5e8e29 | 1769 | lp->msg_enable = pcnet32_debug; |
8e95a202 JP |
1770 | if ((cards_found >= MAX_UNITS) || |
1771 | (options[cards_found] >= sizeof(options_mapping))) | |
4a5e8e29 JG |
1772 | lp->options = PCNET32_PORT_ASEL; |
1773 | else | |
1774 | lp->options = options_mapping[options[cards_found]]; | |
1775 | lp->mii_if.dev = dev; | |
1776 | lp->mii_if.mdio_read = mdio_read; | |
1777 | lp->mii_if.mdio_write = mdio_write; | |
1778 | ||
feff348f DF |
1779 | /* napi.weight is used in both the napi and non-napi cases */ |
1780 | lp->napi.weight = lp->rx_ring_size / 2; | |
1781 | ||
bea3348e | 1782 | netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); |
bea3348e | 1783 | |
4a5e8e29 JG |
1784 | if (fdx && !(lp->options & PCNET32_PORT_ASEL) && |
1785 | ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) | |
1786 | lp->options |= PCNET32_PORT_FD; | |
1787 | ||
1d70cb06 | 1788 | lp->a = a; |
4a5e8e29 JG |
1789 | |
1790 | /* prior to register_netdev, dev->name is not yet correct */ | |
1791 | if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { | |
1792 | ret = -ENOMEM; | |
1793 | goto err_free_ring; | |
1794 | } | |
1795 | /* detect special T1/E1 WAN card by checking for MAC address */ | |
8e95a202 JP |
1796 | if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && |
1797 | dev->dev_addr[2] == 0x75) | |
4a5e8e29 | 1798 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; |
1da177e4 | 1799 | |
3e33545b | 1800 | lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ |
6ecb7667 | 1801 | lp->init_block->tlen_rlen = |
3e33545b | 1802 | cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); |
4a5e8e29 | 1803 | for (i = 0; i < 6; i++) |
6ecb7667 DF |
1804 | lp->init_block->phys_addr[i] = dev->dev_addr[i]; |
1805 | lp->init_block->filter[0] = 0x00000000; | |
1806 | lp->init_block->filter[1] = 0x00000000; | |
3e33545b AV |
1807 | lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); |
1808 | lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); | |
4a5e8e29 JG |
1809 | |
1810 | /* switch pcnet32 to 32bit mode */ | |
1811 | a->write_bcr(ioaddr, 20, 2); | |
1812 | ||
6ecb7667 DF |
1813 | a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); |
1814 | a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); | |
4a5e8e29 JG |
1815 | |
1816 | if (pdev) { /* use the IRQ provided by PCI */ | |
1817 | dev->irq = pdev->irq; | |
1818 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1819 | pr_cont(" assigned IRQ %d\n", dev->irq); |
4a5e8e29 JG |
1820 | } else { |
1821 | unsigned long irq_mask = probe_irq_on(); | |
1822 | ||
1823 | /* | |
1824 | * To auto-IRQ we enable the initialization-done and DMA error | |
1825 | * interrupts. For ISA boards we get a DMA error, but VLB and PCI | |
1826 | * boards will work. | |
1827 | */ | |
1828 | /* Trigger an initialization just for the interrupt. */ | |
b368a3fb | 1829 | a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); |
4a5e8e29 JG |
1830 | mdelay(1); |
1831 | ||
1832 | dev->irq = probe_irq_off(irq_mask); | |
1833 | if (!dev->irq) { | |
1834 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1835 | pr_cont(", failed to detect IRQ line\n"); |
4a5e8e29 JG |
1836 | ret = -ENODEV; |
1837 | goto err_free_ring; | |
1838 | } | |
1839 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1840 | pr_cont(", probed IRQ %d\n", dev->irq); |
4a5e8e29 | 1841 | } |
1da177e4 | 1842 | |
4a5e8e29 JG |
1843 | /* Set the mii phy_id so that we can query the link state */ |
1844 | if (lp->mii) { | |
1845 | /* lp->phycount and lp->phymask are set to 0 by memset above */ | |
1846 | ||
1d70cb06 | 1847 | lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; |
4a5e8e29 JG |
1848 | /* scan for PHYs */ |
1849 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
1850 | unsigned short id1, id2; | |
1851 | ||
1852 | id1 = mdio_read(dev, i, MII_PHYSID1); | |
1853 | if (id1 == 0xffff) | |
1854 | continue; | |
1855 | id2 = mdio_read(dev, i, MII_PHYSID2); | |
1856 | if (id2 == 0xffff) | |
1857 | continue; | |
1858 | if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) | |
1859 | continue; /* 79C971 & 79C972 have phantom phy at id 31 */ | |
1860 | lp->phycount++; | |
1861 | lp->phymask |= (1 << i); | |
1862 | lp->mii_if.phy_id = i; | |
1863 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 JP |
1864 | pr_info("Found PHY %04x:%04x at address %d\n", |
1865 | id1, id2, i); | |
4a5e8e29 | 1866 | } |
1d70cb06 | 1867 | lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); |
9e3f8063 | 1868 | if (lp->phycount > 1) |
4a5e8e29 | 1869 | lp->options |= PCNET32_PORT_MII; |
1da177e4 | 1870 | } |
4a5e8e29 JG |
1871 | |
1872 | init_timer(&lp->watchdog_timer); | |
1873 | lp->watchdog_timer.data = (unsigned long)dev; | |
1874 | lp->watchdog_timer.function = (void *)&pcnet32_watchdog; | |
1875 | ||
1876 | /* The PCNET32-specific entries in the device structure. */ | |
3bc124dd | 1877 | dev->netdev_ops = &pcnet32_netdev_ops; |
4a5e8e29 | 1878 | dev->ethtool_ops = &pcnet32_ethtool_ops; |
4a5e8e29 | 1879 | dev->watchdog_timeo = (5 * HZ); |
1da177e4 | 1880 | |
4a5e8e29 JG |
1881 | /* Fill in the generic fields of the device structure. */ |
1882 | if (register_netdev(dev)) | |
1883 | goto err_free_ring; | |
1884 | ||
1885 | if (pdev) { | |
1886 | pci_set_drvdata(pdev, dev); | |
1887 | } else { | |
1888 | lp->next = pcnet32_dev; | |
1889 | pcnet32_dev = dev; | |
1890 | } | |
1891 | ||
1892 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
13ff83b9 | 1893 | pr_info("%s: registered as %s\n", dev->name, lp->name); |
4a5e8e29 JG |
1894 | cards_found++; |
1895 | ||
1896 | /* enable LED writes */ | |
1897 | a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); | |
1da177e4 | 1898 | |
4a5e8e29 JG |
1899 | return 0; |
1900 | ||
df4e7f72 | 1901 | err_free_ring: |
4a5e8e29 | 1902 | pcnet32_free_ring(dev); |
7d2e3cb7 | 1903 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
6ecb7667 | 1904 | lp->init_block, lp->init_dma_addr); |
df4e7f72 | 1905 | err_free_netdev: |
4a5e8e29 | 1906 | free_netdev(dev); |
df4e7f72 | 1907 | err_release_region: |
4a5e8e29 JG |
1908 | release_region(ioaddr, PCNET32_TOTAL_SIZE); |
1909 | return ret; | |
1910 | } | |
1da177e4 | 1911 | |
a88c844c | 1912 | /* if any allocation fails, caller must also call pcnet32_free_ring */ |
b166cfba | 1913 | static int pcnet32_alloc_ring(struct net_device *dev, const char *name) |
eabf0415 | 1914 | { |
1e56a4b4 | 1915 | struct pcnet32_private *lp = netdev_priv(dev); |
eabf0415 | 1916 | |
4a5e8e29 JG |
1917 | lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1918 | sizeof(struct pcnet32_tx_head) * | |
1919 | lp->tx_ring_size, | |
1920 | &lp->tx_ring_dma_addr); | |
1921 | if (lp->tx_ring == NULL) { | |
13ff83b9 | 1922 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
4a5e8e29 JG |
1923 | return -ENOMEM; |
1924 | } | |
eabf0415 | 1925 | |
4a5e8e29 JG |
1926 | lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
1927 | sizeof(struct pcnet32_rx_head) * | |
1928 | lp->rx_ring_size, | |
1929 | &lp->rx_ring_dma_addr); | |
1930 | if (lp->rx_ring == NULL) { | |
13ff83b9 | 1931 | netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); |
4a5e8e29 JG |
1932 | return -ENOMEM; |
1933 | } | |
eabf0415 | 1934 | |
12fa30f3 | 1935 | lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), |
4a5e8e29 JG |
1936 | GFP_ATOMIC); |
1937 | if (!lp->tx_dma_addr) { | |
13ff83b9 | 1938 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
4a5e8e29 JG |
1939 | return -ENOMEM; |
1940 | } | |
4a5e8e29 | 1941 | |
12fa30f3 | 1942 | lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), |
4a5e8e29 JG |
1943 | GFP_ATOMIC); |
1944 | if (!lp->rx_dma_addr) { | |
13ff83b9 | 1945 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
4a5e8e29 JG |
1946 | return -ENOMEM; |
1947 | } | |
4a5e8e29 | 1948 | |
12fa30f3 | 1949 | lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), |
4a5e8e29 JG |
1950 | GFP_ATOMIC); |
1951 | if (!lp->tx_skbuff) { | |
13ff83b9 | 1952 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
4a5e8e29 JG |
1953 | return -ENOMEM; |
1954 | } | |
4a5e8e29 | 1955 | |
12fa30f3 | 1956 | lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), |
4a5e8e29 JG |
1957 | GFP_ATOMIC); |
1958 | if (!lp->rx_skbuff) { | |
13ff83b9 | 1959 | netif_err(lp, drv, dev, "Memory allocation failed\n"); |
4a5e8e29 JG |
1960 | return -ENOMEM; |
1961 | } | |
4a5e8e29 JG |
1962 | |
1963 | return 0; | |
1964 | } | |
eabf0415 HWL |
1965 | |
1966 | static void pcnet32_free_ring(struct net_device *dev) | |
1967 | { | |
1e56a4b4 | 1968 | struct pcnet32_private *lp = netdev_priv(dev); |
eabf0415 | 1969 | |
4a5e8e29 JG |
1970 | kfree(lp->tx_skbuff); |
1971 | lp->tx_skbuff = NULL; | |
eabf0415 | 1972 | |
4a5e8e29 JG |
1973 | kfree(lp->rx_skbuff); |
1974 | lp->rx_skbuff = NULL; | |
eabf0415 | 1975 | |
4a5e8e29 JG |
1976 | kfree(lp->tx_dma_addr); |
1977 | lp->tx_dma_addr = NULL; | |
eabf0415 | 1978 | |
4a5e8e29 JG |
1979 | kfree(lp->rx_dma_addr); |
1980 | lp->rx_dma_addr = NULL; | |
eabf0415 | 1981 | |
4a5e8e29 JG |
1982 | if (lp->tx_ring) { |
1983 | pci_free_consistent(lp->pci_dev, | |
1984 | sizeof(struct pcnet32_tx_head) * | |
1985 | lp->tx_ring_size, lp->tx_ring, | |
1986 | lp->tx_ring_dma_addr); | |
1987 | lp->tx_ring = NULL; | |
1988 | } | |
eabf0415 | 1989 | |
4a5e8e29 JG |
1990 | if (lp->rx_ring) { |
1991 | pci_free_consistent(lp->pci_dev, | |
1992 | sizeof(struct pcnet32_rx_head) * | |
1993 | lp->rx_ring_size, lp->rx_ring, | |
1994 | lp->rx_ring_dma_addr); | |
1995 | lp->rx_ring = NULL; | |
1996 | } | |
eabf0415 HWL |
1997 | } |
1998 | ||
4a5e8e29 | 1999 | static int pcnet32_open(struct net_device *dev) |
1da177e4 | 2000 | { |
1e56a4b4 | 2001 | struct pcnet32_private *lp = netdev_priv(dev); |
63097b3a | 2002 | struct pci_dev *pdev = lp->pci_dev; |
4a5e8e29 JG |
2003 | unsigned long ioaddr = dev->base_addr; |
2004 | u16 val; | |
2005 | int i; | |
2006 | int rc; | |
2007 | unsigned long flags; | |
2008 | ||
a0607fd3 | 2009 | if (request_irq(dev->irq, pcnet32_interrupt, |
1fb9df5d | 2010 | lp->shared_irq ? IRQF_SHARED : 0, dev->name, |
4a5e8e29 JG |
2011 | (void *)dev)) { |
2012 | return -EAGAIN; | |
2013 | } | |
2014 | ||
2015 | spin_lock_irqsave(&lp->lock, flags); | |
2016 | /* Check for a valid station address */ | |
2017 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
2018 | rc = -EINVAL; | |
2019 | goto err_free_irq; | |
2020 | } | |
2021 | ||
2022 | /* Reset the PCNET32 */ | |
1d70cb06 | 2023 | lp->a->reset(ioaddr); |
4a5e8e29 JG |
2024 | |
2025 | /* switch pcnet32 to 32bit mode */ | |
1d70cb06 | 2026 | lp->a->write_bcr(ioaddr, 20, 2); |
4a5e8e29 | 2027 | |
13ff83b9 JP |
2028 | netif_printk(lp, ifup, KERN_DEBUG, dev, |
2029 | "%s() irq %d tx/rx rings %#x/%#x init %#x\n", | |
2030 | __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), | |
2031 | (u32) (lp->rx_ring_dma_addr), | |
2032 | (u32) (lp->init_dma_addr)); | |
4a5e8e29 JG |
2033 | |
2034 | /* set/reset autoselect bit */ | |
1d70cb06 | 2035 | val = lp->a->read_bcr(ioaddr, 2) & ~2; |
4a5e8e29 | 2036 | if (lp->options & PCNET32_PORT_ASEL) |
1da177e4 | 2037 | val |= 2; |
1d70cb06 | 2038 | lp->a->write_bcr(ioaddr, 2, val); |
4a5e8e29 JG |
2039 | |
2040 | /* handle full duplex setting */ | |
2041 | if (lp->mii_if.full_duplex) { | |
1d70cb06 | 2042 | val = lp->a->read_bcr(ioaddr, 9) & ~3; |
4a5e8e29 JG |
2043 | if (lp->options & PCNET32_PORT_FD) { |
2044 | val |= 1; | |
2045 | if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) | |
2046 | val |= 2; | |
2047 | } else if (lp->options & PCNET32_PORT_ASEL) { | |
2048 | /* workaround of xSeries250, turn on for 79C975 only */ | |
8d916266 | 2049 | if (lp->chip_version == 0x2627) |
4a5e8e29 JG |
2050 | val |= 3; |
2051 | } | |
1d70cb06 | 2052 | lp->a->write_bcr(ioaddr, 9, val); |
4a5e8e29 JG |
2053 | } |
2054 | ||
2055 | /* set/reset GPSI bit in test register */ | |
1d70cb06 | 2056 | val = lp->a->read_csr(ioaddr, 124) & ~0x10; |
4a5e8e29 JG |
2057 | if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) |
2058 | val |= 0x10; | |
1d70cb06 | 2059 | lp->a->write_csr(ioaddr, 124, val); |
4a5e8e29 JG |
2060 | |
2061 | /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ | |
63097b3a DF |
2062 | if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && |
2063 | (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || | |
2064 | pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { | |
ac62ef04 | 2065 | if (lp->options & PCNET32_PORT_ASEL) { |
4a5e8e29 | 2066 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; |
13ff83b9 JP |
2067 | netif_printk(lp, link, KERN_DEBUG, dev, |
2068 | "Setting 100Mb-Full Duplex\n"); | |
4a5e8e29 JG |
2069 | } |
2070 | } | |
2071 | if (lp->phycount < 2) { | |
2072 | /* | |
2073 | * 24 Jun 2004 according AMD, in order to change the PHY, | |
2074 | * DANAS (or DISPM for 79C976) must be set; then select the speed, | |
2075 | * duplex, and/or enable auto negotiation, and clear DANAS | |
2076 | */ | |
2077 | if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { | |
1d70cb06 | 2078 | lp->a->write_bcr(ioaddr, 32, |
2079 | lp->a->read_bcr(ioaddr, 32) | 0x0080); | |
4a5e8e29 | 2080 | /* disable Auto Negotiation, set 10Mpbs, HD */ |
1d70cb06 | 2081 | val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; |
4a5e8e29 JG |
2082 | if (lp->options & PCNET32_PORT_FD) |
2083 | val |= 0x10; | |
2084 | if (lp->options & PCNET32_PORT_100) | |
2085 | val |= 0x08; | |
1d70cb06 | 2086 | lp->a->write_bcr(ioaddr, 32, val); |
4a5e8e29 JG |
2087 | } else { |
2088 | if (lp->options & PCNET32_PORT_ASEL) { | |
1d70cb06 | 2089 | lp->a->write_bcr(ioaddr, 32, |
2090 | lp->a->read_bcr(ioaddr, | |
4a5e8e29 JG |
2091 | 32) | 0x0080); |
2092 | /* enable auto negotiate, setup, disable fd */ | |
1d70cb06 | 2093 | val = lp->a->read_bcr(ioaddr, 32) & ~0x98; |
4a5e8e29 | 2094 | val |= 0x20; |
1d70cb06 | 2095 | lp->a->write_bcr(ioaddr, 32, val); |
4a5e8e29 JG |
2096 | } |
2097 | } | |
2098 | } else { | |
2099 | int first_phy = -1; | |
2100 | u16 bmcr; | |
2101 | u32 bcr9; | |
8ae6daca | 2102 | struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; |
4a5e8e29 JG |
2103 | |
2104 | /* | |
2105 | * There is really no good other way to handle multiple PHYs | |
2106 | * other than turning off all automatics | |
2107 | */ | |
1d70cb06 | 2108 | val = lp->a->read_bcr(ioaddr, 2); |
2109 | lp->a->write_bcr(ioaddr, 2, val & ~2); | |
2110 | val = lp->a->read_bcr(ioaddr, 32); | |
2111 | lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ | |
4a5e8e29 JG |
2112 | |
2113 | if (!(lp->options & PCNET32_PORT_ASEL)) { | |
2114 | /* setup ecmd */ | |
2115 | ecmd.port = PORT_MII; | |
2116 | ecmd.transceiver = XCVR_INTERNAL; | |
2117 | ecmd.autoneg = AUTONEG_DISABLE; | |
8ae6daca DD |
2118 | ethtool_cmd_speed_set(&ecmd, |
2119 | (lp->options & PCNET32_PORT_100) ? | |
2120 | SPEED_100 : SPEED_10); | |
1d70cb06 | 2121 | bcr9 = lp->a->read_bcr(ioaddr, 9); |
4a5e8e29 JG |
2122 | |
2123 | if (lp->options & PCNET32_PORT_FD) { | |
2124 | ecmd.duplex = DUPLEX_FULL; | |
2125 | bcr9 |= (1 << 0); | |
2126 | } else { | |
2127 | ecmd.duplex = DUPLEX_HALF; | |
2128 | bcr9 |= ~(1 << 0); | |
2129 | } | |
1d70cb06 | 2130 | lp->a->write_bcr(ioaddr, 9, bcr9); |
ac62ef04 | 2131 | } |
4a5e8e29 JG |
2132 | |
2133 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
2134 | if (lp->phymask & (1 << i)) { | |
2135 | /* isolate all but the first PHY */ | |
2136 | bmcr = mdio_read(dev, i, MII_BMCR); | |
2137 | if (first_phy == -1) { | |
2138 | first_phy = i; | |
2139 | mdio_write(dev, i, MII_BMCR, | |
2140 | bmcr & ~BMCR_ISOLATE); | |
2141 | } else { | |
2142 | mdio_write(dev, i, MII_BMCR, | |
2143 | bmcr | BMCR_ISOLATE); | |
2144 | } | |
2145 | /* use mii_ethtool_sset to setup PHY */ | |
2146 | lp->mii_if.phy_id = i; | |
2147 | ecmd.phy_address = i; | |
2148 | if (lp->options & PCNET32_PORT_ASEL) { | |
2149 | mii_ethtool_gset(&lp->mii_if, &ecmd); | |
2150 | ecmd.autoneg = AUTONEG_ENABLE; | |
2151 | } | |
2152 | mii_ethtool_sset(&lp->mii_if, &ecmd); | |
2153 | } | |
2154 | } | |
2155 | lp->mii_if.phy_id = first_phy; | |
13ff83b9 | 2156 | netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); |
4a5e8e29 | 2157 | } |
1da177e4 LT |
2158 | |
2159 | #ifdef DO_DXSUFLO | |
4a5e8e29 | 2160 | if (lp->dxsuflo) { /* Disable transmit stop on underflow */ |
1d70cb06 | 2161 | val = lp->a->read_csr(ioaddr, CSR3); |
4a5e8e29 | 2162 | val |= 0x40; |
1d70cb06 | 2163 | lp->a->write_csr(ioaddr, CSR3, val); |
4a5e8e29 | 2164 | } |
1da177e4 LT |
2165 | #endif |
2166 | ||
6ecb7667 | 2167 | lp->init_block->mode = |
3e33545b | 2168 | cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); |
4a5e8e29 JG |
2169 | pcnet32_load_multicast(dev); |
2170 | ||
2171 | if (pcnet32_init_ring(dev)) { | |
2172 | rc = -ENOMEM; | |
2173 | goto err_free_ring; | |
2174 | } | |
2175 | ||
bea3348e | 2176 | napi_enable(&lp->napi); |
bea3348e | 2177 | |
4a5e8e29 | 2178 | /* Re-initialize the PCNET32, and start it when done. */ |
1d70cb06 | 2179 | lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); |
2180 | lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); | |
4a5e8e29 | 2181 | |
1d70cb06 | 2182 | lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ |
2183 | lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); | |
4a5e8e29 JG |
2184 | |
2185 | netif_start_queue(dev); | |
2186 | ||
8d916266 DF |
2187 | if (lp->chip_version >= PCNET32_79C970A) { |
2188 | /* Print the link status and start the watchdog */ | |
2189 | pcnet32_check_media(dev, 1); | |
283a21d3 | 2190 | mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); |
8d916266 | 2191 | } |
4a5e8e29 JG |
2192 | |
2193 | i = 0; | |
2194 | while (i++ < 100) | |
1d70cb06 | 2195 | if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) |
4a5e8e29 JG |
2196 | break; |
2197 | /* | |
2198 | * We used to clear the InitDone bit, 0x0100, here but Mark Stockton | |
2199 | * reports that doing so triggers a bug in the '974. | |
2200 | */ | |
1d70cb06 | 2201 | lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); |
4a5e8e29 | 2202 | |
13ff83b9 JP |
2203 | netif_printk(lp, ifup, KERN_DEBUG, dev, |
2204 | "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", | |
2205 | i, | |
2206 | (u32) (lp->init_dma_addr), | |
1d70cb06 | 2207 | lp->a->read_csr(ioaddr, CSR0)); |
4a5e8e29 JG |
2208 | |
2209 | spin_unlock_irqrestore(&lp->lock, flags); | |
2210 | ||
2211 | return 0; /* Always succeed */ | |
2212 | ||
9e3f8063 | 2213 | err_free_ring: |
4a5e8e29 | 2214 | /* free any allocated skbuffs */ |
ac5bfe40 | 2215 | pcnet32_purge_rx_ring(dev); |
4a5e8e29 | 2216 | |
4a5e8e29 JG |
2217 | /* |
2218 | * Switch back to 16bit mode to avoid problems with dumb | |
2219 | * DOS packet driver after a warm reboot | |
2220 | */ | |
1d70cb06 | 2221 | lp->a->write_bcr(ioaddr, 20, 4); |
4a5e8e29 | 2222 | |
9e3f8063 | 2223 | err_free_irq: |
4a5e8e29 JG |
2224 | spin_unlock_irqrestore(&lp->lock, flags); |
2225 | free_irq(dev->irq, dev); | |
2226 | return rc; | |
1da177e4 LT |
2227 | } |
2228 | ||
2229 | /* | |
2230 | * The LANCE has been halted for one reason or another (busmaster memory | |
2231 | * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, | |
2232 | * etc.). Modern LANCE variants always reload their ring-buffer | |
2233 | * configuration when restarted, so we must reinitialize our ring | |
2234 | * context before restarting. As part of this reinitialization, | |
2235 | * find all packets still on the Tx ring and pretend that they had been | |
2236 | * sent (in effect, drop the packets on the floor) - the higher-level | |
2237 | * protocols will time out and retransmit. It'd be better to shuffle | |
2238 | * these skbs to a temp list and then actually re-Tx them after | |
2239 | * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com | |
2240 | */ | |
2241 | ||
4a5e8e29 | 2242 | static void pcnet32_purge_tx_ring(struct net_device *dev) |
1da177e4 | 2243 | { |
1e56a4b4 | 2244 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 2245 | int i; |
1da177e4 | 2246 | |
4a5e8e29 JG |
2247 | for (i = 0; i < lp->tx_ring_size; i++) { |
2248 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
2249 | wmb(); /* Make sure adapter sees owner change */ | |
2250 | if (lp->tx_skbuff[i]) { | |
2251 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
2252 | lp->tx_skbuff[i]->len, | |
2253 | PCI_DMA_TODEVICE); | |
2254 | dev_kfree_skb_any(lp->tx_skbuff[i]); | |
2255 | } | |
2256 | lp->tx_skbuff[i] = NULL; | |
2257 | lp->tx_dma_addr[i] = 0; | |
2258 | } | |
2259 | } | |
1da177e4 LT |
2260 | |
2261 | /* Initialize the PCNET32 Rx and Tx rings. */ | |
4a5e8e29 | 2262 | static int pcnet32_init_ring(struct net_device *dev) |
1da177e4 | 2263 | { |
1e56a4b4 | 2264 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2265 | int i; |
2266 | ||
2267 | lp->tx_full = 0; | |
2268 | lp->cur_rx = lp->cur_tx = 0; | |
2269 | lp->dirty_rx = lp->dirty_tx = 0; | |
2270 | ||
2271 | for (i = 0; i < lp->rx_ring_size; i++) { | |
2272 | struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; | |
2273 | if (rx_skbuff == NULL) { | |
9e3f8063 JP |
2274 | lp->rx_skbuff[i] = dev_alloc_skb(PKT_BUF_SKB); |
2275 | rx_skbuff = lp->rx_skbuff[i]; | |
2276 | if (!rx_skbuff) { | |
2277 | /* there is not much we can do at this point */ | |
13ff83b9 JP |
2278 | netif_err(lp, drv, dev, "%s dev_alloc_skb failed\n", |
2279 | __func__); | |
4a5e8e29 JG |
2280 | return -1; |
2281 | } | |
232c5640 | 2282 | skb_reserve(rx_skbuff, NET_IP_ALIGN); |
4a5e8e29 JG |
2283 | } |
2284 | ||
2285 | rmb(); | |
2286 | if (lp->rx_dma_addr[i] == 0) | |
2287 | lp->rx_dma_addr[i] = | |
2288 | pci_map_single(lp->pci_dev, rx_skbuff->data, | |
232c5640 | 2289 | PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); |
3e33545b | 2290 | lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); |
232c5640 | 2291 | lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); |
4a5e8e29 | 2292 | wmb(); /* Make sure owner changes after all others are visible */ |
3e33545b | 2293 | lp->rx_ring[i].status = cpu_to_le16(0x8000); |
4a5e8e29 JG |
2294 | } |
2295 | /* The Tx buffer address is filled in as needed, but we do need to clear | |
2296 | * the upper ownership bit. */ | |
2297 | for (i = 0; i < lp->tx_ring_size; i++) { | |
2298 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
2299 | wmb(); /* Make sure adapter sees owner change */ | |
2300 | lp->tx_ring[i].base = 0; | |
2301 | lp->tx_dma_addr[i] = 0; | |
2302 | } | |
2303 | ||
6ecb7667 | 2304 | lp->init_block->tlen_rlen = |
3e33545b | 2305 | cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); |
4a5e8e29 | 2306 | for (i = 0; i < 6; i++) |
6ecb7667 | 2307 | lp->init_block->phys_addr[i] = dev->dev_addr[i]; |
3e33545b AV |
2308 | lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); |
2309 | lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); | |
4a5e8e29 JG |
2310 | wmb(); /* Make sure all changes are visible */ |
2311 | return 0; | |
1da177e4 LT |
2312 | } |
2313 | ||
2314 | /* the pcnet32 has been issued a stop or reset. Wait for the stop bit | |
2315 | * then flush the pending transmit operations, re-initialize the ring, | |
2316 | * and tell the chip to initialize. | |
2317 | */ | |
4a5e8e29 | 2318 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) |
1da177e4 | 2319 | { |
1e56a4b4 | 2320 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2321 | unsigned long ioaddr = dev->base_addr; |
2322 | int i; | |
1da177e4 | 2323 | |
4a5e8e29 JG |
2324 | /* wait for stop */ |
2325 | for (i = 0; i < 100; i++) | |
1d70cb06 | 2326 | if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) |
4a5e8e29 | 2327 | break; |
1da177e4 | 2328 | |
13ff83b9 JP |
2329 | if (i >= 100) |
2330 | netif_err(lp, drv, dev, "%s timed out waiting for stop\n", | |
2331 | __func__); | |
1da177e4 | 2332 | |
4a5e8e29 JG |
2333 | pcnet32_purge_tx_ring(dev); |
2334 | if (pcnet32_init_ring(dev)) | |
2335 | return; | |
1da177e4 | 2336 | |
4a5e8e29 | 2337 | /* ReInit Ring */ |
1d70cb06 | 2338 | lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); |
4a5e8e29 JG |
2339 | i = 0; |
2340 | while (i++ < 1000) | |
1d70cb06 | 2341 | if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) |
4a5e8e29 | 2342 | break; |
1da177e4 | 2343 | |
1d70cb06 | 2344 | lp->a->write_csr(ioaddr, CSR0, csr0_bits); |
1da177e4 LT |
2345 | } |
2346 | ||
4a5e8e29 | 2347 | static void pcnet32_tx_timeout(struct net_device *dev) |
1da177e4 | 2348 | { |
1e56a4b4 | 2349 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2350 | unsigned long ioaddr = dev->base_addr, flags; |
2351 | ||
2352 | spin_lock_irqsave(&lp->lock, flags); | |
2353 | /* Transmitter timeout, serious problems. */ | |
2354 | if (pcnet32_debug & NETIF_MSG_DRV) | |
13ff83b9 | 2355 | pr_err("%s: transmit timed out, status %4.4x, resetting\n", |
1d70cb06 | 2356 | dev->name, lp->a->read_csr(ioaddr, CSR0)); |
2357 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); | |
4f1e5ba0 | 2358 | dev->stats.tx_errors++; |
4a5e8e29 JG |
2359 | if (netif_msg_tx_err(lp)) { |
2360 | int i; | |
2361 | printk(KERN_DEBUG | |
2362 | " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", | |
2363 | lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", | |
2364 | lp->cur_rx); | |
2365 | for (i = 0; i < lp->rx_ring_size; i++) | |
2366 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
2367 | le32_to_cpu(lp->rx_ring[i].base), | |
2368 | (-le16_to_cpu(lp->rx_ring[i].buf_length)) & | |
2369 | 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), | |
2370 | le16_to_cpu(lp->rx_ring[i].status)); | |
2371 | for (i = 0; i < lp->tx_ring_size; i++) | |
2372 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
2373 | le32_to_cpu(lp->tx_ring[i].base), | |
2374 | (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, | |
2375 | le32_to_cpu(lp->tx_ring[i].misc), | |
2376 | le16_to_cpu(lp->tx_ring[i].status)); | |
2377 | printk("\n"); | |
2378 | } | |
b368a3fb | 2379 | pcnet32_restart(dev, CSR0_NORMAL); |
1da177e4 | 2380 | |
1ae5dc34 | 2381 | dev->trans_start = jiffies; /* prevent tx timeout */ |
4a5e8e29 | 2382 | netif_wake_queue(dev); |
1da177e4 | 2383 | |
4a5e8e29 JG |
2384 | spin_unlock_irqrestore(&lp->lock, flags); |
2385 | } | |
2386 | ||
61357325 SH |
2387 | static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, |
2388 | struct net_device *dev) | |
1da177e4 | 2389 | { |
1e56a4b4 | 2390 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2391 | unsigned long ioaddr = dev->base_addr; |
2392 | u16 status; | |
2393 | int entry; | |
2394 | unsigned long flags; | |
1da177e4 | 2395 | |
4a5e8e29 | 2396 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2397 | |
13ff83b9 JP |
2398 | netif_printk(lp, tx_queued, KERN_DEBUG, dev, |
2399 | "%s() called, csr0 %4.4x\n", | |
1d70cb06 | 2400 | __func__, lp->a->read_csr(ioaddr, CSR0)); |
1da177e4 | 2401 | |
4a5e8e29 JG |
2402 | /* Default status -- will not enable Successful-TxDone |
2403 | * interrupt when that option is available to us. | |
2404 | */ | |
2405 | status = 0x8300; | |
1da177e4 | 2406 | |
4a5e8e29 | 2407 | /* Fill in a Tx ring entry */ |
1da177e4 | 2408 | |
4a5e8e29 JG |
2409 | /* Mask to ring buffer boundary. */ |
2410 | entry = lp->cur_tx & lp->tx_mod_mask; | |
1da177e4 | 2411 | |
4a5e8e29 JG |
2412 | /* Caution: the write order is important here, set the status |
2413 | * with the "ownership" bits last. */ | |
1da177e4 | 2414 | |
3e33545b | 2415 | lp->tx_ring[entry].length = cpu_to_le16(-skb->len); |
1da177e4 | 2416 | |
4a5e8e29 | 2417 | lp->tx_ring[entry].misc = 0x00000000; |
1da177e4 | 2418 | |
4a5e8e29 JG |
2419 | lp->tx_skbuff[entry] = skb; |
2420 | lp->tx_dma_addr[entry] = | |
2421 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
3e33545b | 2422 | lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); |
4a5e8e29 | 2423 | wmb(); /* Make sure owner changes after all others are visible */ |
3e33545b | 2424 | lp->tx_ring[entry].status = cpu_to_le16(status); |
1da177e4 | 2425 | |
4a5e8e29 | 2426 | lp->cur_tx++; |
4f1e5ba0 | 2427 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 2428 | |
4a5e8e29 | 2429 | /* Trigger an immediate send poll. */ |
1d70cb06 | 2430 | lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); |
1da177e4 | 2431 | |
4a5e8e29 JG |
2432 | if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { |
2433 | lp->tx_full = 1; | |
2434 | netif_stop_queue(dev); | |
2435 | } | |
2436 | spin_unlock_irqrestore(&lp->lock, flags); | |
6ed10654 | 2437 | return NETDEV_TX_OK; |
1da177e4 LT |
2438 | } |
2439 | ||
2440 | /* The PCNET32 interrupt handler. */ | |
2441 | static irqreturn_t | |
7d12e780 | 2442 | pcnet32_interrupt(int irq, void *dev_id) |
1da177e4 | 2443 | { |
4a5e8e29 JG |
2444 | struct net_device *dev = dev_id; |
2445 | struct pcnet32_private *lp; | |
2446 | unsigned long ioaddr; | |
5c99346a | 2447 | u16 csr0; |
4a5e8e29 | 2448 | int boguscnt = max_interrupt_work; |
4a5e8e29 | 2449 | |
4a5e8e29 | 2450 | ioaddr = dev->base_addr; |
1e56a4b4 | 2451 | lp = netdev_priv(dev); |
1da177e4 | 2452 | |
4a5e8e29 JG |
2453 | spin_lock(&lp->lock); |
2454 | ||
1d70cb06 | 2455 | csr0 = lp->a->read_csr(ioaddr, CSR0); |
3904c324 | 2456 | while ((csr0 & 0x8f00) && --boguscnt >= 0) { |
9e3f8063 | 2457 | if (csr0 == 0xffff) |
4a5e8e29 | 2458 | break; /* PCMCIA remove happened */ |
4a5e8e29 | 2459 | /* Acknowledge all of the current interrupt sources ASAP. */ |
1d70cb06 | 2460 | lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); |
4a5e8e29 | 2461 | |
13ff83b9 JP |
2462 | netif_printk(lp, intr, KERN_DEBUG, dev, |
2463 | "interrupt csr0=%#2.2x new csr=%#2.2x\n", | |
1d70cb06 | 2464 | csr0, lp->a->read_csr(ioaddr, CSR0)); |
4a5e8e29 | 2465 | |
4a5e8e29 JG |
2466 | /* Log misc errors. */ |
2467 | if (csr0 & 0x4000) | |
4f1e5ba0 | 2468 | dev->stats.tx_errors++; /* Tx babble. */ |
4a5e8e29 JG |
2469 | if (csr0 & 0x1000) { |
2470 | /* | |
3904c324 DF |
2471 | * This happens when our receive ring is full. This |
2472 | * shouldn't be a problem as we will see normal rx | |
2473 | * interrupts for the frames in the receive ring. But | |
2474 | * there are some PCI chipsets (I can reproduce this | |
2475 | * on SP3G with Intel saturn chipset) which have | |
2476 | * sometimes problems and will fill up the receive | |
2477 | * ring with error descriptors. In this situation we | |
2478 | * don't get a rx interrupt, but a missed frame | |
7de745e5 | 2479 | * interrupt sooner or later. |
4a5e8e29 | 2480 | */ |
4f1e5ba0 | 2481 | dev->stats.rx_errors++; /* Missed a Rx frame. */ |
4a5e8e29 JG |
2482 | } |
2483 | if (csr0 & 0x0800) { | |
13ff83b9 JP |
2484 | netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", |
2485 | csr0); | |
4a5e8e29 | 2486 | /* unlike for the lance, there is no restart needed */ |
1da177e4 | 2487 | } |
288379f0 | 2488 | if (napi_schedule_prep(&lp->napi)) { |
7de745e5 DF |
2489 | u16 val; |
2490 | /* set interrupt masks */ | |
1d70cb06 | 2491 | val = lp->a->read_csr(ioaddr, CSR3); |
7de745e5 | 2492 | val |= 0x5f00; |
1d70cb06 | 2493 | lp->a->write_csr(ioaddr, CSR3, val); |
ce105a08 | 2494 | |
288379f0 | 2495 | __napi_schedule(&lp->napi); |
7de745e5 DF |
2496 | break; |
2497 | } | |
1d70cb06 | 2498 | csr0 = lp->a->read_csr(ioaddr, CSR0); |
4a5e8e29 JG |
2499 | } |
2500 | ||
13ff83b9 JP |
2501 | netif_printk(lp, intr, KERN_DEBUG, dev, |
2502 | "exiting interrupt, csr0=%#4.4x\n", | |
1d70cb06 | 2503 | lp->a->read_csr(ioaddr, CSR0)); |
4a5e8e29 JG |
2504 | |
2505 | spin_unlock(&lp->lock); | |
2506 | ||
2507 | return IRQ_HANDLED; | |
1da177e4 LT |
2508 | } |
2509 | ||
4a5e8e29 | 2510 | static int pcnet32_close(struct net_device *dev) |
1da177e4 | 2511 | { |
4a5e8e29 | 2512 | unsigned long ioaddr = dev->base_addr; |
1e56a4b4 | 2513 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 2514 | unsigned long flags; |
1da177e4 | 2515 | |
4a5e8e29 | 2516 | del_timer_sync(&lp->watchdog_timer); |
1da177e4 | 2517 | |
4a5e8e29 | 2518 | netif_stop_queue(dev); |
bea3348e | 2519 | napi_disable(&lp->napi); |
1da177e4 | 2520 | |
4a5e8e29 | 2521 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2522 | |
1d70cb06 | 2523 | dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); |
1da177e4 | 2524 | |
13ff83b9 JP |
2525 | netif_printk(lp, ifdown, KERN_DEBUG, dev, |
2526 | "Shutting down ethercard, status was %2.2x\n", | |
1d70cb06 | 2527 | lp->a->read_csr(ioaddr, CSR0)); |
1da177e4 | 2528 | |
4a5e8e29 | 2529 | /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ |
1d70cb06 | 2530 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); |
1da177e4 | 2531 | |
4a5e8e29 JG |
2532 | /* |
2533 | * Switch back to 16bit mode to avoid problems with dumb | |
2534 | * DOS packet driver after a warm reboot | |
2535 | */ | |
1d70cb06 | 2536 | lp->a->write_bcr(ioaddr, 20, 4); |
1da177e4 | 2537 | |
4a5e8e29 | 2538 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2539 | |
4a5e8e29 | 2540 | free_irq(dev->irq, dev); |
1da177e4 | 2541 | |
4a5e8e29 | 2542 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2543 | |
ac5bfe40 DF |
2544 | pcnet32_purge_rx_ring(dev); |
2545 | pcnet32_purge_tx_ring(dev); | |
1da177e4 | 2546 | |
4a5e8e29 | 2547 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2548 | |
4a5e8e29 | 2549 | return 0; |
1da177e4 LT |
2550 | } |
2551 | ||
4a5e8e29 | 2552 | static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) |
1da177e4 | 2553 | { |
1e56a4b4 | 2554 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 2555 | unsigned long ioaddr = dev->base_addr; |
4a5e8e29 JG |
2556 | unsigned long flags; |
2557 | ||
2558 | spin_lock_irqsave(&lp->lock, flags); | |
1d70cb06 | 2559 | dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); |
4a5e8e29 JG |
2560 | spin_unlock_irqrestore(&lp->lock, flags); |
2561 | ||
4f1e5ba0 | 2562 | return &dev->stats; |
1da177e4 LT |
2563 | } |
2564 | ||
2565 | /* taken from the sunlance driver, which it took from the depca driver */ | |
4a5e8e29 | 2566 | static void pcnet32_load_multicast(struct net_device *dev) |
1da177e4 | 2567 | { |
1e56a4b4 | 2568 | struct pcnet32_private *lp = netdev_priv(dev); |
6ecb7667 | 2569 | volatile struct pcnet32_init_block *ib = lp->init_block; |
3e33545b | 2570 | volatile __le16 *mcast_table = (__le16 *)ib->filter; |
22bedad3 | 2571 | struct netdev_hw_addr *ha; |
df27f4a6 | 2572 | unsigned long ioaddr = dev->base_addr; |
4a5e8e29 JG |
2573 | int i; |
2574 | u32 crc; | |
2575 | ||
2576 | /* set all multicast bits */ | |
2577 | if (dev->flags & IFF_ALLMULTI) { | |
3e33545b AV |
2578 | ib->filter[0] = cpu_to_le32(~0U); |
2579 | ib->filter[1] = cpu_to_le32(~0U); | |
1d70cb06 | 2580 | lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); |
2581 | lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); | |
2582 | lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); | |
2583 | lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); | |
4a5e8e29 JG |
2584 | return; |
2585 | } | |
2586 | /* clear the multicast filter */ | |
2587 | ib->filter[0] = 0; | |
2588 | ib->filter[1] = 0; | |
2589 | ||
2590 | /* Add addresses */ | |
22bedad3 | 2591 | netdev_for_each_mc_addr(ha, dev) { |
498d8e23 | 2592 | crc = ether_crc_le(6, ha->addr); |
4a5e8e29 | 2593 | crc = crc >> 26; |
3e33545b | 2594 | mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); |
4a5e8e29 | 2595 | } |
df27f4a6 | 2596 | for (i = 0; i < 4; i++) |
1d70cb06 | 2597 | lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, |
df27f4a6 | 2598 | le16_to_cpu(mcast_table[i])); |
1da177e4 LT |
2599 | } |
2600 | ||
1da177e4 LT |
2601 | /* |
2602 | * Set or clear the multicast filter for this adaptor. | |
2603 | */ | |
2604 | static void pcnet32_set_multicast_list(struct net_device *dev) | |
2605 | { | |
4a5e8e29 | 2606 | unsigned long ioaddr = dev->base_addr, flags; |
1e56a4b4 | 2607 | struct pcnet32_private *lp = netdev_priv(dev); |
df27f4a6 | 2608 | int csr15, suspended; |
4a5e8e29 JG |
2609 | |
2610 | spin_lock_irqsave(&lp->lock, flags); | |
df27f4a6 | 2611 | suspended = pcnet32_suspend(dev, &flags, 0); |
1d70cb06 | 2612 | csr15 = lp->a->read_csr(ioaddr, CSR15); |
4a5e8e29 JG |
2613 | if (dev->flags & IFF_PROMISC) { |
2614 | /* Log any net taps. */ | |
13ff83b9 | 2615 | netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); |
6ecb7667 | 2616 | lp->init_block->mode = |
3e33545b | 2617 | cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << |
4a5e8e29 | 2618 | 7); |
1d70cb06 | 2619 | lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); |
4a5e8e29 | 2620 | } else { |
6ecb7667 | 2621 | lp->init_block->mode = |
3e33545b | 2622 | cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); |
1d70cb06 | 2623 | lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); |
4a5e8e29 JG |
2624 | pcnet32_load_multicast(dev); |
2625 | } | |
2626 | ||
df27f4a6 DF |
2627 | if (suspended) { |
2628 | int csr5; | |
2629 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ | |
1d70cb06 | 2630 | csr5 = lp->a->read_csr(ioaddr, CSR5); |
2631 | lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); | |
b368a3fb | 2632 | } else { |
1d70cb06 | 2633 | lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); |
df27f4a6 DF |
2634 | pcnet32_restart(dev, CSR0_NORMAL); |
2635 | netif_wake_queue(dev); | |
2636 | } | |
4a5e8e29 JG |
2637 | |
2638 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
2639 | } |
2640 | ||
2641 | /* This routine assumes that the lp->lock is held */ | |
2642 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) | |
2643 | { | |
1e56a4b4 | 2644 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2645 | unsigned long ioaddr = dev->base_addr; |
2646 | u16 val_out; | |
1da177e4 | 2647 | |
4a5e8e29 JG |
2648 | if (!lp->mii) |
2649 | return 0; | |
1da177e4 | 2650 | |
1d70cb06 | 2651 | lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2652 | val_out = lp->a->read_bcr(ioaddr, 34); | |
1da177e4 | 2653 | |
4a5e8e29 | 2654 | return val_out; |
1da177e4 LT |
2655 | } |
2656 | ||
2657 | /* This routine assumes that the lp->lock is held */ | |
2658 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) | |
2659 | { | |
1e56a4b4 | 2660 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 2661 | unsigned long ioaddr = dev->base_addr; |
1da177e4 | 2662 | |
4a5e8e29 JG |
2663 | if (!lp->mii) |
2664 | return; | |
1da177e4 | 2665 | |
1d70cb06 | 2666 | lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2667 | lp->a->write_bcr(ioaddr, 34, val); | |
1da177e4 LT |
2668 | } |
2669 | ||
2670 | static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2671 | { | |
1e56a4b4 | 2672 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2673 | int rc; |
2674 | unsigned long flags; | |
1da177e4 | 2675 | |
4a5e8e29 JG |
2676 | /* SIOC[GS]MIIxxx ioctls */ |
2677 | if (lp->mii) { | |
2678 | spin_lock_irqsave(&lp->lock, flags); | |
2679 | rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); | |
2680 | spin_unlock_irqrestore(&lp->lock, flags); | |
2681 | } else { | |
2682 | rc = -EOPNOTSUPP; | |
2683 | } | |
1da177e4 | 2684 | |
4a5e8e29 | 2685 | return rc; |
1da177e4 LT |
2686 | } |
2687 | ||
ac62ef04 DF |
2688 | static int pcnet32_check_otherphy(struct net_device *dev) |
2689 | { | |
1e56a4b4 | 2690 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2691 | struct mii_if_info mii = lp->mii_if; |
2692 | u16 bmcr; | |
2693 | int i; | |
ac62ef04 | 2694 | |
4a5e8e29 JG |
2695 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
2696 | if (i == lp->mii_if.phy_id) | |
2697 | continue; /* skip active phy */ | |
2698 | if (lp->phymask & (1 << i)) { | |
2699 | mii.phy_id = i; | |
2700 | if (mii_link_ok(&mii)) { | |
2701 | /* found PHY with active link */ | |
13ff83b9 JP |
2702 | netif_info(lp, link, dev, "Using PHY number %d\n", |
2703 | i); | |
4a5e8e29 JG |
2704 | |
2705 | /* isolate inactive phy */ | |
2706 | bmcr = | |
2707 | mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); | |
2708 | mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, | |
2709 | bmcr | BMCR_ISOLATE); | |
2710 | ||
2711 | /* de-isolate new phy */ | |
2712 | bmcr = mdio_read(dev, i, MII_BMCR); | |
2713 | mdio_write(dev, i, MII_BMCR, | |
2714 | bmcr & ~BMCR_ISOLATE); | |
2715 | ||
2716 | /* set new phy address */ | |
2717 | lp->mii_if.phy_id = i; | |
2718 | return 1; | |
2719 | } | |
2720 | } | |
ac62ef04 | 2721 | } |
4a5e8e29 | 2722 | return 0; |
ac62ef04 DF |
2723 | } |
2724 | ||
2725 | /* | |
2726 | * Show the status of the media. Similar to mii_check_media however it | |
2727 | * correctly shows the link speed for all (tested) pcnet32 variants. | |
2728 | * Devices with no mii just report link state without speed. | |
2729 | * | |
2730 | * Caller is assumed to hold and release the lp->lock. | |
2731 | */ | |
2732 | ||
2733 | static void pcnet32_check_media(struct net_device *dev, int verbose) | |
2734 | { | |
1e56a4b4 | 2735 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2736 | int curr_link; |
2737 | int prev_link = netif_carrier_ok(dev) ? 1 : 0; | |
2738 | u32 bcr9; | |
2739 | ||
ac62ef04 | 2740 | if (lp->mii) { |
4a5e8e29 | 2741 | curr_link = mii_link_ok(&lp->mii_if); |
ac62ef04 | 2742 | } else { |
4a5e8e29 | 2743 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
1d70cb06 | 2744 | curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); |
4a5e8e29 JG |
2745 | } |
2746 | if (!curr_link) { | |
2747 | if (prev_link || verbose) { | |
2748 | netif_carrier_off(dev); | |
13ff83b9 | 2749 | netif_info(lp, link, dev, "link down\n"); |
4a5e8e29 JG |
2750 | } |
2751 | if (lp->phycount > 1) { | |
2752 | curr_link = pcnet32_check_otherphy(dev); | |
2753 | prev_link = 0; | |
2754 | } | |
2755 | } else if (verbose || !prev_link) { | |
2756 | netif_carrier_on(dev); | |
2757 | if (lp->mii) { | |
2758 | if (netif_msg_link(lp)) { | |
8ae6daca DD |
2759 | struct ethtool_cmd ecmd = { |
2760 | .cmd = ETHTOOL_GSET }; | |
4a5e8e29 | 2761 | mii_ethtool_gset(&lp->mii_if, &ecmd); |
8ae6daca DD |
2762 | netdev_info(dev, "link up, %uMbps, %s-duplex\n", |
2763 | ethtool_cmd_speed(&ecmd), | |
13ff83b9 JP |
2764 | (ecmd.duplex == DUPLEX_FULL) |
2765 | ? "full" : "half"); | |
4a5e8e29 | 2766 | } |
1d70cb06 | 2767 | bcr9 = lp->a->read_bcr(dev->base_addr, 9); |
4a5e8e29 JG |
2768 | if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { |
2769 | if (lp->mii_if.full_duplex) | |
2770 | bcr9 |= (1 << 0); | |
2771 | else | |
2772 | bcr9 &= ~(1 << 0); | |
1d70cb06 | 2773 | lp->a->write_bcr(dev->base_addr, 9, bcr9); |
4a5e8e29 JG |
2774 | } |
2775 | } else { | |
13ff83b9 | 2776 | netif_info(lp, link, dev, "link up\n"); |
4a5e8e29 | 2777 | } |
ac62ef04 | 2778 | } |
ac62ef04 DF |
2779 | } |
2780 | ||
2781 | /* | |
2782 | * Check for loss of link and link establishment. | |
2783 | * Can not use mii_check_media because it does nothing if mode is forced. | |
2784 | */ | |
2785 | ||
1da177e4 LT |
2786 | static void pcnet32_watchdog(struct net_device *dev) |
2787 | { | |
1e56a4b4 | 2788 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 | 2789 | unsigned long flags; |
1da177e4 | 2790 | |
4a5e8e29 JG |
2791 | /* Print the link status if it has changed */ |
2792 | spin_lock_irqsave(&lp->lock, flags); | |
2793 | pcnet32_check_media(dev, 0); | |
2794 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 | 2795 | |
283a21d3 | 2796 | mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); |
1da177e4 LT |
2797 | } |
2798 | ||
917270c6 DF |
2799 | static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) |
2800 | { | |
2801 | struct net_device *dev = pci_get_drvdata(pdev); | |
2802 | ||
2803 | if (netif_running(dev)) { | |
2804 | netif_device_detach(dev); | |
2805 | pcnet32_close(dev); | |
2806 | } | |
2807 | pci_save_state(pdev); | |
2808 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
2809 | return 0; | |
2810 | } | |
2811 | ||
2812 | static int pcnet32_pm_resume(struct pci_dev *pdev) | |
2813 | { | |
2814 | struct net_device *dev = pci_get_drvdata(pdev); | |
2815 | ||
2816 | pci_set_power_state(pdev, PCI_D0); | |
2817 | pci_restore_state(pdev); | |
2818 | ||
2819 | if (netif_running(dev)) { | |
2820 | pcnet32_open(dev); | |
2821 | netif_device_attach(dev); | |
2822 | } | |
2823 | return 0; | |
2824 | } | |
2825 | ||
1da177e4 LT |
2826 | static void __devexit pcnet32_remove_one(struct pci_dev *pdev) |
2827 | { | |
4a5e8e29 JG |
2828 | struct net_device *dev = pci_get_drvdata(pdev); |
2829 | ||
2830 | if (dev) { | |
1e56a4b4 | 2831 | struct pcnet32_private *lp = netdev_priv(dev); |
4a5e8e29 JG |
2832 | |
2833 | unregister_netdev(dev); | |
2834 | pcnet32_free_ring(dev); | |
2835 | release_region(dev->base_addr, PCNET32_TOTAL_SIZE); | |
7d2e3cb7 | 2836 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
6ecb7667 | 2837 | lp->init_block, lp->init_dma_addr); |
4a5e8e29 JG |
2838 | free_netdev(dev); |
2839 | pci_disable_device(pdev); | |
2840 | pci_set_drvdata(pdev, NULL); | |
2841 | } | |
1da177e4 LT |
2842 | } |
2843 | ||
2844 | static struct pci_driver pcnet32_driver = { | |
4a5e8e29 JG |
2845 | .name = DRV_NAME, |
2846 | .probe = pcnet32_probe_pci, | |
2847 | .remove = __devexit_p(pcnet32_remove_one), | |
2848 | .id_table = pcnet32_pci_tbl, | |
917270c6 DF |
2849 | .suspend = pcnet32_pm_suspend, |
2850 | .resume = pcnet32_pm_resume, | |
1da177e4 LT |
2851 | }; |
2852 | ||
2853 | /* An additional parameter that may be passed in... */ | |
2854 | static int debug = -1; | |
2855 | static int tx_start_pt = -1; | |
2856 | static int pcnet32_have_pci; | |
2857 | ||
2858 | module_param(debug, int, 0); | |
2859 | MODULE_PARM_DESC(debug, DRV_NAME " debug level"); | |
2860 | module_param(max_interrupt_work, int, 0); | |
4a5e8e29 JG |
2861 | MODULE_PARM_DESC(max_interrupt_work, |
2862 | DRV_NAME " maximum events handled per interrupt"); | |
1da177e4 | 2863 | module_param(rx_copybreak, int, 0); |
4a5e8e29 JG |
2864 | MODULE_PARM_DESC(rx_copybreak, |
2865 | DRV_NAME " copy breakpoint for copy-only-tiny-frames"); | |
1da177e4 LT |
2866 | module_param(tx_start_pt, int, 0); |
2867 | MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); | |
2868 | module_param(pcnet32vlb, int, 0); | |
2869 | MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); | |
2870 | module_param_array(options, int, NULL, 0); | |
2871 | MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); | |
2872 | module_param_array(full_duplex, int, NULL, 0); | |
2873 | MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); | |
2874 | /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ | |
2875 | module_param_array(homepna, int, NULL, 0); | |
4a5e8e29 JG |
2876 | MODULE_PARM_DESC(homepna, |
2877 | DRV_NAME | |
2878 | " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); | |
1da177e4 LT |
2879 | |
2880 | MODULE_AUTHOR("Thomas Bogendoerfer"); | |
2881 | MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); | |
2882 | MODULE_LICENSE("GPL"); | |
2883 | ||
2884 | #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
2885 | ||
2886 | static int __init pcnet32_init_module(void) | |
2887 | { | |
13ff83b9 | 2888 | pr_info("%s", version); |
1da177e4 | 2889 | |
4a5e8e29 | 2890 | pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); |
1da177e4 | 2891 | |
4a5e8e29 JG |
2892 | if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) |
2893 | tx_start = tx_start_pt; | |
1da177e4 | 2894 | |
4a5e8e29 | 2895 | /* find the PCI devices */ |
29917620 | 2896 | if (!pci_register_driver(&pcnet32_driver)) |
4a5e8e29 | 2897 | pcnet32_have_pci = 1; |
1da177e4 | 2898 | |
4a5e8e29 JG |
2899 | /* should we find any remaining VLbus devices ? */ |
2900 | if (pcnet32vlb) | |
dcaf9769 | 2901 | pcnet32_probe_vlbus(pcnet32_portlist); |
1da177e4 | 2902 | |
4a5e8e29 | 2903 | if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) |
13ff83b9 | 2904 | pr_info("%d cards_found\n", cards_found); |
1da177e4 | 2905 | |
4a5e8e29 | 2906 | return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; |
1da177e4 LT |
2907 | } |
2908 | ||
2909 | static void __exit pcnet32_cleanup_module(void) | |
2910 | { | |
4a5e8e29 JG |
2911 | struct net_device *next_dev; |
2912 | ||
2913 | while (pcnet32_dev) { | |
1e56a4b4 | 2914 | struct pcnet32_private *lp = netdev_priv(pcnet32_dev); |
4a5e8e29 JG |
2915 | next_dev = lp->next; |
2916 | unregister_netdev(pcnet32_dev); | |
2917 | pcnet32_free_ring(pcnet32_dev); | |
2918 | release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); | |
7d2e3cb7 | 2919 | pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), |
6ecb7667 | 2920 | lp->init_block, lp->init_dma_addr); |
4a5e8e29 JG |
2921 | free_netdev(pcnet32_dev); |
2922 | pcnet32_dev = next_dev; | |
2923 | } | |
1da177e4 | 2924 | |
4a5e8e29 JG |
2925 | if (pcnet32_have_pci) |
2926 | pci_unregister_driver(&pcnet32_driver); | |
1da177e4 LT |
2927 | } |
2928 | ||
2929 | module_init(pcnet32_init_module); | |
2930 | module_exit(pcnet32_cleanup_module); | |
2931 | ||
2932 | /* | |
2933 | * Local variables: | |
2934 | * c-indent-level: 4 | |
2935 | * tab-width: 8 | |
2936 | * End: | |
2937 | */ |