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net: amd-xgbe: Reset the PHY rx data path when mailbox command timeout
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-phy-v2.c
CommitLineData
47f164de
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
abf0a1c2 118#include <linux/device.h>
47f164de
LT		 119#include <linux/kmod.h>
120#include <linux/mdio.h>
121#include <linux/phy.h>
53a1024a 122#include <linux/ethtool.h>
47f164de
LT		 123
124#include "xgbe.h"
125#include "xgbe-common.h"
126
127#define XGBE_PHY_PORT_SPEED_100 BIT(0)
128#define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129#define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130#define XGBE_PHY_PORT_SPEED_10000 BIT(3)
131
abf0a1c2
LT		 132#define XGBE_MUTEX_RELEASE 0x80000000
133
134#define XGBE_SFP_DIRECT 7
135
136/* I2C target addresses */
137#define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138#define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139#define XGBE_SFP_PHY_ADDRESS 0x56
140#define XGBE_GPIO_ADDRESS_PCA9555 0x20
141
142/* SFP sideband signal indicators */
143#define XGBE_GPIO_NO_TX_FAULT BIT(0)
144#define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145#define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146#define XGBE_GPIO_NO_RX_LOS BIT(3)
147
47f164de
LT		 148/* Rate-change complete wait/retry count */
149#define XGBE_RATECHANGE_COUNT 500
150
96f4d430
TL		 151/* CDR delay values for KR support (in usec) */
152#define XGBE_CDR_DELAY_INIT 10000
153#define XGBE_CDR_DELAY_INC 10000
154#define XGBE_CDR_DELAY_MAX 100000
155
156/* RRC frequency during link status check */
157#define XGBE_RRC_FREQUENCY 10
158
47f164de
LT		 159enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
168 XGBE_PORT_MODE_SFP,
7deedd9f 169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
47f164de
LT		 170 XGBE_PORT_MODE_MAX,
171};
172
173enum xgbe_conn_type {
174 XGBE_CONN_TYPE_NONE = 0,
175 XGBE_CONN_TYPE_SFP,
176 XGBE_CONN_TYPE_MDIO,
5a4e4c8f 177 XGBE_CONN_TYPE_RSVD1,
47f164de
LT		 178 XGBE_CONN_TYPE_BACKPLANE,
179 XGBE_CONN_TYPE_MAX,
180};
181
abf0a1c2
LT		 182/* SFP/SFP+ related definitions */
183enum xgbe_sfp_comm {
184 XGBE_SFP_COMM_DIRECT = 0,
185 XGBE_SFP_COMM_PCA9545,
186};
187
188enum xgbe_sfp_cable {
189 XGBE_SFP_CABLE_UNKNOWN = 0,
190 XGBE_SFP_CABLE_ACTIVE,
191 XGBE_SFP_CABLE_PASSIVE,
192};
193
194enum xgbe_sfp_base {
195 XGBE_SFP_BASE_UNKNOWN = 0,
196 XGBE_SFP_BASE_1000_T,
197 XGBE_SFP_BASE_1000_SX,
198 XGBE_SFP_BASE_1000_LX,
199 XGBE_SFP_BASE_1000_CX,
200 XGBE_SFP_BASE_10000_SR,
201 XGBE_SFP_BASE_10000_LR,
202 XGBE_SFP_BASE_10000_LRM,
203 XGBE_SFP_BASE_10000_ER,
204 XGBE_SFP_BASE_10000_CR,
205};
206
207enum xgbe_sfp_speed {
208 XGBE_SFP_SPEED_UNKNOWN = 0,
209 XGBE_SFP_SPEED_100_1000,
210 XGBE_SFP_SPEED_1000,
211 XGBE_SFP_SPEED_10000,
212};
213
214/* SFP Serial ID Base ID values relative to an offset of 0 */
215#define XGBE_SFP_BASE_ID 0
216#define XGBE_SFP_ID_SFP 0x03
217
218#define XGBE_SFP_BASE_EXT_ID 1
219#define XGBE_SFP_EXT_ID_SFP 0x04
220
221#define XGBE_SFP_BASE_10GBE_CC 3
222#define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
223#define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
224#define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
225#define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
226
227#define XGBE_SFP_BASE_1GBE_CC 6
228#define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
229#define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
230#define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
231#define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
232
233#define XGBE_SFP_BASE_CABLE 8
234#define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
235#define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
236
237#define XGBE_SFP_BASE_BR 12
238#define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
239#define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
240#define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
241#define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
242
243#define XGBE_SFP_BASE_CU_CABLE_LEN 18
244
245#define XGBE_SFP_BASE_VENDOR_NAME 20
246#define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
247#define XGBE_SFP_BASE_VENDOR_PN 40
248#define XGBE_SFP_BASE_VENDOR_PN_LEN 16
249#define XGBE_SFP_BASE_VENDOR_REV 56
250#define XGBE_SFP_BASE_VENDOR_REV_LEN 4
251
252#define XGBE_SFP_BASE_CC 63
253
254/* SFP Serial ID Extended ID values relative to an offset of 64 */
255#define XGBE_SFP_BASE_VENDOR_SN 4
256#define XGBE_SFP_BASE_VENDOR_SN_LEN 16
257
117df655
TL		 258#define XGBE_SFP_EXTD_OPT1 1
259#define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
260#define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
261
abf0a1c2
LT		 262#define XGBE_SFP_EXTD_DIAG 28
263#define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
264
265#define XGBE_SFP_EXTD_SFF_8472 30
266
267#define XGBE_SFP_EXTD_CC 31
268
269struct xgbe_sfp_eeprom {
270 u8 base[64];
271 u8 extd[32];
272 u8 vendor[32];
273};
274
53a1024a
TL		 275#define XGBE_SFP_DIAGS_SUPPORTED(_x) \
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
278
279#define XGBE_SFP_EEPROM_BASE_LEN 256
280#define XGBE_SFP_EEPROM_DIAG_LEN 256
281#define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
282 XGBE_SFP_EEPROM_DIAG_LEN)
283
abf0a1c2
LT		 284#define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285#define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
286
287struct xgbe_sfp_ascii {
288 union {
289 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
290 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
291 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
292 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
293 } u;
294};
295
732f2ab7
LT		 296/* MDIO PHY reset types */
297enum xgbe_mdio_reset {
298 XGBE_MDIO_RESET_NONE = 0,
299 XGBE_MDIO_RESET_I2C_GPIO,
300 XGBE_MDIO_RESET_INT_GPIO,
301 XGBE_MDIO_RESET_MAX,
302};
303
d7445d1f
LT		 304/* Re-driver related definitions */
305enum xgbe_phy_redrv_if {
306 XGBE_PHY_REDRV_IF_MDIO = 0,
307 XGBE_PHY_REDRV_IF_I2C,
308 XGBE_PHY_REDRV_IF_MAX,
309};
310
311enum xgbe_phy_redrv_model {
312 XGBE_PHY_REDRV_MODEL_4223 = 0,
313 XGBE_PHY_REDRV_MODEL_4227,
314 XGBE_PHY_REDRV_MODEL_MAX,
315};
316
317enum xgbe_phy_redrv_mode {
318 XGBE_PHY_REDRV_MODE_CX = 5,
319 XGBE_PHY_REDRV_MODE_SR = 9,
320};
321
322#define XGBE_PHY_REDRV_MODE_REG 0x12b0
323
abf0a1c2
LT		 324/* PHY related configuration information */
325struct xgbe_phy_data {
326 enum xgbe_port_mode port_mode;
327
328 unsigned int port_id;
329
330 unsigned int port_speeds;
331
332 enum xgbe_conn_type conn_type;
333
334 enum xgbe_mode cur_mode;
335 enum xgbe_mode start_mode;
336
337 unsigned int rrc_count;
338
339 unsigned int mdio_addr;
340
abf0a1c2
LT		 341 /* SFP Support */
342 enum xgbe_sfp_comm sfp_comm;
343 unsigned int sfp_mux_address;
344 unsigned int sfp_mux_channel;
345
346 unsigned int sfp_gpio_address;
347 unsigned int sfp_gpio_mask;
117df655 348 unsigned int sfp_gpio_inputs;
abf0a1c2
LT		 349 unsigned int sfp_gpio_rx_los;
350 unsigned int sfp_gpio_tx_fault;
351 unsigned int sfp_gpio_mod_absent;
352 unsigned int sfp_gpio_rate_select;
353
354 unsigned int sfp_rx_los;
355 unsigned int sfp_tx_fault;
356 unsigned int sfp_mod_absent;
abf0a1c2
LT		 357 unsigned int sfp_changed;
358 unsigned int sfp_phy_avail;
359 unsigned int sfp_cable_len;
360 enum xgbe_sfp_base sfp_base;
361 enum xgbe_sfp_cable sfp_cable;
362 enum xgbe_sfp_speed sfp_speed;
363 struct xgbe_sfp_eeprom sfp_eeprom;
364
365 /* External PHY support */
366 enum xgbe_mdio_mode phydev_mode;
367 struct mii_bus *mii;
368 struct phy_device *phydev;
732f2ab7
LT		 369 enum xgbe_mdio_reset mdio_reset;
370 unsigned int mdio_reset_addr;
371 unsigned int mdio_reset_gpio;
d7445d1f
LT		 372
373 /* Re-driver support */
374 unsigned int redrv;
375 unsigned int redrv_if;
376 unsigned int redrv_addr;
377 unsigned int redrv_lane;
378 unsigned int redrv_model;
96f4d430
TL		 379
380 /* KR AN support */
381 unsigned int phy_cdr_notrack;
382 unsigned int phy_cdr_delay;
abf0a1c2
LT		 383};
384
385/* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
386static DEFINE_MUTEX(xgbe_phy_comm_lock);
387
388static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
389
390static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
391 struct xgbe_i2c_op *i2c_op)
392{
abf0a1c2
LT		 393 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
394}
395
d7445d1f
LT		 396static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
397 unsigned int val)
398{
399 struct xgbe_phy_data *phy_data = pdata->phy_data;
400 struct xgbe_i2c_op i2c_op;
401 __be16 *redrv_val;
402 u8 redrv_data[5], csum;
403 unsigned int i, retry;
404 int ret;
405
406 /* High byte of register contains read/write indicator */
407 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
408 redrv_data[1] = reg & 0xff;
409 redrv_val = (__be16 *)&redrv_data[2];
410 *redrv_val = cpu_to_be16(val);
411
412 /* Calculate 1 byte checksum */
413 csum = 0;
414 for (i = 0; i < 4; i++) {
415 csum += redrv_data[i];
416 if (redrv_data[i] > csum)
417 csum++;
418 }
419 redrv_data[4] = ~csum;
420
421 retry = 1;
422again1:
423 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
424 i2c_op.target = phy_data->redrv_addr;
425 i2c_op.len = sizeof(redrv_data);
426 i2c_op.buf = redrv_data;
427 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
428 if (ret) {
429 if ((ret == -EAGAIN) && retry--)
430 goto again1;
431
432 return ret;
433 }
434
435 retry = 1;
436again2:
437 i2c_op.cmd = XGBE_I2C_CMD_READ;
438 i2c_op.target = phy_data->redrv_addr;
439 i2c_op.len = 1;
440 i2c_op.buf = redrv_data;
441 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
442 if (ret) {
443 if ((ret == -EAGAIN) && retry--)
444 goto again2;
445
446 return ret;
447 }
448
449 if (redrv_data[0] != 0xff) {
450 netif_dbg(pdata, drv, pdata->netdev,
451 "Redriver write checksum error\n");
452 ret = -EIO;
453 }
454
455 return ret;
456}
457
abf0a1c2
LT		 458static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
459 void *val, unsigned int val_len)
460{
461 struct xgbe_i2c_op i2c_op;
462 int retry, ret;
463
464 retry = 1;
465again:
466 /* Write the specfied register */
467 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
468 i2c_op.target = target;
469 i2c_op.len = val_len;
470 i2c_op.buf = val;
471 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
472 if ((ret == -EAGAIN) && retry--)
473 goto again;
474
475 return ret;
476}
477
478static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
479 void *reg, unsigned int reg_len,
480 void *val, unsigned int val_len)
481{
482 struct xgbe_i2c_op i2c_op;
483 int retry, ret;
484
485 retry = 1;
486again1:
487 /* Set the specified register to read */
488 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
489 i2c_op.target = target;
490 i2c_op.len = reg_len;
491 i2c_op.buf = reg;
492 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
493 if (ret) {
494 if ((ret == -EAGAIN) && retry--)
495 goto again1;
496
497 return ret;
498 }
499
500 retry = 1;
501again2:
502 /* Read the specfied register */
503 i2c_op.cmd = XGBE_I2C_CMD_READ;
504 i2c_op.target = target;
505 i2c_op.len = val_len;
506 i2c_op.buf = val;
507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
508 if ((ret == -EAGAIN) && retry--)
509 goto again2;
510
511 return ret;
512}
513
514static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
515{
516 struct xgbe_phy_data *phy_data = pdata->phy_data;
517 struct xgbe_i2c_op i2c_op;
518 u8 mux_channel;
519
520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
521 return 0;
522
523 /* Select no mux channels */
524 mux_channel = 0;
525 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
526 i2c_op.target = phy_data->sfp_mux_address;
527 i2c_op.len = sizeof(mux_channel);
528 i2c_op.buf = &mux_channel;
529
530 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
531}
532
533static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
534{
535 struct xgbe_phy_data *phy_data = pdata->phy_data;
536 struct xgbe_i2c_op i2c_op;
537 u8 mux_channel;
538
539 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
540 return 0;
541
542 /* Select desired mux channel */
543 mux_channel = 1 << phy_data->sfp_mux_channel;
544 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
545 i2c_op.target = phy_data->sfp_mux_address;
546 i2c_op.len = sizeof(mux_channel);
547 i2c_op.buf = &mux_channel;
548
549 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
550}
551
552static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
553{
abf0a1c2
LT		 554 mutex_unlock(&xgbe_phy_comm_lock);
555}
556
557static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
558{
559 struct xgbe_phy_data *phy_data = pdata->phy_data;
560 unsigned long timeout;
561 unsigned int mutex_id;
562
abf0a1c2
LT		 563 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
564 * the driver needs to take the software mutex and then the hardware
565 * mutexes before being able to use the busses.
566 */
567 mutex_lock(&xgbe_phy_comm_lock);
568
569 /* Clear the mutexes */
570 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
571 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
572
573 /* Mutex formats are the same for I2C and MDIO/GPIO */
574 mutex_id = 0;
575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
577
578 timeout = jiffies + (5 * HZ);
579 while (time_before(jiffies, timeout)) {
580 /* Must be all zeroes in order to obtain the mutex */
581 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
582 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
583 usleep_range(100, 200);
584 continue;
585 }
586
587 /* Obtain the mutex */
588 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
589 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
590
abf0a1c2
LT		 591 return 0;
592 }
593
594 mutex_unlock(&xgbe_phy_comm_lock);
595
596 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
597
598 return -ETIMEDOUT;
599}
600
732f2ab7
LT		 601static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
602 int reg, u16 val)
603{
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
605
606 if (reg & MII_ADDR_C45) {
607 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
608 return -ENOTSUPP;
609 } else {
610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
611 return -ENOTSUPP;
612 }
613
614 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
615}
616
abf0a1c2
LT		 617static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
618{
619 __be16 *mii_val;
620 u8 mii_data[3];
621 int ret;
622
623 ret = xgbe_phy_sfp_get_mux(pdata);
624 if (ret)
625 return ret;
626
627 mii_data[0] = reg & 0xff;
628 mii_val = (__be16 *)&mii_data[1];
629 *mii_val = cpu_to_be16(val);
630
631 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
632 mii_data, sizeof(mii_data));
633
634 xgbe_phy_sfp_put_mux(pdata);
635
636 return ret;
637}
638
639static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
640{
641 struct xgbe_prv_data *pdata = mii->priv;
642 struct xgbe_phy_data *phy_data = pdata->phy_data;
643 int ret;
644
645 ret = xgbe_phy_get_comm_ownership(pdata);
646 if (ret)
647 return ret;
648
649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
650 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
732f2ab7
LT		 651 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
652 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
abf0a1c2
LT		 653 else
654 ret = -ENOTSUPP;
655
656 xgbe_phy_put_comm_ownership(pdata);
657
658 return ret;
659}
660
732f2ab7
LT		 661static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
662 int reg)
663{
664 struct xgbe_phy_data *phy_data = pdata->phy_data;
665
666 if (reg & MII_ADDR_C45) {
667 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
668 return -ENOTSUPP;
669 } else {
670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
671 return -ENOTSUPP;
672 }
673
674 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
675}
676
abf0a1c2
LT		 677static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
678{
679 __be16 mii_val;
680 u8 mii_reg;
681 int ret;
682
683 ret = xgbe_phy_sfp_get_mux(pdata);
684 if (ret)
685 return ret;
686
687 mii_reg = reg;
688 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
689 &mii_reg, sizeof(mii_reg),
690 &mii_val, sizeof(mii_val));
691 if (!ret)
692 ret = be16_to_cpu(mii_val);
693
694 xgbe_phy_sfp_put_mux(pdata);
695
696 return ret;
697}
698
699static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
700{
701 struct xgbe_prv_data *pdata = mii->priv;
702 struct xgbe_phy_data *phy_data = pdata->phy_data;
703 int ret;
704
705 ret = xgbe_phy_get_comm_ownership(pdata);
706 if (ret)
707 return ret;
708
709 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
710 ret = xgbe_phy_i2c_mii_read(pdata, reg);
732f2ab7
LT		 711 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
712 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
abf0a1c2
LT		 713 else
714 ret = -ENOTSUPP;
715
716 xgbe_phy_put_comm_ownership(pdata);
717
718 return ret;
719}
720
721static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
722{
85f9feb6 723 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2
LT		 724 struct xgbe_phy_data *phy_data = pdata->phy_data;
725
56503d55
LT		 726 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
727 return;
728
85f9feb6 729 XGBE_ZERO_SUP(lks);
56503d55 730
abf0a1c2
LT		 731 if (phy_data->sfp_mod_absent) {
732 pdata->phy.speed = SPEED_UNKNOWN;
733 pdata->phy.duplex = DUPLEX_UNKNOWN;
734 pdata->phy.autoneg = AUTONEG_ENABLE;
56503d55
LT		 735 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
736
85f9feb6
LT		 737 XGBE_SET_SUP(lks, Autoneg);
738 XGBE_SET_SUP(lks, Pause);
739 XGBE_SET_SUP(lks, Asym_Pause);
740 XGBE_SET_SUP(lks, TP);
741 XGBE_SET_SUP(lks, FIBRE);
56503d55 742
85f9feb6 743 XGBE_LM_COPY(lks, advertising, lks, supported);
2697ea5a
LT		 744
745 return;
abf0a1c2
LT		 746 }
747
abf0a1c2
LT		 748 switch (phy_data->sfp_base) {
749 case XGBE_SFP_BASE_1000_T:
750 case XGBE_SFP_BASE_1000_SX:
751 case XGBE_SFP_BASE_1000_LX:
752 case XGBE_SFP_BASE_1000_CX:
753 pdata->phy.speed = SPEED_UNKNOWN;
754 pdata->phy.duplex = DUPLEX_UNKNOWN;
755 pdata->phy.autoneg = AUTONEG_ENABLE;
56503d55 756 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
85f9feb6
LT		 757 XGBE_SET_SUP(lks, Autoneg);
758 XGBE_SET_SUP(lks, Pause);
759 XGBE_SET_SUP(lks, Asym_Pause);
760 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
761 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
762 XGBE_SET_SUP(lks, 100baseT_Full);
763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
764 XGBE_SET_SUP(lks, 1000baseT_Full);
765 } else {
766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
767 XGBE_SET_SUP(lks, 1000baseX_Full);
768 }
abf0a1c2
LT		 769 break;
770 case XGBE_SFP_BASE_10000_SR:
771 case XGBE_SFP_BASE_10000_LR:
772 case XGBE_SFP_BASE_10000_LRM:
773 case XGBE_SFP_BASE_10000_ER:
774 case XGBE_SFP_BASE_10000_CR:
abf0a1c2
LT		 775 pdata->phy.speed = SPEED_10000;
776 pdata->phy.duplex = DUPLEX_FULL;
777 pdata->phy.autoneg = AUTONEG_DISABLE;
56503d55 778 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
85f9feb6
LT		 779 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
780 switch (phy_data->sfp_base) {
781 case XGBE_SFP_BASE_10000_SR:
782 XGBE_SET_SUP(lks, 10000baseSR_Full);
783 break;
784 case XGBE_SFP_BASE_10000_LR:
785 XGBE_SET_SUP(lks, 10000baseLR_Full);
786 break;
787 case XGBE_SFP_BASE_10000_LRM:
788 XGBE_SET_SUP(lks, 10000baseLRM_Full);
789 break;
790 case XGBE_SFP_BASE_10000_ER:
791 XGBE_SET_SUP(lks, 10000baseER_Full);
792 break;
793 case XGBE_SFP_BASE_10000_CR:
794 XGBE_SET_SUP(lks, 10000baseCR_Full);
795 break;
796 default:
797 break;
798 }
799 }
56503d55
LT		 800 break;
801 default:
802 pdata->phy.speed = SPEED_UNKNOWN;
803 pdata->phy.duplex = DUPLEX_UNKNOWN;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
abf0a1c2
LT		 806 break;
807 }
808
809 switch (phy_data->sfp_base) {
810 case XGBE_SFP_BASE_1000_T:
811 case XGBE_SFP_BASE_1000_CX:
812 case XGBE_SFP_BASE_10000_CR:
85f9feb6 813 XGBE_SET_SUP(lks, TP);
abf0a1c2
LT		 814 break;
815 default:
85f9feb6 816 XGBE_SET_SUP(lks, FIBRE);
abf0a1c2 817 break;
abf0a1c2 818 }
56503d55 819
85f9feb6 820 XGBE_LM_COPY(lks, advertising, lks, supported);
abf0a1c2
LT		 821}
822
823static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
824 enum xgbe_sfp_speed sfp_speed)
825{
826 u8 *sfp_base, min, max;
827
828 sfp_base = sfp_eeprom->base;
829
830 switch (sfp_speed) {
831 case XGBE_SFP_SPEED_1000:
832 min = XGBE_SFP_BASE_BR_1GBE_MIN;
833 max = XGBE_SFP_BASE_BR_1GBE_MAX;
834 break;
835 case XGBE_SFP_SPEED_10000:
836 min = XGBE_SFP_BASE_BR_10GBE_MIN;
837 max = XGBE_SFP_BASE_BR_10GBE_MAX;
838 break;
839 default:
840 return false;
841 }
842
843 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
844 (sfp_base[XGBE_SFP_BASE_BR] <= max));
845}
846
847static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
848{
849 struct xgbe_phy_data *phy_data = pdata->phy_data;
850
851 if (phy_data->phydev) {
852 phy_detach(phy_data->phydev);
853 phy_device_remove(phy_data->phydev);
854 phy_device_free(phy_data->phydev);
855 phy_data->phydev = NULL;
856 }
857}
858
859static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
860{
3c1bcc86 861 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
abf0a1c2
LT		 862 struct xgbe_phy_data *phy_data = pdata->phy_data;
863 unsigned int phy_id = phy_data->phydev->phy_id;
864
e722ec82
TL		 865 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
866 return false;
867
abf0a1c2
LT		 868 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
869 return false;
870
871 /* Enable Base-T AN */
872 phy_write(phy_data->phydev, 0x16, 0x0001);
873 phy_write(phy_data->phydev, 0x00, 0x9140);
874 phy_write(phy_data->phydev, 0x16, 0x0000);
875
876 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
877 phy_write(phy_data->phydev, 0x1b, 0x9084);
878 phy_write(phy_data->phydev, 0x09, 0x0e00);
879 phy_write(phy_data->phydev, 0x00, 0x8140);
880 phy_write(phy_data->phydev, 0x04, 0x0d01);
881 phy_write(phy_data->phydev, 0x00, 0x9140);
882
3c1bcc86
AL		 883 linkmode_set_bit_array(phy_10_100_features_array,
884 ARRAY_SIZE(phy_10_100_features_array),
885 supported);
886 linkmode_set_bit_array(phy_gbit_features_array,
887 ARRAY_SIZE(phy_gbit_features_array),
888 supported);
889
890 linkmode_copy(phy_data->phydev->supported, supported);
891
af8d9bb2 892 phy_support_asym_pause(phy_data->phydev);
abf0a1c2
LT		 893
894 netif_dbg(pdata, drv, pdata->netdev,
895 "Finisar PHY quirk in place\n");
896
897 return true;
898}
899
e722ec82
TL		 900static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
901{
3c1bcc86 902 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
e722ec82
TL		 903 struct xgbe_phy_data *phy_data = pdata->phy_data;
904 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
905 unsigned int phy_id = phy_data->phydev->phy_id;
906 int reg;
907
908 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
909 return false;
910
911 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
912 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
913 return false;
914
76cce0af
TL		 915 /* For Bel-Fuse, use the extra AN flag */
916 pdata->an_again = 1;
917
e722ec82
TL		 918 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
919 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
920 return false;
921
922 if ((phy_id & 0xfffffff0) != 0x03625d10)
923 return false;
924
925 /* Disable RGMII mode */
926 phy_write(phy_data->phydev, 0x18, 0x7007);
927 reg = phy_read(phy_data->phydev, 0x18);
928 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
929
930 /* Enable fiber register bank */
931 phy_write(phy_data->phydev, 0x1c, 0x7c00);
932 reg = phy_read(phy_data->phydev, 0x1c);
933 reg &= 0x03ff;
934 reg &= ~0x0001;
935 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
936
937 /* Power down SerDes */
938 reg = phy_read(phy_data->phydev, 0x00);
939 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
940
941 /* Configure SGMII-to-Copper mode */
942 phy_write(phy_data->phydev, 0x1c, 0x7c00);
943 reg = phy_read(phy_data->phydev, 0x1c);
944 reg &= 0x03ff;
945 reg &= ~0x0006;
946 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
947
948 /* Power up SerDes */
949 reg = phy_read(phy_data->phydev, 0x00);
950 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
951
952 /* Enable copper register bank */
953 phy_write(phy_data->phydev, 0x1c, 0x7c00);
954 reg = phy_read(phy_data->phydev, 0x1c);
955 reg &= 0x03ff;
956 reg &= ~0x0001;
957 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
958
959 /* Power up SerDes */
960 reg = phy_read(phy_data->phydev, 0x00);
961 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
962
3c1bcc86
AL		 963 linkmode_set_bit_array(phy_10_100_features_array,
964 ARRAY_SIZE(phy_10_100_features_array),
965 supported);
966 linkmode_set_bit_array(phy_gbit_features_array,
967 ARRAY_SIZE(phy_gbit_features_array),
968 supported);
969 linkmode_copy(phy_data->phydev->supported, supported);
af8d9bb2 970 phy_support_asym_pause(phy_data->phydev);
e722ec82
TL		 971
972 netif_dbg(pdata, drv, pdata->netdev,
973 "BelFuse PHY quirk in place\n");
974
975 return true;
976}
977
abf0a1c2
LT		 978static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
979{
e722ec82
TL		 980 if (xgbe_phy_belfuse_phy_quirks(pdata))
981 return;
982
abf0a1c2
LT		 983 if (xgbe_phy_finisar_phy_quirks(pdata))
984 return;
985}
986
987static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
988{
85f9feb6 989 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2
LT		 990 struct xgbe_phy_data *phy_data = pdata->phy_data;
991 struct phy_device *phydev;
992 int ret;
993
994 /* If we already have a PHY, just return */
995 if (phy_data->phydev)
996 return 0;
997
76cce0af
TL		 998 /* Clear the extra AN flag */
999 pdata->an_again = 0;
1000
abf0a1c2
LT		 1001 /* Check for the use of an external PHY */
1002 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1003 return 0;
1004
1005 /* For SFP, only use an external PHY if available */
1006 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1007 !phy_data->sfp_phy_avail)
1008 return 0;
1009
b42c6761
LT		 1010 /* Set the proper MDIO mode for the PHY */
1011 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1012 phy_data->phydev_mode);
1013 if (ret) {
1014 netdev_err(pdata->netdev,
1015 "mdio port/clause not compatible (%u/%u)\n",
1016 phy_data->mdio_addr, phy_data->phydev_mode);
1017 return ret;
1018 }
1019
abf0a1c2
LT		 1020 /* Create and connect to the PHY device */
1021 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1022 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1023 if (IS_ERR(phydev)) {
1024 netdev_err(pdata->netdev, "get_phy_device failed\n");
1025 return -ENODEV;
1026 }
1027 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1028 phydev->phy_id);
1029
1030 /*TODO: If c45, add request_module based on one of the MMD ids? */
1031
1032 ret = phy_device_register(phydev);
1033 if (ret) {
1034 netdev_err(pdata->netdev, "phy_device_register failed\n");
1035 phy_device_free(phydev);
1036 return ret;
1037 }
1038
1039 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1040 PHY_INTERFACE_MODE_SGMII);
1041 if (ret) {
1042 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1043 phy_device_remove(phydev);
1044 phy_device_free(phydev);
1045 return ret;
1046 }
1047 phy_data->phydev = phydev;
1048
1049 xgbe_phy_external_phy_quirks(pdata);
85f9feb6 1050
3c1bcc86
AL		 1051 linkmode_and(phydev->advertising, phydev->advertising,
1052 lks->link_modes.advertising);
abf0a1c2
LT		 1053
1054 phy_start_aneg(phy_data->phydev);
1055
1056 return 0;
1057}
1058
1059static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1060{
1061 struct xgbe_phy_data *phy_data = pdata->phy_data;
1062 int ret;
1063
1064 if (!phy_data->sfp_changed)
1065 return;
1066
1067 phy_data->sfp_phy_avail = 0;
1068
1069 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1070 return;
1071
1072 /* Check access to the PHY by reading CTRL1 */
1073 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1074 if (ret < 0)
1075 return;
1076
1077 /* Successfully accessed the PHY */
1078 phy_data->sfp_phy_avail = 1;
1079}
1080
117df655
TL		 1081static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1082{
1083 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1084
1085 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1086 return false;
1087
1088 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1089 return false;
1090
1091 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1092 return true;
1093
1094 return false;
1095}
1096
1097static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1098{
1099 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1100
1101 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1102 return false;
1103
1104 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1105 return false;
1106
1107 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1108 return true;
1109
1110 return false;
1111}
1112
1113static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1114{
1115 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1116 return false;
1117
1118 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1119 return true;
1120
1121 return false;
1122}
1123
abf0a1c2
LT		 1124static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1125{
1126 struct xgbe_phy_data *phy_data = pdata->phy_data;
1127 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1128 u8 *sfp_base;
1129
1130 sfp_base = sfp_eeprom->base;
1131
1132 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1133 return;
1134
1135 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1136 return;
1137
117df655
TL		 1138 /* Update transceiver signals (eeprom extd/options) */
1139 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1140 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1141
abf0a1c2
LT		 1142 /* Assume ACTIVE cable unless told it is PASSIVE */
1143 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1144 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1145 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1146 } else {
1147 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1148 }
1149
1150 /* Determine the type of SFP */
1151 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1152 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1153 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1154 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1155 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1156 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1157 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1158 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1159 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1160 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1161 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1162 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1163 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1164 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1165 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1166 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1167 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1168 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1169 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1170
1171 switch (phy_data->sfp_base) {
1172 case XGBE_SFP_BASE_1000_T:
1173 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1174 break;
1175 case XGBE_SFP_BASE_1000_SX:
1176 case XGBE_SFP_BASE_1000_LX:
1177 case XGBE_SFP_BASE_1000_CX:
1178 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1179 break;
1180 case XGBE_SFP_BASE_10000_SR:
1181 case XGBE_SFP_BASE_10000_LR:
1182 case XGBE_SFP_BASE_10000_LRM:
1183 case XGBE_SFP_BASE_10000_ER:
1184 case XGBE_SFP_BASE_10000_CR:
1185 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1186 break;
1187 default:
1188 break;
1189 }
1190}
1191
1192static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1193 struct xgbe_sfp_eeprom *sfp_eeprom)
1194{
1195 struct xgbe_sfp_ascii sfp_ascii;
1196 char *sfp_data = (char *)&sfp_ascii;
1197
1198 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1199 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1200 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1201 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1202 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1203 sfp_data);
1204
1205 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1206 XGBE_SFP_BASE_VENDOR_PN_LEN);
1207 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1208 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1209 sfp_data);
1210
1211 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1212 XGBE_SFP_BASE_VENDOR_REV_LEN);
1213 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1214 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1215 sfp_data);
1216
1217 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1218 XGBE_SFP_BASE_VENDOR_SN_LEN);
1219 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1220 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1221 sfp_data);
1222}
1223
1224static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1225{
1226 u8 cc;
1227
1228 for (cc = 0; len; buf++, len--)
1229 cc += *buf;
1230
ab9837b5 1231 return cc == cc_in;
abf0a1c2
LT		 1232}
1233
1234static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1235{
1236 struct xgbe_phy_data *phy_data = pdata->phy_data;
1237 struct xgbe_sfp_eeprom sfp_eeprom;
1238 u8 eeprom_addr;
1239 int ret;
1240
1241 ret = xgbe_phy_sfp_get_mux(pdata);
1242 if (ret) {
45a2005e
LT		 1243 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1244 netdev_name(pdata->netdev));
abf0a1c2
LT		 1245 return ret;
1246 }
1247
1248 /* Read the SFP serial ID eeprom */
1249 eeprom_addr = 0;
1250 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1251 &eeprom_addr, sizeof(eeprom_addr),
1252 &sfp_eeprom, sizeof(sfp_eeprom));
1253 if (ret) {
45a2005e
LT		 1254 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1255 netdev_name(pdata->netdev));
abf0a1c2
LT		 1256 goto put;
1257 }
1258
1259 /* Validate the contents read */
1260 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1261 sfp_eeprom.base,
1262 sizeof(sfp_eeprom.base) - 1)) {
1263 ret = -EINVAL;
1264 goto put;
1265 }
1266
1267 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1268 sfp_eeprom.extd,
1269 sizeof(sfp_eeprom.extd) - 1)) {
1270 ret = -EINVAL;
1271 goto put;
1272 }
1273
1274 /* Check for an added or changed SFP */
1275 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1276 phy_data->sfp_changed = 1;
1277
1278 if (netif_msg_drv(pdata))
1279 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1280
1281 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1282
abf0a1c2
LT		 1283 xgbe_phy_free_phy_device(pdata);
1284 } else {
1285 phy_data->sfp_changed = 0;
1286 }
1287
1288put:
1289 xgbe_phy_sfp_put_mux(pdata);
1290
1291 return ret;
1292}
1293
1294static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1295{
1296 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2
LT		 1297 u8 gpio_reg, gpio_ports[2];
1298 int ret;
1299
1300 /* Read the input port registers */
1301 gpio_reg = 0;
1302 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1303 &gpio_reg, sizeof(gpio_reg),
1304 gpio_ports, sizeof(gpio_ports));
1305 if (ret) {
45a2005e
LT		 1306 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1307 netdev_name(pdata->netdev));
abf0a1c2
LT		 1308 return;
1309 }
1310
117df655 1311 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
abf0a1c2 1312
117df655 1313 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
abf0a1c2
LT		 1314}
1315
1316static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1317{
1318 struct xgbe_phy_data *phy_data = pdata->phy_data;
1319
1320 xgbe_phy_free_phy_device(pdata);
1321
1322 phy_data->sfp_mod_absent = 1;
1323 phy_data->sfp_phy_avail = 0;
1324 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1325}
1326
1327static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1328{
1329 phy_data->sfp_rx_los = 0;
1330 phy_data->sfp_tx_fault = 0;
1331 phy_data->sfp_mod_absent = 1;
abf0a1c2
LT		 1332 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1333 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1334 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1335}
1336
1337static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1338{
1339 struct xgbe_phy_data *phy_data = pdata->phy_data;
1340 int ret;
1341
1342 /* Reset the SFP signals and info */
1343 xgbe_phy_sfp_reset(phy_data);
1344
1345 ret = xgbe_phy_get_comm_ownership(pdata);
1346 if (ret)
1347 return;
1348
1349 /* Read the SFP signals and check for module presence */
1350 xgbe_phy_sfp_signals(pdata);
1351 if (phy_data->sfp_mod_absent) {
1352 xgbe_phy_sfp_mod_absent(pdata);
1353 goto put;
1354 }
1355
1356 ret = xgbe_phy_sfp_read_eeprom(pdata);
1357 if (ret) {
1358 /* Treat any error as if there isn't an SFP plugged in */
1359 xgbe_phy_sfp_reset(phy_data);
1360 xgbe_phy_sfp_mod_absent(pdata);
1361 goto put;
1362 }
1363
1364 xgbe_phy_sfp_parse_eeprom(pdata);
1365
1366 xgbe_phy_sfp_external_phy(pdata);
1367
1368put:
1369 xgbe_phy_sfp_phy_settings(pdata);
1370
1371 xgbe_phy_put_comm_ownership(pdata);
1372}
1373
53a1024a
TL		 1374static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1375 struct ethtool_eeprom *eeprom, u8 *data)
1376{
1377 struct xgbe_phy_data *phy_data = pdata->phy_data;
1378 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1379 struct xgbe_sfp_eeprom *sfp_eeprom;
1380 unsigned int i, j, rem;
1381 int ret;
1382
1383 rem = eeprom->len;
1384
1385 if (!eeprom->len) {
1386 ret = -EINVAL;
1387 goto done;
1388 }
1389
1390 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1391 ret = -EINVAL;
1392 goto done;
1393 }
1394
1395 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1396 ret = -ENXIO;
1397 goto done;
1398 }
1399
1400 if (!netif_running(pdata->netdev)) {
1401 ret = -EIO;
1402 goto done;
1403 }
1404
1405 if (phy_data->sfp_mod_absent) {
1406 ret = -EIO;
1407 goto done;
1408 }
1409
1410 ret = xgbe_phy_get_comm_ownership(pdata);
1411 if (ret) {
1412 ret = -EIO;
1413 goto done;
1414 }
1415
1416 ret = xgbe_phy_sfp_get_mux(pdata);
1417 if (ret) {
1418 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1419 ret = -EIO;
1420 goto put_own;
1421 }
1422
1423 /* Read the SFP serial ID eeprom */
1424 eeprom_addr = 0;
1425 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1426 &eeprom_addr, sizeof(eeprom_addr),
1427 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1428 if (ret) {
1429 netdev_err(pdata->netdev,
1430 "I2C error reading SFP EEPROM\n");
1431 ret = -EIO;
1432 goto put_mux;
1433 }
1434
1435 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1436
1437 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1438 /* Read the SFP diagnostic eeprom */
1439 eeprom_addr = 0;
1440 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1441 &eeprom_addr, sizeof(eeprom_addr),
1442 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1443 XGBE_SFP_EEPROM_DIAG_LEN);
1444 if (ret) {
1445 netdev_err(pdata->netdev,
1446 "I2C error reading SFP DIAGS\n");
1447 ret = -EIO;
1448 goto put_mux;
1449 }
1450 }
1451
1452 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1453 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1454 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1455 break;
1456
1457 data[i] = eeprom_data[j];
1458 rem--;
1459 }
1460
1461put_mux:
1462 xgbe_phy_sfp_put_mux(pdata);
1463
1464put_own:
1465 xgbe_phy_put_comm_ownership(pdata);
1466
1467done:
1468 eeprom->len -= rem;
1469
1470 return ret;
1471}
1472
1473static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1474 struct ethtool_modinfo *modinfo)
1475{
1476 struct xgbe_phy_data *phy_data = pdata->phy_data;
1477
1478 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1479 return -ENXIO;
1480
1481 if (!netif_running(pdata->netdev))
1482 return -EIO;
1483
1484 if (phy_data->sfp_mod_absent)
1485 return -EIO;
1486
1487 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1488 modinfo->type = ETH_MODULE_SFF_8472;
1489 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1490 } else {
1491 modinfo->type = ETH_MODULE_SFF_8079;
1492 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1493 }
1494
1495 return 0;
1496}
1497
d7445d1f 1498static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
abf0a1c2 1499{
85f9feb6 1500 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2 1501 struct xgbe_phy_data *phy_data = pdata->phy_data;
d7445d1f
LT		 1502 u16 lcl_adv = 0, rmt_adv = 0;
1503 u8 fc;
abf0a1c2 1504
d7445d1f
LT		 1505 pdata->phy.tx_pause = 0;
1506 pdata->phy.rx_pause = 0;
abf0a1c2 1507
d7445d1f
LT		 1508 if (!phy_data->phydev)
1509 return;
abf0a1c2 1510
3c1bcc86 1511 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
abf0a1c2 1512
d7445d1f 1513 if (phy_data->phydev->pause) {
85f9feb6 1514 XGBE_SET_LP_ADV(lks, Pause);
d7445d1f
LT		 1515 rmt_adv |= LPA_PAUSE_CAP;
1516 }
1517 if (phy_data->phydev->asym_pause) {
85f9feb6 1518 XGBE_SET_LP_ADV(lks, Asym_Pause);
d7445d1f
LT		 1519 rmt_adv |= LPA_PAUSE_ASYM;
1520 }
abf0a1c2 1521
d7445d1f
LT		 1522 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1523 if (fc & FLOW_CTRL_TX)
1524 pdata->phy.tx_pause = 1;
1525 if (fc & FLOW_CTRL_RX)
1526 pdata->phy.rx_pause = 1;
1527}
abf0a1c2 1528
d7445d1f
LT		 1529static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1530{
85f9feb6 1531 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
d7445d1f
LT		 1532 enum xgbe_mode mode;
1533
85f9feb6
LT		 1534 XGBE_SET_LP_ADV(lks, Autoneg);
1535 XGBE_SET_LP_ADV(lks, TP);
d7445d1f
LT		 1536
1537 /* Use external PHY to determine flow control */
1538 if (pdata->phy.pause_autoneg)
1539 xgbe_phy_phydev_flowctrl(pdata);
abf0a1c2
LT		 1540
1541 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1542 case XGBE_SGMII_AN_LINK_SPEED_100:
1543 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
85f9feb6 1544 XGBE_SET_LP_ADV(lks, 100baseT_Full);
abf0a1c2
LT		 1545 mode = XGBE_MODE_SGMII_100;
1546 } else {
1547 /* Half-duplex not supported */
85f9feb6 1548 XGBE_SET_LP_ADV(lks, 100baseT_Half);
abf0a1c2
LT		 1549 mode = XGBE_MODE_UNKNOWN;
1550 }
1551 break;
1552 case XGBE_SGMII_AN_LINK_SPEED_1000:
1553 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
85f9feb6 1554 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
abf0a1c2
LT		 1555 mode = XGBE_MODE_SGMII_1000;
1556 } else {
1557 /* Half-duplex not supported */
85f9feb6 1558 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
abf0a1c2
LT		 1559 mode = XGBE_MODE_UNKNOWN;
1560 }
1561 break;
1562 default:
1563 mode = XGBE_MODE_UNKNOWN;
1564 }
1565
1566 return mode;
1567}
1568
1569static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1570{
85f9feb6 1571 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2
LT		 1572 enum xgbe_mode mode;
1573 unsigned int ad_reg, lp_reg;
1574
85f9feb6
LT		 1575 XGBE_SET_LP_ADV(lks, Autoneg);
1576 XGBE_SET_LP_ADV(lks, FIBRE);
abf0a1c2
LT		 1577
1578 /* Compare Advertisement and Link Partner register */
1579 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1580 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1581 if (lp_reg & 0x100)
85f9feb6 1582 XGBE_SET_LP_ADV(lks, Pause);
abf0a1c2 1583 if (lp_reg & 0x80)
85f9feb6 1584 XGBE_SET_LP_ADV(lks, Asym_Pause);
47f164de 1585
abf0a1c2
LT		 1586 if (pdata->phy.pause_autoneg) {
1587 /* Set flow control based on auto-negotiation result */
1588 pdata->phy.tx_pause = 0;
1589 pdata->phy.rx_pause = 0;
47f164de 1590
abf0a1c2
LT		 1591 if (ad_reg & lp_reg & 0x100) {
1592 pdata->phy.tx_pause = 1;
1593 pdata->phy.rx_pause = 1;
1594 } else if (ad_reg & lp_reg & 0x80) {
1595 if (ad_reg & 0x100)
1596 pdata->phy.rx_pause = 1;
1597 else if (lp_reg & 0x100)
1598 pdata->phy.tx_pause = 1;
1599 }
1600 }
47f164de 1601
abf0a1c2 1602 if (lp_reg & 0x20)
85f9feb6 1603 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
47f164de 1604
abf0a1c2
LT		 1605 /* Half duplex is not supported */
1606 ad_reg &= lp_reg;
1607 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
47f164de 1608
abf0a1c2
LT		 1609 return mode;
1610}
47f164de 1611
d7445d1f
LT		 1612static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1613{
85f9feb6 1614 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
d7445d1f
LT		 1615 struct xgbe_phy_data *phy_data = pdata->phy_data;
1616 enum xgbe_mode mode;
1617 unsigned int ad_reg, lp_reg;
1618
85f9feb6
LT		 1619 XGBE_SET_LP_ADV(lks, Autoneg);
1620 XGBE_SET_LP_ADV(lks, Backplane);
d7445d1f
LT		 1621
1622 /* Use external PHY to determine flow control */
1623 if (pdata->phy.pause_autoneg)
1624 xgbe_phy_phydev_flowctrl(pdata);
1625
1626 /* Compare Advertisement and Link Partner register 2 */
1627 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1628 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1629 if (lp_reg & 0x80)
85f9feb6 1630 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
d7445d1f 1631 if (lp_reg & 0x20)
85f9feb6 1632 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
d7445d1f
LT		 1633
1634 ad_reg &= lp_reg;
1635 if (ad_reg & 0x80) {
1636 switch (phy_data->port_mode) {
1637 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 1638 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
d7445d1f
LT		 1639 mode = XGBE_MODE_KR;
1640 break;
1641 default:
1642 mode = XGBE_MODE_SFI;
1643 break;
1644 }
1645 } else if (ad_reg & 0x20) {
1646 switch (phy_data->port_mode) {
1647 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 1648 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
d7445d1f
LT		 1649 mode = XGBE_MODE_KX_1000;
1650 break;
1651 case XGBE_PORT_MODE_1000BASE_X:
1652 mode = XGBE_MODE_X;
1653 break;
1654 case XGBE_PORT_MODE_SFP:
1655 switch (phy_data->sfp_base) {
1656 case XGBE_SFP_BASE_1000_T:
1657 if (phy_data->phydev &&
1658 (phy_data->phydev->speed == SPEED_100))
1659 mode = XGBE_MODE_SGMII_100;
1660 else
1661 mode = XGBE_MODE_SGMII_1000;
1662 break;
1663 case XGBE_SFP_BASE_1000_SX:
1664 case XGBE_SFP_BASE_1000_LX:
1665 case XGBE_SFP_BASE_1000_CX:
1666 default:
1667 mode = XGBE_MODE_X;
1668 break;
1669 }
1670 break;
1671 default:
1672 if (phy_data->phydev &&
1673 (phy_data->phydev->speed == SPEED_100))
1674 mode = XGBE_MODE_SGMII_100;
1675 else
1676 mode = XGBE_MODE_SGMII_1000;
1677 break;
1678 }
1679 } else {
1680 mode = XGBE_MODE_UNKNOWN;
1681 }
1682
1683 /* Compare Advertisement and Link Partner register 3 */
1684 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1685 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1686 if (lp_reg & 0xc000)
85f9feb6 1687 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
d7445d1f
LT		 1688
1689 return mode;
1690}
1691
abf0a1c2 1692static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
47f164de 1693{
85f9feb6 1694 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
47f164de
LT		 1695 enum xgbe_mode mode;
1696 unsigned int ad_reg, lp_reg;
1697
85f9feb6
LT		 1698 XGBE_SET_LP_ADV(lks, Autoneg);
1699 XGBE_SET_LP_ADV(lks, Backplane);
47f164de
LT		 1700
1701 /* Compare Advertisement and Link Partner register 1 */
1702 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1703 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1704 if (lp_reg & 0x400)
85f9feb6 1705 XGBE_SET_LP_ADV(lks, Pause);
47f164de 1706 if (lp_reg & 0x800)
85f9feb6 1707 XGBE_SET_LP_ADV(lks, Asym_Pause);
47f164de
LT		 1708
1709 if (pdata->phy.pause_autoneg) {
1710 /* Set flow control based on auto-negotiation result */
1711 pdata->phy.tx_pause = 0;
1712 pdata->phy.rx_pause = 0;
1713
1714 if (ad_reg & lp_reg & 0x400) {
1715 pdata->phy.tx_pause = 1;
1716 pdata->phy.rx_pause = 1;
1717 } else if (ad_reg & lp_reg & 0x800) {
1718 if (ad_reg & 0x400)
1719 pdata->phy.rx_pause = 1;
1720 else if (lp_reg & 0x400)
1721 pdata->phy.tx_pause = 1;
1722 }
1723 }
1724
1725 /* Compare Advertisement and Link Partner register 2 */
1726 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1727 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1728 if (lp_reg & 0x80)
85f9feb6 1729 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
47f164de 1730 if (lp_reg & 0x20)
85f9feb6 1731 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
47f164de
LT		 1732
1733 ad_reg &= lp_reg;
1734 if (ad_reg & 0x80)
1735 mode = XGBE_MODE_KR;
1736 else if (ad_reg & 0x20)
1737 mode = XGBE_MODE_KX_1000;
1738 else
1739 mode = XGBE_MODE_UNKNOWN;
1740
1741 /* Compare Advertisement and Link Partner register 3 */
1742 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1743 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1744 if (lp_reg & 0xc000)
85f9feb6 1745 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
47f164de
LT		 1746
1747 return mode;
1748}
1749
abf0a1c2
LT		 1750static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1751{
1752 switch (pdata->an_mode) {
1753 case XGBE_AN_MODE_CL73:
1754 return xgbe_phy_an73_outcome(pdata);
d7445d1f
LT		 1755 case XGBE_AN_MODE_CL73_REDRV:
1756 return xgbe_phy_an73_redrv_outcome(pdata);
abf0a1c2
LT		 1757 case XGBE_AN_MODE_CL37:
1758 return xgbe_phy_an37_outcome(pdata);
1759 case XGBE_AN_MODE_CL37_SGMII:
1760 return xgbe_phy_an37_sgmii_outcome(pdata);
1761 default:
1762 return XGBE_MODE_UNKNOWN;
1763 }
1764}
1765
85f9feb6
LT		 1766static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1767 struct ethtool_link_ksettings *dlks)
d7445d1f 1768{
85f9feb6 1769 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
d7445d1f 1770 struct xgbe_phy_data *phy_data = pdata->phy_data;
85f9feb6
LT		 1771
1772 XGBE_LM_COPY(dlks, advertising, slks, advertising);
d7445d1f
LT		 1773
1774 /* Without a re-driver, just return current advertising */
1775 if (!phy_data->redrv)
85f9feb6 1776 return;
d7445d1f
LT		 1777
1778 /* With the KR re-driver we need to advertise a single speed */
85f9feb6
LT		 1779 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1780 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
d7445d1f 1781
41874629
TL		 1782 /* Advertise FEC support is present */
1783 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1784 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1785
d7445d1f
LT		 1786 switch (phy_data->port_mode) {
1787 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 1788 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
85f9feb6 1789 XGBE_SET_ADV(dlks, 10000baseKR_Full);
d7445d1f
LT		 1790 break;
1791 case XGBE_PORT_MODE_BACKPLANE_2500:
85f9feb6 1792 XGBE_SET_ADV(dlks, 1000baseKX_Full);
d7445d1f
LT		 1793 break;
1794 case XGBE_PORT_MODE_1000BASE_T:
1795 case XGBE_PORT_MODE_1000BASE_X:
1796 case XGBE_PORT_MODE_NBASE_T:
85f9feb6 1797 XGBE_SET_ADV(dlks, 1000baseKX_Full);
d7445d1f
LT		 1798 break;
1799 case XGBE_PORT_MODE_10GBASE_T:
1800 if (phy_data->phydev &&
1801 (phy_data->phydev->speed == SPEED_10000))
85f9feb6 1802 XGBE_SET_ADV(dlks, 10000baseKR_Full);
d7445d1f 1803 else
85f9feb6 1804 XGBE_SET_ADV(dlks, 1000baseKX_Full);
d7445d1f
LT		 1805 break;
1806 case XGBE_PORT_MODE_10GBASE_R:
85f9feb6 1807 XGBE_SET_ADV(dlks, 10000baseKR_Full);
d7445d1f
LT		 1808 break;
1809 case XGBE_PORT_MODE_SFP:
1810 switch (phy_data->sfp_base) {
1811 case XGBE_SFP_BASE_1000_T:
1812 case XGBE_SFP_BASE_1000_SX:
1813 case XGBE_SFP_BASE_1000_LX:
1814 case XGBE_SFP_BASE_1000_CX:
85f9feb6 1815 XGBE_SET_ADV(dlks, 1000baseKX_Full);
d7445d1f
LT		 1816 break;
1817 default:
85f9feb6 1818 XGBE_SET_ADV(dlks, 10000baseKR_Full);
d7445d1f
LT		 1819 break;
1820 }
1821 break;
1822 default:
85f9feb6 1823 XGBE_SET_ADV(dlks, 10000baseKR_Full);
d7445d1f
LT		 1824 break;
1825 }
d7445d1f
LT		 1826}
1827
abf0a1c2
LT		 1828static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1829{
85f9feb6 1830 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2
LT		 1831 struct xgbe_phy_data *phy_data = pdata->phy_data;
1832 int ret;
1833
1834 ret = xgbe_phy_find_phy_device(pdata);
1835 if (ret)
1836 return ret;
1837
1838 if (!phy_data->phydev)
1839 return 0;
1840
1841 phy_data->phydev->autoneg = pdata->phy.autoneg;
3c1bcc86
AL		 1842 linkmode_and(phy_data->phydev->advertising,
1843 phy_data->phydev->supported,
1844 lks->link_modes.advertising);
abf0a1c2
LT		 1845
1846 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1847 phy_data->phydev->speed = pdata->phy.speed;
1848 phy_data->phydev->duplex = pdata->phy.duplex;
1849 }
1850
1851 ret = phy_start_aneg(phy_data->phydev);
1852
1853 return ret;
1854}
1855
1856static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1857{
1858 switch (phy_data->sfp_base) {
1859 case XGBE_SFP_BASE_1000_T:
1860 return XGBE_AN_MODE_CL37_SGMII;
1861 case XGBE_SFP_BASE_1000_SX:
1862 case XGBE_SFP_BASE_1000_LX:
1863 case XGBE_SFP_BASE_1000_CX:
1864 return XGBE_AN_MODE_CL37;
1865 default:
1866 return XGBE_AN_MODE_NONE;
1867 }
1868}
1869
47f164de
LT		 1870static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1871{
1872 struct xgbe_phy_data *phy_data = pdata->phy_data;
1873
d7445d1f
LT		 1874 /* A KR re-driver will always require CL73 AN */
1875 if (phy_data->redrv)
1876 return XGBE_AN_MODE_CL73_REDRV;
1877
47f164de
LT		 1878 switch (phy_data->port_mode) {
1879 case XGBE_PORT_MODE_BACKPLANE:
1880 return XGBE_AN_MODE_CL73;
7deedd9f 1881 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 1882 case XGBE_PORT_MODE_BACKPLANE_2500:
1883 return XGBE_AN_MODE_NONE;
1884 case XGBE_PORT_MODE_1000BASE_T:
732f2ab7 1885 return XGBE_AN_MODE_CL37_SGMII;
47f164de 1886 case XGBE_PORT_MODE_1000BASE_X:
732f2ab7 1887 return XGBE_AN_MODE_CL37;
47f164de 1888 case XGBE_PORT_MODE_NBASE_T:
732f2ab7 1889 return XGBE_AN_MODE_CL37_SGMII;
47f164de 1890 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7 1891 return XGBE_AN_MODE_CL73;
47f164de 1892 case XGBE_PORT_MODE_10GBASE_R:
abf0a1c2 1893 return XGBE_AN_MODE_NONE;
47f164de 1894 case XGBE_PORT_MODE_SFP:
abf0a1c2 1895 return xgbe_phy_an_sfp_mode(phy_data);
47f164de
LT		 1896 default:
1897 return XGBE_AN_MODE_NONE;
1898 }
1899}
1900
d7445d1f
LT		 1901static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1902 enum xgbe_phy_redrv_mode mode)
1903{
1904 struct xgbe_phy_data *phy_data = pdata->phy_data;
1905 u16 redrv_reg, redrv_val;
1906
1907 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1908 redrv_val = (u16)mode;
1909
1910 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1911 redrv_reg, redrv_val);
1912}
1913
1914static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1915 enum xgbe_phy_redrv_mode mode)
1916{
1917 struct xgbe_phy_data *phy_data = pdata->phy_data;
1918 unsigned int redrv_reg;
1919 int ret;
1920
1921 /* Calculate the register to write */
1922 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1923
1924 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1925
1926 return ret;
1927}
1928
1929static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1930{
1931 struct xgbe_phy_data *phy_data = pdata->phy_data;
1932 enum xgbe_phy_redrv_mode mode;
1933 int ret;
1934
1935 if (!phy_data->redrv)
1936 return;
1937
1938 mode = XGBE_PHY_REDRV_MODE_CX;
1939 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1940 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1941 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1942 mode = XGBE_PHY_REDRV_MODE_SR;
1943
1944 ret = xgbe_phy_get_comm_ownership(pdata);
1945 if (ret)
1946 return;
1947
1948 if (phy_data->redrv_if)
1949 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1950 else
1951 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1952
1953 xgbe_phy_put_comm_ownership(pdata);
1954}
1955
6f4bd839
SS		 1956static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1957{
1958 int reg;
1959
1960 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1961 XGBE_PCS_PSEQ_STATE_MASK);
1962 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1963 /* Mailbox command timed out, reset of RX block is required.
1964 * This can be done by asseting the reset bit and wait for
1965 * its compeletion.
1966 */
1967 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1968 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1969 ndelay(20);
1970 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1971 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1972 usleep_range(40, 50);
1973 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1974 }
1975}
1976
549b32af
LT		 1977static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1978 unsigned int cmd, unsigned int sub_cmd)
47f164de 1979{
549b32af
LT		 1980 unsigned int s0 = 0;
1981 unsigned int wait;
47f164de
LT		 1982
1983 /* Log if a previous command did not complete */
6f4bd839 1984 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
549b32af
LT		 1985 netif_dbg(pdata, link, pdata->netdev,
1986 "firmware mailbox not ready for command\n");
6f4bd839
SS		 1987 xgbe_phy_rx_reset(pdata);
1988 }
47f164de 1989
549b32af
LT		 1990 /* Construct the command */
1991 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1992 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1993
1994 /* Issue the command */
1995 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1996 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1997 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
47f164de
LT		 1998
1999 /* Wait for command to complete */
2000 wait = XGBE_RATECHANGE_COUNT;
2001 while (wait--) {
2002 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2003 return;
2004
2005 usleep_range(1000, 2000);
2006 }
2007
2008 netif_dbg(pdata, link, pdata->netdev,
2009 "firmware mailbox command did not complete\n");
6f4bd839
SS		 2010
2011 /* Reset on error */
2012 xgbe_phy_rx_reset(pdata);
47f164de
LT		 2013}
2014
2015static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2016{
47f164de 2017 /* Receiver Reset Cycle */
549b32af 2018 xgbe_phy_perform_ratechange(pdata, 5, 0);
47f164de
LT		 2019
2020 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2021}
2022
2023static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2024{
2025 struct xgbe_phy_data *phy_data = pdata->phy_data;
2026
549b32af
LT		 2027 /* Power off */
2028 xgbe_phy_perform_ratechange(pdata, 0, 0);
47f164de
LT		 2029
2030 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2031
2032 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2033}
2034
abf0a1c2
LT		 2035static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2036{
2037 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2 2038
d7445d1f
LT		 2039 xgbe_phy_set_redrv_mode(pdata);
2040
abf0a1c2 2041 /* 10G/SFI */
abf0a1c2 2042 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
549b32af 2043 xgbe_phy_perform_ratechange(pdata, 3, 0);
abf0a1c2
LT		 2044 } else {
2045 if (phy_data->sfp_cable_len <= 1)
549b32af 2046 xgbe_phy_perform_ratechange(pdata, 3, 1);
abf0a1c2 2047 else if (phy_data->sfp_cable_len <= 3)
549b32af 2048 xgbe_phy_perform_ratechange(pdata, 3, 2);
abf0a1c2 2049 else
549b32af 2050 xgbe_phy_perform_ratechange(pdata, 3, 3);
abf0a1c2
LT		 2051 }
2052
abf0a1c2
LT		 2053 phy_data->cur_mode = XGBE_MODE_SFI;
2054
2055 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2056}
2057
2058static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2059{
2060 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2 2061
d7445d1f
LT		 2062 xgbe_phy_set_redrv_mode(pdata);
2063
abf0a1c2 2064 /* 1G/X */
549b32af 2065 xgbe_phy_perform_ratechange(pdata, 1, 3);
abf0a1c2
LT		 2066
2067 phy_data->cur_mode = XGBE_MODE_X;
2068
2069 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2070}
2071
2072static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2073{
2074 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2 2075
d7445d1f
LT		 2076 xgbe_phy_set_redrv_mode(pdata);
2077
abf0a1c2 2078 /* 1G/SGMII */
549b32af 2079 xgbe_phy_perform_ratechange(pdata, 1, 2);
abf0a1c2
LT		 2080
2081 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2082
2083 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2084}
2085
2086static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2087{
2088 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2 2089
d7445d1f
LT		 2090 xgbe_phy_set_redrv_mode(pdata);
2091
549b32af
LT		 2092 /* 100M/SGMII */
2093 xgbe_phy_perform_ratechange(pdata, 1, 1);
abf0a1c2
LT		 2094
2095 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2096
2097 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2098}
2099
47f164de
LT		 2100static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2101{
2102 struct xgbe_phy_data *phy_data = pdata->phy_data;
47f164de 2103
d7445d1f
LT		 2104 xgbe_phy_set_redrv_mode(pdata);
2105
47f164de 2106 /* 10G/KR */
549b32af 2107 xgbe_phy_perform_ratechange(pdata, 4, 0);
47f164de
LT		 2108
2109 phy_data->cur_mode = XGBE_MODE_KR;
2110
2111 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2112}
2113
2114static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2115{
2116 struct xgbe_phy_data *phy_data = pdata->phy_data;
47f164de 2117
d7445d1f
LT		 2118 xgbe_phy_set_redrv_mode(pdata);
2119
47f164de 2120 /* 2.5G/KX */
549b32af 2121 xgbe_phy_perform_ratechange(pdata, 2, 0);
47f164de
LT		 2122
2123 phy_data->cur_mode = XGBE_MODE_KX_2500;
2124
2125 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2126}
2127
2128static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2129{
2130 struct xgbe_phy_data *phy_data = pdata->phy_data;
47f164de 2131
d7445d1f
LT		 2132 xgbe_phy_set_redrv_mode(pdata);
2133
47f164de 2134 /* 1G/KX */
549b32af 2135 xgbe_phy_perform_ratechange(pdata, 1, 3);
47f164de
LT		 2136
2137 phy_data->cur_mode = XGBE_MODE_KX_1000;
2138
2139 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2140}
2141
2142static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2143{
2144 struct xgbe_phy_data *phy_data = pdata->phy_data;
2145
2146 return phy_data->cur_mode;
2147}
2148
732f2ab7
LT		 2149static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2150{
2151 struct xgbe_phy_data *phy_data = pdata->phy_data;
2152
2153 /* No switching if not 10GBase-T */
2154 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2155 return xgbe_phy_cur_mode(pdata);
2156
2157 switch (xgbe_phy_cur_mode(pdata)) {
2158 case XGBE_MODE_SGMII_100:
2159 case XGBE_MODE_SGMII_1000:
2160 return XGBE_MODE_KR;
2161 case XGBE_MODE_KR:
2162 default:
2163 return XGBE_MODE_SGMII_1000;
2164 }
2165}
2166
47f164de
LT		 2167static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2168{
2169 return XGBE_MODE_KX_2500;
2170}
2171
2172static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2173{
2174 /* If we are in KR switch to KX, and vice-versa */
2175 switch (xgbe_phy_cur_mode(pdata)) {
2176 case XGBE_MODE_KX_1000:
2177 return XGBE_MODE_KR;
2178 case XGBE_MODE_KR:
2179 default:
2180 return XGBE_MODE_KX_1000;
2181 }
2182}
2183
2184static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2185{
2186 struct xgbe_phy_data *phy_data = pdata->phy_data;
2187
2188 switch (phy_data->port_mode) {
2189 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2190 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2191 return xgbe_phy_switch_bp_mode(pdata);
2192 case XGBE_PORT_MODE_BACKPLANE_2500:
2193 return xgbe_phy_switch_bp_2500_mode(pdata);
2194 case XGBE_PORT_MODE_1000BASE_T:
47f164de
LT		 2195 case XGBE_PORT_MODE_NBASE_T:
2196 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7
LT		 2197 return xgbe_phy_switch_baset_mode(pdata);
2198 case XGBE_PORT_MODE_1000BASE_X:
47f164de
LT		 2199 case XGBE_PORT_MODE_10GBASE_R:
2200 case XGBE_PORT_MODE_SFP:
abf0a1c2
LT		 2201 /* No switching, so just return current mode */
2202 return xgbe_phy_cur_mode(pdata);
2203 default:
2204 return XGBE_MODE_UNKNOWN;
2205 }
2206}
2207
732f2ab7
LT		 2208static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2209 int speed)
2210{
2211 switch (speed) {
2212 case SPEED_1000:
2213 return XGBE_MODE_X;
2214 case SPEED_10000:
2215 return XGBE_MODE_KR;
2216 default:
2217 return XGBE_MODE_UNKNOWN;
2218 }
2219}
2220
2221static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2222 int speed)
2223{
2224 switch (speed) {
2225 case SPEED_100:
2226 return XGBE_MODE_SGMII_100;
2227 case SPEED_1000:
2228 return XGBE_MODE_SGMII_1000;
ed3333fa
LT		 2229 case SPEED_2500:
2230 return XGBE_MODE_KX_2500;
732f2ab7
LT		 2231 case SPEED_10000:
2232 return XGBE_MODE_KR;
2233 default:
2234 return XGBE_MODE_UNKNOWN;
2235 }
2236}
2237
abf0a1c2
LT		 2238static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2239 int speed)
2240{
2241 switch (speed) {
2242 case SPEED_100:
2243 return XGBE_MODE_SGMII_100;
2244 case SPEED_1000:
2245 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2246 return XGBE_MODE_SGMII_1000;
2247 else
2248 return XGBE_MODE_X;
2249 case SPEED_10000:
2250 case SPEED_UNKNOWN:
2251 return XGBE_MODE_SFI;
47f164de
LT		 2252 default:
2253 return XGBE_MODE_UNKNOWN;
2254 }
2255}
2256
2257static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2258{
2259 switch (speed) {
2260 case SPEED_2500:
2261 return XGBE_MODE_KX_2500;
2262 default:
2263 return XGBE_MODE_UNKNOWN;
2264 }
2265}
2266
2267static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2268{
2269 switch (speed) {
2270 case SPEED_1000:
2271 return XGBE_MODE_KX_1000;
2272 case SPEED_10000:
2273 return XGBE_MODE_KR;
2274 default:
2275 return XGBE_MODE_UNKNOWN;
2276 }
2277}
2278
2279static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2280 int speed)
2281{
2282 struct xgbe_phy_data *phy_data = pdata->phy_data;
2283
2284 switch (phy_data->port_mode) {
2285 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2286 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2287 return xgbe_phy_get_bp_mode(speed);
2288 case XGBE_PORT_MODE_BACKPLANE_2500:
2289 return xgbe_phy_get_bp_2500_mode(speed);
2290 case XGBE_PORT_MODE_1000BASE_T:
47f164de
LT		 2291 case XGBE_PORT_MODE_NBASE_T:
2292 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7
LT		 2293 return xgbe_phy_get_baset_mode(phy_data, speed);
2294 case XGBE_PORT_MODE_1000BASE_X:
47f164de 2295 case XGBE_PORT_MODE_10GBASE_R:
732f2ab7 2296 return xgbe_phy_get_basex_mode(phy_data, speed);
47f164de 2297 case XGBE_PORT_MODE_SFP:
abf0a1c2 2298 return xgbe_phy_get_sfp_mode(phy_data, speed);
47f164de
LT		 2299 default:
2300 return XGBE_MODE_UNKNOWN;
2301 }
2302}
2303
2304static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2305{
2306 switch (mode) {
2307 case XGBE_MODE_KX_1000:
2308 xgbe_phy_kx_1000_mode(pdata);
2309 break;
2310 case XGBE_MODE_KX_2500:
2311 xgbe_phy_kx_2500_mode(pdata);
2312 break;
2313 case XGBE_MODE_KR:
2314 xgbe_phy_kr_mode(pdata);
2315 break;
abf0a1c2
LT		 2316 case XGBE_MODE_SGMII_100:
2317 xgbe_phy_sgmii_100_mode(pdata);
2318 break;
2319 case XGBE_MODE_SGMII_1000:
2320 xgbe_phy_sgmii_1000_mode(pdata);
2321 break;
2322 case XGBE_MODE_X:
2323 xgbe_phy_x_mode(pdata);
2324 break;
2325 case XGBE_MODE_SFI:
2326 xgbe_phy_sfi_mode(pdata);
2327 break;
47f164de
LT		 2328 default:
2329 break;
2330 }
2331}
2332
2333static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
85f9feb6 2334 enum xgbe_mode mode, bool advert)
47f164de
LT		 2335{
2336 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
85f9feb6 2337 return advert;
47f164de
LT		 2338 } else {
2339 enum xgbe_mode cur_mode;
2340
2341 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2342 if (cur_mode == mode)
2343 return true;
2344 }
2345
2346 return false;
2347}
2348
732f2ab7
LT		 2349static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2350 enum xgbe_mode mode)
2351{
85f9feb6
LT		 2352 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2353
732f2ab7
LT		 2354 switch (mode) {
2355 case XGBE_MODE_X:
2356 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2357 XGBE_ADV(lks, 1000baseX_Full));
732f2ab7
LT		 2358 case XGBE_MODE_KR:
2359 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2360 XGBE_ADV(lks, 10000baseKR_Full));
732f2ab7
LT		 2361 default:
2362 return false;
2363 }
2364}
2365
2366static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2367 enum xgbe_mode mode)
2368{
85f9feb6
LT		 2369 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2370
732f2ab7
LT		 2371 switch (mode) {
2372 case XGBE_MODE_SGMII_100:
2373 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2374 XGBE_ADV(lks, 100baseT_Full));
732f2ab7
LT		 2375 case XGBE_MODE_SGMII_1000:
2376 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2377 XGBE_ADV(lks, 1000baseT_Full));
ed3333fa
LT		 2378 case XGBE_MODE_KX_2500:
2379 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2380 XGBE_ADV(lks, 2500baseT_Full));
732f2ab7
LT		 2381 case XGBE_MODE_KR:
2382 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2383 XGBE_ADV(lks, 10000baseT_Full));
732f2ab7
LT		 2384 default:
2385 return false;
2386 }
2387}
2388
abf0a1c2
LT		 2389static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2390 enum xgbe_mode mode)
2391{
85f9feb6 2392 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
abf0a1c2
LT		 2393 struct xgbe_phy_data *phy_data = pdata->phy_data;
2394
2395 switch (mode) {
2396 case XGBE_MODE_X:
2397 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2398 return false;
2399 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2400 XGBE_ADV(lks, 1000baseX_Full));
abf0a1c2
LT		 2401 case XGBE_MODE_SGMII_100:
2402 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2403 return false;
2404 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2405 XGBE_ADV(lks, 100baseT_Full));
abf0a1c2
LT		 2406 case XGBE_MODE_SGMII_1000:
2407 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2408 return false;
2409 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2410 XGBE_ADV(lks, 1000baseT_Full));
abf0a1c2 2411 case XGBE_MODE_SFI:
56503d55
LT		 2412 if (phy_data->sfp_mod_absent)
2413 return true;
abf0a1c2 2414 return xgbe_phy_check_mode(pdata, mode,
85f9feb6
LT		 2415 XGBE_ADV(lks, 10000baseSR_Full) ||
2416 XGBE_ADV(lks, 10000baseLR_Full) ||
2417 XGBE_ADV(lks, 10000baseLRM_Full) ||
2418 XGBE_ADV(lks, 10000baseER_Full) ||
2419 XGBE_ADV(lks, 10000baseCR_Full));
abf0a1c2
LT		 2420 default:
2421 return false;
2422 }
2423}
2424
47f164de
LT		 2425static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2426 enum xgbe_mode mode)
2427{
85f9feb6
LT		 2428 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2429
47f164de
LT		 2430 switch (mode) {
2431 case XGBE_MODE_KX_2500:
2432 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2433 XGBE_ADV(lks, 2500baseX_Full));
47f164de
LT		 2434 default:
2435 return false;
2436 }
2437}
2438
2439static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2440 enum xgbe_mode mode)
2441{
85f9feb6
LT		 2442 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2443
47f164de
LT		 2444 switch (mode) {
2445 case XGBE_MODE_KX_1000:
2446 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2447 XGBE_ADV(lks, 1000baseKX_Full));
47f164de
LT		 2448 case XGBE_MODE_KR:
2449 return xgbe_phy_check_mode(pdata, mode,
85f9feb6 2450 XGBE_ADV(lks, 10000baseKR_Full));
47f164de
LT		 2451 default:
2452 return false;
2453 }
2454}
2455
2456static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2457{
2458 struct xgbe_phy_data *phy_data = pdata->phy_data;
2459
2460 switch (phy_data->port_mode) {
2461 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2462 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2463 return xgbe_phy_use_bp_mode(pdata, mode);
2464 case XGBE_PORT_MODE_BACKPLANE_2500:
2465 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2466 case XGBE_PORT_MODE_1000BASE_T:
47f164de
LT		 2467 case XGBE_PORT_MODE_NBASE_T:
2468 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7
LT		 2469 return xgbe_phy_use_baset_mode(pdata, mode);
2470 case XGBE_PORT_MODE_1000BASE_X:
47f164de 2471 case XGBE_PORT_MODE_10GBASE_R:
732f2ab7 2472 return xgbe_phy_use_basex_mode(pdata, mode);
47f164de 2473 case XGBE_PORT_MODE_SFP:
abf0a1c2
LT		 2474 return xgbe_phy_use_sfp_mode(pdata, mode);
2475 default:
2476 return false;
2477 }
2478}
2479
732f2ab7
LT		 2480static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2481 int speed)
2482{
2483 switch (speed) {
2484 case SPEED_1000:
2485 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2486 case SPEED_10000:
2487 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2488 default:
2489 return false;
2490 }
2491}
2492
2493static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2494 int speed)
2495{
2496 switch (speed) {
2497 case SPEED_100:
2498 case SPEED_1000:
2499 return true;
ed3333fa
LT		 2500 case SPEED_2500:
2501 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
732f2ab7
LT		 2502 case SPEED_10000:
2503 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2504 default:
2505 return false;
2506 }
2507}
2508
abf0a1c2
LT		 2509static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2510 int speed)
2511{
2512 switch (speed) {
2513 case SPEED_100:
2514 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2515 case SPEED_1000:
2516 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2517 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2518 case SPEED_10000:
2519 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
47f164de
LT		 2520 default:
2521 return false;
2522 }
2523}
2524
2525static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2526{
2527 switch (speed) {
2528 case SPEED_2500:
2529 return true;
2530 default:
2531 return false;
2532 }
2533}
2534
2535static bool xgbe_phy_valid_speed_bp_mode(int speed)
2536{
2537 switch (speed) {
2538 case SPEED_1000:
2539 case SPEED_10000:
2540 return true;
2541 default:
2542 return false;
2543 }
2544}
2545
2546static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2547{
2548 struct xgbe_phy_data *phy_data = pdata->phy_data;
2549
2550 switch (phy_data->port_mode) {
2551 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2552 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2553 return xgbe_phy_valid_speed_bp_mode(speed);
2554 case XGBE_PORT_MODE_BACKPLANE_2500:
2555 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2556 case XGBE_PORT_MODE_1000BASE_T:
47f164de
LT		 2557 case XGBE_PORT_MODE_NBASE_T:
2558 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7
LT		 2559 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2560 case XGBE_PORT_MODE_1000BASE_X:
47f164de 2561 case XGBE_PORT_MODE_10GBASE_R:
732f2ab7 2562 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
47f164de 2563 case XGBE_PORT_MODE_SFP:
abf0a1c2 2564 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
47f164de
LT		 2565 default:
2566 return false;
2567 }
2568}
2569
abf0a1c2 2570static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
47f164de
LT		 2571{
2572 struct xgbe_phy_data *phy_data = pdata->phy_data;
8c5385cb
LT		 2573 unsigned int reg;
2574 int ret;
abf0a1c2
LT		 2575
2576 *an_restart = 0;
2577
2578 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2579 /* Check SFP signals */
2580 xgbe_phy_sfp_detect(pdata);
2581
2582 if (phy_data->sfp_changed) {
2583 *an_restart = 1;
2584 return 0;
2585 }
2586
2587 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2588 return 0;
2589 }
2590
2591 if (phy_data->phydev) {
2592 /* Check external PHY */
2593 ret = phy_read_status(phy_data->phydev);
2594 if (ret < 0)
2595 return 0;
2596
2597 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2598 !phy_aneg_done(phy_data->phydev))
2599 return 0;
2600
2601 if (!phy_data->phydev->link)
2602 return 0;
2603 }
47f164de
LT		 2604
2605 /* Link status is latched low, so read once to clear
2606 * and then read again to get current state
2607 */
2608 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2609 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2610 if (reg & MDIO_STAT1_LSTATUS)
2611 return 1;
2612
2613 /* No link, attempt a receiver reset cycle */
96f4d430 2614 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
47f164de
LT		 2615 phy_data->rrc_count = 0;
2616 xgbe_phy_rrc(pdata);
2617 }
2618
2619 return 0;
2620}
2621
abf0a1c2
LT		 2622static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2623{
2624 struct xgbe_phy_data *phy_data = pdata->phy_data;
abf0a1c2
LT		 2625
2626 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
b93c3ab6
TL		 2627 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2628 GPIO_ADDR);
abf0a1c2 2629
b93c3ab6
TL		 2630 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2631 GPIO_MASK);
abf0a1c2 2632
b93c3ab6 2633 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
abf0a1c2 2634 GPIO_RX_LOS);
b93c3ab6 2635 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
abf0a1c2 2636 GPIO_TX_FAULT);
b93c3ab6 2637 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
abf0a1c2 2638 GPIO_MOD_ABS);
b93c3ab6 2639 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
abf0a1c2
LT		 2640 GPIO_RATE_SELECT);
2641
2642 if (netif_msg_probe(pdata)) {
2643 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2644 phy_data->sfp_gpio_address);
2645 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2646 phy_data->sfp_gpio_mask);
2647 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2648 phy_data->sfp_gpio_rx_los);
2649 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2650 phy_data->sfp_gpio_tx_fault);
2651 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2652 phy_data->sfp_gpio_mod_absent);
2653 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2654 phy_data->sfp_gpio_rate_select);
2655 }
2656}
2657
2658static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2659{
2660 struct xgbe_phy_data *phy_data = pdata->phy_data;
b93c3ab6 2661 unsigned int mux_addr_hi, mux_addr_lo;
abf0a1c2 2662
b93c3ab6
TL		 2663 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2664 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
abf0a1c2
LT		 2665 if (mux_addr_lo == XGBE_SFP_DIRECT)
2666 return;
2667
2668 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2669 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
b93c3ab6
TL		 2670 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2671 MUX_CHAN);
abf0a1c2
LT		 2672
2673 if (netif_msg_probe(pdata)) {
2674 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2675 phy_data->sfp_mux_address);
2676 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2677 phy_data->sfp_mux_channel);
2678 }
2679}
2680
2681static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2682{
2683 xgbe_phy_sfp_comm_setup(pdata);
2684 xgbe_phy_sfp_gpio_setup(pdata);
2685}
2686
732f2ab7
LT		 2687static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2688{
2689 struct xgbe_phy_data *phy_data = pdata->phy_data;
2690 unsigned int ret;
2691
2692 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2693 if (ret)
2694 return ret;
2695
2696 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2697
2698 return ret;
2699}
2700
2701static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2702{
2703 struct xgbe_phy_data *phy_data = pdata->phy_data;
2704 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2705 int ret;
2706
2707 /* Read the output port registers */
2708 gpio_reg = 2;
2709 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2710 &gpio_reg, sizeof(gpio_reg),
2711 gpio_ports, sizeof(gpio_ports));
2712 if (ret)
2713 return ret;
2714
2715 /* Prepare to write the GPIO data */
2716 gpio_data[0] = 2;
2717 gpio_data[1] = gpio_ports[0];
2718 gpio_data[2] = gpio_ports[1];
2719
2720 /* Set the GPIO pin */
2721 if (phy_data->mdio_reset_gpio < 8)
2722 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2723 else
2724 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2725
2726 /* Write the output port registers */
2727 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2728 gpio_data, sizeof(gpio_data));
2729 if (ret)
2730 return ret;
2731
2732 /* Clear the GPIO pin */
2733 if (phy_data->mdio_reset_gpio < 8)
2734 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2735 else
2736 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2737
2738 /* Write the output port registers */
2739 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2740 gpio_data, sizeof(gpio_data));
2741
2742 return ret;
2743}
2744
2745static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2746{
2747 struct xgbe_phy_data *phy_data = pdata->phy_data;
2748 int ret;
2749
2750 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2751 return 0;
2752
2753 ret = xgbe_phy_get_comm_ownership(pdata);
2754 if (ret)
2755 return ret;
2756
2757 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2758 ret = xgbe_phy_i2c_mdio_reset(pdata);
2759 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2760 ret = xgbe_phy_int_mdio_reset(pdata);
2761
2762 xgbe_phy_put_comm_ownership(pdata);
2763
2764 return ret;
2765}
2766
d7445d1f
LT		 2767static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2768{
2769 if (!phy_data->redrv)
2770 return false;
2771
2772 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2773 return true;
2774
2775 switch (phy_data->redrv_model) {
2776 case XGBE_PHY_REDRV_MODEL_4223:
2777 if (phy_data->redrv_lane > 3)
2778 return true;
2779 break;
2780 case XGBE_PHY_REDRV_MODEL_4227:
2781 if (phy_data->redrv_lane > 1)
2782 return true;
2783 break;
2784 default:
2785 return true;
2786 }
2787
2788 return false;
2789}
2790
732f2ab7
LT		 2791static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2792{
2793 struct xgbe_phy_data *phy_data = pdata->phy_data;
732f2ab7
LT		 2794
2795 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2796 return 0;
2797
b93c3ab6 2798 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
732f2ab7
LT		 2799 switch (phy_data->mdio_reset) {
2800 case XGBE_MDIO_RESET_NONE:
2801 case XGBE_MDIO_RESET_I2C_GPIO:
2802 case XGBE_MDIO_RESET_INT_GPIO:
2803 break;
2804 default:
2805 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2806 phy_data->mdio_reset);
2807 return -EINVAL;
2808 }
2809
2810 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2811 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
b93c3ab6 2812 XP_GET_BITS(pdata->pp3, XP_PROP_3,
732f2ab7 2813 MDIO_RESET_I2C_ADDR);
b93c3ab6 2814 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
732f2ab7
LT		 2815 MDIO_RESET_I2C_GPIO);
2816 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
b93c3ab6 2817 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
732f2ab7
LT		 2818 MDIO_RESET_INT_GPIO);
2819 }
2820
2821 return 0;
2822}
2823
47f164de
LT		 2824static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2825{
2826 struct xgbe_phy_data *phy_data = pdata->phy_data;
2827
2828 switch (phy_data->port_mode) {
2829 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2830 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2831 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2832 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2833 return false;
2834 break;
2835 case XGBE_PORT_MODE_BACKPLANE_2500:
2836 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2837 return false;
2838 break;
2839 case XGBE_PORT_MODE_1000BASE_T:
2840 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2841 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2842 return false;
2843 break;
2844 case XGBE_PORT_MODE_1000BASE_X:
2845 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2846 return false;
2847 break;
2848 case XGBE_PORT_MODE_NBASE_T:
2849 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2850 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2851 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2852 return false;
2853 break;
2854 case XGBE_PORT_MODE_10GBASE_T:
732f2ab7
LT		 2855 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2856 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
47f164de
LT		 2857 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2858 return false;
2859 break;
2860 case XGBE_PORT_MODE_10GBASE_R:
2861 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2862 return false;
2863 break;
2864 case XGBE_PORT_MODE_SFP:
2865 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2866 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2867 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2868 return false;
2869 break;
2870 default:
2871 break;
2872 }
2873
2874 return true;
2875}
2876
2877static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2878{
2879 struct xgbe_phy_data *phy_data = pdata->phy_data;
2880
2881 switch (phy_data->port_mode) {
2882 case XGBE_PORT_MODE_BACKPLANE:
7deedd9f 2883 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
47f164de
LT		 2884 case XGBE_PORT_MODE_BACKPLANE_2500:
2885 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2886 return false;
2887 break;
2888 case XGBE_PORT_MODE_1000BASE_T:
2889 case XGBE_PORT_MODE_1000BASE_X:
2890 case XGBE_PORT_MODE_NBASE_T:
2891 case XGBE_PORT_MODE_10GBASE_T:
2892 case XGBE_PORT_MODE_10GBASE_R:
2893 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2894 return false;
2895 break;
2896 case XGBE_PORT_MODE_SFP:
2897 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2898 return false;
2899 break;
2900 default:
2901 break;
2902 }
2903
2904 return true;
2905}
2906
2907static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2908{
b93c3ab6 2909 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
47f164de 2910 return false;
b93c3ab6 2911 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
47f164de
LT		 2912 return false;
2913
2914 return true;
2915}
2916
96f4d430
TL		 2917static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2918{
2919 struct xgbe_phy_data *phy_data = pdata->phy_data;
2920
2921 if (!pdata->debugfs_an_cdr_workaround)
2922 return;
2923
2924 if (!phy_data->phy_cdr_notrack)
2925 return;
2926
2927 usleep_range(phy_data->phy_cdr_delay,
2928 phy_data->phy_cdr_delay + 500);
2929
2930 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2931 XGBE_PMA_CDR_TRACK_EN_MASK,
2932 XGBE_PMA_CDR_TRACK_EN_ON);
2933
2934 phy_data->phy_cdr_notrack = 0;
2935}
2936
2937static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2938{
2939 struct xgbe_phy_data *phy_data = pdata->phy_data;
2940
2941 if (!pdata->debugfs_an_cdr_workaround)
2942 return;
2943
2944 if (phy_data->phy_cdr_notrack)
2945 return;
2946
2947 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2948 XGBE_PMA_CDR_TRACK_EN_MASK,
2949 XGBE_PMA_CDR_TRACK_EN_OFF);
2950
2951 xgbe_phy_rrc(pdata);
2952
2953 phy_data->phy_cdr_notrack = 1;
2954}
2955
2956static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2957{
2958 if (!pdata->debugfs_an_cdr_track_early)
2959 xgbe_phy_cdr_track(pdata);
2960}
2961
2962static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2963{
2964 if (pdata->debugfs_an_cdr_track_early)
2965 xgbe_phy_cdr_track(pdata);
2966}
2967
2968static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2969{
2970 struct xgbe_phy_data *phy_data = pdata->phy_data;
2971
2972 switch (pdata->an_mode) {
2973 case XGBE_AN_MODE_CL73:
2974 case XGBE_AN_MODE_CL73_REDRV:
2975 if (phy_data->cur_mode != XGBE_MODE_KR)
2976 break;
2977
2978 xgbe_phy_cdr_track(pdata);
2979
2980 switch (pdata->an_result) {
2981 case XGBE_AN_READY:
2982 case XGBE_AN_COMPLETE:
2983 break;
2984 default:
2985 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2986 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2987 else
2988 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2989 break;
2990 }
2991 break;
2992 default:
2993 break;
2994 }
2995}
2996
2997static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2998{
2999 struct xgbe_phy_data *phy_data = pdata->phy_data;
3000
3001 switch (pdata->an_mode) {
3002 case XGBE_AN_MODE_CL73:
3003 case XGBE_AN_MODE_CL73_REDRV:
3004 if (phy_data->cur_mode != XGBE_MODE_KR)
3005 break;
3006
3007 xgbe_phy_cdr_notrack(pdata);
3008 break;
3009 default:
3010 break;
3011 }
3012}
3013
47f164de
LT		 3014static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3015{
abf0a1c2
LT		 3016 struct xgbe_phy_data *phy_data = pdata->phy_data;
3017
3018 /* If we have an external PHY, free it */
3019 xgbe_phy_free_phy_device(pdata);
3020
3021 /* Reset SFP data */
3022 xgbe_phy_sfp_reset(phy_data);
3023 xgbe_phy_sfp_mod_absent(pdata);
3024
96f4d430
TL		 3025 /* Reset CDR support */
3026 xgbe_phy_cdr_track(pdata);
3027
47f164de
LT		 3028 /* Power off the PHY */
3029 xgbe_phy_power_off(pdata);
5ab1dcd5
LT		 3030
3031 /* Stop the I2C controller */
3032 pdata->i2c_if.i2c_stop(pdata);
47f164de
LT		 3033}
3034
3035static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3036{
3037 struct xgbe_phy_data *phy_data = pdata->phy_data;
5ab1dcd5
LT		 3038 int ret;
3039
3040 /* Start the I2C controller */
3041 ret = pdata->i2c_if.i2c_start(pdata);
3042 if (ret)
3043 return ret;
47f164de 3044
b42c6761
LT		 3045 /* Set the proper MDIO mode for the re-driver */
3046 if (phy_data->redrv && !phy_data->redrv_if) {
3047 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3048 XGBE_MDIO_MODE_CL22);
3049 if (ret) {
3050 netdev_err(pdata->netdev,
3051 "redriver mdio port not compatible (%u)\n",
3052 phy_data->redrv_addr);
3053 return ret;
3054 }
3055 }
3056
47f164de
LT		 3057 /* Start in highest supported mode */
3058 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3059
96f4d430
TL		 3060 /* Reset CDR support */
3061 xgbe_phy_cdr_track(pdata);
3062
abf0a1c2
LT		 3063 /* After starting the I2C controller, we can check for an SFP */
3064 switch (phy_data->port_mode) {
3065 case XGBE_PORT_MODE_SFP:
3066 xgbe_phy_sfp_detect(pdata);
3067 break;
3068 default:
3069 break;
3070 }
3071
3072 /* If we have an external PHY, start it */
3073 ret = xgbe_phy_find_phy_device(pdata);
3074 if (ret)
3075 goto err_i2c;
3076
47f164de 3077 return 0;
abf0a1c2
LT		 3078
3079err_i2c:
3080 pdata->i2c_if.i2c_stop(pdata);
3081
3082 return ret;
47f164de
LT		 3083}
3084
3085static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3086{
3087 struct xgbe_phy_data *phy_data = pdata->phy_data;
3088 enum xgbe_mode cur_mode;
732f2ab7 3089 int ret;
47f164de
LT		 3090
3091 /* Reset by power cycling the PHY */
3092 cur_mode = phy_data->cur_mode;
3093 xgbe_phy_power_off(pdata);
3094 xgbe_phy_set_mode(pdata, cur_mode);
3095
abf0a1c2
LT		 3096 if (!phy_data->phydev)
3097 return 0;
3098
3099 /* Reset the external PHY */
732f2ab7
LT		 3100 ret = xgbe_phy_mdio_reset(pdata);
3101 if (ret)
3102 return ret;
3103
abf0a1c2 3104 return phy_init_hw(phy_data->phydev);
47f164de
LT		 3105}
3106
3107static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3108{
abf0a1c2
LT		 3109 struct xgbe_phy_data *phy_data = pdata->phy_data;
3110
3111 /* Unregister for driving external PHYs */
3112 mdiobus_unregister(phy_data->mii);
47f164de
LT		 3113}
3114
3115static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3116{
85f9feb6 3117 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
47f164de 3118 struct xgbe_phy_data *phy_data;
abf0a1c2 3119 struct mii_bus *mii;
5ab1dcd5 3120 int ret;
47f164de
LT		 3121
3122 /* Check if enabled */
3123 if (!xgbe_phy_port_enabled(pdata)) {
3124 dev_info(pdata->dev, "device is not enabled\n");
3125 return -ENODEV;
3126 }
3127
5ab1dcd5
LT		 3128 /* Initialize the I2C controller */
3129 ret = pdata->i2c_if.i2c_init(pdata);
3130 if (ret)
3131 return ret;
3132
47f164de
LT		 3133 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3134 if (!phy_data)
3135 return -ENOMEM;
3136 pdata->phy_data = phy_data;
3137
b93c3ab6
TL		 3138 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3139 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3140 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3141 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3142 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
47f164de
LT		 3143 if (netif_msg_probe(pdata)) {
3144 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3145 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3146 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3147 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
abf0a1c2 3148 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
47f164de
LT		 3149 }
3150
b93c3ab6
TL		 3151 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3152 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3153 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3154 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3155 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
d7445d1f
LT		 3156 if (phy_data->redrv && netif_msg_probe(pdata)) {
3157 dev_dbg(pdata->dev, "redrv present\n");
3158 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3159 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3160 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3161 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3162 }
3163
47f164de
LT		 3164 /* Validate the connection requested */
3165 if (xgbe_phy_conn_type_mismatch(pdata)) {
3166 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3167 phy_data->port_mode, phy_data->conn_type);
5a4e4c8f 3168 return -EINVAL;
47f164de
LT		 3169 }
3170
3171 /* Validate the mode requested */
3172 if (xgbe_phy_port_mode_mismatch(pdata)) {
3173 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3174 phy_data->port_mode, phy_data->port_speeds);
3175 return -EINVAL;
3176 }
3177
732f2ab7
LT		 3178 /* Check for and validate MDIO reset support */
3179 ret = xgbe_phy_mdio_reset_setup(pdata);
3180 if (ret)
3181 return ret;
3182
d7445d1f
LT		 3183 /* Validate the re-driver information */
3184 if (xgbe_phy_redrv_error(phy_data)) {
3185 dev_err(pdata->dev, "phy re-driver settings error\n");
3186 return -EINVAL;
3187 }
3188 pdata->kr_redrv = phy_data->redrv;
3189
47f164de
LT		 3190 /* Indicate current mode is unknown */
3191 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3192
3193 /* Initialize supported features */
85f9feb6 3194 XGBE_ZERO_SUP(lks);
47f164de
LT		 3195
3196 switch (phy_data->port_mode) {
732f2ab7 3197 /* Backplane support */
47f164de 3198 case XGBE_PORT_MODE_BACKPLANE:
85f9feb6 3199 XGBE_SET_SUP(lks, Autoneg);
7deedd9f
SS		 3200 fallthrough;
3201 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
85f9feb6
LT		 3202 XGBE_SET_SUP(lks, Pause);
3203 XGBE_SET_SUP(lks, Asym_Pause);
3204 XGBE_SET_SUP(lks, Backplane);
47f164de 3205 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
85f9feb6 3206 XGBE_SET_SUP(lks, 1000baseKX_Full);
47f164de
LT		 3207 phy_data->start_mode = XGBE_MODE_KX_1000;
3208 }
3209 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
85f9feb6 3210 XGBE_SET_SUP(lks, 10000baseKR_Full);
47f164de 3211 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
85f9feb6 3212 XGBE_SET_SUP(lks, 10000baseR_FEC);
47f164de
LT		 3213 phy_data->start_mode = XGBE_MODE_KR;
3214 }
abf0a1c2
LT		 3215
3216 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
47f164de
LT		 3217 break;
3218 case XGBE_PORT_MODE_BACKPLANE_2500:
85f9feb6
LT		 3219 XGBE_SET_SUP(lks, Pause);
3220 XGBE_SET_SUP(lks, Asym_Pause);
3221 XGBE_SET_SUP(lks, Backplane);
3222 XGBE_SET_SUP(lks, 2500baseX_Full);
47f164de 3223 phy_data->start_mode = XGBE_MODE_KX_2500;
abf0a1c2
LT		 3224
3225 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
47f164de 3226 break;
732f2ab7
LT		 3227
3228 /* MDIO 1GBase-T support */
47f164de 3229 case XGBE_PORT_MODE_1000BASE_T:
85f9feb6
LT		 3230 XGBE_SET_SUP(lks, Autoneg);
3231 XGBE_SET_SUP(lks, Pause);
3232 XGBE_SET_SUP(lks, Asym_Pause);
3233 XGBE_SET_SUP(lks, TP);
732f2ab7 3234 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
85f9feb6 3235 XGBE_SET_SUP(lks, 100baseT_Full);
732f2ab7
LT		 3236 phy_data->start_mode = XGBE_MODE_SGMII_100;
3237 }
3238 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
85f9feb6 3239 XGBE_SET_SUP(lks, 1000baseT_Full);
732f2ab7
LT		 3240 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3241 }
3242
3243 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3244 break;
3245
3246 /* MDIO Base-X support */
47f164de 3247 case XGBE_PORT_MODE_1000BASE_X:
85f9feb6
LT		 3248 XGBE_SET_SUP(lks, Autoneg);
3249 XGBE_SET_SUP(lks, Pause);
3250 XGBE_SET_SUP(lks, Asym_Pause);
3251 XGBE_SET_SUP(lks, FIBRE);
3252 XGBE_SET_SUP(lks, 1000baseX_Full);
732f2ab7
LT		 3253 phy_data->start_mode = XGBE_MODE_X;
3254
3255 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3256 break;
3257
3258 /* MDIO NBase-T support */
47f164de 3259 case XGBE_PORT_MODE_NBASE_T:
85f9feb6
LT		 3260 XGBE_SET_SUP(lks, Autoneg);
3261 XGBE_SET_SUP(lks, Pause);
3262 XGBE_SET_SUP(lks, Asym_Pause);
3263 XGBE_SET_SUP(lks, TP);
732f2ab7 3264 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
85f9feb6 3265 XGBE_SET_SUP(lks, 100baseT_Full);
732f2ab7
LT		 3266 phy_data->start_mode = XGBE_MODE_SGMII_100;
3267 }
3268 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
85f9feb6 3269 XGBE_SET_SUP(lks, 1000baseT_Full);
732f2ab7
LT		 3270 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3271 }
3272 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
85f9feb6 3273 XGBE_SET_SUP(lks, 2500baseT_Full);
732f2ab7
LT		 3274 phy_data->start_mode = XGBE_MODE_KX_2500;
3275 }
3276
3277 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3278 break;
3279
3280 /* 10GBase-T support */
47f164de 3281 case XGBE_PORT_MODE_10GBASE_T:
85f9feb6
LT		 3282 XGBE_SET_SUP(lks, Autoneg);
3283 XGBE_SET_SUP(lks, Pause);
3284 XGBE_SET_SUP(lks, Asym_Pause);
3285 XGBE_SET_SUP(lks, TP);
732f2ab7 3286 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
85f9feb6 3287 XGBE_SET_SUP(lks, 100baseT_Full);
732f2ab7
LT		 3288 phy_data->start_mode = XGBE_MODE_SGMII_100;
3289 }
3290 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
85f9feb6 3291 XGBE_SET_SUP(lks, 1000baseT_Full);
732f2ab7
LT		 3292 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3293 }
3294 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
85f9feb6 3295 XGBE_SET_SUP(lks, 10000baseT_Full);
732f2ab7
LT		 3296 phy_data->start_mode = XGBE_MODE_KR;
3297 }
3298
3b1ded4e 3299 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
732f2ab7
LT		 3300 break;
3301
3302 /* 10GBase-R support */
47f164de 3303 case XGBE_PORT_MODE_10GBASE_R:
85f9feb6
LT		 3304 XGBE_SET_SUP(lks, Autoneg);
3305 XGBE_SET_SUP(lks, Pause);
3306 XGBE_SET_SUP(lks, Asym_Pause);
3307 XGBE_SET_SUP(lks, FIBRE);
3308 XGBE_SET_SUP(lks, 10000baseSR_Full);
3309 XGBE_SET_SUP(lks, 10000baseLR_Full);
3310 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3311 XGBE_SET_SUP(lks, 10000baseER_Full);
732f2ab7 3312 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
85f9feb6 3313 XGBE_SET_SUP(lks, 10000baseR_FEC);
732f2ab7
LT		 3314 phy_data->start_mode = XGBE_MODE_SFI;
3315
3316 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3317 break;
3318
3319 /* SFP support */
47f164de 3320 case XGBE_PORT_MODE_SFP:
85f9feb6
LT		 3321 XGBE_SET_SUP(lks, Autoneg);
3322 XGBE_SET_SUP(lks, Pause);
3323 XGBE_SET_SUP(lks, Asym_Pause);
3324 XGBE_SET_SUP(lks, TP);
3325 XGBE_SET_SUP(lks, FIBRE);
3326 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
abf0a1c2 3327 phy_data->start_mode = XGBE_MODE_SGMII_100;
85f9feb6 3328 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
abf0a1c2 3329 phy_data->start_mode = XGBE_MODE_SGMII_1000;
85f9feb6 3330 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
abf0a1c2 3331 phy_data->start_mode = XGBE_MODE_SFI;
abf0a1c2
LT		 3332
3333 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3334
3335 xgbe_phy_sfp_setup(pdata);
3336 break;
47f164de
LT		 3337 default:
3338 return -EINVAL;
3339 }
3340
3341 if (netif_msg_probe(pdata))
85f9feb6
LT		 3342 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3343 __ETHTOOL_LINK_MODE_MASK_NBITS,
3344 lks->link_modes.supported);
47f164de 3345
d7445d1f
LT		 3346 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3347 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3348 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3349 phy_data->phydev_mode);
3350 if (ret) {
3351 dev_err(pdata->dev,
3352 "mdio port/clause not compatible (%d/%u)\n",
3353 phy_data->mdio_addr, phy_data->phydev_mode);
3354 return -EINVAL;
3355 }
3356 }
3357
3358 if (phy_data->redrv && !phy_data->redrv_if) {
3359 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3360 XGBE_MDIO_MODE_CL22);
3361 if (ret) {
3362 dev_err(pdata->dev,
3363 "redriver mdio port not compatible (%u)\n",
3364 phy_data->redrv_addr);
3365 return -EINVAL;
3366 }
3367 }
3368
96f4d430
TL		 3369 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3370
abf0a1c2
LT		 3371 /* Register for driving external PHYs */
3372 mii = devm_mdiobus_alloc(pdata->dev);
3373 if (!mii) {
3374 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3375 return -ENOMEM;
3376 }
3377
3378 mii->priv = pdata;
3379 mii->name = "amd-xgbe-mii";
3380 mii->read = xgbe_phy_mii_read;
3381 mii->write = xgbe_phy_mii_write;
3382 mii->parent = pdata->dev;
3383 mii->phy_mask = ~0;
3384 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3385 ret = mdiobus_register(mii);
3386 if (ret) {
3387 dev_err(pdata->dev, "mdiobus_register failed\n");
3388 return ret;
3389 }
3390 phy_data->mii = mii;
3391
47f164de
LT		 3392 return 0;
3393}
3394
3395void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3396{
3397 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3398
3399 phy_impl->init = xgbe_phy_init;
3400 phy_impl->exit = xgbe_phy_exit;
3401
3402 phy_impl->reset = xgbe_phy_reset;
3403 phy_impl->start = xgbe_phy_start;
3404 phy_impl->stop = xgbe_phy_stop;
3405
3406 phy_impl->link_status = xgbe_phy_link_status;
3407
3408 phy_impl->valid_speed = xgbe_phy_valid_speed;
3409
3410 phy_impl->use_mode = xgbe_phy_use_mode;
3411 phy_impl->set_mode = xgbe_phy_set_mode;
3412 phy_impl->get_mode = xgbe_phy_get_mode;
3413 phy_impl->switch_mode = xgbe_phy_switch_mode;
3414 phy_impl->cur_mode = xgbe_phy_cur_mode;
3415
3416 phy_impl->an_mode = xgbe_phy_an_mode;
3417
abf0a1c2
LT		 3418 phy_impl->an_config = xgbe_phy_an_config;
3419
d7445d1f
LT		 3420 phy_impl->an_advertising = xgbe_phy_an_advertising;
3421
47f164de 3422 phy_impl->an_outcome = xgbe_phy_an_outcome;
96f4d430
TL		 3423
3424 phy_impl->an_pre = xgbe_phy_an_pre;
3425 phy_impl->an_post = xgbe_phy_an_post;
3426
3427 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3428 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
53a1024a
TL		 3429
3430 phy_impl->module_info = xgbe_phy_module_info;
3431 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
47f164de 3432}
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