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e6ad7673 IS |
1 | /* Applied Micro X-Gene SoC Ethernet Driver |
2 | * | |
3 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
4 | * Authors: Iyappan Subramanian <isubramanian@apm.com> | |
5 | * Ravi Patel <rapatel@apm.com> | |
6 | * Keyur Chudgar <kchudgar@apm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
27ecf87c | 22 | #include <linux/gpio.h> |
e6ad7673 IS |
23 | #include "xgene_enet_main.h" |
24 | #include "xgene_enet_hw.h" | |
32f784b5 | 25 | #include "xgene_enet_sgmac.h" |
0148d38d | 26 | #include "xgene_enet_xgmac.h" |
e6ad7673 | 27 | |
de7b5b3d FK |
28 | #define RES_ENET_CSR 0 |
29 | #define RES_RING_CSR 1 | |
30 | #define RES_RING_CMD 2 | |
31 | ||
bc1b7c13 | 32 | static const struct of_device_id xgene_enet_of_match[]; |
0738c54d | 33 | static const struct acpi_device_id xgene_enet_acpi_match[]; |
bc1b7c13 | 34 | |
e6ad7673 IS |
35 | static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool) |
36 | { | |
37 | struct xgene_enet_raw_desc16 *raw_desc; | |
38 | int i; | |
39 | ||
a9380b0f IS |
40 | if (!buf_pool) |
41 | return; | |
42 | ||
e6ad7673 IS |
43 | for (i = 0; i < buf_pool->slots; i++) { |
44 | raw_desc = &buf_pool->raw_desc16[i]; | |
45 | ||
46 | /* Hardware expects descriptor in little endian format */ | |
47 | raw_desc->m0 = cpu_to_le64(i | | |
48 | SET_VAL(FPQNUM, buf_pool->dst_ring_num) | | |
49 | SET_VAL(STASH, 3)); | |
50 | } | |
51 | } | |
52 | ||
a9380b0f IS |
53 | static u16 xgene_enet_get_data_len(u64 bufdatalen) |
54 | { | |
55 | u16 hw_len, mask; | |
56 | ||
57 | hw_len = GET_VAL(BUFDATALEN, bufdatalen); | |
58 | ||
59 | if (unlikely(hw_len == 0x7800)) { | |
60 | return 0; | |
61 | } else if (!(hw_len & BIT(14))) { | |
62 | mask = GENMASK(13, 0); | |
63 | return (hw_len & mask) ? (hw_len & mask) : SIZE_16K; | |
64 | } else if (!(hw_len & GENMASK(13, 12))) { | |
65 | mask = GENMASK(11, 0); | |
66 | return (hw_len & mask) ? (hw_len & mask) : SIZE_4K; | |
67 | } else { | |
68 | mask = GENMASK(11, 0); | |
69 | return (hw_len & mask) ? (hw_len & mask) : SIZE_2K; | |
70 | } | |
71 | } | |
72 | ||
73 | static u16 xgene_enet_set_data_len(u32 size) | |
74 | { | |
75 | u16 hw_len; | |
76 | ||
77 | hw_len = (size == SIZE_4K) ? BIT(14) : 0; | |
78 | ||
79 | return hw_len; | |
80 | } | |
81 | ||
82 | static int xgene_enet_refill_pagepool(struct xgene_enet_desc_ring *buf_pool, | |
83 | u32 nbuf) | |
84 | { | |
85 | struct xgene_enet_raw_desc16 *raw_desc; | |
86 | struct xgene_enet_pdata *pdata; | |
87 | struct net_device *ndev; | |
88 | dma_addr_t dma_addr; | |
89 | struct device *dev; | |
90 | struct page *page; | |
91 | u32 slots, tail; | |
92 | u16 hw_len; | |
93 | int i; | |
94 | ||
95 | if (unlikely(!buf_pool)) | |
96 | return 0; | |
97 | ||
98 | ndev = buf_pool->ndev; | |
99 | pdata = netdev_priv(ndev); | |
100 | dev = ndev_to_dev(ndev); | |
101 | slots = buf_pool->slots - 1; | |
102 | tail = buf_pool->tail; | |
103 | ||
104 | for (i = 0; i < nbuf; i++) { | |
105 | raw_desc = &buf_pool->raw_desc16[tail]; | |
106 | ||
107 | page = dev_alloc_page(); | |
108 | if (unlikely(!page)) | |
109 | return -ENOMEM; | |
110 | ||
111 | dma_addr = dma_map_page(dev, page, 0, | |
112 | PAGE_SIZE, DMA_FROM_DEVICE); | |
113 | if (unlikely(dma_mapping_error(dev, dma_addr))) { | |
114 | put_page(page); | |
115 | return -ENOMEM; | |
116 | } | |
117 | ||
118 | hw_len = xgene_enet_set_data_len(PAGE_SIZE); | |
119 | raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | | |
120 | SET_VAL(BUFDATALEN, hw_len) | | |
121 | SET_BIT(COHERENT)); | |
122 | ||
123 | buf_pool->frag_page[tail] = page; | |
124 | tail = (tail + 1) & slots; | |
125 | } | |
126 | ||
127 | pdata->ring_ops->wr_cmd(buf_pool, nbuf); | |
128 | buf_pool->tail = tail; | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
e6ad7673 IS |
133 | static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool, |
134 | u32 nbuf) | |
135 | { | |
136 | struct sk_buff *skb; | |
137 | struct xgene_enet_raw_desc16 *raw_desc; | |
81cefb81 | 138 | struct xgene_enet_pdata *pdata; |
e6ad7673 IS |
139 | struct net_device *ndev; |
140 | struct device *dev; | |
141 | dma_addr_t dma_addr; | |
142 | u32 tail = buf_pool->tail; | |
143 | u32 slots = buf_pool->slots - 1; | |
144 | u16 bufdatalen, len; | |
145 | int i; | |
146 | ||
147 | ndev = buf_pool->ndev; | |
148 | dev = ndev_to_dev(buf_pool->ndev); | |
81cefb81 | 149 | pdata = netdev_priv(ndev); |
a9380b0f | 150 | |
e6ad7673 | 151 | bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0)); |
a9380b0f | 152 | len = XGENE_ENET_STD_MTU; |
e6ad7673 IS |
153 | |
154 | for (i = 0; i < nbuf; i++) { | |
155 | raw_desc = &buf_pool->raw_desc16[tail]; | |
156 | ||
157 | skb = netdev_alloc_skb_ip_align(ndev, len); | |
158 | if (unlikely(!skb)) | |
159 | return -ENOMEM; | |
e6ad7673 IS |
160 | |
161 | dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE); | |
162 | if (dma_mapping_error(dev, dma_addr)) { | |
163 | netdev_err(ndev, "DMA mapping error\n"); | |
164 | dev_kfree_skb_any(skb); | |
165 | return -EINVAL; | |
166 | } | |
167 | ||
6e434627 IS |
168 | buf_pool->rx_skb[tail] = skb; |
169 | ||
e6ad7673 IS |
170 | raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | |
171 | SET_VAL(BUFDATALEN, bufdatalen) | | |
172 | SET_BIT(COHERENT)); | |
173 | tail = (tail + 1) & slots; | |
174 | } | |
175 | ||
81cefb81 | 176 | pdata->ring_ops->wr_cmd(buf_pool, nbuf); |
e6ad7673 IS |
177 | buf_pool->tail = tail; |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
e6ad7673 IS |
182 | static u8 xgene_enet_hdr_len(const void *data) |
183 | { | |
184 | const struct ethhdr *eth = data; | |
185 | ||
186 | return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN; | |
187 | } | |
188 | ||
e6ad7673 IS |
189 | static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool) |
190 | { | |
6e434627 IS |
191 | struct device *dev = ndev_to_dev(buf_pool->ndev); |
192 | struct xgene_enet_raw_desc16 *raw_desc; | |
193 | dma_addr_t dma_addr; | |
cb11c062 | 194 | int i; |
e6ad7673 | 195 | |
cb11c062 IS |
196 | /* Free up the buffers held by hardware */ |
197 | for (i = 0; i < buf_pool->slots; i++) { | |
6e434627 | 198 | if (buf_pool->rx_skb[i]) { |
cb11c062 | 199 | dev_kfree_skb_any(buf_pool->rx_skb[i]); |
6e434627 IS |
200 | |
201 | raw_desc = &buf_pool->raw_desc16[i]; | |
202 | dma_addr = GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)); | |
203 | dma_unmap_single(dev, dma_addr, XGENE_ENET_MAX_MTU, | |
204 | DMA_FROM_DEVICE); | |
205 | } | |
e6ad7673 | 206 | } |
e6ad7673 IS |
207 | } |
208 | ||
a9380b0f IS |
209 | static void xgene_enet_delete_pagepool(struct xgene_enet_desc_ring *buf_pool) |
210 | { | |
211 | struct device *dev = ndev_to_dev(buf_pool->ndev); | |
212 | dma_addr_t dma_addr; | |
213 | struct page *page; | |
214 | int i; | |
215 | ||
216 | /* Free up the buffers held by hardware */ | |
217 | for (i = 0; i < buf_pool->slots; i++) { | |
218 | page = buf_pool->frag_page[i]; | |
219 | if (page) { | |
220 | dma_addr = buf_pool->frag_dma_addr[i]; | |
221 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, | |
222 | DMA_FROM_DEVICE); | |
223 | put_page(page); | |
224 | } | |
225 | } | |
226 | } | |
227 | ||
e6ad7673 IS |
228 | static irqreturn_t xgene_enet_rx_irq(const int irq, void *data) |
229 | { | |
230 | struct xgene_enet_desc_ring *rx_ring = data; | |
231 | ||
232 | if (napi_schedule_prep(&rx_ring->napi)) { | |
233 | disable_irq_nosync(irq); | |
234 | __napi_schedule(&rx_ring->napi); | |
235 | } | |
236 | ||
237 | return IRQ_HANDLED; | |
238 | } | |
239 | ||
240 | static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring, | |
241 | struct xgene_enet_raw_desc *raw_desc) | |
242 | { | |
e3978673 | 243 | struct xgene_enet_pdata *pdata = netdev_priv(cp_ring->ndev); |
e6ad7673 IS |
244 | struct sk_buff *skb; |
245 | struct device *dev; | |
9b00eb49 IS |
246 | skb_frag_t *frag; |
247 | dma_addr_t *frag_dma_addr; | |
e6ad7673 | 248 | u16 skb_index; |
e3978673 | 249 | u8 mss_index; |
089f97c7 QN |
250 | u8 status; |
251 | int i; | |
e6ad7673 IS |
252 | |
253 | skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); | |
254 | skb = cp_ring->cp_skb[skb_index]; | |
9b00eb49 | 255 | frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS]; |
e6ad7673 IS |
256 | |
257 | dev = ndev_to_dev(cp_ring->ndev); | |
258 | dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), | |
9b00eb49 | 259 | skb_headlen(skb), |
e6ad7673 IS |
260 | DMA_TO_DEVICE); |
261 | ||
9b00eb49 IS |
262 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
263 | frag = &skb_shinfo(skb)->frags[i]; | |
264 | dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag), | |
265 | DMA_TO_DEVICE); | |
266 | } | |
267 | ||
e3978673 IS |
268 | if (GET_BIT(ET, le64_to_cpu(raw_desc->m3))) { |
269 | mss_index = GET_VAL(MSS, le64_to_cpu(raw_desc->m3)); | |
270 | spin_lock(&pdata->mss_lock); | |
271 | pdata->mss_refcnt[mss_index]--; | |
272 | spin_unlock(&pdata->mss_lock); | |
273 | } | |
274 | ||
e6ad7673 IS |
275 | /* Checking for error */ |
276 | status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); | |
277 | if (unlikely(status > 2)) { | |
089f97c7 QN |
278 | cp_ring->tx_dropped++; |
279 | cp_ring->tx_errors++; | |
e6ad7673 IS |
280 | } |
281 | ||
282 | if (likely(skb)) { | |
283 | dev_kfree_skb_any(skb); | |
284 | } else { | |
285 | netdev_err(cp_ring->ndev, "completion skb is NULL\n"); | |
e6ad7673 IS |
286 | } |
287 | ||
089f97c7 | 288 | return 0; |
e6ad7673 IS |
289 | } |
290 | ||
e3978673 IS |
291 | static int xgene_enet_setup_mss(struct net_device *ndev, u32 mss) |
292 | { | |
293 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
1b8c1012 | 294 | int mss_index = -EBUSY; |
e3978673 IS |
295 | int i; |
296 | ||
297 | spin_lock(&pdata->mss_lock); | |
298 | ||
299 | /* Reuse the slot if MSS matches */ | |
1b8c1012 | 300 | for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) { |
e3978673 IS |
301 | if (pdata->mss[i] == mss) { |
302 | pdata->mss_refcnt[i]++; | |
303 | mss_index = i; | |
e3978673 IS |
304 | } |
305 | } | |
306 | ||
307 | /* Overwrite the slot with ref_count = 0 */ | |
1b8c1012 | 308 | for (i = 0; mss_index < 0 && i < NUM_MSS_REG; i++) { |
e3978673 IS |
309 | if (!pdata->mss_refcnt[i]) { |
310 | pdata->mss_refcnt[i]++; | |
311 | pdata->mac_ops->set_mss(pdata, mss, i); | |
312 | pdata->mss[i] = mss; | |
313 | mss_index = i; | |
e3978673 IS |
314 | } |
315 | } | |
316 | ||
f006b2c5 | 317 | spin_unlock(&pdata->mss_lock); |
e3978673 IS |
318 | |
319 | return mss_index; | |
320 | } | |
321 | ||
322 | static int xgene_enet_work_msg(struct sk_buff *skb, u64 *hopinfo) | |
e6ad7673 | 323 | { |
9b00eb49 | 324 | struct net_device *ndev = skb->dev; |
e6ad7673 | 325 | struct iphdr *iph; |
9b00eb49 IS |
326 | u8 l3hlen = 0, l4hlen = 0; |
327 | u8 ethhdr, proto = 0, csum_enable = 0; | |
9b00eb49 IS |
328 | u32 hdr_len, mss = 0; |
329 | u32 i, len, nr_frags; | |
e3978673 | 330 | int mss_index; |
9b00eb49 IS |
331 | |
332 | ethhdr = xgene_enet_hdr_len(skb->data); | |
e6ad7673 IS |
333 | |
334 | if (unlikely(skb->protocol != htons(ETH_P_IP)) && | |
335 | unlikely(skb->protocol != htons(ETH_P_8021Q))) | |
336 | goto out; | |
337 | ||
338 | if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM))) | |
339 | goto out; | |
340 | ||
341 | iph = ip_hdr(skb); | |
342 | if (unlikely(ip_is_fragment(iph))) | |
343 | goto out; | |
344 | ||
345 | if (likely(iph->protocol == IPPROTO_TCP)) { | |
346 | l4hlen = tcp_hdrlen(skb) >> 2; | |
347 | csum_enable = 1; | |
348 | proto = TSO_IPPROTO_TCP; | |
9b00eb49 IS |
349 | if (ndev->features & NETIF_F_TSO) { |
350 | hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb); | |
351 | mss = skb_shinfo(skb)->gso_size; | |
352 | ||
353 | if (skb_is_nonlinear(skb)) { | |
354 | len = skb_headlen(skb); | |
355 | nr_frags = skb_shinfo(skb)->nr_frags; | |
356 | ||
357 | for (i = 0; i < 2 && i < nr_frags; i++) | |
358 | len += skb_shinfo(skb)->frags[i].size; | |
359 | ||
360 | /* HW requires header must reside in 3 buffer */ | |
361 | if (unlikely(hdr_len > len)) { | |
362 | if (skb_linearize(skb)) | |
363 | return 0; | |
364 | } | |
365 | } | |
366 | ||
367 | if (!mss || ((skb->len - hdr_len) <= mss)) | |
368 | goto out; | |
369 | ||
e3978673 IS |
370 | mss_index = xgene_enet_setup_mss(ndev, mss); |
371 | if (unlikely(mss_index < 0)) | |
372 | return -EBUSY; | |
373 | ||
374 | *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); | |
9b00eb49 | 375 | } |
e6ad7673 IS |
376 | } else if (iph->protocol == IPPROTO_UDP) { |
377 | l4hlen = UDP_HDR_SIZE; | |
378 | csum_enable = 1; | |
379 | } | |
380 | out: | |
381 | l3hlen = ip_hdrlen(skb) >> 2; | |
e3978673 IS |
382 | *hopinfo |= SET_VAL(TCPHDR, l4hlen) | |
383 | SET_VAL(IPHDR, l3hlen) | | |
384 | SET_VAL(ETHHDR, ethhdr) | | |
385 | SET_VAL(EC, csum_enable) | | |
386 | SET_VAL(IS, proto) | | |
387 | SET_BIT(IC) | | |
388 | SET_BIT(TYPE_ETH_WORK_MESSAGE); | |
389 | ||
390 | return 0; | |
e6ad7673 IS |
391 | } |
392 | ||
949c40bb IS |
393 | static u16 xgene_enet_encode_len(u16 len) |
394 | { | |
395 | return (len == BUFLEN_16K) ? 0 : len; | |
396 | } | |
397 | ||
9b00eb49 IS |
398 | static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len) |
399 | { | |
400 | desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) | | |
401 | SET_VAL(BUFDATALEN, len)); | |
402 | } | |
403 | ||
404 | static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring) | |
405 | { | |
406 | __le64 *exp_bufs; | |
407 | ||
408 | exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS]; | |
409 | memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS); | |
410 | ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1); | |
411 | ||
412 | return exp_bufs; | |
413 | } | |
414 | ||
415 | static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring) | |
416 | { | |
417 | return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS]; | |
418 | } | |
419 | ||
e6ad7673 IS |
420 | static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring, |
421 | struct sk_buff *skb) | |
422 | { | |
423 | struct device *dev = ndev_to_dev(tx_ring->ndev); | |
67894eec | 424 | struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev); |
e6ad7673 | 425 | struct xgene_enet_raw_desc *raw_desc; |
9b00eb49 IS |
426 | __le64 *exp_desc = NULL, *exp_bufs = NULL; |
427 | dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr; | |
428 | skb_frag_t *frag; | |
e6ad7673 | 429 | u16 tail = tx_ring->tail; |
e3978673 | 430 | u64 hopinfo = 0; |
949c40bb | 431 | u32 len, hw_len; |
9b00eb49 IS |
432 | u8 ll = 0, nv = 0, idx = 0; |
433 | bool split = false; | |
434 | u32 size, offset, ell_bytes = 0; | |
435 | u32 i, fidx, nr_frags, count = 1; | |
e3978673 | 436 | int ret; |
e6ad7673 IS |
437 | |
438 | raw_desc = &tx_ring->raw_desc[tail]; | |
9b00eb49 | 439 | tail = (tail + 1) & (tx_ring->slots - 1); |
e6ad7673 IS |
440 | memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc)); |
441 | ||
e3978673 IS |
442 | ret = xgene_enet_work_msg(skb, &hopinfo); |
443 | if (ret) | |
444 | return ret; | |
445 | ||
9b00eb49 IS |
446 | raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) | |
447 | hopinfo); | |
448 | ||
949c40bb IS |
449 | len = skb_headlen(skb); |
450 | hw_len = xgene_enet_encode_len(len); | |
451 | ||
452 | dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE); | |
e6ad7673 IS |
453 | if (dma_mapping_error(dev, dma_addr)) { |
454 | netdev_err(tx_ring->ndev, "DMA mapping error\n"); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
458 | /* Hardware expects descriptor in little endian format */ | |
e6ad7673 | 459 | raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | |
949c40bb | 460 | SET_VAL(BUFDATALEN, hw_len) | |
e6ad7673 | 461 | SET_BIT(COHERENT)); |
949c40bb | 462 | |
9b00eb49 IS |
463 | if (!skb_is_nonlinear(skb)) |
464 | goto out; | |
e6ad7673 | 465 | |
9b00eb49 IS |
466 | /* scatter gather */ |
467 | nv = 1; | |
468 | exp_desc = (void *)&tx_ring->raw_desc[tail]; | |
949c40bb | 469 | tail = (tail + 1) & (tx_ring->slots - 1); |
9b00eb49 IS |
470 | memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc)); |
471 | ||
472 | nr_frags = skb_shinfo(skb)->nr_frags; | |
473 | for (i = nr_frags; i < 4 ; i++) | |
474 | exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER); | |
475 | ||
476 | frag_dma_addr = xgene_get_frag_dma_array(tx_ring); | |
477 | ||
478 | for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) { | |
479 | if (!split) { | |
480 | frag = &skb_shinfo(skb)->frags[fidx]; | |
481 | size = skb_frag_size(frag); | |
482 | offset = 0; | |
483 | ||
484 | pbuf_addr = skb_frag_dma_map(dev, frag, 0, size, | |
485 | DMA_TO_DEVICE); | |
486 | if (dma_mapping_error(dev, pbuf_addr)) | |
487 | return -EINVAL; | |
488 | ||
489 | frag_dma_addr[fidx] = pbuf_addr; | |
490 | fidx++; | |
491 | ||
492 | if (size > BUFLEN_16K) | |
493 | split = true; | |
494 | } | |
495 | ||
496 | if (size > BUFLEN_16K) { | |
497 | len = BUFLEN_16K; | |
498 | size -= BUFLEN_16K; | |
499 | } else { | |
500 | len = size; | |
501 | split = false; | |
502 | } | |
503 | ||
504 | dma_addr = pbuf_addr + offset; | |
505 | hw_len = xgene_enet_encode_len(len); | |
506 | ||
507 | switch (i) { | |
508 | case 0: | |
509 | case 1: | |
510 | case 2: | |
511 | xgene_set_addr_len(exp_desc, i, dma_addr, hw_len); | |
512 | break; | |
513 | case 3: | |
514 | if (split || (fidx != nr_frags)) { | |
515 | exp_bufs = xgene_enet_get_exp_bufs(tx_ring); | |
516 | xgene_set_addr_len(exp_bufs, idx, dma_addr, | |
517 | hw_len); | |
518 | idx++; | |
519 | ell_bytes += len; | |
520 | } else { | |
521 | xgene_set_addr_len(exp_desc, i, dma_addr, | |
522 | hw_len); | |
523 | } | |
524 | break; | |
525 | default: | |
526 | xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len); | |
527 | idx++; | |
528 | ell_bytes += len; | |
529 | break; | |
530 | } | |
531 | ||
532 | if (split) | |
533 | offset += BUFLEN_16K; | |
534 | } | |
535 | count++; | |
536 | ||
537 | if (idx) { | |
538 | ll = 1; | |
539 | dma_addr = dma_map_single(dev, exp_bufs, | |
540 | sizeof(u64) * MAX_EXP_BUFFS, | |
541 | DMA_TO_DEVICE); | |
542 | if (dma_mapping_error(dev, dma_addr)) { | |
543 | dev_kfree_skb_any(skb); | |
544 | return -EINVAL; | |
545 | } | |
546 | i = ell_bytes >> LL_BYTES_LSB_LEN; | |
547 | exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) | | |
548 | SET_VAL(LL_BYTES_MSB, i) | | |
549 | SET_VAL(LL_LEN, idx)); | |
550 | raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes)); | |
551 | } | |
552 | ||
553 | out: | |
554 | raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) | | |
555 | SET_VAL(USERINFO, tx_ring->tail)); | |
556 | tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb; | |
107dec27 | 557 | pdata->tx_level[tx_ring->cp_ring->index] += count; |
949c40bb IS |
558 | tx_ring->tail = tail; |
559 | ||
560 | return count; | |
e6ad7673 IS |
561 | } |
562 | ||
563 | static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb, | |
564 | struct net_device *ndev) | |
565 | { | |
566 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
107dec27 IS |
567 | struct xgene_enet_desc_ring *tx_ring; |
568 | int index = skb->queue_mapping; | |
569 | u32 tx_level = pdata->tx_level[index]; | |
949c40bb | 570 | int count; |
e6ad7673 | 571 | |
107dec27 IS |
572 | tx_ring = pdata->tx_ring[index]; |
573 | if (tx_level < pdata->txc_level[index]) | |
574 | tx_level += ((typeof(pdata->tx_level[index]))~0U); | |
67894eec | 575 | |
107dec27 IS |
576 | if ((tx_level - pdata->txc_level[index]) > pdata->tx_qcnt_hi) { |
577 | netif_stop_subqueue(ndev, index); | |
e6ad7673 IS |
578 | return NETDEV_TX_BUSY; |
579 | } | |
580 | ||
9b00eb49 IS |
581 | if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE)) |
582 | return NETDEV_TX_OK; | |
583 | ||
949c40bb | 584 | count = xgene_enet_setup_tx_desc(tx_ring, skb); |
e3978673 IS |
585 | if (count == -EBUSY) |
586 | return NETDEV_TX_BUSY; | |
587 | ||
949c40bb | 588 | if (count <= 0) { |
e6ad7673 IS |
589 | dev_kfree_skb_any(skb); |
590 | return NETDEV_TX_OK; | |
591 | } | |
592 | ||
e6ad7673 | 593 | skb_tx_timestamp(skb); |
e6ad7673 | 594 | |
3bb502f8 IS |
595 | tx_ring->tx_packets++; |
596 | tx_ring->tx_bytes += skb->len; | |
e6ad7673 | 597 | |
9ffad80a | 598 | pdata->ring_ops->wr_cmd(tx_ring, count); |
e6ad7673 IS |
599 | return NETDEV_TX_OK; |
600 | } | |
601 | ||
0a0400c3 | 602 | static void xgene_enet_rx_csum(struct sk_buff *skb) |
e6ad7673 | 603 | { |
0a0400c3 | 604 | struct net_device *ndev = skb->dev; |
e6ad7673 IS |
605 | struct iphdr *iph = ip_hdr(skb); |
606 | ||
0a0400c3 IS |
607 | if (!(ndev->features & NETIF_F_RXCSUM)) |
608 | return; | |
609 | ||
610 | if (skb->protocol != htons(ETH_P_IP)) | |
611 | return; | |
612 | ||
613 | if (ip_is_fragment(iph)) | |
614 | return; | |
615 | ||
616 | if (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP) | |
617 | return; | |
618 | ||
619 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
e6ad7673 IS |
620 | } |
621 | ||
a9380b0f IS |
622 | static void xgene_enet_free_pagepool(struct xgene_enet_desc_ring *buf_pool, |
623 | struct xgene_enet_raw_desc *raw_desc, | |
624 | struct xgene_enet_raw_desc *exp_desc) | |
625 | { | |
626 | __le64 *desc = (void *)exp_desc; | |
627 | dma_addr_t dma_addr; | |
628 | struct device *dev; | |
629 | struct page *page; | |
630 | u16 slots, head; | |
631 | u32 frag_size; | |
632 | int i; | |
633 | ||
634 | if (!buf_pool || !raw_desc || !exp_desc || | |
635 | (!GET_VAL(NV, le64_to_cpu(raw_desc->m0)))) | |
636 | return; | |
637 | ||
638 | dev = ndev_to_dev(buf_pool->ndev); | |
0b801290 | 639 | slots = buf_pool->slots - 1; |
a9380b0f IS |
640 | head = buf_pool->head; |
641 | ||
642 | for (i = 0; i < 4; i++) { | |
643 | frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); | |
644 | if (!frag_size) | |
645 | break; | |
646 | ||
647 | dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); | |
648 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); | |
649 | ||
650 | page = buf_pool->frag_page[head]; | |
651 | put_page(page); | |
652 | ||
653 | buf_pool->frag_page[head] = NULL; | |
654 | head = (head + 1) & slots; | |
655 | } | |
656 | buf_pool->head = head; | |
657 | } | |
658 | ||
61c759cd QN |
659 | /* Errata 10GE_10 and ENET_15 - Fix duplicated HW statistic counters */ |
660 | static bool xgene_enet_errata_10GE_10(struct sk_buff *skb, u32 len, u8 status) | |
661 | { | |
662 | if (status == INGRESS_CRC && | |
663 | len >= (ETHER_STD_PACKET + 1) && | |
664 | len <= (ETHER_STD_PACKET + 4) && | |
665 | skb->protocol == htons(ETH_P_8021Q)) | |
666 | return true; | |
667 | ||
668 | return false; | |
669 | } | |
670 | ||
4902a922 IS |
671 | /* Errata 10GE_8 and ENET_11 - allow packet with length <=64B */ |
672 | static bool xgene_enet_errata_10GE_8(struct sk_buff *skb, u32 len, u8 status) | |
673 | { | |
674 | if (status == INGRESS_PKT_LEN && len == ETHER_MIN_PACKET) { | |
675 | if (ntohs(eth_hdr(skb)->h_proto) < 46) | |
676 | return true; | |
677 | } | |
678 | ||
679 | return false; | |
680 | } | |
681 | ||
e6ad7673 | 682 | static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring, |
a9380b0f IS |
683 | struct xgene_enet_raw_desc *raw_desc, |
684 | struct xgene_enet_raw_desc *exp_desc) | |
e6ad7673 | 685 | { |
a9380b0f IS |
686 | struct xgene_enet_desc_ring *buf_pool, *page_pool; |
687 | u32 datalen, frag_size, skb_index; | |
4902a922 | 688 | struct xgene_enet_pdata *pdata; |
e6ad7673 | 689 | struct net_device *ndev; |
a9380b0f | 690 | dma_addr_t dma_addr; |
e6ad7673 | 691 | struct sk_buff *skb; |
a9380b0f IS |
692 | struct device *dev; |
693 | struct page *page; | |
694 | u16 slots, head; | |
695 | int i, ret = 0; | |
696 | __le64 *desc; | |
e6ad7673 | 697 | u8 status; |
a9380b0f | 698 | bool nv; |
e6ad7673 IS |
699 | |
700 | ndev = rx_ring->ndev; | |
4902a922 | 701 | pdata = netdev_priv(ndev); |
e6ad7673 IS |
702 | dev = ndev_to_dev(rx_ring->ndev); |
703 | buf_pool = rx_ring->buf_pool; | |
a9380b0f | 704 | page_pool = rx_ring->page_pool; |
e6ad7673 IS |
705 | |
706 | dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)), | |
a9380b0f | 707 | XGENE_ENET_STD_MTU, DMA_FROM_DEVICE); |
e6ad7673 IS |
708 | skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); |
709 | skb = buf_pool->rx_skb[skb_index]; | |
cb11c062 | 710 | buf_pool->rx_skb[skb_index] = NULL; |
e6ad7673 | 711 | |
4902a922 IS |
712 | datalen = xgene_enet_get_data_len(le64_to_cpu(raw_desc->m1)); |
713 | skb_put(skb, datalen); | |
714 | prefetch(skb->data - NET_IP_ALIGN); | |
715 | skb->protocol = eth_type_trans(skb, ndev); | |
716 | ||
e6ad7673 | 717 | /* checking for error */ |
11623fce | 718 | status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) | |
3bb502f8 | 719 | GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); |
11623fce | 720 | if (unlikely(status)) { |
61c759cd QN |
721 | if (xgene_enet_errata_10GE_8(skb, datalen, status)) { |
722 | pdata->false_rflr++; | |
723 | } else if (xgene_enet_errata_10GE_10(skb, datalen, status)) { | |
724 | pdata->vlan_rjbr++; | |
725 | } else { | |
4902a922 IS |
726 | dev_kfree_skb_any(skb); |
727 | xgene_enet_free_pagepool(page_pool, raw_desc, exp_desc); | |
089f97c7 QN |
728 | xgene_enet_parse_error(rx_ring, status); |
729 | rx_ring->rx_dropped++; | |
4902a922 IS |
730 | goto out; |
731 | } | |
e6ad7673 IS |
732 | } |
733 | ||
a9380b0f | 734 | nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); |
4902a922 IS |
735 | if (!nv) { |
736 | /* strip off CRC as HW isn't doing this */ | |
a9380b0f | 737 | datalen -= 4; |
a9380b0f | 738 | goto skip_jumbo; |
4902a922 | 739 | } |
a9380b0f IS |
740 | |
741 | slots = page_pool->slots - 1; | |
742 | head = page_pool->head; | |
743 | desc = (void *)exp_desc; | |
744 | ||
745 | for (i = 0; i < 4; i++) { | |
746 | frag_size = xgene_enet_get_data_len(le64_to_cpu(desc[i ^ 1])); | |
747 | if (!frag_size) | |
748 | break; | |
749 | ||
750 | dma_addr = GET_VAL(DATAADDR, le64_to_cpu(desc[i ^ 1])); | |
751 | dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); | |
752 | ||
753 | page = page_pool->frag_page[head]; | |
754 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, | |
755 | frag_size, PAGE_SIZE); | |
756 | ||
757 | datalen += frag_size; | |
758 | ||
759 | page_pool->frag_page[head] = NULL; | |
760 | head = (head + 1) & slots; | |
761 | } | |
762 | ||
763 | page_pool->head = head; | |
764 | rx_ring->npagepool -= skb_shinfo(skb)->nr_frags; | |
e6ad7673 | 765 | |
a9380b0f | 766 | skip_jumbo: |
e6ad7673 | 767 | skb_checksum_none_assert(skb); |
0a0400c3 | 768 | xgene_enet_rx_csum(skb); |
e6ad7673 | 769 | |
3bb502f8 IS |
770 | rx_ring->rx_packets++; |
771 | rx_ring->rx_bytes += datalen; | |
e6ad7673 | 772 | napi_gro_receive(&rx_ring->napi, skb); |
a9380b0f | 773 | |
e6ad7673 | 774 | out: |
a9380b0f IS |
775 | if (rx_ring->npagepool <= 0) { |
776 | ret = xgene_enet_refill_pagepool(page_pool, NUM_NXTBUFPOOL); | |
777 | rx_ring->npagepool = NUM_NXTBUFPOOL; | |
778 | if (ret) | |
779 | return ret; | |
780 | } | |
781 | ||
e6ad7673 IS |
782 | if (--rx_ring->nbufpool == 0) { |
783 | ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL); | |
784 | rx_ring->nbufpool = NUM_BUFPOOL; | |
785 | } | |
786 | ||
787 | return ret; | |
788 | } | |
789 | ||
790 | static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc) | |
791 | { | |
792 | return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; | |
793 | } | |
794 | ||
795 | static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring, | |
796 | int budget) | |
797 | { | |
107dec27 IS |
798 | struct net_device *ndev = ring->ndev; |
799 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
9b00eb49 | 800 | struct xgene_enet_raw_desc *raw_desc, *exp_desc; |
e6ad7673 IS |
801 | u16 head = ring->head; |
802 | u16 slots = ring->slots - 1; | |
67894eec IS |
803 | int ret, desc_count, count = 0, processed = 0; |
804 | bool is_completion; | |
e6ad7673 IS |
805 | |
806 | do { | |
807 | raw_desc = &ring->raw_desc[head]; | |
67894eec IS |
808 | desc_count = 0; |
809 | is_completion = false; | |
9b00eb49 | 810 | exp_desc = NULL; |
e6ad7673 IS |
811 | if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc))) |
812 | break; | |
813 | ||
ecf6ba83 IS |
814 | /* read fpqnum field after dataaddr field */ |
815 | dma_rmb(); | |
9b00eb49 IS |
816 | if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) { |
817 | head = (head + 1) & slots; | |
818 | exp_desc = &ring->raw_desc[head]; | |
819 | ||
820 | if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) { | |
821 | head = (head - 1) & slots; | |
822 | break; | |
823 | } | |
824 | dma_rmb(); | |
825 | count++; | |
67894eec | 826 | desc_count++; |
9b00eb49 | 827 | } |
67894eec | 828 | if (is_rx_desc(raw_desc)) { |
a9380b0f | 829 | ret = xgene_enet_rx_frame(ring, raw_desc, exp_desc); |
67894eec | 830 | } else { |
e6ad7673 | 831 | ret = xgene_enet_tx_completion(ring, raw_desc); |
67894eec IS |
832 | is_completion = true; |
833 | } | |
e6ad7673 | 834 | xgene_enet_mark_desc_slot_empty(raw_desc); |
9b00eb49 IS |
835 | if (exp_desc) |
836 | xgene_enet_mark_desc_slot_empty(exp_desc); | |
e6ad7673 IS |
837 | |
838 | head = (head + 1) & slots; | |
839 | count++; | |
67894eec | 840 | desc_count++; |
9b00eb49 | 841 | processed++; |
67894eec | 842 | if (is_completion) |
107dec27 | 843 | pdata->txc_level[ring->index] += desc_count; |
e6ad7673 IS |
844 | |
845 | if (ret) | |
846 | break; | |
847 | } while (--budget); | |
848 | ||
849 | if (likely(count)) { | |
81cefb81 | 850 | pdata->ring_ops->wr_cmd(ring, -count); |
e6ad7673 IS |
851 | ring->head = head; |
852 | ||
107dec27 IS |
853 | if (__netif_subqueue_stopped(ndev, ring->index)) |
854 | netif_start_subqueue(ndev, ring->index); | |
e6ad7673 IS |
855 | } |
856 | ||
9b00eb49 | 857 | return processed; |
e6ad7673 IS |
858 | } |
859 | ||
860 | static int xgene_enet_napi(struct napi_struct *napi, const int budget) | |
861 | { | |
862 | struct xgene_enet_desc_ring *ring; | |
863 | int processed; | |
864 | ||
865 | ring = container_of(napi, struct xgene_enet_desc_ring, napi); | |
866 | processed = xgene_enet_process_ring(ring, budget); | |
867 | ||
868 | if (processed != budget) { | |
6ad20165 | 869 | napi_complete_done(napi, processed); |
e6ad7673 IS |
870 | enable_irq(ring->irq); |
871 | } | |
872 | ||
873 | return processed; | |
874 | } | |
875 | ||
876 | static void xgene_enet_timeout(struct net_device *ndev) | |
877 | { | |
878 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
107dec27 IS |
879 | struct netdev_queue *txq; |
880 | int i; | |
e6ad7673 | 881 | |
d0eb7458 | 882 | pdata->mac_ops->reset(pdata); |
107dec27 IS |
883 | |
884 | for (i = 0; i < pdata->txq_cnt; i++) { | |
885 | txq = netdev_get_tx_queue(ndev, i); | |
886 | txq->trans_start = jiffies; | |
887 | netif_tx_start_queue(txq); | |
888 | } | |
e6ad7673 IS |
889 | } |
890 | ||
cb0366b7 IS |
891 | static void xgene_enet_set_irq_name(struct net_device *ndev) |
892 | { | |
893 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
894 | struct xgene_enet_desc_ring *ring; | |
895 | int i; | |
896 | ||
897 | for (i = 0; i < pdata->rxq_cnt; i++) { | |
898 | ring = pdata->rx_ring[i]; | |
899 | if (!pdata->cq_cnt) { | |
900 | snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc", | |
901 | ndev->name); | |
902 | } else { | |
903 | snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-rx-%d", | |
904 | ndev->name, i); | |
905 | } | |
906 | } | |
907 | ||
908 | for (i = 0; i < pdata->cq_cnt; i++) { | |
909 | ring = pdata->tx_ring[i]->cp_ring; | |
910 | snprintf(ring->irq_name, IRQ_ID_SIZE, "%s-txc-%d", | |
911 | ndev->name, i); | |
912 | } | |
913 | } | |
914 | ||
e6ad7673 IS |
915 | static int xgene_enet_register_irq(struct net_device *ndev) |
916 | { | |
917 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
918 | struct device *dev = ndev_to_dev(ndev); | |
6772b653 | 919 | struct xgene_enet_desc_ring *ring; |
107dec27 | 920 | int ret = 0, i; |
e6ad7673 | 921 | |
cb0366b7 | 922 | xgene_enet_set_irq_name(ndev); |
107dec27 IS |
923 | for (i = 0; i < pdata->rxq_cnt; i++) { |
924 | ring = pdata->rx_ring[i]; | |
925 | irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); | |
926 | ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, | |
46a22d29 | 927 | 0, ring->irq_name, ring); |
107dec27 IS |
928 | if (ret) { |
929 | netdev_err(ndev, "Failed to request irq %s\n", | |
930 | ring->irq_name); | |
931 | } | |
932 | } | |
6772b653 | 933 | |
107dec27 IS |
934 | for (i = 0; i < pdata->cq_cnt; i++) { |
935 | ring = pdata->tx_ring[i]->cp_ring; | |
b5d7a069 | 936 | irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); |
6772b653 | 937 | ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq, |
46a22d29 | 938 | 0, ring->irq_name, ring); |
6772b653 IS |
939 | if (ret) { |
940 | netdev_err(ndev, "Failed to request irq %s\n", | |
941 | ring->irq_name); | |
942 | } | |
e6ad7673 IS |
943 | } |
944 | ||
945 | return ret; | |
946 | } | |
947 | ||
948 | static void xgene_enet_free_irq(struct net_device *ndev) | |
949 | { | |
950 | struct xgene_enet_pdata *pdata; | |
b5d7a069 | 951 | struct xgene_enet_desc_ring *ring; |
e6ad7673 | 952 | struct device *dev; |
107dec27 | 953 | int i; |
e6ad7673 IS |
954 | |
955 | pdata = netdev_priv(ndev); | |
956 | dev = ndev_to_dev(ndev); | |
6772b653 | 957 | |
107dec27 IS |
958 | for (i = 0; i < pdata->rxq_cnt; i++) { |
959 | ring = pdata->rx_ring[i]; | |
960 | irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); | |
961 | devm_free_irq(dev, ring->irq, ring); | |
962 | } | |
963 | ||
964 | for (i = 0; i < pdata->cq_cnt; i++) { | |
965 | ring = pdata->tx_ring[i]->cp_ring; | |
b5d7a069 IS |
966 | irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY); |
967 | devm_free_irq(dev, ring->irq, ring); | |
6772b653 IS |
968 | } |
969 | } | |
970 | ||
971 | static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata) | |
972 | { | |
973 | struct napi_struct *napi; | |
107dec27 | 974 | int i; |
6772b653 | 975 | |
107dec27 IS |
976 | for (i = 0; i < pdata->rxq_cnt; i++) { |
977 | napi = &pdata->rx_ring[i]->napi; | |
978 | napi_enable(napi); | |
979 | } | |
6772b653 | 980 | |
107dec27 IS |
981 | for (i = 0; i < pdata->cq_cnt; i++) { |
982 | napi = &pdata->tx_ring[i]->cp_ring->napi; | |
6772b653 IS |
983 | napi_enable(napi); |
984 | } | |
985 | } | |
986 | ||
987 | static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata) | |
988 | { | |
989 | struct napi_struct *napi; | |
107dec27 | 990 | int i; |
6772b653 | 991 | |
107dec27 IS |
992 | for (i = 0; i < pdata->rxq_cnt; i++) { |
993 | napi = &pdata->rx_ring[i]->napi; | |
994 | napi_disable(napi); | |
995 | } | |
6772b653 | 996 | |
107dec27 IS |
997 | for (i = 0; i < pdata->cq_cnt; i++) { |
998 | napi = &pdata->tx_ring[i]->cp_ring->napi; | |
6772b653 IS |
999 | napi_disable(napi); |
1000 | } | |
e6ad7673 IS |
1001 | } |
1002 | ||
1003 | static int xgene_enet_open(struct net_device *ndev) | |
1004 | { | |
1005 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
3cdb7309 | 1006 | const struct xgene_mac_ops *mac_ops = pdata->mac_ops; |
e6ad7673 IS |
1007 | int ret; |
1008 | ||
107dec27 IS |
1009 | ret = netif_set_real_num_tx_queues(ndev, pdata->txq_cnt); |
1010 | if (ret) | |
1011 | return ret; | |
1012 | ||
1013 | ret = netif_set_real_num_rx_queues(ndev, pdata->rxq_cnt); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
aeb20b6b | 1017 | xgene_enet_napi_enable(pdata); |
e6ad7673 IS |
1018 | ret = xgene_enet_register_irq(ndev); |
1019 | if (ret) | |
1020 | return ret; | |
e6ad7673 | 1021 | |
971d3a44 PR |
1022 | if (ndev->phydev) { |
1023 | phy_start(ndev->phydev); | |
47c62b6d | 1024 | } else { |
0148d38d | 1025 | schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF); |
9a8c5dde IS |
1026 | netif_carrier_off(ndev); |
1027 | } | |
e6ad7673 | 1028 | |
cb11c062 IS |
1029 | mac_ops->tx_enable(pdata); |
1030 | mac_ops->rx_enable(pdata); | |
cb0366b7 | 1031 | netif_tx_start_all_queues(ndev); |
e6ad7673 IS |
1032 | |
1033 | return ret; | |
1034 | } | |
1035 | ||
1036 | static int xgene_enet_close(struct net_device *ndev) | |
1037 | { | |
1038 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
3cdb7309 | 1039 | const struct xgene_mac_ops *mac_ops = pdata->mac_ops; |
107dec27 | 1040 | int i; |
e6ad7673 | 1041 | |
cb0366b7 | 1042 | netif_tx_stop_all_queues(ndev); |
cb11c062 IS |
1043 | mac_ops->tx_disable(pdata); |
1044 | mac_ops->rx_disable(pdata); | |
e6ad7673 | 1045 | |
971d3a44 PR |
1046 | if (ndev->phydev) |
1047 | phy_stop(ndev->phydev); | |
0148d38d IS |
1048 | else |
1049 | cancel_delayed_work_sync(&pdata->link_work); | |
e6ad7673 | 1050 | |
aeb20b6b IS |
1051 | xgene_enet_free_irq(ndev); |
1052 | xgene_enet_napi_disable(pdata); | |
107dec27 IS |
1053 | for (i = 0; i < pdata->rxq_cnt; i++) |
1054 | xgene_enet_process_ring(pdata->rx_ring[i], -1); | |
aeb20b6b | 1055 | |
e6ad7673 IS |
1056 | return 0; |
1057 | } | |
e6ad7673 IS |
1058 | static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring) |
1059 | { | |
1060 | struct xgene_enet_pdata *pdata; | |
1061 | struct device *dev; | |
1062 | ||
1063 | pdata = netdev_priv(ring->ndev); | |
1064 | dev = ndev_to_dev(ring->ndev); | |
1065 | ||
81cefb81 | 1066 | pdata->ring_ops->clear(ring); |
cb0366b7 | 1067 | dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); |
e6ad7673 IS |
1068 | } |
1069 | ||
1070 | static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata) | |
1071 | { | |
a9380b0f | 1072 | struct xgene_enet_desc_ring *buf_pool, *page_pool; |
107dec27 IS |
1073 | struct xgene_enet_desc_ring *ring; |
1074 | int i; | |
e6ad7673 | 1075 | |
107dec27 IS |
1076 | for (i = 0; i < pdata->txq_cnt; i++) { |
1077 | ring = pdata->tx_ring[i]; | |
1078 | if (ring) { | |
1079 | xgene_enet_delete_ring(ring); | |
cb11c062 IS |
1080 | pdata->port_ops->clear(pdata, ring); |
1081 | if (pdata->cq_cnt) | |
1082 | xgene_enet_delete_ring(ring->cp_ring); | |
107dec27 IS |
1083 | pdata->tx_ring[i] = NULL; |
1084 | } | |
a9380b0f | 1085 | |
e6ad7673 IS |
1086 | } |
1087 | ||
107dec27 IS |
1088 | for (i = 0; i < pdata->rxq_cnt; i++) { |
1089 | ring = pdata->rx_ring[i]; | |
1090 | if (ring) { | |
a9380b0f IS |
1091 | page_pool = ring->page_pool; |
1092 | if (page_pool) { | |
1093 | xgene_enet_delete_pagepool(page_pool); | |
1094 | xgene_enet_delete_ring(page_pool); | |
1095 | pdata->port_ops->clear(pdata, page_pool); | |
1096 | } | |
1097 | ||
107dec27 IS |
1098 | buf_pool = ring->buf_pool; |
1099 | xgene_enet_delete_bufpool(buf_pool); | |
1100 | xgene_enet_delete_ring(buf_pool); | |
cb11c062 | 1101 | pdata->port_ops->clear(pdata, buf_pool); |
a9380b0f | 1102 | |
107dec27 IS |
1103 | xgene_enet_delete_ring(ring); |
1104 | pdata->rx_ring[i] = NULL; | |
1105 | } | |
a9380b0f | 1106 | |
e6ad7673 IS |
1107 | } |
1108 | } | |
1109 | ||
1110 | static int xgene_enet_get_ring_size(struct device *dev, | |
1111 | enum xgene_enet_ring_cfgsize cfgsize) | |
1112 | { | |
1113 | int size = -EINVAL; | |
1114 | ||
1115 | switch (cfgsize) { | |
1116 | case RING_CFGSIZE_512B: | |
1117 | size = 0x200; | |
1118 | break; | |
1119 | case RING_CFGSIZE_2KB: | |
1120 | size = 0x800; | |
1121 | break; | |
1122 | case RING_CFGSIZE_16KB: | |
1123 | size = 0x4000; | |
1124 | break; | |
1125 | case RING_CFGSIZE_64KB: | |
1126 | size = 0x10000; | |
1127 | break; | |
1128 | case RING_CFGSIZE_512KB: | |
1129 | size = 0x80000; | |
1130 | break; | |
1131 | default: | |
1132 | dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize); | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | return size; | |
1137 | } | |
1138 | ||
1139 | static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring) | |
1140 | { | |
81cefb81 | 1141 | struct xgene_enet_pdata *pdata; |
e6ad7673 IS |
1142 | struct device *dev; |
1143 | ||
1144 | if (!ring) | |
1145 | return; | |
1146 | ||
1147 | dev = ndev_to_dev(ring->ndev); | |
81cefb81 | 1148 | pdata = netdev_priv(ring->ndev); |
e6ad7673 IS |
1149 | |
1150 | if (ring->desc_addr) { | |
81cefb81 | 1151 | pdata->ring_ops->clear(ring); |
cb0366b7 | 1152 | dmam_free_coherent(dev, ring->size, ring->desc_addr, ring->dma); |
e6ad7673 IS |
1153 | } |
1154 | devm_kfree(dev, ring); | |
1155 | } | |
1156 | ||
1157 | static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata) | |
1158 | { | |
a9380b0f | 1159 | struct xgene_enet_desc_ring *page_pool; |
e6ad7673 IS |
1160 | struct device *dev = &pdata->pdev->dev; |
1161 | struct xgene_enet_desc_ring *ring; | |
a9380b0f | 1162 | void *p; |
107dec27 | 1163 | int i; |
e6ad7673 | 1164 | |
107dec27 IS |
1165 | for (i = 0; i < pdata->txq_cnt; i++) { |
1166 | ring = pdata->tx_ring[i]; | |
1167 | if (ring) { | |
1168 | if (ring->cp_ring && ring->cp_ring->cp_skb) | |
1169 | devm_kfree(dev, ring->cp_ring->cp_skb); | |
a9380b0f | 1170 | |
107dec27 IS |
1171 | if (ring->cp_ring && pdata->cq_cnt) |
1172 | xgene_enet_free_desc_ring(ring->cp_ring); | |
a9380b0f | 1173 | |
107dec27 IS |
1174 | xgene_enet_free_desc_ring(ring); |
1175 | } | |
a9380b0f | 1176 | |
107dec27 IS |
1177 | } |
1178 | ||
1179 | for (i = 0; i < pdata->rxq_cnt; i++) { | |
1180 | ring = pdata->rx_ring[i]; | |
1181 | if (ring) { | |
1182 | if (ring->buf_pool) { | |
1183 | if (ring->buf_pool->rx_skb) | |
1184 | devm_kfree(dev, ring->buf_pool->rx_skb); | |
a9380b0f | 1185 | |
107dec27 IS |
1186 | xgene_enet_free_desc_ring(ring->buf_pool); |
1187 | } | |
a9380b0f IS |
1188 | |
1189 | page_pool = ring->page_pool; | |
1190 | if (page_pool) { | |
1191 | p = page_pool->frag_page; | |
1192 | if (p) | |
1193 | devm_kfree(dev, p); | |
1194 | ||
1195 | p = page_pool->frag_dma_addr; | |
1196 | if (p) | |
1197 | devm_kfree(dev, p); | |
1198 | } | |
1199 | ||
107dec27 | 1200 | xgene_enet_free_desc_ring(ring); |
c10e4caf | 1201 | } |
c10e4caf | 1202 | } |
e6ad7673 IS |
1203 | } |
1204 | ||
bc1b7c13 IS |
1205 | static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata, |
1206 | struct xgene_enet_desc_ring *ring) | |
1207 | { | |
1208 | if ((pdata->enet_id == XGENE_ENET2) && | |
1209 | (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) { | |
1210 | return true; | |
1211 | } | |
1212 | ||
1213 | return false; | |
1214 | } | |
1215 | ||
1216 | static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata, | |
1217 | struct xgene_enet_desc_ring *ring) | |
1218 | { | |
1219 | u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift; | |
1220 | ||
1221 | return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift); | |
1222 | } | |
1223 | ||
e6ad7673 IS |
1224 | static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring( |
1225 | struct net_device *ndev, u32 ring_num, | |
1226 | enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id) | |
1227 | { | |
e6ad7673 IS |
1228 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); |
1229 | struct device *dev = ndev_to_dev(ndev); | |
cb0366b7 IS |
1230 | struct xgene_enet_desc_ring *ring; |
1231 | void *irq_mbox_addr; | |
9b9ba821 TK |
1232 | int size; |
1233 | ||
1234 | size = xgene_enet_get_ring_size(dev, cfgsize); | |
1235 | if (size < 0) | |
1236 | return NULL; | |
e6ad7673 IS |
1237 | |
1238 | ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring), | |
1239 | GFP_KERNEL); | |
1240 | if (!ring) | |
1241 | return NULL; | |
1242 | ||
1243 | ring->ndev = ndev; | |
1244 | ring->num = ring_num; | |
1245 | ring->cfgsize = cfgsize; | |
1246 | ring->id = ring_id; | |
1247 | ||
cb0366b7 IS |
1248 | ring->desc_addr = dmam_alloc_coherent(dev, size, &ring->dma, |
1249 | GFP_KERNEL | __GFP_ZERO); | |
e6ad7673 IS |
1250 | if (!ring->desc_addr) { |
1251 | devm_kfree(dev, ring); | |
1252 | return NULL; | |
1253 | } | |
1254 | ring->size = size; | |
1255 | ||
bc1b7c13 | 1256 | if (is_irq_mbox_required(pdata, ring)) { |
cb0366b7 IS |
1257 | irq_mbox_addr = dmam_alloc_coherent(dev, INTR_MBOX_SIZE, |
1258 | &ring->irq_mbox_dma, | |
1259 | GFP_KERNEL | __GFP_ZERO); | |
1260 | if (!irq_mbox_addr) { | |
1261 | dmam_free_coherent(dev, size, ring->desc_addr, | |
1262 | ring->dma); | |
bc1b7c13 IS |
1263 | devm_kfree(dev, ring); |
1264 | return NULL; | |
1265 | } | |
cb0366b7 | 1266 | ring->irq_mbox_addr = irq_mbox_addr; |
bc1b7c13 IS |
1267 | } |
1268 | ||
1269 | ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring); | |
e6ad7673 | 1270 | ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR; |
81cefb81 | 1271 | ring = pdata->ring_ops->setup(ring); |
e6ad7673 IS |
1272 | netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n", |
1273 | ring->num, ring->size, ring->id, ring->slots); | |
1274 | ||
1275 | return ring; | |
1276 | } | |
1277 | ||
1278 | static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum) | |
1279 | { | |
1280 | return (owner << 6) | (bufnum & GENMASK(5, 0)); | |
1281 | } | |
1282 | ||
bc1b7c13 IS |
1283 | static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p) |
1284 | { | |
1285 | enum xgene_ring_owner owner; | |
1286 | ||
1287 | if (p->enet_id == XGENE_ENET1) { | |
1288 | switch (p->phy_mode) { | |
1289 | case PHY_INTERFACE_MODE_SGMII: | |
1290 | owner = RING_OWNER_ETH0; | |
1291 | break; | |
1292 | default: | |
1293 | owner = (!p->port_id) ? RING_OWNER_ETH0 : | |
1294 | RING_OWNER_ETH1; | |
1295 | break; | |
1296 | } | |
1297 | } else { | |
1298 | owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1; | |
1299 | } | |
1300 | ||
1301 | return owner; | |
1302 | } | |
1303 | ||
2a37daa6 IS |
1304 | static u8 xgene_start_cpu_bufnum(struct xgene_enet_pdata *pdata) |
1305 | { | |
1306 | struct device *dev = &pdata->pdev->dev; | |
1307 | u32 cpu_bufnum; | |
1308 | int ret; | |
1309 | ||
1310 | ret = device_property_read_u32(dev, "channel", &cpu_bufnum); | |
1311 | ||
1312 | return (!ret) ? cpu_bufnum : pdata->cpu_bufnum; | |
1313 | } | |
1314 | ||
e6ad7673 IS |
1315 | static int xgene_enet_create_desc_rings(struct net_device *ndev) |
1316 | { | |
e6ad7673 | 1317 | struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring; |
a9380b0f IS |
1318 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); |
1319 | struct xgene_enet_desc_ring *page_pool = NULL; | |
e6ad7673 | 1320 | struct xgene_enet_desc_ring *buf_pool = NULL; |
a9380b0f | 1321 | struct device *dev = ndev_to_dev(ndev); |
ca626454 KC |
1322 | u8 eth_bufnum = pdata->eth_bufnum; |
1323 | u8 bp_bufnum = pdata->bp_bufnum; | |
1324 | u16 ring_num = pdata->ring_num; | |
a9380b0f IS |
1325 | enum xgene_ring_owner owner; |
1326 | dma_addr_t dma_exp_bufs; | |
1327 | u16 ring_id, slots; | |
cb0366b7 | 1328 | __le64 *exp_bufs; |
107dec27 | 1329 | int i, ret, size; |
a9380b0f | 1330 | u8 cpu_bufnum; |
e6ad7673 | 1331 | |
2a37daa6 IS |
1332 | cpu_bufnum = xgene_start_cpu_bufnum(pdata); |
1333 | ||
107dec27 IS |
1334 | for (i = 0; i < pdata->rxq_cnt; i++) { |
1335 | /* allocate rx descriptor ring */ | |
1336 | owner = xgene_derive_ring_owner(pdata); | |
1337 | ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++); | |
1338 | rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, | |
1339 | RING_CFGSIZE_16KB, | |
1340 | ring_id); | |
1341 | if (!rx_ring) { | |
1342 | ret = -ENOMEM; | |
1343 | goto err; | |
1344 | } | |
e6ad7673 | 1345 | |
107dec27 IS |
1346 | /* allocate buffer pool for receiving packets */ |
1347 | owner = xgene_derive_ring_owner(pdata); | |
1348 | ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); | |
1349 | buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++, | |
a9380b0f | 1350 | RING_CFGSIZE_16KB, |
107dec27 IS |
1351 | ring_id); |
1352 | if (!buf_pool) { | |
1353 | ret = -ENOMEM; | |
1354 | goto err; | |
1355 | } | |
9b00eb49 | 1356 | |
107dec27 | 1357 | rx_ring->nbufpool = NUM_BUFPOOL; |
a9380b0f | 1358 | rx_ring->npagepool = NUM_NXTBUFPOOL; |
107dec27 | 1359 | rx_ring->irq = pdata->irqs[i]; |
107dec27 IS |
1360 | buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots, |
1361 | sizeof(struct sk_buff *), | |
9b00eb49 | 1362 | GFP_KERNEL); |
107dec27 IS |
1363 | if (!buf_pool->rx_skb) { |
1364 | ret = -ENOMEM; | |
1365 | goto err; | |
1366 | } | |
9b00eb49 | 1367 | |
107dec27 IS |
1368 | buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool); |
1369 | rx_ring->buf_pool = buf_pool; | |
1370 | pdata->rx_ring[i] = rx_ring; | |
a9380b0f IS |
1371 | |
1372 | if ((pdata->enet_id == XGENE_ENET1 && pdata->rxq_cnt > 4) || | |
1373 | (pdata->enet_id == XGENE_ENET2 && pdata->rxq_cnt > 16)) { | |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | /* allocate next buffer pool for jumbo packets */ | |
1378 | owner = xgene_derive_ring_owner(pdata); | |
1379 | ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++); | |
1380 | page_pool = xgene_enet_create_desc_ring(ndev, ring_num++, | |
1381 | RING_CFGSIZE_16KB, | |
1382 | ring_id); | |
1383 | if (!page_pool) { | |
1384 | ret = -ENOMEM; | |
1385 | goto err; | |
1386 | } | |
1387 | ||
1388 | slots = page_pool->slots; | |
1389 | page_pool->frag_page = devm_kcalloc(dev, slots, | |
1390 | sizeof(struct page *), | |
1391 | GFP_KERNEL); | |
1392 | if (!page_pool->frag_page) { | |
1393 | ret = -ENOMEM; | |
1394 | goto err; | |
1395 | } | |
1396 | ||
1397 | page_pool->frag_dma_addr = devm_kcalloc(dev, slots, | |
1398 | sizeof(dma_addr_t), | |
1399 | GFP_KERNEL); | |
1400 | if (!page_pool->frag_dma_addr) { | |
1401 | ret = -ENOMEM; | |
1402 | goto err; | |
1403 | } | |
1404 | ||
1405 | page_pool->dst_ring_num = xgene_enet_dst_ring_num(page_pool); | |
1406 | rx_ring->page_pool = page_pool; | |
107dec27 | 1407 | } |
e6ad7673 | 1408 | |
107dec27 IS |
1409 | for (i = 0; i < pdata->txq_cnt; i++) { |
1410 | /* allocate tx descriptor ring */ | |
1411 | owner = xgene_derive_ring_owner(pdata); | |
1412 | ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++); | |
1413 | tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++, | |
6772b653 IS |
1414 | RING_CFGSIZE_16KB, |
1415 | ring_id); | |
107dec27 | 1416 | if (!tx_ring) { |
6772b653 IS |
1417 | ret = -ENOMEM; |
1418 | goto err; | |
1419 | } | |
6772b653 | 1420 | |
107dec27 | 1421 | size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS; |
cb0366b7 IS |
1422 | exp_bufs = dmam_alloc_coherent(dev, size, &dma_exp_bufs, |
1423 | GFP_KERNEL | __GFP_ZERO); | |
1424 | if (!exp_bufs) { | |
107dec27 IS |
1425 | ret = -ENOMEM; |
1426 | goto err; | |
1427 | } | |
cb0366b7 | 1428 | tx_ring->exp_bufs = exp_bufs; |
9b00eb49 | 1429 | |
107dec27 IS |
1430 | pdata->tx_ring[i] = tx_ring; |
1431 | ||
1432 | if (!pdata->cq_cnt) { | |
1433 | cp_ring = pdata->rx_ring[i]; | |
1434 | } else { | |
1435 | /* allocate tx completion descriptor ring */ | |
1436 | ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, | |
1437 | cpu_bufnum++); | |
1438 | cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++, | |
1439 | RING_CFGSIZE_16KB, | |
1440 | ring_id); | |
1441 | if (!cp_ring) { | |
1442 | ret = -ENOMEM; | |
1443 | goto err; | |
1444 | } | |
9b00eb49 | 1445 | |
107dec27 IS |
1446 | cp_ring->irq = pdata->irqs[pdata->rxq_cnt + i]; |
1447 | cp_ring->index = i; | |
107dec27 IS |
1448 | } |
1449 | ||
1450 | cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots, | |
1451 | sizeof(struct sk_buff *), | |
1452 | GFP_KERNEL); | |
1453 | if (!cp_ring->cp_skb) { | |
1454 | ret = -ENOMEM; | |
1455 | goto err; | |
1456 | } | |
e6ad7673 | 1457 | |
107dec27 IS |
1458 | size = sizeof(dma_addr_t) * MAX_SKB_FRAGS; |
1459 | cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots, | |
1460 | size, GFP_KERNEL); | |
1461 | if (!cp_ring->frag_dma_addr) { | |
1462 | devm_kfree(dev, cp_ring->cp_skb); | |
1463 | ret = -ENOMEM; | |
1464 | goto err; | |
1465 | } | |
1466 | ||
1467 | tx_ring->cp_ring = cp_ring; | |
1468 | tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring); | |
1469 | } | |
1470 | ||
b5a4a3eb IS |
1471 | if (pdata->ring_ops->coalesce) |
1472 | pdata->ring_ops->coalesce(pdata->tx_ring[0]); | |
107dec27 | 1473 | pdata->tx_qcnt_hi = pdata->tx_ring[0]->slots - 128; |
e6ad7673 IS |
1474 | |
1475 | return 0; | |
1476 | ||
1477 | err: | |
1478 | xgene_enet_free_desc_rings(pdata); | |
1479 | return ret; | |
1480 | } | |
1481 | ||
bc1f4470 | 1482 | static void xgene_enet_get_stats64( |
e6ad7673 | 1483 | struct net_device *ndev, |
3f5a2ef1 | 1484 | struct rtnl_link_stats64 *stats) |
e6ad7673 IS |
1485 | { |
1486 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
3bb502f8 IS |
1487 | struct xgene_enet_desc_ring *ring; |
1488 | int i; | |
e6ad7673 | 1489 | |
3bb502f8 IS |
1490 | for (i = 0; i < pdata->txq_cnt; i++) { |
1491 | ring = pdata->tx_ring[i]; | |
1492 | if (ring) { | |
1493 | stats->tx_packets += ring->tx_packets; | |
1494 | stats->tx_bytes += ring->tx_bytes; | |
089f97c7 QN |
1495 | stats->tx_dropped += ring->tx_dropped; |
1496 | stats->tx_errors += ring->tx_errors; | |
3bb502f8 IS |
1497 | } |
1498 | } | |
e6ad7673 | 1499 | |
3bb502f8 IS |
1500 | for (i = 0; i < pdata->rxq_cnt; i++) { |
1501 | ring = pdata->rx_ring[i]; | |
1502 | if (ring) { | |
1503 | stats->rx_packets += ring->rx_packets; | |
1504 | stats->rx_bytes += ring->rx_bytes; | |
089f97c7 QN |
1505 | stats->rx_dropped += ring->rx_dropped; |
1506 | stats->rx_errors += ring->rx_errors + | |
1507 | ring->rx_length_errors + | |
3bb502f8 IS |
1508 | ring->rx_crc_errors + |
1509 | ring->rx_frame_errors + | |
1510 | ring->rx_fifo_errors; | |
089f97c7 QN |
1511 | stats->rx_length_errors += ring->rx_length_errors; |
1512 | stats->rx_crc_errors += ring->rx_crc_errors; | |
1513 | stats->rx_frame_errors += ring->rx_frame_errors; | |
1514 | stats->rx_fifo_errors += ring->rx_fifo_errors; | |
3bb502f8 IS |
1515 | } |
1516 | } | |
e6ad7673 IS |
1517 | } |
1518 | ||
1519 | static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr) | |
1520 | { | |
1521 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
1522 | int ret; | |
1523 | ||
1524 | ret = eth_mac_addr(ndev, addr); | |
1525 | if (ret) | |
1526 | return ret; | |
d0eb7458 | 1527 | pdata->mac_ops->set_mac_addr(pdata); |
e6ad7673 IS |
1528 | |
1529 | return ret; | |
1530 | } | |
1531 | ||
350b4e33 IS |
1532 | static int xgene_change_mtu(struct net_device *ndev, int new_mtu) |
1533 | { | |
1534 | struct xgene_enet_pdata *pdata = netdev_priv(ndev); | |
1535 | int frame_size; | |
1536 | ||
1537 | if (!netif_running(ndev)) | |
1538 | return 0; | |
1539 | ||
1540 | frame_size = (new_mtu > ETH_DATA_LEN) ? (new_mtu + 18) : 0x600; | |
1541 | ||
1542 | xgene_enet_close(ndev); | |
1543 | ndev->mtu = new_mtu; | |
1544 | pdata->mac_ops->set_framesize(pdata, frame_size); | |
1545 | xgene_enet_open(ndev); | |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
e6ad7673 IS |
1550 | static const struct net_device_ops xgene_ndev_ops = { |
1551 | .ndo_open = xgene_enet_open, | |
1552 | .ndo_stop = xgene_enet_close, | |
1553 | .ndo_start_xmit = xgene_enet_start_xmit, | |
1554 | .ndo_tx_timeout = xgene_enet_timeout, | |
1555 | .ndo_get_stats64 = xgene_enet_get_stats64, | |
350b4e33 | 1556 | .ndo_change_mtu = xgene_change_mtu, |
e6ad7673 IS |
1557 | .ndo_set_mac_address = xgene_enet_set_mac_address, |
1558 | }; | |
1559 | ||
8beeef8d | 1560 | #ifdef CONFIG_ACPI |
724fe695 | 1561 | static void xgene_get_port_id_acpi(struct device *dev, |
0738c54d ST |
1562 | struct xgene_enet_pdata *pdata) |
1563 | { | |
1564 | acpi_status status; | |
1565 | u64 temp; | |
1566 | ||
1567 | status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp); | |
1568 | if (ACPI_FAILURE(status)) { | |
1569 | pdata->port_id = 0; | |
1570 | } else { | |
1571 | pdata->port_id = temp; | |
1572 | } | |
1573 | ||
724fe695 | 1574 | return; |
0738c54d | 1575 | } |
8beeef8d | 1576 | #endif |
0738c54d | 1577 | |
724fe695 | 1578 | static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata) |
ca626454 KC |
1579 | { |
1580 | u32 id = 0; | |
ca626454 | 1581 | |
724fe695 | 1582 | of_property_read_u32(dev->of_node, "port-id", &id); |
ca626454 | 1583 | |
724fe695 SS |
1584 | pdata->port_id = id & BIT(0); |
1585 | ||
1586 | return; | |
ca626454 KC |
1587 | } |
1588 | ||
16615a4c IS |
1589 | static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) |
1590 | { | |
1591 | struct device *dev = &pdata->pdev->dev; | |
1592 | int delay, ret; | |
1593 | ||
1594 | ret = of_property_read_u32(dev->of_node, "tx-delay", &delay); | |
1595 | if (ret) { | |
1596 | pdata->tx_delay = 4; | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | if (delay < 0 || delay > 7) { | |
1601 | dev_err(dev, "Invalid tx-delay specified\n"); | |
1602 | return -EINVAL; | |
1603 | } | |
1604 | ||
1605 | pdata->tx_delay = delay; | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata) | |
1611 | { | |
1612 | struct device *dev = &pdata->pdev->dev; | |
1613 | int delay, ret; | |
1614 | ||
1615 | ret = of_property_read_u32(dev->of_node, "rx-delay", &delay); | |
1616 | if (ret) { | |
1617 | pdata->rx_delay = 2; | |
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | if (delay < 0 || delay > 7) { | |
1622 | dev_err(dev, "Invalid rx-delay specified\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | ||
1626 | pdata->rx_delay = delay; | |
1627 | ||
1628 | return 0; | |
1629 | } | |
de7b5b3d | 1630 | |
107dec27 IS |
1631 | static int xgene_enet_get_irqs(struct xgene_enet_pdata *pdata) |
1632 | { | |
1633 | struct platform_device *pdev = pdata->pdev; | |
1634 | struct device *dev = &pdev->dev; | |
1635 | int i, ret, max_irqs; | |
1636 | ||
326dde3e | 1637 | if (phy_interface_mode_is_rgmii(pdata->phy_mode)) |
107dec27 IS |
1638 | max_irqs = 1; |
1639 | else if (pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) | |
1640 | max_irqs = 2; | |
1641 | else | |
1642 | max_irqs = XGENE_MAX_ENET_IRQ; | |
1643 | ||
1644 | for (i = 0; i < max_irqs; i++) { | |
1645 | ret = platform_get_irq(pdev, i); | |
1646 | if (ret <= 0) { | |
1b090a48 IS |
1647 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { |
1648 | max_irqs = i; | |
1649 | pdata->rxq_cnt = max_irqs / 2; | |
1650 | pdata->txq_cnt = max_irqs / 2; | |
1651 | pdata->cq_cnt = max_irqs / 2; | |
1652 | break; | |
1653 | } | |
107dec27 IS |
1654 | dev_err(dev, "Unable to get ENET IRQ\n"); |
1655 | ret = ret ? : -ENXIO; | |
1656 | return ret; | |
1657 | } | |
1658 | pdata->irqs[i] = ret; | |
1659 | } | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
183db481 | 1664 | static void xgene_enet_check_phy_handle(struct xgene_enet_pdata *pdata) |
8089a96f IS |
1665 | { |
1666 | int ret; | |
1667 | ||
1668 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) | |
183db481 | 1669 | return; |
8089a96f IS |
1670 | |
1671 | if (!IS_ENABLED(CONFIG_MDIO_XGENE)) | |
183db481 | 1672 | return; |
8089a96f IS |
1673 | |
1674 | ret = xgene_enet_phy_connect(pdata->ndev); | |
1675 | if (!ret) | |
1676 | pdata->mdio_driver = true; | |
1677 | ||
183db481 | 1678 | return; |
8089a96f IS |
1679 | } |
1680 | ||
27ecf87c IS |
1681 | static void xgene_enet_gpiod_get(struct xgene_enet_pdata *pdata) |
1682 | { | |
1683 | struct device *dev = &pdata->pdev->dev; | |
1684 | ||
751d6fd1 IS |
1685 | pdata->sfp_gpio_en = false; |
1686 | if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII || | |
1687 | (!device_property_present(dev, "sfp-gpios") && | |
1688 | !device_property_present(dev, "rxlos-gpios"))) | |
27ecf87c IS |
1689 | return; |
1690 | ||
751d6fd1 | 1691 | pdata->sfp_gpio_en = true; |
27ecf87c IS |
1692 | pdata->sfp_rdy = gpiod_get(dev, "rxlos", GPIOD_IN); |
1693 | if (IS_ERR(pdata->sfp_rdy)) | |
1694 | pdata->sfp_rdy = gpiod_get(dev, "sfp", GPIOD_IN); | |
1695 | } | |
1696 | ||
e6ad7673 IS |
1697 | static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) |
1698 | { | |
1699 | struct platform_device *pdev; | |
1700 | struct net_device *ndev; | |
1701 | struct device *dev; | |
1702 | struct resource *res; | |
1703 | void __iomem *base_addr; | |
561fea6d | 1704 | u32 offset; |
2e598712 | 1705 | int ret = 0; |
e6ad7673 IS |
1706 | |
1707 | pdev = pdata->pdev; | |
1708 | dev = &pdev->dev; | |
1709 | ndev = pdata->ndev; | |
1710 | ||
de7b5b3d FK |
1711 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR); |
1712 | if (!res) { | |
1713 | dev_err(dev, "Resource enet_csr not defined\n"); | |
1714 | return -ENODEV; | |
1715 | } | |
1716 | pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res)); | |
3ec7a176 | 1717 | if (!pdata->base_addr) { |
e6ad7673 | 1718 | dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); |
3ec7a176 | 1719 | return -ENOMEM; |
e6ad7673 IS |
1720 | } |
1721 | ||
de7b5b3d FK |
1722 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR); |
1723 | if (!res) { | |
1724 | dev_err(dev, "Resource ring_csr not defined\n"); | |
1725 | return -ENODEV; | |
1726 | } | |
1727 | pdata->ring_csr_addr = devm_ioremap(dev, res->start, | |
1728 | resource_size(res)); | |
3ec7a176 | 1729 | if (!pdata->ring_csr_addr) { |
e6ad7673 | 1730 | dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); |
3ec7a176 | 1731 | return -ENOMEM; |
e6ad7673 IS |
1732 | } |
1733 | ||
de7b5b3d FK |
1734 | res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD); |
1735 | if (!res) { | |
1736 | dev_err(dev, "Resource ring_cmd not defined\n"); | |
1737 | return -ENODEV; | |
1738 | } | |
1739 | pdata->ring_cmd_addr = devm_ioremap(dev, res->start, | |
1740 | resource_size(res)); | |
3ec7a176 | 1741 | if (!pdata->ring_cmd_addr) { |
e6ad7673 | 1742 | dev_err(dev, "Unable to retrieve ENET Ring command region\n"); |
3ec7a176 | 1743 | return -ENOMEM; |
e6ad7673 IS |
1744 | } |
1745 | ||
0738c54d | 1746 | if (dev->of_node) |
724fe695 | 1747 | xgene_get_port_id_dt(dev, pdata); |
0738c54d ST |
1748 | #ifdef CONFIG_ACPI |
1749 | else | |
724fe695 | 1750 | xgene_get_port_id_acpi(dev, pdata); |
0738c54d | 1751 | #endif |
ca626454 | 1752 | |
938049e1 | 1753 | if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN)) |
e6ad7673 | 1754 | eth_hw_addr_random(ndev); |
de7b5b3d | 1755 | |
e6ad7673 IS |
1756 | memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); |
1757 | ||
938049e1 | 1758 | pdata->phy_mode = device_get_phy_mode(dev); |
e6ad7673 | 1759 | if (pdata->phy_mode < 0) { |
0148d38d IS |
1760 | dev_err(dev, "Unable to get phy-connection-type\n"); |
1761 | return pdata->phy_mode; | |
1762 | } | |
326dde3e | 1763 | if (!phy_interface_mode_is_rgmii(pdata->phy_mode) && |
32f784b5 | 1764 | pdata->phy_mode != PHY_INTERFACE_MODE_SGMII && |
0148d38d IS |
1765 | pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) { |
1766 | dev_err(dev, "Incorrect phy-connection-type specified\n"); | |
1767 | return -ENODEV; | |
e6ad7673 IS |
1768 | } |
1769 | ||
16615a4c IS |
1770 | ret = xgene_get_tx_delay(pdata); |
1771 | if (ret) | |
1772 | return ret; | |
1773 | ||
1774 | ret = xgene_get_rx_delay(pdata); | |
1775 | if (ret) | |
1776 | return ret; | |
1777 | ||
107dec27 IS |
1778 | ret = xgene_enet_get_irqs(pdata); |
1779 | if (ret) | |
6772b653 | 1780 | return ret; |
6772b653 | 1781 | |
27ecf87c IS |
1782 | xgene_enet_gpiod_get(pdata); |
1783 | ||
aaf83aec TB |
1784 | pdata->clk = devm_clk_get(&pdev->dev, NULL); |
1785 | if (IS_ERR(pdata->clk)) { | |
1786 | if (pdata->phy_mode != PHY_INTERFACE_MODE_SGMII) { | |
0db01097 TB |
1787 | /* Abort if the clock is defined but couldn't be |
1788 | * retrived. Always abort if the clock is missing on | |
1789 | * DT system as the driver can't cope with this case. | |
1790 | */ | |
1791 | if (PTR_ERR(pdata->clk) != -ENOENT || dev->of_node) | |
1792 | return PTR_ERR(pdata->clk); | |
1793 | /* Firmware may have set up the clock already. */ | |
1794 | dev_info(dev, "clocks have been setup already\n"); | |
1795 | } | |
e6ad7673 IS |
1796 | } |
1797 | ||
bc1b7c13 IS |
1798 | if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) |
1799 | base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET); | |
1800 | else | |
1801 | base_addr = pdata->base_addr; | |
e6ad7673 | 1802 | pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET; |
76f94a9c | 1803 | pdata->cle.base = base_addr + BLOCK_ETH_CLE_CSR_OFFSET; |
e6ad7673 IS |
1804 | pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET; |
1805 | pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET; | |
326dde3e | 1806 | if (phy_interface_mode_is_rgmii(pdata->phy_mode) || |
32f784b5 | 1807 | pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) { |
ca626454 | 1808 | pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET; |
2d07d8e4 QN |
1809 | pdata->mcx_stats_addr = |
1810 | pdata->base_addr + BLOCK_ETH_STATS_OFFSET; | |
561fea6d IS |
1811 | offset = (pdata->enet_id == XGENE_ENET1) ? |
1812 | BLOCK_ETH_MAC_CSR_OFFSET : | |
1813 | X2_BLOCK_ETH_MAC_CSR_OFFSET; | |
1814 | pdata->mcx_mac_csr_addr = base_addr + offset; | |
0148d38d IS |
1815 | } else { |
1816 | pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET; | |
2d07d8e4 | 1817 | pdata->mcx_stats_addr = base_addr + BLOCK_AXG_STATS_OFFSET; |
0148d38d | 1818 | pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET; |
3eb7cb9d | 1819 | pdata->pcs_addr = base_addr + BLOCK_PCS_OFFSET; |
0148d38d | 1820 | } |
e6ad7673 IS |
1821 | pdata->rx_buff_cnt = NUM_PKT_BUF; |
1822 | ||
0148d38d | 1823 | return 0; |
e6ad7673 IS |
1824 | } |
1825 | ||
1826 | static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata) | |
1827 | { | |
76f94a9c | 1828 | struct xgene_enet_cle *enet_cle = &pdata->cle; |
d6d48969 | 1829 | struct xgene_enet_desc_ring *page_pool; |
e6ad7673 IS |
1830 | struct net_device *ndev = pdata->ndev; |
1831 | struct xgene_enet_desc_ring *buf_pool; | |
d6d48969 | 1832 | u16 dst_ring_num, ring_id; |
107dec27 | 1833 | int i, ret; |
a9380b0f | 1834 | u32 count; |
e6ad7673 | 1835 | |
c3f4465d IS |
1836 | ret = pdata->port_ops->reset(pdata); |
1837 | if (ret) | |
1838 | return ret; | |
e6ad7673 IS |
1839 | |
1840 | ret = xgene_enet_create_desc_rings(ndev); | |
1841 | if (ret) { | |
1842 | netdev_err(ndev, "Error in ring configuration\n"); | |
1843 | return ret; | |
1844 | } | |
1845 | ||
1846 | /* setup buffer pool */ | |
107dec27 IS |
1847 | for (i = 0; i < pdata->rxq_cnt; i++) { |
1848 | buf_pool = pdata->rx_ring[i]->buf_pool; | |
1849 | xgene_enet_init_bufpool(buf_pool); | |
a9380b0f IS |
1850 | page_pool = pdata->rx_ring[i]->page_pool; |
1851 | xgene_enet_init_bufpool(page_pool); | |
1852 | ||
1853 | count = pdata->rx_buff_cnt; | |
1854 | ret = xgene_enet_refill_bufpool(buf_pool, count); | |
15e32296 IS |
1855 | if (ret) |
1856 | goto err; | |
a9380b0f IS |
1857 | |
1858 | ret = xgene_enet_refill_pagepool(page_pool, count); | |
1859 | if (ret) | |
1860 | goto err; | |
1861 | ||
e6ad7673 IS |
1862 | } |
1863 | ||
107dec27 IS |
1864 | dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); |
1865 | buf_pool = pdata->rx_ring[0]->buf_pool; | |
76f94a9c IS |
1866 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { |
1867 | /* Initialize and Enable PreClassifier Tree */ | |
1868 | enet_cle->max_nodes = 512; | |
1869 | enet_cle->max_dbptrs = 1024; | |
1870 | enet_cle->parsers = 3; | |
1871 | enet_cle->active_parser = PARSER_ALL; | |
1872 | enet_cle->ptree.start_node = 0; | |
1873 | enet_cle->ptree.start_dbptr = 0; | |
1874 | enet_cle->jump_bytes = 8; | |
1875 | ret = pdata->cle_ops->cle_init(pdata); | |
1876 | if (ret) { | |
1877 | netdev_err(ndev, "Preclass Tree init error\n"); | |
15e32296 | 1878 | goto err; |
76f94a9c | 1879 | } |
d6d48969 | 1880 | |
76f94a9c | 1881 | } else { |
d6d48969 IS |
1882 | dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring[0]); |
1883 | buf_pool = pdata->rx_ring[0]->buf_pool; | |
1884 | page_pool = pdata->rx_ring[0]->page_pool; | |
1885 | ring_id = (page_pool) ? page_pool->id : 0; | |
1886 | pdata->port_ops->cle_bypass(pdata, dst_ring_num, | |
1887 | buf_pool->id, ring_id); | |
76f94a9c IS |
1888 | } |
1889 | ||
350b4e33 | 1890 | ndev->max_mtu = XGENE_ENET_MAX_MTU; |
9a8c5dde | 1891 | pdata->phy_speed = SPEED_UNKNOWN; |
0148d38d | 1892 | pdata->mac_ops->init(pdata); |
e6ad7673 IS |
1893 | |
1894 | return ret; | |
15e32296 IS |
1895 | |
1896 | err: | |
1897 | xgene_enet_delete_desc_rings(pdata); | |
1898 | return ret; | |
e6ad7673 IS |
1899 | } |
1900 | ||
d0eb7458 IS |
1901 | static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata) |
1902 | { | |
0148d38d IS |
1903 | switch (pdata->phy_mode) { |
1904 | case PHY_INTERFACE_MODE_RGMII: | |
326dde3e IS |
1905 | case PHY_INTERFACE_MODE_RGMII_ID: |
1906 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
1907 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
0148d38d IS |
1908 | pdata->mac_ops = &xgene_gmac_ops; |
1909 | pdata->port_ops = &xgene_gport_ops; | |
dc8385f0 | 1910 | pdata->rm = RM3; |
107dec27 IS |
1911 | pdata->rxq_cnt = 1; |
1912 | pdata->txq_cnt = 1; | |
1913 | pdata->cq_cnt = 0; | |
0148d38d | 1914 | break; |
32f784b5 IS |
1915 | case PHY_INTERFACE_MODE_SGMII: |
1916 | pdata->mac_ops = &xgene_sgmac_ops; | |
1917 | pdata->port_ops = &xgene_sgport_ops; | |
1918 | pdata->rm = RM1; | |
107dec27 IS |
1919 | pdata->rxq_cnt = 1; |
1920 | pdata->txq_cnt = 1; | |
1921 | pdata->cq_cnt = 1; | |
32f784b5 | 1922 | break; |
0148d38d IS |
1923 | default: |
1924 | pdata->mac_ops = &xgene_xgmac_ops; | |
1925 | pdata->port_ops = &xgene_xgport_ops; | |
76f94a9c | 1926 | pdata->cle_ops = &xgene_cle3in_ops; |
dc8385f0 | 1927 | pdata->rm = RM0; |
1b090a48 IS |
1928 | if (!pdata->rxq_cnt) { |
1929 | pdata->rxq_cnt = XGENE_NUM_RX_RING; | |
1930 | pdata->txq_cnt = XGENE_NUM_TX_RING; | |
1931 | pdata->cq_cnt = XGENE_NUM_TXC_RING; | |
1932 | } | |
0148d38d IS |
1933 | break; |
1934 | } | |
ca626454 | 1935 | |
bc1b7c13 IS |
1936 | if (pdata->enet_id == XGENE_ENET1) { |
1937 | switch (pdata->port_id) { | |
1938 | case 0: | |
1b090a48 IS |
1939 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { |
1940 | pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; | |
1941 | pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; | |
1942 | pdata->bp_bufnum = X2_START_BP_BUFNUM_0; | |
1943 | pdata->ring_num = START_RING_NUM_0; | |
1944 | } else { | |
1945 | pdata->cpu_bufnum = START_CPU_BUFNUM_0; | |
1946 | pdata->eth_bufnum = START_ETH_BUFNUM_0; | |
1947 | pdata->bp_bufnum = START_BP_BUFNUM_0; | |
1948 | pdata->ring_num = START_RING_NUM_0; | |
1949 | } | |
bc1b7c13 IS |
1950 | break; |
1951 | case 1: | |
149e9ab4 IS |
1952 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { |
1953 | pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1; | |
1954 | pdata->eth_bufnum = XG_START_ETH_BUFNUM_1; | |
1955 | pdata->bp_bufnum = XG_START_BP_BUFNUM_1; | |
1956 | pdata->ring_num = XG_START_RING_NUM_1; | |
1957 | } else { | |
1958 | pdata->cpu_bufnum = START_CPU_BUFNUM_1; | |
1959 | pdata->eth_bufnum = START_ETH_BUFNUM_1; | |
1960 | pdata->bp_bufnum = START_BP_BUFNUM_1; | |
1961 | pdata->ring_num = START_RING_NUM_1; | |
1962 | } | |
bc1b7c13 IS |
1963 | break; |
1964 | default: | |
1965 | break; | |
1966 | } | |
1967 | pdata->ring_ops = &xgene_ring1_ops; | |
1968 | } else { | |
1969 | switch (pdata->port_id) { | |
1970 | case 0: | |
1971 | pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0; | |
1972 | pdata->eth_bufnum = X2_START_ETH_BUFNUM_0; | |
1973 | pdata->bp_bufnum = X2_START_BP_BUFNUM_0; | |
1974 | pdata->ring_num = X2_START_RING_NUM_0; | |
1975 | break; | |
1976 | case 1: | |
1977 | pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1; | |
1978 | pdata->eth_bufnum = X2_START_ETH_BUFNUM_1; | |
1979 | pdata->bp_bufnum = X2_START_BP_BUFNUM_1; | |
1980 | pdata->ring_num = X2_START_RING_NUM_1; | |
1981 | break; | |
1982 | default: | |
1983 | break; | |
1984 | } | |
1985 | pdata->rm = RM0; | |
1986 | pdata->ring_ops = &xgene_ring2_ops; | |
ca626454 | 1987 | } |
d0eb7458 IS |
1988 | } |
1989 | ||
6772b653 IS |
1990 | static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata) |
1991 | { | |
1992 | struct napi_struct *napi; | |
107dec27 | 1993 | int i; |
6772b653 | 1994 | |
107dec27 IS |
1995 | for (i = 0; i < pdata->rxq_cnt; i++) { |
1996 | napi = &pdata->rx_ring[i]->napi; | |
1997 | netif_napi_add(pdata->ndev, napi, xgene_enet_napi, | |
1998 | NAPI_POLL_WEIGHT); | |
1999 | } | |
6772b653 | 2000 | |
107dec27 IS |
2001 | for (i = 0; i < pdata->cq_cnt; i++) { |
2002 | napi = &pdata->tx_ring[i]->cp_ring->napi; | |
6772b653 IS |
2003 | netif_napi_add(pdata->ndev, napi, xgene_enet_napi, |
2004 | NAPI_POLL_WEIGHT); | |
2005 | } | |
2006 | } | |
2007 | ||
1f3d6209 AB |
2008 | #ifdef CONFIG_ACPI |
2009 | static const struct acpi_device_id xgene_enet_acpi_match[] = { | |
2010 | { "APMC0D05", XGENE_ENET1}, | |
2011 | { "APMC0D30", XGENE_ENET1}, | |
2012 | { "APMC0D31", XGENE_ENET1}, | |
2013 | { "APMC0D3F", XGENE_ENET1}, | |
2014 | { "APMC0D26", XGENE_ENET2}, | |
2015 | { "APMC0D25", XGENE_ENET2}, | |
2016 | { } | |
2017 | }; | |
2018 | MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match); | |
2019 | #endif | |
2020 | ||
2021 | static const struct of_device_id xgene_enet_of_match[] = { | |
2022 | {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1}, | |
2023 | {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1}, | |
2024 | {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1}, | |
2025 | {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2}, | |
2026 | {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2}, | |
2027 | {}, | |
2028 | }; | |
2029 | ||
2030 | MODULE_DEVICE_TABLE(of, xgene_enet_of_match); | |
2031 | ||
e6ad7673 IS |
2032 | static int xgene_enet_probe(struct platform_device *pdev) |
2033 | { | |
2034 | struct net_device *ndev; | |
2035 | struct xgene_enet_pdata *pdata; | |
2036 | struct device *dev = &pdev->dev; | |
8089a96f | 2037 | void (*link_state)(struct work_struct *); |
bc1b7c13 | 2038 | const struct of_device_id *of_id; |
e6ad7673 IS |
2039 | int ret; |
2040 | ||
107dec27 IS |
2041 | ndev = alloc_etherdev_mqs(sizeof(struct xgene_enet_pdata), |
2042 | XGENE_NUM_RX_RING, XGENE_NUM_TX_RING); | |
e6ad7673 IS |
2043 | if (!ndev) |
2044 | return -ENOMEM; | |
2045 | ||
2046 | pdata = netdev_priv(ndev); | |
2047 | ||
2048 | pdata->pdev = pdev; | |
2049 | pdata->ndev = ndev; | |
2050 | SET_NETDEV_DEV(ndev, dev); | |
2051 | platform_set_drvdata(pdev, pdata); | |
2052 | ndev->netdev_ops = &xgene_ndev_ops; | |
2053 | xgene_enet_set_ethtool_ops(ndev); | |
2054 | ndev->features |= NETIF_F_IP_CSUM | | |
2055 | NETIF_F_GSO | | |
9b00eb49 IS |
2056 | NETIF_F_GRO | |
2057 | NETIF_F_SG; | |
e6ad7673 | 2058 | |
bc1b7c13 IS |
2059 | of_id = of_match_device(xgene_enet_of_match, &pdev->dev); |
2060 | if (of_id) { | |
2061 | pdata->enet_id = (enum xgene_enet_id)of_id->data; | |
0738c54d ST |
2062 | } |
2063 | #ifdef CONFIG_ACPI | |
2064 | else { | |
2065 | const struct acpi_device_id *acpi_id; | |
2066 | ||
2067 | acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev); | |
2068 | if (acpi_id) | |
2069 | pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data; | |
bc1b7c13 IS |
2070 | } |
2071 | #endif | |
0738c54d | 2072 | if (!pdata->enet_id) { |
cecd6e51 IS |
2073 | ret = -ENODEV; |
2074 | goto err; | |
0738c54d | 2075 | } |
bc1b7c13 | 2076 | |
e6ad7673 IS |
2077 | ret = xgene_enet_get_resources(pdata); |
2078 | if (ret) | |
2079 | goto err; | |
2080 | ||
d0eb7458 | 2081 | xgene_enet_setup_ops(pdata); |
ae1aed95 | 2082 | spin_lock_init(&pdata->mac_lock); |
e6ad7673 | 2083 | |
9b00eb49 | 2084 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { |
0a0400c3 | 2085 | ndev->features |= NETIF_F_TSO | NETIF_F_RXCSUM; |
e3978673 | 2086 | spin_lock_init(&pdata->mss_lock); |
9b00eb49 IS |
2087 | } |
2088 | ndev->hw_features = ndev->features; | |
2089 | ||
aeb20b6b | 2090 | ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
e6ad7673 | 2091 | if (ret) { |
aeb20b6b | 2092 | netdev_err(ndev, "No usable DMA configuration\n"); |
e6ad7673 IS |
2093 | goto err; |
2094 | } | |
2095 | ||
183db481 QN |
2096 | xgene_enet_check_phy_handle(pdata); |
2097 | ||
e6ad7673 IS |
2098 | ret = xgene_enet_init_hw(pdata); |
2099 | if (ret) | |
183db481 | 2100 | goto err2; |
e6ad7673 | 2101 | |
8089a96f IS |
2102 | link_state = pdata->mac_ops->link_state; |
2103 | if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) { | |
2104 | INIT_DELAYED_WORK(&pdata->link_work, link_state); | |
2105 | } else if (!pdata->mdio_driver) { | |
326dde3e | 2106 | if (phy_interface_mode_is_rgmii(pdata->phy_mode)) |
8089a96f IS |
2107 | ret = xgene_enet_mdio_config(pdata); |
2108 | else | |
2109 | INIT_DELAYED_WORK(&pdata->link_work, link_state); | |
cecd6e51 IS |
2110 | |
2111 | if (ret) | |
2112 | goto err1; | |
aeb20b6b | 2113 | } |
e6ad7673 | 2114 | |
2d07d8e4 QN |
2115 | spin_lock_init(&pdata->stats_lock); |
2116 | ret = xgene_extd_stats_init(pdata); | |
2117 | if (ret) | |
183db481 | 2118 | goto err1; |
2d07d8e4 | 2119 | |
aeb20b6b | 2120 | xgene_enet_napi_add(pdata); |
cb0366b7 IS |
2121 | ret = register_netdev(ndev); |
2122 | if (ret) { | |
2123 | netdev_err(ndev, "Failed to register netdev\n"); | |
183db481 | 2124 | goto err1; |
cb0366b7 IS |
2125 | } |
2126 | ||
aeb20b6b | 2127 | return 0; |
cb0366b7 | 2128 | |
183db481 | 2129 | err1: |
cecd6e51 IS |
2130 | /* |
2131 | * If necessary, free_netdev() will call netif_napi_del() and undo | |
2132 | * the effects of xgene_enet_napi_add()'s calls to netif_napi_add(). | |
2133 | */ | |
2134 | ||
183db481 QN |
2135 | xgene_enet_delete_desc_rings(pdata); |
2136 | ||
2137 | err2: | |
cecd6e51 IS |
2138 | if (pdata->mdio_driver) |
2139 | xgene_enet_phy_disconnect(pdata); | |
326dde3e | 2140 | else if (phy_interface_mode_is_rgmii(pdata->phy_mode)) |
cecd6e51 | 2141 | xgene_enet_mdio_remove(pdata); |
20decb7e | 2142 | err: |
e6ad7673 IS |
2143 | free_netdev(ndev); |
2144 | return ret; | |
2145 | } | |
2146 | ||
2147 | static int xgene_enet_remove(struct platform_device *pdev) | |
2148 | { | |
2149 | struct xgene_enet_pdata *pdata; | |
2150 | struct net_device *ndev; | |
2151 | ||
2152 | pdata = platform_get_drvdata(pdev); | |
2153 | ndev = pdata->ndev; | |
2154 | ||
cb0366b7 IS |
2155 | rtnl_lock(); |
2156 | if (netif_running(ndev)) | |
2157 | dev_close(ndev); | |
2158 | rtnl_unlock(); | |
2159 | ||
8089a96f IS |
2160 | if (pdata->mdio_driver) |
2161 | xgene_enet_phy_disconnect(pdata); | |
326dde3e | 2162 | else if (phy_interface_mode_is_rgmii(pdata->phy_mode)) |
ccc02ddb | 2163 | xgene_enet_mdio_remove(pdata); |
8089a96f | 2164 | |
e6ad7673 | 2165 | unregister_netdev(ndev); |
cb11c062 | 2166 | xgene_enet_delete_desc_rings(pdata); |
8aba8474 | 2167 | pdata->port_ops->shutdown(pdata); |
e6ad7673 IS |
2168 | free_netdev(ndev); |
2169 | ||
2170 | return 0; | |
2171 | } | |
2172 | ||
cb0366b7 IS |
2173 | static void xgene_enet_shutdown(struct platform_device *pdev) |
2174 | { | |
2175 | struct xgene_enet_pdata *pdata; | |
2176 | ||
2177 | pdata = platform_get_drvdata(pdev); | |
2178 | if (!pdata) | |
2179 | return; | |
2180 | ||
2181 | if (!pdata->ndev) | |
2182 | return; | |
2183 | ||
2184 | xgene_enet_remove(pdev); | |
2185 | } | |
2186 | ||
e6ad7673 IS |
2187 | static struct platform_driver xgene_enet_driver = { |
2188 | .driver = { | |
2189 | .name = "xgene-enet", | |
de7b5b3d FK |
2190 | .of_match_table = of_match_ptr(xgene_enet_of_match), |
2191 | .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match), | |
e6ad7673 IS |
2192 | }, |
2193 | .probe = xgene_enet_probe, | |
2194 | .remove = xgene_enet_remove, | |
cb0366b7 | 2195 | .shutdown = xgene_enet_shutdown, |
e6ad7673 IS |
2196 | }; |
2197 | ||
2198 | module_platform_driver(xgene_enet_driver); | |
2199 | ||
2200 | MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver"); | |
2201 | MODULE_VERSION(XGENE_DRV_VERSION); | |
d0eb7458 | 2202 | MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>"); |
e6ad7673 IS |
2203 | MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>"); |
2204 | MODULE_LICENSE("GPL"); |