[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / apm / xgene / xgene_enet_sgmac.c

/* Applied Micro X-Gene SoC Ethernet Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Authors: Iyappan Subramanian <isubramanian@apm.com>
 *	    Keyur Chudgar <kchudgar@apm.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "xgene_enet_main.h"
#include "xgene_enet_hw.h"
#include "xgene_enet_sgmac.h"
#include "xgene_enet_xgmac.h"

static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
{
	iowrite32(val, p->eth_csr_addr + offset);
}

static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset,
				     u32 val)
{
	iowrite32(val, p->base_addr + offset);
}

static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
				  u32 offset, u32 val)
{
	iowrite32(val, p->eth_ring_if_addr + offset);
}

static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p,
				   u32 offset, u32 val)
{
	iowrite32(val, p->eth_diag_csr_addr + offset);
}

static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
				  u32 offset, u32 val)
{
	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;

	iowrite32(val, addr);
}

static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl,
				   u32 wr_addr, u32 wr_data)
{
	int i;

	iowrite32(wr_addr, ctl->addr);
	iowrite32(wr_data, ctl->ctl);
	iowrite32(XGENE_ENET_WR_CMD, ctl->cmd);

	/* wait for write command to complete */
	for (i = 0; i < 10; i++) {
		if (ioread32(ctl->cmd_done)) {
			iowrite32(0, ctl->cmd);
			return true;
		}
		udelay(1);
	}

	return false;
}

static void xgene_enet_wr_mac(struct xgene_enet_pdata *p,
			      u32 wr_addr, u32 wr_data)
{
	struct xgene_indirect_ctl ctl = {
		.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
		.ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET,
		.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
		.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
	};

	if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data))
		netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr);
}

static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset)
{
	return ioread32(p->eth_csr_addr + offset);
}

static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset)
{
	return ioread32(p->eth_diag_csr_addr + offset);
}

static u32 xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *p, u32 offset)
{
	return ioread32(p->mcx_mac_csr_addr + offset);
}

static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr)
{
	u32 rd_data;
	int i;

	iowrite32(rd_addr, ctl->addr);
	iowrite32(XGENE_ENET_RD_CMD, ctl->cmd);

	/* wait for read command to complete */
	for (i = 0; i < 10; i++) {
		if (ioread32(ctl->cmd_done)) {
			rd_data = ioread32(ctl->ctl);
			iowrite32(0, ctl->cmd);

			return rd_data;
		}
		udelay(1);
	}

	pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr);

	return 0;
}

static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr)
{
	struct xgene_indirect_ctl ctl = {
		.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
		.ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET,
		.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
		.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
	};

	return xgene_enet_rd_indirect(&ctl, rd_addr);
}

static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
{
	struct net_device *ndev = p->ndev;
	u32 data, shutdown;
	int i = 0;

	shutdown = xgene_enet_rd_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR);
	data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);

	if (!shutdown && data == ~0U) {
		netdev_dbg(ndev, "+ ecc_init done, skipping\n");
		return 0;
	}

	xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0);
	do {
		usleep_range(100, 110);
		data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
		if (data == ~0U)
			return 0;
	} while (++i < 10);

	netdev_err(ndev, "Failed to release memory from shutdown\n");
	return -ENODEV;
}

static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
{
	u32 val;

	val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0;
	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val);
	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val);
}

static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id,
				u32 reg, u16 data)
{
	u32 addr, wr_data, done;
	int i;

	addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);

	wr_data = PHY_CONTROL(data);
	xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data);

	for (i = 0; i < 10; i++) {
		done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
		if (!(done & BUSY_MASK))
			return;
		usleep_range(10, 20);
	}

	netdev_err(p->ndev, "MII_MGMT write failed\n");
}

static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg)
{
	u32 addr, data, done;
	int i;

	addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
	xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);

	for (i = 0; i < 10; i++) {
		done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
		if (!(done & BUSY_MASK)) {
			data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR);
			xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0);

			return data;
		}
		usleep_range(10, 20);
	}

	netdev_err(p->ndev, "MII_MGMT read failed\n");

	return 0;
}

static void xgene_sgmac_reset(struct xgene_enet_pdata *p)
{
	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1);
	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0);
}

static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p)
{
	u32 addr0, addr1;
	u8 *dev_addr = p->ndev->dev_addr;

	addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
		(dev_addr[1] << 8) | dev_addr[0];
	xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0);

	addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR);
	addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16);
	xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1);
}

static u32 xgene_enet_link_status(struct xgene_enet_pdata *p)
{
	u32 data;

	data = xgene_mii_phy_read(p, INT_PHY_ADDR,
				  SGMII_BASE_PAGE_ABILITY_ADDR >> 2);

	if (LINK_SPEED(data) == PHY_SPEED_1000)
		p->phy_speed = SPEED_1000;
	else if (LINK_SPEED(data) == PHY_SPEED_100)
		p->phy_speed = SPEED_100;
	else
		p->phy_speed = SPEED_10;

	return data & LINK_UP;
}

static void xgene_sgmii_configure(struct xgene_enet_pdata *p)
{
	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
			    0x8000);
	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x9000);
	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
}

static void xgene_sgmii_tbi_control_reset(struct xgene_enet_pdata *p)
{
	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
			    0x8000);
	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
}

static void xgene_sgmii_reset(struct xgene_enet_pdata *p)
{
	u32 value;

	if (p->phy_speed == SPEED_UNKNOWN)
		return;

	value = xgene_mii_phy_read(p, INT_PHY_ADDR,
				   SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
	if (!(value & LINK_UP))
		xgene_sgmii_tbi_control_reset(p);
}

static void xgene_sgmac_set_speed(struct xgene_enet_pdata *p)
{
	u32 icm0_addr, icm2_addr, debug_addr;
	u32 icm0, icm2, intf_ctl;
	u32 mc2, value;

	xgene_sgmii_reset(p);

	if (p->enet_id == XGENE_ENET1) {
		icm0_addr = ICM_CONFIG0_REG_0_ADDR + p->port_id * OFFSET_8;
		icm2_addr = ICM_CONFIG2_REG_0_ADDR + p->port_id * OFFSET_4;
		debug_addr = DEBUG_REG_ADDR;
	} else {
		icm0_addr = XG_MCX_ICM_CONFIG0_REG_0_ADDR;
		icm2_addr = XG_MCX_ICM_CONFIG2_REG_0_ADDR;
		debug_addr = XG_DEBUG_REG_ADDR;
	}

	icm0 = xgene_enet_rd_mcx_csr(p, icm0_addr);
	icm2 = xgene_enet_rd_mcx_csr(p, icm2_addr);
	mc2 = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR);
	intf_ctl = xgene_enet_rd_mac(p, INTERFACE_CONTROL_ADDR);

	switch (p->phy_speed) {
	case SPEED_10:
		ENET_INTERFACE_MODE2_SET(&mc2, 1);
		intf_ctl &= ~(ENET_LHD_MODE | ENET_GHD_MODE);
		CFG_MACMODE_SET(&icm0, 0);
		CFG_WAITASYNCRD_SET(&icm2, 500);
		break;
	case SPEED_100:
		ENET_INTERFACE_MODE2_SET(&mc2, 1);
		intf_ctl &= ~ENET_GHD_MODE;
		intf_ctl |= ENET_LHD_MODE;
		CFG_MACMODE_SET(&icm0, 1);
		CFG_WAITASYNCRD_SET(&icm2, 80);
		break;
	default:
		ENET_INTERFACE_MODE2_SET(&mc2, 2);
		intf_ctl &= ~ENET_LHD_MODE;
		intf_ctl |= ENET_GHD_MODE;
		CFG_MACMODE_SET(&icm0, 2);
		CFG_WAITASYNCRD_SET(&icm2, 16);
		value = xgene_enet_rd_csr(p, debug_addr);
		value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
		xgene_enet_wr_csr(p, debug_addr, value);
		break;
	}

	mc2 |= FULL_DUPLEX2 | PAD_CRC;
	xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2);
	xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, intf_ctl);
	xgene_enet_wr_mcx_csr(p, icm0_addr, icm0);
	xgene_enet_wr_mcx_csr(p, icm2_addr, icm2);
}

static void xgene_sgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size)
{
	xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size);
}

static void xgene_sgmii_enable_autoneg(struct xgene_enet_pdata *p)
{
	u32 data, loop = 10;

	xgene_sgmii_configure(p);

	while (loop--) {
		data = xgene_mii_phy_read(p, INT_PHY_ADDR,
					  SGMII_STATUS_ADDR >> 2);
		if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS))
			break;
		usleep_range(1000, 2000);
	}
	if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS))
		netdev_err(p->ndev, "Auto-negotiation failed\n");
}

static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set)
{
	u32 data;

	data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR);

	if (set)
		data |= bits;
	else
		data &= ~bits;

	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data);
}

static void xgene_sgmac_flowctl_tx(struct xgene_enet_pdata *p, bool enable)
{
	xgene_sgmac_rxtx(p, TX_FLOW_EN, enable);

	p->mac_ops->enable_tx_pause(p, enable);
}

static void xgene_sgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
{
	xgene_sgmac_rxtx(pdata, RX_FLOW_EN, enable);
}

static void xgene_sgmac_init(struct xgene_enet_pdata *p)
{
	u32 enet_spare_cfg_reg, rsif_config_reg;
	u32 cfg_bypass_reg, rx_dv_gate_reg;
	u32 data, offset;

	if (!(p->enet_id == XGENE_ENET2 && p->mdio_driver))
		xgene_sgmac_reset(p);

	xgene_sgmii_enable_autoneg(p);
	xgene_sgmac_set_speed(p);
	xgene_sgmac_set_mac_addr(p);

	if (p->enet_id == XGENE_ENET1) {
		enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR;
		rsif_config_reg = RSIF_CONFIG_REG_ADDR;
		cfg_bypass_reg = CFG_BYPASS_ADDR;
		offset = p->port_id * OFFSET_4;
		rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR + offset;
	} else {
		enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR;
		rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR;
		cfg_bypass_reg = XG_CFG_BYPASS_ADDR;
		rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR;
	}

	data = xgene_enet_rd_csr(p, enet_spare_cfg_reg);
	data |= MPA_IDLE_WITH_QMI_EMPTY;
	xgene_enet_wr_csr(p, enet_spare_cfg_reg, data);

	/* Adjust MDC clock frequency */
	data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR);
	MGMT_CLOCK_SEL_SET(&data, 7);
	xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data);

	/* Enable drop if bufpool not available */
	data = xgene_enet_rd_csr(p, rsif_config_reg);
	data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
	xgene_enet_wr_csr(p, rsif_config_reg, data);

	/* Bypass traffic gating */
	xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84);
	xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX);
	xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg, RESUME_RX0);
}

static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p)
{
	xgene_sgmac_rxtx(p, RX_EN, true);
}

static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p)
{
	xgene_sgmac_rxtx(p, TX_EN, true);
}

static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p)
{
	xgene_sgmac_rxtx(p, RX_EN, false);
}

static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
{
	xgene_sgmac_rxtx(p, TX_EN, false);
}

static int xgene_enet_reset(struct xgene_enet_pdata *p)
{
	struct device *dev = &p->pdev->dev;

	if (!xgene_ring_mgr_init(p))
		return -ENODEV;

	if (p->mdio_driver && p->enet_id == XGENE_ENET2) {
		xgene_enet_config_ring_if_assoc(p);
		return 0;
	}

	if (p->enet_id == XGENE_ENET2)
		xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN);

	if (dev->of_node) {
		if (!IS_ERR(p->clk)) {
			clk_prepare_enable(p->clk);
			udelay(5);
			clk_disable_unprepare(p->clk);
			udelay(5);
			clk_prepare_enable(p->clk);
			udelay(5);
		}
	} else {
#ifdef CONFIG_ACPI
		if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_RST"))
			acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
					     "_RST", NULL, NULL);
		else if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_INI"))
			acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
					     "_INI", NULL, NULL);
#endif
	}

	if (!p->port_id) {
		xgene_enet_ecc_init(p);
		xgene_enet_config_ring_if_assoc(p);
	}

	return 0;
}

static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p,
				  u32 dst_ring_num, u16 bufpool_id,
				  u16 nxtbufpool_id)
{
	u32 cle_bypass_reg0, cle_bypass_reg1;
	u32 offset = p->port_id * MAC_OFFSET;
	u32 data, fpsel, nxtfpsel;

	if (p->enet_id == XGENE_ENET1) {
		cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR;
		cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR;
	} else {
		cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR;
		cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR;
	}

	data = CFG_CLE_BYPASS_EN0;
	xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data);

	fpsel = xgene_enet_get_fpsel(bufpool_id);
	nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
	data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel) |
	       CFG_CLE_NXTFPSEL0(nxtfpsel);
	xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data);
}

static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
			     struct xgene_enet_desc_ring *ring)
{
	u32 addr, data;

	if (xgene_enet_is_bufpool(ring->id)) {
		addr = ENET_CFGSSQMIFPRESET_ADDR;
		data = BIT(xgene_enet_get_fpsel(ring->id));
	} else {
		addr = ENET_CFGSSQMIWQRESET_ADDR;
		data = BIT(xgene_enet_ring_bufnum(ring->id));
	}

	xgene_enet_wr_ring_if(pdata, addr, data);
}

static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
{
	struct device *dev = &p->pdev->dev;
	struct xgene_enet_desc_ring *ring;
	u32 pb;
	int i;

	pb = 0;
	for (i = 0; i < p->rxq_cnt; i++) {
		ring = p->rx_ring[i]->buf_pool;
		pb |= BIT(xgene_enet_get_fpsel(ring->id));
		ring = p->rx_ring[i]->page_pool;
		if (ring)
			pb |= BIT(xgene_enet_get_fpsel(ring->id));
	}
	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb);

	pb = 0;
	for (i = 0; i < p->txq_cnt; i++) {
		ring = p->tx_ring[i];
		pb |= BIT(xgene_enet_ring_bufnum(ring->id));
	}
	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQRESET_ADDR, pb);

	if (dev->of_node) {
		if (!IS_ERR(p->clk))
			clk_disable_unprepare(p->clk);
	}
}

static void xgene_enet_link_state(struct work_struct *work)
{
	struct xgene_enet_pdata *p = container_of(to_delayed_work(work),
				     struct xgene_enet_pdata, link_work);
	struct net_device *ndev = p->ndev;
	u32 link, poll_interval;

	link = xgene_enet_link_status(p);
	if (link) {
		if (!netif_carrier_ok(ndev)) {
			netif_carrier_on(ndev);
			xgene_sgmac_set_speed(p);
			xgene_sgmac_rx_enable(p);
			xgene_sgmac_tx_enable(p);
			netdev_info(ndev, "Link is Up - %dMbps\n",
				    p->phy_speed);
		}
		poll_interval = PHY_POLL_LINK_ON;
	} else {
		if (netif_carrier_ok(ndev)) {
			xgene_sgmac_rx_disable(p);
			xgene_sgmac_tx_disable(p);
			netif_carrier_off(ndev);
			netdev_info(ndev, "Link is Down\n");
		}
		poll_interval = PHY_POLL_LINK_OFF;
	}

	schedule_delayed_work(&p->link_work, poll_interval);
}

static void xgene_sgmac_enable_tx_pause(struct xgene_enet_pdata *p, bool enable)
{
	u32 data, ecm_cfg_addr;

	if (p->enet_id == XGENE_ENET1) {
		ecm_cfg_addr = (!(p->port_id % 2)) ? CSR_ECM_CFG_0_ADDR :
				CSR_ECM_CFG_1_ADDR;
	} else {
		ecm_cfg_addr = XG_MCX_ECM_CFG_0_ADDR;
	}

	data = xgene_enet_rd_mcx_csr(p, ecm_cfg_addr);
	if (enable)
		data |= MULTI_DPF_AUTOCTRL | PAUSE_XON_EN;
	else
		data &= ~(MULTI_DPF_AUTOCTRL | PAUSE_XON_EN);
	xgene_enet_wr_mcx_csr(p, ecm_cfg_addr, data);
}

const struct xgene_mac_ops xgene_sgmac_ops = {
	.init		= xgene_sgmac_init,
	.reset		= xgene_sgmac_reset,
	.rx_enable	= xgene_sgmac_rx_enable,
	.tx_enable	= xgene_sgmac_tx_enable,
	.rx_disable	= xgene_sgmac_rx_disable,
	.tx_disable	= xgene_sgmac_tx_disable,
	.set_speed	= xgene_sgmac_set_speed,
	.set_mac_addr	= xgene_sgmac_set_mac_addr,
	.set_framesize  = xgene_sgmac_set_frame_size,
	.link_state	= xgene_enet_link_state,
	.enable_tx_pause = xgene_sgmac_enable_tx_pause,
	.flowctl_tx     = xgene_sgmac_flowctl_tx,
	.flowctl_rx     = xgene_sgmac_flowctl_rx
};

const struct xgene_port_ops xgene_sgport_ops = {
	.reset		= xgene_enet_reset,
	.clear		= xgene_enet_clear,
	.cle_bypass	= xgene_enet_cle_bypass,
	.shutdown	= xgene_enet_shutdown
};
Commit	Line	Data
32f784b5 IS	1	/* Applied Micro X-Gene SoC Ethernet Driver
	2	*
	3	* Copyright (c) 2014, Applied Micro Circuits Corporation
	4	* Authors: Iyappan Subramanian <isubramanian@apm.com>
	5	* Keyur Chudgar <kchudgar@apm.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "xgene_enet_main.h"
	22	#include "xgene_enet_hw.h"
	23	#include "xgene_enet_sgmac.h"
561fea6d	24	#include "xgene_enet_xgmac.h"
32f784b5 IS	25
	26	static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val)
	27	{
	28	iowrite32(val, p->eth_csr_addr + offset);
	29	}
	30
bc61167a IS	31	static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset,
	32	u32 val)
	33	{
	34	iowrite32(val, p->base_addr + offset);
	35	}
	36
32f784b5 IS	37	static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p,
	38	u32 offset, u32 val)
	39	{
	40	iowrite32(val, p->eth_ring_if_addr + offset);
	41	}
	42
	43	static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p,
	44	u32 offset, u32 val)
	45	{
	46	iowrite32(val, p->eth_diag_csr_addr + offset);
	47	}
	48
561fea6d IS	49	static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
	50	u32 offset, u32 val)
	51	{
	52	void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
	53
	54	iowrite32(val, addr);
	55	}
	56
32f784b5 IS	57	static bool xgene_enet_wr_indirect(struct xgene_indirect_ctl *ctl,
	58	u32 wr_addr, u32 wr_data)
	59	{
	60	int i;
	61
	62	iowrite32(wr_addr, ctl->addr);
	63	iowrite32(wr_data, ctl->ctl);
	64	iowrite32(XGENE_ENET_WR_CMD, ctl->cmd);
	65
	66	/* wait for write command to complete */
	67	for (i = 0; i < 10; i++) {
	68	if (ioread32(ctl->cmd_done)) {
	69	iowrite32(0, ctl->cmd);
	70	return true;
	71	}
	72	udelay(1);
	73	}
	74
	75	return false;
	76	}
	77
	78	static void xgene_enet_wr_mac(struct xgene_enet_pdata *p,
	79	u32 wr_addr, u32 wr_data)
	80	{
	81	struct xgene_indirect_ctl ctl = {
	82	.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
	83	.ctl = p->mcx_mac_addr + MAC_WRITE_REG_OFFSET,
	84	.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
	85	.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
	86	};
	87
	88	if (!xgene_enet_wr_indirect(&ctl, wr_addr, wr_data))
	89	netdev_err(p->ndev, "mac write failed, addr: %04x\n", wr_addr);
	90	}
	91
	92	static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset)
	93	{
	94	return ioread32(p->eth_csr_addr + offset);
	95	}
	96
	97	static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset)
	98	{
	99	return ioread32(p->eth_diag_csr_addr + offset);
	100	}
	101
9a8c5dde IS	102	static u32 xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *p, u32 offset)
	103	{
	104	return ioread32(p->mcx_mac_csr_addr + offset);
	105	}
	106
32f784b5 IS	107	static u32 xgene_enet_rd_indirect(struct xgene_indirect_ctl *ctl, u32 rd_addr)
	108	{
	109	u32 rd_data;
	110	int i;
	111
	112	iowrite32(rd_addr, ctl->addr);
	113	iowrite32(XGENE_ENET_RD_CMD, ctl->cmd);
	114
	115	/* wait for read command to complete */
	116	for (i = 0; i < 10; i++) {
	117	if (ioread32(ctl->cmd_done)) {
	118	rd_data = ioread32(ctl->ctl);
	119	iowrite32(0, ctl->cmd);
	120
	121	return rd_data;
	122	}
	123	udelay(1);
	124	}
	125
	126	pr_err("%s: mac read failed, addr: %04x\n", __func__, rd_addr);
	127
	128	return 0;
	129	}
	130
	131	static u32 xgene_enet_rd_mac(struct xgene_enet_pdata *p, u32 rd_addr)
	132	{
	133	struct xgene_indirect_ctl ctl = {
	134	.addr = p->mcx_mac_addr + MAC_ADDR_REG_OFFSET,
	135	.ctl = p->mcx_mac_addr + MAC_READ_REG_OFFSET,
	136	.cmd = p->mcx_mac_addr + MAC_COMMAND_REG_OFFSET,
	137	.cmd_done = p->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET
	138	};
	139
	140	return xgene_enet_rd_indirect(&ctl, rd_addr);
	141	}
	142
	143	static int xgene_enet_ecc_init(struct xgene_enet_pdata *p)
	144	{
	145	struct net_device *ndev = p->ndev;
cb11c062	146	u32 data, shutdown;
b71e821d	147	int i = 0;
32f784b5	148
cb11c062 IS	149	shutdown = xgene_enet_rd_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR);
	150	data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
	151
	152	if (!shutdown && data == ~0U) {
	153	netdev_dbg(ndev, "+ ecc_init done, skipping\n");
	154	return 0;
	155	}
	156
32f784b5	157	xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0);
b71e821d	158	do {
32f784b5 IS	159	usleep_range(100, 110);
32f784b5 IS	160	data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR);
b71e821d GU	161	if (data == ~0U)
	162	return 0;
	163	} while (++i < 10);
32f784b5	164
b71e821d GU	165	netdev_err(ndev, "Failed to release memory from shutdown\n");
b71e821d GU	166	return -ENODEV;
32f784b5 IS	167	}
	168
	169	static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p)
	170	{
561fea6d	171	u32 val;
32f784b5	172
561fea6d	173	val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0;
32f784b5 IS	174	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val);
	175	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val);
	176	}
	177
	178	static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id,
	179	u32 reg, u16 data)
	180	{
	181	u32 addr, wr_data, done;
	182	int i;
	183
	184	addr = PHY_ADDR(phy_id) \| REG_ADDR(reg);
	185	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
	186
	187	wr_data = PHY_CONTROL(data);
	188	xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data);
	189
	190	for (i = 0; i < 10; i++) {
	191	done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
	192	if (!(done & BUSY_MASK))
	193	return;
	194	usleep_range(10, 20);
	195	}
	196
	197	netdev_err(p->ndev, "MII_MGMT write failed\n");
	198	}
	199
	200	static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg)
	201	{
	202	u32 addr, data, done;
	203	int i;
	204
	205	addr = PHY_ADDR(phy_id) \| REG_ADDR(reg);
	206	xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr);
	207	xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
	208
	209	for (i = 0; i < 10; i++) {
	210	done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR);
	211	if (!(done & BUSY_MASK)) {
	212	data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR);
	213	xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0);
	214
	215	return data;
	216	}
	217	usleep_range(10, 20);
	218	}
	219
	220	netdev_err(p->ndev, "MII_MGMT read failed\n");
	221
	222	return 0;
	223	}
	224
	225	static void xgene_sgmac_reset(struct xgene_enet_pdata *p)
	226	{
	227	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1);
	228	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0);
	229	}
	230
	231	static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p)
	232	{
	233	u32 addr0, addr1;
	234	u8 *dev_addr = p->ndev->dev_addr;
	235
	236	addr0 = (dev_addr[3] << 24) \| (dev_addr[2] << 16) \|
	237	(dev_addr[1] << 8) \| dev_addr[0];
238	xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0);
239
240	addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR);
241	addr1 \|= (dev_addr[5] << 24) \| (dev_addr[4] << 16);
242	xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1);
243	}
244
245	static u32 xgene_enet_link_status(struct xgene_enet_pdata *p)
246	{
247	u32 data;
248
249	data = xgene_mii_phy_read(p, INT_PHY_ADDR,
250	SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
251
9a8c5dde IS	252	if (LINK_SPEED(data) == PHY_SPEED_1000)
	253	p->phy_speed = SPEED_1000;
	254	else if (LINK_SPEED(data) == PHY_SPEED_100)
	255	p->phy_speed = SPEED_100;
	256	else
	257	p->phy_speed = SPEED_10;
	258
32f784b5 IS	259	return data & LINK_UP;
	260	}
	261
9a8c5dde	262	static void xgene_sgmii_configure(struct xgene_enet_pdata *p)
32f784b5	263	{
9a8c5dde IS	264	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
	265	0x8000);
	266	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x9000);
	267	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
	268	}
32f784b5	269
9a8c5dde IS	270	static void xgene_sgmii_tbi_control_reset(struct xgene_enet_pdata *p)
	271	{
	272	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2,
	273	0x8000);
32f784b5	274	xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0);
9a8c5dde IS	275	}
	276
	277	static void xgene_sgmii_reset(struct xgene_enet_pdata *p)
	278	{
	279	u32 value;
	280
	281	if (p->phy_speed == SPEED_UNKNOWN)
	282	return;
	283
	284	value = xgene_mii_phy_read(p, INT_PHY_ADDR,
	285	SGMII_BASE_PAGE_ABILITY_ADDR >> 2);
	286	if (!(value & LINK_UP))
	287	xgene_sgmii_tbi_control_reset(p);
	288	}
	289
	290	static void xgene_sgmac_set_speed(struct xgene_enet_pdata *p)
	291	{
	292	u32 icm0_addr, icm2_addr, debug_addr;
	293	u32 icm0, icm2, intf_ctl;
	294	u32 mc2, value;
	295
	296	xgene_sgmii_reset(p);
	297
	298	if (p->enet_id == XGENE_ENET1) {
	299	icm0_addr = ICM_CONFIG0_REG_0_ADDR + p->port_id * OFFSET_8;
	300	icm2_addr = ICM_CONFIG2_REG_0_ADDR + p->port_id * OFFSET_4;
	301	debug_addr = DEBUG_REG_ADDR;
	302	} else {
	303	icm0_addr = XG_MCX_ICM_CONFIG0_REG_0_ADDR;
	304	icm2_addr = XG_MCX_ICM_CONFIG2_REG_0_ADDR;
	305	debug_addr = XG_DEBUG_REG_ADDR;
	306	}
	307
	308	icm0 = xgene_enet_rd_mcx_csr(p, icm0_addr);
	309	icm2 = xgene_enet_rd_mcx_csr(p, icm2_addr);
	310	mc2 = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR);
	311	intf_ctl = xgene_enet_rd_mac(p, INTERFACE_CONTROL_ADDR);
	312
	313	switch (p->phy_speed) {
	314	case SPEED_10:
	315	ENET_INTERFACE_MODE2_SET(&mc2, 1);
	316	intf_ctl &= ~(ENET_LHD_MODE \| ENET_GHD_MODE);
	317	CFG_MACMODE_SET(&icm0, 0);
	318	CFG_WAITASYNCRD_SET(&icm2, 500);
	319	break;
	320	case SPEED_100:
	321	ENET_INTERFACE_MODE2_SET(&mc2, 1);
	322	intf_ctl &= ~ENET_GHD_MODE;
	323	intf_ctl \|= ENET_LHD_MODE;
	324	CFG_MACMODE_SET(&icm0, 1);
	325	CFG_WAITASYNCRD_SET(&icm2, 80);
	326	break;
	327	default:
	328	ENET_INTERFACE_MODE2_SET(&mc2, 2);
	329	intf_ctl &= ~ENET_LHD_MODE;
	330	intf_ctl \|= ENET_GHD_MODE;
	331	CFG_MACMODE_SET(&icm0, 2);
	332	CFG_WAITASYNCRD_SET(&icm2, 16);
	333	value = xgene_enet_rd_csr(p, debug_addr);
	334	value \|= CFG_BYPASS_UNISEC_TX \| CFG_BYPASS_UNISEC_RX;
	335	xgene_enet_wr_csr(p, debug_addr, value);
	336	break;
	337	}
	338
339	mc2 \|= FULL_DUPLEX2 \| PAD_CRC;
340	xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2);
341	xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, intf_ctl);
342	xgene_enet_wr_mcx_csr(p, icm0_addr, icm0);
343	xgene_enet_wr_mcx_csr(p, icm2_addr, icm2);
344	}
345
350b4e33 IS	346	static void xgene_sgmac_set_frame_size(struct xgene_enet_pdata *pdata, int size)
	347	{
	348	xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size);
	349	}
	350
9a8c5dde IS	351	static void xgene_sgmii_enable_autoneg(struct xgene_enet_pdata *p)
	352	{
	353	u32 data, loop = 10;
	354
	355	xgene_sgmii_configure(p);
32f784b5 IS	356
	357	while (loop--) {
	358	data = xgene_mii_phy_read(p, INT_PHY_ADDR,
	359	SGMII_STATUS_ADDR >> 2);
	360	if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS))
	361	break;
561fea6d	362	usleep_range(1000, 2000);
32f784b5 IS	363	}
	364	if (!(data & AUTO_NEG_COMPLETE) \|\| !(data & LINK_STATUS))
	365	netdev_err(p->ndev, "Auto-negotiation failed\n");
9a8c5dde	366	}
32f784b5	367
bb64fa09 IS	368	static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set)
	369	{
	370	u32 data;
	371
	372	data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR);
	373
	374	if (set)
	375	data \|= bits;
	376	else
	377	data &= ~bits;
	378
	379	xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data);
	380	}
	381
	382	static void xgene_sgmac_flowctl_tx(struct xgene_enet_pdata *p, bool enable)
	383	{
	384	xgene_sgmac_rxtx(p, TX_FLOW_EN, enable);
	385
	386	p->mac_ops->enable_tx_pause(p, enable);
	387	}
	388
	389	static void xgene_sgmac_flowctl_rx(struct xgene_enet_pdata *pdata, bool enable)
	390	{
	391	xgene_sgmac_rxtx(pdata, RX_FLOW_EN, enable);
	392	}
	393
9a8c5dde IS	394	static void xgene_sgmac_init(struct xgene_enet_pdata *p)
	395	{
	396	u32 enet_spare_cfg_reg, rsif_config_reg;
	397	u32 cfg_bypass_reg, rx_dv_gate_reg;
	398	u32 data, offset;
	399
8089a96f IS	400	if (!(p->enet_id == XGENE_ENET2 && p->mdio_driver))
	401	xgene_sgmac_reset(p);
	402
9a8c5dde IS	403	xgene_sgmii_enable_autoneg(p);
	404	xgene_sgmac_set_speed(p);
	405	xgene_sgmac_set_mac_addr(p);
32f784b5	406
561fea6d IS	407	if (p->enet_id == XGENE_ENET1) {
	408	enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR;
	409	rsif_config_reg = RSIF_CONFIG_REG_ADDR;
	410	cfg_bypass_reg = CFG_BYPASS_ADDR;
9a8c5dde IS	411	offset = p->port_id * OFFSET_4;
9a8c5dde IS	412	rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR + offset;
561fea6d IS	413	} else {
	414	enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR;
	415	rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR;
	416	cfg_bypass_reg = XG_CFG_BYPASS_ADDR;
	417	rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR;
	418	}
	419
	420	data = xgene_enet_rd_csr(p, enet_spare_cfg_reg);
32f784b5	421	data \|= MPA_IDLE_WITH_QMI_EMPTY;
561fea6d	422	xgene_enet_wr_csr(p, enet_spare_cfg_reg, data);
32f784b5	423
32f784b5 IS	424	/* Adjust MDC clock frequency */
	425	data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR);
	426	MGMT_CLOCK_SEL_SET(&data, 7);
	427	xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data);
	428
	429	/* Enable drop if bufpool not available */
561fea6d	430	data = xgene_enet_rd_csr(p, rsif_config_reg);
32f784b5	431	data \|= CFG_RSIF_FPBUFF_TIMEOUT_EN;
561fea6d	432	xgene_enet_wr_csr(p, rsif_config_reg, data);
32f784b5 IS	433
32f784b5 IS	434	/* Bypass traffic gating */
561fea6d IS	435	xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84);
561fea6d IS	436	xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX);
9a8c5dde	437	xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg, RESUME_RX0);
32f784b5 IS	438	}
32f784b5 IS	439
32f784b5 IS	440	static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p)
	441	{
	442	xgene_sgmac_rxtx(p, RX_EN, true);
	443	}
	444
	445	static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p)
	446	{
	447	xgene_sgmac_rxtx(p, TX_EN, true);
	448	}
	449
	450	static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p)
	451	{
	452	xgene_sgmac_rxtx(p, RX_EN, false);
	453	}
	454
	455	static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p)
	456	{
	457	xgene_sgmac_rxtx(p, TX_EN, false);
	458	}
	459
c3f4465d	460	static int xgene_enet_reset(struct xgene_enet_pdata *p)
32f784b5	461	{
bc61167a IS	462	struct device *dev = &p->pdev->dev;
bc61167a IS	463
c3f4465d IS	464	if (!xgene_ring_mgr_init(p))
	465	return -ENODEV;
	466
8089a96f IS	467	if (p->mdio_driver && p->enet_id == XGENE_ENET2) {
	468	xgene_enet_config_ring_if_assoc(p);
	469	return 0;
	470	}
	471
bc61167a IS	472	if (p->enet_id == XGENE_ENET2)
	473	xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN);
	474
	475	if (dev->of_node) {
	476	if (!IS_ERR(p->clk)) {
	477	clk_prepare_enable(p->clk);
	478	udelay(5);
	479	clk_disable_unprepare(p->clk);
	480	udelay(5);
	481	clk_prepare_enable(p->clk);
	482	udelay(5);
	483	}
	484	} else {
	485	#ifdef CONFIG_ACPI
	486	if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_RST"))
	487	acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
	488	"_RST", NULL, NULL);
	489	else if (acpi_has_method(ACPI_HANDLE(&p->pdev->dev), "_INI"))
	490	acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev),
	491	"_INI", NULL, NULL);
	492	#endif
c2d33bdc	493	}
32f784b5	494
bc61167a IS	495	if (!p->port_id) {
	496	xgene_enet_ecc_init(p);
	497	xgene_enet_config_ring_if_assoc(p);
	498	}
c3f4465d IS	499
c3f4465d IS	500	return 0;
32f784b5 IS	501	}
	502
	503	static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p,
d6d48969 IS	504	u32 dst_ring_num, u16 bufpool_id,
d6d48969 IS	505	u16 nxtbufpool_id)
32f784b5	506	{
561fea6d	507	u32 cle_bypass_reg0, cle_bypass_reg1;
ca626454	508	u32 offset = p->port_id * MAC_OFFSET;
d6d48969	509	u32 data, fpsel, nxtfpsel;
32f784b5	510
561fea6d IS	511	if (p->enet_id == XGENE_ENET1) {
	512	cle_bypass_reg0 = CLE_BYPASS_REG0_0_ADDR;
	513	cle_bypass_reg1 = CLE_BYPASS_REG1_0_ADDR;
	514	} else {
	515	cle_bypass_reg0 = XCLE_BYPASS_REG0_ADDR;
	516	cle_bypass_reg1 = XCLE_BYPASS_REG1_ADDR;
	517	}
	518
32f784b5	519	data = CFG_CLE_BYPASS_EN0;
561fea6d	520	xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data);
32f784b5	521
2c839337	522	fpsel = xgene_enet_get_fpsel(bufpool_id);
d6d48969 IS	523	nxtfpsel = xgene_enet_get_fpsel(nxtbufpool_id);
	524	data = CFG_CLE_DSTQID0(dst_ring_num) \| CFG_CLE_FPSEL0(fpsel) \|
	525	CFG_CLE_NXTFPSEL0(nxtfpsel);
561fea6d	526	xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data);
32f784b5 IS	527	}
32f784b5 IS	528
cb11c062 IS	529	static void xgene_enet_clear(struct xgene_enet_pdata *pdata,
	530	struct xgene_enet_desc_ring *ring)
	531	{
2c839337	532	u32 addr, data;
cb11c062 IS	533
	534	if (xgene_enet_is_bufpool(ring->id)) {
	535	addr = ENET_CFGSSQMIFPRESET_ADDR;
2c839337	536	data = BIT(xgene_enet_get_fpsel(ring->id));
cb11c062 IS	537	} else {
cb11c062 IS	538	addr = ENET_CFGSSQMIWQRESET_ADDR;
2c839337	539	data = BIT(xgene_enet_ring_bufnum(ring->id));
cb11c062 IS	540	}
	541
	542	xgene_enet_wr_ring_if(pdata, addr, data);
	543	}
	544
32f784b5 IS	545	static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
32f784b5 IS	546	{
bc61167a	547	struct device *dev = &p->pdev->dev;
cb11c062	548	struct xgene_enet_desc_ring *ring;
2c839337	549	u32 pb;
cb11c062 IS	550	int i;
	551
	552	pb = 0;
	553	for (i = 0; i < p->rxq_cnt; i++) {
	554	ring = p->rx_ring[i]->buf_pool;
2c839337	555	pb \|= BIT(xgene_enet_get_fpsel(ring->id));
a9380b0f IS	556	ring = p->rx_ring[i]->page_pool;
	557	if (ring)
	558	pb \|= BIT(xgene_enet_get_fpsel(ring->id));
cb11c062 IS	559	}
	560	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb);
	561
	562	pb = 0;
	563	for (i = 0; i < p->txq_cnt; i++) {
	564	ring = p->tx_ring[i];
2c839337	565	pb \|= BIT(xgene_enet_ring_bufnum(ring->id));
cb11c062 IS	566	}
cb11c062 IS	567	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQRESET_ADDR, pb);
bc61167a IS	568
	569	if (dev->of_node) {
	570	if (!IS_ERR(p->clk))
	571	clk_disable_unprepare(p->clk);
	572	}
32f784b5 IS	573	}
	574
	575	static void xgene_enet_link_state(struct work_struct *work)
	576	{
	577	struct xgene_enet_pdata *p = container_of(to_delayed_work(work),
	578	struct xgene_enet_pdata, link_work);
	579	struct net_device *ndev = p->ndev;
	580	u32 link, poll_interval;
	581
	582	link = xgene_enet_link_status(p);
	583	if (link) {
	584	if (!netif_carrier_ok(ndev)) {
	585	netif_carrier_on(ndev);
9a8c5dde	586	xgene_sgmac_set_speed(p);
32f784b5 IS	587	xgene_sgmac_rx_enable(p);
32f784b5 IS	588	xgene_sgmac_tx_enable(p);
9a8c5dde IS	589	netdev_info(ndev, "Link is Up - %dMbps\n",
9a8c5dde IS	590	p->phy_speed);
32f784b5 IS	591	}
	592	poll_interval = PHY_POLL_LINK_ON;
	593	} else {
	594	if (netif_carrier_ok(ndev)) {
	595	xgene_sgmac_rx_disable(p);
	596	xgene_sgmac_tx_disable(p);
	597	netif_carrier_off(ndev);
	598	netdev_info(ndev, "Link is Down\n");
	599	}
	600	poll_interval = PHY_POLL_LINK_OFF;
	601	}
	602
	603	schedule_delayed_work(&p->link_work, poll_interval);
	604	}
	605
bb64fa09 IS	606	static void xgene_sgmac_enable_tx_pause(struct xgene_enet_pdata *p, bool enable)
	607	{
	608	u32 data, ecm_cfg_addr;
	609
	610	if (p->enet_id == XGENE_ENET1) {
	611	ecm_cfg_addr = (!(p->port_id % 2)) ? CSR_ECM_CFG_0_ADDR :
	612	CSR_ECM_CFG_1_ADDR;
	613	} else {
	614	ecm_cfg_addr = XG_MCX_ECM_CFG_0_ADDR;
	615	}
	616
	617	data = xgene_enet_rd_mcx_csr(p, ecm_cfg_addr);
	618	if (enable)
	619	data \|= MULTI_DPF_AUTOCTRL \| PAUSE_XON_EN;
	620	else
	621	data &= ~(MULTI_DPF_AUTOCTRL \| PAUSE_XON_EN);
	622	xgene_enet_wr_mcx_csr(p, ecm_cfg_addr, data);
	623	}
	624
3cdb7309	625	const struct xgene_mac_ops xgene_sgmac_ops = {
32f784b5 IS	626	.init = xgene_sgmac_init,
	627	.reset = xgene_sgmac_reset,
	628	.rx_enable = xgene_sgmac_rx_enable,
	629	.tx_enable = xgene_sgmac_tx_enable,
	630	.rx_disable = xgene_sgmac_rx_disable,
	631	.tx_disable = xgene_sgmac_tx_disable,
9a8c5dde	632	.set_speed = xgene_sgmac_set_speed,
32f784b5	633	.set_mac_addr = xgene_sgmac_set_mac_addr,
350b4e33	634	.set_framesize = xgene_sgmac_set_frame_size,
bb64fa09 IS	635	.link_state = xgene_enet_link_state,
	636	.enable_tx_pause = xgene_sgmac_enable_tx_pause,
	637	.flowctl_tx = xgene_sgmac_flowctl_tx,
	638	.flowctl_rx = xgene_sgmac_flowctl_rx
32f784b5 IS	639	};
32f784b5 IS	640
3cdb7309	641	const struct xgene_port_ops xgene_sgport_ops = {
32f784b5	642	.reset = xgene_enet_reset,
cb11c062	643	.clear = xgene_enet_clear,
32f784b5 IS	644	.cle_bypass = xgene_enet_cle_bypass,
	645	.shutdown = xgene_enet_shutdown
	646	};