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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / aquantia / atlantic / aq_nic.c
CommitLineData
75a6faf6 1// SPDX-License-Identifier: GPL-2.0-only
843e1396
MS
2/* Atlantic Network Driver
3 *
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
97bde5c4
DV
6 */
7
8/* File aq_nic.c: Definition of common code for NIC. */
9
10#include "aq_nic.h"
11#include "aq_ring.h"
12#include "aq_vec.h"
13#include "aq_hw.h"
14#include "aq_pci_func.h"
62c1c2e6 15#include "aq_macsec.h"
4c83f170 16#include "aq_main.h"
dbcd6806 17#include "aq_phy.h"
1a64f8dc 18#include "aq_ptp.h"
5a1bf9ef 19#include "aq_filters.h"
97bde5c4 20
b82ee71a 21#include <linux/moduleparam.h>
97bde5c4
DV
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/timer.h>
25#include <linux/cpu.h>
26#include <linux/ip.h>
27#include <linux/tcp.h>
28#include <net/ip.h>
a83fe6b6 29#include <net/pkt_cls.h>
97bde5c4 30
b82ee71a
IR
31static unsigned int aq_itr = AQ_CFG_INTERRUPT_MODERATION_AUTO;
32module_param_named(aq_itr, aq_itr, uint, 0644);
33MODULE_PARM_DESC(aq_itr, "Interrupt throttling mode");
34
35static unsigned int aq_itr_tx;
36module_param_named(aq_itr_tx, aq_itr_tx, uint, 0644);
37MODULE_PARM_DESC(aq_itr_tx, "TX interrupt throttle rate");
38
39static unsigned int aq_itr_rx;
40module_param_named(aq_itr_rx, aq_itr_rx, uint, 0644);
41MODULE_PARM_DESC(aq_itr_rx, "RX interrupt throttle rate");
42
9f8a2203
IR
43static void aq_nic_update_ndev_stats(struct aq_nic_s *self);
44
97bde5c4
DV
45static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)
46{
474fb115 47 static u8 rss_key[AQ_CFG_RSS_HASHKEY_SIZE] = {
97bde5c4
DV
48 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d,
49 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18,
50 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8,
51 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70,
52 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c
53 };
7b0c342f
ND
54 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
55 struct aq_rss_parameters *rss_params;
56 int i = 0;
57
58 rss_params = &cfg->aq_rss;
97bde5c4
DV
59
60 rss_params->hash_secret_key_size = sizeof(rss_key);
61 memcpy(rss_params->hash_secret_key, rss_key, sizeof(rss_key));
62 rss_params->indirection_table_size = AQ_CFG_RSS_INDIRECTION_TABLE_MAX;
63
64 for (i = rss_params->indirection_table_size; i--;)
65 rss_params->indirection_table[i] = i & (num_rss_queues - 1);
66}
67
14ef766b
MS
68/* Recalculate the number of vectors */
69static void aq_nic_cfg_update_num_vecs(struct aq_nic_s *self)
70{
71 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
72
73 cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
74 cfg->vecs = min(cfg->vecs, num_online_cpus());
75 if (self->irqvecs > AQ_HW_SERVICE_IRQS)
76 cfg->vecs = min(cfg->vecs, self->irqvecs - AQ_HW_SERVICE_IRQS);
77 /* cfg->vecs should be power of 2 for RSS */
78 cfg->vecs = rounddown_pow_of_two(cfg->vecs);
79
80 if (ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ANTIGUA)) {
81 if (cfg->tcs > 2)
82 cfg->vecs = min(cfg->vecs, 4U);
83 }
84
85 if (cfg->vecs <= 4)
86 cfg->tc_mode = AQ_TC_MODE_8TCS;
87 else
88 cfg->tc_mode = AQ_TC_MODE_4TCS;
89
90 /*rss rings */
91 cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF);
92 aq_nic_rss_init(self, cfg->num_rss_queues);
93}
94
23ee07ad
IR
95/* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */
96void aq_nic_cfg_start(struct aq_nic_s *self)
97bde5c4
DV
97{
98 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
a83fe6b6 99 int i;
97bde5c4 100
97bde5c4
DV
101 cfg->tcs = AQ_CFG_TCS_DEF;
102
97bde5c4
DV
103 cfg->is_polling = AQ_CFG_IS_POLLING_DEF;
104
b82ee71a
IR
105 cfg->itr = aq_itr;
106 cfg->tx_itr = aq_itr_tx;
107 cfg->rx_itr = aq_itr_rx;
97bde5c4 108
46f4c29d 109 cfg->rxpageorder = AQ_CFG_RX_PAGEORDER;
97bde5c4 110 cfg->is_rss = AQ_CFG_IS_RSS_DEF;
97bde5c4 111 cfg->aq_rss.base_cpu_number = AQ_CFG_RSS_BASE_CPU_NUM_DEF;
8009bb19 112 cfg->fc.req = AQ_CFG_FC_MODE;
837c6378 113 cfg->wol = AQ_CFG_WOL_MODES;
97bde5c4
DV
114
115 cfg->mtu = AQ_CFG_MTU_DEF;
116 cfg->link_speed_msk = AQ_CFG_SPEED_MSK;
117 cfg->is_autoneg = AQ_CFG_IS_AUTONEG_DEF;
118
119 cfg->is_lro = AQ_CFG_IS_LRO_DEF;
0aa7bc3e 120 cfg->is_ptp = true;
97bde5c4 121
97bde5c4 122 /*descriptors */
c1af5427
AM
123 cfg->rxds = min(cfg->aq_hw_caps->rxds_max, AQ_CFG_RXDS_DEF);
124 cfg->txds = min(cfg->aq_hw_caps->txds_max, AQ_CFG_TXDS_DEF);
97bde5c4 125
14ef766b 126 aq_nic_cfg_update_num_vecs(self);
a8c69ca7 127
23ee07ad 128 cfg->irq_type = aq_pci_func_get_irq_type(self);
97bde5c4
DV
129
130 if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) ||
8fcb98f4 131 (cfg->aq_hw_caps->vecs == 1U) ||
97bde5c4
DV
132 (cfg->vecs == 1U)) {
133 cfg->is_rss = 0U;
134 cfg->vecs = 1U;
135 }
136
4c83f170
IR
137 /* Check if we have enough vectors allocated for
138 * link status IRQ. If no - we'll know link state from
139 * slower service task.
140 */
141 if (AQ_HW_SERVICE_IRQS > 0 && cfg->vecs + 1 <= self->irqvecs)
142 cfg->link_irq_vec = cfg->vecs;
143 else
144 cfg->link_irq_vec = 0;
145
8fcb98f4 146 cfg->link_speed_msk &= cfg->aq_hw_caps->link_speed_msk;
bbb67a44 147 cfg->features = cfg->aq_hw_caps->hw_features;
d3ed7c5c
IR
148 cfg->is_vlan_rx_strip = !!(cfg->features & NETIF_F_HW_VLAN_CTAG_RX);
149 cfg->is_vlan_tx_insert = !!(cfg->features & NETIF_F_HW_VLAN_CTAG_TX);
48dd73d0 150 cfg->is_vlan_force_promisc = true;
a83fe6b6
DB
151
152 for (i = 0; i < sizeof(cfg->prio_tc_map); i++)
153 cfg->prio_tc_map[i] = cfg->tcs * i / 8;
97bde5c4
DV
154}
155
3aec6412
IR
156static int aq_nic_update_link_status(struct aq_nic_s *self)
157{
0c58c35f 158 int err = self->aq_fw_ops->update_link_status(self->aq_hw);
35e8e8b4 159 u32 fc = 0;
3aec6412
IR
160
161 if (err)
162 return err;
163
8009bb19
ND
164 if (self->aq_fw_ops->get_flow_control)
165 self->aq_fw_ops->get_flow_control(self->aq_hw, &fc);
166 self->aq_nic_cfg.fc.cur = fc;
167
b82ee71a 168 if (self->link_status.mbps != self->aq_hw->aq_link_status.mbps) {
58128fa0
ND
169 netdev_info(self->ndev, "%s: link change old %d new %d\n",
170 AQ_CFG_DRV_NAME, self->link_status.mbps,
171 self->aq_hw->aq_link_status.mbps);
b82ee71a 172 aq_nic_update_interrupt_moderation_settings(self);
35e8e8b4 173
04a18399 174 if (self->aq_ptp) {
910479a9 175 aq_ptp_clock_init(self);
04a18399
EP
176 aq_ptp_tm_offset_set(self,
177 self->aq_hw->aq_link_status.mbps);
9c477032 178 aq_ptp_link_change(self);
04a18399 179 }
910479a9 180
35e8e8b4
IR
181 /* Driver has to update flow control settings on RX block
182 * on any link event.
183 * We should query FW whether it negotiated FC.
184 */
35e8e8b4
IR
185 if (self->aq_hw_ops->hw_set_fc)
186 self->aq_hw_ops->hw_set_fc(self->aq_hw, fc, 0);
b82ee71a 187 }
3aec6412
IR
188
189 self->link_status = self->aq_hw->aq_link_status;
190 if (!netif_carrier_ok(self->ndev) && self->link_status.mbps) {
78f5193d 191 aq_utils_obj_set(&self->flags,
3aec6412 192 AQ_NIC_FLAG_STARTED);
78f5193d 193 aq_utils_obj_clear(&self->flags,
3aec6412
IR
194 AQ_NIC_LINK_DOWN);
195 netif_carrier_on(self->ndev);
62c1c2e6
DB
196#if IS_ENABLED(CONFIG_MACSEC)
197 aq_macsec_enable(self);
198#endif
2deac71a
MS
199 if (self->aq_hw_ops->hw_tc_rate_limit_set)
200 self->aq_hw_ops->hw_tc_rate_limit_set(self->aq_hw);
201
3aec6412
IR
202 netif_tx_wake_all_queues(self->ndev);
203 }
204 if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) {
205 netif_carrier_off(self->ndev);
206 netif_tx_disable(self->ndev);
78f5193d 207 aq_utils_obj_set(&self->flags, AQ_NIC_LINK_DOWN);
3aec6412 208 }
7b0c342f 209
3aec6412
IR
210 return 0;
211}
212
1d2a8a13
IR
213static irqreturn_t aq_linkstate_threaded_isr(int irq, void *private)
214{
215 struct aq_nic_s *self = private;
216
217 if (!self)
218 return IRQ_NONE;
219
220 aq_nic_update_link_status(self);
221
222 self->aq_hw_ops->hw_irq_enable(self->aq_hw,
223 BIT(self->aq_nic_cfg.link_irq_vec));
7b0c342f 224
1d2a8a13
IR
225 return IRQ_HANDLED;
226}
227
49544935 228static void aq_nic_service_task(struct work_struct *work)
97bde5c4 229{
49544935
IR
230 struct aq_nic_s *self = container_of(work, struct aq_nic_s,
231 service_task);
232 int err;
97bde5c4 233
04a18399
EP
234 aq_ptp_service_task(self);
235
78f5193d 236 if (aq_utils_obj_test(&self->flags, AQ_NIC_FLAGS_IS_NOT_READY))
49544935 237 return;
97bde5c4 238
3aec6412
IR
239 err = aq_nic_update_link_status(self);
240 if (err)
49544935 241 return;
97bde5c4 242
62c1c2e6
DB
243#if IS_ENABLED(CONFIG_MACSEC)
244 aq_macsec_work(self);
245#endif
246
49544935 247 mutex_lock(&self->fwreq_mutex);
0c58c35f
IR
248 if (self->aq_fw_ops->update_stats)
249 self->aq_fw_ops->update_stats(self->aq_hw);
49544935 250 mutex_unlock(&self->fwreq_mutex);
65e665e6 251
9f8a2203 252 aq_nic_update_ndev_stats(self);
49544935
IR
253}
254
255static void aq_nic_service_timer_cb(struct timer_list *t)
256{
257 struct aq_nic_s *self = from_timer(self, t, service_timer);
97bde5c4 258
7b0c342f
ND
259 mod_timer(&self->service_timer,
260 jiffies + AQ_CFG_SERVICE_TIMER_INTERVAL);
49544935
IR
261
262 aq_ndev_schedule_work(&self->service_task);
97bde5c4
DV
263}
264
e99e88a9 265static void aq_nic_polling_timer_cb(struct timer_list *t)
97bde5c4 266{
e99e88a9 267 struct aq_nic_s *self = from_timer(self, t, polling_timer);
97bde5c4
DV
268 struct aq_vec_s *aq_vec = NULL;
269 unsigned int i = 0U;
270
271 for (i = 0U, aq_vec = self->aq_vec[0];
272 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
273 aq_vec_isr(i, (void *)aq_vec);
274
275 mod_timer(&self->polling_timer, jiffies +
e9157848 276 AQ_CFG_POLLING_TIMER_INTERVAL);
97bde5c4
DV
277}
278
099d074e
MS
279static int aq_nic_hw_prepare(struct aq_nic_s *self)
280{
281 int err = 0;
282
283 err = self->aq_hw_ops->hw_soft_reset(self->aq_hw);
284 if (err)
285 goto exit;
286
287 err = self->aq_hw_ops->hw_prepare(self->aq_hw, &self->aq_fw_ops);
288
289exit:
290 return err;
291}
292
b4de6c49
MS
293static bool aq_nic_is_valid_ether_addr(const u8 *addr)
294{
295 /* Some engineering samples of Aquantia NICs are provisioned with a
296 * partially populated MAC, which is still invalid.
297 */
298 return !(addr[0] == 0 && addr[1] == 0 && addr[2] == 0);
299}
300
97bde5c4
DV
301int aq_nic_ndev_register(struct aq_nic_s *self)
302{
303 int err = 0;
97bde5c4
DV
304
305 if (!self->ndev) {
306 err = -EINVAL;
307 goto err_exit;
308 }
23ee07ad 309
099d074e 310 err = aq_nic_hw_prepare(self);
0c58c35f
IR
311 if (err)
312 goto err_exit;
313
62c1c2e6
DB
314#if IS_ENABLED(CONFIG_MACSEC)
315 aq_macsec_init(self);
316#endif
317
f5dce08a 318 mutex_lock(&self->fwreq_mutex);
0c58c35f 319 err = self->aq_fw_ops->get_mac_permanent(self->aq_hw,
97bde5c4 320 self->ndev->dev_addr);
f5dce08a 321 mutex_unlock(&self->fwreq_mutex);
23ee07ad 322 if (err)
97bde5c4
DV
323 goto err_exit;
324
b4de6c49
MS
325 if (!is_valid_ether_addr(self->ndev->dev_addr) ||
326 !aq_nic_is_valid_ether_addr(self->ndev->dev_addr)) {
327 netdev_warn(self->ndev, "MAC is invalid, will use random.");
328 eth_hw_addr_random(self->ndev);
329 }
330
97bde5c4
DV
331#if defined(AQ_CFG_MAC_ADDR_PERMANENT)
332 {
333 static u8 mac_addr_permanent[] = AQ_CFG_MAC_ADDR_PERMANENT;
334
335 ether_addr_copy(self->ndev->dev_addr, mac_addr_permanent);
336 }
337#endif
97bde5c4 338
23ee07ad
IR
339 for (self->aq_vecs = 0; self->aq_vecs < aq_nic_get_cfg(self)->vecs;
340 self->aq_vecs++) {
341 self->aq_vec[self->aq_vecs] =
342 aq_vec_alloc(self, self->aq_vecs, aq_nic_get_cfg(self));
343 if (!self->aq_vec[self->aq_vecs]) {
344 err = -ENOMEM;
345 goto err_exit;
346 }
347 }
348
97bde5c4
DV
349 netif_carrier_off(self->ndev);
350
3aec6412 351 netif_tx_disable(self->ndev);
97bde5c4 352
55629109 353 err = register_netdev(self->ndev);
23ee07ad 354 if (err)
55629109
PB
355 goto err_exit;
356
97bde5c4 357err_exit:
62c1c2e6
DB
358#if IS_ENABLED(CONFIG_MACSEC)
359 if (err)
360 aq_macsec_free(self);
361#endif
97bde5c4
DV
362 return err;
363}
364
23ee07ad 365void aq_nic_ndev_init(struct aq_nic_s *self)
97bde5c4 366{
4cbc9f92 367 const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps;
97bde5c4
DV
368 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg;
369
370 self->ndev->hw_features |= aq_hw_caps->hw_features;
371 self->ndev->features = aq_hw_caps->hw_features;
8c61ab7f 372 self->ndev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
d3ed7c5c 373 NETIF_F_RXHASH | NETIF_F_SG |
8bd60710 374 NETIF_F_LRO | NETIF_F_TSO | NETIF_F_TSO6;
822cd114 375 self->ndev->gso_partial_features = NETIF_F_GSO_UDP_L4;
97bde5c4 376 self->ndev->priv_flags = aq_hw_caps->hw_priv_flags;
3e9a5451
IR
377 self->ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
378
58128fa0 379 self->msg_enable = NETIF_MSG_DRV | NETIF_MSG_LINK;
97bde5c4 380 self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN;
8fcb98f4 381 self->ndev->max_mtu = aq_hw_caps->mtu - ETH_FCS_LEN - ETH_HLEN;
97bde5c4 382
97bde5c4
DV
383}
384
385void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
386 struct aq_ring_s *ring)
387{
388 self->aq_ring_tx[idx] = ring;
389}
390
97bde5c4
DV
391struct net_device *aq_nic_get_ndev(struct aq_nic_s *self)
392{
393 return self->ndev;
394}
395
396int aq_nic_init(struct aq_nic_s *self)
397{
398 struct aq_vec_s *aq_vec = NULL;
97bde5c4 399 unsigned int i = 0U;
7b0c342f 400 int err = 0;
97bde5c4
DV
401
402 self->power_state = AQ_HW_POWER_STATE_D0;
f5dce08a 403 mutex_lock(&self->fwreq_mutex);
8fcb98f4 404 err = self->aq_hw_ops->hw_reset(self->aq_hw);
f5dce08a 405 mutex_unlock(&self->fwreq_mutex);
97bde5c4
DV
406 if (err < 0)
407 goto err_exit;
e193c3ab
IR
408 /* Restore default settings */
409 aq_nic_set_downshift(self, self->aq_nic_cfg.downshift_counter);
60db5e40
IR
410 aq_nic_set_media_detect(self, self->aq_nic_cfg.is_media_detect ?
411 AQ_HW_MEDIA_DETECT_CNT : 0);
97bde5c4 412
8fcb98f4 413 err = self->aq_hw_ops->hw_init(self->aq_hw,
23ee07ad 414 aq_nic_get_ndev(self)->dev_addr);
97bde5c4
DV
415 if (err < 0)
416 goto err_exit;
417
e54dcf4b
IR
418 if (ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ATLANTIC) &&
419 self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_TP) {
dbcd6806
DB
420 self->aq_hw->phy_id = HW_ATL_PHY_ID_MAX;
421 err = aq_phy_init(self->aq_hw);
23e500e8
ND
422
423 /* Disable the PTP on NICs where it's known to cause datapath
424 * problems.
425 * Ideally this should have been done by PHY provisioning, but
426 * many units have been shipped with enabled PTP block already.
427 */
428 if (self->aq_nic_cfg.aq_hw_caps->quirks & AQ_NIC_QUIRK_BAD_PTP)
429 if (self->aq_hw->phy_id != HW_ATL_PHY_ID_MAX)
430 aq_phy_disable_ptp(self->aq_hw);
dbcd6806
DB
431 }
432
8ce84271
DB
433 for (i = 0U; i < self->aq_vecs; i++) {
434 aq_vec = self->aq_vec[i];
435 err = aq_vec_ring_alloc(aq_vec, self, i,
436 aq_nic_get_cfg(self));
437 if (err)
438 goto err_exit;
439
8fcb98f4 440 aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw);
8ce84271 441 }
97bde5c4 442
0aa7bc3e
DB
443 if (aq_nic_get_cfg(self)->is_ptp) {
444 err = aq_ptp_init(self, self->irqvecs - 1);
445 if (err < 0)
446 goto err_exit;
1a64f8dc 447
0aa7bc3e
DB
448 err = aq_ptp_ring_alloc(self);
449 if (err < 0)
450 goto err_exit;
94ad9455 451
0aa7bc3e
DB
452 err = aq_ptp_ring_init(self);
453 if (err < 0)
454 goto err_exit;
455 }
94ad9455 456
23ee07ad
IR
457 netif_carrier_off(self->ndev);
458
97bde5c4
DV
459err_exit:
460 return err;
461}
462
97bde5c4
DV
463int aq_nic_start(struct aq_nic_s *self)
464{
465 struct aq_vec_s *aq_vec = NULL;
8ce84271 466 struct aq_nic_cfg_s *cfg;
97bde5c4 467 unsigned int i = 0U;
7b0c342f 468 int err = 0;
97bde5c4 469
8ce84271
DB
470 cfg = aq_nic_get_cfg(self);
471
8fcb98f4 472 err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw,
e9157848
ND
473 self->mc_list.ar,
474 self->mc_list.count);
97bde5c4
DV
475 if (err < 0)
476 goto err_exit;
477
8fcb98f4 478 err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw,
e9157848 479 self->packet_filter);
97bde5c4
DV
480 if (err < 0)
481 goto err_exit;
482
483 for (i = 0U, aq_vec = self->aq_vec[0];
484 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
485 err = aq_vec_start(aq_vec);
486 if (err < 0)
487 goto err_exit;
488 }
489
94ad9455
EP
490 err = aq_ptp_ring_start(self);
491 if (err < 0)
492 goto err_exit;
493
883daa18
IR
494 aq_nic_set_loopback(self);
495
8fcb98f4 496 err = self->aq_hw_ops->hw_start(self->aq_hw);
97bde5c4
DV
497 if (err < 0)
498 goto err_exit;
499
b82ee71a
IR
500 err = aq_nic_update_interrupt_moderation_settings(self);
501 if (err)
97bde5c4 502 goto err_exit;
49544935
IR
503
504 INIT_WORK(&self->service_task, aq_nic_service_task);
505
e99e88a9 506 timer_setup(&self->service_timer, aq_nic_service_timer_cb, 0);
67758788 507 aq_nic_service_timer_cb(&self->service_timer);
97bde5c4 508
8ce84271 509 if (cfg->is_polling) {
e99e88a9 510 timer_setup(&self->polling_timer, aq_nic_polling_timer_cb, 0);
97bde5c4
DV
511 mod_timer(&self->polling_timer, jiffies +
512 AQ_CFG_POLLING_TIMER_INTERVAL);
513 } else {
514 for (i = 0U, aq_vec = self->aq_vec[0];
515 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
4c83f170
IR
516 err = aq_pci_func_alloc_irq(self, i, self->ndev->name,
517 aq_vec_isr, aq_vec,
23ee07ad 518 aq_vec_get_affinity_mask(aq_vec));
97bde5c4
DV
519 if (err < 0)
520 goto err_exit;
521 }
522
04a18399
EP
523 err = aq_ptp_irq_alloc(self);
524 if (err < 0)
525 goto err_exit;
526
8ce84271 527 if (cfg->link_irq_vec) {
4c83f170 528 int irqvec = pci_irq_vector(self->pdev,
8ce84271 529 cfg->link_irq_vec);
4c83f170
IR
530 err = request_threaded_irq(irqvec, NULL,
531 aq_linkstate_threaded_isr,
5c47e3ba 532 IRQF_SHARED | IRQF_ONESHOT,
4c83f170
IR
533 self->ndev->name, self);
534 if (err < 0)
535 goto err_exit;
8ce84271 536 self->msix_entry_mask |= (1 << cfg->link_irq_vec);
4c83f170
IR
537 }
538
8fcb98f4 539 err = self->aq_hw_ops->hw_irq_enable(self->aq_hw,
e9157848 540 AQ_CFG_IRQ_MASK);
97bde5c4
DV
541 if (err < 0)
542 goto err_exit;
543 }
544
a83fe6b6
DB
545 err = netif_set_real_num_tx_queues(self->ndev,
546 self->aq_vecs * cfg->tcs);
97bde5c4
DV
547 if (err < 0)
548 goto err_exit;
549
a83fe6b6
DB
550 err = netif_set_real_num_rx_queues(self->ndev,
551 self->aq_vecs * cfg->tcs);
97bde5c4
DV
552 if (err < 0)
553 goto err_exit;
554
a83fe6b6
DB
555 for (i = 0; i < cfg->tcs; i++) {
556 u16 offset = self->aq_vecs * i;
557
558 netdev_set_tc_queue(self->ndev, i, self->aq_vecs, offset);
559 }
3aec6412
IR
560 netif_tx_start_all_queues(self->ndev);
561
97bde5c4
DV
562err_exit:
563 return err;
564}
565
04a18399
EP
566unsigned int aq_nic_map_skb(struct aq_nic_s *self, struct sk_buff *skb,
567 struct aq_ring_s *ring)
97bde5c4 568{
97bde5c4 569 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
8ce84271
DB
570 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self);
571 struct device *dev = aq_nic_get_dev(self);
c7545689 572 struct aq_ring_buff_s *first = NULL;
822cd114 573 u8 ipver = ip_hdr(skb)->version;
7b0c342f 574 struct aq_ring_buff_s *dx_buff;
880b3ca5 575 bool need_context_tag = false;
7b0c342f
ND
576 unsigned int frag_count = 0U;
577 unsigned int ret = 0U;
578 unsigned int dx;
822cd114
IR
579 u8 l4proto = 0;
580
581 if (ipver == 4)
582 l4proto = ip_hdr(skb)->protocol;
583 else if (ipver == 6)
584 l4proto = ipv6_hdr(skb)->nexthdr;
880b3ca5 585
7b0c342f
ND
586 dx = ring->sw_tail;
587 dx_buff = &ring->buff_ring[dx];
880b3ca5 588 dx_buff->flags = 0U;
97bde5c4 589
e399553d 590 if (unlikely(skb_is_gso(skb))) {
880b3ca5 591 dx_buff->mss = skb_shinfo(skb)->gso_size;
822cd114
IR
592 if (l4proto == IPPROTO_TCP) {
593 dx_buff->is_gso_tcp = 1U;
594 dx_buff->len_l4 = tcp_hdrlen(skb);
595 } else if (l4proto == IPPROTO_UDP) {
596 dx_buff->is_gso_udp = 1U;
597 dx_buff->len_l4 = sizeof(struct udphdr);
598 /* UDP GSO Hardware does not replace packet length. */
599 udp_hdr(skb)->len = htons(dx_buff->mss +
600 dx_buff->len_l4);
601 } else {
602 WARN_ONCE(true, "Bad GSO mode");
603 goto exit;
604 }
e399553d
PB
605 dx_buff->len_pkt = skb->len;
606 dx_buff->len_l2 = ETH_HLEN;
822cd114 607 dx_buff->len_l3 = skb_network_header_len(skb);
c7545689 608 dx_buff->eop_index = 0xffffU;
822cd114 609 dx_buff->is_ipv6 = (ipver == 6);
880b3ca5
IR
610 need_context_tag = true;
611 }
386aff88 612
8ce84271 613 if (cfg->is_vlan_tx_insert && skb_vlan_tag_present(skb)) {
880b3ca5
IR
614 dx_buff->vlan_tx_tag = skb_vlan_tag_get(skb);
615 dx_buff->len_pkt = skb->len;
616 dx_buff->is_vlan = 1U;
617 need_context_tag = true;
618 }
619
620 if (need_context_tag) {
e399553d
PB
621 dx = aq_ring_next_dx(ring, dx);
622 dx_buff = &ring->buff_ring[dx];
880b3ca5 623 dx_buff->flags = 0U;
e399553d
PB
624 ++ret;
625 }
626
e399553d 627 dx_buff->len = skb_headlen(skb);
8ce84271 628 dx_buff->pa = dma_map_single(dev,
e399553d
PB
629 skb->data,
630 dx_buff->len,
631 DMA_TO_DEVICE);
97bde5c4 632
8ce84271 633 if (unlikely(dma_mapping_error(dev, dx_buff->pa))) {
380ec5b9 634 ret = 0;
e399553d 635 goto exit;
380ec5b9 636 }
e399553d 637
c7545689 638 first = dx_buff;
e399553d
PB
639 dx_buff->len_pkt = skb->len;
640 dx_buff->is_sop = 1U;
641 dx_buff->is_mapped = 1U;
97bde5c4
DV
642 ++ret;
643
644 if (skb->ip_summed == CHECKSUM_PARTIAL) {
822cd114
IR
645 dx_buff->is_ip_cso = (htons(ETH_P_IP) == skb->protocol);
646 dx_buff->is_tcp_cso = (l4proto == IPPROTO_TCP);
647 dx_buff->is_udp_cso = (l4proto == IPPROTO_UDP);
97bde5c4
DV
648 }
649
650 for (; nr_frags--; ++frag_count) {
e399553d 651 unsigned int frag_len = 0U;
c7545689
PB
652 unsigned int buff_offset = 0U;
653 unsigned int buff_size = 0U;
97bde5c4
DV
654 dma_addr_t frag_pa;
655 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_count];
656
657 frag_len = skb_frag_size(frag);
97bde5c4 658
c7545689
PB
659 while (frag_len) {
660 if (frag_len > AQ_CFG_TX_FRAME_MAX)
661 buff_size = AQ_CFG_TX_FRAME_MAX;
662 else
663 buff_size = frag_len;
664
8ce84271 665 frag_pa = skb_frag_dma_map(dev,
c7545689
PB
666 frag,
667 buff_offset,
668 buff_size,
669 DMA_TO_DEVICE);
670
8ce84271 671 if (unlikely(dma_mapping_error(dev,
c7545689
PB
672 frag_pa)))
673 goto mapping_error;
e399553d 674
e399553d
PB
675 dx = aq_ring_next_dx(ring, dx);
676 dx_buff = &ring->buff_ring[dx];
677
678 dx_buff->flags = 0U;
c7545689 679 dx_buff->len = buff_size;
e399553d
PB
680 dx_buff->pa = frag_pa;
681 dx_buff->is_mapped = 1U;
c7545689
PB
682 dx_buff->eop_index = 0xffffU;
683
684 frag_len -= buff_size;
685 buff_offset += buff_size;
97bde5c4 686
e399553d 687 ++ret;
97bde5c4 688 }
97bde5c4
DV
689 }
690
c7545689 691 first->eop_index = dx;
e399553d
PB
692 dx_buff->is_eop = 1U;
693 dx_buff->skb = skb;
694 goto exit;
695
696mapping_error:
697 for (dx = ring->sw_tail;
698 ret > 0;
699 --ret, dx = aq_ring_next_dx(ring, dx)) {
700 dx_buff = &ring->buff_ring[dx];
701
822cd114
IR
702 if (!(dx_buff->is_gso_tcp || dx_buff->is_gso_udp) &&
703 !dx_buff->is_vlan && dx_buff->pa) {
e399553d 704 if (unlikely(dx_buff->is_sop)) {
8ce84271 705 dma_unmap_single(dev,
e399553d
PB
706 dx_buff->pa,
707 dx_buff->len,
708 DMA_TO_DEVICE);
709 } else {
8ce84271 710 dma_unmap_page(dev,
e399553d
PB
711 dx_buff->pa,
712 dx_buff->len,
713 DMA_TO_DEVICE);
714 }
715 }
97bde5c4
DV
716 }
717
e399553d 718exit:
97bde5c4
DV
719 return ret;
720}
721
722int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb)
97bde5c4 723{
b9e98926
MS
724 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self);
725 unsigned int vec = skb->queue_mapping % cfg->vecs;
726 unsigned int tc = skb->queue_mapping / cfg->vecs;
97bde5c4
DV
727 struct aq_ring_s *ring = NULL;
728 unsigned int frags = 0U;
b350d7b8 729 int err = NETDEV_TX_OK;
97bde5c4
DV
730
731 frags = skb_shinfo(skb)->nr_frags + 1;
732
b9e98926 733 ring = self->aq_ring_tx[AQ_NIC_CFG_TCVEC2RING(cfg, tc, vec)];
97bde5c4 734
97bde5c4
DV
735 if (frags > AQ_CFG_SKB_FRAGS_MAX) {
736 dev_kfree_skb_any(skb);
737 goto err_exit;
738 }
739
3aec6412 740 aq_ring_update_queue_state(ring);
97bde5c4 741
b9e98926 742 if (cfg->priv_flags & BIT(AQ_HW_LOOPBACK_DMA_NET)) {
ea4b4d7f
IR
743 err = NETDEV_TX_BUSY;
744 goto err_exit;
745 }
746
3aec6412 747 /* Above status update may stop the queue. Check this. */
a83fe6b6
DB
748 if (__netif_subqueue_stopped(self->ndev,
749 AQ_NIC_RING2QMAP(self, ring->idx))) {
97bde5c4
DV
750 err = NETDEV_TX_BUSY;
751 goto err_exit;
752 }
753
278175ab 754 frags = aq_nic_map_skb(self, skb, ring);
97bde5c4 755
278175ab 756 if (likely(frags)) {
8fcb98f4 757 err = self->aq_hw_ops->hw_ring_tx_xmit(self->aq_hw,
23ee07ad 758 ring, frags);
278175ab 759 } else {
97bde5c4 760 err = NETDEV_TX_BUSY;
97bde5c4
DV
761 }
762
763err_exit:
97bde5c4
DV
764 return err;
765}
766
b82ee71a
IR
767int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self)
768{
8fcb98f4 769 return self->aq_hw_ops->hw_interrupt_moderation_set(self->aq_hw);
b82ee71a
IR
770}
771
97bde5c4
DV
772int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags)
773{
774 int err = 0;
775
8fcb98f4 776 err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, flags);
97bde5c4
DV
777 if (err < 0)
778 goto err_exit;
779
780 self->packet_filter = flags;
781
782err_exit:
783 return err;
784}
785
786int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
787{
9f051db5
DB
788 const struct aq_hw_ops *hw_ops = self->aq_hw_ops;
789 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
790 unsigned int packet_filter = ndev->flags;
97bde5c4
DV
791 struct netdev_hw_addr *ha = NULL;
792 unsigned int i = 0U;
9f051db5 793 int err = 0;
97bde5c4 794
94b3b542
IR
795 self->mc_list.count = 0;
796 if (netdev_uc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
797 packet_filter |= IFF_PROMISC;
798 } else {
799 netdev_for_each_uc_addr(ha, ndev) {
800 ether_addr_copy(self->mc_list.ar[i++], ha->addr);
94b3b542 801 }
97bde5c4
DV
802 }
803
9f051db5
DB
804 cfg->is_mc_list_enabled = !!(packet_filter & IFF_MULTICAST);
805 if (cfg->is_mc_list_enabled) {
806 if (i + netdev_mc_count(ndev) > AQ_HW_MULTICAST_ADDRESS_MAX) {
807 packet_filter |= IFF_ALLMULTI;
808 } else {
809 netdev_for_each_mc_addr(ha, ndev) {
810 ether_addr_copy(self->mc_list.ar[i++],
811 ha->addr);
812 }
94b3b542
IR
813 }
814 }
815
bfaa9f85 816 if (i > 0 && i <= AQ_HW_MULTICAST_ADDRESS_MAX) {
94b3b542 817 self->mc_list.count = i;
9f051db5
DB
818 err = hw_ops->hw_multicast_list_set(self->aq_hw,
819 self->mc_list.ar,
820 self->mc_list.count);
3d00cf2f
C
821 if (err < 0)
822 return err;
b21f502f 823 }
7b0c342f 824
94b3b542 825 return aq_nic_set_packet_filter(self, packet_filter);
97bde5c4
DV
826}
827
828int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu)
829{
97bde5c4
DV
830 self->aq_nic_cfg.mtu = new_mtu;
831
d85fc17b 832 return 0;
97bde5c4
DV
833}
834
835int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev)
836{
8fcb98f4 837 return self->aq_hw_ops->hw_set_mac_address(self->aq_hw, ndev->dev_addr);
97bde5c4
DV
838}
839
840unsigned int aq_nic_get_link_speed(struct aq_nic_s *self)
841{
842 return self->link_status.mbps;
843}
844
845int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p)
846{
847 u32 *regs_buff = p;
848 int err = 0;
849
d0f23741
MS
850 if (unlikely(!self->aq_hw_ops->hw_get_regs))
851 return -EOPNOTSUPP;
852
97bde5c4
DV
853 regs->version = 1;
854
8fcb98f4
IR
855 err = self->aq_hw_ops->hw_get_regs(self->aq_hw,
856 self->aq_nic_cfg.aq_hw_caps,
857 regs_buff);
97bde5c4
DV
858 if (err < 0)
859 goto err_exit;
860
861err_exit:
862 return err;
863}
864
865int aq_nic_get_regs_count(struct aq_nic_s *self)
866{
d0f23741
MS
867 if (unlikely(!self->aq_hw_ops->hw_get_regs))
868 return 0;
869
8fcb98f4 870 return self->aq_nic_cfg.aq_hw_caps->mac_regs_count;
97bde5c4
DV
871}
872
aec0f1aa 873u64 *aq_nic_get_stats(struct aq_nic_s *self, u64 *data)
97bde5c4 874{
be08d839 875 struct aq_vec_s *aq_vec = NULL;
190f3438 876 struct aq_stats_s *stats;
7b0c342f
ND
877 unsigned int count = 0U;
878 unsigned int i = 0U;
4272ba8b 879 unsigned int tc;
190f3438
DB
880
881 if (self->aq_fw_ops->update_stats) {
882 mutex_lock(&self->fwreq_mutex);
883 self->aq_fw_ops->update_stats(self->aq_hw);
884 mutex_unlock(&self->fwreq_mutex);
885 }
886 stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
97bde5c4 887
be08d839 888 if (!stats)
97bde5c4
DV
889 goto err_exit;
890
be08d839
IR
891 data[i] = stats->uprc + stats->mprc + stats->bprc;
892 data[++i] = stats->uprc;
893 data[++i] = stats->mprc;
894 data[++i] = stats->bprc;
895 data[++i] = stats->erpt;
896 data[++i] = stats->uptc + stats->mptc + stats->bptc;
897 data[++i] = stats->uptc;
898 data[++i] = stats->mptc;
899 data[++i] = stats->bptc;
900 data[++i] = stats->ubrc;
901 data[++i] = stats->ubtc;
902 data[++i] = stats->mbrc;
903 data[++i] = stats->mbtc;
904 data[++i] = stats->bbrc;
905 data[++i] = stats->bbtc;
e1dcef44
DB
906 if (stats->brc)
907 data[++i] = stats->brc;
908 else
909 data[++i] = stats->ubrc + stats->mbrc + stats->bbrc;
910 if (stats->btc)
911 data[++i] = stats->btc;
912 else
913 data[++i] = stats->ubtc + stats->mbtc + stats->bbtc;
be08d839
IR
914 data[++i] = stats->dma_pkt_rc;
915 data[++i] = stats->dma_pkt_tc;
916 data[++i] = stats->dma_oct_rc;
917 data[++i] = stats->dma_oct_tc;
918 data[++i] = stats->dpc;
919
920 i++;
921
922 data += i;
97bde5c4 923
4272ba8b
MS
924 for (tc = 0U; tc < self->aq_nic_cfg.tcs; tc++) {
925 for (i = 0U, aq_vec = self->aq_vec[0];
926 aq_vec && self->aq_vecs > i;
927 ++i, aq_vec = self->aq_vec[i]) {
928 data += count;
b772112c 929 count = aq_vec_get_sw_stats(aq_vec, tc, data);
4272ba8b 930 }
97bde5c4
DV
931 }
932
aec0f1aa
DB
933 data += count;
934
b772112c 935err_exit:
aec0f1aa 936 return data;
97bde5c4
DV
937}
938
9f8a2203
IR
939static void aq_nic_update_ndev_stats(struct aq_nic_s *self)
940{
8fcb98f4 941 struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
7b0c342f 942 struct net_device *ndev = self->ndev;
9f8a2203 943
f55d477b
DB
944 ndev->stats.rx_packets = stats->dma_pkt_rc;
945 ndev->stats.rx_bytes = stats->dma_oct_rc;
9f8a2203 946 ndev->stats.rx_errors = stats->erpr;
f55d477b
DB
947 ndev->stats.rx_dropped = stats->dpc;
948 ndev->stats.tx_packets = stats->dma_pkt_tc;
949 ndev->stats.tx_bytes = stats->dma_oct_tc;
9f8a2203 950 ndev->stats.tx_errors = stats->erpt;
45cc1c7a 951 ndev->stats.multicast = stats->mprc;
9f8a2203
IR
952}
953
f8244ab5
PR
954void aq_nic_get_link_ksettings(struct aq_nic_s *self,
955 struct ethtool_link_ksettings *cmd)
97bde5c4 956{
2b53b04d
DB
957 u32 lp_link_speed_msk;
958
854ab38c
IR
959 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
960 cmd->base.port = PORT_FIBRE;
961 else
962 cmd->base.port = PORT_TP;
071a0204
IR
963
964 cmd->base.duplex = DUPLEX_UNKNOWN;
965 if (self->link_status.mbps)
966 cmd->base.duplex = self->link_status.full_duplex ?
967 DUPLEX_FULL : DUPLEX_HALF;
f8244ab5
PR
968 cmd->base.autoneg = self->aq_nic_cfg.is_autoneg;
969
8f9000a5
PB
970 ethtool_link_ksettings_zero_link_mode(cmd, supported);
971
8fcb98f4 972 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10G)
8f9000a5
PB
973 ethtool_link_ksettings_add_link_mode(cmd, supported,
974 10000baseT_Full);
975
8fcb98f4 976 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_5G)
8f9000a5
PB
977 ethtool_link_ksettings_add_link_mode(cmd, supported,
978 5000baseT_Full);
979
843e1396 980 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2G5)
8f9000a5
PB
981 ethtool_link_ksettings_add_link_mode(cmd, supported,
982 2500baseT_Full);
983
8fcb98f4 984 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_1G)
8f9000a5
PB
985 ethtool_link_ksettings_add_link_mode(cmd, supported,
986 1000baseT_Full);
987
071a0204
IR
988 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_1G_HALF)
989 ethtool_link_ksettings_add_link_mode(cmd, supported,
990 1000baseT_Half);
991
8fcb98f4 992 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_100M)
8f9000a5
PB
993 ethtool_link_ksettings_add_link_mode(cmd, supported,
994 100baseT_Full);
995
071a0204
IR
996 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_100M_HALF)
997 ethtool_link_ksettings_add_link_mode(cmd, supported,
998 100baseT_Half);
999
3d464aad
IR
1000 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10M)
1001 ethtool_link_ksettings_add_link_mode(cmd, supported,
1002 10baseT_Full);
1003
071a0204
IR
1004 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10M_HALF)
1005 ethtool_link_ksettings_add_link_mode(cmd, supported,
1006 10baseT_Half);
1007
8009bb19 1008 if (self->aq_nic_cfg.aq_hw_caps->flow_control) {
8f9000a5
PB
1009 ethtool_link_ksettings_add_link_mode(cmd, supported,
1010 Pause);
8009bb19
ND
1011 ethtool_link_ksettings_add_link_mode(cmd, supported,
1012 Asym_Pause);
1013 }
8f9000a5
PB
1014
1015 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
854ab38c
IR
1016
1017 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
1018 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1019 else
1020 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
8f9000a5
PB
1021
1022 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
1023
1024 if (self->aq_nic_cfg.is_autoneg)
1025 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
1026
071a0204 1027 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10G)
8f9000a5
PB
1028 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1029 10000baseT_Full);
1030
071a0204 1031 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_5G)
8f9000a5
PB
1032 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1033 5000baseT_Full);
1034
071a0204 1035 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_2G5)
8f9000a5
PB
1036 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1037 2500baseT_Full);
1038
071a0204 1039 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G)
8f9000a5
PB
1040 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1041 1000baseT_Full);
1042
071a0204
IR
1043 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_1G_HALF)
1044 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1045 1000baseT_Half);
1046
1047 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M)
8f9000a5
PB
1048 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1049 100baseT_Full);
1050
071a0204
IR
1051 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_100M_HALF)
1052 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1053 100baseT_Half);
1054
1055 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10M)
3d464aad
IR
1056 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1057 10baseT_Full);
1058
071a0204
IR
1059 if (self->aq_nic_cfg.link_speed_msk & AQ_NIC_RATE_10M_HALF)
1060 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1061 10baseT_Half);
1062
8009bb19 1063 if (self->aq_nic_cfg.fc.cur & AQ_NIC_FC_RX)
8f9000a5
PB
1064 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1065 Pause);
1066
35e8e8b4 1067 /* Asym is when either RX or TX, but not both */
8009bb19
ND
1068 if (!!(self->aq_nic_cfg.fc.cur & AQ_NIC_FC_TX) ^
1069 !!(self->aq_nic_cfg.fc.cur & AQ_NIC_FC_RX))
288551de
IR
1070 ethtool_link_ksettings_add_link_mode(cmd, advertising,
1071 Asym_Pause);
1072
854ab38c
IR
1073 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
1074 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
1075 else
1076 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
2b53b04d
DB
1077
1078 ethtool_link_ksettings_zero_link_mode(cmd, lp_advertising);
1079 lp_link_speed_msk = self->aq_hw->aq_link_status.lp_link_speed_msk;
1080
1081 if (lp_link_speed_msk & AQ_NIC_RATE_10G)
1082 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1083 10000baseT_Full);
1084
1085 if (lp_link_speed_msk & AQ_NIC_RATE_5G)
1086 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1087 5000baseT_Full);
1088
1089 if (lp_link_speed_msk & AQ_NIC_RATE_2G5)
1090 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1091 2500baseT_Full);
1092
1093 if (lp_link_speed_msk & AQ_NIC_RATE_1G)
1094 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1095 1000baseT_Full);
1096
1097 if (lp_link_speed_msk & AQ_NIC_RATE_1G_HALF)
1098 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1099 1000baseT_Half);
1100
1101 if (lp_link_speed_msk & AQ_NIC_RATE_100M)
1102 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1103 100baseT_Full);
1104
1105 if (lp_link_speed_msk & AQ_NIC_RATE_100M_HALF)
1106 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1107 100baseT_Half);
1108
1109 if (lp_link_speed_msk & AQ_NIC_RATE_10M)
1110 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1111 10baseT_Full);
1112
1113 if (lp_link_speed_msk & AQ_NIC_RATE_10M_HALF)
1114 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1115 10baseT_Half);
1116
1117 if (self->aq_hw->aq_link_status.lp_flow_control & AQ_NIC_FC_RX)
1118 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1119 Pause);
1120 if (!!(self->aq_hw->aq_link_status.lp_flow_control & AQ_NIC_FC_TX) ^
1121 !!(self->aq_hw->aq_link_status.lp_flow_control & AQ_NIC_FC_RX))
1122 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising,
1123 Asym_Pause);
97bde5c4
DV
1124}
1125
f8244ab5
PR
1126int aq_nic_set_link_ksettings(struct aq_nic_s *self,
1127 const struct ethtool_link_ksettings *cmd)
97bde5c4 1128{
071a0204
IR
1129 int fduplex = (cmd->base.duplex == DUPLEX_FULL);
1130 u32 speed = cmd->base.speed;
97bde5c4
DV
1131 u32 rate = 0U;
1132 int err = 0;
1133
071a0204
IR
1134 if (!fduplex && speed > SPEED_1000) {
1135 err = -EINVAL;
1136 goto err_exit;
1137 }
1138
f8244ab5 1139 if (cmd->base.autoneg == AUTONEG_ENABLE) {
8fcb98f4 1140 rate = self->aq_nic_cfg.aq_hw_caps->link_speed_msk;
97bde5c4
DV
1141 self->aq_nic_cfg.is_autoneg = true;
1142 } else {
97bde5c4 1143 switch (speed) {
3d464aad 1144 case SPEED_10:
071a0204 1145 rate = fduplex ? AQ_NIC_RATE_10M : AQ_NIC_RATE_10M_HALF;
3d464aad
IR
1146 break;
1147
97bde5c4 1148 case SPEED_100:
071a0204
IR
1149 rate = fduplex ? AQ_NIC_RATE_100M
1150 : AQ_NIC_RATE_100M_HALF;
97bde5c4
DV
1151 break;
1152
1153 case SPEED_1000:
071a0204 1154 rate = fduplex ? AQ_NIC_RATE_1G : AQ_NIC_RATE_1G_HALF;
97bde5c4
DV
1155 break;
1156
1157 case SPEED_2500:
843e1396 1158 rate = AQ_NIC_RATE_2G5;
97bde5c4
DV
1159 break;
1160
1161 case SPEED_5000:
1162 rate = AQ_NIC_RATE_5G;
1163 break;
1164
1165 case SPEED_10000:
1166 rate = AQ_NIC_RATE_10G;
1167 break;
1168
1169 default:
1170 err = -1;
1171 goto err_exit;
97bde5c4 1172 }
8fcb98f4 1173 if (!(self->aq_nic_cfg.aq_hw_caps->link_speed_msk & rate)) {
97bde5c4
DV
1174 err = -1;
1175 goto err_exit;
1176 }
1177
1178 self->aq_nic_cfg.is_autoneg = false;
1179 }
1180
f5dce08a 1181 mutex_lock(&self->fwreq_mutex);
0c58c35f 1182 err = self->aq_fw_ops->set_link_speed(self->aq_hw, rate);
f5dce08a 1183 mutex_unlock(&self->fwreq_mutex);
97bde5c4
DV
1184 if (err < 0)
1185 goto err_exit;
1186
1187 self->aq_nic_cfg.link_speed_msk = rate;
1188
1189err_exit:
1190 return err;
1191}
1192
1193struct aq_nic_cfg_s *aq_nic_get_cfg(struct aq_nic_s *self)
1194{
1195 return &self->aq_nic_cfg;
1196}
1197
1198u32 aq_nic_get_fw_version(struct aq_nic_s *self)
1199{
36e90a52 1200 return self->aq_hw_ops->hw_get_fw_version(self->aq_hw);
97bde5c4
DV
1201}
1202
ea4b4d7f
IR
1203int aq_nic_set_loopback(struct aq_nic_s *self)
1204{
1205 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
1206
1207 if (!self->aq_hw_ops->hw_set_loopback ||
1208 !self->aq_fw_ops->set_phyloopback)
e35df218 1209 return -EOPNOTSUPP;
ea4b4d7f
IR
1210
1211 mutex_lock(&self->fwreq_mutex);
1212 self->aq_hw_ops->hw_set_loopback(self->aq_hw,
1213 AQ_HW_LOOPBACK_DMA_SYS,
1214 !!(cfg->priv_flags &
1215 BIT(AQ_HW_LOOPBACK_DMA_SYS)));
1216
1217 self->aq_hw_ops->hw_set_loopback(self->aq_hw,
1218 AQ_HW_LOOPBACK_PKT_SYS,
1219 !!(cfg->priv_flags &
1220 BIT(AQ_HW_LOOPBACK_PKT_SYS)));
1221
1222 self->aq_hw_ops->hw_set_loopback(self->aq_hw,
1223 AQ_HW_LOOPBACK_DMA_NET,
1224 !!(cfg->priv_flags &
1225 BIT(AQ_HW_LOOPBACK_DMA_NET)));
1226
1227 self->aq_fw_ops->set_phyloopback(self->aq_hw,
1228 AQ_HW_LOOPBACK_PHYINT_SYS,
1229 !!(cfg->priv_flags &
1230 BIT(AQ_HW_LOOPBACK_PHYINT_SYS)));
1231
1232 self->aq_fw_ops->set_phyloopback(self->aq_hw,
1233 AQ_HW_LOOPBACK_PHYEXT_SYS,
1234 !!(cfg->priv_flags &
1235 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)));
1236 mutex_unlock(&self->fwreq_mutex);
1237
1238 return 0;
1239}
1240
97bde5c4
DV
1241int aq_nic_stop(struct aq_nic_s *self)
1242{
1243 struct aq_vec_s *aq_vec = NULL;
1244 unsigned int i = 0U;
1245
3aec6412 1246 netif_tx_disable(self->ndev);
93d87b8f 1247 netif_carrier_off(self->ndev);
97bde5c4
DV
1248
1249 del_timer_sync(&self->service_timer);
49544935 1250 cancel_work_sync(&self->service_task);
97bde5c4 1251
8fcb98f4 1252 self->aq_hw_ops->hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK);
97bde5c4
DV
1253
1254 if (self->aq_nic_cfg.is_polling)
1255 del_timer_sync(&self->polling_timer);
1256 else
23ee07ad 1257 aq_pci_func_free_irqs(self);
97bde5c4 1258
04a18399
EP
1259 aq_ptp_irq_free(self);
1260
97bde5c4
DV
1261 for (i = 0U, aq_vec = self->aq_vec[0];
1262 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
1263 aq_vec_stop(aq_vec);
1264
94ad9455
EP
1265 aq_ptp_ring_stop(self);
1266
8fcb98f4 1267 return self->aq_hw_ops->hw_stop(self->aq_hw);
97bde5c4
DV
1268}
1269
837c6378
ND
1270void aq_nic_set_power(struct aq_nic_s *self)
1271{
1272 if (self->power_state != AQ_HW_POWER_STATE_D0 ||
1273 self->aq_hw->aq_nic_cfg->wol)
1274 if (likely(self->aq_fw_ops->set_power)) {
1275 mutex_lock(&self->fwreq_mutex);
1276 self->aq_fw_ops->set_power(self->aq_hw,
1277 self->power_state,
1278 self->ndev->dev_addr);
1279 mutex_unlock(&self->fwreq_mutex);
1280 }
1281}
1282
1283void aq_nic_deinit(struct aq_nic_s *self, bool link_down)
97bde5c4
DV
1284{
1285 struct aq_vec_s *aq_vec = NULL;
1286 unsigned int i = 0U;
1287
1288 if (!self)
1289 goto err_exit;
1290
8ce84271
DB
1291 for (i = 0U; i < self->aq_vecs; i++) {
1292 aq_vec = self->aq_vec[i];
97bde5c4 1293 aq_vec_deinit(aq_vec);
8ce84271
DB
1294 aq_vec_ring_free(aq_vec);
1295 }
97bde5c4 1296
1a64f8dc 1297 aq_ptp_unregister(self);
94ad9455
EP
1298 aq_ptp_ring_deinit(self);
1299 aq_ptp_ring_free(self);
1a64f8dc
EP
1300 aq_ptp_free(self);
1301
837c6378 1302 if (likely(self->aq_fw_ops->deinit) && link_down) {
f5dce08a
ND
1303 mutex_lock(&self->fwreq_mutex);
1304 self->aq_fw_ops->deinit(self->aq_hw);
1305 mutex_unlock(&self->fwreq_mutex);
1306 }
a0da96c0 1307
97bde5c4
DV
1308err_exit:;
1309}
1310
23ee07ad 1311void aq_nic_free_vectors(struct aq_nic_s *self)
97bde5c4
DV
1312{
1313 unsigned int i = 0U;
1314
1315 if (!self)
1316 goto err_exit;
1317
08b5cf08 1318 for (i = ARRAY_SIZE(self->aq_vec); i--;) {
3013c498 1319 if (self->aq_vec[i]) {
97bde5c4 1320 aq_vec_free(self->aq_vec[i]);
3013c498
PB
1321 self->aq_vec[i] = NULL;
1322 }
97bde5c4
DV
1323 }
1324
1325err_exit:;
1326}
1327
14ef766b
MS
1328int aq_nic_realloc_vectors(struct aq_nic_s *self)
1329{
1330 struct aq_nic_cfg_s *cfg = aq_nic_get_cfg(self);
1331
1332 aq_nic_free_vectors(self);
1333
1334 for (self->aq_vecs = 0; self->aq_vecs < cfg->vecs; self->aq_vecs++) {
1335 self->aq_vec[self->aq_vecs] = aq_vec_alloc(self, self->aq_vecs,
1336 cfg);
1337 if (unlikely(!self->aq_vec[self->aq_vecs]))
1338 return -ENOMEM;
1339 }
1340
1341 return 0;
1342}
1343
90869ddf
IR
1344void aq_nic_shutdown(struct aq_nic_s *self)
1345{
1346 int err = 0;
1347
1348 if (!self->ndev)
1349 return;
1350
1351 rtnl_lock();
1352
1353 netif_device_detach(self->ndev);
1354
9a11aff2
IR
1355 if (netif_running(self->ndev)) {
1356 err = aq_nic_stop(self);
1357 if (err < 0)
1358 goto err_exit;
1359 }
837c6378
ND
1360 aq_nic_deinit(self, !self->aq_hw->aq_nic_cfg->wol);
1361 aq_nic_set_power(self);
90869ddf
IR
1362
1363err_exit:
1364 rtnl_unlock();
ea4854dd 1365}
5a1bf9ef
DB
1366
1367u8 aq_nic_reserve_filter(struct aq_nic_s *self, enum aq_rx_filter_type type)
1368{
1369 u8 location = 0xFF;
1370 u32 fltr_cnt;
1371 u32 n_bit;
1372
1373 switch (type) {
1374 case aq_rx_filter_ethertype:
1375 location = AQ_RX_LAST_LOC_FETHERT - AQ_RX_FIRST_LOC_FETHERT -
1376 self->aq_hw_rx_fltrs.fet_reserved_count;
1377 self->aq_hw_rx_fltrs.fet_reserved_count++;
1378 break;
1379 case aq_rx_filter_l3l4:
1380 fltr_cnt = AQ_RX_LAST_LOC_FL3L4 - AQ_RX_FIRST_LOC_FL3L4;
1381 n_bit = fltr_cnt - self->aq_hw_rx_fltrs.fl3l4.reserved_count;
1382
1383 self->aq_hw_rx_fltrs.fl3l4.active_ipv4 |= BIT(n_bit);
1384 self->aq_hw_rx_fltrs.fl3l4.reserved_count++;
1385 location = n_bit;
1386 break;
1387 default:
1388 break;
1389 }
1390
1391 return location;
1392}
1393
1394void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type,
1395 u32 location)
1396{
1397 switch (type) {
1398 case aq_rx_filter_ethertype:
1399 self->aq_hw_rx_fltrs.fet_reserved_count--;
1400 break;
1401 case aq_rx_filter_l3l4:
1402 self->aq_hw_rx_fltrs.fl3l4.reserved_count--;
1403 self->aq_hw_rx_fltrs.fl3l4.active_ipv4 &= ~BIT(location);
1404 break;
1405 default:
1406 break;
1407 }
1408}
a83fe6b6 1409
e193c3ab
IR
1410int aq_nic_set_downshift(struct aq_nic_s *self, int val)
1411{
1412 int err = 0;
1413 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
1414
1415 if (!self->aq_fw_ops->set_downshift)
1416 return -EOPNOTSUPP;
1417
1418 if (val > 15) {
1419 netdev_err(self->ndev, "downshift counter should be <= 15\n");
1420 return -EINVAL;
1421 }
1422 cfg->downshift_counter = val;
1423
1424 mutex_lock(&self->fwreq_mutex);
1425 err = self->aq_fw_ops->set_downshift(self->aq_hw, cfg->downshift_counter);
1426 mutex_unlock(&self->fwreq_mutex);
1427
1428 return err;
1429}
1430
60db5e40
IR
1431int aq_nic_set_media_detect(struct aq_nic_s *self, int val)
1432{
1433 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
1434 int err = 0;
1435
1436 if (!self->aq_fw_ops->set_media_detect)
1437 return -EOPNOTSUPP;
1438
1439 if (val > 0 && val != AQ_HW_MEDIA_DETECT_CNT) {
1440 netdev_err(self->ndev, "EDPD on this device could have only fixed value of %d\n",
1441 AQ_HW_MEDIA_DETECT_CNT);
1442 return -EINVAL;
1443 }
1444
1445 mutex_lock(&self->fwreq_mutex);
1446 err = self->aq_fw_ops->set_media_detect(self->aq_hw, !!val);
1447 mutex_unlock(&self->fwreq_mutex);
1448
1449 /* msecs plays no role - configuration is always fixed in PHY */
1450 if (!err)
1451 cfg->is_media_detect = !!val;
1452
1453 return err;
1454}
1455
a83fe6b6
DB
1456int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map)
1457{
1458 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
14ef766b 1459 const unsigned int prev_vecs = cfg->vecs;
a83fe6b6
DB
1460 bool ndev_running;
1461 int err = 0;
1462 int i;
1463
1464 /* if already the same configuration or
1465 * disable request (tcs is 0) and we already is disabled
1466 */
1467 if (tcs == cfg->tcs || (tcs == 0 && !cfg->is_qos))
1468 return 0;
1469
1470 ndev_running = netif_running(self->ndev);
1471 if (ndev_running)
1472 dev_close(self->ndev);
1473
1474 cfg->tcs = tcs;
1475 if (cfg->tcs == 0)
1476 cfg->tcs = 1;
1477 if (prio_tc_map)
1478 memcpy(cfg->prio_tc_map, prio_tc_map, sizeof(cfg->prio_tc_map));
1479 else
1480 for (i = 0; i < sizeof(cfg->prio_tc_map); i++)
1481 cfg->prio_tc_map[i] = cfg->tcs * i / 8;
1482
3ec94da9 1483 cfg->is_qos = !!tcs;
a83fe6b6
DB
1484 cfg->is_ptp = (cfg->tcs <= AQ_HW_PTP_TC);
1485 if (!cfg->is_ptp)
1486 netdev_warn(self->ndev, "%s\n",
1487 "PTP is auto disabled due to requested TC count.");
1488
1489 netdev_set_num_tc(self->ndev, cfg->tcs);
1490
14ef766b
MS
1491 /* Changing the number of TCs might change the number of vectors */
1492 aq_nic_cfg_update_num_vecs(self);
1493 if (prev_vecs != cfg->vecs) {
1494 err = aq_nic_realloc_vectors(self);
1495 if (err)
1496 goto err_exit;
1497 }
1498
a83fe6b6
DB
1499 if (ndev_running)
1500 err = dev_open(self->ndev, NULL);
1501
14ef766b 1502err_exit:
a83fe6b6
DB
1503 return err;
1504}
7327699f
MS
1505
1506int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
1507 const u32 max_rate)
1508{
1509 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
1510
1511 if (tc >= AQ_CFG_TCS_MAX)
1512 return -EINVAL;
1513
1514 if (max_rate && max_rate < 10) {
1515 netdev_warn(self->ndev,
1516 "Setting %s to the minimum usable value of %dMbps.\n",
1517 "max rate", 10);
1518 cfg->tc_max_rate[tc] = 10;
1519 } else {
1520 cfg->tc_max_rate[tc] = max_rate;
1521 }
1522
1523 return 0;
1524}
2deac71a
MS
1525
1526int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc,
1527 const u32 min_rate)
1528{
1529 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
1530
1531 if (tc >= AQ_CFG_TCS_MAX)
1532 return -EINVAL;
1533
1534 if (min_rate)
1535 set_bit(tc, &cfg->tc_min_rate_msk);
1536 else
1537 clear_bit(tc, &cfg->tc_min_rate_msk);
1538
1539 if (min_rate && min_rate < 20) {
1540 netdev_warn(self->ndev,
1541 "Setting %s to the minimum usable value of %dMbps.\n",
1542 "min rate", 20);
1543 cfg->tc_min_rate[tc] = 20;
1544 } else {
1545 cfg->tc_min_rate[tc] = min_rate;
1546 }
1547
1548 return 0;
1549}