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1 | /* |
2 | * aQuantia Corporation Network Driver | |
3 | * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | /* File aq_ring.h: Declaration of functions for Rx/Tx rings. */ | |
11 | ||
12 | #ifndef AQ_RING_H | |
13 | #define AQ_RING_H | |
14 | ||
15 | #include "aq_common.h" | |
16 | ||
17 | struct page; | |
18 | ||
19 | /* TxC SOP DX EOP | |
20 | * +----------+----------+----------+----------- | |
21 | * 8bytes|len l3,l4 | pa | pa | pa | |
22 | * +----------+----------+----------+----------- | |
23 | * 4/8bytes|len pkt |len pkt | | skb | |
24 | * +----------+----------+----------+----------- | |
25 | * 4/8bytes|is_txc |len,flags |len |len,is_eop | |
26 | * +----------+----------+----------+----------- | |
27 | * | |
28 | * This aq_ring_buff_s doesn't have endianness dependency. | |
29 | * It is __packed for cache line optimizations. | |
30 | */ | |
31 | struct __packed aq_ring_buff_s { | |
32 | union { | |
33 | /* RX */ | |
34 | struct { | |
35 | u32 rss_hash; | |
36 | u16 next; | |
37 | u8 is_hash_l4; | |
38 | u8 rsvd1; | |
39 | struct page *page; | |
40 | }; | |
41 | /* EOP */ | |
42 | struct { | |
43 | dma_addr_t pa_eop; | |
44 | struct sk_buff *skb; | |
45 | }; | |
46 | /* DX */ | |
47 | struct { | |
48 | dma_addr_t pa; | |
49 | }; | |
50 | /* SOP */ | |
51 | struct { | |
52 | dma_addr_t pa_sop; | |
53 | u32 len_pkt_sop; | |
54 | }; | |
55 | /* TxC */ | |
56 | struct { | |
57 | u32 mss; | |
58 | u8 len_l2; | |
59 | u8 len_l3; | |
60 | u8 len_l4; | |
386aff88 PB |
61 | u8 is_ipv6:1; |
62 | u8 rsvd2:7; | |
018423e9 DV |
63 | u32 len_pkt; |
64 | }; | |
65 | }; | |
66 | union { | |
67 | struct { | |
68 | u32 len:16; | |
69 | u32 is_ip_cso:1; | |
70 | u32 is_udp_cso:1; | |
71 | u32 is_tcp_cso:1; | |
72 | u32 is_cso_err:1; | |
73 | u32 is_sop:1; | |
74 | u32 is_eop:1; | |
75 | u32 is_txc:1; | |
76 | u32 is_mapped:1; | |
77 | u32 is_cleaned:1; | |
78 | u32 is_error:1; | |
79 | u32 rsvd3:6; | |
80 | }; | |
81 | u32 flags; | |
82 | }; | |
83 | }; | |
84 | ||
85 | struct aq_ring_stats_rx_s { | |
86 | u64 errors; | |
87 | u64 packets; | |
88 | u64 bytes; | |
89 | u64 lro_packets; | |
90 | u64 jumbo_packets; | |
91 | }; | |
92 | ||
93 | struct aq_ring_stats_tx_s { | |
94 | u64 errors; | |
95 | u64 packets; | |
96 | u64 bytes; | |
97 | }; | |
98 | ||
99 | union aq_ring_stats_s { | |
100 | struct aq_ring_stats_rx_s rx; | |
101 | struct aq_ring_stats_tx_s tx; | |
102 | }; | |
103 | ||
104 | struct aq_ring_s { | |
105 | struct aq_obj_s header; | |
106 | struct aq_ring_buff_s *buff_ring; | |
107 | u8 *dx_ring; /* descriptors ring, dma shared mem */ | |
108 | struct aq_nic_s *aq_nic; | |
109 | unsigned int idx; /* for HW layer registers operations */ | |
110 | unsigned int hw_head; | |
111 | unsigned int sw_head; | |
112 | unsigned int sw_tail; | |
113 | unsigned int size; /* descriptors number */ | |
114 | unsigned int dx_size; /* TX or RX descriptor size, */ | |
115 | /* stored here for fater math */ | |
116 | union aq_ring_stats_s stats; | |
117 | dma_addr_t dx_ring_pa; | |
118 | }; | |
119 | ||
120 | struct aq_ring_param_s { | |
121 | unsigned int vec_idx; | |
122 | unsigned int cpu; | |
123 | cpumask_t affinity_mask; | |
124 | }; | |
125 | ||
126 | static inline unsigned int aq_ring_next_dx(struct aq_ring_s *self, | |
127 | unsigned int dx) | |
128 | { | |
129 | return (++dx >= self->size) ? 0U : dx; | |
130 | } | |
131 | ||
132 | static inline unsigned int aq_ring_avail_dx(struct aq_ring_s *self) | |
133 | { | |
134 | return (((self->sw_tail >= self->sw_head)) ? | |
135 | (self->size - 1) - self->sw_tail + self->sw_head : | |
136 | self->sw_head - self->sw_tail - 1); | |
137 | } | |
138 | ||
139 | struct aq_ring_s *aq_ring_tx_alloc(struct aq_ring_s *self, | |
140 | struct aq_nic_s *aq_nic, | |
141 | unsigned int idx, | |
142 | struct aq_nic_cfg_s *aq_nic_cfg); | |
143 | struct aq_ring_s *aq_ring_rx_alloc(struct aq_ring_s *self, | |
144 | struct aq_nic_s *aq_nic, | |
145 | unsigned int idx, | |
146 | struct aq_nic_cfg_s *aq_nic_cfg); | |
147 | int aq_ring_init(struct aq_ring_s *self); | |
018423e9 DV |
148 | void aq_ring_rx_deinit(struct aq_ring_s *self); |
149 | void aq_ring_free(struct aq_ring_s *self); | |
eb36bedf | 150 | void aq_ring_tx_clean(struct aq_ring_s *self); |
018423e9 DV |
151 | int aq_ring_rx_clean(struct aq_ring_s *self, int *work_done, int budget); |
152 | int aq_ring_rx_fill(struct aq_ring_s *self); | |
153 | ||
154 | #endif /* AQ_RING_H */ |