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net: aquantia: Fix actual speed capabilities reporting
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / aquantia / atlantic / hw_atl / hw_atl_b0.c
CommitLineData
bab6de8f
DV		 1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
11
12#include "../aq_hw.h"
13#include "../aq_hw_utils.h"
14#include "../aq_ring.h"
15#include "hw_atl_b0.h"
16#include "hw_atl_utils.h"
17#include "hw_atl_llh.h"
18#include "hw_atl_b0_internal.h"
19
20static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
e4d02ca0
IR		 21 struct aq_hw_caps_s *aq_hw_caps,
22 unsigned short device,
23 unsigned short subsystem_device)
bab6de8f
DV		 24{
25 memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
e4d02ca0
IR		 26
27 if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001)
28 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
29
30 if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) {
31 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G;
32 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G;
33 }
34
bab6de8f
DV		 35 return 0;
36}
37
38static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
39 unsigned int port,
40 struct aq_hw_ops *ops)
41{
42 struct hw_atl_s *self = NULL;
43
44 self = kzalloc(sizeof(*self), GFP_KERNEL);
45 if (!self)
46 goto err_exit;
47
48 self->base.aq_pci_func = aq_pci_func;
49
50 self->base.not_ff_addr = 0x10U;
51
52err_exit:
53 return (struct aq_hw_s *)self;
54}
55
56static void hw_atl_b0_destroy(struct aq_hw_s *self)
57{
58 kfree(self);
59}
60
61static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
62{
63 int err = 0;
64
65 glb_glb_reg_res_dis_set(self, 1U);
66 pci_pci_reg_res_dis_set(self, 0U);
67 rx_rx_reg_res_dis_set(self, 0U);
68 tx_tx_reg_res_dis_set(self, 0U);
69
70 HW_ATL_FLUSH();
71 glb_soft_res_set(self, 1);
72
73 /* check 10 times by 1ms */
74 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
75 if (err < 0)
76 goto err_exit;
77
78 itr_irq_reg_res_dis_set(self, 0U);
79 itr_res_irq_set(self, 1U);
80
81 /* check 10 times by 1ms */
82 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
83 if (err < 0)
84 goto err_exit;
85
86 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
87
88 err = aq_hw_err_from_flags(self);
89
90err_exit:
91 return err;
92}
93
94static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
95{
96 u32 tc = 0U;
97 u32 buff_size = 0U;
98 unsigned int i_priority = 0U;
99 bool is_rx_flow_control = false;
100
101 /* TPS Descriptor rate init */
102 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
103 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
104
105 /* TPS VM init */
106 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
107
108 /* TPS TC credits init */
109 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
110 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
111
112 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
113 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
114 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
115 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
116
117 /* Tx buf size */
118 buff_size = HW_ATL_B0_TXBUF_MAX;
119
120 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
121 tpb_tx_buff_hi_threshold_per_tc_set(self,
122 (buff_size * (1024 / 32U) * 66U) /
123 100U, tc);
124 tpb_tx_buff_lo_threshold_per_tc_set(self,
125 (buff_size * (1024 / 32U) * 50U) /
126 100U, tc);
127
128 /* QoS Rx buf size per TC */
129 tc = 0;
130 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
131 buff_size = HW_ATL_B0_RXBUF_MAX;
132
133 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
134 rpb_rx_buff_hi_threshold_per_tc_set(self,
135 (buff_size *
136 (1024U / 32U) * 66U) /
137 100U, tc);
138 rpb_rx_buff_lo_threshold_per_tc_set(self,
139 (buff_size *
140 (1024U / 32U) * 50U) /
141 100U, tc);
142 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
143
144 /* QoS 802.1p priority -> TC mapping */
145 for (i_priority = 8U; i_priority--;)
146 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
147
148 return aq_hw_err_from_flags(self);
149}
150
151static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
152 struct aq_rss_parameters *rss_params)
153{
154 struct aq_nic_cfg_s *cfg = NULL;
155 int err = 0;
156 unsigned int i = 0U;
157 unsigned int addr = 0U;
158
159 cfg = self->aq_nic_cfg;
160
161 for (i = 10, addr = 0U; i--; ++addr) {
162 u32 key_data = cfg->is_rss ?
163 __swab32(rss_params->hash_secret_key[i]) : 0U;
164 rpf_rss_key_wr_data_set(self, key_data);
165 rpf_rss_key_addr_set(self, addr);
166 rpf_rss_key_wr_en_set(self, 1U);
167 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
168 if (err < 0)
169 goto err_exit;
170 }
171
172 err = aq_hw_err_from_flags(self);
173
174err_exit:
175 return err;
176}
177
178static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
179 struct aq_rss_parameters *rss_params)
180{
181 u8 *indirection_table = rss_params->indirection_table;
182 u32 i = 0U;
183 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
184 int err = 0;
185 u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
186 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
187
188 memset(bitary, 0, sizeof(bitary));
189
190 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
191 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
192 ((indirection_table[i] % num_rss_queues) <<
193 ((i * 3U) & 0xFU));
194 }
195
196 for (i = AQ_DIMOF(bitary); i--;) {
197 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
198 rpf_rss_redir_tbl_addr_set(self, i);
199 rpf_rss_redir_wr_en_set(self, 1U);
200 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
201 if (err < 0)
202 goto err_exit;
203 }
204
205 err = aq_hw_err_from_flags(self);
206
207err_exit:
208 return err;
209}
210
211static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
212 struct aq_nic_cfg_s *aq_nic_cfg)
213{
bab6de8f
DV		 214 unsigned int i;
215
216 /* TX checksums offloads*/
217 tpo_ipv4header_crc_offload_en_set(self, 1);
218 tpo_tcp_udp_crc_offload_en_set(self, 1);
bab6de8f
DV		 219
220 /* RX checksums offloads*/
221 rpo_ipv4header_crc_offload_en_set(self, 1);
222 rpo_tcp_udp_crc_offload_en_set(self, 1);
bab6de8f
DV		 223
224 /* LSO offloads*/
225 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
bab6de8f
DV		 226
227/* LRO offloads */
228 {
229 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
230 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
231 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
232
233 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
234 rpo_lro_max_num_of_descriptors_set(self, val, i);
235
236 rpo_lro_time_base_divider_set(self, 0x61AU);
237 rpo_lro_inactive_interval_set(self, 0);
238 rpo_lro_max_coalescing_interval_set(self, 2);
239
240 rpo_lro_qsessions_lim_set(self, 1U);
241
242 rpo_lro_total_desc_lim_set(self, 2U);
243
244 rpo_lro_patch_optimization_en_set(self, 0U);
245
246 rpo_lro_min_pay_of_first_pkt_set(self, 10U);
247
248 rpo_lro_pkt_lim_set(self, 1U);
249
250 rpo_lro_en_set(self, aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
251 }
d2be3667 252 return aq_hw_err_from_flags(self);
bab6de8f
DV		 253}
254
255static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
256{
257 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
258 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
259 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
260
261 /* Tx interrupts */
262 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
263
264 /* misc */
265 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
266 0x00010000U : 0x00000000U);
267 tdm_tx_dca_en_set(self, 0U);
268 tdm_tx_dca_mode_set(self, 0U);
269
270 tpb_tx_path_scp_ins_en_set(self, 1U);
271
272 return aq_hw_err_from_flags(self);
273}
274
275static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
276{
277 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
278 int i;
279
280 /* Rx TC/RSS number config */
281 rpb_rpf_rx_traf_class_mode_set(self, 1U);
282
283 /* Rx flow control */
284 rpb_rx_flow_ctl_mode_set(self, 1U);
285
286 /* RSS Ring selection */
287 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
288 0xB3333333U : 0x00000000U);
289
290 /* Multicast filters */
291 for (i = HW_ATL_B0_MAC_MAX; i--;) {
292 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
293 rpfl2unicast_flr_act_set(self, 1U, i);
294 }
295
296 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
297 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
298
299 /* Vlan filters */
300 rpf_vlan_outer_etht_set(self, 0x88A8U);
301 rpf_vlan_inner_etht_set(self, 0x8100U);
302
303 if (cfg->vlan_id) {
304 rpf_vlan_flr_act_set(self, 1U, 0U);
305 rpf_vlan_id_flr_set(self, 0U, 0U);
306 rpf_vlan_flr_en_set(self, 0U, 0U);
307
308 rpf_vlan_accept_untagged_packets_set(self, 1U);
309 rpf_vlan_untagged_act_set(self, 1U);
310
311 rpf_vlan_flr_act_set(self, 1U, 1U);
312 rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
313 rpf_vlan_flr_en_set(self, 1U, 1U);
314 } else {
315 rpf_vlan_prom_mode_en_set(self, 1);
316 }
317
318 /* Rx Interrupts */
319 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
320
321 /* misc */
322 aq_hw_write_reg(self, 0x00005040U,
323 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
324
325 rpfl2broadcast_flr_act_set(self, 1U);
326 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
327
328 rdm_rx_dca_en_set(self, 0U);
329 rdm_rx_dca_mode_set(self, 0U);
330
331 return aq_hw_err_from_flags(self);
332}
333
334static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
335{
336 int err = 0;
337 unsigned int h = 0U;
338 unsigned int l = 0U;
339
340 if (!mac_addr) {
341 err = -EINVAL;
342 goto err_exit;
343 }
344 h = (mac_addr[0] << 8) | (mac_addr[1]);
345 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
346 (mac_addr[4] << 8) | mac_addr[5];
347
348 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
349 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
350 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
351 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
352
353 err = aq_hw_err_from_flags(self);
354
355err_exit:
356 return err;
357}
358
359static int hw_atl_b0_hw_init(struct aq_hw_s *self,
360 struct aq_nic_cfg_s *aq_nic_cfg,
361 u8 *mac_addr)
362{
363 static u32 aq_hw_atl_igcr_table_[4][2] = {
364 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
365 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
366 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
367 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
368 };
369
370 int err = 0;
371
372 self->aq_nic_cfg = aq_nic_cfg;
373
374 hw_atl_utils_hw_chip_features_init(self,
375 &PHAL_ATLANTIC_B0->chip_features);
376
377 hw_atl_b0_hw_init_tx_path(self);
378 hw_atl_b0_hw_init_rx_path(self);
379
380 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
381
382 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
383
384 hw_atl_b0_hw_qos_set(self);
385 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
386 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
387
388 err = aq_hw_err_from_flags(self);
389 if (err < 0)
390 goto err_exit;
391
392 /* Interrupts */
393 reg_irq_glb_ctl_set(self,
394 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
395 [(aq_nic_cfg->vecs > 1U) ?
396 1 : 0]);
397
398 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
399
400 /* Interrupts */
401 reg_gen_irq_map_set(self,
402 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
403 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
404
405 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
406
407err_exit:
408 return err;
409}
410
411static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
412 struct aq_ring_s *ring)
413{
414 tdm_tx_desc_en_set(self, 1, ring->idx);
415 return aq_hw_err_from_flags(self);
416}
417
418static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
419 struct aq_ring_s *ring)
420{
421 rdm_rx_desc_en_set(self, 1, ring->idx);
422 return aq_hw_err_from_flags(self);
423}
424
425static int hw_atl_b0_hw_start(struct aq_hw_s *self)
426{
427 tpb_tx_buff_en_set(self, 1);
428 rpb_rx_buff_en_set(self, 1);
429 return aq_hw_err_from_flags(self);
430}
431
432static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
433 struct aq_ring_s *ring)
434{
435 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
436 return 0;
437}
438
439static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
440 struct aq_ring_s *ring,
441 unsigned int frags)
442{
443 struct aq_ring_buff_s *buff = NULL;
444 struct hw_atl_txd_s *txd = NULL;
445 unsigned int buff_pa_len = 0U;
446 unsigned int pkt_len = 0U;
447 unsigned int frag_count = 0U;
448 bool is_gso = false;
449
450 buff = &ring->buff_ring[ring->sw_tail];
451 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
452
453 for (frag_count = 0; frag_count < frags; frag_count++) {
454 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
455 HW_ATL_B0_TXD_SIZE];
456 txd->ctl = 0;
457 txd->ctl2 = 0;
458 txd->buf_addr = 0;
459
460 buff = &ring->buff_ring[ring->sw_tail];
461
462 if (buff->is_txc) {
463 txd->ctl |= (buff->len_l3 << 31) |
464 (buff->len_l2 << 24) |
465 HW_ATL_B0_TXD_CTL_CMD_TCP |
466 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
467 txd->ctl2 |= (buff->mss << 16) |
468 (buff->len_l4 << 8) |
469 (buff->len_l3 >> 1);
470
471 pkt_len -= (buff->len_l4 +
472 buff->len_l3 +
473 buff->len_l2);
474 is_gso = true;
386aff88
PB		 475
476 if (buff->is_ipv6)
477 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
bab6de8f
DV		 478 } else {
479 buff_pa_len = buff->len;
480
481 txd->buf_addr = buff->pa;
482 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
483 ((u32)buff_pa_len << 4));
484 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
485 /* PAY_LEN */
486 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
487
488 if (is_gso) {
489 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
490 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
491 }
492
493 /* Tx checksum offloads */
494 if (buff->is_ip_cso)
495 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
496
497 if (buff->is_udp_cso || buff->is_tcp_cso)
498 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
499
500 if (unlikely(buff->is_eop)) {
501 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
502 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
5d73bb86 503 is_gso = false;
bab6de8f
DV		 504 }
505 }
506
507 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
508 }
509
510 hw_atl_b0_hw_tx_ring_tail_update(self, ring);
511 return aq_hw_err_from_flags(self);
512}
513
514static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
515 struct aq_ring_s *aq_ring,
516 struct aq_ring_param_s *aq_ring_param)
517{
518 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
519 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
520
521 rdm_rx_desc_en_set(self, false, aq_ring->idx);
522
523 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
524
525 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
526 aq_ring->idx);
527
528 reg_rx_dma_desc_base_addressmswset(self,
529 dma_desc_addr_msw, aq_ring->idx);
530
531 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
532
533 rdm_rx_desc_data_buff_size_set(self,
534 AQ_CFG_RX_FRAME_MAX / 1024U,
535 aq_ring->idx);
536
537 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
538 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
539 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
540
541 /* Rx ring set mode */
542
543 /* Mapping interrupt vector */
544 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
545 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
546
547 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
548 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
549 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
550 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
551
552 return aq_hw_err_from_flags(self);
553}
554
555static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
556 struct aq_ring_s *aq_ring,
557 struct aq_ring_param_s *aq_ring_param)
558{
559 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
560 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
561
562 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
563 aq_ring->idx);
564
565 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
566 aq_ring->idx);
567
568 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
569
570 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
571
572 /* Set Tx threshold */
573 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
574
575 /* Mapping interrupt vector */
576 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
577 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
578
579 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
580 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
581
582 return aq_hw_err_from_flags(self);
583}
584
585static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
586 struct aq_ring_s *ring,
587 unsigned int sw_tail_old)
588{
589 for (; sw_tail_old != ring->sw_tail;
590 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
591 struct hw_atl_rxd_s *rxd =
592 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
593 HW_ATL_B0_RXD_SIZE];
594
595 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
596
597 rxd->buf_addr = buff->pa;
598 rxd->hdr_addr = 0U;
599 }
600
601 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
602
603 return aq_hw_err_from_flags(self);
604}
605
606static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
607 struct aq_ring_s *ring)
608{
609 int err = 0;
610 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
611
612 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
613 err = -ENXIO;
614 goto err_exit;
615 }
616 ring->hw_head = hw_head_;
617 err = aq_hw_err_from_flags(self);
618
619err_exit:
620 return err;
621}
622
623static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
624 struct aq_ring_s *ring)
625{
626 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
627
628 for (; ring->hw_head != ring->sw_tail;
629 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
630 struct aq_ring_buff_s *buff = NULL;
631 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
632 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
633
634 unsigned int is_err = 1U;
635 unsigned int is_rx_check_sum_enabled = 0U;
636 unsigned int pkt_type = 0U;
637
638 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
639 break;
640 }
641
642 buff = &ring->buff_ring[ring->hw_head];
643
644 is_err = (0x0000003CU & rxd_wb->status);
645
646 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
647 is_err &= ~0x20U; /* exclude validity bit */
648
649 pkt_type = 0xFFU & (rxd_wb->type >> 4);
650
651 if (is_rx_check_sum_enabled) {
652 if (0x0U == (pkt_type & 0x3U))
653 buff->is_ip_cso = (is_err & 0x08U) ? 0U : 1U;
654
655 if (0x4U == (pkt_type & 0x1CU))
656 buff->is_udp_cso = buff->is_cso_err ? 0U : 1U;
657 else if (0x0U == (pkt_type & 0x1CU))
658 buff->is_tcp_cso = buff->is_cso_err ? 0U : 1U;
0a402e7b
PB		 659
660 /* Checksum offload workaround for small packets */
661 if (rxd_wb->pkt_len <= 60) {
662 buff->is_ip_cso = 0U;
663 buff->is_cso_err = 0U;
664 }
bab6de8f
DV		 665 }
666
667 is_err &= ~0x18U;
668
669 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
670
671 if (is_err || rxd_wb->type & 0x1000U) {
672 /* status error or DMA error */
673 buff->is_error = 1U;
674 } else {
675 if (self->aq_nic_cfg->is_rss) {
676 /* last 4 byte */
677 u16 rss_type = rxd_wb->type & 0xFU;
678
679 if (rss_type && rss_type < 0x8U) {
680 buff->is_hash_l4 = (rss_type == 0x4 ||
681 rss_type == 0x5);
682 buff->rss_hash = rxd_wb->rss_hash;
683 }
684 }
685
686 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
c0788f74
PB		 687 buff->len = rxd_wb->pkt_len %
688 AQ_CFG_RX_FRAME_MAX;
bab6de8f
DV		 689 buff->len = buff->len ?
690 buff->len : AQ_CFG_RX_FRAME_MAX;
691 buff->next = 0U;
692 buff->is_eop = 1U;
693 } else {
694 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
695 rxd_wb->status) {
696 /* LRO */
697 buff->next = rxd_wb->next_desc_ptr;
698 ++ring->stats.rx.lro_packets;
699 } else {
700 /* jumbo */
701 buff->next =
702 aq_ring_next_dx(ring,
703 ring->hw_head);
704 ++ring->stats.rx.jumbo_packets;
705 }
706 }
707 }
708 }
709
710 return aq_hw_err_from_flags(self);
711}
712
713static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
714{
715 itr_irq_msk_setlsw_set(self, LODWORD(mask));
716 return aq_hw_err_from_flags(self);
717}
718
719static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
720{
721 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
722 itr_irq_status_clearlsw_set(self, LODWORD(mask));
723
724 atomic_inc(&PHAL_ATLANTIC_B0->dpc);
725 return aq_hw_err_from_flags(self);
726}
727
728static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
729{
730 *mask = itr_irq_statuslsw_get(self);
731 return aq_hw_err_from_flags(self);
732}
733
734#define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
735
736static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
737 unsigned int packet_filter)
738{
739 unsigned int i = 0U;
740
741 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
742 rpfl2multicast_flr_en_set(self,
743 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
744
745 rpfl2_accept_all_mc_packets_set(self,
746 IS_FILTER_ENABLED(IFF_ALLMULTI));
747
748 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
749
750 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
751
752 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
753 rpfl2_uc_flr_en_set(self,
754 (self->aq_nic_cfg->is_mc_list_enabled &&
755 (i <= self->aq_nic_cfg->mc_list_count)) ?
756 1U : 0U, i);
757
758 return aq_hw_err_from_flags(self);
759}
760
761#undef IS_FILTER_ENABLED
762
763static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
764 u8 ar_mac
765 [AQ_CFG_MULTICAST_ADDRESS_MAX]
766 [ETH_ALEN],
767 u32 count)
768{
769 int err = 0;
770
771 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
772 err = -EBADRQC;
773 goto err_exit;
774 }
775 for (self->aq_nic_cfg->mc_list_count = 0U;
776 self->aq_nic_cfg->mc_list_count < count;
777 ++self->aq_nic_cfg->mc_list_count) {
778 u32 i = self->aq_nic_cfg->mc_list_count;
779 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
780 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
781 (ar_mac[i][4] << 8) | ar_mac[i][5];
782
783 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
784
785 rpfl2unicast_dest_addresslsw_set(self,
786 l, HW_ATL_B0_MAC_MIN + i);
787
788 rpfl2unicast_dest_addressmsw_set(self,
789 h, HW_ATL_B0_MAC_MIN + i);
790
791 rpfl2_uc_flr_en_set(self,
792 (self->aq_nic_cfg->is_mc_list_enabled),
793 HW_ATL_B0_MAC_MIN + i);
794 }
795
796 err = aq_hw_err_from_flags(self);
797
798err_exit:
799 return err;
800}
801
b82ee71a 802static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
bab6de8f
DV		 803{
804 unsigned int i = 0U;
b82ee71a
IR		 805 u32 itr_tx = 2U;
806 u32 itr_rx = 2U;
bab6de8f 807
b82ee71a
IR		 808 switch (self->aq_nic_cfg->itr) {
809 case AQ_CFG_INTERRUPT_MODERATION_ON:
810 case AQ_CFG_INTERRUPT_MODERATION_AUTO:
bab6de8f
DV		 811 tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
812 tdm_tdm_intr_moder_en_set(self, 1U);
813 rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
814 rdm_rdm_intr_moder_en_set(self, 1U);
815
b82ee71a
IR		 816 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
817 /* HW timers are in 2us units */
818 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
819 int tx_min_timer = tx_max_timer / 2;
bab6de8f 820
b82ee71a
IR		 821 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
822 int rx_min_timer = rx_max_timer / 2;
bab6de8f 823
b82ee71a
IR		 824 tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
825 tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
826 rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
827 rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
bab6de8f 828
b82ee71a
IR		 829 itr_tx |= tx_min_timer << 0x8U;
830 itr_tx |= tx_max_timer << 0x10U;
831 itr_rx |= rx_min_timer << 0x8U;
832 itr_rx |= rx_max_timer << 0x10U;
bab6de8f
DV		 833 } else {
834 static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
417a3ae4
IR		 835 {0xfU, 0xffU}, /* 10Gbit */
836 {0xfU, 0x1ffU}, /* 5Gbit */
837 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
838 {0xfU, 0x1ffU}, /* 2.5Gbit */
839 {0xfU, 0x1ffU}, /* 1Gbit */
840 {0xfU, 0x1ffU}, /* 100Mbit */
bab6de8f
DV		 841 };
842
843 static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
844 {0x6U, 0x38U},/* 10Gbit */
845 {0xCU, 0x70U},/* 5Gbit */
846 {0xCU, 0x70U},/* 5Gbit 5GS */
847 {0x18U, 0xE0U},/* 2.5Gbit */
848 {0x30U, 0x80U},/* 1Gbit */
849 {0x4U, 0x50U},/* 100Mbit */
850 };
851
852 unsigned int speed_index =
853 hw_atl_utils_mbps_2_speed_index(
854 self->aq_link_status.mbps);
855
b82ee71a
IR		 856 /* Update user visible ITR settings */
857 self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
858 [speed_index][1] * 2;
859 self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
860 [speed_index][1] * 2;
861
862 itr_tx |= hw_atl_b0_timers_table_tx_
863 [speed_index][0] << 0x8U;
864 itr_tx |= hw_atl_b0_timers_table_tx_
865 [speed_index][1] << 0x10U;
866
867 itr_rx |= hw_atl_b0_timers_table_rx_
868 [speed_index][0] << 0x8U;
869 itr_rx |= hw_atl_b0_timers_table_rx_
870 [speed_index][1] << 0x10U;
bab6de8f 871 }
b82ee71a
IR		 872 break;
873 case AQ_CFG_INTERRUPT_MODERATION_OFF:
bab6de8f
DV		 874 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
875 tdm_tdm_intr_moder_en_set(self, 0U);
876 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
877 rdm_rdm_intr_moder_en_set(self, 0U);
b82ee71a
IR		 878 itr_tx = 0U;
879 itr_rx = 0U;
880 break;
bab6de8f
DV		 881 }
882
883 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
b82ee71a
IR		 884 reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
885 reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
bab6de8f
DV		 886 }
887
888 return aq_hw_err_from_flags(self);
889}
890
891static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
892{
893 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
894 return aq_hw_err_from_flags(self);
895}
896
897static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
898 struct aq_ring_s *ring)
899{
900 tdm_tx_desc_en_set(self, 0U, ring->idx);
901 return aq_hw_err_from_flags(self);
902}
903
904static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
905 struct aq_ring_s *ring)
906{
907 rdm_rx_desc_en_set(self, 0U, ring->idx);
908 return aq_hw_err_from_flags(self);
909}
910
911static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed)
912{
913 int err = 0;
914
915 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
916 if (err < 0)
917 goto err_exit;
918
919err_exit:
920 return err;
921}
922
923static struct aq_hw_ops hw_atl_ops_ = {
924 .create = hw_atl_b0_create,
925 .destroy = hw_atl_b0_destroy,
926 .get_hw_caps = hw_atl_b0_get_hw_caps,
927
928 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
929 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
930 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
931 .hw_set_link_speed = hw_atl_b0_hw_set_speed,
932 .hw_init = hw_atl_b0_hw_init,
933 .hw_deinit = hw_atl_utils_hw_deinit,
934 .hw_set_power = hw_atl_utils_hw_set_power,
935 .hw_reset = hw_atl_b0_hw_reset,
936 .hw_start = hw_atl_b0_hw_start,
937 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
938 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop,
939 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start,
940 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop,
941 .hw_stop = hw_atl_b0_hw_stop,
942
943 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit,
944 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update,
945
946 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive,
947 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill,
948
949 .hw_irq_enable = hw_atl_b0_hw_irq_enable,
950 .hw_irq_disable = hw_atl_b0_hw_irq_disable,
951 .hw_irq_read = hw_atl_b0_hw_irq_read,
952
953 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
954 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
955 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
956 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
957 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
958 .hw_rss_set = hw_atl_b0_hw_rss_set,
959 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
960 .hw_get_regs = hw_atl_utils_hw_get_regs,
65e665e6 961 .hw_update_stats = hw_atl_utils_update_stats,
bab6de8f
DV		 962 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
963 .hw_get_fw_version = hw_atl_utils_get_fw_version,
964};
965
966struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
967{
968 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
969 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
970 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
971 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
972 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
973 (pdev->device == HW_ATL_DEVICE_ID_D109));
974
975 bool is_rev_ok = (pdev->revision == 2U);
976
977 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
978}
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