[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / arc / emac.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
 *
 * Registers and bits definitions of ARC EMAC
 */

#ifndef ARC_EMAC_H
#define ARC_EMAC_H

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <linux/clk.h>

/* STATUS and ENABLE Register bit masks */
#define TXINT_MASK	(1 << 0)	/* Transmit interrupt */
#define RXINT_MASK	(1 << 1)	/* Receive interrupt */
#define ERR_MASK	(1 << 2)	/* Error interrupt */
#define TXCH_MASK	(1 << 3)	/* Transmit chaining error interrupt */
#define MSER_MASK	(1 << 4)	/* Missed packet counter error */
#define RXCR_MASK	(1 << 8)	/* RXCRCERR counter rolled over  */
#define RXFR_MASK	(1 << 9)	/* RXFRAMEERR counter rolled over */
#define RXFL_MASK	(1 << 10)	/* RXOFLOWERR counter rolled over */
#define MDIO_MASK	(1 << 12)	/* MDIO complete interrupt */
#define TXPL_MASK	(1 << 31)	/* Force polling of BD by EMAC */

/* CONTROL Register bit masks */
#define EN_MASK		(1 << 0)	/* VMAC enable */
#define TXRN_MASK	(1 << 3)	/* TX enable */
#define RXRN_MASK	(1 << 4)	/* RX enable */
#define DSBC_MASK	(1 << 8)	/* Disable receive broadcast */
#define ENFL_MASK	(1 << 10)	/* Enable Full-duplex */
#define PROM_MASK	(1 << 11)	/* Promiscuous mode */

/* Buffer descriptor INFO bit masks */
#define OWN_MASK	(1 << 31)	/* 0-CPU or 1-EMAC owns buffer */
#define FIRST_MASK	(1 << 16)	/* First buffer in chain */
#define LAST_MASK	(1 << 17)	/* Last buffer in chain */
#define LEN_MASK	0x000007FF	/* last 11 bits */
#define CRLS		(1 << 21)
#define DEFR		(1 << 22)
#define DROP		(1 << 23)
#define RTRY		(1 << 24)
#define LTCL		(1 << 28)
#define UFLO		(1 << 29)

#define FOR_EMAC	OWN_MASK
#define FOR_CPU		0

/* ARC EMAC register set combines entries for MAC and MDIO */
enum {
	R_ID = 0,
	R_STATUS,
	R_ENABLE,
	R_CTRL,
	R_POLLRATE,
	R_RXERR,
	R_MISS,
	R_TX_RING,
	R_RX_RING,
	R_ADDRL,
	R_ADDRH,
	R_LAFL,
	R_LAFH,
	R_MDIO,
};

#define TX_TIMEOUT		(400 * HZ / 1000) /* Transmission timeout */

#define ARC_EMAC_NAPI_WEIGHT	40		/* Workload for NAPI */

#define EMAC_BUFFER_SIZE	1536		/* EMAC buffer size */

/**
 * struct arc_emac_bd - EMAC buffer descriptor (BD).
 *
 * @info:	Contains status information on the buffer itself.
 * @data:	32-bit byte addressable pointer to the packet data.
 */
struct arc_emac_bd {
	__le32 info;
	dma_addr_t data;
};

/* Number of Rx/Tx BD's */
#define RX_BD_NUM	128
#define TX_BD_NUM	128

#define RX_RING_SZ	(RX_BD_NUM * sizeof(struct arc_emac_bd))
#define TX_RING_SZ	(TX_BD_NUM * sizeof(struct arc_emac_bd))

/**
 * struct buffer_state - Stores Rx/Tx buffer state.
 * @sk_buff:	Pointer to socket buffer.
 * @addr:	Start address of DMA-mapped memory region.
 * @len:	Length of DMA-mapped memory region.
 */
struct buffer_state {
	struct sk_buff *skb;
	DEFINE_DMA_UNMAP_ADDR(addr);
	DEFINE_DMA_UNMAP_LEN(len);
};

struct arc_emac_mdio_bus_data {
	struct gpio_desc *reset_gpio;
	int msec;
};

/**
 * struct arc_emac_priv - Storage of EMAC's private information.
 * @dev:	Pointer to the current device.
 * @phy_dev:	Pointer to attached PHY device.
 * @bus:	Pointer to the current MII bus.
 * @regs:	Base address of EMAC memory-mapped control registers.
 * @napi:	Structure for NAPI.
 * @rxbd:	Pointer to Rx BD ring.
 * @txbd:	Pointer to Tx BD ring.
 * @rxbd_dma:	DMA handle for Rx BD ring.
 * @txbd_dma:	DMA handle for Tx BD ring.
 * @rx_buff:	Storage for Rx buffers states.
 * @tx_buff:	Storage for Tx buffers states.
 * @txbd_curr:	Index of Tx BD to use on the next "ndo_start_xmit".
 * @txbd_dirty:	Index of Tx BD to free on the next Tx interrupt.
 * @last_rx_bd:	Index of the last Rx BD we've got from EMAC.
 * @link:	PHY's last seen link state.
 * @duplex:	PHY's last set duplex mode.
 * @speed:	PHY's last set speed.
 */
struct arc_emac_priv {
	const char *drv_name;
	const char *drv_version;
	void (*set_mac_speed)(void *priv, unsigned int speed);

	/* Devices */
	struct device *dev;
	struct mii_bus *bus;
	struct arc_emac_mdio_bus_data bus_data;

	void __iomem *regs;
	struct clk *clk;

	struct napi_struct napi;

	struct arc_emac_bd *rxbd;
	struct arc_emac_bd *txbd;

	dma_addr_t rxbd_dma;
	dma_addr_t txbd_dma;

	struct buffer_state rx_buff[RX_BD_NUM];
	struct buffer_state tx_buff[TX_BD_NUM];
	unsigned int txbd_curr;
	unsigned int txbd_dirty;

	unsigned int last_rx_bd;

	unsigned int link;
	unsigned int duplex;
	unsigned int speed;

	unsigned int rx_missed_errors;
};

/**
 * arc_reg_set - Sets EMAC register with provided value.
 * @priv:	Pointer to ARC EMAC private data structure.
 * @reg:	Register offset from base address.
 * @value:	Value to set in register.
 */
static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
{
	iowrite32(value, priv->regs + reg * sizeof(int));
}

/**
 * arc_reg_get - Gets value of specified EMAC register.
 * @priv:	Pointer to ARC EMAC private data structure.
 * @reg:	Register offset from base address.
 *
 * returns:	Value of requested register.
 */
static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
{
	return ioread32(priv->regs + reg * sizeof(int));
}

/**
 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
 * @priv:	Pointer to ARC EMAC private data structure.
 * @reg:	Register offset from base address.
 * @mask:	Mask to apply to specified register.
 *
 * This function reads initial register value, then applies provided mask
 * to it and then writes register back.
 */
static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
{
	unsigned int value = arc_reg_get(priv, reg);

	arc_reg_set(priv, reg, value | mask);
}

/**
 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
 * @priv:	Pointer to ARC EMAC private data structure.
 * @reg:	Register offset from base address.
 * @mask:	Mask to apply to specified register.
 *
 * This function reads initial register value, then applies provided mask
 * to it and then writes register back.
 */
static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
{
	unsigned int value = arc_reg_get(priv, reg);

	arc_reg_set(priv, reg, value & ~mask);
}

int arc_mdio_probe(struct arc_emac_priv *priv);
int arc_mdio_remove(struct arc_emac_priv *priv);
int arc_emac_probe(struct net_device *ndev, int interface);
int arc_emac_remove(struct net_device *ndev);

#endif /* ARC_EMAC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
e4f2379d AB	2	/*
	3	* Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
	4	*
	5	* Registers and bits definitions of ARC EMAC
	6	*/
	7
	8	#ifndef ARC_EMAC_H
	9	#define ARC_EMAC_H
	10
	11	#include <linux/device.h>
	12	#include <linux/dma-mapping.h>
	13	#include <linux/netdevice.h>
	14	#include <linux/phy.h>
88154c96	15	#include <linux/clk.h>
e4f2379d AB	16
e4f2379d AB	17	/* STATUS and ENABLE Register bit masks */
663713eb CW	18	#define TXINT_MASK (1 << 0) /* Transmit interrupt */
	19	#define RXINT_MASK (1 << 1) /* Receive interrupt */
	20	#define ERR_MASK (1 << 2) /* Error interrupt */
	21	#define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
	22	#define MSER_MASK (1 << 4) /* Missed packet counter error */
	23	#define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
	24	#define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
	25	#define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
	26	#define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
	27	#define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
e4f2379d AB	28
e4f2379d AB	29	/* CONTROL Register bit masks */
663713eb CW	30	#define EN_MASK (1 << 0) /* VMAC enable */
	31	#define TXRN_MASK (1 << 3) /* TX enable */
	32	#define RXRN_MASK (1 << 4) /* RX enable */
	33	#define DSBC_MASK (1 << 8) /* Disable receive broadcast */
	34	#define ENFL_MASK (1 << 10) /* Enable Full-duplex */
	35	#define PROM_MASK (1 << 11) /* Promiscuous mode */
e4f2379d AB	36
e4f2379d AB	37	/* Buffer descriptor INFO bit masks */
663713eb CW	38	#define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
	39	#define FIRST_MASK (1 << 16) /* First buffer in chain */
	40	#define LAST_MASK (1 << 17) /* Last buffer in chain */
e4f2379d	41	#define LEN_MASK 0x000007FF /* last 11 bits */
663713eb CW	42	#define CRLS (1 << 21)
	43	#define DEFR (1 << 22)
	44	#define DROP (1 << 23)
	45	#define RTRY (1 << 24)
	46	#define LTCL (1 << 28)
	47	#define UFLO (1 << 29)
e4f2379d AB	48
	49	#define FOR_EMAC OWN_MASK
	50	#define FOR_CPU 0
	51
	52	/* ARC EMAC register set combines entries for MAC and MDIO */
	53	enum {
	54	R_ID = 0,
	55	R_STATUS,
	56	R_ENABLE,
	57	R_CTRL,
	58	R_POLLRATE,
	59	R_RXERR,
	60	R_MISS,
	61	R_TX_RING,
	62	R_RX_RING,
	63	R_ADDRL,
	64	R_ADDRH,
	65	R_LAFL,
	66	R_LAFH,
	67	R_MDIO,
	68	};
	69
663713eb	70	#define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
e4f2379d AB	71
	72	#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
	73
	74	#define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
	75
	76	/**
	77	* struct arc_emac_bd - EMAC buffer descriptor (BD).
	78	*
	79	* @info: Contains status information on the buffer itself.
	80	* @data: 32-bit byte addressable pointer to the packet data.
	81	*/
	82	struct arc_emac_bd {
	83	__le32 info;
	84	dma_addr_t data;
	85	};
	86
	87	/* Number of Rx/Tx BD's */
	88	#define RX_BD_NUM 128
	89	#define TX_BD_NUM 128
	90
	91	#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
	92	#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
	93
	94	/**
	95	* struct buffer_state - Stores Rx/Tx buffer state.
	96	* @sk_buff: Pointer to socket buffer.
	97	* @addr: Start address of DMA-mapped memory region.
	98	* @len: Length of DMA-mapped memory region.
	99	*/
	100	struct buffer_state {
	101	struct sk_buff *skb;
	102	DEFINE_DMA_UNMAP_ADDR(addr);
	103	DEFINE_DMA_UNMAP_LEN(len);
	104	};
	105
1bddd96c CW	106	struct arc_emac_mdio_bus_data {
	107	struct gpio_desc *reset_gpio;
	108	int msec;
	109	};
	110
e4f2379d AB	111	/**
	112	* struct arc_emac_priv - Storage of EMAC's private information.
	113	* @dev: Pointer to the current device.
e4f2379d AB	114	* @phy_dev: Pointer to attached PHY device.
	115	* @bus: Pointer to the current MII bus.
	116	* @regs: Base address of EMAC memory-mapped control registers.
	117	* @napi: Structure for NAPI.
e4f2379d AB	118	* @rxbd: Pointer to Rx BD ring.
	119	* @txbd: Pointer to Tx BD ring.
	120	* @rxbd_dma: DMA handle for Rx BD ring.
	121	* @txbd_dma: DMA handle for Tx BD ring.
	122	* @rx_buff: Storage for Rx buffers states.
	123	* @tx_buff: Storage for Tx buffers states.
	124	* @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
	125	* @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
	126	* @last_rx_bd: Index of the last Rx BD we've got from EMAC.
	127	* @link: PHY's last seen link state.
	128	* @duplex: PHY's last set duplex mode.
	129	* @speed: PHY's last set speed.
e4f2379d AB	130	*/
e4f2379d AB	131	struct arc_emac_priv {
23d2d9a6 RP	132	const char *drv_name;
23d2d9a6 RP	133	const char *drv_version;
6eacf311 RP	134	void (set_mac_speed)(void priv, unsigned int speed);
	135
	136	/* Devices */
e4f2379d	137	struct device *dev;
e4f2379d	138	struct mii_bus *bus;
1bddd96c	139	struct arc_emac_mdio_bus_data bus_data;
e4f2379d AB	140
e4f2379d AB	141	void __iomem *regs;
88154c96	142	struct clk *clk;
e4f2379d AB	143
e4f2379d AB	144	struct napi_struct napi;
e4f2379d AB	145
	146	struct arc_emac_bd *rxbd;
	147	struct arc_emac_bd *txbd;
	148
	149	dma_addr_t rxbd_dma;
	150	dma_addr_t txbd_dma;
	151
	152	struct buffer_state rx_buff[RX_BD_NUM];
	153	struct buffer_state tx_buff[TX_BD_NUM];
	154	unsigned int txbd_curr;
	155	unsigned int txbd_dirty;
	156
	157	unsigned int last_rx_bd;
	158
	159	unsigned int link;
	160	unsigned int duplex;
	161	unsigned int speed;
78aa0975 AK	162
78aa0975 AK	163	unsigned int rx_missed_errors;
e4f2379d AB	164	};
	165
	166	/**
	167	* arc_reg_set - Sets EMAC register with provided value.
	168	* @priv: Pointer to ARC EMAC private data structure.
	169	* @reg: Register offset from base address.
	170	* @value: Value to set in register.
	171	*/
	172	static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
	173	{
	174	iowrite32(value, priv->regs + reg * sizeof(int));
	175	}
	176
	177	/**
	178	* arc_reg_get - Gets value of specified EMAC register.
	179	* @priv: Pointer to ARC EMAC private data structure.
	180	* @reg: Register offset from base address.
	181	*
	182	* returns: Value of requested register.
	183	*/
	184	static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
	185	{
	186	return ioread32(priv->regs + reg * sizeof(int));
	187	}
	188
	189	/**
	190	* arc_reg_or - Applies mask to specified EMAC register - ("reg" \| "mask").
	191	* @priv: Pointer to ARC EMAC private data structure.
	192	* @reg: Register offset from base address.
	193	* @mask: Mask to apply to specified register.
	194	*
	195	* This function reads initial register value, then applies provided mask
	196	* to it and then writes register back.
	197	*/
	198	static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
	199	{
	200	unsigned int value = arc_reg_get(priv, reg);
663713eb	201
e4f2379d AB	202	arc_reg_set(priv, reg, value \| mask);
	203	}
	204
	205	/**
	206	* arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
	207	* @priv: Pointer to ARC EMAC private data structure.
	208	* @reg: Register offset from base address.
	209	* @mask: Mask to apply to specified register.
	210	*
	211	* This function reads initial register value, then applies provided mask
	212	* to it and then writes register back.
	213	*/
	214	static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
	215	{
	216	unsigned int value = arc_reg_get(priv, reg);
663713eb	217
e4f2379d AB	218	arc_reg_set(priv, reg, value & ~mask);
	219	}
	220
93e91b3d	221	int arc_mdio_probe(struct arc_emac_priv *priv);
e4f2379d	222	int arc_mdio_remove(struct arc_emac_priv *priv);
23d2d9a6 RP	223	int arc_emac_probe(struct net_device *ndev, int interface);
23d2d9a6 RP	224	int arc_emac_remove(struct net_device *ndev);
e4f2379d AB	225
e4f2379d AB	226	#endif /* ARC_EMAC_H */