[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / arc / emac_rockchip.c

/**
 * emac-rockchip.c - Rockchip EMAC specific glue layer
 *
 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/etherdevice.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_net.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>

#include "emac.h"

#define DRV_NAME        "rockchip_emac"
#define DRV_VERSION     "1.1"

struct emac_rockchip_soc_data {
	unsigned int grf_offset;
	unsigned int grf_mode_offset;
	unsigned int grf_speed_offset;
	bool need_div_macclk;
};

struct rockchip_priv_data {
	struct arc_emac_priv emac;
	struct regmap *grf;
	const struct emac_rockchip_soc_data *soc_data;
	struct regulator *regulator;
	struct clk *refclk;
	struct clk *macclk;
};

static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
{
	struct rockchip_priv_data *emac = priv;
	u32 speed_offset = emac->soc_data->grf_speed_offset;
	u32 data;
	int err = 0;

	switch (speed) {
	case 10:
		data = (1 << (speed_offset + 16)) | (0 << speed_offset);
		break;
	case 100:
		data = (1 << (speed_offset + 16)) | (1 << speed_offset);
		break;
	default:
		pr_err("speed %u not supported\n", speed);
		return;
	}

	err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
	if (err)
		pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
}

static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
	.grf_offset = 0x140,   .grf_mode_offset = 8,
	.grf_speed_offset = 9, .need_div_macclk = 1,
};

static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
	.grf_offset = 0x154,   .grf_mode_offset = 0,
	.grf_speed_offset = 1, .need_div_macclk = 0,
};

static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
	.grf_offset = 0x0a4,   .grf_mode_offset = 0,
	.grf_speed_offset = 1, .need_div_macclk = 0,
};

static const struct of_device_id emac_rockchip_dt_ids[] = {
	{
		.compatible = "rockchip,rk3036-emac",
		.data = &emac_rk3036_emac_data,
	},
	{
		.compatible = "rockchip,rk3066-emac",
		.data = &emac_rk3066_emac_data,
	},
	{
		.compatible = "rockchip,rk3188-emac",
		.data = &emac_rk3188_emac_data,
	},
	{ /* Sentinel */ }
};

MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);

static int emac_rockchip_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct net_device *ndev;
	struct rockchip_priv_data *priv;
	const struct of_device_id *match;
	u32 data;
	int err, interface;

	if (!pdev->dev.of_node)
		return -ENODEV;

	ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
	if (!ndev)
		return -ENOMEM;
	platform_set_drvdata(pdev, ndev);
	SET_NETDEV_DEV(ndev, dev);

	priv = netdev_priv(ndev);
	priv->emac.drv_name = DRV_NAME;
	priv->emac.drv_version = DRV_VERSION;
	priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;

	interface = of_get_phy_mode(dev->of_node);

	/* RK3036/RK3066/RK3188 SoCs only support RMII */
	if (interface != PHY_INTERFACE_MODE_RMII) {
		dev_err(dev, "unsupported phy interface mode %d\n", interface);
		err = -ENOTSUPP;
		goto out_netdev;
	}

	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
						    "rockchip,grf");
	if (IS_ERR(priv->grf)) {
		dev_err(dev, "failed to retrieve global register file (%ld)\n",
			PTR_ERR(priv->grf));
		err = PTR_ERR(priv->grf);
		goto out_netdev;
	}

	match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
	priv->soc_data = match->data;

	priv->emac.clk = devm_clk_get(dev, "hclk");
	if (IS_ERR(priv->emac.clk)) {
		dev_err(dev, "failed to retrieve host clock (%ld)\n",
			PTR_ERR(priv->emac.clk));
		err = PTR_ERR(priv->emac.clk);
		goto out_netdev;
	}

	priv->refclk = devm_clk_get(dev, "macref");
	if (IS_ERR(priv->refclk)) {
		dev_err(dev, "failed to retrieve reference clock (%ld)\n",
			PTR_ERR(priv->refclk));
		err = PTR_ERR(priv->refclk);
		goto out_netdev;
	}

	err = clk_prepare_enable(priv->refclk);
	if (err) {
		dev_err(dev, "failed to enable reference clock (%d)\n", err);
		goto out_netdev;
	}

	/* Optional regulator for PHY */
	priv->regulator = devm_regulator_get_optional(dev, "phy");
	if (IS_ERR(priv->regulator)) {
		if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
			err = -EPROBE_DEFER;
			goto out_clk_disable;
		}
		dev_err(dev, "no regulator found\n");
		priv->regulator = NULL;
	}

	if (priv->regulator) {
		err = regulator_enable(priv->regulator);
		if (err) {
			dev_err(dev, "failed to enable phy-supply (%d)\n", err);
			goto out_clk_disable;
		}
	}

	/* Set speed 100M */
	data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
	       (1 << priv->soc_data->grf_speed_offset);
	/* Set RMII mode */
	data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
		(0 << priv->soc_data->grf_mode_offset);

	err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
	if (err) {
		dev_err(dev, "unable to apply initial settings to grf (%d)\n",
			err);
		goto out_regulator_disable;
	}

	/* RMII interface needs always a rate of 50MHz */
	err = clk_set_rate(priv->refclk, 50000000);
	if (err) {
		dev_err(dev,
			"failed to change reference clock rate (%d)\n", err);
		goto out_regulator_disable;
	}

	if (priv->soc_data->need_div_macclk) {
		priv->macclk = devm_clk_get(dev, "macclk");
		if (IS_ERR(priv->macclk)) {
			dev_err(dev, "failed to retrieve mac clock (%ld)\n",
				PTR_ERR(priv->macclk));
			err = PTR_ERR(priv->macclk);
			goto out_regulator_disable;
		}

		err = clk_prepare_enable(priv->macclk);
		if (err) {
			dev_err(dev, "failed to enable mac clock (%d)\n", err);
			goto out_regulator_disable;
		}

		/* RMII TX/RX needs always a rate of 25MHz */
		err = clk_set_rate(priv->macclk, 25000000);
		if (err) {
			dev_err(dev,
				"failed to change mac clock rate (%d)\n", err);
			goto out_clk_disable_macclk;
		}
	}

	err = arc_emac_probe(ndev, interface);
	if (err) {
		dev_err(dev, "failed to probe arc emac (%d)\n", err);
		goto out_clk_disable_macclk;
	}

	return 0;

out_clk_disable_macclk:
	if (priv->soc_data->need_div_macclk)
		clk_disable_unprepare(priv->macclk);
out_regulator_disable:
	if (priv->regulator)
		regulator_disable(priv->regulator);
out_clk_disable:
	clk_disable_unprepare(priv->refclk);
out_netdev:
	free_netdev(ndev);
	return err;
}

static int emac_rockchip_remove(struct platform_device *pdev)
{
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct rockchip_priv_data *priv = netdev_priv(ndev);
	int err;

	err = arc_emac_remove(ndev);

	clk_disable_unprepare(priv->refclk);

	if (priv->regulator)
		regulator_disable(priv->regulator);

	free_netdev(ndev);
	return err;
}

static struct platform_driver emac_rockchip_driver = {
	.probe = emac_rockchip_probe,
	.remove = emac_rockchip_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table  = emac_rockchip_dt_ids,
	},
};

module_platform_driver(emac_rockchip_driver);

MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
MODULE_DESCRIPTION("Rockchip EMAC platform driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6eacf311 RP	1	/**
	2	* emac-rockchip.c - Rockchip EMAC specific glue layer
	3	*
	4	* Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/etherdevice.h>
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/module.h>
	20	#include <linux/of_net.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/regmap.h>
	23	#include <linux/regulator/consumer.h>
	24
	25	#include "emac.h"
	26
	27	#define DRV_NAME "rockchip_emac"
f4c9d3ee	28	#define DRV_VERSION "1.1"
6eacf311 RP	29
6eacf311 RP	30	struct emac_rockchip_soc_data {
f4c9d3ee XZ	31	unsigned int grf_offset;
	32	unsigned int grf_mode_offset;
	33	unsigned int grf_speed_offset;
	34	bool need_div_macclk;
6eacf311 RP	35	};
	36
	37	struct rockchip_priv_data {
	38	struct arc_emac_priv emac;
	39	struct regmap *grf;
	40	const struct emac_rockchip_soc_data *soc_data;
	41	struct regulator *regulator;
	42	struct clk *refclk;
f4c9d3ee	43	struct clk *macclk;
6eacf311 RP	44	};
	45
	46	static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
	47	{
	48	struct rockchip_priv_data *emac = priv;
f4c9d3ee	49	u32 speed_offset = emac->soc_data->grf_speed_offset;
6eacf311 RP	50	u32 data;
	51	int err = 0;
	52
663713eb	53	switch (speed) {
6eacf311	54	case 10:
f4c9d3ee	55	data = (1 << (speed_offset + 16)) \| (0 << speed_offset);
6eacf311 RP	56	break;
6eacf311 RP	57	case 100:
f4c9d3ee	58	data = (1 << (speed_offset + 16)) \| (1 << speed_offset);
6eacf311 RP	59	break;
	60	default:
	61	pr_err("speed %u not supported\n", speed);
	62	return;
	63	}
	64
	65	err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
	66	if (err)
	67	pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
	68	}
	69
af72261f XZ	70	static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
	71	.grf_offset = 0x140, .grf_mode_offset = 8,
	72	.grf_speed_offset = 9, .need_div_macclk = 1,
	73	};
	74
f4c9d3ee XZ	75	static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
	76	.grf_offset = 0x154, .grf_mode_offset = 0,
	77	.grf_speed_offset = 1, .need_div_macclk = 0,
	78	};
	79
	80	static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
	81	.grf_offset = 0x0a4, .grf_mode_offset = 0,
	82	.grf_speed_offset = 1, .need_div_macclk = 0,
6eacf311 RP	83	};
	84
	85	static const struct of_device_id emac_rockchip_dt_ids[] = {
663713eb CW	86	{
	87	.compatible = "rockchip,rk3036-emac",
	88	.data = &emac_rk3036_emac_data,
	89	},
	90	{
	91	.compatible = "rockchip,rk3066-emac",
	92	.data = &emac_rk3066_emac_data,
	93	},
	94	{
	95	.compatible = "rockchip,rk3188-emac",
	96	.data = &emac_rk3188_emac_data,
	97	},
6eacf311 RP	98	{ /* Sentinel */ }
	99	};
	100
	101	MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
	102
	103	static int emac_rockchip_probe(struct platform_device *pdev)
	104	{
	105	struct device *dev = &pdev->dev;
	106	struct net_device *ndev;
	107	struct rockchip_priv_data *priv;
	108	const struct of_device_id *match;
	109	u32 data;
	110	int err, interface;
	111
	112	if (!pdev->dev.of_node)
	113	return -ENODEV;
	114
	115	ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
	116	if (!ndev)
	117	return -ENOMEM;
	118	platform_set_drvdata(pdev, ndev);
	119	SET_NETDEV_DEV(ndev, dev);
	120
	121	priv = netdev_priv(ndev);
	122	priv->emac.drv_name = DRV_NAME;
	123	priv->emac.drv_version = DRV_VERSION;
	124	priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
	125
	126	interface = of_get_phy_mode(dev->of_node);
	127
af72261f	128	/* RK3036/RK3066/RK3188 SoCs only support RMII */
6eacf311 RP	129	if (interface != PHY_INTERFACE_MODE_RMII) {
	130	dev_err(dev, "unsupported phy interface mode %d\n", interface);
	131	err = -ENOTSUPP;
	132	goto out_netdev;
	133	}
	134
663713eb CW	135	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
663713eb CW	136	"rockchip,grf");
6eacf311	137	if (IS_ERR(priv->grf)) {
663713eb CW	138	dev_err(dev, "failed to retrieve global register file (%ld)\n",
663713eb CW	139	PTR_ERR(priv->grf));
6eacf311 RP	140	err = PTR_ERR(priv->grf);
	141	goto out_netdev;
	142	}
	143
	144	match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
	145	priv->soc_data = match->data;
	146
	147	priv->emac.clk = devm_clk_get(dev, "hclk");
	148	if (IS_ERR(priv->emac.clk)) {
663713eb CW	149	dev_err(dev, "failed to retrieve host clock (%ld)\n",
663713eb CW	150	PTR_ERR(priv->emac.clk));
6eacf311 RP	151	err = PTR_ERR(priv->emac.clk);
	152	goto out_netdev;
	153	}
	154
	155	priv->refclk = devm_clk_get(dev, "macref");
	156	if (IS_ERR(priv->refclk)) {
663713eb CW	157	dev_err(dev, "failed to retrieve reference clock (%ld)\n",
663713eb CW	158	PTR_ERR(priv->refclk));
6eacf311 RP	159	err = PTR_ERR(priv->refclk);
	160	goto out_netdev;
	161	}
	162
	163	err = clk_prepare_enable(priv->refclk);
	164	if (err) {
	165	dev_err(dev, "failed to enable reference clock (%d)\n", err);
	166	goto out_netdev;
	167	}
	168
	169	/* Optional regulator for PHY */
	170	priv->regulator = devm_regulator_get_optional(dev, "phy");
	171	if (IS_ERR(priv->regulator)) {
00777fac CJ	172	if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
	173	err = -EPROBE_DEFER;
	174	goto out_clk_disable;
	175	}
6eacf311 RP	176	dev_err(dev, "no regulator found\n");
	177	priv->regulator = NULL;
	178	}
	179
	180	if (priv->regulator) {
	181	err = regulator_enable(priv->regulator);
	182	if (err) {
	183	dev_err(dev, "failed to enable phy-supply (%d)\n", err);
	184	goto out_clk_disable;
	185	}
	186	}
	187
f4c9d3ee XZ	188	/* Set speed 100M */
	189	data = (1 << (priv->soc_data->grf_speed_offset + 16)) \|
	190	(1 << priv->soc_data->grf_speed_offset);
	191	/* Set RMII mode */
	192	data \|= (1 << (priv->soc_data->grf_mode_offset + 16)) \|
	193	(0 << priv->soc_data->grf_mode_offset);
6eacf311 RP	194
	195	err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
	196	if (err) {
663713eb CW	197	dev_err(dev, "unable to apply initial settings to grf (%d)\n",
663713eb CW	198	err);
6eacf311 RP	199	goto out_regulator_disable;
	200	}
	201
	202	/* RMII interface needs always a rate of 50MHz */
	203	err = clk_set_rate(priv->refclk, 50000000);
2a9ee696	204	if (err) {
663713eb CW	205	dev_err(dev,
663713eb CW	206	"failed to change reference clock rate (%d)\n", err);
2a9ee696 BR	207	goto out_regulator_disable;
2a9ee696 BR	208	}
c9bca2fe	209
f4c9d3ee XZ	210	if (priv->soc_data->need_div_macclk) {
	211	priv->macclk = devm_clk_get(dev, "macclk");
	212	if (IS_ERR(priv->macclk)) {
663713eb CW	213	dev_err(dev, "failed to retrieve mac clock (%ld)\n",
663713eb CW	214	PTR_ERR(priv->macclk));
f4c9d3ee XZ	215	err = PTR_ERR(priv->macclk);
	216	goto out_regulator_disable;
	217	}
	218
	219	err = clk_prepare_enable(priv->macclk);
	220	if (err) {
	221	dev_err(dev, "failed to enable mac clock (%d)\n", err);
	222	goto out_regulator_disable;
	223	}
	224
	225	/* RMII TX/RX needs always a rate of 25MHz */
	226	err = clk_set_rate(priv->macclk, 25000000);
e46772a6	227	if (err) {
663713eb CW	228	dev_err(dev,
663713eb CW	229	"failed to change mac clock rate (%d)\n", err);
e46772a6 BR	230	goto out_clk_disable_macclk;
e46772a6 BR	231	}
f4c9d3ee XZ	232	}
f4c9d3ee XZ	233
c9bca2fe XZ	234	err = arc_emac_probe(ndev, interface);
	235	if (err) {
	236	dev_err(dev, "failed to probe arc emac (%d)\n", err);
2a9ee696	237	goto out_clk_disable_macclk;
c9bca2fe XZ	238	}
c9bca2fe XZ	239
6eacf311	240	return 0;
2a9ee696	241
e46772a6	242	out_clk_disable_macclk:
2a9ee696 BR	243	if (priv->soc_data->need_div_macclk)
2a9ee696 BR	244	clk_disable_unprepare(priv->macclk);
6eacf311 RP	245	out_regulator_disable:
	246	if (priv->regulator)
	247	regulator_disable(priv->regulator);
	248	out_clk_disable:
	249	clk_disable_unprepare(priv->refclk);
	250	out_netdev:
	251	free_netdev(ndev);
	252	return err;
	253	}
	254
	255	static int emac_rockchip_remove(struct platform_device *pdev)
	256	{
	257	struct net_device *ndev = platform_get_drvdata(pdev);
	258	struct rockchip_priv_data *priv = netdev_priv(ndev);
	259	int err;
	260
cf98192d RP	261	err = arc_emac_remove(ndev);
cf98192d RP	262
6eacf311 RP	263	clk_disable_unprepare(priv->refclk);
	264
	265	if (priv->regulator)
	266	regulator_disable(priv->regulator);
	267
6eacf311 RP	268	free_netdev(ndev);
	269	return err;
	270	}
	271
	272	static struct platform_driver emac_rockchip_driver = {
	273	.probe = emac_rockchip_probe,
	274	.remove = emac_rockchip_remove,
	275	.driver = {
	276	.name = DRV_NAME,
	277	.of_match_table = emac_rockchip_dt_ids,
	278	},
	279	};
	280
	281	module_platform_driver(emac_rockchip_driver);
	282
	283	MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
	284	MODULE_DESCRIPTION("Rockchip EMAC platform driver");
	285	MODULE_LICENSE("GPL");