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f3cc28c7 JC |
1 | /* |
2 | * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. | |
305282ba | 3 | * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> |
e8f720fd | 4 | * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> |
f3cc28c7 JC |
5 | * |
6 | * Derived from Intel e1000 driver | |
7 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the Free | |
11 | * Software Foundation; either version 2 of the License, or (at your option) | |
12 | * any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
21 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called COPYING. | |
25 | * | |
26 | * Contact Information: | |
c8f2d9bc JC |
27 | * Xiong Huang <xiong.huang@atheros.com> |
28 | * Jie Yang <jie.yang@atheros.com> | |
f3cc28c7 JC |
29 | * Chris Snook <csnook@redhat.com> |
30 | * Jay Cliburn <jcliburn@gmail.com> | |
31 | * | |
c8f2d9bc | 32 | * This version is adapted from the Attansic reference driver. |
f3cc28c7 JC |
33 | * |
34 | * TODO: | |
53ffb42c | 35 | * Add more ethtool functions. |
f3cc28c7 JC |
36 | * Fix abstruse irq enable/disable condition described here: |
37 | * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 | |
38 | * | |
39 | * NEEDS TESTING: | |
40 | * VLAN | |
41 | * multicast | |
42 | * promiscuous mode | |
43 | * interrupt coalescing | |
44 | * SMP torture testing | |
45 | */ | |
46 | ||
60063497 | 47 | #include <linux/atomic.h> |
305282ba JC |
48 | #include <asm/byteorder.h> |
49 | ||
50 | #include <linux/compiler.h> | |
51 | #include <linux/crc32.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/dma-mapping.h> | |
f3cc28c7 | 54 | #include <linux/etherdevice.h> |
f3cc28c7 | 55 | #include <linux/hardirq.h> |
305282ba JC |
56 | #include <linux/if_ether.h> |
57 | #include <linux/if_vlan.h> | |
58 | #include <linux/in.h> | |
f3cc28c7 | 59 | #include <linux/interrupt.h> |
305282ba | 60 | #include <linux/ip.h> |
f3cc28c7 | 61 | #include <linux/irqflags.h> |
305282ba JC |
62 | #include <linux/irqreturn.h> |
63 | #include <linux/jiffies.h> | |
64 | #include <linux/mii.h> | |
65 | #include <linux/module.h> | |
66 | #include <linux/moduleparam.h> | |
f3cc28c7 | 67 | #include <linux/net.h> |
305282ba JC |
68 | #include <linux/netdevice.h> |
69 | #include <linux/pci.h> | |
70 | #include <linux/pci_ids.h> | |
f3cc28c7 | 71 | #include <linux/pm.h> |
305282ba JC |
72 | #include <linux/skbuff.h> |
73 | #include <linux/slab.h> | |
74 | #include <linux/spinlock.h> | |
75 | #include <linux/string.h> | |
f3cc28c7 | 76 | #include <linux/tcp.h> |
305282ba JC |
77 | #include <linux/timer.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/workqueue.h> | |
f3cc28c7 | 80 | |
f3cc28c7 JC |
81 | #include <net/checksum.h> |
82 | ||
f3cc28c7 JC |
83 | #include "atl1.h" |
84 | ||
5ad18900 | 85 | #define ATLX_DRIVER_VERSION "2.1.3" |
85ee7a1d JP |
86 | MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, " |
87 | "Chris Snook <csnook@redhat.com>, " | |
88 | "Jay Cliburn <jcliburn@gmail.com>"); | |
5ad18900 AC |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_VERSION(ATLX_DRIVER_VERSION); | |
91 | ||
305282ba JC |
92 | /* Temporary hack for merging atl1 and atl2 */ |
93 | #include "atlx.c" | |
f3cc28c7 | 94 | |
ff2d8d6c | 95 | static const struct ethtool_ops atl1_ethtool_ops; |
96 | ||
8ec7226a CS |
97 | /* |
98 | * This is the only thing that needs to be changed to adjust the | |
99 | * maximum number of ports that the driver can manage. | |
100 | */ | |
101 | #define ATL1_MAX_NIC 4 | |
102 | ||
103 | #define OPTION_UNSET -1 | |
104 | #define OPTION_DISABLED 0 | |
105 | #define OPTION_ENABLED 1 | |
106 | ||
107 | #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } | |
108 | ||
109 | /* | |
110 | * Interrupt Moderate Timer in units of 2 us | |
111 | * | |
112 | * Valid Range: 10-65535 | |
113 | * | |
114 | * Default Value: 100 (200us) | |
115 | */ | |
093d369d | 116 | static int int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; |
b79d8fff | 117 | static unsigned int num_int_mod_timer; |
8ec7226a CS |
118 | module_param_array_named(int_mod_timer, int_mod_timer, int, |
119 | &num_int_mod_timer, 0); | |
120 | MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); | |
121 | ||
122 | #define DEFAULT_INT_MOD_CNT 100 /* 200us */ | |
123 | #define MAX_INT_MOD_CNT 65000 | |
124 | #define MIN_INT_MOD_CNT 50 | |
125 | ||
126 | struct atl1_option { | |
127 | enum { enable_option, range_option, list_option } type; | |
128 | char *name; | |
129 | char *err; | |
130 | int def; | |
131 | union { | |
132 | struct { /* range_option info */ | |
133 | int min; | |
134 | int max; | |
135 | } r; | |
136 | struct { /* list_option info */ | |
137 | int nr; | |
138 | struct atl1_opt_list { | |
139 | int i; | |
140 | char *str; | |
141 | } *p; | |
142 | } l; | |
143 | } arg; | |
144 | }; | |
145 | ||
093d369d | 146 | static int atl1_validate_option(int *value, struct atl1_option *opt, |
1dd06ae8 | 147 | struct pci_dev *pdev) |
8ec7226a CS |
148 | { |
149 | if (*value == OPTION_UNSET) { | |
150 | *value = opt->def; | |
151 | return 0; | |
152 | } | |
153 | ||
154 | switch (opt->type) { | |
155 | case enable_option: | |
156 | switch (*value) { | |
157 | case OPTION_ENABLED: | |
158 | dev_info(&pdev->dev, "%s enabled\n", opt->name); | |
159 | return 0; | |
160 | case OPTION_DISABLED: | |
161 | dev_info(&pdev->dev, "%s disabled\n", opt->name); | |
162 | return 0; | |
163 | } | |
164 | break; | |
165 | case range_option: | |
166 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | |
167 | dev_info(&pdev->dev, "%s set to %i\n", opt->name, | |
168 | *value); | |
169 | return 0; | |
170 | } | |
171 | break; | |
172 | case list_option:{ | |
173 | int i; | |
174 | struct atl1_opt_list *ent; | |
175 | ||
176 | for (i = 0; i < opt->arg.l.nr; i++) { | |
177 | ent = &opt->arg.l.p[i]; | |
178 | if (*value == ent->i) { | |
179 | if (ent->str[0] != '\0') | |
180 | dev_info(&pdev->dev, "%s\n", | |
181 | ent->str); | |
182 | return 0; | |
183 | } | |
184 | } | |
185 | } | |
186 | break; | |
187 | ||
188 | default: | |
189 | break; | |
190 | } | |
191 | ||
192 | dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", | |
193 | opt->name, *value, opt->err); | |
194 | *value = opt->def; | |
195 | return -1; | |
196 | } | |
197 | ||
49ce9c2c | 198 | /** |
8ec7226a CS |
199 | * atl1_check_options - Range Checking for Command Line Parameters |
200 | * @adapter: board private structure | |
201 | * | |
202 | * This routine checks all command line parameters for valid user | |
203 | * input. If an invalid value is given, or if no user specified | |
204 | * value exists, a default value is used. The final value is stored | |
205 | * in a variable in the adapter structure. | |
206 | */ | |
093d369d | 207 | static void atl1_check_options(struct atl1_adapter *adapter) |
8ec7226a CS |
208 | { |
209 | struct pci_dev *pdev = adapter->pdev; | |
210 | int bd = adapter->bd_number; | |
211 | if (bd >= ATL1_MAX_NIC) { | |
212 | dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); | |
213 | dev_notice(&pdev->dev, "using defaults for all values\n"); | |
214 | } | |
215 | { /* Interrupt Moderate Timer */ | |
216 | struct atl1_option opt = { | |
217 | .type = range_option, | |
218 | .name = "Interrupt Moderator Timer", | |
219 | .err = "using default of " | |
220 | __MODULE_STRING(DEFAULT_INT_MOD_CNT), | |
221 | .def = DEFAULT_INT_MOD_CNT, | |
222 | .arg = {.r = {.min = MIN_INT_MOD_CNT, | |
223 | .max = MAX_INT_MOD_CNT} } | |
224 | }; | |
225 | int val; | |
226 | if (num_int_mod_timer > bd) { | |
227 | val = int_mod_timer[bd]; | |
228 | atl1_validate_option(&val, &opt, pdev); | |
229 | adapter->imt = (u16) val; | |
230 | } else | |
231 | adapter->imt = (u16) (opt.def); | |
232 | } | |
233 | } | |
234 | ||
f3cc28c7 JC |
235 | /* |
236 | * atl1_pci_tbl - PCI Device ID Table | |
237 | */ | |
9baa3c34 | 238 | static const struct pci_device_id atl1_pci_tbl[] = { |
e81e557a | 239 | {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, |
f3cc28c7 JC |
240 | /* required last entry */ |
241 | {0,} | |
242 | }; | |
f3cc28c7 JC |
243 | MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); |
244 | ||
460578bf JC |
245 | static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | |
246 | NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; | |
247 | ||
248 | static int debug = -1; | |
249 | module_param(debug, int, 0); | |
250 | MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); | |
251 | ||
f3cc28c7 | 252 | /* |
6446a860 JC |
253 | * Reset the transmit and receive units; mask and clear all interrupts. |
254 | * hw - Struct containing variables accessed by shared code | |
255 | * return : 0 or idle status (if error) | |
f3cc28c7 | 256 | */ |
6446a860 | 257 | static s32 atl1_reset_hw(struct atl1_hw *hw) |
f3cc28c7 | 258 | { |
6446a860 JC |
259 | struct pci_dev *pdev = hw->back->pdev; |
260 | struct atl1_adapter *adapter = hw->back; | |
261 | u32 icr; | |
262 | int i; | |
f3cc28c7 | 263 | |
6446a860 JC |
264 | /* |
265 | * Clear Interrupt mask to stop board from generating | |
266 | * interrupts & Clear any pending interrupt events | |
267 | */ | |
268 | /* | |
5c3d52ef | 269 | * atlx_irq_disable(adapter); |
6446a860 JC |
270 | * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); |
271 | */ | |
f3cc28c7 | 272 | |
6446a860 JC |
273 | /* |
274 | * Issue Soft Reset to the MAC. This will reset the chip's | |
275 | * transmit, receive, DMA. It will not effect | |
276 | * the current PCI configuration. The global reset bit is self- | |
277 | * clearing, and should clear within a microsecond. | |
278 | */ | |
279 | iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); | |
280 | ioread32(hw->hw_addr + REG_MASTER_CTRL); | |
f3cc28c7 | 281 | |
6446a860 JC |
282 | iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); |
283 | ioread16(hw->hw_addr + REG_PHY_ENABLE); | |
f3cc28c7 | 284 | |
6446a860 JC |
285 | /* delay about 1ms */ |
286 | msleep(1); | |
f3cc28c7 | 287 | |
6446a860 JC |
288 | /* Wait at least 10ms for All module to be Idle */ |
289 | for (i = 0; i < 10; i++) { | |
290 | icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); | |
291 | if (!icr) | |
292 | break; | |
293 | /* delay 1 ms */ | |
294 | msleep(1); | |
295 | /* FIXME: still the right way to do this? */ | |
296 | cpu_relax(); | |
297 | } | |
05ffdd7b | 298 | |
6446a860 JC |
299 | if (icr) { |
300 | if (netif_msg_hw(adapter)) | |
301 | dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); | |
302 | return icr; | |
303 | } | |
05ffdd7b | 304 | |
6446a860 | 305 | return 0; |
05ffdd7b JC |
306 | } |
307 | ||
6446a860 JC |
308 | /* function about EEPROM |
309 | * | |
310 | * check_eeprom_exist | |
311 | * return 0 if eeprom exist | |
312 | */ | |
313 | static int atl1_check_eeprom_exist(struct atl1_hw *hw) | |
05ffdd7b | 314 | { |
6446a860 JC |
315 | u32 value; |
316 | value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
317 | if (value & SPI_FLASH_CTRL_EN_VPD) { | |
318 | value &= ~SPI_FLASH_CTRL_EN_VPD; | |
319 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); | |
320 | } | |
05ffdd7b | 321 | |
6446a860 JC |
322 | value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); |
323 | return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | |
05ffdd7b JC |
324 | } |
325 | ||
6446a860 | 326 | static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) |
05ffdd7b | 327 | { |
6446a860 JC |
328 | int i; |
329 | u32 control; | |
05ffdd7b | 330 | |
6446a860 JC |
331 | if (offset & 3) |
332 | /* address do not align */ | |
333 | return false; | |
05ffdd7b | 334 | |
6446a860 JC |
335 | iowrite32(0, hw->hw_addr + REG_VPD_DATA); |
336 | control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | |
337 | iowrite32(control, hw->hw_addr + REG_VPD_CAP); | |
338 | ioread32(hw->hw_addr + REG_VPD_CAP); | |
05ffdd7b | 339 | |
6446a860 JC |
340 | for (i = 0; i < 10; i++) { |
341 | msleep(2); | |
342 | control = ioread32(hw->hw_addr + REG_VPD_CAP); | |
343 | if (control & VPD_CAP_VPD_FLAG) | |
344 | break; | |
345 | } | |
346 | if (control & VPD_CAP_VPD_FLAG) { | |
347 | *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); | |
348 | return true; | |
349 | } | |
350 | /* timeout */ | |
351 | return false; | |
05ffdd7b JC |
352 | } |
353 | ||
f3cc28c7 | 354 | /* |
6446a860 JC |
355 | * Reads the value from a PHY register |
356 | * hw - Struct containing variables accessed by shared code | |
357 | * reg_addr - address of the PHY register to read | |
f3cc28c7 | 358 | */ |
ff2d8d6c | 359 | static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) |
f3cc28c7 | 360 | { |
6446a860 JC |
361 | u32 val; |
362 | int i; | |
f3cc28c7 | 363 | |
6446a860 JC |
364 | val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | |
365 | MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << | |
366 | MDIO_CLK_SEL_SHIFT; | |
367 | iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); | |
368 | ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
f3cc28c7 | 369 | |
6446a860 JC |
370 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { |
371 | udelay(2); | |
372 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
373 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
374 | break; | |
375 | } | |
376 | if (!(val & (MDIO_START | MDIO_BUSY))) { | |
377 | *phy_data = (u16) val; | |
378 | return 0; | |
f3cc28c7 | 379 | } |
6446a860 JC |
380 | return ATLX_ERR_PHY; |
381 | } | |
f3cc28c7 | 382 | |
6446a860 JC |
383 | #define CUSTOM_SPI_CS_SETUP 2 |
384 | #define CUSTOM_SPI_CLK_HI 2 | |
385 | #define CUSTOM_SPI_CLK_LO 2 | |
386 | #define CUSTOM_SPI_CS_HOLD 2 | |
387 | #define CUSTOM_SPI_CS_HI 3 | |
f3cc28c7 | 388 | |
6446a860 JC |
389 | static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) |
390 | { | |
391 | int i; | |
392 | u32 value; | |
f3cc28c7 | 393 | |
6446a860 JC |
394 | iowrite32(0, hw->hw_addr + REG_SPI_DATA); |
395 | iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); | |
2ca13da7 | 396 | |
6446a860 JC |
397 | value = SPI_FLASH_CTRL_WAIT_READY | |
398 | (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << | |
399 | SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & | |
400 | SPI_FLASH_CTRL_CLK_HI_MASK) << | |
401 | SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & | |
402 | SPI_FLASH_CTRL_CLK_LO_MASK) << | |
403 | SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & | |
404 | SPI_FLASH_CTRL_CS_HOLD_MASK) << | |
405 | SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & | |
406 | SPI_FLASH_CTRL_CS_HI_MASK) << | |
407 | SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << | |
408 | SPI_FLASH_CTRL_INS_SHIFT; | |
f3cc28c7 | 409 | |
6446a860 | 410 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); |
f3cc28c7 | 411 | |
6446a860 JC |
412 | value |= SPI_FLASH_CTRL_START; |
413 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); | |
414 | ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
f3cc28c7 | 415 | |
6446a860 JC |
416 | for (i = 0; i < 10; i++) { |
417 | msleep(1); | |
418 | value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
419 | if (!(value & SPI_FLASH_CTRL_START)) | |
420 | break; | |
421 | } | |
f3cc28c7 | 422 | |
6446a860 JC |
423 | if (value & SPI_FLASH_CTRL_START) |
424 | return false; | |
f3cc28c7 | 425 | |
6446a860 | 426 | *buf = ioread32(hw->hw_addr + REG_SPI_DATA); |
2ca13da7 | 427 | |
6446a860 | 428 | return true; |
f3cc28c7 JC |
429 | } |
430 | ||
f3cc28c7 | 431 | /* |
6446a860 JC |
432 | * get_permanent_address |
433 | * return 0 if get valid mac address, | |
f3cc28c7 | 434 | */ |
6446a860 | 435 | static int atl1_get_permanent_address(struct atl1_hw *hw) |
f3cc28c7 | 436 | { |
6446a860 JC |
437 | u32 addr[2]; |
438 | u32 i, control; | |
439 | u16 reg; | |
440 | u8 eth_addr[ETH_ALEN]; | |
441 | bool key_valid; | |
f3cc28c7 | 442 | |
6446a860 JC |
443 | if (is_valid_ether_addr(hw->perm_mac_addr)) |
444 | return 0; | |
445 | ||
446 | /* init */ | |
447 | addr[0] = addr[1] = 0; | |
448 | ||
449 | if (!atl1_check_eeprom_exist(hw)) { | |
450 | reg = 0; | |
451 | key_valid = false; | |
452 | /* Read out all EEPROM content */ | |
453 | i = 0; | |
454 | while (1) { | |
455 | if (atl1_read_eeprom(hw, i + 0x100, &control)) { | |
456 | if (key_valid) { | |
457 | if (reg == REG_MAC_STA_ADDR) | |
458 | addr[0] = control; | |
459 | else if (reg == (REG_MAC_STA_ADDR + 4)) | |
460 | addr[1] = control; | |
461 | key_valid = false; | |
462 | } else if ((control & 0xff) == 0x5A) { | |
463 | key_valid = true; | |
464 | reg = (u16) (control >> 16); | |
465 | } else | |
466 | break; | |
467 | } else | |
468 | /* read error */ | |
469 | break; | |
470 | i += 4; | |
05ffdd7b | 471 | } |
6446a860 JC |
472 | |
473 | *(u32 *) ð_addr[2] = swab32(addr[0]); | |
474 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
475 | if (is_valid_ether_addr(eth_addr)) { | |
476 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
477 | return 0; | |
05ffdd7b JC |
478 | } |
479 | } | |
f3cc28c7 | 480 | |
6446a860 JC |
481 | /* see if SPI FLAGS exist ? */ |
482 | addr[0] = addr[1] = 0; | |
483 | reg = 0; | |
484 | key_valid = false; | |
485 | i = 0; | |
486 | while (1) { | |
487 | if (atl1_spi_read(hw, i + 0x1f000, &control)) { | |
488 | if (key_valid) { | |
489 | if (reg == REG_MAC_STA_ADDR) | |
490 | addr[0] = control; | |
491 | else if (reg == (REG_MAC_STA_ADDR + 4)) | |
492 | addr[1] = control; | |
493 | key_valid = false; | |
494 | } else if ((control & 0xff) == 0x5A) { | |
495 | key_valid = true; | |
496 | reg = (u16) (control >> 16); | |
497 | } else | |
498 | /* data end */ | |
499 | break; | |
500 | } else | |
501 | /* read error */ | |
502 | break; | |
503 | i += 4; | |
504 | } | |
f3cc28c7 | 505 | |
6446a860 JC |
506 | *(u32 *) ð_addr[2] = swab32(addr[0]); |
507 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
508 | if (is_valid_ether_addr(eth_addr)) { | |
509 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
510 | return 0; | |
511 | } | |
f3cc28c7 | 512 | |
6446a860 JC |
513 | /* |
514 | * On some motherboards, the MAC address is written by the | |
515 | * BIOS directly to the MAC register during POST, and is | |
516 | * not stored in eeprom. If all else thus far has failed | |
517 | * to fetch the permanent MAC address, try reading it directly. | |
518 | */ | |
519 | addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); | |
520 | addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); | |
521 | *(u32 *) ð_addr[2] = swab32(addr[0]); | |
522 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
523 | if (is_valid_ether_addr(eth_addr)) { | |
524 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
525 | return 0; | |
526 | } | |
f3cc28c7 | 527 | |
6446a860 | 528 | return 1; |
f3cc28c7 JC |
529 | } |
530 | ||
05ffdd7b | 531 | /* |
6446a860 JC |
532 | * Reads the adapter's MAC address from the EEPROM |
533 | * hw - Struct containing variables accessed by shared code | |
05ffdd7b | 534 | */ |
9dc20f55 | 535 | static s32 atl1_read_mac_addr(struct atl1_hw *hw) |
f3cc28c7 | 536 | { |
6a214fd4 | 537 | s32 ret = 0; |
6446a860 | 538 | u16 i; |
f3cc28c7 | 539 | |
6a214fd4 | 540 | if (atl1_get_permanent_address(hw)) { |
7efd26d0 | 541 | eth_random_addr(hw->perm_mac_addr); |
6a214fd4 DK |
542 | ret = 1; |
543 | } | |
f3cc28c7 | 544 | |
6446a860 JC |
545 | for (i = 0; i < ETH_ALEN; i++) |
546 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
6a214fd4 | 547 | return ret; |
f3cc28c7 JC |
548 | } |
549 | ||
550 | /* | |
6446a860 JC |
551 | * Hashes an address to determine its location in the multicast table |
552 | * hw - Struct containing variables accessed by shared code | |
553 | * mc_addr - the multicast address to hash | |
05ffdd7b | 554 | * |
6446a860 JC |
555 | * atl1_hash_mc_addr |
556 | * purpose | |
557 | * set hash value for a multicast address | |
558 | * hash calcu processing : | |
559 | * 1. calcu 32bit CRC for multicast address | |
560 | * 2. reverse crc with MSB to LSB | |
f3cc28c7 | 561 | */ |
ff2d8d6c | 562 | static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) |
f3cc28c7 | 563 | { |
6446a860 JC |
564 | u32 crc32, value = 0; |
565 | int i; | |
f3cc28c7 | 566 | |
6446a860 JC |
567 | crc32 = ether_crc_le(6, mc_addr); |
568 | for (i = 0; i < 32; i++) | |
569 | value |= (((crc32 >> i) & 1) << (31 - i)); | |
f3cc28c7 | 570 | |
6446a860 | 571 | return value; |
f3cc28c7 JC |
572 | } |
573 | ||
6446a860 JC |
574 | /* |
575 | * Sets the bit in the multicast table corresponding to the hash value. | |
576 | * hw - Struct containing variables accessed by shared code | |
577 | * hash_value - Multicast address hash value | |
578 | */ | |
ff2d8d6c | 579 | static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) |
f3cc28c7 | 580 | { |
6446a860 JC |
581 | u32 hash_bit, hash_reg; |
582 | u32 mta; | |
583 | ||
584 | /* | |
585 | * The HASH Table is a register array of 2 32-bit registers. | |
586 | * It is treated like an array of 64 bits. We want to set | |
587 | * bit BitArray[hash_value]. So we figure out what register | |
588 | * the bit is in, read it, OR in the new bit, then write | |
589 | * back the new value. The register is determined by the | |
590 | * upper 7 bits of the hash value and the bit within that | |
591 | * register are determined by the lower 5 bits of the value. | |
05ffdd7b | 592 | */ |
6446a860 JC |
593 | hash_reg = (hash_value >> 31) & 0x1; |
594 | hash_bit = (hash_value >> 26) & 0x1F; | |
595 | mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); | |
596 | mta |= (1 << hash_bit); | |
597 | iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); | |
05ffdd7b | 598 | } |
f3cc28c7 | 599 | |
6446a860 JC |
600 | /* |
601 | * Writes a value to a PHY register | |
602 | * hw - Struct containing variables accessed by shared code | |
603 | * reg_addr - address of the PHY register to write | |
604 | * data - data to write to the PHY | |
605 | */ | |
606 | static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) | |
05ffdd7b | 607 | { |
6446a860 JC |
608 | int i; |
609 | u32 val; | |
f3cc28c7 | 610 | |
6446a860 JC |
611 | val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | |
612 | (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | |
613 | MDIO_SUP_PREAMBLE | | |
614 | MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
615 | iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); | |
616 | ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
f3cc28c7 | 617 | |
6446a860 JC |
618 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { |
619 | udelay(2); | |
620 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
621 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
622 | break; | |
05ffdd7b | 623 | } |
f3cc28c7 | 624 | |
6446a860 | 625 | if (!(val & (MDIO_START | MDIO_BUSY))) |
305282ba | 626 | return 0; |
f3cc28c7 | 627 | |
6446a860 JC |
628 | return ATLX_ERR_PHY; |
629 | } | |
f3cc28c7 | 630 | |
6446a860 JC |
631 | /* |
632 | * Make L001's PHY out of Power Saving State (bug) | |
633 | * hw - Struct containing variables accessed by shared code | |
634 | * when power on, L001's PHY always on Power saving State | |
635 | * (Gigabit Link forbidden) | |
636 | */ | |
637 | static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) | |
638 | { | |
639 | s32 ret; | |
640 | ret = atl1_write_phy_reg(hw, 29, 0x0029); | |
641 | if (ret) | |
642 | return ret; | |
643 | return atl1_write_phy_reg(hw, 30, 0); | |
644 | } | |
645 | ||
6446a860 JC |
646 | /* |
647 | * Resets the PHY and make all config validate | |
648 | * hw - Struct containing variables accessed by shared code | |
649 | * | |
650 | * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) | |
651 | */ | |
652 | static s32 atl1_phy_reset(struct atl1_hw *hw) | |
653 | { | |
654 | struct pci_dev *pdev = hw->back->pdev; | |
655 | struct atl1_adapter *adapter = hw->back; | |
656 | s32 ret_val; | |
657 | u16 phy_data; | |
658 | ||
659 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
660 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
661 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
662 | else { | |
05ffdd7b JC |
663 | switch (hw->media_type) { |
664 | case MEDIA_TYPE_100M_FULL: | |
6446a860 JC |
665 | phy_data = |
666 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
667 | MII_CR_RESET; | |
05ffdd7b JC |
668 | break; |
669 | case MEDIA_TYPE_100M_HALF: | |
670 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
671 | break; | |
672 | case MEDIA_TYPE_10M_FULL: | |
673 | phy_data = | |
674 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
675 | break; | |
305282ba JC |
676 | default: |
677 | /* MEDIA_TYPE_10M_HALF: */ | |
05ffdd7b JC |
678 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; |
679 | break; | |
f3cc28c7 | 680 | } |
f3cc28c7 | 681 | } |
f3cc28c7 | 682 | |
6446a860 JC |
683 | ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
684 | if (ret_val) { | |
685 | u32 val; | |
686 | int i; | |
687 | /* pcie serdes link may be down! */ | |
688 | if (netif_msg_hw(adapter)) | |
689 | dev_dbg(&pdev->dev, "pcie phy link down\n"); | |
690 | ||
691 | for (i = 0; i < 25; i++) { | |
692 | msleep(1); | |
693 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
694 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
695 | break; | |
696 | } | |
f3cc28c7 | 697 | |
6446a860 JC |
698 | if ((val & (MDIO_START | MDIO_BUSY)) != 0) { |
699 | if (netif_msg_hw(adapter)) | |
700 | dev_warn(&pdev->dev, | |
701 | "pcie link down at least 25ms\n"); | |
702 | return ret_val; | |
703 | } | |
704 | } | |
305282ba | 705 | return 0; |
2ca13da7 JC |
706 | } |
707 | ||
6446a860 JC |
708 | /* |
709 | * Configures PHY autoneg and flow control advertisement settings | |
710 | * hw - Struct containing variables accessed by shared code | |
711 | */ | |
712 | static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) | |
05ffdd7b | 713 | { |
6446a860 JC |
714 | s32 ret_val; |
715 | s16 mii_autoneg_adv_reg; | |
716 | s16 mii_1000t_ctrl_reg; | |
f3cc28c7 | 717 | |
6446a860 JC |
718 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
719 | mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | |
f3cc28c7 | 720 | |
6446a860 JC |
721 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
722 | mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; | |
f3cc28c7 | 723 | |
6446a860 JC |
724 | /* |
725 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
726 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
727 | * the 1000Base-T Control Register (Address 9). | |
728 | */ | |
729 | mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | |
730 | mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; | |
f3cc28c7 | 731 | |
6446a860 JC |
732 | /* |
733 | * Need to parse media_type and set up | |
734 | * the appropriate PHY registers. | |
735 | */ | |
736 | switch (hw->media_type) { | |
737 | case MEDIA_TYPE_AUTO_SENSOR: | |
738 | mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | | |
739 | MII_AR_10T_FD_CAPS | | |
740 | MII_AR_100TX_HD_CAPS | | |
741 | MII_AR_100TX_FD_CAPS); | |
742 | mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; | |
743 | break; | |
f3cc28c7 | 744 | |
6446a860 JC |
745 | case MEDIA_TYPE_1000M_FULL: |
746 | mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; | |
747 | break; | |
f3cc28c7 | 748 | |
6446a860 JC |
749 | case MEDIA_TYPE_100M_FULL: |
750 | mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | |
751 | break; | |
f3cc28c7 | 752 | |
6446a860 JC |
753 | case MEDIA_TYPE_100M_HALF: |
754 | mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | |
755 | break; | |
f3cc28c7 | 756 | |
6446a860 JC |
757 | case MEDIA_TYPE_10M_FULL: |
758 | mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | |
05ffdd7b | 759 | break; |
6446a860 | 760 | |
05ffdd7b | 761 | default: |
6446a860 | 762 | mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; |
05ffdd7b | 763 | break; |
f3cc28c7 | 764 | } |
f3cc28c7 | 765 | |
6446a860 JC |
766 | /* flow control fixed to enable all */ |
767 | mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | |
f3cc28c7 | 768 | |
6446a860 JC |
769 | hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; |
770 | hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; | |
f3cc28c7 | 771 | |
6446a860 JC |
772 | ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
773 | if (ret_val) | |
774 | return ret_val; | |
f3cc28c7 | 775 | |
6446a860 JC |
776 | ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); |
777 | if (ret_val) | |
778 | return ret_val; | |
f3cc28c7 | 779 | |
6446a860 | 780 | return 0; |
f3cc28c7 | 781 | } |
f3cc28c7 | 782 | |
05ffdd7b | 783 | /* |
6446a860 JC |
784 | * Configures link settings. |
785 | * hw - Struct containing variables accessed by shared code | |
786 | * Assumes the hardware has previously been reset and the | |
787 | * transmitter and receiver are not enabled. | |
05ffdd7b | 788 | */ |
6446a860 | 789 | static s32 atl1_setup_link(struct atl1_hw *hw) |
f3cc28c7 | 790 | { |
6446a860 JC |
791 | struct pci_dev *pdev = hw->back->pdev; |
792 | struct atl1_adapter *adapter = hw->back; | |
793 | s32 ret_val; | |
f3cc28c7 | 794 | |
6446a860 JC |
795 | /* |
796 | * Options: | |
797 | * PHY will advertise value(s) parsed from | |
798 | * autoneg_advertised and fc | |
799 | * no matter what autoneg is , We will not wait link result. | |
800 | */ | |
801 | ret_val = atl1_phy_setup_autoneg_adv(hw); | |
802 | if (ret_val) { | |
803 | if (netif_msg_link(adapter)) | |
804 | dev_dbg(&pdev->dev, | |
805 | "error setting up autonegotiation\n"); | |
806 | return ret_val; | |
807 | } | |
808 | /* SW.Reset , En-Auto-Neg if needed */ | |
809 | ret_val = atl1_phy_reset(hw); | |
810 | if (ret_val) { | |
811 | if (netif_msg_link(adapter)) | |
812 | dev_dbg(&pdev->dev, "error resetting phy\n"); | |
813 | return ret_val; | |
814 | } | |
815 | hw->phy_configured = true; | |
816 | return ret_val; | |
817 | } | |
f3cc28c7 | 818 | |
6446a860 | 819 | static void atl1_init_flash_opcode(struct atl1_hw *hw) |
f3cc28c7 | 820 | { |
6446a860 JC |
821 | if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) |
822 | /* Atmel */ | |
823 | hw->flash_vendor = 0; | |
f3cc28c7 | 824 | |
6446a860 JC |
825 | /* Init OP table */ |
826 | iowrite8(flash_table[hw->flash_vendor].cmd_program, | |
827 | hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); | |
828 | iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, | |
829 | hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); | |
830 | iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, | |
831 | hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); | |
832 | iowrite8(flash_table[hw->flash_vendor].cmd_rdid, | |
833 | hw->hw_addr + REG_SPI_FLASH_OP_RDID); | |
834 | iowrite8(flash_table[hw->flash_vendor].cmd_wren, | |
835 | hw->hw_addr + REG_SPI_FLASH_OP_WREN); | |
836 | iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, | |
837 | hw->hw_addr + REG_SPI_FLASH_OP_RDSR); | |
838 | iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, | |
839 | hw->hw_addr + REG_SPI_FLASH_OP_WRSR); | |
840 | iowrite8(flash_table[hw->flash_vendor].cmd_read, | |
841 | hw->hw_addr + REG_SPI_FLASH_OP_READ); | |
f3cc28c7 | 842 | } |
f3cc28c7 | 843 | |
6446a860 JC |
844 | /* |
845 | * Performs basic configuration of the adapter. | |
846 | * hw - Struct containing variables accessed by shared code | |
847 | * Assumes that the controller has previously been reset and is in a | |
848 | * post-reset uninitialized state. Initializes multicast table, | |
849 | * and Calls routines to setup link | |
850 | * Leaves the transmit and receive units disabled and uninitialized. | |
851 | */ | |
852 | static s32 atl1_init_hw(struct atl1_hw *hw) | |
05ffdd7b | 853 | { |
6446a860 | 854 | u32 ret_val = 0; |
f3cc28c7 | 855 | |
6446a860 JC |
856 | /* Zero out the Multicast HASH table */ |
857 | iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); | |
858 | /* clear the old settings from the multicast hash table */ | |
859 | iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); | |
f3cc28c7 | 860 | |
6446a860 | 861 | atl1_init_flash_opcode(hw); |
f3cc28c7 | 862 | |
6446a860 | 863 | if (!hw->phy_configured) { |
fb914ebf | 864 | /* enable GPHY LinkChange Interrupt */ |
6446a860 JC |
865 | ret_val = atl1_write_phy_reg(hw, 18, 0xC00); |
866 | if (ret_val) | |
867 | return ret_val; | |
868 | /* make PHY out of power-saving state */ | |
869 | ret_val = atl1_phy_leave_power_saving(hw); | |
870 | if (ret_val) | |
871 | return ret_val; | |
872 | /* Call a subroutine to configure the link */ | |
873 | ret_val = atl1_setup_link(hw); | |
874 | } | |
875 | return ret_val; | |
f3cc28c7 | 876 | } |
f3cc28c7 JC |
877 | |
878 | /* | |
6446a860 JC |
879 | * Detects the current speed and duplex settings of the hardware. |
880 | * hw - Struct containing variables accessed by shared code | |
881 | * speed - Speed of the connection | |
882 | * duplex - Duplex setting of the connection | |
f3cc28c7 | 883 | */ |
6446a860 | 884 | static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) |
f3cc28c7 | 885 | { |
6446a860 JC |
886 | struct pci_dev *pdev = hw->back->pdev; |
887 | struct atl1_adapter *adapter = hw->back; | |
888 | s32 ret_val; | |
889 | u16 phy_data; | |
f3cc28c7 | 890 | |
6446a860 JC |
891 | /* ; --- Read PHY Specific Status Register (17) */ |
892 | ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); | |
893 | if (ret_val) | |
894 | return ret_val; | |
f3cc28c7 | 895 | |
6446a860 JC |
896 | if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) |
897 | return ATLX_ERR_PHY_RES; | |
f3cc28c7 | 898 | |
6446a860 JC |
899 | switch (phy_data & MII_ATLX_PSSR_SPEED) { |
900 | case MII_ATLX_PSSR_1000MBS: | |
901 | *speed = SPEED_1000; | |
902 | break; | |
903 | case MII_ATLX_PSSR_100MBS: | |
904 | *speed = SPEED_100; | |
905 | break; | |
906 | case MII_ATLX_PSSR_10MBS: | |
907 | *speed = SPEED_10; | |
908 | break; | |
909 | default: | |
910 | if (netif_msg_hw(adapter)) | |
911 | dev_dbg(&pdev->dev, "error getting speed\n"); | |
912 | return ATLX_ERR_PHY_SPEED; | |
f3cc28c7 | 913 | } |
6446a860 JC |
914 | if (phy_data & MII_ATLX_PSSR_DPLX) |
915 | *duplex = FULL_DUPLEX; | |
916 | else | |
917 | *duplex = HALF_DUPLEX; | |
918 | ||
919 | return 0; | |
05ffdd7b | 920 | } |
f3cc28c7 | 921 | |
ff2d8d6c | 922 | static void atl1_set_mac_addr(struct atl1_hw *hw) |
05ffdd7b | 923 | { |
6446a860 JC |
924 | u32 value; |
925 | /* | |
926 | * 00-0B-6A-F6-00-DC | |
927 | * 0: 6AF600DC 1: 000B | |
928 | * low dword | |
929 | */ | |
930 | value = (((u32) hw->mac_addr[2]) << 24) | | |
931 | (((u32) hw->mac_addr[3]) << 16) | | |
932 | (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); | |
933 | iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); | |
934 | /* high dword */ | |
935 | value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); | |
936 | iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); | |
05ffdd7b | 937 | } |
f3cc28c7 | 938 | |
49ce9c2c | 939 | /** |
f3cc28c7 JC |
940 | * atl1_sw_init - Initialize general software structures (struct atl1_adapter) |
941 | * @adapter: board private structure to initialize | |
942 | * | |
943 | * atl1_sw_init initializes the Adapter private data structure. | |
944 | * Fields are initialized based on PCI device information and | |
945 | * OS network device settings (MTU size). | |
946 | */ | |
093d369d | 947 | static int atl1_sw_init(struct atl1_adapter *adapter) |
f3cc28c7 JC |
948 | { |
949 | struct atl1_hw *hw = &adapter->hw; | |
950 | struct net_device *netdev = adapter->netdev; | |
f3cc28c7 | 951 | |
2a49128f | 952 | hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
a3093d9b | 953 | hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
f3cc28c7 JC |
954 | |
955 | adapter->wol = 0; | |
dd68153d | 956 | device_set_wakeup_enable(&adapter->pdev->dev, false); |
f3cc28c7 | 957 | adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; |
6446a860 | 958 | adapter->ict = 50000; /* 100ms */ |
f3cc28c7 JC |
959 | adapter->link_speed = SPEED_0; /* hardware init */ |
960 | adapter->link_duplex = FULL_DUPLEX; | |
961 | ||
962 | hw->phy_configured = false; | |
963 | hw->preamble_len = 7; | |
964 | hw->ipgt = 0x60; | |
965 | hw->min_ifg = 0x50; | |
966 | hw->ipgr1 = 0x40; | |
967 | hw->ipgr2 = 0x60; | |
968 | hw->max_retry = 0xf; | |
969 | hw->lcol = 0x37; | |
970 | hw->jam_ipg = 7; | |
971 | hw->rfd_burst = 8; | |
972 | hw->rrd_burst = 8; | |
973 | hw->rfd_fetch_gap = 1; | |
974 | hw->rx_jumbo_th = adapter->rx_buffer_len / 8; | |
975 | hw->rx_jumbo_lkah = 1; | |
976 | hw->rrd_ret_timer = 16; | |
977 | hw->tpd_burst = 4; | |
978 | hw->tpd_fetch_th = 16; | |
979 | hw->txf_burst = 0x100; | |
980 | hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; | |
981 | hw->tpd_fetch_gap = 1; | |
982 | hw->rcb_value = atl1_rcb_64; | |
983 | hw->dma_ord = atl1_dma_ord_enh; | |
984 | hw->dmar_block = atl1_dma_req_256; | |
985 | hw->dmaw_block = atl1_dma_req_256; | |
986 | hw->cmb_rrd = 4; | |
987 | hw->cmb_tpd = 4; | |
988 | hw->cmb_rx_timer = 1; /* about 2us */ | |
989 | hw->cmb_tx_timer = 1; /* about 2us */ | |
990 | hw->smb_timer = 100000; /* about 200ms */ | |
991 | ||
f3cc28c7 JC |
992 | spin_lock_init(&adapter->lock); |
993 | spin_lock_init(&adapter->mb_lock); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
05ffdd7b JC |
998 | static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) |
999 | { | |
1000 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
1001 | u16 result; | |
1002 | ||
1003 | atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); | |
1004 | ||
1005 | return result; | |
1006 | } | |
1007 | ||
1008 | static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, | |
1009 | int val) | |
1010 | { | |
1011 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
1012 | ||
1013 | atl1_write_phy_reg(&adapter->hw, reg_num, val); | |
1014 | } | |
1015 | ||
05ffdd7b JC |
1016 | static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1017 | { | |
1018 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
1019 | unsigned long flags; | |
1020 | int retval; | |
1021 | ||
1022 | if (!netif_running(netdev)) | |
1023 | return -EINVAL; | |
1024 | ||
1025 | spin_lock_irqsave(&adapter->lock, flags); | |
1026 | retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); | |
1027 | spin_unlock_irqrestore(&adapter->lock, flags); | |
1028 | ||
1029 | return retval; | |
1030 | } | |
1031 | ||
49ce9c2c | 1032 | /** |
f3cc28c7 JC |
1033 | * atl1_setup_mem_resources - allocate Tx / RX descriptor resources |
1034 | * @adapter: board private structure | |
1035 | * | |
1036 | * Return 0 on success, negative on failure | |
1037 | */ | |
6446a860 | 1038 | static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) |
f3cc28c7 JC |
1039 | { |
1040 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; | |
1041 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1042 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1043 | struct atl1_ring_header *ring_header = &adapter->ring_header; | |
1044 | struct pci_dev *pdev = adapter->pdev; | |
1045 | int size; | |
1046 | u8 offset = 0; | |
1047 | ||
1048 | size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); | |
1049 | tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); | |
1050 | if (unlikely(!tpd_ring->buffer_info)) { | |
6446a860 JC |
1051 | if (netif_msg_drv(adapter)) |
1052 | dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", | |
1053 | size); | |
f3cc28c7 JC |
1054 | goto err_nomem; |
1055 | } | |
1056 | rfd_ring->buffer_info = | |
64699336 | 1057 | (tpd_ring->buffer_info + tpd_ring->count); |
f3cc28c7 | 1058 | |
6446a860 JC |
1059 | /* |
1060 | * real ring DMA buffer | |
53ffb42c JC |
1061 | * each ring/block may need up to 8 bytes for alignment, hence the |
1062 | * additional 40 bytes tacked onto the end. | |
1063 | */ | |
1064 | ring_header->size = size = | |
1065 | sizeof(struct tx_packet_desc) * tpd_ring->count | |
1066 | + sizeof(struct rx_free_desc) * rfd_ring->count | |
1067 | + sizeof(struct rx_return_desc) * rrd_ring->count | |
1068 | + sizeof(struct coals_msg_block) | |
1069 | + sizeof(struct stats_msg_block) | |
1070 | + 40; | |
f3cc28c7 JC |
1071 | |
1072 | ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, | |
53ffb42c | 1073 | &ring_header->dma); |
f3cc28c7 | 1074 | if (unlikely(!ring_header->desc)) { |
6446a860 JC |
1075 | if (netif_msg_drv(adapter)) |
1076 | dev_err(&pdev->dev, "pci_alloc_consistent failed\n"); | |
f3cc28c7 JC |
1077 | goto err_nomem; |
1078 | } | |
1079 | ||
1080 | memset(ring_header->desc, 0, ring_header->size); | |
1081 | ||
1082 | /* init TPD ring */ | |
1083 | tpd_ring->dma = ring_header->dma; | |
1084 | offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; | |
1085 | tpd_ring->dma += offset; | |
1086 | tpd_ring->desc = (u8 *) ring_header->desc + offset; | |
1087 | tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; | |
f3cc28c7 JC |
1088 | |
1089 | /* init RFD ring */ | |
1090 | rfd_ring->dma = tpd_ring->dma + tpd_ring->size; | |
1091 | offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; | |
1092 | rfd_ring->dma += offset; | |
1093 | rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); | |
1094 | rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; | |
2ca13da7 | 1095 | |
f3cc28c7 JC |
1096 | |
1097 | /* init RRD ring */ | |
1098 | rrd_ring->dma = rfd_ring->dma + rfd_ring->size; | |
1099 | offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; | |
1100 | rrd_ring->dma += offset; | |
1101 | rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); | |
1102 | rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; | |
2ca13da7 | 1103 | |
f3cc28c7 JC |
1104 | |
1105 | /* init CMB */ | |
1106 | adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; | |
1107 | offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; | |
1108 | adapter->cmb.dma += offset; | |
53ffb42c JC |
1109 | adapter->cmb.cmb = (struct coals_msg_block *) |
1110 | ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); | |
f3cc28c7 JC |
1111 | |
1112 | /* init SMB */ | |
1113 | adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); | |
1114 | offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; | |
1115 | adapter->smb.dma += offset; | |
1116 | adapter->smb.smb = (struct stats_msg_block *) | |
53ffb42c JC |
1117 | ((u8 *) adapter->cmb.cmb + |
1118 | (sizeof(struct coals_msg_block) + offset)); | |
f3cc28c7 | 1119 | |
6446a860 | 1120 | return 0; |
f3cc28c7 JC |
1121 | |
1122 | err_nomem: | |
1123 | kfree(tpd_ring->buffer_info); | |
1124 | return -ENOMEM; | |
1125 | } | |
1126 | ||
3d2557f6 | 1127 | static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) |
f3cc28c7 | 1128 | { |
2ca13da7 JC |
1129 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1130 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1131 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
f3cc28c7 | 1132 | |
2ca13da7 JC |
1133 | atomic_set(&tpd_ring->next_to_use, 0); |
1134 | atomic_set(&tpd_ring->next_to_clean, 0); | |
f3cc28c7 | 1135 | |
2ca13da7 JC |
1136 | rfd_ring->next_to_clean = 0; |
1137 | atomic_set(&rfd_ring->next_to_use, 0); | |
1138 | ||
1139 | rrd_ring->next_to_use = 0; | |
1140 | atomic_set(&rrd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1141 | } |
1142 | ||
49ce9c2c | 1143 | /** |
05ffdd7b | 1144 | * atl1_clean_rx_ring - Free RFD Buffers |
f3cc28c7 JC |
1145 | * @adapter: board private structure |
1146 | */ | |
05ffdd7b | 1147 | static void atl1_clean_rx_ring(struct atl1_adapter *adapter) |
f3cc28c7 | 1148 | { |
05ffdd7b JC |
1149 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1150 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1151 | struct atl1_buffer *buffer_info; | |
1152 | struct pci_dev *pdev = adapter->pdev; | |
1153 | unsigned long size; | |
1154 | unsigned int i; | |
f3cc28c7 | 1155 | |
05ffdd7b JC |
1156 | /* Free all the Rx ring sk_buffs */ |
1157 | for (i = 0; i < rfd_ring->count; i++) { | |
1158 | buffer_info = &rfd_ring->buffer_info[i]; | |
1159 | if (buffer_info->dma) { | |
1160 | pci_unmap_page(pdev, buffer_info->dma, | |
1161 | buffer_info->length, PCI_DMA_FROMDEVICE); | |
1162 | buffer_info->dma = 0; | |
1163 | } | |
1164 | if (buffer_info->skb) { | |
1165 | dev_kfree_skb(buffer_info->skb); | |
1166 | buffer_info->skb = NULL; | |
1167 | } | |
1168 | } | |
f3cc28c7 | 1169 | |
05ffdd7b JC |
1170 | size = sizeof(struct atl1_buffer) * rfd_ring->count; |
1171 | memset(rfd_ring->buffer_info, 0, size); | |
f3cc28c7 | 1172 | |
05ffdd7b JC |
1173 | /* Zero out the descriptor ring */ |
1174 | memset(rfd_ring->desc, 0, rfd_ring->size); | |
f3cc28c7 | 1175 | |
05ffdd7b JC |
1176 | rfd_ring->next_to_clean = 0; |
1177 | atomic_set(&rfd_ring->next_to_use, 0); | |
f3cc28c7 | 1178 | |
05ffdd7b JC |
1179 | rrd_ring->next_to_use = 0; |
1180 | atomic_set(&rrd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1181 | } |
1182 | ||
49ce9c2c | 1183 | /** |
05ffdd7b JC |
1184 | * atl1_clean_tx_ring - Free Tx Buffers |
1185 | * @adapter: board private structure | |
1186 | */ | |
1187 | static void atl1_clean_tx_ring(struct atl1_adapter *adapter) | |
f3cc28c7 | 1188 | { |
05ffdd7b JC |
1189 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1190 | struct atl1_buffer *buffer_info; | |
53ffb42c | 1191 | struct pci_dev *pdev = adapter->pdev; |
05ffdd7b JC |
1192 | unsigned long size; |
1193 | unsigned int i; | |
f3cc28c7 | 1194 | |
05ffdd7b JC |
1195 | /* Free all the Tx ring sk_buffs */ |
1196 | for (i = 0; i < tpd_ring->count; i++) { | |
1197 | buffer_info = &tpd_ring->buffer_info[i]; | |
1198 | if (buffer_info->dma) { | |
1199 | pci_unmap_page(pdev, buffer_info->dma, | |
1200 | buffer_info->length, PCI_DMA_TODEVICE); | |
1201 | buffer_info->dma = 0; | |
f3cc28c7 JC |
1202 | } |
1203 | } | |
1204 | ||
05ffdd7b JC |
1205 | for (i = 0; i < tpd_ring->count; i++) { |
1206 | buffer_info = &tpd_ring->buffer_info[i]; | |
1207 | if (buffer_info->skb) { | |
1208 | dev_kfree_skb_any(buffer_info->skb); | |
1209 | buffer_info->skb = NULL; | |
f3cc28c7 | 1210 | } |
f3cc28c7 JC |
1211 | } |
1212 | ||
05ffdd7b JC |
1213 | size = sizeof(struct atl1_buffer) * tpd_ring->count; |
1214 | memset(tpd_ring->buffer_info, 0, size); | |
f3cc28c7 | 1215 | |
05ffdd7b JC |
1216 | /* Zero out the descriptor ring */ |
1217 | memset(tpd_ring->desc, 0, tpd_ring->size); | |
f3cc28c7 | 1218 | |
05ffdd7b JC |
1219 | atomic_set(&tpd_ring->next_to_use, 0); |
1220 | atomic_set(&tpd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1221 | } |
1222 | ||
49ce9c2c | 1223 | /** |
05ffdd7b JC |
1224 | * atl1_free_ring_resources - Free Tx / RX descriptor Resources |
1225 | * @adapter: board private structure | |
1226 | * | |
1227 | * Free all transmit software resources | |
f3cc28c7 | 1228 | */ |
6446a860 | 1229 | static void atl1_free_ring_resources(struct atl1_adapter *adapter) |
f3cc28c7 | 1230 | { |
f3cc28c7 | 1231 | struct pci_dev *pdev = adapter->pdev; |
05ffdd7b JC |
1232 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1233 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1234 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1235 | struct atl1_ring_header *ring_header = &adapter->ring_header; | |
f3cc28c7 | 1236 | |
05ffdd7b JC |
1237 | atl1_clean_tx_ring(adapter); |
1238 | atl1_clean_rx_ring(adapter); | |
f3cc28c7 | 1239 | |
05ffdd7b JC |
1240 | kfree(tpd_ring->buffer_info); |
1241 | pci_free_consistent(pdev, ring_header->size, ring_header->desc, | |
1242 | ring_header->dma); | |
f3cc28c7 | 1243 | |
05ffdd7b JC |
1244 | tpd_ring->buffer_info = NULL; |
1245 | tpd_ring->desc = NULL; | |
1246 | tpd_ring->dma = 0; | |
f3cc28c7 | 1247 | |
05ffdd7b JC |
1248 | rfd_ring->buffer_info = NULL; |
1249 | rfd_ring->desc = NULL; | |
1250 | rfd_ring->dma = 0; | |
f3cc28c7 | 1251 | |
05ffdd7b JC |
1252 | rrd_ring->desc = NULL; |
1253 | rrd_ring->dma = 0; | |
3f5a2a71 LT |
1254 | |
1255 | adapter->cmb.dma = 0; | |
1256 | adapter->cmb.cmb = NULL; | |
1257 | ||
1258 | adapter->smb.dma = 0; | |
1259 | adapter->smb.smb = NULL; | |
f3cc28c7 JC |
1260 | } |
1261 | ||
05ffdd7b | 1262 | static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) |
f3cc28c7 | 1263 | { |
f3cc28c7 | 1264 | u32 value; |
05ffdd7b JC |
1265 | struct atl1_hw *hw = &adapter->hw; |
1266 | struct net_device *netdev = adapter->netdev; | |
1267 | /* Config MAC CTRL Register */ | |
1268 | value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; | |
1269 | /* duplex */ | |
1270 | if (FULL_DUPLEX == adapter->link_duplex) | |
1271 | value |= MAC_CTRL_DUPLX; | |
1272 | /* speed */ | |
1273 | value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? | |
1274 | MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << | |
1275 | MAC_CTRL_SPEED_SHIFT); | |
1276 | /* flow control */ | |
1277 | value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | |
1278 | /* PAD & CRC */ | |
1279 | value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1280 | /* preamble length */ | |
1281 | value |= (((u32) adapter->hw.preamble_len | |
1282 | & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
1283 | /* vlan */ | |
92491709 | 1284 | __atlx_vlan_mode(netdev->features, &value); |
05ffdd7b JC |
1285 | /* rx checksum |
1286 | if (adapter->rx_csum) | |
1287 | value |= MAC_CTRL_RX_CHKSUM_EN; | |
1288 | */ | |
1289 | /* filter mode */ | |
1290 | value |= MAC_CTRL_BC_EN; | |
1291 | if (netdev->flags & IFF_PROMISC) | |
1292 | value |= MAC_CTRL_PROMIS_EN; | |
1293 | else if (netdev->flags & IFF_ALLMULTI) | |
1294 | value |= MAC_CTRL_MC_ALL_EN; | |
1295 | /* value |= MAC_CTRL_LOOPBACK; */ | |
1296 | iowrite32(value, hw->hw_addr + REG_MAC_CTRL); | |
1297 | } | |
f3cc28c7 | 1298 | |
05ffdd7b JC |
1299 | static u32 atl1_check_link(struct atl1_adapter *adapter) |
1300 | { | |
1301 | struct atl1_hw *hw = &adapter->hw; | |
1302 | struct net_device *netdev = adapter->netdev; | |
1303 | u32 ret_val; | |
1304 | u16 speed, duplex, phy_data; | |
1305 | int reconfig = 0; | |
f3cc28c7 | 1306 | |
05ffdd7b JC |
1307 | /* MII_BMSR must read twice */ |
1308 | atl1_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1309 | atl1_read_phy_reg(hw, MII_BMSR, &phy_data); | |
6446a860 JC |
1310 | if (!(phy_data & BMSR_LSTATUS)) { |
1311 | /* link down */ | |
1312 | if (netif_carrier_ok(netdev)) { | |
1313 | /* old link state: Up */ | |
1314 | if (netif_msg_link(adapter)) | |
1315 | dev_info(&adapter->pdev->dev, "link is down\n"); | |
05ffdd7b JC |
1316 | adapter->link_speed = SPEED_0; |
1317 | netif_carrier_off(netdev); | |
f3cc28c7 | 1318 | } |
6446a860 | 1319 | return 0; |
f3cc28c7 JC |
1320 | } |
1321 | ||
05ffdd7b JC |
1322 | /* Link Up */ |
1323 | ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); | |
1324 | if (ret_val) | |
1325 | return ret_val; | |
f3cc28c7 | 1326 | |
05ffdd7b JC |
1327 | switch (hw->media_type) { |
1328 | case MEDIA_TYPE_1000M_FULL: | |
1329 | if (speed != SPEED_1000 || duplex != FULL_DUPLEX) | |
1330 | reconfig = 1; | |
1331 | break; | |
1332 | case MEDIA_TYPE_100M_FULL: | |
1333 | if (speed != SPEED_100 || duplex != FULL_DUPLEX) | |
1334 | reconfig = 1; | |
1335 | break; | |
1336 | case MEDIA_TYPE_100M_HALF: | |
1337 | if (speed != SPEED_100 || duplex != HALF_DUPLEX) | |
1338 | reconfig = 1; | |
1339 | break; | |
1340 | case MEDIA_TYPE_10M_FULL: | |
1341 | if (speed != SPEED_10 || duplex != FULL_DUPLEX) | |
1342 | reconfig = 1; | |
1343 | break; | |
1344 | case MEDIA_TYPE_10M_HALF: | |
1345 | if (speed != SPEED_10 || duplex != HALF_DUPLEX) | |
1346 | reconfig = 1; | |
1347 | break; | |
1348 | } | |
f3cc28c7 | 1349 | |
05ffdd7b JC |
1350 | /* link result is our setting */ |
1351 | if (!reconfig) { | |
8e95a202 JP |
1352 | if (adapter->link_speed != speed || |
1353 | adapter->link_duplex != duplex) { | |
05ffdd7b JC |
1354 | adapter->link_speed = speed; |
1355 | adapter->link_duplex = duplex; | |
1356 | atl1_setup_mac_ctrl(adapter); | |
6446a860 JC |
1357 | if (netif_msg_link(adapter)) |
1358 | dev_info(&adapter->pdev->dev, | |
1359 | "%s link is up %d Mbps %s\n", | |
1360 | netdev->name, adapter->link_speed, | |
1361 | adapter->link_duplex == FULL_DUPLEX ? | |
1362 | "full duplex" : "half duplex"); | |
05ffdd7b | 1363 | } |
6446a860 JC |
1364 | if (!netif_carrier_ok(netdev)) { |
1365 | /* Link down -> Up */ | |
05ffdd7b | 1366 | netif_carrier_on(netdev); |
05ffdd7b | 1367 | } |
6446a860 | 1368 | return 0; |
f3cc28c7 | 1369 | } |
f3cc28c7 | 1370 | |
6446a860 | 1371 | /* change original link status */ |
05ffdd7b JC |
1372 | if (netif_carrier_ok(netdev)) { |
1373 | adapter->link_speed = SPEED_0; | |
1374 | netif_carrier_off(netdev); | |
1375 | netif_stop_queue(netdev); | |
f3cc28c7 | 1376 | } |
f3cc28c7 | 1377 | |
05ffdd7b JC |
1378 | if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && |
1379 | hw->media_type != MEDIA_TYPE_1000M_FULL) { | |
1380 | switch (hw->media_type) { | |
1381 | case MEDIA_TYPE_100M_FULL: | |
1382 | phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
1383 | MII_CR_RESET; | |
1384 | break; | |
1385 | case MEDIA_TYPE_100M_HALF: | |
1386 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
1387 | break; | |
1388 | case MEDIA_TYPE_10M_FULL: | |
1389 | phy_data = | |
1390 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
1391 | break; | |
6446a860 JC |
1392 | default: |
1393 | /* MEDIA_TYPE_10M_HALF: */ | |
05ffdd7b JC |
1394 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; |
1395 | break; | |
f3cc28c7 | 1396 | } |
05ffdd7b | 1397 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
6446a860 | 1398 | return 0; |
f3cc28c7 | 1399 | } |
f3cc28c7 | 1400 | |
05ffdd7b JC |
1401 | /* auto-neg, insert timer to re-config phy */ |
1402 | if (!adapter->phy_timer_pending) { | |
1403 | adapter->phy_timer_pending = true; | |
e053b628 SH |
1404 | mod_timer(&adapter->phy_config_timer, |
1405 | round_jiffies(jiffies + 3 * HZ)); | |
f3cc28c7 | 1406 | } |
f3cc28c7 | 1407 | |
05ffdd7b JC |
1408 | return 0; |
1409 | } | |
f3cc28c7 | 1410 | |
05ffdd7b JC |
1411 | static void set_flow_ctrl_old(struct atl1_adapter *adapter) |
1412 | { | |
1413 | u32 hi, lo, value; | |
f3cc28c7 | 1414 | |
05ffdd7b JC |
1415 | /* RFD Flow Control */ |
1416 | value = adapter->rfd_ring.count; | |
1417 | hi = value / 16; | |
1418 | if (hi < 2) | |
1419 | hi = 2; | |
1420 | lo = value * 7 / 8; | |
f3cc28c7 | 1421 | |
05ffdd7b JC |
1422 | value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | |
1423 | ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); | |
1424 | iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); | |
f3cc28c7 | 1425 | |
05ffdd7b JC |
1426 | /* RRD Flow Control */ |
1427 | value = adapter->rrd_ring.count; | |
1428 | lo = value / 16; | |
1429 | hi = value * 7 / 8; | |
1430 | if (lo < 2) | |
1431 | lo = 2; | |
1432 | value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | | |
1433 | ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); | |
1434 | iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); | |
1435 | } | |
f3cc28c7 | 1436 | |
05ffdd7b JC |
1437 | static void set_flow_ctrl_new(struct atl1_hw *hw) |
1438 | { | |
1439 | u32 hi, lo, value; | |
1440 | ||
1441 | /* RXF Flow Control */ | |
1442 | value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); | |
1443 | lo = value / 16; | |
1444 | if (lo < 192) | |
1445 | lo = 192; | |
1446 | hi = value * 7 / 8; | |
1447 | if (hi < lo) | |
1448 | hi = lo + 16; | |
1449 | value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | | |
1450 | ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); | |
1451 | iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); | |
1452 | ||
1453 | /* RRD Flow Control */ | |
1454 | value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); | |
1455 | lo = value / 8; | |
1456 | hi = value * 7 / 8; | |
1457 | if (lo < 2) | |
1458 | lo = 2; | |
1459 | if (hi < lo) | |
1460 | hi = lo + 3; | |
1461 | value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | | |
1462 | ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); | |
1463 | iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); | |
1464 | } | |
1465 | ||
49ce9c2c | 1466 | /** |
05ffdd7b JC |
1467 | * atl1_configure - Configure Transmit&Receive Unit after Reset |
1468 | * @adapter: board private structure | |
1469 | * | |
1470 | * Configure the Tx /Rx unit of the MAC after a reset. | |
1471 | */ | |
1472 | static u32 atl1_configure(struct atl1_adapter *adapter) | |
1473 | { | |
1474 | struct atl1_hw *hw = &adapter->hw; | |
1475 | u32 value; | |
1476 | ||
1477 | /* clear interrupt status */ | |
1478 | iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); | |
1479 | ||
1480 | /* set MAC Address */ | |
1481 | value = (((u32) hw->mac_addr[2]) << 24) | | |
1482 | (((u32) hw->mac_addr[3]) << 16) | | |
1483 | (((u32) hw->mac_addr[4]) << 8) | | |
1484 | (((u32) hw->mac_addr[5])); | |
1485 | iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); | |
1486 | value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); | |
1487 | iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); | |
1488 | ||
1489 | /* tx / rx ring */ | |
f3cc28c7 | 1490 | |
05ffdd7b JC |
1491 | /* HI base address */ |
1492 | iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), | |
1493 | hw->hw_addr + REG_DESC_BASE_ADDR_HI); | |
1494 | /* LO base address */ | |
1495 | iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), | |
1496 | hw->hw_addr + REG_DESC_RFD_ADDR_LO); | |
1497 | iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), | |
1498 | hw->hw_addr + REG_DESC_RRD_ADDR_LO); | |
1499 | iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), | |
1500 | hw->hw_addr + REG_DESC_TPD_ADDR_LO); | |
1501 | iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), | |
1502 | hw->hw_addr + REG_DESC_CMB_ADDR_LO); | |
1503 | iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), | |
1504 | hw->hw_addr + REG_DESC_SMB_ADDR_LO); | |
f3cc28c7 | 1505 | |
05ffdd7b JC |
1506 | /* element count */ |
1507 | value = adapter->rrd_ring.count; | |
1508 | value <<= 16; | |
1509 | value += adapter->rfd_ring.count; | |
1510 | iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); | |
1511 | iowrite32(adapter->tpd_ring.count, hw->hw_addr + | |
1512 | REG_DESC_TPD_RING_SIZE); | |
f3cc28c7 | 1513 | |
05ffdd7b JC |
1514 | /* Load Ptr */ |
1515 | iowrite32(1, hw->hw_addr + REG_LOAD_PTR); | |
f3cc28c7 | 1516 | |
05ffdd7b JC |
1517 | /* config Mailbox */ |
1518 | value = ((atomic_read(&adapter->tpd_ring.next_to_use) | |
1519 | & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | | |
1520 | ((atomic_read(&adapter->rrd_ring.next_to_clean) | |
1521 | & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | | |
1522 | ((atomic_read(&adapter->rfd_ring.next_to_use) | |
1523 | & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); | |
1524 | iowrite32(value, hw->hw_addr + REG_MAILBOX); | |
f3cc28c7 | 1525 | |
05ffdd7b JC |
1526 | /* config IPG/IFG */ |
1527 | value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) | |
1528 | << MAC_IPG_IFG_IPGT_SHIFT) | | |
1529 | (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) | |
1530 | << MAC_IPG_IFG_MIFG_SHIFT) | | |
1531 | (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) | |
1532 | << MAC_IPG_IFG_IPGR1_SHIFT) | | |
1533 | (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) | |
1534 | << MAC_IPG_IFG_IPGR2_SHIFT); | |
1535 | iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); | |
f3cc28c7 | 1536 | |
05ffdd7b JC |
1537 | /* config Half-Duplex Control */ |
1538 | value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | | |
1539 | (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) | |
1540 | << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | | |
1541 | MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | | |
1542 | (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | | |
1543 | (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) | |
1544 | << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); | |
1545 | iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); | |
f3cc28c7 | 1546 | |
05ffdd7b JC |
1547 | /* set Interrupt Moderator Timer */ |
1548 | iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); | |
1549 | iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); | |
f3cc28c7 | 1550 | |
05ffdd7b JC |
1551 | /* set Interrupt Clear Timer */ |
1552 | iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); | |
f3cc28c7 | 1553 | |
2a49128f JC |
1554 | /* set max frame size hw will accept */ |
1555 | iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); | |
f3cc28c7 | 1556 | |
05ffdd7b JC |
1557 | /* jumbo size & rrd retirement timer */ |
1558 | value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) | |
1559 | << RXQ_JMBOSZ_TH_SHIFT) | | |
1560 | (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) | |
1561 | << RXQ_JMBO_LKAH_SHIFT) | | |
1562 | (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) | |
1563 | << RXQ_RRD_TIMER_SHIFT); | |
1564 | iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); | |
f3cc28c7 | 1565 | |
05ffdd7b JC |
1566 | /* Flow Control */ |
1567 | switch (hw->dev_rev) { | |
1568 | case 0x8001: | |
1569 | case 0x9001: | |
1570 | case 0x9002: | |
1571 | case 0x9003: | |
1572 | set_flow_ctrl_old(adapter); | |
1573 | break; | |
1574 | default: | |
1575 | set_flow_ctrl_new(hw); | |
1576 | break; | |
f3cc28c7 | 1577 | } |
f3cc28c7 | 1578 | |
05ffdd7b JC |
1579 | /* config TXQ */ |
1580 | value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) | |
1581 | << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | | |
1582 | (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) | |
1583 | << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | | |
1584 | (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) | |
1585 | << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | | |
1586 | TXQ_CTRL_EN; | |
1587 | iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); | |
f3cc28c7 | 1588 | |
05ffdd7b JC |
1589 | /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ |
1590 | value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) | |
1591 | << TX_JUMBO_TASK_TH_SHIFT) | | |
1592 | (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) | |
1593 | << TX_TPD_MIN_IPG_SHIFT); | |
1594 | iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); | |
f3cc28c7 | 1595 | |
05ffdd7b JC |
1596 | /* config RXQ */ |
1597 | value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) | |
1598 | << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | | |
1599 | (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) | |
1600 | << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | | |
1601 | (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) | |
1602 | << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | | |
1603 | RXQ_CTRL_EN; | |
1604 | iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); | |
f3cc28c7 | 1605 | |
05ffdd7b JC |
1606 | /* config DMA Engine */ |
1607 | value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) | |
1608 | << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | | |
3f516c00 JC |
1609 | ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) |
1610 | << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | | |
05ffdd7b JC |
1611 | DMA_CTRL_DMAW_EN; |
1612 | value |= (u32) hw->dma_ord; | |
1613 | if (atl1_rcb_128 == hw->rcb_value) | |
1614 | value |= DMA_CTRL_RCB_VALUE; | |
1615 | iowrite32(value, hw->hw_addr + REG_DMA_CTRL); | |
f3cc28c7 | 1616 | |
05ffdd7b | 1617 | /* config CMB / SMB */ |
91a500ac JC |
1618 | value = (hw->cmb_tpd > adapter->tpd_ring.count) ? |
1619 | hw->cmb_tpd : adapter->tpd_ring.count; | |
1620 | value <<= 16; | |
1621 | value |= hw->cmb_rrd; | |
05ffdd7b JC |
1622 | iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); |
1623 | value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); | |
1624 | iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); | |
1625 | iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); | |
f3cc28c7 | 1626 | |
05ffdd7b JC |
1627 | /* --- enable CMB / SMB */ |
1628 | value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; | |
1629 | iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); | |
f3cc28c7 | 1630 | |
05ffdd7b JC |
1631 | value = ioread32(adapter->hw.hw_addr + REG_ISR); |
1632 | if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) | |
1633 | value = 1; /* config failed */ | |
1634 | else | |
1635 | value = 0; | |
f3cc28c7 | 1636 | |
05ffdd7b JC |
1637 | /* clear all interrupt status */ |
1638 | iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); | |
1639 | iowrite32(0, adapter->hw.hw_addr + REG_ISR); | |
1640 | return value; | |
f3cc28c7 | 1641 | } |
f3cc28c7 | 1642 | |
05ffdd7b JC |
1643 | /* |
1644 | * atl1_pcie_patch - Patch for PCIE module | |
1645 | */ | |
1646 | static void atl1_pcie_patch(struct atl1_adapter *adapter) | |
f3cc28c7 | 1647 | { |
05ffdd7b | 1648 | u32 value; |
f3cc28c7 | 1649 | |
05ffdd7b JC |
1650 | /* much vendor magic here */ |
1651 | value = 0x6500; | |
1652 | iowrite32(value, adapter->hw.hw_addr + 0x12FC); | |
1653 | /* pcie flow control mode change */ | |
1654 | value = ioread32(adapter->hw.hw_addr + 0x1008); | |
1655 | value |= 0x8000; | |
1656 | iowrite32(value, adapter->hw.hw_addr + 0x1008); | |
f3cc28c7 | 1657 | } |
f3cc28c7 | 1658 | |
f3cc28c7 | 1659 | /* |
05ffdd7b JC |
1660 | * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 |
1661 | * on PCI Command register is disable. | |
1662 | * The function enable this bit. | |
1663 | * Brackett, 2006/03/15 | |
f3cc28c7 | 1664 | */ |
05ffdd7b | 1665 | static void atl1_via_workaround(struct atl1_adapter *adapter) |
f3cc28c7 | 1666 | { |
05ffdd7b | 1667 | unsigned long value; |
f3cc28c7 | 1668 | |
05ffdd7b JC |
1669 | value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); |
1670 | if (value & PCI_COMMAND_INTX_DISABLE) | |
1671 | value &= ~PCI_COMMAND_INTX_DISABLE; | |
1672 | iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); | |
f3cc28c7 JC |
1673 | } |
1674 | ||
05ffdd7b JC |
1675 | static void atl1_inc_smb(struct atl1_adapter *adapter) |
1676 | { | |
02e71731 | 1677 | struct net_device *netdev = adapter->netdev; |
05ffdd7b | 1678 | struct stats_msg_block *smb = adapter->smb.smb; |
f3cc28c7 | 1679 | |
e3d21ea1 SD |
1680 | u64 new_rx_errors = smb->rx_frag + |
1681 | smb->rx_fcs_err + | |
1682 | smb->rx_len_err + | |
1683 | smb->rx_sz_ov + | |
1684 | smb->rx_rxf_ov + | |
1685 | smb->rx_rrd_ov + | |
1686 | smb->rx_align_err; | |
1687 | u64 new_tx_errors = smb->tx_late_col + | |
1688 | smb->tx_abort_col + | |
1689 | smb->tx_underrun + | |
1690 | smb->tx_trunc; | |
1691 | ||
05ffdd7b | 1692 | /* Fill out the OS statistics structure */ |
e3d21ea1 SD |
1693 | adapter->soft_stats.rx_packets += smb->rx_ok + new_rx_errors; |
1694 | adapter->soft_stats.tx_packets += smb->tx_ok + new_tx_errors; | |
05ffdd7b JC |
1695 | adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; |
1696 | adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; | |
1697 | adapter->soft_stats.multicast += smb->rx_mcast; | |
e3d21ea1 SD |
1698 | adapter->soft_stats.collisions += smb->tx_1_col + |
1699 | smb->tx_2_col + | |
1700 | smb->tx_late_col + | |
1701 | smb->tx_abort_col; | |
f3cc28c7 | 1702 | |
05ffdd7b | 1703 | /* Rx Errors */ |
e3d21ea1 | 1704 | adapter->soft_stats.rx_errors += new_rx_errors; |
05ffdd7b JC |
1705 | adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; |
1706 | adapter->soft_stats.rx_length_errors += smb->rx_len_err; | |
1707 | adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; | |
1708 | adapter->soft_stats.rx_frame_errors += smb->rx_align_err; | |
f3cc28c7 | 1709 | |
05ffdd7b JC |
1710 | adapter->soft_stats.rx_pause += smb->rx_pause; |
1711 | adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; | |
1712 | adapter->soft_stats.rx_trunc += smb->rx_sz_ov; | |
f3cc28c7 | 1713 | |
05ffdd7b | 1714 | /* Tx Errors */ |
e3d21ea1 | 1715 | adapter->soft_stats.tx_errors += new_tx_errors; |
05ffdd7b JC |
1716 | adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; |
1717 | adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; | |
1718 | adapter->soft_stats.tx_window_errors += smb->tx_late_col; | |
f3cc28c7 | 1719 | |
05ffdd7b JC |
1720 | adapter->soft_stats.excecol += smb->tx_abort_col; |
1721 | adapter->soft_stats.deffer += smb->tx_defer; | |
1722 | adapter->soft_stats.scc += smb->tx_1_col; | |
1723 | adapter->soft_stats.mcc += smb->tx_2_col; | |
1724 | adapter->soft_stats.latecol += smb->tx_late_col; | |
1725 | adapter->soft_stats.tx_underun += smb->tx_underrun; | |
1726 | adapter->soft_stats.tx_trunc += smb->tx_trunc; | |
1727 | adapter->soft_stats.tx_pause += smb->tx_pause; | |
f3cc28c7 | 1728 | |
02e71731 SH |
1729 | netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; |
1730 | netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; | |
1731 | netdev->stats.multicast = adapter->soft_stats.multicast; | |
1732 | netdev->stats.collisions = adapter->soft_stats.collisions; | |
1733 | netdev->stats.rx_errors = adapter->soft_stats.rx_errors; | |
02e71731 | 1734 | netdev->stats.rx_length_errors = |
05ffdd7b | 1735 | adapter->soft_stats.rx_length_errors; |
02e71731 SH |
1736 | netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; |
1737 | netdev->stats.rx_frame_errors = | |
05ffdd7b | 1738 | adapter->soft_stats.rx_frame_errors; |
02e71731 | 1739 | netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; |
e3d21ea1 | 1740 | netdev->stats.rx_dropped = adapter->soft_stats.rx_rrd_ov; |
02e71731 SH |
1741 | netdev->stats.tx_errors = adapter->soft_stats.tx_errors; |
1742 | netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; | |
1743 | netdev->stats.tx_aborted_errors = | |
05ffdd7b | 1744 | adapter->soft_stats.tx_aborted_errors; |
02e71731 | 1745 | netdev->stats.tx_window_errors = |
05ffdd7b | 1746 | adapter->soft_stats.tx_window_errors; |
02e71731 | 1747 | netdev->stats.tx_carrier_errors = |
05ffdd7b | 1748 | adapter->soft_stats.tx_carrier_errors; |
e3d21ea1 SD |
1749 | |
1750 | netdev->stats.rx_packets = adapter->soft_stats.rx_packets; | |
1751 | netdev->stats.tx_packets = adapter->soft_stats.tx_packets; | |
f3cc28c7 JC |
1752 | } |
1753 | ||
05ffdd7b | 1754 | static void atl1_update_mailbox(struct atl1_adapter *adapter) |
f3cc28c7 | 1755 | { |
05ffdd7b JC |
1756 | unsigned long flags; |
1757 | u32 tpd_next_to_use; | |
1758 | u32 rfd_next_to_use; | |
1759 | u32 rrd_next_to_clean; | |
f3cc28c7 | 1760 | u32 value; |
f3cc28c7 | 1761 | |
05ffdd7b | 1762 | spin_lock_irqsave(&adapter->mb_lock, flags); |
f3cc28c7 | 1763 | |
05ffdd7b JC |
1764 | tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); |
1765 | rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); | |
1766 | rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); | |
f3cc28c7 | 1767 | |
05ffdd7b JC |
1768 | value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << |
1769 | MB_RFD_PROD_INDX_SHIFT) | | |
1770 | ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << | |
1771 | MB_RRD_CONS_INDX_SHIFT) | | |
1772 | ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << | |
1773 | MB_TPD_PROD_INDX_SHIFT); | |
1774 | iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); | |
f3cc28c7 | 1775 | |
05ffdd7b | 1776 | spin_unlock_irqrestore(&adapter->mb_lock, flags); |
f3cc28c7 JC |
1777 | } |
1778 | ||
05ffdd7b JC |
1779 | static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, |
1780 | struct rx_return_desc *rrd, u16 offset) | |
f3cc28c7 | 1781 | { |
05ffdd7b | 1782 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
f3cc28c7 | 1783 | |
05ffdd7b JC |
1784 | while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { |
1785 | rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; | |
1786 | if (++rfd_ring->next_to_clean == rfd_ring->count) { | |
1787 | rfd_ring->next_to_clean = 0; | |
f3cc28c7 | 1788 | } |
f3cc28c7 | 1789 | } |
05ffdd7b | 1790 | } |
f3cc28c7 | 1791 | |
05ffdd7b JC |
1792 | static void atl1_update_rfd_index(struct atl1_adapter *adapter, |
1793 | struct rx_return_desc *rrd) | |
1794 | { | |
1795 | u16 num_buf; | |
f3cc28c7 | 1796 | |
05ffdd7b JC |
1797 | num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / |
1798 | adapter->rx_buffer_len; | |
1799 | if (rrd->num_buf == num_buf) | |
1800 | /* clean alloc flag for bad rrd */ | |
1801 | atl1_clean_alloc_flag(adapter, rrd, num_buf); | |
1802 | } | |
f3cc28c7 | 1803 | |
05ffdd7b JC |
1804 | static void atl1_rx_checksum(struct atl1_adapter *adapter, |
1805 | struct rx_return_desc *rrd, struct sk_buff *skb) | |
1806 | { | |
1807 | struct pci_dev *pdev = adapter->pdev; | |
f3cc28c7 | 1808 | |
c2ac3ef3 JC |
1809 | /* |
1810 | * The L1 hardware contains a bug that erroneously sets the | |
1811 | * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a | |
1812 | * fragmented IP packet is received, even though the packet | |
1813 | * is perfectly valid and its checksum is correct. There's | |
1814 | * no way to distinguish between one of these good packets | |
1815 | * and a packet that actually contains a TCP/UDP checksum | |
1816 | * error, so all we can do is allow it to be handed up to | |
1817 | * the higher layers and let it be sorted out there. | |
1818 | */ | |
1819 | ||
bc8acf2c | 1820 | skb_checksum_none_assert(skb); |
f3cc28c7 | 1821 | |
05ffdd7b JC |
1822 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { |
1823 | if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | | |
1824 | ERR_FLAG_CODE | ERR_FLAG_OV)) { | |
1825 | adapter->hw_csum_err++; | |
6446a860 JC |
1826 | if (netif_msg_rx_err(adapter)) |
1827 | dev_printk(KERN_DEBUG, &pdev->dev, | |
1828 | "rx checksum error\n"); | |
05ffdd7b | 1829 | return; |
f3cc28c7 | 1830 | } |
f3cc28c7 JC |
1831 | } |
1832 | ||
05ffdd7b JC |
1833 | /* not IPv4 */ |
1834 | if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) | |
1835 | /* checksum is invalid, but it's not an IPv4 pkt, so ok */ | |
1836 | return; | |
1837 | ||
1838 | /* IPv4 packet */ | |
1839 | if (likely(!(rrd->err_flg & | |
1840 | (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { | |
1841 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1842 | adapter->hw_csum_good++; | |
1843 | return; | |
f3cc28c7 | 1844 | } |
f3cc28c7 JC |
1845 | } |
1846 | ||
49ce9c2c | 1847 | /** |
05ffdd7b JC |
1848 | * atl1_alloc_rx_buffers - Replace used receive buffers |
1849 | * @adapter: address of board private structure | |
1850 | */ | |
1851 | static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) | |
f3cc28c7 | 1852 | { |
05ffdd7b JC |
1853 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1854 | struct pci_dev *pdev = adapter->pdev; | |
1855 | struct page *page; | |
1856 | unsigned long offset; | |
1857 | struct atl1_buffer *buffer_info, *next_info; | |
1858 | struct sk_buff *skb; | |
1859 | u16 num_alloc = 0; | |
1860 | u16 rfd_next_to_use, next_next; | |
1861 | struct rx_free_desc *rfd_desc; | |
f3cc28c7 | 1862 | |
05ffdd7b JC |
1863 | next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); |
1864 | if (++next_next == rfd_ring->count) | |
1865 | next_next = 0; | |
1866 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; | |
1867 | next_info = &rfd_ring->buffer_info[next_next]; | |
f3cc28c7 | 1868 | |
05ffdd7b JC |
1869 | while (!buffer_info->alloced && !next_info->alloced) { |
1870 | if (buffer_info->skb) { | |
1871 | buffer_info->alloced = 1; | |
1872 | goto next; | |
1873 | } | |
f3cc28c7 | 1874 | |
05ffdd7b | 1875 | rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); |
f3cc28c7 | 1876 | |
89d71a66 ED |
1877 | skb = netdev_alloc_skb_ip_align(adapter->netdev, |
1878 | adapter->rx_buffer_len); | |
6446a860 JC |
1879 | if (unlikely(!skb)) { |
1880 | /* Better luck next round */ | |
e3d21ea1 | 1881 | adapter->soft_stats.rx_dropped++; |
05ffdd7b JC |
1882 | break; |
1883 | } | |
f3cc28c7 | 1884 | |
05ffdd7b JC |
1885 | buffer_info->alloced = 1; |
1886 | buffer_info->skb = skb; | |
1887 | buffer_info->length = (u16) adapter->rx_buffer_len; | |
1888 | page = virt_to_page(skb->data); | |
1889 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
1890 | buffer_info->dma = pci_map_page(pdev, page, offset, | |
1891 | adapter->rx_buffer_len, | |
1892 | PCI_DMA_FROMDEVICE); | |
1893 | rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | |
1894 | rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); | |
1895 | rfd_desc->coalese = 0; | |
f3cc28c7 | 1896 | |
05ffdd7b JC |
1897 | next: |
1898 | rfd_next_to_use = next_next; | |
1899 | if (unlikely(++next_next == rfd_ring->count)) | |
1900 | next_next = 0; | |
f3cc28c7 | 1901 | |
05ffdd7b JC |
1902 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; |
1903 | next_info = &rfd_ring->buffer_info[next_next]; | |
1904 | num_alloc++; | |
1905 | } | |
f3cc28c7 | 1906 | |
05ffdd7b JC |
1907 | if (num_alloc) { |
1908 | /* | |
1909 | * Force memory writes to complete before letting h/w | |
1910 | * know there are new descriptors to fetch. (Only | |
1911 | * applicable for weak-ordered memory model archs, | |
1912 | * such as IA-64). | |
1913 | */ | |
1914 | wmb(); | |
1915 | atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); | |
1916 | } | |
1917 | return num_alloc; | |
f3cc28c7 JC |
1918 | } |
1919 | ||
6294512b | 1920 | static int atl1_intr_rx(struct atl1_adapter *adapter, int budget) |
f3cc28c7 | 1921 | { |
05ffdd7b JC |
1922 | int i, count; |
1923 | u16 length; | |
1924 | u16 rrd_next_to_clean; | |
f3cc28c7 | 1925 | u32 value; |
05ffdd7b JC |
1926 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1927 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1928 | struct atl1_buffer *buffer_info; | |
1929 | struct rx_return_desc *rrd; | |
1930 | struct sk_buff *skb; | |
f3cc28c7 | 1931 | |
05ffdd7b | 1932 | count = 0; |
f3cc28c7 | 1933 | |
05ffdd7b | 1934 | rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); |
f3cc28c7 | 1935 | |
6294512b | 1936 | while (count < budget) { |
05ffdd7b JC |
1937 | rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); |
1938 | i = 1; | |
1939 | if (likely(rrd->xsz.valid)) { /* packet valid */ | |
1940 | chk_rrd: | |
1941 | /* check rrd status */ | |
1942 | if (likely(rrd->num_buf == 1)) | |
1943 | goto rrd_ok; | |
6446a860 JC |
1944 | else if (netif_msg_rx_err(adapter)) { |
1945 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1946 | "unexpected RRD buffer count\n"); | |
1947 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1948 | "rx_buf_len = %d\n", | |
1949 | adapter->rx_buffer_len); | |
1950 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1951 | "RRD num_buf = %d\n", | |
1952 | rrd->num_buf); | |
1953 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1954 | "RRD pkt_len = %d\n", | |
1955 | rrd->xsz.xsum_sz.pkt_size); | |
1956 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1957 | "RRD pkt_flg = 0x%08X\n", | |
1958 | rrd->pkt_flg); | |
1959 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1960 | "RRD err_flg = 0x%08X\n", | |
1961 | rrd->err_flg); | |
1962 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1963 | "RRD vlan_tag = 0x%08X\n", | |
1964 | rrd->vlan_tag); | |
1965 | } | |
f3cc28c7 | 1966 | |
05ffdd7b JC |
1967 | /* rrd seems to be bad */ |
1968 | if (unlikely(i-- > 0)) { | |
1969 | /* rrd may not be DMAed completely */ | |
05ffdd7b JC |
1970 | udelay(1); |
1971 | goto chk_rrd; | |
1972 | } | |
1973 | /* bad rrd */ | |
6446a860 JC |
1974 | if (netif_msg_rx_err(adapter)) |
1975 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1976 | "bad RRD\n"); | |
05ffdd7b JC |
1977 | /* see if update RFD index */ |
1978 | if (rrd->num_buf > 1) | |
1979 | atl1_update_rfd_index(adapter, rrd); | |
f3cc28c7 | 1980 | |
05ffdd7b JC |
1981 | /* update rrd */ |
1982 | rrd->xsz.valid = 0; | |
1983 | if (++rrd_next_to_clean == rrd_ring->count) | |
1984 | rrd_next_to_clean = 0; | |
1985 | count++; | |
1986 | continue; | |
1987 | } else { /* current rrd still not be updated */ | |
f3cc28c7 | 1988 | |
05ffdd7b JC |
1989 | break; |
1990 | } | |
1991 | rrd_ok: | |
1992 | /* clean alloc flag for bad rrd */ | |
1993 | atl1_clean_alloc_flag(adapter, rrd, 0); | |
f3cc28c7 | 1994 | |
05ffdd7b JC |
1995 | buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; |
1996 | if (++rfd_ring->next_to_clean == rfd_ring->count) | |
1997 | rfd_ring->next_to_clean = 0; | |
f3cc28c7 | 1998 | |
05ffdd7b JC |
1999 | /* update rrd next to clean */ |
2000 | if (++rrd_next_to_clean == rrd_ring->count) | |
2001 | rrd_next_to_clean = 0; | |
2002 | count++; | |
f3cc28c7 | 2003 | |
05ffdd7b JC |
2004 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { |
2005 | if (!(rrd->err_flg & | |
2006 | (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM | |
2007 | | ERR_FLAG_LEN))) { | |
2008 | /* packet error, don't need upstream */ | |
2009 | buffer_info->alloced = 0; | |
2010 | rrd->xsz.valid = 0; | |
2011 | continue; | |
2012 | } | |
2013 | } | |
f3cc28c7 | 2014 | |
05ffdd7b JC |
2015 | /* Good Receive */ |
2016 | pci_unmap_page(adapter->pdev, buffer_info->dma, | |
2017 | buffer_info->length, PCI_DMA_FROMDEVICE); | |
aefdbf1a | 2018 | buffer_info->dma = 0; |
05ffdd7b JC |
2019 | skb = buffer_info->skb; |
2020 | length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); | |
f3cc28c7 | 2021 | |
a3093d9b | 2022 | skb_put(skb, length - ETH_FCS_LEN); |
f3cc28c7 | 2023 | |
05ffdd7b JC |
2024 | /* Receive Checksum Offload */ |
2025 | atl1_rx_checksum(adapter, rrd, skb); | |
2026 | skb->protocol = eth_type_trans(skb, adapter->netdev); | |
f3cc28c7 | 2027 | |
92491709 | 2028 | if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) { |
05ffdd7b JC |
2029 | u16 vlan_tag = (rrd->vlan_tag >> 4) | |
2030 | ((rrd->vlan_tag & 7) << 13) | | |
2031 | ((rrd->vlan_tag & 8) << 9); | |
92491709 | 2032 | |
86a9bad3 | 2033 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
92491709 | 2034 | } |
6294512b | 2035 | netif_receive_skb(skb); |
f3cc28c7 | 2036 | |
05ffdd7b JC |
2037 | /* let protocol layer free skb */ |
2038 | buffer_info->skb = NULL; | |
2039 | buffer_info->alloced = 0; | |
2040 | rrd->xsz.valid = 0; | |
05ffdd7b | 2041 | } |
f3cc28c7 | 2042 | |
05ffdd7b | 2043 | atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); |
f3cc28c7 | 2044 | |
05ffdd7b | 2045 | atl1_alloc_rx_buffers(adapter); |
f3cc28c7 | 2046 | |
05ffdd7b JC |
2047 | /* update mailbox ? */ |
2048 | if (count) { | |
2049 | u32 tpd_next_to_use; | |
2050 | u32 rfd_next_to_use; | |
f3cc28c7 | 2051 | |
05ffdd7b | 2052 | spin_lock(&adapter->mb_lock); |
f3cc28c7 | 2053 | |
05ffdd7b JC |
2054 | tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); |
2055 | rfd_next_to_use = | |
2056 | atomic_read(&adapter->rfd_ring.next_to_use); | |
2057 | rrd_next_to_clean = | |
2058 | atomic_read(&adapter->rrd_ring.next_to_clean); | |
2059 | value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << | |
2060 | MB_RFD_PROD_INDX_SHIFT) | | |
2061 | ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << | |
2062 | MB_RRD_CONS_INDX_SHIFT) | | |
2063 | ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << | |
2064 | MB_TPD_PROD_INDX_SHIFT); | |
2065 | iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); | |
2066 | spin_unlock(&adapter->mb_lock); | |
2067 | } | |
6294512b TZ |
2068 | |
2069 | return count; | |
f3cc28c7 JC |
2070 | } |
2071 | ||
0dbab2fb | 2072 | static int atl1_intr_tx(struct atl1_adapter *adapter) |
f3cc28c7 | 2073 | { |
05ffdd7b JC |
2074 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
2075 | struct atl1_buffer *buffer_info; | |
2076 | u16 sw_tpd_next_to_clean; | |
2077 | u16 cmb_tpd_next_to_clean; | |
0dbab2fb | 2078 | int count = 0; |
f3cc28c7 | 2079 | |
05ffdd7b JC |
2080 | sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); |
2081 | cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); | |
f3cc28c7 | 2082 | |
05ffdd7b | 2083 | while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { |
05ffdd7b JC |
2084 | buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; |
2085 | if (buffer_info->dma) { | |
2086 | pci_unmap_page(adapter->pdev, buffer_info->dma, | |
2087 | buffer_info->length, PCI_DMA_TODEVICE); | |
2088 | buffer_info->dma = 0; | |
2089 | } | |
f3cc28c7 | 2090 | |
05ffdd7b JC |
2091 | if (buffer_info->skb) { |
2092 | dev_kfree_skb_irq(buffer_info->skb); | |
2093 | buffer_info->skb = NULL; | |
2094 | } | |
f3cc28c7 | 2095 | |
05ffdd7b JC |
2096 | if (++sw_tpd_next_to_clean == tpd_ring->count) |
2097 | sw_tpd_next_to_clean = 0; | |
0dbab2fb TZ |
2098 | |
2099 | count++; | |
05ffdd7b JC |
2100 | } |
2101 | atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); | |
2102 | ||
8e95a202 JP |
2103 | if (netif_queue_stopped(adapter->netdev) && |
2104 | netif_carrier_ok(adapter->netdev)) | |
05ffdd7b | 2105 | netif_wake_queue(adapter->netdev); |
0dbab2fb TZ |
2106 | |
2107 | return count; | |
f3cc28c7 JC |
2108 | } |
2109 | ||
e6a7ff4a | 2110 | static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) |
f3cc28c7 JC |
2111 | { |
2112 | u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); | |
2113 | u16 next_to_use = atomic_read(&tpd_ring->next_to_use); | |
807540ba | 2114 | return (next_to_clean > next_to_use) ? |
53ffb42c | 2115 | next_to_clean - next_to_use - 1 : |
807540ba | 2116 | tpd_ring->count + next_to_clean - next_to_use - 1; |
f3cc28c7 JC |
2117 | } |
2118 | ||
2119 | static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, | |
4067caba | 2120 | struct tx_packet_desc *ptpd) |
f3cc28c7 | 2121 | { |
6446a860 JC |
2122 | u8 hdr_len, ip_off; |
2123 | u32 real_len; | |
f3cc28c7 JC |
2124 | |
2125 | if (skb_shinfo(skb)->gso_size) { | |
4067caba | 2126 | int err; |
2127 | ||
2128 | err = skb_cow_head(skb, 0); | |
2129 | if (err < 0) | |
2130 | return err; | |
f3cc28c7 | 2131 | |
d63ddcec | 2132 | if (skb->protocol == htons(ETH_P_IP)) { |
eddc9ec5 ACM |
2133 | struct iphdr *iph = ip_hdr(skb); |
2134 | ||
6446a860 JC |
2135 | real_len = (((unsigned char *)iph - skb->data) + |
2136 | ntohs(iph->tot_len)); | |
2137 | if (real_len < skb->len) | |
2138 | pskb_trim(skb, real_len); | |
2139 | hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); | |
2140 | if (skb->len == hdr_len) { | |
2141 | iph->check = 0; | |
2142 | tcp_hdr(skb)->check = | |
2143 | ~csum_tcpudp_magic(iph->saddr, | |
2144 | iph->daddr, tcp_hdrlen(skb), | |
2145 | IPPROTO_TCP, 0); | |
2146 | ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << | |
2147 | TPD_IPHL_SHIFT; | |
2148 | ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & | |
2149 | TPD_TCPHDRLEN_MASK) << | |
2150 | TPD_TCPHDRLEN_SHIFT; | |
2151 | ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; | |
2152 | ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; | |
2153 | return 1; | |
2154 | } | |
2155 | ||
eddc9ec5 | 2156 | iph->check = 0; |
aa8223c7 | 2157 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, |
6446a860 JC |
2158 | iph->daddr, 0, IPPROTO_TCP, 0); |
2159 | ip_off = (unsigned char *)iph - | |
2160 | (unsigned char *) skb_network_header(skb); | |
2161 | if (ip_off == 8) /* 802.3-SNAP frame */ | |
2162 | ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; | |
2163 | else if (ip_off != 0) | |
2164 | return -2; | |
2165 | ||
2166 | ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << | |
2167 | TPD_IPHL_SHIFT; | |
2168 | ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & | |
2169 | TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; | |
2170 | ptpd->word3 |= (skb_shinfo(skb)->gso_size & | |
2171 | TPD_MSS_MASK) << TPD_MSS_SHIFT; | |
2172 | ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; | |
2173 | return 3; | |
f3cc28c7 JC |
2174 | } |
2175 | } | |
4067caba | 2176 | return 0; |
f3cc28c7 JC |
2177 | } |
2178 | ||
2179 | static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, | |
6446a860 | 2180 | struct tx_packet_desc *ptpd) |
f3cc28c7 JC |
2181 | { |
2182 | u8 css, cso; | |
2183 | ||
2184 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { | |
55508d60 | 2185 | css = skb_checksum_start_offset(skb); |
6446a860 JC |
2186 | cso = css + (u8) skb->csum_offset; |
2187 | if (unlikely(css & 0x1)) { | |
2188 | /* L1 hardware requires an even number here */ | |
2189 | if (netif_msg_tx_err(adapter)) | |
2190 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2191 | "payload offset not an even number\n"); | |
f3cc28c7 JC |
2192 | return -1; |
2193 | } | |
6446a860 JC |
2194 | ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << |
2195 | TPD_PLOADOFFSET_SHIFT; | |
2196 | ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << | |
2197 | TPD_CCSUMOFFSET_SHIFT; | |
2198 | ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; | |
f3cc28c7 JC |
2199 | return true; |
2200 | } | |
6446a860 | 2201 | return 0; |
f3cc28c7 JC |
2202 | } |
2203 | ||
53ffb42c | 2204 | static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, |
6446a860 | 2205 | struct tx_packet_desc *ptpd) |
f3cc28c7 | 2206 | { |
f3cc28c7 JC |
2207 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
2208 | struct atl1_buffer *buffer_info; | |
6446a860 | 2209 | u16 buf_len = skb->len; |
f3cc28c7 | 2210 | struct page *page; |
f3cc28c7 JC |
2211 | unsigned long offset; |
2212 | unsigned int nr_frags; | |
2213 | unsigned int f; | |
6446a860 JC |
2214 | int retval; |
2215 | u16 next_to_use; | |
2216 | u16 data_len; | |
2217 | u8 hdr_len; | |
f3cc28c7 | 2218 | |
6446a860 | 2219 | buf_len -= skb->data_len; |
f3cc28c7 | 2220 | nr_frags = skb_shinfo(skb)->nr_frags; |
6446a860 JC |
2221 | next_to_use = atomic_read(&tpd_ring->next_to_use); |
2222 | buffer_info = &tpd_ring->buffer_info[next_to_use]; | |
0ee904c3 | 2223 | BUG_ON(buffer_info->skb); |
6446a860 JC |
2224 | /* put skb in last TPD */ |
2225 | buffer_info->skb = NULL; | |
f3cc28c7 | 2226 | |
6446a860 JC |
2227 | retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; |
2228 | if (retval) { | |
2229 | /* TSO */ | |
2230 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2231 | buffer_info->length = hdr_len; | |
f3cc28c7 JC |
2232 | page = virt_to_page(skb->data); |
2233 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
2234 | buffer_info->dma = pci_map_page(adapter->pdev, page, | |
6446a860 | 2235 | offset, hdr_len, |
f3cc28c7 JC |
2236 | PCI_DMA_TODEVICE); |
2237 | ||
6446a860 JC |
2238 | if (++next_to_use == tpd_ring->count) |
2239 | next_to_use = 0; | |
f3cc28c7 | 2240 | |
6446a860 JC |
2241 | if (buf_len > hdr_len) { |
2242 | int i, nseg; | |
ddfce6bb | 2243 | |
6446a860 JC |
2244 | data_len = buf_len - hdr_len; |
2245 | nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / | |
53ffb42c | 2246 | ATL1_MAX_TX_BUF_LEN; |
6446a860 | 2247 | for (i = 0; i < nseg; i++) { |
f3cc28c7 | 2248 | buffer_info = |
6446a860 | 2249 | &tpd_ring->buffer_info[next_to_use]; |
f3cc28c7 JC |
2250 | buffer_info->skb = NULL; |
2251 | buffer_info->length = | |
2b116145 | 2252 | (ATL1_MAX_TX_BUF_LEN >= |
6446a860 JC |
2253 | data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; |
2254 | data_len -= buffer_info->length; | |
f3cc28c7 | 2255 | page = virt_to_page(skb->data + |
6446a860 | 2256 | (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); |
f3cc28c7 | 2257 | offset = (unsigned long)(skb->data + |
6446a860 JC |
2258 | (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) & |
2259 | ~PAGE_MASK; | |
53ffb42c JC |
2260 | buffer_info->dma = pci_map_page(adapter->pdev, |
2261 | page, offset, buffer_info->length, | |
2262 | PCI_DMA_TODEVICE); | |
6446a860 JC |
2263 | if (++next_to_use == tpd_ring->count) |
2264 | next_to_use = 0; | |
f3cc28c7 JC |
2265 | } |
2266 | } | |
2267 | } else { | |
6446a860 JC |
2268 | /* not TSO */ |
2269 | buffer_info->length = buf_len; | |
f3cc28c7 JC |
2270 | page = virt_to_page(skb->data); |
2271 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
2272 | buffer_info->dma = pci_map_page(adapter->pdev, page, | |
6446a860 JC |
2273 | offset, buf_len, PCI_DMA_TODEVICE); |
2274 | if (++next_to_use == tpd_ring->count) | |
2275 | next_to_use = 0; | |
f3cc28c7 JC |
2276 | } |
2277 | ||
2278 | for (f = 0; f < nr_frags; f++) { | |
9e903e08 | 2279 | const struct skb_frag_struct *frag; |
6446a860 | 2280 | u16 i, nseg; |
f3cc28c7 JC |
2281 | |
2282 | frag = &skb_shinfo(skb)->frags[f]; | |
9e903e08 | 2283 | buf_len = skb_frag_size(frag); |
f3cc28c7 | 2284 | |
6446a860 JC |
2285 | nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / |
2286 | ATL1_MAX_TX_BUF_LEN; | |
2287 | for (i = 0; i < nseg; i++) { | |
2288 | buffer_info = &tpd_ring->buffer_info[next_to_use]; | |
0ee904c3 AB |
2289 | BUG_ON(buffer_info->skb); |
2290 | ||
f3cc28c7 | 2291 | buffer_info->skb = NULL; |
6446a860 JC |
2292 | buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? |
2293 | ATL1_MAX_TX_BUF_LEN : buf_len; | |
2294 | buf_len -= buffer_info->length; | |
9b22c735 IC |
2295 | buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev, |
2296 | frag, i * ATL1_MAX_TX_BUF_LEN, | |
5d6bcdfe | 2297 | buffer_info->length, DMA_TO_DEVICE); |
f3cc28c7 | 2298 | |
6446a860 JC |
2299 | if (++next_to_use == tpd_ring->count) |
2300 | next_to_use = 0; | |
f3cc28c7 JC |
2301 | } |
2302 | } | |
2303 | ||
2304 | /* last tpd's buffer-info */ | |
2305 | buffer_info->skb = skb; | |
2306 | } | |
2307 | ||
6446a860 JC |
2308 | static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, |
2309 | struct tx_packet_desc *ptpd) | |
f3cc28c7 | 2310 | { |
f3cc28c7 | 2311 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
f3cc28c7 JC |
2312 | struct atl1_buffer *buffer_info; |
2313 | struct tx_packet_desc *tpd; | |
6446a860 JC |
2314 | u16 j; |
2315 | u32 val; | |
2316 | u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); | |
f3cc28c7 JC |
2317 | |
2318 | for (j = 0; j < count; j++) { | |
6446a860 JC |
2319 | buffer_info = &tpd_ring->buffer_info[next_to_use]; |
2320 | tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); | |
2321 | if (tpd != ptpd) | |
2322 | memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); | |
f3cc28c7 | 2323 | tpd->buffer_addr = cpu_to_le64(buffer_info->dma); |
dc5596d9 JC |
2324 | tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); |
2325 | tpd->word2 |= (cpu_to_le16(buffer_info->length) & | |
6446a860 | 2326 | TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; |
f3cc28c7 | 2327 | |
6446a860 JC |
2328 | /* |
2329 | * if this is the first packet in a TSO chain, set | |
2330 | * TPD_HDRFLAG, otherwise, clear it. | |
2331 | */ | |
2332 | val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & | |
2333 | TPD_SEGMENT_EN_MASK; | |
2334 | if (val) { | |
2335 | if (!j) | |
2336 | tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; | |
2337 | else | |
2338 | tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); | |
2339 | } | |
f3cc28c7 JC |
2340 | |
2341 | if (j == (count - 1)) | |
6446a860 | 2342 | tpd->word3 |= 1 << TPD_EOP_SHIFT; |
f3cc28c7 | 2343 | |
6446a860 JC |
2344 | if (++next_to_use == tpd_ring->count) |
2345 | next_to_use = 0; | |
f3cc28c7 JC |
2346 | } |
2347 | /* | |
2348 | * Force memory writes to complete before letting h/w | |
2349 | * know there are new descriptors to fetch. (Only | |
2350 | * applicable for weak-ordered memory model archs, | |
2351 | * such as IA-64). | |
2352 | */ | |
2353 | wmb(); | |
2354 | ||
6446a860 | 2355 | atomic_set(&tpd_ring->next_to_use, next_to_use); |
f3cc28c7 JC |
2356 | } |
2357 | ||
61357325 SH |
2358 | static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb, |
2359 | struct net_device *netdev) | |
f3cc28c7 JC |
2360 | { |
2361 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
6446a860 | 2362 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
e743d313 | 2363 | int len; |
f3cc28c7 JC |
2364 | int tso; |
2365 | int count = 1; | |
2366 | int ret_val; | |
6446a860 | 2367 | struct tx_packet_desc *ptpd; |
f3cc28c7 | 2368 | u16 vlan_tag; |
f3cc28c7 JC |
2369 | unsigned int nr_frags = 0; |
2370 | unsigned int mss = 0; | |
2371 | unsigned int f; | |
2372 | unsigned int proto_hdr_len; | |
2373 | ||
e743d313 | 2374 | len = skb_headlen(skb); |
f3cc28c7 | 2375 | |
6446a860 | 2376 | if (unlikely(skb->len <= 0)) { |
f3cc28c7 JC |
2377 | dev_kfree_skb_any(skb); |
2378 | return NETDEV_TX_OK; | |
2379 | } | |
2380 | ||
f3cc28c7 JC |
2381 | nr_frags = skb_shinfo(skb)->nr_frags; |
2382 | for (f = 0; f < nr_frags; f++) { | |
9e903e08 ED |
2383 | unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); |
2384 | count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) / | |
2385 | ATL1_MAX_TX_BUF_LEN; | |
f3cc28c7 JC |
2386 | } |
2387 | ||
f3cc28c7 JC |
2388 | mss = skb_shinfo(skb)->gso_size; |
2389 | if (mss) { | |
17d0cdfa | 2390 | if (skb->protocol == htons(ETH_P_IP)) { |
ea2ae17d | 2391 | proto_hdr_len = (skb_transport_offset(skb) + |
ab6a5bb6 | 2392 | tcp_hdrlen(skb)); |
f3cc28c7 JC |
2393 | if (unlikely(proto_hdr_len > len)) { |
2394 | dev_kfree_skb_any(skb); | |
2395 | return NETDEV_TX_OK; | |
2396 | } | |
2397 | /* need additional TPD ? */ | |
2398 | if (proto_hdr_len != len) | |
2399 | count += (len - proto_hdr_len + | |
53ffb42c JC |
2400 | ATL1_MAX_TX_BUF_LEN - 1) / |
2401 | ATL1_MAX_TX_BUF_LEN; | |
f3cc28c7 JC |
2402 | } |
2403 | } | |
2404 | ||
e6a7ff4a | 2405 | if (atl1_tpd_avail(&adapter->tpd_ring) < count) { |
f3cc28c7 JC |
2406 | /* not enough descriptors */ |
2407 | netif_stop_queue(netdev); | |
6446a860 JC |
2408 | if (netif_msg_tx_queued(adapter)) |
2409 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2410 | "tx busy\n"); | |
f3cc28c7 JC |
2411 | return NETDEV_TX_BUSY; |
2412 | } | |
2413 | ||
6446a860 JC |
2414 | ptpd = ATL1_TPD_DESC(tpd_ring, |
2415 | (u16) atomic_read(&tpd_ring->next_to_use)); | |
2416 | memset(ptpd, 0, sizeof(struct tx_packet_desc)); | |
f3cc28c7 | 2417 | |
eab6d18d | 2418 | if (vlan_tx_tag_present(skb)) { |
f3cc28c7 JC |
2419 | vlan_tag = vlan_tx_tag_get(skb); |
2420 | vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | | |
2421 | ((vlan_tag >> 9) & 0x8); | |
6446a860 | 2422 | ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; |
dc5596d9 JC |
2423 | ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << |
2424 | TPD_VLANTAG_SHIFT; | |
f3cc28c7 JC |
2425 | } |
2426 | ||
6446a860 | 2427 | tso = atl1_tso(adapter, skb, ptpd); |
f3cc28c7 | 2428 | if (tso < 0) { |
f3cc28c7 JC |
2429 | dev_kfree_skb_any(skb); |
2430 | return NETDEV_TX_OK; | |
2431 | } | |
2432 | ||
2433 | if (!tso) { | |
6446a860 | 2434 | ret_val = atl1_tx_csum(adapter, skb, ptpd); |
f3cc28c7 | 2435 | if (ret_val < 0) { |
f3cc28c7 JC |
2436 | dev_kfree_skb_any(skb); |
2437 | return NETDEV_TX_OK; | |
2438 | } | |
2439 | } | |
2440 | ||
6446a860 JC |
2441 | atl1_tx_map(adapter, skb, ptpd); |
2442 | atl1_tx_queue(adapter, count, ptpd); | |
f3cc28c7 | 2443 | atl1_update_mailbox(adapter); |
e1098328 | 2444 | mmiowb(); |
f3cc28c7 JC |
2445 | return NETDEV_TX_OK; |
2446 | } | |
2447 | ||
0dbab2fb | 2448 | static int atl1_rings_clean(struct napi_struct *napi, int budget) |
6294512b TZ |
2449 | { |
2450 | struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi); | |
2451 | int work_done = atl1_intr_rx(adapter, budget); | |
2452 | ||
0dbab2fb TZ |
2453 | if (atl1_intr_tx(adapter)) |
2454 | work_done = budget; | |
2455 | ||
6294512b TZ |
2456 | /* Let's come again to process some more packets */ |
2457 | if (work_done >= budget) | |
2458 | return work_done; | |
2459 | ||
2460 | napi_complete(napi); | |
2461 | /* re-enable Interrupt */ | |
73650f28 TZ |
2462 | if (likely(adapter->int_enabled)) |
2463 | atlx_imr_set(adapter, IMR_NORMAL_MASK); | |
6294512b TZ |
2464 | return work_done; |
2465 | } | |
2466 | ||
0dbab2fb | 2467 | static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter) |
6294512b | 2468 | { |
73650f28 TZ |
2469 | if (!napi_schedule_prep(&adapter->napi)) |
2470 | /* It is possible in case even the RX/TX ints are disabled via IMR | |
2471 | * register the ISR bits are set anyway (but do not produce IRQ). | |
2472 | * To handle such situation the napi functions used to check is | |
2473 | * something scheduled or not. | |
2474 | */ | |
2475 | return 0; | |
2476 | ||
2477 | __napi_schedule(&adapter->napi); | |
2478 | ||
2479 | /* | |
2480 | * Disable RX/TX ints via IMR register if it is | |
2481 | * allowed. NAPI handler must reenable them in same | |
2482 | * way. | |
2483 | */ | |
2484 | if (!adapter->int_enabled) | |
6294512b | 2485 | return 1; |
6294512b | 2486 | |
73650f28 TZ |
2487 | atlx_imr_set(adapter, IMR_NORXTX_MASK); |
2488 | return 1; | |
6294512b TZ |
2489 | } |
2490 | ||
49ce9c2c | 2491 | /** |
05ffdd7b JC |
2492 | * atl1_intr - Interrupt Handler |
2493 | * @irq: interrupt number | |
2494 | * @data: pointer to a network interface device structure | |
f3cc28c7 | 2495 | */ |
05ffdd7b | 2496 | static irqreturn_t atl1_intr(int irq, void *data) |
f3cc28c7 | 2497 | { |
05ffdd7b JC |
2498 | struct atl1_adapter *adapter = netdev_priv(data); |
2499 | u32 status; | |
f3cc28c7 | 2500 | |
05ffdd7b JC |
2501 | status = adapter->cmb.cmb->int_stats; |
2502 | if (!status) | |
2503 | return IRQ_NONE; | |
f3cc28c7 | 2504 | |
136cd14e TZ |
2505 | /* clear CMB interrupt status at once, |
2506 | * but leave rx/tx interrupt status in case it should be dropped | |
2507 | * only if rx/tx processing queued. In other case interrupt | |
2508 | * can be lost. | |
2509 | */ | |
2510 | adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX); | |
05ffdd7b | 2511 | |
2a9bc71e TZ |
2512 | if (status & ISR_GPHY) /* clear phy status */ |
2513 | atlx_clear_phy_int(adapter); | |
05ffdd7b | 2514 | |
2a9bc71e TZ |
2515 | /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ |
2516 | iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); | |
05ffdd7b | 2517 | |
2a9bc71e TZ |
2518 | /* check if SMB intr */ |
2519 | if (status & ISR_SMB) | |
2520 | atl1_inc_smb(adapter); | |
05ffdd7b | 2521 | |
2a9bc71e TZ |
2522 | /* check if PCIE PHY Link down */ |
2523 | if (status & ISR_PHY_LINKDOWN) { | |
2524 | if (netif_msg_intr(adapter)) | |
2525 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2526 | "pcie phy link down %x\n", status); | |
2527 | if (netif_running(adapter->netdev)) { /* reset MAC */ | |
5c3d52ef | 2528 | atlx_irq_disable(adapter); |
03662e41 | 2529 | schedule_work(&adapter->reset_dev_task); |
05ffdd7b | 2530 | return IRQ_HANDLED; |
f3cc28c7 | 2531 | } |
2a9bc71e | 2532 | } |
f3cc28c7 | 2533 | |
2a9bc71e TZ |
2534 | /* check if DMA read/write error ? */ |
2535 | if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { | |
2536 | if (netif_msg_intr(adapter)) | |
2537 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2538 | "pcie DMA r/w error (status = 0x%x)\n", | |
2539 | status); | |
2540 | atlx_irq_disable(adapter); | |
56845d78 | 2541 | schedule_work(&adapter->reset_dev_task); |
2a9bc71e TZ |
2542 | return IRQ_HANDLED; |
2543 | } | |
f3cc28c7 | 2544 | |
2a9bc71e TZ |
2545 | /* link event */ |
2546 | if (status & ISR_GPHY) { | |
2547 | adapter->soft_stats.tx_carrier_errors++; | |
2548 | atl1_check_for_link(adapter); | |
2549 | } | |
05ffdd7b | 2550 | |
2a9bc71e | 2551 | /* transmit or receive event */ |
136cd14e TZ |
2552 | if (status & (ISR_CMB_TX | ISR_CMB_RX) && |
2553 | atl1_sched_rings_clean(adapter)) | |
2554 | adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats & | |
2555 | ~(ISR_CMB_TX | ISR_CMB_RX); | |
2a9bc71e TZ |
2556 | |
2557 | /* rx exception */ | |
2558 | if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | | |
2559 | ISR_RRD_OV | ISR_HOST_RFD_UNRUN | | |
2560 | ISR_HOST_RRD_OV))) { | |
2561 | if (netif_msg_intr(adapter)) | |
2562 | dev_printk(KERN_DEBUG, | |
2563 | &adapter->pdev->dev, | |
2564 | "rx exception, ISR = 0x%x\n", | |
2565 | status); | |
2566 | atl1_sched_rings_clean(adapter); | |
2567 | } | |
05ffdd7b JC |
2568 | |
2569 | /* re-enable Interrupt */ | |
2570 | iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); | |
2571 | return IRQ_HANDLED; | |
f3cc28c7 JC |
2572 | } |
2573 | ||
f3cc28c7 | 2574 | |
49ce9c2c | 2575 | /** |
05ffdd7b JC |
2576 | * atl1_phy_config - Timer Call-back |
2577 | * @data: pointer to netdev cast into an unsigned long | |
2578 | */ | |
2579 | static void atl1_phy_config(unsigned long data) | |
2580 | { | |
6446a860 JC |
2581 | struct atl1_adapter *adapter = (struct atl1_adapter *)data; |
2582 | struct atl1_hw *hw = &adapter->hw; | |
05ffdd7b | 2583 | unsigned long flags; |
f3cc28c7 | 2584 | |
05ffdd7b | 2585 | spin_lock_irqsave(&adapter->lock, flags); |
6446a860 JC |
2586 | adapter->phy_timer_pending = false; |
2587 | atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | |
2588 | atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); | |
2589 | atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); | |
05ffdd7b JC |
2590 | spin_unlock_irqrestore(&adapter->lock, flags); |
2591 | } | |
2592 | ||
6446a860 JC |
2593 | /* |
2594 | * Orphaned vendor comment left intact here: | |
2595 | * <vendor comment> | |
2596 | * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT | |
2597 | * will assert. We do soft reset <0x1400=1> according | |
2598 | * with the SPEC. BUT, it seemes that PCIE or DMA | |
2599 | * state-machine will not be reset. DMAR_TO_INT will | |
2600 | * assert again and again. | |
2601 | * </vendor comment> | |
2602 | */ | |
05ffdd7b | 2603 | |
6446a860 | 2604 | static int atl1_reset(struct atl1_adapter *adapter) |
05ffdd7b JC |
2605 | { |
2606 | int ret; | |
05ffdd7b | 2607 | ret = atl1_reset_hw(&adapter->hw); |
6446a860 | 2608 | if (ret) |
05ffdd7b JC |
2609 | return ret; |
2610 | return atl1_init_hw(&adapter->hw); | |
f3cc28c7 JC |
2611 | } |
2612 | ||
6446a860 | 2613 | static s32 atl1_up(struct atl1_adapter *adapter) |
f3cc28c7 JC |
2614 | { |
2615 | struct net_device *netdev = adapter->netdev; | |
2616 | int err; | |
ab392d2d | 2617 | int irq_flags = 0; |
f3cc28c7 JC |
2618 | |
2619 | /* hardware has been reset, we need to reload some things */ | |
6446a860 | 2620 | atlx_set_multi(netdev); |
2ca13da7 | 2621 | atl1_init_ring_ptrs(adapter); |
6446a860 | 2622 | atlx_restore_vlan(adapter); |
f3cc28c7 | 2623 | err = atl1_alloc_rx_buffers(adapter); |
6446a860 JC |
2624 | if (unlikely(!err)) |
2625 | /* no RX BUFFER allocated */ | |
f3cc28c7 JC |
2626 | return -ENOMEM; |
2627 | ||
2628 | if (unlikely(atl1_configure(adapter))) { | |
2629 | err = -EIO; | |
2630 | goto err_up; | |
2631 | } | |
2632 | ||
2633 | err = pci_enable_msi(adapter->pdev); | |
2634 | if (err) { | |
6446a860 JC |
2635 | if (netif_msg_ifup(adapter)) |
2636 | dev_info(&adapter->pdev->dev, | |
2637 | "Unable to enable MSI: %d\n", err); | |
f3cc28c7 JC |
2638 | irq_flags |= IRQF_SHARED; |
2639 | } | |
2640 | ||
a0607fd3 | 2641 | err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags, |
f3cc28c7 JC |
2642 | netdev->name, netdev); |
2643 | if (unlikely(err)) | |
2644 | goto err_up; | |
2645 | ||
6294512b | 2646 | napi_enable(&adapter->napi); |
6446a860 | 2647 | atlx_irq_enable(adapter); |
f3cc28c7 | 2648 | atl1_check_link(adapter); |
39d48157 | 2649 | netif_start_queue(netdev); |
f3cc28c7 JC |
2650 | return 0; |
2651 | ||
f3cc28c7 JC |
2652 | err_up: |
2653 | pci_disable_msi(adapter->pdev); | |
2654 | /* free rx_buffers */ | |
2655 | atl1_clean_rx_ring(adapter); | |
2656 | return err; | |
2657 | } | |
2658 | ||
6446a860 | 2659 | static void atl1_down(struct atl1_adapter *adapter) |
f3cc28c7 JC |
2660 | { |
2661 | struct net_device *netdev = adapter->netdev; | |
2662 | ||
6294512b | 2663 | napi_disable(&adapter->napi); |
b29be6d3 | 2664 | netif_stop_queue(netdev); |
f3cc28c7 JC |
2665 | del_timer_sync(&adapter->phy_config_timer); |
2666 | adapter->phy_timer_pending = false; | |
2667 | ||
6446a860 | 2668 | atlx_irq_disable(adapter); |
f3cc28c7 JC |
2669 | free_irq(adapter->pdev->irq, netdev); |
2670 | pci_disable_msi(adapter->pdev); | |
2671 | atl1_reset_hw(&adapter->hw); | |
2672 | adapter->cmb.cmb->int_stats = 0; | |
2673 | ||
2674 | adapter->link_speed = SPEED_0; | |
2675 | adapter->link_duplex = -1; | |
2676 | netif_carrier_off(netdev); | |
f3cc28c7 | 2677 | |
f3cc28c7 JC |
2678 | atl1_clean_tx_ring(adapter); |
2679 | atl1_clean_rx_ring(adapter); | |
f3cc28c7 JC |
2680 | } |
2681 | ||
03662e41 | 2682 | static void atl1_reset_dev_task(struct work_struct *work) |
6446a860 JC |
2683 | { |
2684 | struct atl1_adapter *adapter = | |
03662e41 | 2685 | container_of(work, struct atl1_adapter, reset_dev_task); |
6446a860 JC |
2686 | struct net_device *netdev = adapter->netdev; |
2687 | ||
2688 | netif_device_detach(netdev); | |
2689 | atl1_down(adapter); | |
305282ba | 2690 | atl1_up(adapter); |
6446a860 | 2691 | netif_device_attach(netdev); |
305282ba JC |
2692 | } |
2693 | ||
49ce9c2c | 2694 | /** |
6446a860 JC |
2695 | * atl1_change_mtu - Change the Maximum Transfer Unit |
2696 | * @netdev: network interface device structure | |
2697 | * @new_mtu: new value for maximum frame size | |
2698 | * | |
2699 | * Returns 0 on success, negative on failure | |
2700 | */ | |
2701 | static int atl1_change_mtu(struct net_device *netdev, int new_mtu) | |
305282ba JC |
2702 | { |
2703 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
6446a860 JC |
2704 | int old_mtu = netdev->mtu; |
2705 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
305282ba | 2706 | |
6446a860 JC |
2707 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || |
2708 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
2709 | if (netif_msg_link(adapter)) | |
2710 | dev_warn(&adapter->pdev->dev, "invalid MTU setting\n"); | |
2711 | return -EINVAL; | |
305282ba | 2712 | } |
6446a860 JC |
2713 | |
2714 | adapter->hw.max_frame_size = max_frame; | |
2715 | adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; | |
2716 | adapter->rx_buffer_len = (max_frame + 7) & ~7; | |
2717 | adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; | |
2718 | ||
2719 | netdev->mtu = new_mtu; | |
2720 | if ((old_mtu != new_mtu) && netif_running(netdev)) { | |
2721 | atl1_down(adapter); | |
2722 | atl1_up(adapter); | |
2723 | } | |
2724 | ||
2725 | return 0; | |
305282ba JC |
2726 | } |
2727 | ||
49ce9c2c | 2728 | /** |
f3cc28c7 JC |
2729 | * atl1_open - Called when a network interface is made active |
2730 | * @netdev: network interface device structure | |
2731 | * | |
2732 | * Returns 0 on success, negative value on failure | |
2733 | * | |
2734 | * The open entry point is called when a network interface is made | |
2735 | * active by the system (IFF_UP). At this point all resources needed | |
2736 | * for transmit and receive operations are allocated, the interrupt | |
2737 | * handler is registered with the OS, the watchdog timer is started, | |
2738 | * and the stack is notified that the interface is ready. | |
2739 | */ | |
2740 | static int atl1_open(struct net_device *netdev) | |
2741 | { | |
2742 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2743 | int err; | |
2744 | ||
b29be6d3 JC |
2745 | netif_carrier_off(netdev); |
2746 | ||
f3cc28c7 JC |
2747 | /* allocate transmit descriptors */ |
2748 | err = atl1_setup_ring_resources(adapter); | |
2749 | if (err) | |
2750 | return err; | |
2751 | ||
2752 | err = atl1_up(adapter); | |
2753 | if (err) | |
2754 | goto err_up; | |
2755 | ||
2756 | return 0; | |
2757 | ||
2758 | err_up: | |
2759 | atl1_reset(adapter); | |
2760 | return err; | |
2761 | } | |
2762 | ||
49ce9c2c | 2763 | /** |
f3cc28c7 JC |
2764 | * atl1_close - Disables a network interface |
2765 | * @netdev: network interface device structure | |
2766 | * | |
2767 | * Returns 0, this is not allowed to fail | |
2768 | * | |
2769 | * The close entry point is called when an interface is de-activated | |
2770 | * by the OS. The hardware is still under the drivers control, but | |
2771 | * needs to be disabled. A global MAC reset is issued to stop the | |
2772 | * hardware, and all transmit and receive resources are freed. | |
2773 | */ | |
2774 | static int atl1_close(struct net_device *netdev) | |
2775 | { | |
2776 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2777 | atl1_down(adapter); | |
2778 | atl1_free_ring_resources(adapter); | |
2779 | return 0; | |
2780 | } | |
2781 | ||
8bca4242 | 2782 | #ifdef CONFIG_PM_SLEEP |
dd68153d | 2783 | static int atl1_suspend(struct device *dev) |
f3cc28c7 | 2784 | { |
dd68153d | 2785 | struct pci_dev *pdev = to_pci_dev(dev); |
05ffdd7b JC |
2786 | struct net_device *netdev = pci_get_drvdata(pdev); |
2787 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2788 | struct atl1_hw *hw = &adapter->hw; | |
2789 | u32 ctrl = 0; | |
2790 | u32 wufc = adapter->wol; | |
08e0f1dc | 2791 | u32 val; |
08e0f1dc JC |
2792 | u16 speed; |
2793 | u16 duplex; | |
f3cc28c7 JC |
2794 | |
2795 | netif_device_detach(netdev); | |
05ffdd7b JC |
2796 | if (netif_running(netdev)) |
2797 | atl1_down(adapter); | |
f3cc28c7 | 2798 | |
05ffdd7b JC |
2799 | atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); |
2800 | atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); | |
08e0f1dc JC |
2801 | val = ctrl & BMSR_LSTATUS; |
2802 | if (val) | |
6446a860 | 2803 | wufc &= ~ATLX_WUFC_LNKC; |
dd68153d RW |
2804 | if (!wufc) |
2805 | goto disable_wol; | |
f3cc28c7 | 2806 | |
dd68153d | 2807 | if (val) { |
08e0f1dc JC |
2808 | val = atl1_get_speed_and_duplex(hw, &speed, &duplex); |
2809 | if (val) { | |
2810 | if (netif_msg_ifdown(adapter)) | |
2811 | dev_printk(KERN_DEBUG, &pdev->dev, | |
2812 | "error getting speed/duplex\n"); | |
2813 | goto disable_wol; | |
2814 | } | |
05ffdd7b JC |
2815 | |
2816 | ctrl = 0; | |
05ffdd7b | 2817 | |
08e0f1dc JC |
2818 | /* enable magic packet WOL */ |
2819 | if (wufc & ATLX_WUFC_MAG) | |
2820 | ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); | |
05ffdd7b | 2821 | iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); |
08e0f1dc JC |
2822 | ioread32(hw->hw_addr + REG_WOL_CTRL); |
2823 | ||
2824 | /* configure the mac */ | |
2825 | ctrl = MAC_CTRL_RX_EN; | |
2826 | ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : | |
2827 | MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); | |
2828 | if (duplex == FULL_DUPLEX) | |
2829 | ctrl |= MAC_CTRL_DUPLX; | |
2830 | ctrl |= (((u32)adapter->hw.preamble_len & | |
2831 | MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
92491709 | 2832 | __atlx_vlan_mode(netdev->features, &ctrl); |
08e0f1dc | 2833 | if (wufc & ATLX_WUFC_MAG) |
05ffdd7b | 2834 | ctrl |= MAC_CTRL_BC_EN; |
05ffdd7b | 2835 | iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); |
08e0f1dc JC |
2836 | ioread32(hw->hw_addr + REG_MAC_CTRL); |
2837 | ||
2838 | /* poke the PHY */ | |
2839 | ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
2840 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
2841 | iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); | |
2842 | ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
dd68153d | 2843 | } else { |
08e0f1dc JC |
2844 | ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); |
2845 | iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); | |
2846 | ioread32(hw->hw_addr + REG_WOL_CTRL); | |
2847 | iowrite32(0, hw->hw_addr + REG_MAC_CTRL); | |
2848 | ioread32(hw->hw_addr + REG_MAC_CTRL); | |
2849 | hw->phy_configured = false; | |
08e0f1dc | 2850 | } |
05ffdd7b | 2851 | |
dd68153d RW |
2852 | return 0; |
2853 | ||
2854 | disable_wol: | |
08e0f1dc JC |
2855 | iowrite32(0, hw->hw_addr + REG_WOL_CTRL); |
2856 | ioread32(hw->hw_addr + REG_WOL_CTRL); | |
2857 | ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
2858 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
2859 | iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); | |
2860 | ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
08e0f1dc | 2861 | hw->phy_configured = false; |
05ffdd7b JC |
2862 | |
2863 | return 0; | |
f3cc28c7 JC |
2864 | } |
2865 | ||
dd68153d | 2866 | static int atl1_resume(struct device *dev) |
f3cc28c7 | 2867 | { |
dd68153d | 2868 | struct pci_dev *pdev = to_pci_dev(dev); |
05ffdd7b JC |
2869 | struct net_device *netdev = pci_get_drvdata(pdev); |
2870 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
53ffb42c | 2871 | |
08e0f1dc | 2872 | iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); |
05ffdd7b | 2873 | |
08e0f1dc | 2874 | atl1_reset_hw(&adapter->hw); |
05ffdd7b | 2875 | |
ec5a32f6 LT |
2876 | if (netif_running(netdev)) { |
2877 | adapter->cmb.cmb->int_stats = 0; | |
05ffdd7b | 2878 | atl1_up(adapter); |
ec5a32f6 | 2879 | } |
05ffdd7b | 2880 | netif_device_attach(netdev); |
05ffdd7b JC |
2881 | |
2882 | return 0; | |
f3cc28c7 | 2883 | } |
7b7a2bbb | 2884 | #endif |
dd68153d RW |
2885 | |
2886 | static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume); | |
f3cc28c7 | 2887 | |
bf455a22 JC |
2888 | static void atl1_shutdown(struct pci_dev *pdev) |
2889 | { | |
dd68153d RW |
2890 | struct net_device *netdev = pci_get_drvdata(pdev); |
2891 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2892 | ||
98d2f0e6 | 2893 | #ifdef CONFIG_PM_SLEEP |
dd68153d | 2894 | atl1_suspend(&pdev->dev); |
98d2f0e6 | 2895 | #endif |
dd68153d RW |
2896 | pci_wake_from_d3(pdev, adapter->wol); |
2897 | pci_set_power_state(pdev, PCI_D3hot); | |
bf455a22 JC |
2898 | } |
2899 | ||
05ffdd7b JC |
2900 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2901 | static void atl1_poll_controller(struct net_device *netdev) | |
f3cc28c7 | 2902 | { |
05ffdd7b JC |
2903 | disable_irq(netdev->irq); |
2904 | atl1_intr(netdev->irq, netdev); | |
2905 | enable_irq(netdev->irq); | |
f3cc28c7 | 2906 | } |
05ffdd7b | 2907 | #endif |
f3cc28c7 | 2908 | |
825a84d1 SH |
2909 | static const struct net_device_ops atl1_netdev_ops = { |
2910 | .ndo_open = atl1_open, | |
2911 | .ndo_stop = atl1_close, | |
00829823 | 2912 | .ndo_start_xmit = atl1_xmit_frame, |
afc4b13d | 2913 | .ndo_set_rx_mode = atlx_set_multi, |
825a84d1 SH |
2914 | .ndo_validate_addr = eth_validate_addr, |
2915 | .ndo_set_mac_address = atl1_set_mac, | |
2916 | .ndo_change_mtu = atl1_change_mtu, | |
92491709 JP |
2917 | .ndo_fix_features = atlx_fix_features, |
2918 | .ndo_set_features = atlx_set_features, | |
825a84d1 | 2919 | .ndo_do_ioctl = atlx_ioctl, |
00829823 | 2920 | .ndo_tx_timeout = atlx_tx_timeout, |
825a84d1 SH |
2921 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2922 | .ndo_poll_controller = atl1_poll_controller, | |
2923 | #endif | |
2924 | }; | |
2925 | ||
49ce9c2c | 2926 | /** |
f3cc28c7 JC |
2927 | * atl1_probe - Device Initialization Routine |
2928 | * @pdev: PCI device information struct | |
2929 | * @ent: entry in atl1_pci_tbl | |
2930 | * | |
2931 | * Returns 0 on success, negative on failure | |
2932 | * | |
2933 | * atl1_probe initializes an adapter identified by a pci_dev structure. | |
2934 | * The OS initialization, configuring of the adapter private structure, | |
2935 | * and a hardware reset occur. | |
2936 | */ | |
1dd06ae8 | 2937 | static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
f3cc28c7 JC |
2938 | { |
2939 | struct net_device *netdev; | |
2940 | struct atl1_adapter *adapter; | |
2941 | static int cards_found = 0; | |
f3cc28c7 JC |
2942 | int err; |
2943 | ||
2944 | err = pci_enable_device(pdev); | |
2945 | if (err) | |
2946 | return err; | |
2947 | ||
5f08e46b | 2948 | /* |
cdcc520d CS |
2949 | * The atl1 chip can DMA to 64-bit addresses, but it uses a single |
2950 | * shared register for the high 32 bits, so only a single, aligned, | |
2951 | * 4 GB physical address range can be used at a time. | |
2952 | * | |
2953 | * Supporting 64-bit DMA on this hardware is more trouble than it's | |
2954 | * worth. It is far easier to limit to 32-bit DMA than update | |
2955 | * various kernel subsystems to support the mechanics required by a | |
2956 | * fixed-high-32-bit system. | |
5f08e46b | 2957 | */ |
284901a9 | 2958 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
f3cc28c7 | 2959 | if (err) { |
5f08e46b LT |
2960 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
2961 | goto err_dma; | |
f3cc28c7 | 2962 | } |
6446a860 JC |
2963 | /* |
2964 | * Mark all PCI regions associated with PCI device | |
f3cc28c7 JC |
2965 | * pdev as being reserved by owner atl1_driver_name |
2966 | */ | |
6446a860 | 2967 | err = pci_request_regions(pdev, ATLX_DRIVER_NAME); |
f3cc28c7 JC |
2968 | if (err) |
2969 | goto err_request_regions; | |
2970 | ||
6446a860 JC |
2971 | /* |
2972 | * Enables bus-mastering on the device and calls | |
f3cc28c7 JC |
2973 | * pcibios_set_master to do the needed arch specific settings |
2974 | */ | |
2975 | pci_set_master(pdev); | |
2976 | ||
2977 | netdev = alloc_etherdev(sizeof(struct atl1_adapter)); | |
2978 | if (!netdev) { | |
2979 | err = -ENOMEM; | |
2980 | goto err_alloc_etherdev; | |
2981 | } | |
f3cc28c7 JC |
2982 | SET_NETDEV_DEV(netdev, &pdev->dev); |
2983 | ||
2984 | pci_set_drvdata(pdev, netdev); | |
2985 | adapter = netdev_priv(netdev); | |
2986 | adapter->netdev = netdev; | |
2987 | adapter->pdev = pdev; | |
2988 | adapter->hw.back = adapter; | |
6446a860 | 2989 | adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); |
f3cc28c7 JC |
2990 | |
2991 | adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); | |
2992 | if (!adapter->hw.hw_addr) { | |
2993 | err = -EIO; | |
2994 | goto err_pci_iomap; | |
2995 | } | |
2996 | /* get device revision number */ | |
1e006364 | 2997 | adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + |
53ffb42c | 2998 | (REG_MASTER_CTRL + 2)); |
6446a860 JC |
2999 | if (netif_msg_probe(adapter)) |
3000 | dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION); | |
f3cc28c7 JC |
3001 | |
3002 | /* set default ring resource counts */ | |
3003 | adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; | |
3004 | adapter->tpd_ring.count = ATL1_DEFAULT_TPD; | |
3005 | ||
3006 | adapter->mii.dev = netdev; | |
3007 | adapter->mii.mdio_read = mdio_read; | |
3008 | adapter->mii.mdio_write = mdio_write; | |
3009 | adapter->mii.phy_id_mask = 0x1f; | |
3010 | adapter->mii.reg_num_mask = 0x1f; | |
3011 | ||
825a84d1 | 3012 | netdev->netdev_ops = &atl1_netdev_ops; |
f3cc28c7 | 3013 | netdev->watchdog_timeo = 5 * HZ; |
0dbab2fb | 3014 | netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64); |
cb434e38 | 3015 | |
f3cc28c7 JC |
3016 | netdev->ethtool_ops = &atl1_ethtool_ops; |
3017 | adapter->bd_number = cards_found; | |
f3cc28c7 JC |
3018 | |
3019 | /* setup the private structure */ | |
3020 | err = atl1_sw_init(adapter); | |
3021 | if (err) | |
3022 | goto err_common; | |
3023 | ||
3024 | netdev->features = NETIF_F_HW_CSUM; | |
3025 | netdev->features |= NETIF_F_SG; | |
f646968f | 3026 | netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); |
f3cc28c7 | 3027 | |
92491709 | 3028 | netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO | |
f646968f | 3029 | NETIF_F_HW_VLAN_CTAG_RX; |
782d640a MM |
3030 | |
3031 | /* is this valid? see atl1_setup_mac_ctrl() */ | |
3032 | netdev->features |= NETIF_F_RXCSUM; | |
3033 | ||
f3cc28c7 JC |
3034 | /* |
3035 | * patch for some L1 of old version, | |
3036 | * the final version of L1 may not need these | |
3037 | * patches | |
3038 | */ | |
3039 | /* atl1_pcie_patch(adapter); */ | |
3040 | ||
3041 | /* really reset GPHY core */ | |
6446a860 | 3042 | iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); |
f3cc28c7 JC |
3043 | |
3044 | /* | |
3045 | * reset the controller to | |
3046 | * put the device in a known good starting state | |
3047 | */ | |
3048 | if (atl1_reset_hw(&adapter->hw)) { | |
3049 | err = -EIO; | |
3050 | goto err_common; | |
3051 | } | |
3052 | ||
3053 | /* copy the MAC address out of the EEPROM */ | |
6a214fd4 DK |
3054 | if (atl1_read_mac_addr(&adapter->hw)) { |
3055 | /* mark random mac */ | |
e41b2d7f | 3056 | netdev->addr_assign_type = NET_ADDR_RANDOM; |
6a214fd4 | 3057 | } |
f3cc28c7 JC |
3058 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); |
3059 | ||
3060 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
3061 | err = -EIO; | |
3062 | goto err_common; | |
3063 | } | |
3064 | ||
3065 | atl1_check_options(adapter); | |
3066 | ||
3067 | /* pre-init the MAC, and setup link */ | |
3068 | err = atl1_init_hw(&adapter->hw); | |
3069 | if (err) { | |
3070 | err = -EIO; | |
3071 | goto err_common; | |
3072 | } | |
3073 | ||
3074 | atl1_pcie_patch(adapter); | |
3075 | /* assume we have no link for now */ | |
3076 | netif_carrier_off(netdev); | |
f3cc28c7 | 3077 | |
c061b18d | 3078 | setup_timer(&adapter->phy_config_timer, atl1_phy_config, |
e053b628 | 3079 | (unsigned long)adapter); |
f3cc28c7 JC |
3080 | adapter->phy_timer_pending = false; |
3081 | ||
03662e41 | 3082 | INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task); |
f3cc28c7 | 3083 | |
6446a860 | 3084 | INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); |
f3cc28c7 | 3085 | |
f3cc28c7 JC |
3086 | err = register_netdev(netdev); |
3087 | if (err) | |
3088 | goto err_common; | |
3089 | ||
3090 | cards_found++; | |
3091 | atl1_via_workaround(adapter); | |
3092 | return 0; | |
3093 | ||
3094 | err_common: | |
3095 | pci_iounmap(pdev, adapter->hw.hw_addr); | |
3096 | err_pci_iomap: | |
3097 | free_netdev(netdev); | |
3098 | err_alloc_etherdev: | |
3099 | pci_release_regions(pdev); | |
3100 | err_dma: | |
3101 | err_request_regions: | |
3102 | pci_disable_device(pdev); | |
3103 | return err; | |
3104 | } | |
3105 | ||
49ce9c2c | 3106 | /** |
f3cc28c7 JC |
3107 | * atl1_remove - Device Removal Routine |
3108 | * @pdev: PCI device information struct | |
3109 | * | |
3110 | * atl1_remove is called by the PCI subsystem to alert the driver | |
3111 | * that it should release a PCI device. The could be caused by a | |
3112 | * Hot-Plug event, or because the driver is going to be removed from | |
3113 | * memory. | |
3114 | */ | |
093d369d | 3115 | static void atl1_remove(struct pci_dev *pdev) |
f3cc28c7 JC |
3116 | { |
3117 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3118 | struct atl1_adapter *adapter; | |
3119 | /* Device not available. Return. */ | |
3120 | if (!netdev) | |
3121 | return; | |
3122 | ||
3123 | adapter = netdev_priv(netdev); | |
8c754a04 | 3124 | |
6446a860 JC |
3125 | /* |
3126 | * Some atl1 boards lack persistent storage for their MAC, and get it | |
8c754a04 CS |
3127 | * from the BIOS during POST. If we've been messing with the MAC |
3128 | * address, we need to save the permanent one. | |
3129 | */ | |
e6d9f8a3 | 3130 | if (!ether_addr_equal_unaligned(adapter->hw.mac_addr, |
3131 | adapter->hw.perm_mac_addr)) { | |
53ffb42c JC |
3132 | memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, |
3133 | ETH_ALEN); | |
8c754a04 CS |
3134 | atl1_set_mac_addr(&adapter->hw); |
3135 | } | |
3136 | ||
6446a860 | 3137 | iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); |
f3cc28c7 JC |
3138 | unregister_netdev(netdev); |
3139 | pci_iounmap(pdev, adapter->hw.hw_addr); | |
3140 | pci_release_regions(pdev); | |
3141 | free_netdev(netdev); | |
3142 | pci_disable_device(pdev); | |
3143 | } | |
3144 | ||
f3cc28c7 | 3145 | static struct pci_driver atl1_driver = { |
6446a860 | 3146 | .name = ATLX_DRIVER_NAME, |
f3cc28c7 JC |
3147 | .id_table = atl1_pci_tbl, |
3148 | .probe = atl1_probe, | |
093d369d | 3149 | .remove = atl1_remove, |
dd68153d | 3150 | .shutdown = atl1_shutdown, |
7b7a2bbb | 3151 | .driver.pm = &atl1_pm_ops, |
f3cc28c7 JC |
3152 | }; |
3153 | ||
6446a860 JC |
3154 | struct atl1_stats { |
3155 | char stat_string[ETH_GSTRING_LEN]; | |
3156 | int sizeof_stat; | |
3157 | int stat_offset; | |
3158 | }; | |
3159 | ||
3160 | #define ATL1_STAT(m) \ | |
3161 | sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) | |
3162 | ||
3163 | static struct atl1_stats atl1_gstrings_stats[] = { | |
3164 | {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, | |
3165 | {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, | |
3166 | {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, | |
3167 | {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, | |
3168 | {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, | |
3169 | {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, | |
6446a860 JC |
3170 | {"multicast", ATL1_STAT(soft_stats.multicast)}, |
3171 | {"collisions", ATL1_STAT(soft_stats.collisions)}, | |
3172 | {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, | |
3173 | {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, | |
3174 | {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, | |
3175 | {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, | |
3176 | {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, | |
3177 | {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, | |
3178 | {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, | |
3179 | {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, | |
3180 | {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, | |
3181 | {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, | |
3182 | {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, | |
3183 | {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, | |
3184 | {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, | |
3185 | {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, | |
3186 | {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, | |
3187 | {"tx_underun", ATL1_STAT(soft_stats.tx_underun)}, | |
3188 | {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, | |
3189 | {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, | |
3190 | {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, | |
3191 | {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, | |
3192 | {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} | |
3193 | }; | |
3194 | ||
3195 | static void atl1_get_ethtool_stats(struct net_device *netdev, | |
3196 | struct ethtool_stats *stats, u64 *data) | |
305282ba | 3197 | { |
6446a860 | 3198 | struct atl1_adapter *adapter = netdev_priv(netdev); |
305282ba | 3199 | int i; |
6446a860 | 3200 | char *p; |
305282ba | 3201 | |
6446a860 JC |
3202 | for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { |
3203 | p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; | |
3204 | data[i] = (atl1_gstrings_stats[i].sizeof_stat == | |
3205 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
305282ba JC |
3206 | } |
3207 | ||
305282ba JC |
3208 | } |
3209 | ||
6446a860 | 3210 | static int atl1_get_sset_count(struct net_device *netdev, int sset) |
305282ba | 3211 | { |
6446a860 JC |
3212 | switch (sset) { |
3213 | case ETH_SS_STATS: | |
3214 | return ARRAY_SIZE(atl1_gstrings_stats); | |
3215 | default: | |
3216 | return -EOPNOTSUPP; | |
3217 | } | |
305282ba JC |
3218 | } |
3219 | ||
6446a860 JC |
3220 | static int atl1_get_settings(struct net_device *netdev, |
3221 | struct ethtool_cmd *ecmd) | |
305282ba | 3222 | { |
6446a860 JC |
3223 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3224 | struct atl1_hw *hw = &adapter->hw; | |
3225 | ||
3226 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
3227 | SUPPORTED_10baseT_Full | | |
3228 | SUPPORTED_100baseT_Half | | |
3229 | SUPPORTED_100baseT_Full | | |
3230 | SUPPORTED_1000baseT_Full | | |
3231 | SUPPORTED_Autoneg | SUPPORTED_TP); | |
3232 | ecmd->advertising = ADVERTISED_TP; | |
3233 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
3234 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3235 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3236 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { | |
3237 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3238 | ecmd->advertising |= | |
3239 | (ADVERTISED_10baseT_Half | | |
3240 | ADVERTISED_10baseT_Full | | |
3241 | ADVERTISED_100baseT_Half | | |
3242 | ADVERTISED_100baseT_Full | | |
3243 | ADVERTISED_1000baseT_Full); | |
3244 | } else | |
3245 | ecmd->advertising |= (ADVERTISED_1000baseT_Full); | |
3246 | } | |
3247 | ecmd->port = PORT_TP; | |
3248 | ecmd->phy_address = 0; | |
3249 | ecmd->transceiver = XCVR_INTERNAL; | |
3250 | ||
3251 | if (netif_carrier_ok(adapter->netdev)) { | |
3252 | u16 link_speed, link_duplex; | |
3253 | atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); | |
70739497 | 3254 | ethtool_cmd_speed_set(ecmd, link_speed); |
6446a860 JC |
3255 | if (link_duplex == FULL_DUPLEX) |
3256 | ecmd->duplex = DUPLEX_FULL; | |
3257 | else | |
3258 | ecmd->duplex = DUPLEX_HALF; | |
3259 | } else { | |
537fae01 JP |
3260 | ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); |
3261 | ecmd->duplex = DUPLEX_UNKNOWN; | |
6446a860 JC |
3262 | } |
3263 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
3264 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
3265 | ecmd->autoneg = AUTONEG_ENABLE; | |
3266 | else | |
3267 | ecmd->autoneg = AUTONEG_DISABLE; | |
305282ba | 3268 | |
305282ba JC |
3269 | return 0; |
3270 | } | |
3271 | ||
6446a860 JC |
3272 | static int atl1_set_settings(struct net_device *netdev, |
3273 | struct ethtool_cmd *ecmd) | |
305282ba | 3274 | { |
6446a860 JC |
3275 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3276 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3277 | u16 phy_data; |
6446a860 JC |
3278 | int ret_val = 0; |
3279 | u16 old_media_type = hw->media_type; | |
305282ba | 3280 | |
6446a860 JC |
3281 | if (netif_running(adapter->netdev)) { |
3282 | if (netif_msg_link(adapter)) | |
3283 | dev_dbg(&adapter->pdev->dev, | |
3284 | "ethtool shutting down adapter\n"); | |
3285 | atl1_down(adapter); | |
3286 | } | |
3287 | ||
3288 | if (ecmd->autoneg == AUTONEG_ENABLE) | |
3289 | hw->media_type = MEDIA_TYPE_AUTO_SENSOR; | |
3290 | else { | |
25db0338 DD |
3291 | u32 speed = ethtool_cmd_speed(ecmd); |
3292 | if (speed == SPEED_1000) { | |
6446a860 JC |
3293 | if (ecmd->duplex != DUPLEX_FULL) { |
3294 | if (netif_msg_link(adapter)) | |
3295 | dev_warn(&adapter->pdev->dev, | |
3296 | "1000M half is invalid\n"); | |
3297 | ret_val = -EINVAL; | |
3298 | goto exit_sset; | |
3299 | } | |
3300 | hw->media_type = MEDIA_TYPE_1000M_FULL; | |
25db0338 | 3301 | } else if (speed == SPEED_100) { |
6446a860 JC |
3302 | if (ecmd->duplex == DUPLEX_FULL) |
3303 | hw->media_type = MEDIA_TYPE_100M_FULL; | |
3304 | else | |
3305 | hw->media_type = MEDIA_TYPE_100M_HALF; | |
3306 | } else { | |
3307 | if (ecmd->duplex == DUPLEX_FULL) | |
3308 | hw->media_type = MEDIA_TYPE_10M_FULL; | |
3309 | else | |
3310 | hw->media_type = MEDIA_TYPE_10M_HALF; | |
3311 | } | |
3312 | } | |
3313 | switch (hw->media_type) { | |
3314 | case MEDIA_TYPE_AUTO_SENSOR: | |
3315 | ecmd->advertising = | |
3316 | ADVERTISED_10baseT_Half | | |
3317 | ADVERTISED_10baseT_Full | | |
3318 | ADVERTISED_100baseT_Half | | |
3319 | ADVERTISED_100baseT_Full | | |
3320 | ADVERTISED_1000baseT_Full | | |
3321 | ADVERTISED_Autoneg | ADVERTISED_TP; | |
3322 | break; | |
3323 | case MEDIA_TYPE_1000M_FULL: | |
3324 | ecmd->advertising = | |
3325 | ADVERTISED_1000baseT_Full | | |
3326 | ADVERTISED_Autoneg | ADVERTISED_TP; | |
3327 | break; | |
3328 | default: | |
3329 | ecmd->advertising = 0; | |
3330 | break; | |
3331 | } | |
3332 | if (atl1_phy_setup_autoneg_adv(hw)) { | |
3333 | ret_val = -EINVAL; | |
3334 | if (netif_msg_link(adapter)) | |
3335 | dev_warn(&adapter->pdev->dev, | |
3336 | "invalid ethtool speed/duplex setting\n"); | |
3337 | goto exit_sset; | |
3338 | } | |
305282ba JC |
3339 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3340 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
3341 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
3342 | else { | |
3343 | switch (hw->media_type) { | |
3344 | case MEDIA_TYPE_100M_FULL: | |
3345 | phy_data = | |
3346 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
3347 | MII_CR_RESET; | |
3348 | break; | |
3349 | case MEDIA_TYPE_100M_HALF: | |
3350 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
3351 | break; | |
3352 | case MEDIA_TYPE_10M_FULL: | |
3353 | phy_data = | |
3354 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
3355 | break; | |
3356 | default: | |
3357 | /* MEDIA_TYPE_10M_HALF: */ | |
3358 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; | |
3359 | break; | |
3360 | } | |
3361 | } | |
6446a860 JC |
3362 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
3363 | exit_sset: | |
3364 | if (ret_val) | |
3365 | hw->media_type = old_media_type; | |
305282ba | 3366 | |
6446a860 JC |
3367 | if (netif_running(adapter->netdev)) { |
3368 | if (netif_msg_link(adapter)) | |
3369 | dev_dbg(&adapter->pdev->dev, | |
3370 | "ethtool starting adapter\n"); | |
3371 | atl1_up(adapter); | |
3372 | } else if (!ret_val) { | |
3373 | if (netif_msg_link(adapter)) | |
3374 | dev_dbg(&adapter->pdev->dev, | |
3375 | "ethtool resetting adapter\n"); | |
3376 | atl1_reset(adapter); | |
3377 | } | |
3378 | return ret_val; | |
3379 | } | |
305282ba | 3380 | |
6446a860 JC |
3381 | static void atl1_get_drvinfo(struct net_device *netdev, |
3382 | struct ethtool_drvinfo *drvinfo) | |
3383 | { | |
3384 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
305282ba | 3385 | |
082ba88a RK |
3386 | strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); |
3387 | strlcpy(drvinfo->version, ATLX_DRIVER_VERSION, | |
6446a860 | 3388 | sizeof(drvinfo->version)); |
082ba88a | 3389 | strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), |
6446a860 JC |
3390 | sizeof(drvinfo->bus_info)); |
3391 | drvinfo->eedump_len = ATL1_EEDUMP_LEN; | |
3392 | } | |
3393 | ||
3394 | static void atl1_get_wol(struct net_device *netdev, | |
3395 | struct ethtool_wolinfo *wol) | |
3396 | { | |
3397 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3398 | ||
3b259e36 | 3399 | wol->supported = WAKE_MAGIC; |
6446a860 | 3400 | wol->wolopts = 0; |
6446a860 JC |
3401 | if (adapter->wol & ATLX_WUFC_MAG) |
3402 | wol->wolopts |= WAKE_MAGIC; | |
6446a860 JC |
3403 | } |
3404 | ||
3405 | static int atl1_set_wol(struct net_device *netdev, | |
3406 | struct ethtool_wolinfo *wol) | |
3407 | { | |
3408 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3409 | ||
3b259e36 C |
3410 | if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | |
3411 | WAKE_ARP | WAKE_MAGICSECURE)) | |
6446a860 JC |
3412 | return -EOPNOTSUPP; |
3413 | adapter->wol = 0; | |
6446a860 JC |
3414 | if (wol->wolopts & WAKE_MAGIC) |
3415 | adapter->wol |= ATLX_WUFC_MAG; | |
dd68153d RW |
3416 | |
3417 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
3418 | ||
305282ba JC |
3419 | return 0; |
3420 | } | |
3421 | ||
6446a860 | 3422 | static u32 atl1_get_msglevel(struct net_device *netdev) |
305282ba | 3423 | { |
6446a860 JC |
3424 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3425 | return adapter->msg_enable; | |
3426 | } | |
305282ba | 3427 | |
6446a860 JC |
3428 | static void atl1_set_msglevel(struct net_device *netdev, u32 value) |
3429 | { | |
3430 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3431 | adapter->msg_enable = value; | |
3432 | } | |
305282ba | 3433 | |
6446a860 JC |
3434 | static int atl1_get_regs_len(struct net_device *netdev) |
3435 | { | |
3436 | return ATL1_REG_COUNT * sizeof(u32); | |
3437 | } | |
305282ba | 3438 | |
6446a860 JC |
3439 | static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, |
3440 | void *p) | |
3441 | { | |
3442 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3443 | struct atl1_hw *hw = &adapter->hw; | |
3444 | unsigned int i; | |
3445 | u32 *regbuf = p; | |
305282ba | 3446 | |
6446a860 JC |
3447 | for (i = 0; i < ATL1_REG_COUNT; i++) { |
3448 | /* | |
3449 | * This switch statement avoids reserved regions | |
3450 | * of register space. | |
3451 | */ | |
3452 | switch (i) { | |
3453 | case 6 ... 9: | |
3454 | case 14: | |
3455 | case 29 ... 31: | |
3456 | case 34 ... 63: | |
3457 | case 75 ... 127: | |
3458 | case 136 ... 1023: | |
3459 | case 1027 ... 1087: | |
3460 | case 1091 ... 1151: | |
3461 | case 1194 ... 1195: | |
3462 | case 1200 ... 1201: | |
3463 | case 1206 ... 1213: | |
3464 | case 1216 ... 1279: | |
3465 | case 1290 ... 1311: | |
3466 | case 1323 ... 1343: | |
3467 | case 1358 ... 1359: | |
3468 | case 1368 ... 1375: | |
3469 | case 1378 ... 1383: | |
3470 | case 1388 ... 1391: | |
3471 | case 1393 ... 1395: | |
3472 | case 1402 ... 1403: | |
3473 | case 1410 ... 1471: | |
3474 | case 1522 ... 1535: | |
3475 | /* reserved region; don't read it */ | |
3476 | regbuf[i] = 0; | |
3477 | break; | |
3478 | default: | |
3479 | /* unreserved region */ | |
3480 | regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); | |
3481 | } | |
3482 | } | |
3483 | } | |
305282ba | 3484 | |
6446a860 JC |
3485 | static void atl1_get_ringparam(struct net_device *netdev, |
3486 | struct ethtool_ringparam *ring) | |
3487 | { | |
3488 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3489 | struct atl1_tpd_ring *txdr = &adapter->tpd_ring; | |
3490 | struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; | |
305282ba | 3491 | |
6446a860 JC |
3492 | ring->rx_max_pending = ATL1_MAX_RFD; |
3493 | ring->tx_max_pending = ATL1_MAX_TPD; | |
6446a860 JC |
3494 | ring->rx_pending = rxdr->count; |
3495 | ring->tx_pending = txdr->count; | |
6446a860 | 3496 | } |
305282ba | 3497 | |
6446a860 JC |
3498 | static int atl1_set_ringparam(struct net_device *netdev, |
3499 | struct ethtool_ringparam *ring) | |
3500 | { | |
3501 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3502 | struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; | |
3503 | struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; | |
3504 | struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; | |
305282ba | 3505 | |
6446a860 JC |
3506 | struct atl1_tpd_ring tpd_old, tpd_new; |
3507 | struct atl1_rfd_ring rfd_old, rfd_new; | |
3508 | struct atl1_rrd_ring rrd_old, rrd_new; | |
3509 | struct atl1_ring_header rhdr_old, rhdr_new; | |
2f32c867 C |
3510 | struct atl1_smb smb; |
3511 | struct atl1_cmb cmb; | |
6446a860 | 3512 | int err; |
305282ba | 3513 | |
6446a860 JC |
3514 | tpd_old = adapter->tpd_ring; |
3515 | rfd_old = adapter->rfd_ring; | |
3516 | rrd_old = adapter->rrd_ring; | |
3517 | rhdr_old = adapter->ring_header; | |
305282ba | 3518 | |
6446a860 JC |
3519 | if (netif_running(adapter->netdev)) |
3520 | atl1_down(adapter); | |
305282ba | 3521 | |
6446a860 JC |
3522 | rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); |
3523 | rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : | |
3524 | rfdr->count; | |
3525 | rfdr->count = (rfdr->count + 3) & ~3; | |
3526 | rrdr->count = rfdr->count; | |
305282ba | 3527 | |
6446a860 JC |
3528 | tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); |
3529 | tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : | |
3530 | tpdr->count; | |
3531 | tpdr->count = (tpdr->count + 3) & ~3; | |
3532 | ||
3533 | if (netif_running(adapter->netdev)) { | |
3534 | /* try to get new resources before deleting old */ | |
3535 | err = atl1_setup_ring_resources(adapter); | |
3536 | if (err) | |
3537 | goto err_setup_ring; | |
3538 | ||
3539 | /* | |
3540 | * save the new, restore the old in order to free it, | |
3541 | * then restore the new back again | |
3542 | */ | |
305282ba | 3543 | |
6446a860 JC |
3544 | rfd_new = adapter->rfd_ring; |
3545 | rrd_new = adapter->rrd_ring; | |
3546 | tpd_new = adapter->tpd_ring; | |
3547 | rhdr_new = adapter->ring_header; | |
3548 | adapter->rfd_ring = rfd_old; | |
3549 | adapter->rrd_ring = rrd_old; | |
3550 | adapter->tpd_ring = tpd_old; | |
3551 | adapter->ring_header = rhdr_old; | |
2f32c867 C |
3552 | /* |
3553 | * Save SMB and CMB, since atl1_free_ring_resources | |
3554 | * will clear them. | |
3555 | */ | |
3556 | smb = adapter->smb; | |
3557 | cmb = adapter->cmb; | |
6446a860 JC |
3558 | atl1_free_ring_resources(adapter); |
3559 | adapter->rfd_ring = rfd_new; | |
3560 | adapter->rrd_ring = rrd_new; | |
3561 | adapter->tpd_ring = tpd_new; | |
3562 | adapter->ring_header = rhdr_new; | |
2f32c867 C |
3563 | adapter->smb = smb; |
3564 | adapter->cmb = cmb; | |
305282ba | 3565 | |
6446a860 JC |
3566 | err = atl1_up(adapter); |
3567 | if (err) | |
3568 | return err; | |
3569 | } | |
305282ba | 3570 | return 0; |
6446a860 JC |
3571 | |
3572 | err_setup_ring: | |
3573 | adapter->rfd_ring = rfd_old; | |
3574 | adapter->rrd_ring = rrd_old; | |
3575 | adapter->tpd_ring = tpd_old; | |
3576 | adapter->ring_header = rhdr_old; | |
3577 | atl1_up(adapter); | |
3578 | return err; | |
305282ba JC |
3579 | } |
3580 | ||
6446a860 JC |
3581 | static void atl1_get_pauseparam(struct net_device *netdev, |
3582 | struct ethtool_pauseparam *epause) | |
305282ba | 3583 | { |
6446a860 JC |
3584 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3585 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3586 | |
6446a860 JC |
3587 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3588 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3589 | epause->autoneg = AUTONEG_ENABLE; | |
3590 | } else { | |
3591 | epause->autoneg = AUTONEG_DISABLE; | |
305282ba | 3592 | } |
6446a860 JC |
3593 | epause->rx_pause = 1; |
3594 | epause->tx_pause = 1; | |
305282ba JC |
3595 | } |
3596 | ||
6446a860 JC |
3597 | static int atl1_set_pauseparam(struct net_device *netdev, |
3598 | struct ethtool_pauseparam *epause) | |
305282ba | 3599 | { |
6446a860 JC |
3600 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3601 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3602 | |
6446a860 JC |
3603 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3604 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3605 | epause->autoneg = AUTONEG_ENABLE; | |
3606 | } else { | |
3607 | epause->autoneg = AUTONEG_DISABLE; | |
3608 | } | |
3609 | ||
3610 | epause->rx_pause = 1; | |
3611 | epause->tx_pause = 1; | |
3612 | ||
3613 | return 0; | |
305282ba JC |
3614 | } |
3615 | ||
6446a860 JC |
3616 | static void atl1_get_strings(struct net_device *netdev, u32 stringset, |
3617 | u8 *data) | |
3618 | { | |
3619 | u8 *p = data; | |
3620 | int i; | |
305282ba | 3621 | |
6446a860 JC |
3622 | switch (stringset) { |
3623 | case ETH_SS_STATS: | |
3624 | for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { | |
3625 | memcpy(p, atl1_gstrings_stats[i].stat_string, | |
3626 | ETH_GSTRING_LEN); | |
3627 | p += ETH_GSTRING_LEN; | |
3628 | } | |
3629 | break; | |
305282ba | 3630 | } |
305282ba JC |
3631 | } |
3632 | ||
6446a860 | 3633 | static int atl1_nway_reset(struct net_device *netdev) |
305282ba | 3634 | { |
6446a860 JC |
3635 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3636 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3637 | |
6446a860 JC |
3638 | if (netif_running(netdev)) { |
3639 | u16 phy_data; | |
3640 | atl1_down(adapter); | |
305282ba | 3641 | |
6446a860 JC |
3642 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3643 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3644 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
3645 | } else { | |
3646 | switch (hw->media_type) { | |
3647 | case MEDIA_TYPE_100M_FULL: | |
3648 | phy_data = MII_CR_FULL_DUPLEX | | |
3649 | MII_CR_SPEED_100 | MII_CR_RESET; | |
3650 | break; | |
3651 | case MEDIA_TYPE_100M_HALF: | |
3652 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
3653 | break; | |
3654 | case MEDIA_TYPE_10M_FULL: | |
3655 | phy_data = MII_CR_FULL_DUPLEX | | |
3656 | MII_CR_SPEED_10 | MII_CR_RESET; | |
3657 | break; | |
3658 | default: | |
3659 | /* MEDIA_TYPE_10M_HALF */ | |
3660 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; | |
3661 | } | |
3662 | } | |
3663 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); | |
3664 | atl1_up(adapter); | |
305282ba | 3665 | } |
305282ba JC |
3666 | return 0; |
3667 | } | |
3668 | ||
ff2d8d6c | 3669 | static const struct ethtool_ops atl1_ethtool_ops = { |
6446a860 JC |
3670 | .get_settings = atl1_get_settings, |
3671 | .set_settings = atl1_set_settings, | |
3672 | .get_drvinfo = atl1_get_drvinfo, | |
3673 | .get_wol = atl1_get_wol, | |
3674 | .set_wol = atl1_set_wol, | |
3675 | .get_msglevel = atl1_get_msglevel, | |
3676 | .set_msglevel = atl1_set_msglevel, | |
3677 | .get_regs_len = atl1_get_regs_len, | |
3678 | .get_regs = atl1_get_regs, | |
3679 | .get_ringparam = atl1_get_ringparam, | |
3680 | .set_ringparam = atl1_set_ringparam, | |
3681 | .get_pauseparam = atl1_get_pauseparam, | |
3682 | .set_pauseparam = atl1_set_pauseparam, | |
6446a860 | 3683 | .get_link = ethtool_op_get_link, |
6446a860 JC |
3684 | .get_strings = atl1_get_strings, |
3685 | .nway_reset = atl1_nway_reset, | |
3686 | .get_ethtool_stats = atl1_get_ethtool_stats, | |
3687 | .get_sset_count = atl1_get_sset_count, | |
6446a860 | 3688 | }; |
c996f4e8 PH |
3689 | |
3690 | module_pci_driver(atl1_driver); |