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452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
60063497 23#include <linux/atomic.h>
452c1ce2
CS		 24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
5a0e3ad6 42#include <linux/slab.h>
452c1ce2
CS		 43#include <linux/spinlock.h>
44#include <linux/string.h>
45#include <linux/tcp.h>
46#include <linux/timer.h>
47#include <linux/types.h>
48#include <linux/workqueue.h>
49
50#include "atl2.h"
51
52#define ATL2_DRV_VERSION "2.2.3"
53
f27e21a8 54static const char atl2_driver_name[] = "atl2";
452c1ce2 55static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
f27e21a8
SH		 56static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
57static const char atl2_driver_version[] = ATL2_DRV_VERSION;
452c1ce2
CS		 58
59MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
60MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(ATL2_DRV_VERSION);
63
64/*
65 * atl2_pci_tbl - PCI Device ID Table
66 */
a3aa1884 67static DEFINE_PCI_DEVICE_TABLE(atl2_pci_tbl) = {
452c1ce2
CS		 68 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
69 /* required last entry */
70 {0,}
71};
72MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
73
74static void atl2_set_ethtool_ops(struct net_device *netdev);
75
76static void atl2_check_options(struct atl2_adapter *adapter);
77
49ce9c2c 78/**
452c1ce2
CS		 79 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
80 * @adapter: board private structure to initialize
81 *
82 * atl2_sw_init initializes the Adapter private data structure.
83 * Fields are initialized based on PCI device information and
84 * OS network device settings (MTU size).
85 */
86static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
87{
88 struct atl2_hw *hw = &adapter->hw;
89 struct pci_dev *pdev = adapter->pdev;
90
91 /* PCI config space info */
92 hw->vendor_id = pdev->vendor;
93 hw->device_id = pdev->device;
94 hw->subsystem_vendor_id = pdev->subsystem_vendor;
95 hw->subsystem_id = pdev->subsystem_device;
ff938e43 96 hw->revision_id = pdev->revision;
452c1ce2 97
452c1ce2
CS		 98 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
99
100 adapter->wol = 0;
101 adapter->ict = 50000; /* ~100ms */
102 adapter->link_speed = SPEED_0; /* hardware init */
103 adapter->link_duplex = FULL_DUPLEX;
104
105 hw->phy_configured = false;
106 hw->preamble_len = 7;
107 hw->ipgt = 0x60;
108 hw->min_ifg = 0x50;
109 hw->ipgr1 = 0x40;
110 hw->ipgr2 = 0x60;
111 hw->retry_buf = 2;
112 hw->max_retry = 0xf;
113 hw->lcol = 0x37;
114 hw->jam_ipg = 7;
115 hw->fc_rxd_hi = 0;
116 hw->fc_rxd_lo = 0;
117 hw->max_frame_size = adapter->netdev->mtu;
118
119 spin_lock_init(&adapter->stats_lock);
452c1ce2
CS		 120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
49ce9c2c 126/**
452c1ce2
CS		 127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
22bedad3 139 struct netdev_hw_addr *ha;
452c1ce2
CS		 140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 161 netdev_for_each_mc_addr(ha, netdev) {
162 hash_value = atl2_hash_mc_addr(hw, ha->addr);
452c1ce2
CS		 163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
49ce9c2c 180/**
452c1ce2
CS		 181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
49ce9c2c 286/**
452c1ce2
CS		 287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
43d620c8 314 adapter->txd_ring = adapter->ring_vir_addr + offset;
452c1ce2
CS		 315
316 /* Init TXS Ring */
317 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
318 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
319 adapter->txs_dma += offset;
320 adapter->txs_ring = (struct tx_pkt_status *)
321 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
322
323 /* Init RXD Ring */
324 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
325 offset = (adapter->rxd_dma & 127) ?
326 (128 - (adapter->rxd_dma & 127)) : 0;
327 if (offset > 7)
328 offset -= 8;
329 else
330 offset += (128 - 8);
331
332 adapter->rxd_dma += offset;
333 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
334 (adapter->txs_ring_size * 4 + offset));
335
336/*
337 * Read / Write Ptr Initialize:
338 * init_ring_ptrs(adapter);
339 */
340 return 0;
341}
342
49ce9c2c 343/**
452c1ce2
CS		 344 * atl2_irq_enable - Enable default interrupt generation settings
345 * @adapter: board private structure
346 */
347static inline void atl2_irq_enable(struct atl2_adapter *adapter)
348{
349 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
350 ATL2_WRITE_FLUSH(&adapter->hw);
351}
352
49ce9c2c 353/**
452c1ce2
CS		 354 * atl2_irq_disable - Mask off interrupt generation on the NIC
355 * @adapter: board private structure
356 */
357static inline void atl2_irq_disable(struct atl2_adapter *adapter)
358{
359 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
360 ATL2_WRITE_FLUSH(&adapter->hw);
361 synchronize_irq(adapter->pdev->irq);
362}
363
c8f44aff 364static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl)
dc437974
JP		 365{
366 if (features & NETIF_F_HW_VLAN_RX) {
367 /* enable VLAN tag insert/strip */
368 *ctrl |= MAC_CTRL_RMV_VLAN;
369 } else {
370 /* disable VLAN tag insert/strip */
371 *ctrl &= ~MAC_CTRL_RMV_VLAN;
372 }
373}
374
c8f44aff
MM		 375static void atl2_vlan_mode(struct net_device *netdev,
376 netdev_features_t features)
452c1ce2
CS		 377{
378 struct atl2_adapter *adapter = netdev_priv(netdev);
379 u32 ctrl;
380
381 atl2_irq_disable(adapter);
452c1ce2 382
dc437974
JP		 383 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
384 __atl2_vlan_mode(features, &ctrl);
385 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
452c1ce2
CS		 386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
dc437974
JP		 392 atl2_vlan_mode(adapter->netdev, adapter->netdev->features);
393}
394
c8f44aff
MM		 395static netdev_features_t atl2_fix_features(struct net_device *netdev,
396 netdev_features_t features)
dc437974
JP		 397{
398 /*
399 * Since there is no support for separate rx/tx vlan accel
400 * enable/disable make sure tx flag is always in same state as rx.
401 */
402 if (features & NETIF_F_HW_VLAN_RX)
403 features |= NETIF_F_HW_VLAN_TX;
404 else
405 features &= ~NETIF_F_HW_VLAN_TX;
406
407 return features;
408}
409
c8f44aff
MM		 410static int atl2_set_features(struct net_device *netdev,
411 netdev_features_t features)
dc437974 412{
c8f44aff 413 netdev_features_t changed = netdev->features ^ features;
dc437974
JP		 414
415 if (changed & NETIF_F_HW_VLAN_RX)
416 atl2_vlan_mode(netdev, features);
417
418 return 0;
452c1ce2 419}
452c1ce2
CS		 420
421static void atl2_intr_rx(struct atl2_adapter *adapter)
422{
423 struct net_device *netdev = adapter->netdev;
424 struct rx_desc *rxd;
425 struct sk_buff *skb;
426
427 do {
428 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
429 if (!rxd->status.update)
430 break; /* end of tx */
431
432 /* clear this flag at once */
433 rxd->status.update = 0;
434
435 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
436 int rx_size = (int)(rxd->status.pkt_size - 4);
437 /* alloc new buffer */
89d71a66 438 skb = netdev_alloc_skb_ip_align(netdev, rx_size);
452c1ce2
CS		 439 if (NULL == skb) {
440 printk(KERN_WARNING
441 "%s: Mem squeeze, deferring packet.\n",
442 netdev->name);
443 /*
444 * Check that some rx space is free. If not,
445 * free one and mark stats->rx_dropped++.
446 */
02e71731 447 netdev->stats.rx_dropped++;
452c1ce2
CS		 448 break;
449 }
452c1ce2
CS		 450 memcpy(skb->data, rxd->packet, rx_size);
451 skb_put(skb, rx_size);
452 skb->protocol = eth_type_trans(skb, netdev);
dc437974 453 if (rxd->status.vlan) {
452c1ce2
CS		 454 u16 vlan_tag = (rxd->status.vtag>>4) |
455 ((rxd->status.vtag&7) << 13) |
456 ((rxd->status.vtag&8) << 9);
dc437974
JP		 457
458 __vlan_hwaccel_put_tag(skb, vlan_tag);
459 }
452c1ce2 460 netif_rx(skb);
02e71731
SH		 461 netdev->stats.rx_bytes += rx_size;
462 netdev->stats.rx_packets++;
452c1ce2 463 } else {
02e71731 464 netdev->stats.rx_errors++;
452c1ce2
CS		 465
466 if (rxd->status.ok && rxd->status.pkt_size <= 60)
02e71731 467 netdev->stats.rx_length_errors++;
452c1ce2 468 if (rxd->status.mcast)
02e71731 469 netdev->stats.multicast++;
452c1ce2 470 if (rxd->status.crc)
02e71731 471 netdev->stats.rx_crc_errors++;
452c1ce2 472 if (rxd->status.align)
02e71731 473 netdev->stats.rx_frame_errors++;
452c1ce2
CS		 474 }
475
476 /* advance write ptr */
477 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
478 adapter->rxd_write_ptr = 0;
479 } while (1);
480
481 /* update mailbox? */
482 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
483 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
484}
485
486static void atl2_intr_tx(struct atl2_adapter *adapter)
487{
02e71731 488 struct net_device *netdev = adapter->netdev;
452c1ce2
CS		 489 u32 txd_read_ptr;
490 u32 txs_write_ptr;
491 struct tx_pkt_status *txs;
492 struct tx_pkt_header *txph;
493 int free_hole = 0;
494
495 do {
496 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
497 txs = adapter->txs_ring + txs_write_ptr;
498 if (!txs->update)
499 break; /* tx stop here */
500
501 free_hole = 1;
502 txs->update = 0;
503
504 if (++txs_write_ptr == adapter->txs_ring_size)
505 txs_write_ptr = 0;
506 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
507
508 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
509 txph = (struct tx_pkt_header *)
510 (((u8 *)adapter->txd_ring) + txd_read_ptr);
511
512 if (txph->pkt_size != txs->pkt_size) {
513 struct tx_pkt_status *old_txs = txs;
514 printk(KERN_WARNING
515 "%s: txs packet size not consistent with txd"
516 " txd_:0x%08x, txs_:0x%08x!\n",
517 adapter->netdev->name,
518 *(u32 *)txph, *(u32 *)txs);
519 printk(KERN_WARNING
520 "txd read ptr: 0x%x\n",
521 txd_read_ptr);
522 txs = adapter->txs_ring + txs_write_ptr;
523 printk(KERN_WARNING
524 "txs-behind:0x%08x\n",
525 *(u32 *)txs);
526 if (txs_write_ptr < 2) {
527 txs = adapter->txs_ring +
528 (adapter->txs_ring_size +
529 txs_write_ptr - 2);
530 } else {
531 txs = adapter->txs_ring + (txs_write_ptr - 2);
532 }
533 printk(KERN_WARNING
534 "txs-before:0x%08x\n",
535 *(u32 *)txs);
536 txs = old_txs;
537 }
538
539 /* 4for TPH */
540 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
541 if (txd_read_ptr >= adapter->txd_ring_size)
542 txd_read_ptr -= adapter->txd_ring_size;
543
544 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
545
546 /* tx statistics: */
e2f092ff 547 if (txs->ok) {
02e71731
SH		 548 netdev->stats.tx_bytes += txs->pkt_size;
549 netdev->stats.tx_packets++;
e2f092ff 550 }
452c1ce2 551 else
02e71731 552 netdev->stats.tx_errors++;
452c1ce2
CS		 553
554 if (txs->defer)
02e71731 555 netdev->stats.collisions++;
452c1ce2 556 if (txs->abort_col)
02e71731 557 netdev->stats.tx_aborted_errors++;
452c1ce2 558 if (txs->late_col)
02e71731 559 netdev->stats.tx_window_errors++;
452c1ce2 560 if (txs->underun)
02e71731 561 netdev->stats.tx_fifo_errors++;
452c1ce2
CS		 562 } while (1);
563
564 if (free_hole) {
565 if (netif_queue_stopped(adapter->netdev) &&
566 netif_carrier_ok(adapter->netdev))
567 netif_wake_queue(adapter->netdev);
568 }
569}
570
571static void atl2_check_for_link(struct atl2_adapter *adapter)
572{
573 struct net_device *netdev = adapter->netdev;
574 u16 phy_data = 0;
575
576 spin_lock(&adapter->stats_lock);
577 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
578 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
579 spin_unlock(&adapter->stats_lock);
580
581 /* notify upper layer link down ASAP */
582 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
583 if (netif_carrier_ok(netdev)) { /* old link state: Up */
584 printk(KERN_INFO "%s: %s NIC Link is Down\n",
585 atl2_driver_name, netdev->name);
586 adapter->link_speed = SPEED_0;
587 netif_carrier_off(netdev);
588 netif_stop_queue(netdev);
589 }
590 }
591 schedule_work(&adapter->link_chg_task);
592}
593
594static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
595{
596 u16 phy_data;
597 spin_lock(&adapter->stats_lock);
598 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
599 spin_unlock(&adapter->stats_lock);
600}
601
49ce9c2c 602/**
452c1ce2
CS		 603 * atl2_intr - Interrupt Handler
604 * @irq: interrupt number
605 * @data: pointer to a network interface device structure
452c1ce2
CS		 606 */
607static irqreturn_t atl2_intr(int irq, void *data)
608{
609 struct atl2_adapter *adapter = netdev_priv(data);
610 struct atl2_hw *hw = &adapter->hw;
611 u32 status;
612
613 status = ATL2_READ_REG(hw, REG_ISR);
614 if (0 == status)
615 return IRQ_NONE;
616
617 /* link event */
618 if (status & ISR_PHY)
619 atl2_clear_phy_int(adapter);
620
621 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
622 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
623
624 /* check if PCIE PHY Link down */
625 if (status & ISR_PHY_LINKDOWN) {
626 if (netif_running(adapter->netdev)) { /* reset MAC */
627 ATL2_WRITE_REG(hw, REG_ISR, 0);
628 ATL2_WRITE_REG(hw, REG_IMR, 0);
629 ATL2_WRITE_FLUSH(hw);
630 schedule_work(&adapter->reset_task);
631 return IRQ_HANDLED;
632 }
633 }
634
635 /* check if DMA read/write error? */
636 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
637 ATL2_WRITE_REG(hw, REG_ISR, 0);
638 ATL2_WRITE_REG(hw, REG_IMR, 0);
639 ATL2_WRITE_FLUSH(hw);
640 schedule_work(&adapter->reset_task);
641 return IRQ_HANDLED;
642 }
643
644 /* link event */
645 if (status & (ISR_PHY | ISR_MANUAL)) {
02e71731 646 adapter->netdev->stats.tx_carrier_errors++;
452c1ce2
CS		 647 atl2_check_for_link(adapter);
648 }
649
650 /* transmit event */
651 if (status & ISR_TX_EVENT)
652 atl2_intr_tx(adapter);
653
654 /* rx exception */
655 if (status & ISR_RX_EVENT)
656 atl2_intr_rx(adapter);
657
658 /* re-enable Interrupt */
659 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
660 return IRQ_HANDLED;
661}
662
663static int atl2_request_irq(struct atl2_adapter *adapter)
664{
665 struct net_device *netdev = adapter->netdev;
666 int flags, err = 0;
667
668 flags = IRQF_SHARED;
452c1ce2
CS		 669 adapter->have_msi = true;
670 err = pci_enable_msi(adapter->pdev);
671 if (err)
672 adapter->have_msi = false;
673
674 if (adapter->have_msi)
675 flags &= ~IRQF_SHARED;
452c1ce2 676
a0607fd3 677 return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name,
452c1ce2
CS		 678 netdev);
679}
680
49ce9c2c 681/**
452c1ce2
CS		 682 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
683 * @adapter: board private structure
684 *
685 * Free all transmit software resources
686 */
687static void atl2_free_ring_resources(struct atl2_adapter *adapter)
688{
689 struct pci_dev *pdev = adapter->pdev;
690 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
691 adapter->ring_dma);
692}
693
49ce9c2c 694/**
452c1ce2
CS		 695 * atl2_open - Called when a network interface is made active
696 * @netdev: network interface device structure
697 *
698 * Returns 0 on success, negative value on failure
699 *
700 * The open entry point is called when a network interface is made
701 * active by the system (IFF_UP). At this point all resources needed
702 * for transmit and receive operations are allocated, the interrupt
703 * handler is registered with the OS, the watchdog timer is started,
704 * and the stack is notified that the interface is ready.
705 */
706static int atl2_open(struct net_device *netdev)
707{
708 struct atl2_adapter *adapter = netdev_priv(netdev);
709 int err;
710 u32 val;
711
712 /* disallow open during test */
713 if (test_bit(__ATL2_TESTING, &adapter->flags))
714 return -EBUSY;
715
716 /* allocate transmit descriptors */
717 err = atl2_setup_ring_resources(adapter);
718 if (err)
719 return err;
720
721 err = atl2_init_hw(&adapter->hw);
722 if (err) {
723 err = -EIO;
724 goto err_init_hw;
725 }
726
727 /* hardware has been reset, we need to reload some things */
728 atl2_set_multi(netdev);
729 init_ring_ptrs(adapter);
730
452c1ce2 731 atl2_restore_vlan(adapter);
452c1ce2
CS		 732
733 if (atl2_configure(adapter)) {
734 err = -EIO;
735 goto err_config;
736 }
737
738 err = atl2_request_irq(adapter);
739 if (err)
740 goto err_req_irq;
741
742 clear_bit(__ATL2_DOWN, &adapter->flags);
743
e053b628 744 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ));
452c1ce2
CS		 745
746 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
747 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
748 val | MASTER_CTRL_MANUAL_INT);
749
750 atl2_irq_enable(adapter);
751
752 return 0;
753
754err_init_hw:
755err_req_irq:
756err_config:
757 atl2_free_ring_resources(adapter);
758 atl2_reset_hw(&adapter->hw);
759
760 return err;
761}
762
763static void atl2_down(struct atl2_adapter *adapter)
764{
765 struct net_device *netdev = adapter->netdev;
766
767 /* signal that we're down so the interrupt handler does not
768 * reschedule our watchdog timer */
769 set_bit(__ATL2_DOWN, &adapter->flags);
770
452c1ce2 771 netif_tx_disable(netdev);
452c1ce2
CS		 772
773 /* reset MAC to disable all RX/TX */
774 atl2_reset_hw(&adapter->hw);
775 msleep(1);
776
777 atl2_irq_disable(adapter);
778
779 del_timer_sync(&adapter->watchdog_timer);
780 del_timer_sync(&adapter->phy_config_timer);
781 clear_bit(0, &adapter->cfg_phy);
782
783 netif_carrier_off(netdev);
784 adapter->link_speed = SPEED_0;
785 adapter->link_duplex = -1;
786}
787
788static void atl2_free_irq(struct atl2_adapter *adapter)
789{
790 struct net_device *netdev = adapter->netdev;
791
792 free_irq(adapter->pdev->irq, netdev);
793
794#ifdef CONFIG_PCI_MSI
795 if (adapter->have_msi)
796 pci_disable_msi(adapter->pdev);
797#endif
798}
799
49ce9c2c 800/**
452c1ce2
CS		 801 * atl2_close - Disables a network interface
802 * @netdev: network interface device structure
803 *
804 * Returns 0, this is not allowed to fail
805 *
806 * The close entry point is called when an interface is de-activated
807 * by the OS. The hardware is still under the drivers control, but
808 * needs to be disabled. A global MAC reset is issued to stop the
809 * hardware, and all transmit and receive resources are freed.
810 */
811static int atl2_close(struct net_device *netdev)
812{
813 struct atl2_adapter *adapter = netdev_priv(netdev);
814
815 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
816
817 atl2_down(adapter);
818 atl2_free_irq(adapter);
819 atl2_free_ring_resources(adapter);
820
821 return 0;
822}
823
824static inline int TxsFreeUnit(struct atl2_adapter *adapter)
825{
826 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
827
828 return (adapter->txs_next_clear >= txs_write_ptr) ?
829 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
830 txs_write_ptr - 1) :
831 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
832}
833
834static inline int TxdFreeBytes(struct atl2_adapter *adapter)
835{
836 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
837
838 return (adapter->txd_write_ptr >= txd_read_ptr) ?
839 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
840 txd_read_ptr - 1) :
841 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
842}
843
61357325
SH		 844static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb,
845 struct net_device *netdev)
452c1ce2
CS		 846{
847 struct atl2_adapter *adapter = netdev_priv(netdev);
452c1ce2
CS		 848 struct tx_pkt_header *txph;
849 u32 offset, copy_len;
850 int txs_unused;
851 int txbuf_unused;
852
853 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
854 dev_kfree_skb_any(skb);
855 return NETDEV_TX_OK;
856 }
857
858 if (unlikely(skb->len <= 0)) {
859 dev_kfree_skb_any(skb);
860 return NETDEV_TX_OK;
861 }
862
452c1ce2
CS		 863 txs_unused = TxsFreeUnit(adapter);
864 txbuf_unused = TxdFreeBytes(adapter);
865
866 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
867 txs_unused < 1) {
868 /* not enough resources */
869 netif_stop_queue(netdev);
452c1ce2
CS		 870 return NETDEV_TX_BUSY;
871 }
872
873 offset = adapter->txd_write_ptr;
874
875 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
876
877 *(u32 *)txph = 0;
878 txph->pkt_size = skb->len;
879
880 offset += 4;
881 if (offset >= adapter->txd_ring_size)
882 offset -= adapter->txd_ring_size;
883 copy_len = adapter->txd_ring_size - offset;
884 if (copy_len >= skb->len) {
885 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
886 offset += ((u32)(skb->len + 3) & ~3);
887 } else {
888 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
889 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
890 skb->len-copy_len);
891 offset = ((u32)(skb->len-copy_len + 3) & ~3);
892 }
893#ifdef NETIF_F_HW_VLAN_TX
eab6d18d 894 if (vlan_tx_tag_present(skb)) {
452c1ce2
CS		 895 u16 vlan_tag = vlan_tx_tag_get(skb);
896 vlan_tag = (vlan_tag << 4) |
897 (vlan_tag >> 13) |
898 ((vlan_tag >> 9) & 0x8);
899 txph->ins_vlan = 1;
900 txph->vlan = vlan_tag;
901 }
902#endif
903 if (offset >= adapter->txd_ring_size)
904 offset -= adapter->txd_ring_size;
905 adapter->txd_write_ptr = offset;
906
907 /* clear txs before send */
908 adapter->txs_ring[adapter->txs_next_clear].update = 0;
909 if (++adapter->txs_next_clear == adapter->txs_ring_size)
910 adapter->txs_next_clear = 0;
911
912 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
913 (adapter->txd_write_ptr >> 2));
914
87241840 915 mmiowb();
452c1ce2
CS		 916 dev_kfree_skb_any(skb);
917 return NETDEV_TX_OK;
918}
919
49ce9c2c 920/**
452c1ce2
CS		 921 * atl2_change_mtu - Change the Maximum Transfer Unit
922 * @netdev: network interface device structure
923 * @new_mtu: new value for maximum frame size
924 *
925 * Returns 0 on success, negative on failure
926 */
927static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
928{
929 struct atl2_adapter *adapter = netdev_priv(netdev);
930 struct atl2_hw *hw = &adapter->hw;
931
932 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
933 return -EINVAL;
934
935 /* set MTU */
936 if (hw->max_frame_size != new_mtu) {
937 netdev->mtu = new_mtu;
938 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
939 VLAN_SIZE + ETHERNET_FCS_SIZE);
940 }
941
942 return 0;
943}
944
49ce9c2c 945/**
452c1ce2
CS		 946 * atl2_set_mac - Change the Ethernet Address of the NIC
947 * @netdev: network interface device structure
948 * @p: pointer to an address structure
949 *
950 * Returns 0 on success, negative on failure
951 */
952static int atl2_set_mac(struct net_device *netdev, void *p)
953{
954 struct atl2_adapter *adapter = netdev_priv(netdev);
955 struct sockaddr *addr = p;
956
957 if (!is_valid_ether_addr(addr->sa_data))
958 return -EADDRNOTAVAIL;
959
960 if (netif_running(netdev))
961 return -EBUSY;
962
963 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
964 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
965
966 atl2_set_mac_addr(&adapter->hw);
967
968 return 0;
969}
970
452c1ce2
CS		 971static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
972{
973 struct atl2_adapter *adapter = netdev_priv(netdev);
974 struct mii_ioctl_data *data = if_mii(ifr);
975 unsigned long flags;
976
977 switch (cmd) {
978 case SIOCGMIIPHY:
979 data->phy_id = 0;
980 break;
981 case SIOCGMIIREG:
452c1ce2
CS		 982 spin_lock_irqsave(&adapter->stats_lock, flags);
983 if (atl2_read_phy_reg(&adapter->hw,
984 data->reg_num & 0x1F, &data->val_out)) {
985 spin_unlock_irqrestore(&adapter->stats_lock, flags);
986 return -EIO;
987 }
988 spin_unlock_irqrestore(&adapter->stats_lock, flags);
989 break;
990 case SIOCSMIIREG:
452c1ce2
CS		 991 if (data->reg_num & ~(0x1F))
992 return -EFAULT;
993 spin_lock_irqsave(&adapter->stats_lock, flags);
994 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
995 data->val_in)) {
996 spin_unlock_irqrestore(&adapter->stats_lock, flags);
997 return -EIO;
998 }
999 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1000 break;
1001 default:
1002 return -EOPNOTSUPP;
1003 }
1004 return 0;
1005}
1006
452c1ce2
CS		 1007static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1008{
1009 switch (cmd) {
1010 case SIOCGMIIPHY:
1011 case SIOCGMIIREG:
1012 case SIOCSMIIREG:
1013 return atl2_mii_ioctl(netdev, ifr, cmd);
1014#ifdef ETHTOOL_OPS_COMPAT
1015 case SIOCETHTOOL:
1016 return ethtool_ioctl(ifr);
1017#endif
1018 default:
1019 return -EOPNOTSUPP;
1020 }
1021}
1022
49ce9c2c 1023/**
452c1ce2
CS		 1024 * atl2_tx_timeout - Respond to a Tx Hang
1025 * @netdev: network interface device structure
1026 */
1027static void atl2_tx_timeout(struct net_device *netdev)
1028{
1029 struct atl2_adapter *adapter = netdev_priv(netdev);
1030
1031 /* Do the reset outside of interrupt context */
1032 schedule_work(&adapter->reset_task);
1033}
1034
49ce9c2c 1035/**
452c1ce2
CS		 1036 * atl2_watchdog - Timer Call-back
1037 * @data: pointer to netdev cast into an unsigned long
1038 */
1039static void atl2_watchdog(unsigned long data)
1040{
1041 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
452c1ce2
CS		 1042
1043 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
02e71731
SH		 1044 u32 drop_rxd, drop_rxs;
1045 unsigned long flags;
1046
452c1ce2
CS		 1047 spin_lock_irqsave(&adapter->stats_lock, flags);
1048 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1049 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
452c1ce2
CS		 1050 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1051
02e71731
SH		 1052 adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs;
1053
452c1ce2 1054 /* Reset the timer */
e053b628
SH		 1055 mod_timer(&adapter->watchdog_timer,
1056 round_jiffies(jiffies + 4 * HZ));
452c1ce2
CS		 1057 }
1058}
1059
49ce9c2c 1060/**
452c1ce2
CS		 1061 * atl2_phy_config - Timer Call-back
1062 * @data: pointer to netdev cast into an unsigned long
1063 */
1064static void atl2_phy_config(unsigned long data)
1065{
1066 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1067 struct atl2_hw *hw = &adapter->hw;
1068 unsigned long flags;
1069
1070 spin_lock_irqsave(&adapter->stats_lock, flags);
1071 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1072 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1073 MII_CR_RESTART_AUTO_NEG);
1074 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1075 clear_bit(0, &adapter->cfg_phy);
1076}
1077
1078static int atl2_up(struct atl2_adapter *adapter)
1079{
1080 struct net_device *netdev = adapter->netdev;
1081 int err = 0;
1082 u32 val;
1083
1084 /* hardware has been reset, we need to reload some things */
1085
1086 err = atl2_init_hw(&adapter->hw);
1087 if (err) {
1088 err = -EIO;
1089 return err;
1090 }
1091
1092 atl2_set_multi(netdev);
1093 init_ring_ptrs(adapter);
1094
452c1ce2 1095 atl2_restore_vlan(adapter);
452c1ce2
CS		 1096
1097 if (atl2_configure(adapter)) {
1098 err = -EIO;
1099 goto err_up;
1100 }
1101
1102 clear_bit(__ATL2_DOWN, &adapter->flags);
1103
1104 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1105 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1106 MASTER_CTRL_MANUAL_INT);
1107
1108 atl2_irq_enable(adapter);
1109
1110err_up:
1111 return err;
1112}
1113
1114static void atl2_reinit_locked(struct atl2_adapter *adapter)
1115{
1116 WARN_ON(in_interrupt());
1117 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1118 msleep(1);
1119 atl2_down(adapter);
1120 atl2_up(adapter);
1121 clear_bit(__ATL2_RESETTING, &adapter->flags);
1122}
1123
1124static void atl2_reset_task(struct work_struct *work)
1125{
1126 struct atl2_adapter *adapter;
1127 adapter = container_of(work, struct atl2_adapter, reset_task);
1128
1129 atl2_reinit_locked(adapter);
1130}
1131
1132static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1133{
1134 u32 value;
1135 struct atl2_hw *hw = &adapter->hw;
1136 struct net_device *netdev = adapter->netdev;
1137
1138 /* Config MAC CTRL Register */
1139 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1140
1141 /* duplex */
1142 if (FULL_DUPLEX == adapter->link_duplex)
1143 value |= MAC_CTRL_DUPLX;
1144
1145 /* flow control */
1146 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1147
1148 /* PAD & CRC */
1149 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1150
1151 /* preamble length */
1152 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1153 MAC_CTRL_PRMLEN_SHIFT);
1154
1155 /* vlan */
dc437974 1156 __atl2_vlan_mode(netdev->features, &value);
452c1ce2
CS		 1157
1158 /* filter mode */
1159 value |= MAC_CTRL_BC_EN;
1160 if (netdev->flags & IFF_PROMISC)
1161 value |= MAC_CTRL_PROMIS_EN;
1162 else if (netdev->flags & IFF_ALLMULTI)
1163 value |= MAC_CTRL_MC_ALL_EN;
1164
1165 /* half retry buffer */
1166 value |= (((u32)(adapter->hw.retry_buf &
1167 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1168
1169 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1170}
1171
1172static int atl2_check_link(struct atl2_adapter *adapter)
1173{
1174 struct atl2_hw *hw = &adapter->hw;
1175 struct net_device *netdev = adapter->netdev;
1176 int ret_val;
1177 u16 speed, duplex, phy_data;
1178 int reconfig = 0;
1179
1180 /* MII_BMSR must read twise */
1181 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1182 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1183 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1184 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1185 u32 value;
1186 /* disable rx */
1187 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1188 value &= ~MAC_CTRL_RX_EN;
1189 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1190 adapter->link_speed = SPEED_0;
1191 netif_carrier_off(netdev);
1192 netif_stop_queue(netdev);
1193 }
1194 return 0;
1195 }
1196
1197 /* Link Up */
1198 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1199 if (ret_val)
1200 return ret_val;
1201 switch (hw->MediaType) {
1202 case MEDIA_TYPE_100M_FULL:
1203 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1204 reconfig = 1;
1205 break;
1206 case MEDIA_TYPE_100M_HALF:
1207 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1208 reconfig = 1;
1209 break;
1210 case MEDIA_TYPE_10M_FULL:
1211 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1212 reconfig = 1;
1213 break;
1214 case MEDIA_TYPE_10M_HALF:
1215 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1216 reconfig = 1;
1217 break;
1218 }
1219 /* link result is our setting */
1220 if (reconfig == 0) {
1221 if (adapter->link_speed != speed ||
1222 adapter->link_duplex != duplex) {
1223 adapter->link_speed = speed;
1224 adapter->link_duplex = duplex;
1225 atl2_setup_mac_ctrl(adapter);
1226 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1227 atl2_driver_name, netdev->name,
1228 adapter->link_speed,
1229 adapter->link_duplex == FULL_DUPLEX ?
1230 "Full Duplex" : "Half Duplex");
1231 }
1232
1233 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1234 netif_carrier_on(netdev);
1235 netif_wake_queue(netdev);
1236 }
1237 return 0;
1238 }
1239
1240 /* change original link status */
1241 if (netif_carrier_ok(netdev)) {
1242 u32 value;
1243 /* disable rx */
1244 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1245 value &= ~MAC_CTRL_RX_EN;
1246 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1247
1248 adapter->link_speed = SPEED_0;
1249 netif_carrier_off(netdev);
1250 netif_stop_queue(netdev);
1251 }
1252
1253 /* auto-neg, insert timer to re-config phy
1254 * (if interval smaller than 5 seconds, something strange) */
1255 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1256 if (!test_and_set_bit(0, &adapter->cfg_phy))
e053b628
SH		 1257 mod_timer(&adapter->phy_config_timer,
1258 round_jiffies(jiffies + 5 * HZ));
452c1ce2
CS		 1259 }
1260
1261 return 0;
1262}
1263
49ce9c2c 1264/**
452c1ce2 1265 * atl2_link_chg_task - deal with link change event Out of interrupt context
452c1ce2
CS		 1266 */
1267static void atl2_link_chg_task(struct work_struct *work)
1268{
1269 struct atl2_adapter *adapter;
1270 unsigned long flags;
1271
1272 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1273
1274 spin_lock_irqsave(&adapter->stats_lock, flags);
1275 atl2_check_link(adapter);
1276 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1277}
1278
1279static void atl2_setup_pcicmd(struct pci_dev *pdev)
1280{
1281 u16 cmd;
1282
1283 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1284
1285 if (cmd & PCI_COMMAND_INTX_DISABLE)
1286 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1287 if (cmd & PCI_COMMAND_IO)
1288 cmd &= ~PCI_COMMAND_IO;
1289 if (0 == (cmd & PCI_COMMAND_MEMORY))
1290 cmd |= PCI_COMMAND_MEMORY;
1291 if (0 == (cmd & PCI_COMMAND_MASTER))
1292 cmd |= PCI_COMMAND_MASTER;
1293 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1294
1295 /*
1296 * some motherboards BIOS(PXE/EFI) driver may set PME
1297 * while they transfer control to OS (Windows/Linux)
1298 * so we should clear this bit before NIC work normally
1299 */
1300 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1301}
1302
8d1b1fc9
KH		 1303#ifdef CONFIG_NET_POLL_CONTROLLER
1304static void atl2_poll_controller(struct net_device *netdev)
1305{
1306 disable_irq(netdev->irq);
1307 atl2_intr(netdev->irq, netdev);
1308 enable_irq(netdev->irq);
1309}
1310#endif
1311
825a84d1
SH		 1312
1313static const struct net_device_ops atl2_netdev_ops = {
1314 .ndo_open = atl2_open,
1315 .ndo_stop = atl2_close,
00829823 1316 .ndo_start_xmit = atl2_xmit_frame,
afc4b13d 1317 .ndo_set_rx_mode = atl2_set_multi,
825a84d1
SH		 1318 .ndo_validate_addr = eth_validate_addr,
1319 .ndo_set_mac_address = atl2_set_mac,
1320 .ndo_change_mtu = atl2_change_mtu,
dc437974
JP		 1321 .ndo_fix_features = atl2_fix_features,
1322 .ndo_set_features = atl2_set_features,
825a84d1
SH		 1323 .ndo_do_ioctl = atl2_ioctl,
1324 .ndo_tx_timeout = atl2_tx_timeout,
825a84d1
SH		 1325#ifdef CONFIG_NET_POLL_CONTROLLER
1326 .ndo_poll_controller = atl2_poll_controller,
1327#endif
1328};
1329
49ce9c2c 1330/**
452c1ce2
CS		 1331 * atl2_probe - Device Initialization Routine
1332 * @pdev: PCI device information struct
1333 * @ent: entry in atl2_pci_tbl
1334 *
1335 * Returns 0 on success, negative on failure
1336 *
1337 * atl2_probe initializes an adapter identified by a pci_dev structure.
1338 * The OS initialization, configuring of the adapter private structure,
1339 * and a hardware reset occur.
1340 */
1341static int __devinit atl2_probe(struct pci_dev *pdev,
1342 const struct pci_device_id *ent)
1343{
1344 struct net_device *netdev;
1345 struct atl2_adapter *adapter;
1346 static int cards_found;
1347 unsigned long mmio_start;
1348 int mmio_len;
1349 int err;
1350
1351 cards_found = 0;
1352
1353 err = pci_enable_device(pdev);
1354 if (err)
1355 return err;
1356
1357 /*
1358 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1359 * until the kernel has the proper infrastructure to support 64-bit DMA
1360 * on these devices.
1361 */
284901a9
YH		 1362 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) &&
1363 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
452c1ce2
CS		 1364 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1365 goto err_dma;
1366 }
1367
1368 /* Mark all PCI regions associated with PCI device
1369 * pdev as being reserved by owner atl2_driver_name */
1370 err = pci_request_regions(pdev, atl2_driver_name);
1371 if (err)
1372 goto err_pci_reg;
1373
1374 /* Enables bus-mastering on the device and calls
1375 * pcibios_set_master to do the needed arch specific settings */
1376 pci_set_master(pdev);
1377
1378 err = -ENOMEM;
1379 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1380 if (!netdev)
1381 goto err_alloc_etherdev;
1382
1383 SET_NETDEV_DEV(netdev, &pdev->dev);
1384
1385 pci_set_drvdata(pdev, netdev);
1386 adapter = netdev_priv(netdev);
1387 adapter->netdev = netdev;
1388 adapter->pdev = pdev;
1389 adapter->hw.back = adapter;
1390
1391 mmio_start = pci_resource_start(pdev, 0x0);
1392 mmio_len = pci_resource_len(pdev, 0x0);
1393
1394 adapter->hw.mem_rang = (u32)mmio_len;
1395 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1396 if (!adapter->hw.hw_addr) {
1397 err = -EIO;
1398 goto err_ioremap;
1399 }
1400
1401 atl2_setup_pcicmd(pdev);
1402
825a84d1 1403 netdev->netdev_ops = &atl2_netdev_ops;
452c1ce2 1404 atl2_set_ethtool_ops(netdev);
452c1ce2 1405 netdev->watchdog_timeo = 5 * HZ;
452c1ce2
CS		 1406 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1407
1408 netdev->mem_start = mmio_start;
1409 netdev->mem_end = mmio_start + mmio_len;
1410 adapter->bd_number = cards_found;
1411 adapter->pci_using_64 = false;
1412
1413 /* setup the private structure */
1414 err = atl2_sw_init(adapter);
1415 if (err)
1416 goto err_sw_init;
1417
1418 err = -EIO;
1419
dc437974 1420 netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_RX;
452c1ce2 1421 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
452c1ce2 1422
452c1ce2
CS		 1423 /* Init PHY as early as possible due to power saving issue */
1424 atl2_phy_init(&adapter->hw);
1425
1426 /* reset the controller to
1427 * put the device in a known good starting state */
1428
1429 if (atl2_reset_hw(&adapter->hw)) {
1430 err = -EIO;
1431 goto err_reset;
1432 }
1433
1434 /* copy the MAC address out of the EEPROM */
1435 atl2_read_mac_addr(&adapter->hw);
1436 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1437/* FIXME: do we still need this? */
1438#ifdef ETHTOOL_GPERMADDR
1439 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1440
1441 if (!is_valid_ether_addr(netdev->perm_addr)) {
1442#else
1443 if (!is_valid_ether_addr(netdev->dev_addr)) {
1444#endif
1445 err = -EIO;
1446 goto err_eeprom;
1447 }
1448
1449 atl2_check_options(adapter);
1450
1451 init_timer(&adapter->watchdog_timer);
c061b18d 1452 adapter->watchdog_timer.function = atl2_watchdog;
452c1ce2
CS		 1453 adapter->watchdog_timer.data = (unsigned long) adapter;
1454
1455 init_timer(&adapter->phy_config_timer);
c061b18d 1456 adapter->phy_config_timer.function = atl2_phy_config;
452c1ce2
CS		 1457 adapter->phy_config_timer.data = (unsigned long) adapter;
1458
1459 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1460 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1461
1462 strcpy(netdev->name, "eth%d"); /* ?? */
1463 err = register_netdev(netdev);
1464 if (err)
1465 goto err_register;
1466
1467 /* assume we have no link for now */
1468 netif_carrier_off(netdev);
1469 netif_stop_queue(netdev);
1470
1471 cards_found++;
1472
1473 return 0;
1474
1475err_reset:
1476err_register:
1477err_sw_init:
1478err_eeprom:
1479 iounmap(adapter->hw.hw_addr);
1480err_ioremap:
1481 free_netdev(netdev);
1482err_alloc_etherdev:
1483 pci_release_regions(pdev);
1484err_pci_reg:
1485err_dma:
1486 pci_disable_device(pdev);
1487 return err;
1488}
1489
49ce9c2c 1490/**
452c1ce2
CS		 1491 * atl2_remove - Device Removal Routine
1492 * @pdev: PCI device information struct
1493 *
1494 * atl2_remove is called by the PCI subsystem to alert the driver
1495 * that it should release a PCI device. The could be caused by a
1496 * Hot-Plug event, or because the driver is going to be removed from
1497 * memory.
1498 */
1499/* FIXME: write the original MAC address back in case it was changed from a
1500 * BIOS-set value, as in atl1 -- CHS */
1501static void __devexit atl2_remove(struct pci_dev *pdev)
1502{
1503 struct net_device *netdev = pci_get_drvdata(pdev);
1504 struct atl2_adapter *adapter = netdev_priv(netdev);
1505
1506 /* flush_scheduled work may reschedule our watchdog task, so
1507 * explicitly disable watchdog tasks from being rescheduled */
1508 set_bit(__ATL2_DOWN, &adapter->flags);
1509
1510 del_timer_sync(&adapter->watchdog_timer);
1511 del_timer_sync(&adapter->phy_config_timer);
23f333a2
TH		 1512 cancel_work_sync(&adapter->reset_task);
1513 cancel_work_sync(&adapter->link_chg_task);
452c1ce2
CS		 1514
1515 unregister_netdev(netdev);
1516
1517 atl2_force_ps(&adapter->hw);
1518
1519 iounmap(adapter->hw.hw_addr);
1520 pci_release_regions(pdev);
1521
1522 free_netdev(netdev);
1523
1524 pci_disable_device(pdev);
1525}
1526
1527static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1528{
1529 struct net_device *netdev = pci_get_drvdata(pdev);
1530 struct atl2_adapter *adapter = netdev_priv(netdev);
1531 struct atl2_hw *hw = &adapter->hw;
1532 u16 speed, duplex;
1533 u32 ctrl = 0;
1534 u32 wufc = adapter->wol;
1535
1536#ifdef CONFIG_PM
1537 int retval = 0;
1538#endif
1539
1540 netif_device_detach(netdev);
1541
1542 if (netif_running(netdev)) {
1543 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1544 atl2_down(adapter);
1545 }
1546
1547#ifdef CONFIG_PM
1548 retval = pci_save_state(pdev);
1549 if (retval)
1550 return retval;
1551#endif
1552
1553 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1554 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1555 if (ctrl & BMSR_LSTATUS)
1556 wufc &= ~ATLX_WUFC_LNKC;
1557
1558 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1559 u32 ret_val;
1560 /* get current link speed & duplex */
1561 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1562 if (ret_val) {
1563 printk(KERN_DEBUG
1564 "%s: get speed&duplex error while suspend\n",
1565 atl2_driver_name);
1566 goto wol_dis;
1567 }
1568
1569 ctrl = 0;
1570
1571 /* turn on magic packet wol */
1572 if (wufc & ATLX_WUFC_MAG)
1573 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1574
1575 /* ignore Link Chg event when Link is up */
1576 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1577
1578 /* Config MAC CTRL Register */
1579 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1580 if (FULL_DUPLEX == adapter->link_duplex)
1581 ctrl |= MAC_CTRL_DUPLX;
1582 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1583 ctrl |= (((u32)adapter->hw.preamble_len &
1584 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1585 ctrl |= (((u32)(adapter->hw.retry_buf &
1586 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1587 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1588 if (wufc & ATLX_WUFC_MAG) {
1589 /* magic packet maybe Broadcast&multicast&Unicast */
1590 ctrl |= MAC_CTRL_BC_EN;
1591 }
1592
1593 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1594
1595 /* pcie patch */
1596 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1597 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1598 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1599 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1600 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1601 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1602
1603 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1604 goto suspend_exit;
1605 }
1606
1607 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1608 /* link is down, so only LINK CHG WOL event enable */
1609 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1610 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1611 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1612
1613 /* pcie patch */
1614 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1615 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1616 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1617 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1618 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1619 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1620
1621 hw->phy_configured = false; /* re-init PHY when resume */
1622
1623 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1624
1625 goto suspend_exit;
1626 }
1627
1628wol_dis:
1629 /* WOL disabled */
1630 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1631
1632 /* pcie patch */
1633 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1634 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1635 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1636 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1637 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1638 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1639
1640 atl2_force_ps(hw);
1641 hw->phy_configured = false; /* re-init PHY when resume */
1642
1643 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1644
1645suspend_exit:
1646 if (netif_running(netdev))
1647 atl2_free_irq(adapter);
1648
1649 pci_disable_device(pdev);
1650
1651 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1652
1653 return 0;
1654}
1655
1656#ifdef CONFIG_PM
1657static int atl2_resume(struct pci_dev *pdev)
1658{
1659 struct net_device *netdev = pci_get_drvdata(pdev);
1660 struct atl2_adapter *adapter = netdev_priv(netdev);
1661 u32 err;
1662
1663 pci_set_power_state(pdev, PCI_D0);
1664 pci_restore_state(pdev);
1665
1666 err = pci_enable_device(pdev);
1667 if (err) {
1668 printk(KERN_ERR
1669 "atl2: Cannot enable PCI device from suspend\n");
1670 return err;
1671 }
1672
1673 pci_set_master(pdev);
1674
1675 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1676
1677 pci_enable_wake(pdev, PCI_D3hot, 0);
1678 pci_enable_wake(pdev, PCI_D3cold, 0);
1679
1680 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1681
a849854f
AJ		 1682 if (netif_running(netdev)) {
1683 err = atl2_request_irq(adapter);
1684 if (err)
1685 return err;
1686 }
452c1ce2
CS		 1687
1688 atl2_reset_hw(&adapter->hw);
1689
1690 if (netif_running(netdev))
1691 atl2_up(adapter);
1692
1693 netif_device_attach(netdev);
1694
1695 return 0;
1696}
1697#endif
1698
1699static void atl2_shutdown(struct pci_dev *pdev)
1700{
1701 atl2_suspend(pdev, PMSG_SUSPEND);
1702}
1703
1704static struct pci_driver atl2_driver = {
1705 .name = atl2_driver_name,
1706 .id_table = atl2_pci_tbl,
1707 .probe = atl2_probe,
1708 .remove = __devexit_p(atl2_remove),
25985edc 1709 /* Power Management Hooks */
452c1ce2
CS		 1710 .suspend = atl2_suspend,
1711#ifdef CONFIG_PM
1712 .resume = atl2_resume,
1713#endif
1714 .shutdown = atl2_shutdown,
1715};
1716
49ce9c2c 1717/**
452c1ce2
CS		 1718 * atl2_init_module - Driver Registration Routine
1719 *
1720 * atl2_init_module is the first routine called when the driver is
1721 * loaded. All it does is register with the PCI subsystem.
1722 */
1723static int __init atl2_init_module(void)
1724{
1725 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1726 atl2_driver_version);
1727 printk(KERN_INFO "%s\n", atl2_copyright);
1728 return pci_register_driver(&atl2_driver);
1729}
1730module_init(atl2_init_module);
1731
49ce9c2c 1732/**
452c1ce2
CS		 1733 * atl2_exit_module - Driver Exit Cleanup Routine
1734 *
1735 * atl2_exit_module is called just before the driver is removed
1736 * from memory.
1737 */
1738static void __exit atl2_exit_module(void)
1739{
1740 pci_unregister_driver(&atl2_driver);
1741}
1742module_exit(atl2_exit_module);
1743
1744static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1745{
1746 struct atl2_adapter *adapter = hw->back;
1747 pci_read_config_word(adapter->pdev, reg, value);
1748}
1749
1750static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1751{
1752 struct atl2_adapter *adapter = hw->back;
1753 pci_write_config_word(adapter->pdev, reg, *value);
1754}
1755
1756static int atl2_get_settings(struct net_device *netdev,
1757 struct ethtool_cmd *ecmd)
1758{
1759 struct atl2_adapter *adapter = netdev_priv(netdev);
1760 struct atl2_hw *hw = &adapter->hw;
1761
1762 ecmd->supported = (SUPPORTED_10baseT_Half |
1763 SUPPORTED_10baseT_Full |
1764 SUPPORTED_100baseT_Half |
1765 SUPPORTED_100baseT_Full |
1766 SUPPORTED_Autoneg |
1767 SUPPORTED_TP);
1768 ecmd->advertising = ADVERTISED_TP;
1769
1770 ecmd->advertising |= ADVERTISED_Autoneg;
1771 ecmd->advertising |= hw->autoneg_advertised;
1772
1773 ecmd->port = PORT_TP;
1774 ecmd->phy_address = 0;
1775 ecmd->transceiver = XCVR_INTERNAL;
1776
1777 if (adapter->link_speed != SPEED_0) {
70739497 1778 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
452c1ce2
CS		 1779 if (adapter->link_duplex == FULL_DUPLEX)
1780 ecmd->duplex = DUPLEX_FULL;
1781 else
1782 ecmd->duplex = DUPLEX_HALF;
1783 } else {
70739497 1784 ethtool_cmd_speed_set(ecmd, -1);
452c1ce2
CS		 1785 ecmd->duplex = -1;
1786 }
1787
1788 ecmd->autoneg = AUTONEG_ENABLE;
1789 return 0;
1790}
1791
1792static int atl2_set_settings(struct net_device *netdev,
1793 struct ethtool_cmd *ecmd)
1794{
1795 struct atl2_adapter *adapter = netdev_priv(netdev);
1796 struct atl2_hw *hw = &adapter->hw;
1797
1798 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1799 msleep(1);
1800
1801 if (ecmd->autoneg == AUTONEG_ENABLE) {
1802#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1803 ADVERTISE_10_FULL | \
1804 ADVERTISE_100_HALF| \
1805 ADVERTISE_100_FULL)
1806
1807 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1808 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1809 hw->autoneg_advertised = MY_ADV_MASK;
1810 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1811 ADVERTISE_100_FULL) {
1812 hw->MediaType = MEDIA_TYPE_100M_FULL;
1813 hw->autoneg_advertised = ADVERTISE_100_FULL;
1814 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1815 ADVERTISE_100_HALF) {
1816 hw->MediaType = MEDIA_TYPE_100M_HALF;
1817 hw->autoneg_advertised = ADVERTISE_100_HALF;
1818 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1819 ADVERTISE_10_FULL) {
1820 hw->MediaType = MEDIA_TYPE_10M_FULL;
1821 hw->autoneg_advertised = ADVERTISE_10_FULL;
1822 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1823 ADVERTISE_10_HALF) {
1824 hw->MediaType = MEDIA_TYPE_10M_HALF;
1825 hw->autoneg_advertised = ADVERTISE_10_HALF;
1826 } else {
1827 clear_bit(__ATL2_RESETTING, &adapter->flags);
1828 return -EINVAL;
1829 }
1830 ecmd->advertising = hw->autoneg_advertised |
1831 ADVERTISED_TP | ADVERTISED_Autoneg;
1832 } else {
1833 clear_bit(__ATL2_RESETTING, &adapter->flags);
1834 return -EINVAL;
1835 }
1836
1837 /* reset the link */
1838 if (netif_running(adapter->netdev)) {
1839 atl2_down(adapter);
1840 atl2_up(adapter);
1841 } else
1842 atl2_reset_hw(&adapter->hw);
1843
1844 clear_bit(__ATL2_RESETTING, &adapter->flags);
1845 return 0;
1846}
1847
452c1ce2
CS		 1848static u32 atl2_get_msglevel(struct net_device *netdev)
1849{
1850 return 0;
1851}
1852
1853/*
1854 * It's sane for this to be empty, but we might want to take advantage of this.
1855 */
1856static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1857{
1858}
1859
1860static int atl2_get_regs_len(struct net_device *netdev)
1861{
1862#define ATL2_REGS_LEN 42
1863 return sizeof(u32) * ATL2_REGS_LEN;
1864}
1865
1866static void atl2_get_regs(struct net_device *netdev,
1867 struct ethtool_regs *regs, void *p)
1868{
1869 struct atl2_adapter *adapter = netdev_priv(netdev);
1870 struct atl2_hw *hw = &adapter->hw;
1871 u32 *regs_buff = p;
1872 u16 phy_data;
1873
1874 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1875
1876 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1877
1878 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1879 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1880 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1881 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1882 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1883 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1884 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1885 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1886 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1887 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1888 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1889 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1890 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1891 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1892 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1893 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1894 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1895 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1896 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1897 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1898 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1899 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1900 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1901 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1902 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1903 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1904 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1905 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1906 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1907 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1908 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1909 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1910 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1911 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1912 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1913 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1914 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1915 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1916 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1917
1918 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1919 regs_buff[40] = (u32)phy_data;
1920 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1921 regs_buff[41] = (u32)phy_data;
1922}
1923
1924static int atl2_get_eeprom_len(struct net_device *netdev)
1925{
1926 struct atl2_adapter *adapter = netdev_priv(netdev);
1927
1928 if (!atl2_check_eeprom_exist(&adapter->hw))
1929 return 512;
1930 else
1931 return 0;
1932}
1933
1934static int atl2_get_eeprom(struct net_device *netdev,
1935 struct ethtool_eeprom *eeprom, u8 *bytes)
1936{
1937 struct atl2_adapter *adapter = netdev_priv(netdev);
1938 struct atl2_hw *hw = &adapter->hw;
1939 u32 *eeprom_buff;
1940 int first_dword, last_dword;
1941 int ret_val = 0;
1942 int i;
1943
1944 if (eeprom->len == 0)
1945 return -EINVAL;
1946
1947 if (atl2_check_eeprom_exist(hw))
1948 return -EINVAL;
1949
1950 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1951
1952 first_dword = eeprom->offset >> 2;
1953 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1954
1955 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1956 GFP_KERNEL);
1957 if (!eeprom_buff)
1958 return -ENOMEM;
1959
1960 for (i = first_dword; i < last_dword; i++) {
2467ab95
JS		 1961 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) {
1962 ret_val = -EIO;
1963 goto free;
1964 }
452c1ce2
CS		 1965 }
1966
1967 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1968 eeprom->len);
2467ab95 1969free:
452c1ce2
CS		 1970 kfree(eeprom_buff);
1971
1972 return ret_val;
1973}
1974
1975static int atl2_set_eeprom(struct net_device *netdev,
1976 struct ethtool_eeprom *eeprom, u8 *bytes)
1977{
1978 struct atl2_adapter *adapter = netdev_priv(netdev);
1979 struct atl2_hw *hw = &adapter->hw;
1980 u32 *eeprom_buff;
1981 u32 *ptr;
1982 int max_len, first_dword, last_dword, ret_val = 0;
1983 int i;
1984
1985 if (eeprom->len == 0)
1986 return -EOPNOTSUPP;
1987
1988 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1989 return -EFAULT;
1990
1991 max_len = 512;
1992
1993 first_dword = eeprom->offset >> 2;
1994 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1995 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
1996 if (!eeprom_buff)
1997 return -ENOMEM;
1998
ad19031b 1999 ptr = eeprom_buff;
452c1ce2
CS		 2000
2001 if (eeprom->offset & 3) {
2002 /* need read/modify/write of first changed EEPROM word */
2003 /* only the second byte of the word is being modified */
ad19031b
JJ		 2004 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) {
2005 ret_val = -EIO;
2006 goto out;
2007 }
452c1ce2
CS		 2008 ptr++;
2009 }
2010 if (((eeprom->offset + eeprom->len) & 3)) {
2011 /*
2012 * need read/modify/write of last changed EEPROM word
2013 * only the first byte of the word is being modified
2014 */
2015 if (!atl2_read_eeprom(hw, last_dword * 4,
ad19031b
JJ		 2016 &(eeprom_buff[last_dword - first_dword]))) {
2017 ret_val = -EIO;
2018 goto out;
2019 }
452c1ce2
CS		 2020 }
2021
2022 /* Device's eeprom is always little-endian, word addressable */
2023 memcpy(ptr, bytes, eeprom->len);
2024
2025 for (i = 0; i < last_dword - first_dword + 1; i++) {
ad19031b
JJ		 2026 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) {
2027 ret_val = -EIO;
2028 goto out;
2029 }
452c1ce2 2030 }
ad19031b 2031 out:
452c1ce2
CS		 2032 kfree(eeprom_buff);
2033 return ret_val;
2034}
2035
2036static void atl2_get_drvinfo(struct net_device *netdev,
2037 struct ethtool_drvinfo *drvinfo)
2038{
2039 struct atl2_adapter *adapter = netdev_priv(netdev);
2040
68aad78c
RJ		 2041 strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver));
2042 strlcpy(drvinfo->version, atl2_driver_version,
2043 sizeof(drvinfo->version));
2044 strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version));
2045 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
2046 sizeof(drvinfo->bus_info));
452c1ce2
CS		 2047 drvinfo->n_stats = 0;
2048 drvinfo->testinfo_len = 0;
2049 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2050 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2051}
2052
2053static void atl2_get_wol(struct net_device *netdev,
2054 struct ethtool_wolinfo *wol)
2055{
2056 struct atl2_adapter *adapter = netdev_priv(netdev);
2057
2058 wol->supported = WAKE_MAGIC;
2059 wol->wolopts = 0;
2060
2061 if (adapter->wol & ATLX_WUFC_EX)
2062 wol->wolopts |= WAKE_UCAST;
2063 if (adapter->wol & ATLX_WUFC_MC)
2064 wol->wolopts |= WAKE_MCAST;
2065 if (adapter->wol & ATLX_WUFC_BC)
2066 wol->wolopts |= WAKE_BCAST;
2067 if (adapter->wol & ATLX_WUFC_MAG)
2068 wol->wolopts |= WAKE_MAGIC;
2069 if (adapter->wol & ATLX_WUFC_LNKC)
2070 wol->wolopts |= WAKE_PHY;
2071}
2072
2073static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2074{
2075 struct atl2_adapter *adapter = netdev_priv(netdev);
2076
2077 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2078 return -EOPNOTSUPP;
2079
41796e91 2080 if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
452c1ce2
CS		 2081 return -EOPNOTSUPP;
2082
2083 /* these settings will always override what we currently have */
2084 adapter->wol = 0;
2085
2086 if (wol->wolopts & WAKE_MAGIC)
2087 adapter->wol |= ATLX_WUFC_MAG;
2088 if (wol->wolopts & WAKE_PHY)
2089 adapter->wol |= ATLX_WUFC_LNKC;
2090
2091 return 0;
2092}
2093
2094static int atl2_nway_reset(struct net_device *netdev)
2095{
2096 struct atl2_adapter *adapter = netdev_priv(netdev);
2097 if (netif_running(netdev))
2098 atl2_reinit_locked(adapter);
2099 return 0;
2100}
2101
0fc0b732 2102static const struct ethtool_ops atl2_ethtool_ops = {
452c1ce2
CS		 2103 .get_settings = atl2_get_settings,
2104 .set_settings = atl2_set_settings,
2105 .get_drvinfo = atl2_get_drvinfo,
2106 .get_regs_len = atl2_get_regs_len,
2107 .get_regs = atl2_get_regs,
2108 .get_wol = atl2_get_wol,
2109 .set_wol = atl2_set_wol,
2110 .get_msglevel = atl2_get_msglevel,
2111 .set_msglevel = atl2_set_msglevel,
2112 .nway_reset = atl2_nway_reset,
2113 .get_link = ethtool_op_get_link,
2114 .get_eeprom_len = atl2_get_eeprom_len,
2115 .get_eeprom = atl2_get_eeprom,
2116 .set_eeprom = atl2_set_eeprom,
452c1ce2
CS		 2117};
2118
2119static void atl2_set_ethtool_ops(struct net_device *netdev)
2120{
2121 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2122}
2123
2124#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2125 (((a) & 0xff00ff00) >> 8))
2126#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2127#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2128
2129/*
2130 * Reset the transmit and receive units; mask and clear all interrupts.
2131 *
2132 * hw - Struct containing variables accessed by shared code
2133 * return : 0 or idle status (if error)
2134 */
2135static s32 atl2_reset_hw(struct atl2_hw *hw)
2136{
2137 u32 icr;
2138 u16 pci_cfg_cmd_word;
2139 int i;
2140
2141 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2142 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2143 if ((pci_cfg_cmd_word &
2144 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2145 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2146 pci_cfg_cmd_word |=
2147 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2148 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2149 }
2150
2151 /* Clear Interrupt mask to stop board from generating
2152 * interrupts & Clear any pending interrupt events
2153 */
2154 /* FIXME */
2155 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2156 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2157
2158 /* Issue Soft Reset to the MAC. This will reset the chip's
2159 * transmit, receive, DMA. It will not effect
2160 * the current PCI configuration. The global reset bit is self-
2161 * clearing, and should clear within a microsecond.
2162 */
2163 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2164 wmb();
2165 msleep(1); /* delay about 1ms */
2166
2167 /* Wait at least 10ms for All module to be Idle */
2168 for (i = 0; i < 10; i++) {
2169 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2170 if (!icr)
2171 break;
2172 msleep(1); /* delay 1 ms */
2173 cpu_relax();
2174 }
2175
2176 if (icr)
2177 return icr;
2178
2179 return 0;
2180}
2181
2182#define CUSTOM_SPI_CS_SETUP 2
2183#define CUSTOM_SPI_CLK_HI 2
2184#define CUSTOM_SPI_CLK_LO 2
2185#define CUSTOM_SPI_CS_HOLD 2
2186#define CUSTOM_SPI_CS_HI 3
2187
2188static struct atl2_spi_flash_dev flash_table[] =
2189{
2190/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2191{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2192{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2193{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2194};
2195
2196static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2197{
2198 int i;
2199 u32 value;
2200
2201 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2202 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2203
2204 value = SPI_FLASH_CTRL_WAIT_READY |
2205 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2206 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2207 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2208 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2209 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2210 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2211 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2212 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2213 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2214 SPI_FLASH_CTRL_CS_HI_SHIFT |
2215 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2216
2217 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2218
2219 value |= SPI_FLASH_CTRL_START;
2220
2221 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2222
2223 for (i = 0; i < 10; i++) {
2224 msleep(1);
2225 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2226 if (!(value & SPI_FLASH_CTRL_START))
2227 break;
2228 }
2229
2230 if (value & SPI_FLASH_CTRL_START)
2231 return false;
2232
2233 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2234
2235 return true;
2236}
2237
2238/*
2239 * get_permanent_address
2240 * return 0 if get valid mac address,
2241 */
2242static int get_permanent_address(struct atl2_hw *hw)
2243{
2244 u32 Addr[2];
2245 u32 i, Control;
2246 u16 Register;
c81f2124 2247 u8 EthAddr[ETH_ALEN];
452c1ce2
CS		 2248 bool KeyValid;
2249
2250 if (is_valid_ether_addr(hw->perm_mac_addr))
2251 return 0;
2252
2253 Addr[0] = 0;
2254 Addr[1] = 0;
2255
2256 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2257 Register = 0;
2258 KeyValid = false;
2259
2260 /* Read out all EEPROM content */
2261 i = 0;
2262 while (1) {
2263 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2264 if (KeyValid) {
2265 if (Register == REG_MAC_STA_ADDR)
2266 Addr[0] = Control;
2267 else if (Register ==
2268 (REG_MAC_STA_ADDR + 4))
2269 Addr[1] = Control;
2270 KeyValid = false;
2271 } else if ((Control & 0xff) == 0x5A) {
2272 KeyValid = true;
2273 Register = (u16) (Control >> 16);
2274 } else {
2275 /* assume data end while encount an invalid KEYWORD */
2276 break;
2277 }
2278 } else {
2279 break; /* read error */
2280 }
2281 i += 4;
2282 }
2283
2284 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2285 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2286
2287 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2288 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2289 return 0;
2290 }
2291 return 1;
2292 }
2293
2294 /* see if SPI flash exists? */
2295 Addr[0] = 0;
2296 Addr[1] = 0;
2297 Register = 0;
2298 KeyValid = false;
2299 i = 0;
2300 while (1) {
2301 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2302 if (KeyValid) {
2303 if (Register == REG_MAC_STA_ADDR)
2304 Addr[0] = Control;
2305 else if (Register == (REG_MAC_STA_ADDR + 4))
2306 Addr[1] = Control;
2307 KeyValid = false;
2308 } else if ((Control & 0xff) == 0x5A) {
2309 KeyValid = true;
2310 Register = (u16) (Control >> 16);
2311 } else {
2312 break; /* data end */
2313 }
2314 } else {
2315 break; /* read error */
2316 }
2317 i += 4;
2318 }
2319
2320 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2321 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2322 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2323 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2324 return 0;
2325 }
2326 /* maybe MAC-address is from BIOS */
2327 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2328 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2329 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2330 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2331
2332 if (is_valid_ether_addr(EthAddr)) {
c81f2124 2333 memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN);
452c1ce2
CS		 2334 return 0;
2335 }
2336
2337 return 1;
2338}
2339
2340/*
2341 * Reads the adapter's MAC address from the EEPROM
2342 *
2343 * hw - Struct containing variables accessed by shared code
2344 */
2345static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2346{
452c1ce2
CS		 2347 if (get_permanent_address(hw)) {
2348 /* for test */
7efd26d0 2349 /* FIXME: shouldn't we use eth_random_addr() here? */
452c1ce2
CS		 2350 hw->perm_mac_addr[0] = 0x00;
2351 hw->perm_mac_addr[1] = 0x13;
2352 hw->perm_mac_addr[2] = 0x74;
2353 hw->perm_mac_addr[3] = 0x00;
2354 hw->perm_mac_addr[4] = 0x5c;
2355 hw->perm_mac_addr[5] = 0x38;
2356 }
2357
c81f2124 2358 memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN);
452c1ce2
CS		 2359
2360 return 0;
2361}
2362
2363/*
2364 * Hashes an address to determine its location in the multicast table
2365 *
2366 * hw - Struct containing variables accessed by shared code
2367 * mc_addr - the multicast address to hash
2368 *
2369 * atl2_hash_mc_addr
2370 * purpose
2371 * set hash value for a multicast address
2372 * hash calcu processing :
2373 * 1. calcu 32bit CRC for multicast address
2374 * 2. reverse crc with MSB to LSB
2375 */
2376static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2377{
2378 u32 crc32, value;
2379 int i;
2380
2381 value = 0;
2382 crc32 = ether_crc_le(6, mc_addr);
2383
2384 for (i = 0; i < 32; i++)
2385 value |= (((crc32 >> i) & 1) << (31 - i));
2386
2387 return value;
2388}
2389
2390/*
2391 * Sets the bit in the multicast table corresponding to the hash value.
2392 *
2393 * hw - Struct containing variables accessed by shared code
2394 * hash_value - Multicast address hash value
2395 */
2396static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2397{
2398 u32 hash_bit, hash_reg;
2399 u32 mta;
2400
2401 /* The HASH Table is a register array of 2 32-bit registers.
2402 * It is treated like an array of 64 bits. We want to set
2403 * bit BitArray[hash_value]. So we figure out what register
2404 * the bit is in, read it, OR in the new bit, then write
2405 * back the new value. The register is determined by the
2406 * upper 7 bits of the hash value and the bit within that
2407 * register are determined by the lower 5 bits of the value.
2408 */
2409 hash_reg = (hash_value >> 31) & 0x1;
2410 hash_bit = (hash_value >> 26) & 0x1F;
2411
2412 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2413
2414 mta |= (1 << hash_bit);
2415
2416 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2417}
2418
2419/*
2420 * atl2_init_pcie - init PCIE module
2421 */
2422static void atl2_init_pcie(struct atl2_hw *hw)
2423{
2424 u32 value;
2425 value = LTSSM_TEST_MODE_DEF;
2426 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2427
2428 value = PCIE_DLL_TX_CTRL1_DEF;
2429 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2430}
2431
2432static void atl2_init_flash_opcode(struct atl2_hw *hw)
2433{
2434 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2435 hw->flash_vendor = 0; /* ATMEL */
2436
2437 /* Init OP table */
2438 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2439 flash_table[hw->flash_vendor].cmdPROGRAM);
2440 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2441 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2442 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2443 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2444 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2445 flash_table[hw->flash_vendor].cmdRDID);
2446 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2447 flash_table[hw->flash_vendor].cmdWREN);
2448 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2449 flash_table[hw->flash_vendor].cmdRDSR);
2450 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2451 flash_table[hw->flash_vendor].cmdWRSR);
2452 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2453 flash_table[hw->flash_vendor].cmdREAD);
2454}
2455
2456/********************************************************************
2457* Performs basic configuration of the adapter.
2458*
2459* hw - Struct containing variables accessed by shared code
2460* Assumes that the controller has previously been reset and is in a
2461* post-reset uninitialized state. Initializes multicast table,
2462* and Calls routines to setup link
2463* Leaves the transmit and receive units disabled and uninitialized.
2464********************************************************************/
2465static s32 atl2_init_hw(struct atl2_hw *hw)
2466{
2467 u32 ret_val = 0;
2468
2469 atl2_init_pcie(hw);
2470
2471 /* Zero out the Multicast HASH table */
2472 /* clear the old settings from the multicast hash table */
2473 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2474 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2475
2476 atl2_init_flash_opcode(hw);
2477
2478 ret_val = atl2_phy_init(hw);
2479
2480 return ret_val;
2481}
2482
2483/*
2484 * Detects the current speed and duplex settings of the hardware.
2485 *
2486 * hw - Struct containing variables accessed by shared code
2487 * speed - Speed of the connection
2488 * duplex - Duplex setting of the connection
2489 */
2490static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2491 u16 *duplex)
2492{
2493 s32 ret_val;
2494 u16 phy_data;
2495
2496 /* Read PHY Specific Status Register (17) */
2497 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2498 if (ret_val)
2499 return ret_val;
2500
2501 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2502 return ATLX_ERR_PHY_RES;
2503
2504 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2505 case MII_ATLX_PSSR_100MBS:
2506 *speed = SPEED_100;
2507 break;
2508 case MII_ATLX_PSSR_10MBS:
2509 *speed = SPEED_10;
2510 break;
2511 default:
2512 return ATLX_ERR_PHY_SPEED;
2513 break;
2514 }
2515
2516 if (phy_data & MII_ATLX_PSSR_DPLX)
2517 *duplex = FULL_DUPLEX;
2518 else
2519 *duplex = HALF_DUPLEX;
2520
2521 return 0;
2522}
2523
2524/*
2525 * Reads the value from a PHY register
2526 * hw - Struct containing variables accessed by shared code
2527 * reg_addr - address of the PHY register to read
2528 */
2529static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2530{
2531 u32 val;
2532 int i;
2533
2534 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2535 MDIO_START |
2536 MDIO_SUP_PREAMBLE |
2537 MDIO_RW |
2538 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2539 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2540
2541 wmb();
2542
2543 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2544 udelay(2);
2545 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2546 if (!(val & (MDIO_START | MDIO_BUSY)))
2547 break;
2548 wmb();
2549 }
2550 if (!(val & (MDIO_START | MDIO_BUSY))) {
2551 *phy_data = (u16)val;
2552 return 0;
2553 }
2554
2555 return ATLX_ERR_PHY;
2556}
2557
2558/*
2559 * Writes a value to a PHY register
2560 * hw - Struct containing variables accessed by shared code
2561 * reg_addr - address of the PHY register to write
2562 * data - data to write to the PHY
2563 */
2564static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2565{
2566 int i;
2567 u32 val;
2568
2569 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2570 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2571 MDIO_SUP_PREAMBLE |
2572 MDIO_START |
2573 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2574 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2575
2576 wmb();
2577
2578 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2579 udelay(2);
2580 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2581 if (!(val & (MDIO_START | MDIO_BUSY)))
2582 break;
2583
2584 wmb();
2585 }
2586
2587 if (!(val & (MDIO_START | MDIO_BUSY)))
2588 return 0;
2589
2590 return ATLX_ERR_PHY;
2591}
2592
2593/*
2594 * Configures PHY autoneg and flow control advertisement settings
2595 *
2596 * hw - Struct containing variables accessed by shared code
2597 */
2598static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2599{
2600 s32 ret_val;
2601 s16 mii_autoneg_adv_reg;
2602
2603 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2604 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2605
2606 /* Need to parse autoneg_advertised and set up
2607 * the appropriate PHY registers. First we will parse for
2608 * autoneg_advertised software override. Since we can advertise
2609 * a plethora of combinations, we need to check each bit
2610 * individually.
2611 */
2612
2613 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2614 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2615 * the 1000Base-T Control Register (Address 9). */
2616 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2617
2618 /* Need to parse MediaType and setup the
2619 * appropriate PHY registers. */
2620 switch (hw->MediaType) {
2621 case MEDIA_TYPE_AUTO_SENSOR:
2622 mii_autoneg_adv_reg |=
2623 (MII_AR_10T_HD_CAPS |
2624 MII_AR_10T_FD_CAPS |
2625 MII_AR_100TX_HD_CAPS|
2626 MII_AR_100TX_FD_CAPS);
2627 hw->autoneg_advertised =
2628 ADVERTISE_10_HALF |
2629 ADVERTISE_10_FULL |
2630 ADVERTISE_100_HALF|
2631 ADVERTISE_100_FULL;
2632 break;
2633 case MEDIA_TYPE_100M_FULL:
2634 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2635 hw->autoneg_advertised = ADVERTISE_100_FULL;
2636 break;
2637 case MEDIA_TYPE_100M_HALF:
2638 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2639 hw->autoneg_advertised = ADVERTISE_100_HALF;
2640 break;
2641 case MEDIA_TYPE_10M_FULL:
2642 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2643 hw->autoneg_advertised = ADVERTISE_10_FULL;
2644 break;
2645 default:
2646 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2647 hw->autoneg_advertised = ADVERTISE_10_HALF;
2648 break;
2649 }
2650
2651 /* flow control fixed to enable all */
2652 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2653
2654 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2655
2656 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2657
2658 if (ret_val)
2659 return ret_val;
2660
2661 return 0;
2662}
2663
2664/*
2665 * Resets the PHY and make all config validate
2666 *
2667 * hw - Struct containing variables accessed by shared code
2668 *
2669 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2670 */
2671static s32 atl2_phy_commit(struct atl2_hw *hw)
2672{
2673 s32 ret_val;
2674 u16 phy_data;
2675
2676 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2677 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2678 if (ret_val) {
2679 u32 val;
2680 int i;
2681 /* pcie serdes link may be down ! */
2682 for (i = 0; i < 25; i++) {
2683 msleep(1);
2684 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2685 if (!(val & (MDIO_START | MDIO_BUSY)))
2686 break;
2687 }
2688
2689 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2690 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2691 return ret_val;
2692 }
2693 }
2694 return 0;
2695}
2696
2697static s32 atl2_phy_init(struct atl2_hw *hw)
2698{
2699 s32 ret_val;
2700 u16 phy_val;
2701
2702 if (hw->phy_configured)
2703 return 0;
2704
2705 /* Enable PHY */
2706 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2707 ATL2_WRITE_FLUSH(hw);
2708 msleep(1);
2709
2710 /* check if the PHY is in powersaving mode */
2711 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2712 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2713
2714 /* 024E / 124E 0r 0274 / 1274 ? */
2715 if (phy_val & 0x1000) {
2716 phy_val &= ~0x1000;
2717 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2718 }
2719
2720 msleep(1);
2721
2722 /*Enable PHY LinkChange Interrupt */
2723 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2724 if (ret_val)
2725 return ret_val;
2726
2727 /* setup AutoNeg parameters */
2728 ret_val = atl2_phy_setup_autoneg_adv(hw);
2729 if (ret_val)
2730 return ret_val;
2731
2732 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2733 ret_val = atl2_phy_commit(hw);
2734 if (ret_val)
2735 return ret_val;
2736
2737 hw->phy_configured = true;
2738
2739 return ret_val;
2740}
2741
2742static void atl2_set_mac_addr(struct atl2_hw *hw)
2743{
2744 u32 value;
2745 /* 00-0B-6A-F6-00-DC
2746 * 0: 6AF600DC 1: 000B
2747 * low dword */
2748 value = (((u32)hw->mac_addr[2]) << 24) |
2749 (((u32)hw->mac_addr[3]) << 16) |
2750 (((u32)hw->mac_addr[4]) << 8) |
2751 (((u32)hw->mac_addr[5]));
2752 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2753 /* hight dword */
2754 value = (((u32)hw->mac_addr[0]) << 8) |
2755 (((u32)hw->mac_addr[1]));
2756 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2757}
2758
2759/*
2760 * check_eeprom_exist
2761 * return 0 if eeprom exist
2762 */
2763static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2764{
2765 u32 value;
2766
2767 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2768 if (value & SPI_FLASH_CTRL_EN_VPD) {
2769 value &= ~SPI_FLASH_CTRL_EN_VPD;
2770 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2771 }
2772 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2773 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2774}
2775
2776/* FIXME: This doesn't look right. -- CHS */
2777static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2778{
2779 return true;
2780}
2781
2782static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2783{
2784 int i;
2785 u32 Control;
2786
2787 if (Offset & 0x3)
2788 return false; /* address do not align */
2789
2790 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2791 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2792 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2793
2794 for (i = 0; i < 10; i++) {
2795 msleep(2);
2796 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2797 if (Control & VPD_CAP_VPD_FLAG)
2798 break;
2799 }
2800
2801 if (Control & VPD_CAP_VPD_FLAG) {
2802 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2803 return true;
2804 }
2805 return false; /* timeout */
2806}
2807
2808static void atl2_force_ps(struct atl2_hw *hw)
2809{
2810 u16 phy_val;
2811
2812 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2813 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2814 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2815
2816 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2817 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2818 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2819 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2820}
2821
2822/* This is the only thing that needs to be changed to adjust the
2823 * maximum number of ports that the driver can manage.
2824 */
2825#define ATL2_MAX_NIC 4
2826
2827#define OPTION_UNSET -1
2828#define OPTION_DISABLED 0
2829#define OPTION_ENABLED 1
2830
2831/* All parameters are treated the same, as an integer array of values.
2832 * This macro just reduces the need to repeat the same declaration code
2833 * over and over (plus this helps to avoid typo bugs).
2834 */
2835#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2836#ifndef module_param_array
2837/* Module Parameters are always initialized to -1, so that the driver
2838 * can tell the difference between no user specified value or the
2839 * user asking for the default value.
2840 * The true default values are loaded in when atl2_check_options is called.
2841 *
2842 * This is a GCC extension to ANSI C.
2843 * See the item "Labeled Elements in Initializers" in the section
2844 * "Extensions to the C Language Family" of the GCC documentation.
2845 */
2846
2847#define ATL2_PARAM(X, desc) \
c477ebd8 2848 static const int __devinitconst X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
452c1ce2
CS		 2849 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2850 MODULE_PARM_DESC(X, desc);
2851#else
2852#define ATL2_PARAM(X, desc) \
2853 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
b79d8fff 2854 static unsigned int num_##X; \
452c1ce2
CS		 2855 module_param_array_named(X, X, int, &num_##X, 0); \
2856 MODULE_PARM_DESC(X, desc);
2857#endif
2858
2859/*
2860 * Transmit Memory Size
2861 * Valid Range: 64-2048
2862 * Default Value: 128
2863 */
2864#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2865#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2866#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2867ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2868
2869/*
2870 * Receive Memory Block Count
2871 * Valid Range: 16-512
2872 * Default Value: 128
2873 */
2874#define ATL2_MIN_RXD_COUNT 16
2875#define ATL2_MAX_RXD_COUNT 512
2876#define ATL2_DEFAULT_RXD_COUNT 64
2877ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2878
2879/*
2880 * User Specified MediaType Override
2881 *
2882 * Valid Range: 0-5
2883 * - 0 - auto-negotiate at all supported speeds
2884 * - 1 - only link at 1000Mbps Full Duplex
2885 * - 2 - only link at 100Mbps Full Duplex
2886 * - 3 - only link at 100Mbps Half Duplex
2887 * - 4 - only link at 10Mbps Full Duplex
2888 * - 5 - only link at 10Mbps Half Duplex
2889 * Default Value: 0
2890 */
2891ATL2_PARAM(MediaType, "MediaType Select");
2892
2893/*
2894 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2895 * Valid Range: 10-65535
2896 * Default Value: 45000(90ms)
2897 */
2898#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2899#define INT_MOD_MAX_CNT 65000
2900#define INT_MOD_MIN_CNT 50
2901ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2902
2903/*
2904 * FlashVendor
2905 * Valid Range: 0-2
2906 * 0 - Atmel
2907 * 1 - SST
2908 * 2 - ST
2909 */
2910ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2911
2912#define AUTONEG_ADV_DEFAULT 0x2F
2913#define AUTONEG_ADV_MASK 0x2F
2914#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2915
2916#define FLASH_VENDOR_DEFAULT 0
2917#define FLASH_VENDOR_MIN 0
2918#define FLASH_VENDOR_MAX 2
2919
2920struct atl2_option {
2921 enum { enable_option, range_option, list_option } type;
2922 char *name;
2923 char *err;
2924 int def;
2925 union {
2926 struct { /* range_option info */
2927 int min;
2928 int max;
2929 } r;
2930 struct { /* list_option info */
2931 int nr;
2932 struct atl2_opt_list { int i; char *str; } *p;
2933 } l;
2934 } arg;
2935};
2936
2937static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2938{
2939 int i;
2940 struct atl2_opt_list *ent;
2941
2942 if (*value == OPTION_UNSET) {
2943 *value = opt->def;
2944 return 0;
2945 }
2946
2947 switch (opt->type) {
2948 case enable_option:
2949 switch (*value) {
2950 case OPTION_ENABLED:
2951 printk(KERN_INFO "%s Enabled\n", opt->name);
2952 return 0;
2953 break;
2954 case OPTION_DISABLED:
2955 printk(KERN_INFO "%s Disabled\n", opt->name);
2956 return 0;
2957 break;
2958 }
2959 break;
2960 case range_option:
2961 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2962 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2963 return 0;
2964 }
2965 break;
2966 case list_option:
2967 for (i = 0; i < opt->arg.l.nr; i++) {
2968 ent = &opt->arg.l.p[i];
2969 if (*value == ent->i) {
2970 if (ent->str[0] != '\0')
2971 printk(KERN_INFO "%s\n", ent->str);
2972 return 0;
2973 }
2974 }
2975 break;
2976 default:
2977 BUG();
2978 }
2979
2980 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
2981 opt->name, *value, opt->err);
2982 *value = opt->def;
2983 return -1;
2984}
2985
49ce9c2c 2986/**
452c1ce2
CS		 2987 * atl2_check_options - Range Checking for Command Line Parameters
2988 * @adapter: board private structure
2989 *
2990 * This routine checks all command line parameters for valid user
2991 * input. If an invalid value is given, or if no user specified
2992 * value exists, a default value is used. The final value is stored
2993 * in a variable in the adapter structure.
2994 */
2995static void __devinit atl2_check_options(struct atl2_adapter *adapter)
2996{
2997 int val;
2998 struct atl2_option opt;
2999 int bd = adapter->bd_number;
3000 if (bd >= ATL2_MAX_NIC) {
3001 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3002 bd);
3003 printk(KERN_NOTICE "Using defaults for all values\n");
3004#ifndef module_param_array
3005 bd = ATL2_MAX_NIC;
3006#endif
3007 }
3008
3009 /* Bytes of Transmit Memory */
3010 opt.type = range_option;
3011 opt.name = "Bytes of Transmit Memory";
3012 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3013 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3014 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3015 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3016#ifdef module_param_array
3017 if (num_TxMemSize > bd) {
3018#endif
3019 val = TxMemSize[bd];
3020 atl2_validate_option(&val, &opt);
3021 adapter->txd_ring_size = ((u32) val) * 1024;
3022#ifdef module_param_array
3023 } else
3024 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3025#endif
3026 /* txs ring size: */
3027 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3028 if (adapter->txs_ring_size > 160)
3029 adapter->txs_ring_size = 160;
3030
3031 /* Receive Memory Block Count */
3032 opt.type = range_option;
3033 opt.name = "Number of receive memory block";
3034 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3035 opt.def = ATL2_DEFAULT_RXD_COUNT;
3036 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3037 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3038#ifdef module_param_array
3039 if (num_RxMemBlock > bd) {
3040#endif
3041 val = RxMemBlock[bd];
3042 atl2_validate_option(&val, &opt);
3043 adapter->rxd_ring_size = (u32)val;
3044 /* FIXME */
3045 /* ((u16)val)&~1; */ /* even number */
3046#ifdef module_param_array
3047 } else
3048 adapter->rxd_ring_size = (u32)opt.def;
3049#endif
3050 /* init RXD Flow control value */
3051 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3052 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3053 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3054 (adapter->rxd_ring_size / 12);
3055
3056 /* Interrupt Moderate Timer */
3057 opt.type = range_option;
3058 opt.name = "Interrupt Moderate Timer";
3059 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3060 opt.def = INT_MOD_DEFAULT_CNT;
3061 opt.arg.r.min = INT_MOD_MIN_CNT;
3062 opt.arg.r.max = INT_MOD_MAX_CNT;
3063#ifdef module_param_array
3064 if (num_IntModTimer > bd) {
3065#endif
3066 val = IntModTimer[bd];
3067 atl2_validate_option(&val, &opt);
3068 adapter->imt = (u16) val;
3069#ifdef module_param_array
3070 } else
3071 adapter->imt = (u16)(opt.def);
3072#endif
3073 /* Flash Vendor */
3074 opt.type = range_option;
3075 opt.name = "SPI Flash Vendor";
3076 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3077 opt.def = FLASH_VENDOR_DEFAULT;
3078 opt.arg.r.min = FLASH_VENDOR_MIN;
3079 opt.arg.r.max = FLASH_VENDOR_MAX;
3080#ifdef module_param_array
3081 if (num_FlashVendor > bd) {
3082#endif
3083 val = FlashVendor[bd];
3084 atl2_validate_option(&val, &opt);
3085 adapter->hw.flash_vendor = (u8) val;
3086#ifdef module_param_array
3087 } else
3088 adapter->hw.flash_vendor = (u8)(opt.def);
3089#endif
3090 /* MediaType */
3091 opt.type = range_option;
3092 opt.name = "Speed/Duplex Selection";
3093 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3094 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3095 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3096 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3097#ifdef module_param_array
3098 if (num_MediaType > bd) {
3099#endif
3100 val = MediaType[bd];
3101 atl2_validate_option(&val, &opt);
3102 adapter->hw.MediaType = (u16) val;
3103#ifdef module_param_array
3104 } else
3105 adapter->hw.MediaType = (u16)(opt.def);
3106#endif
3107}
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