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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.c
CommitLineData
9b1fc55a
MB		 1/*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/init.h>
539d3ee6 21#include <linux/interrupt.h>
9b1fc55a
MB		 22#include <linux/module.h>
23#include <linux/clk.h>
24#include <linux/etherdevice.h>
5a0e3ad6 25#include <linux/slab.h>
9b1fc55a
MB		 26#include <linux/delay.h>
27#include <linux/ethtool.h>
28#include <linux/crc32.h>
29#include <linux/err.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/if_vlan.h>
33
34#include <bcm63xx_dev_enet.h>
35#include "bcm63xx_enet.h"
36
37static char bcm_enet_driver_name[] = "bcm63xx_enet";
38static char bcm_enet_driver_version[] = "1.0";
39
40static int copybreak __read_mostly = 128;
41module_param(copybreak, int, 0);
42MODULE_PARM_DESC(copybreak, "Receive copy threshold");
43
0ae99b5f
MB		 44/* io registers memory shared between all devices */
45static void __iomem *bcm_enet_shared_base[3];
9b1fc55a
MB		 46
47/*
48 * io helpers to access mac registers
49 */
50static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
51{
52 return bcm_readl(priv->base + off);
53}
54
55static inline void enet_writel(struct bcm_enet_priv *priv,
56 u32 val, u32 off)
57{
58 bcm_writel(val, priv->base + off);
59}
60
61/*
6f00a022 62 * io helpers to access switch registers
9b1fc55a 63 */
6f00a022
MB		 64static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
65{
66 return bcm_readl(priv->base + off);
67}
68
69static inline void enetsw_writel(struct bcm_enet_priv *priv,
70 u32 val, u32 off)
71{
72 bcm_writel(val, priv->base + off);
73}
74
75static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
76{
77 return bcm_readw(priv->base + off);
78}
79
80static inline void enetsw_writew(struct bcm_enet_priv *priv,
81 u16 val, u32 off)
82{
83 bcm_writew(val, priv->base + off);
84}
85
86static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
87{
88 return bcm_readb(priv->base + off);
89}
90
91static inline void enetsw_writeb(struct bcm_enet_priv *priv,
92 u8 val, u32 off)
93{
94 bcm_writeb(val, priv->base + off);
95}
96
97
98/* io helpers to access shared registers */
9b1fc55a
MB		 99static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
100{
0ae99b5f 101 return bcm_readl(bcm_enet_shared_base[0] + off);
9b1fc55a
MB		 102}
103
104static inline void enet_dma_writel(struct bcm_enet_priv *priv,
105 u32 val, u32 off)
106{
0ae99b5f
MB		 107 bcm_writel(val, bcm_enet_shared_base[0] + off);
108}
109
3dc6475c 110static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 111{
3dc6475c
FF		 112 return bcm_readl(bcm_enet_shared_base[1] +
113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 114}
115
116static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
3dc6475c 117 u32 val, u32 off, int chan)
0ae99b5f 118{
3dc6475c
FF		 119 bcm_writel(val, bcm_enet_shared_base[1] +
120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 121}
122
3dc6475c 123static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 124{
3dc6475c 125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
0ae99b5f
MB		 126}
127
128static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
3dc6475c 129 u32 val, u32 off, int chan)
0ae99b5f 130{
3dc6475c 131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
9b1fc55a
MB		 132}
133
134/*
135 * write given data into mii register and wait for transfer to end
136 * with timeout (average measured transfer time is 25us)
137 */
138static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
139{
140 int limit;
141
142 /* make sure mii interrupt status is cleared */
143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
144
145 enet_writel(priv, data, ENET_MIIDATA_REG);
146 wmb();
147
148 /* busy wait on mii interrupt bit, with timeout */
149 limit = 1000;
150 do {
151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
152 break;
153 udelay(1);
ec1652af 154 } while (limit-- > 0);
9b1fc55a
MB		 155
156 return (limit < 0) ? 1 : 0;
157}
158
159/*
160 * MII internal read callback
161 */
162static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
163 int regnum)
164{
165 u32 tmp, val;
166
167 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
170 tmp |= ENET_MIIDATA_OP_READ_MASK;
171
172 if (do_mdio_op(priv, tmp))
173 return -1;
174
175 val = enet_readl(priv, ENET_MIIDATA_REG);
176 val &= 0xffff;
177 return val;
178}
179
180/*
181 * MII internal write callback
182 */
183static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
184 int regnum, u16 value)
185{
186 u32 tmp;
187
188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
192 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
193
194 (void)do_mdio_op(priv, tmp);
195 return 0;
196}
197
198/*
199 * MII read callback from phylib
200 */
201static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
202 int regnum)
203{
204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
205}
206
207/*
208 * MII write callback from phylib
209 */
210static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
211 int regnum, u16 value)
212{
213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
214}
215
216/*
217 * MII read callback from mii core
218 */
219static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
220 int regnum)
221{
222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
223}
224
225/*
226 * MII write callback from mii core
227 */
228static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
229 int regnum, int value)
230{
231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
232}
233
234/*
235 * refill rx queue
236 */
237static int bcm_enet_refill_rx(struct net_device *dev)
238{
239 struct bcm_enet_priv *priv;
240
241 priv = netdev_priv(dev);
242
243 while (priv->rx_desc_count < priv->rx_ring_size) {
244 struct bcm_enet_desc *desc;
245 struct sk_buff *skb;
246 dma_addr_t p;
247 int desc_idx;
248 u32 len_stat;
249
250 desc_idx = priv->rx_dirty_desc;
251 desc = &priv->rx_desc_cpu[desc_idx];
252
253 if (!priv->rx_skb[desc_idx]) {
254 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
255 if (!skb)
256 break;
257 priv->rx_skb[desc_idx] = skb;
9b1fc55a
MB		 258 p = dma_map_single(&priv->pdev->dev, skb->data,
259 priv->rx_skb_size,
260 DMA_FROM_DEVICE);
261 desc->address = p;
262 }
263
264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
265 len_stat |= DMADESC_OWNER_MASK;
266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
3dc6475c 267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 268 priv->rx_dirty_desc = 0;
269 } else {
270 priv->rx_dirty_desc++;
271 }
272 wmb();
273 desc->len_stat = len_stat;
274
275 priv->rx_desc_count++;
276
277 /* tell dma engine we allocated one buffer */
3dc6475c
FF		 278 if (priv->dma_has_sram)
279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
280 else
281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 282 }
283
284 /* If rx ring is still empty, set a timer to try allocating
285 * again at a later time. */
286 if (priv->rx_desc_count == 0 && netif_running(dev)) {
287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
288 priv->rx_timeout.expires = jiffies + HZ;
289 add_timer(&priv->rx_timeout);
290 }
291
292 return 0;
293}
294
295/*
296 * timer callback to defer refill rx queue in case we're OOM
297 */
298static void bcm_enet_refill_rx_timer(unsigned long data)
299{
300 struct net_device *dev;
301 struct bcm_enet_priv *priv;
302
303 dev = (struct net_device *)data;
304 priv = netdev_priv(dev);
305
306 spin_lock(&priv->rx_lock);
307 bcm_enet_refill_rx((struct net_device *)data);
308 spin_unlock(&priv->rx_lock);
309}
310
311/*
312 * extract packet from rx queue
313 */
314static int bcm_enet_receive_queue(struct net_device *dev, int budget)
315{
316 struct bcm_enet_priv *priv;
317 struct device *kdev;
318 int processed;
319
320 priv = netdev_priv(dev);
321 kdev = &priv->pdev->dev;
322 processed = 0;
323
324 /* don't scan ring further than number of refilled
325 * descriptor */
326 if (budget > priv->rx_desc_count)
327 budget = priv->rx_desc_count;
328
329 do {
330 struct bcm_enet_desc *desc;
331 struct sk_buff *skb;
332 int desc_idx;
333 u32 len_stat;
334 unsigned int len;
335
336 desc_idx = priv->rx_curr_desc;
337 desc = &priv->rx_desc_cpu[desc_idx];
338
339 /* make sure we actually read the descriptor status at
340 * each loop */
341 rmb();
342
343 len_stat = desc->len_stat;
344
345 /* break if dma ownership belongs to hw */
346 if (len_stat & DMADESC_OWNER_MASK)
347 break;
348
349 processed++;
350 priv->rx_curr_desc++;
351 if (priv->rx_curr_desc == priv->rx_ring_size)
352 priv->rx_curr_desc = 0;
353 priv->rx_desc_count--;
354
355 /* if the packet does not have start of packet _and_
356 * end of packet flag set, then just recycle it */
3dc6475c
FF		 357 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
358 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
c32d83c0 359 dev->stats.rx_dropped++;
9b1fc55a
MB		 360 continue;
361 }
362
363 /* recycle packet if it's marked as bad */
6f00a022
MB		 364 if (!priv->enet_is_sw &&
365 unlikely(len_stat & DMADESC_ERR_MASK)) {
c32d83c0 366 dev->stats.rx_errors++;
9b1fc55a
MB		 367
368 if (len_stat & DMADESC_OVSIZE_MASK)
c32d83c0 369 dev->stats.rx_length_errors++;
9b1fc55a 370 if (len_stat & DMADESC_CRC_MASK)
c32d83c0 371 dev->stats.rx_crc_errors++;
9b1fc55a 372 if (len_stat & DMADESC_UNDER_MASK)
c32d83c0 373 dev->stats.rx_frame_errors++;
9b1fc55a 374 if (len_stat & DMADESC_OV_MASK)
c32d83c0 375 dev->stats.rx_fifo_errors++;
9b1fc55a
MB		 376 continue;
377 }
378
379 /* valid packet */
380 skb = priv->rx_skb[desc_idx];
381 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
382 /* don't include FCS */
383 len -= 4;
384
385 if (len < copybreak) {
386 struct sk_buff *nskb;
387
45abfb10 388 nskb = napi_alloc_skb(&priv->napi, len);
9b1fc55a
MB		 389 if (!nskb) {
390 /* forget packet, just rearm desc */
c32d83c0 391 dev->stats.rx_dropped++;
9b1fc55a
MB		 392 continue;
393 }
394
9b1fc55a
MB		 395 dma_sync_single_for_cpu(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 memcpy(nskb->data, skb->data, len);
398 dma_sync_single_for_device(kdev, desc->address,
399 len, DMA_FROM_DEVICE);
400 skb = nskb;
401 } else {
402 dma_unmap_single(&priv->pdev->dev, desc->address,
403 priv->rx_skb_size, DMA_FROM_DEVICE);
404 priv->rx_skb[desc_idx] = NULL;
405 }
406
407 skb_put(skb, len);
9b1fc55a 408 skb->protocol = eth_type_trans(skb, dev);
c32d83c0
ED		 409 dev->stats.rx_packets++;
410 dev->stats.rx_bytes += len;
9b1fc55a
MB		 411 netif_receive_skb(skb);
412
413 } while (--budget > 0);
414
415 if (processed || !priv->rx_desc_count) {
416 bcm_enet_refill_rx(dev);
417
418 /* kick rx dma */
3dc6475c
FF		 419 enet_dmac_writel(priv, priv->dma_chan_en_mask,
420 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 421 }
422
423 return processed;
424}
425
426
427/*
428 * try to or force reclaim of transmitted buffers
429 */
430static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
431{
432 struct bcm_enet_priv *priv;
433 int released;
434
435 priv = netdev_priv(dev);
436 released = 0;
437
438 while (priv->tx_desc_count < priv->tx_ring_size) {
439 struct bcm_enet_desc *desc;
440 struct sk_buff *skb;
441
442 /* We run in a bh and fight against start_xmit, which
443 * is called with bh disabled */
444 spin_lock(&priv->tx_lock);
445
446 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
447
448 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
449 spin_unlock(&priv->tx_lock);
450 break;
451 }
452
453 /* ensure other field of the descriptor were not read
454 * before we checked ownership */
455 rmb();
456
457 skb = priv->tx_skb[priv->tx_dirty_desc];
458 priv->tx_skb[priv->tx_dirty_desc] = NULL;
459 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
460 DMA_TO_DEVICE);
461
462 priv->tx_dirty_desc++;
463 if (priv->tx_dirty_desc == priv->tx_ring_size)
464 priv->tx_dirty_desc = 0;
465 priv->tx_desc_count++;
466
467 spin_unlock(&priv->tx_lock);
468
469 if (desc->len_stat & DMADESC_UNDER_MASK)
c32d83c0 470 dev->stats.tx_errors++;
9b1fc55a
MB		 471
472 dev_kfree_skb(skb);
473 released++;
474 }
475
476 if (netif_queue_stopped(dev) && released)
477 netif_wake_queue(dev);
478
479 return released;
480}
481
482/*
483 * poll func, called by network core
484 */
485static int bcm_enet_poll(struct napi_struct *napi, int budget)
486{
487 struct bcm_enet_priv *priv;
488 struct net_device *dev;
cd33ccf5 489 int rx_work_done;
9b1fc55a
MB		 490
491 priv = container_of(napi, struct bcm_enet_priv, napi);
492 dev = priv->net_dev;
493
494 /* ack interrupts */
3dc6475c
FF		 495 enet_dmac_writel(priv, priv->dma_chan_int_mask,
496 ENETDMAC_IR, priv->rx_chan);
497 enet_dmac_writel(priv, priv->dma_chan_int_mask,
498 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 499
500 /* reclaim sent skb */
cd33ccf5 501 bcm_enet_tx_reclaim(dev, 0);
9b1fc55a
MB		 502
503 spin_lock(&priv->rx_lock);
504 rx_work_done = bcm_enet_receive_queue(dev, budget);
505 spin_unlock(&priv->rx_lock);
506
cd33ccf5
NS		 507 if (rx_work_done >= budget) {
508 /* rx queue is not yet empty/clean */
9b1fc55a
MB		 509 return rx_work_done;
510 }
511
512 /* no more packet in rx/tx queue, remove device from poll
513 * queue */
514 napi_complete(napi);
515
516 /* restore rx/tx interrupt */
3dc6475c
FF		 517 enet_dmac_writel(priv, priv->dma_chan_int_mask,
518 ENETDMAC_IRMASK, priv->rx_chan);
519 enet_dmac_writel(priv, priv->dma_chan_int_mask,
520 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 521
522 return rx_work_done;
523}
524
525/*
526 * mac interrupt handler
527 */
528static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
529{
530 struct net_device *dev;
531 struct bcm_enet_priv *priv;
532 u32 stat;
533
534 dev = dev_id;
535 priv = netdev_priv(dev);
536
537 stat = enet_readl(priv, ENET_IR_REG);
538 if (!(stat & ENET_IR_MIB))
539 return IRQ_NONE;
540
541 /* clear & mask interrupt */
542 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
543 enet_writel(priv, 0, ENET_IRMASK_REG);
544
545 /* read mib registers in workqueue */
546 schedule_work(&priv->mib_update_task);
547
548 return IRQ_HANDLED;
549}
550
551/*
552 * rx/tx dma interrupt handler
553 */
554static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
555{
556 struct net_device *dev;
557 struct bcm_enet_priv *priv;
558
559 dev = dev_id;
560 priv = netdev_priv(dev);
561
562 /* mask rx/tx interrupts */
3dc6475c
FF		 563 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 565
566 napi_schedule(&priv->napi);
567
568 return IRQ_HANDLED;
569}
570
571/*
572 * tx request callback
573 */
574static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
575{
576 struct bcm_enet_priv *priv;
577 struct bcm_enet_desc *desc;
578 u32 len_stat;
579 int ret;
580
581 priv = netdev_priv(dev);
582
583 /* lock against tx reclaim */
584 spin_lock(&priv->tx_lock);
585
586 /* make sure the tx hw queue is not full, should not happen
587 * since we stop queue before it's the case */
588 if (unlikely(!priv->tx_desc_count)) {
589 netif_stop_queue(dev);
590 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
591 "available?\n");
592 ret = NETDEV_TX_BUSY;
593 goto out_unlock;
594 }
595
6f00a022
MB		 596 /* pad small packets sent on a switch device */
597 if (priv->enet_is_sw && skb->len < 64) {
598 int needed = 64 - skb->len;
599 char *data;
600
601 if (unlikely(skb_tailroom(skb) < needed)) {
602 struct sk_buff *nskb;
603
604 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
605 if (!nskb) {
606 ret = NETDEV_TX_BUSY;
607 goto out_unlock;
608 }
609 dev_kfree_skb(skb);
610 skb = nskb;
611 }
612 data = skb_put(skb, needed);
613 memset(data, 0, needed);
614 }
615
9b1fc55a
MB		 616 /* point to the next available desc */
617 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
618 priv->tx_skb[priv->tx_curr_desc] = skb;
619
620 /* fill descriptor */
621 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
622 DMA_TO_DEVICE);
623
624 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
3dc6475c 625 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
9b1fc55a
MB		 626 DMADESC_APPEND_CRC |
627 DMADESC_OWNER_MASK;
628
629 priv->tx_curr_desc++;
630 if (priv->tx_curr_desc == priv->tx_ring_size) {
631 priv->tx_curr_desc = 0;
3dc6475c 632 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 633 }
634 priv->tx_desc_count--;
635
636 /* dma might be already polling, make sure we update desc
637 * fields in correct order */
638 wmb();
639 desc->len_stat = len_stat;
640 wmb();
641
642 /* kick tx dma */
3dc6475c
FF		 643 enet_dmac_writel(priv, priv->dma_chan_en_mask,
644 ENETDMAC_CHANCFG, priv->tx_chan);
9b1fc55a
MB		 645
646 /* stop queue if no more desc available */
647 if (!priv->tx_desc_count)
648 netif_stop_queue(dev);
649
c32d83c0
ED		 650 dev->stats.tx_bytes += skb->len;
651 dev->stats.tx_packets++;
9b1fc55a
MB		 652 ret = NETDEV_TX_OK;
653
654out_unlock:
655 spin_unlock(&priv->tx_lock);
656 return ret;
657}
658
659/*
660 * Change the interface's mac address.
661 */
662static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
663{
664 struct bcm_enet_priv *priv;
665 struct sockaddr *addr = p;
666 u32 val;
667
668 priv = netdev_priv(dev);
669 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
670
671 /* use perfect match register 0 to store my mac address */
672 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
673 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
674 enet_writel(priv, val, ENET_PML_REG(0));
675
676 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
677 val |= ENET_PMH_DATAVALID_MASK;
678 enet_writel(priv, val, ENET_PMH_REG(0));
679
680 return 0;
681}
682
683/*
25985edc 684 * Change rx mode (promiscuous/allmulti) and update multicast list
9b1fc55a
MB		 685 */
686static void bcm_enet_set_multicast_list(struct net_device *dev)
687{
688 struct bcm_enet_priv *priv;
22bedad3 689 struct netdev_hw_addr *ha;
9b1fc55a
MB		 690 u32 val;
691 int i;
692
693 priv = netdev_priv(dev);
694
695 val = enet_readl(priv, ENET_RXCFG_REG);
696
697 if (dev->flags & IFF_PROMISC)
698 val |= ENET_RXCFG_PROMISC_MASK;
699 else
700 val &= ~ENET_RXCFG_PROMISC_MASK;
701
702 /* only 3 perfect match registers left, first one is used for
703 * own mac address */
4cd24eaf 704 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
9b1fc55a
MB		 705 val |= ENET_RXCFG_ALLMCAST_MASK;
706 else
707 val &= ~ENET_RXCFG_ALLMCAST_MASK;
708
709 /* no need to set perfect match registers if we catch all
710 * multicast */
711 if (val & ENET_RXCFG_ALLMCAST_MASK) {
712 enet_writel(priv, val, ENET_RXCFG_REG);
713 return;
714 }
715
0ddf477b 716 i = 0;
22bedad3 717 netdev_for_each_mc_addr(ha, dev) {
9b1fc55a
MB		 718 u8 *dmi_addr;
719 u32 tmp;
720
0ddf477b
JP		 721 if (i == 3)
722 break;
9b1fc55a 723 /* update perfect match registers */
22bedad3 724 dmi_addr = ha->addr;
9b1fc55a
MB		 725 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
726 (dmi_addr[4] << 8) | dmi_addr[5];
727 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
728
729 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
730 tmp |= ENET_PMH_DATAVALID_MASK;
0ddf477b 731 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
9b1fc55a
MB		 732 }
733
734 for (; i < 3; i++) {
735 enet_writel(priv, 0, ENET_PML_REG(i + 1));
736 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
737 }
738
739 enet_writel(priv, val, ENET_RXCFG_REG);
740}
741
742/*
743 * set mac duplex parameters
744 */
745static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
746{
747 u32 val;
748
749 val = enet_readl(priv, ENET_TXCTL_REG);
750 if (fullduplex)
751 val |= ENET_TXCTL_FD_MASK;
752 else
753 val &= ~ENET_TXCTL_FD_MASK;
754 enet_writel(priv, val, ENET_TXCTL_REG);
755}
756
757/*
758 * set mac flow control parameters
759 */
760static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
761{
762 u32 val;
763
764 /* rx flow control (pause frame handling) */
765 val = enet_readl(priv, ENET_RXCFG_REG);
766 if (rx_en)
767 val |= ENET_RXCFG_ENFLOW_MASK;
768 else
769 val &= ~ENET_RXCFG_ENFLOW_MASK;
770 enet_writel(priv, val, ENET_RXCFG_REG);
771
3dc6475c
FF		 772 if (!priv->dma_has_sram)
773 return;
774
9b1fc55a
MB		 775 /* tx flow control (pause frame generation) */
776 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
777 if (tx_en)
778 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
779 else
780 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
781 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
782}
783
784/*
785 * link changed callback (from phylib)
786 */
787static void bcm_enet_adjust_phy_link(struct net_device *dev)
788{
789 struct bcm_enet_priv *priv;
790 struct phy_device *phydev;
791 int status_changed;
792
793 priv = netdev_priv(dev);
794 phydev = priv->phydev;
795 status_changed = 0;
796
797 if (priv->old_link != phydev->link) {
798 status_changed = 1;
799 priv->old_link = phydev->link;
800 }
801
802 /* reflect duplex change in mac configuration */
803 if (phydev->link && phydev->duplex != priv->old_duplex) {
804 bcm_enet_set_duplex(priv,
805 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
806 status_changed = 1;
807 priv->old_duplex = phydev->duplex;
808 }
809
810 /* enable flow control if remote advertise it (trust phylib to
811 * check that duplex is full */
812 if (phydev->link && phydev->pause != priv->old_pause) {
813 int rx_pause_en, tx_pause_en;
814
815 if (phydev->pause) {
816 /* pause was advertised by lpa and us */
817 rx_pause_en = 1;
818 tx_pause_en = 1;
819 } else if (!priv->pause_auto) {
820 /* pause setting overrided by user */
821 rx_pause_en = priv->pause_rx;
822 tx_pause_en = priv->pause_tx;
823 } else {
824 rx_pause_en = 0;
825 tx_pause_en = 0;
826 }
827
828 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
829 status_changed = 1;
830 priv->old_pause = phydev->pause;
831 }
832
833 if (status_changed) {
834 pr_info("%s: link %s", dev->name, phydev->link ?
835 "UP" : "DOWN");
836 if (phydev->link)
837 pr_cont(" - %d/%s - flow control %s", phydev->speed,
838 DUPLEX_FULL == phydev->duplex ? "full" : "half",
839 phydev->pause == 1 ? "rx&tx" : "off");
840
841 pr_cont("\n");
842 }
843}
844
845/*
846 * link changed callback (if phylib is not used)
847 */
848static void bcm_enet_adjust_link(struct net_device *dev)
849{
850 struct bcm_enet_priv *priv;
851
852 priv = netdev_priv(dev);
853 bcm_enet_set_duplex(priv, priv->force_duplex_full);
854 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
855 netif_carrier_on(dev);
856
857 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
858 dev->name,
859 priv->force_speed_100 ? 100 : 10,
860 priv->force_duplex_full ? "full" : "half",
861 priv->pause_rx ? "rx" : "off",
862 priv->pause_tx ? "tx" : "off");
863}
864
865/*
866 * open callback, allocate dma rings & buffers and start rx operation
867 */
868static int bcm_enet_open(struct net_device *dev)
869{
870 struct bcm_enet_priv *priv;
871 struct sockaddr addr;
872 struct device *kdev;
873 struct phy_device *phydev;
874 int i, ret;
875 unsigned int size;
876 char phy_id[MII_BUS_ID_SIZE + 3];
877 void *p;
878 u32 val;
879
880 priv = netdev_priv(dev);
881 kdev = &priv->pdev->dev;
882
883 if (priv->has_phy) {
884 /* connect to PHY */
885 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
c56e9e2a 886 priv->mii_bus->id, priv->phy_id);
9b1fc55a 887
f9a8f83b 888 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
9b1fc55a
MB		 889 PHY_INTERFACE_MODE_MII);
890
891 if (IS_ERR(phydev)) {
892 dev_err(kdev, "could not attach to PHY\n");
893 return PTR_ERR(phydev);
894 }
895
896 /* mask with MAC supported features */
897 phydev->supported &= (SUPPORTED_10baseT_Half |
898 SUPPORTED_10baseT_Full |
899 SUPPORTED_100baseT_Half |
900 SUPPORTED_100baseT_Full |
901 SUPPORTED_Autoneg |
902 SUPPORTED_Pause |
903 SUPPORTED_MII);
904 phydev->advertising = phydev->supported;
905
906 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
907 phydev->advertising |= SUPPORTED_Pause;
908 else
909 phydev->advertising &= ~SUPPORTED_Pause;
910
911 dev_info(kdev, "attached PHY at address %d [%s]\n",
912 phydev->addr, phydev->drv->name);
913
914 priv->old_link = 0;
915 priv->old_duplex = -1;
916 priv->old_pause = -1;
917 priv->phydev = phydev;
918 }
919
920 /* mask all interrupts and request them */
921 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 922 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
923 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 924
925 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
926 if (ret)
927 goto out_phy_disconnect;
928
df9f1b9f 929 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
ab392d2d 930 dev->name, dev);
9b1fc55a
MB		 931 if (ret)
932 goto out_freeirq;
933
934 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 935 0, dev->name, dev);
9b1fc55a
MB		 936 if (ret)
937 goto out_freeirq_rx;
938
939 /* initialize perfect match registers */
940 for (i = 0; i < 4; i++) {
941 enet_writel(priv, 0, ENET_PML_REG(i));
942 enet_writel(priv, 0, ENET_PMH_REG(i));
943 }
944
945 /* write device mac address */
946 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
947 bcm_enet_set_mac_address(dev, &addr);
948
949 /* allocate rx dma ring */
950 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 951 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
9b1fc55a 952 if (!p) {
9b1fc55a
MB		 953 ret = -ENOMEM;
954 goto out_freeirq_tx;
955 }
956
9b1fc55a
MB		 957 priv->rx_desc_alloc_size = size;
958 priv->rx_desc_cpu = p;
959
960 /* allocate tx dma ring */
961 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 962 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
9b1fc55a 963 if (!p) {
9b1fc55a
MB		 964 ret = -ENOMEM;
965 goto out_free_rx_ring;
966 }
967
9b1fc55a
MB		 968 priv->tx_desc_alloc_size = size;
969 priv->tx_desc_cpu = p;
970
b2adaca9 971 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 972 GFP_KERNEL);
973 if (!priv->tx_skb) {
9b1fc55a
MB		 974 ret = -ENOMEM;
975 goto out_free_tx_ring;
976 }
977
978 priv->tx_desc_count = priv->tx_ring_size;
979 priv->tx_dirty_desc = 0;
980 priv->tx_curr_desc = 0;
981 spin_lock_init(&priv->tx_lock);
982
983 /* init & fill rx ring with skbs */
b2adaca9 984 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 985 GFP_KERNEL);
986 if (!priv->rx_skb) {
9b1fc55a
MB		 987 ret = -ENOMEM;
988 goto out_free_tx_skb;
989 }
990
991 priv->rx_desc_count = 0;
992 priv->rx_dirty_desc = 0;
993 priv->rx_curr_desc = 0;
994
995 /* initialize flow control buffer allocation */
3dc6475c
FF		 996 if (priv->dma_has_sram)
997 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
998 ENETDMA_BUFALLOC_REG(priv->rx_chan));
999 else
1000 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1001 ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 1002
1003 if (bcm_enet_refill_rx(dev)) {
1004 dev_err(kdev, "cannot allocate rx skb queue\n");
1005 ret = -ENOMEM;
1006 goto out;
1007 }
1008
1009 /* write rx & tx ring addresses */
3dc6475c
FF		 1010 if (priv->dma_has_sram) {
1011 enet_dmas_writel(priv, priv->rx_desc_dma,
1012 ENETDMAS_RSTART_REG, priv->rx_chan);
1013 enet_dmas_writel(priv, priv->tx_desc_dma,
1014 ENETDMAS_RSTART_REG, priv->tx_chan);
1015 } else {
1016 enet_dmac_writel(priv, priv->rx_desc_dma,
1017 ENETDMAC_RSTART, priv->rx_chan);
1018 enet_dmac_writel(priv, priv->tx_desc_dma,
1019 ENETDMAC_RSTART, priv->tx_chan);
1020 }
9b1fc55a
MB		 1021
1022 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 1023 if (priv->dma_has_sram) {
1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1027 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1028 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1029 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1030 } else {
1031 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1032 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1033 }
9b1fc55a
MB		 1034
1035 /* set max rx/tx length */
1036 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1037 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1038
1039 /* set dma maximum burst len */
6f00a022 1040 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1041 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 1042 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1043 ENETDMAC_MAXBURST, priv->tx_chan);
9b1fc55a
MB		 1044
1045 /* set correct transmit fifo watermark */
1046 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1047
1048 /* set flow control low/high threshold to 1/3 / 2/3 */
3dc6475c
FF		 1049 if (priv->dma_has_sram) {
1050 val = priv->rx_ring_size / 3;
1051 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1052 val = (priv->rx_ring_size * 2) / 3;
1053 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1054 } else {
1055 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1056 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1057 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1058 }
9b1fc55a
MB		 1059
1060 /* all set, enable mac and interrupts, start dma engine and
1061 * kick rx dma channel */
1062 wmb();
5e10d4a7
FF		 1063 val = enet_readl(priv, ENET_CTL_REG);
1064 val |= ENET_CTL_ENABLE_MASK;
1065 enet_writel(priv, val, ENET_CTL_REG);
9b1fc55a 1066 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
3dc6475c
FF		 1067 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1068 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 1069
1070 /* watch "mib counters about to overflow" interrupt */
1071 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1072 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1073
1074 /* watch "packet transferred" interrupt in rx and tx */
3dc6475c
FF		 1075 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076 ENETDMAC_IR, priv->rx_chan);
1077 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1078 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 1079
1080 /* make sure we enable napi before rx interrupt */
1081 napi_enable(&priv->napi);
1082
3dc6475c
FF		 1083 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084 ENETDMAC_IRMASK, priv->rx_chan);
1085 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1086 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 1087
1088 if (priv->has_phy)
1089 phy_start(priv->phydev);
1090 else
1091 bcm_enet_adjust_link(dev);
1092
1093 netif_start_queue(dev);
1094 return 0;
1095
1096out:
1097 for (i = 0; i < priv->rx_ring_size; i++) {
1098 struct bcm_enet_desc *desc;
1099
1100 if (!priv->rx_skb[i])
1101 continue;
1102
1103 desc = &priv->rx_desc_cpu[i];
1104 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1105 DMA_FROM_DEVICE);
1106 kfree_skb(priv->rx_skb[i]);
1107 }
1108 kfree(priv->rx_skb);
1109
1110out_free_tx_skb:
1111 kfree(priv->tx_skb);
1112
1113out_free_tx_ring:
1114 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1115 priv->tx_desc_cpu, priv->tx_desc_dma);
1116
1117out_free_rx_ring:
1118 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1119 priv->rx_desc_cpu, priv->rx_desc_dma);
1120
1121out_freeirq_tx:
1122 free_irq(priv->irq_tx, dev);
1123
1124out_freeirq_rx:
1125 free_irq(priv->irq_rx, dev);
1126
1127out_freeirq:
1128 free_irq(dev->irq, dev);
1129
1130out_phy_disconnect:
1131 phy_disconnect(priv->phydev);
1132
1133 return ret;
1134}
1135
1136/*
1137 * disable mac
1138 */
1139static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1140{
1141 int limit;
1142 u32 val;
1143
1144 val = enet_readl(priv, ENET_CTL_REG);
1145 val |= ENET_CTL_DISABLE_MASK;
1146 enet_writel(priv, val, ENET_CTL_REG);
1147
1148 limit = 1000;
1149 do {
1150 u32 val;
1151
1152 val = enet_readl(priv, ENET_CTL_REG);
1153 if (!(val & ENET_CTL_DISABLE_MASK))
1154 break;
1155 udelay(1);
1156 } while (limit--);
1157}
1158
1159/*
1160 * disable dma in given channel
1161 */
1162static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1163{
1164 int limit;
1165
3dc6475c 1166 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
9b1fc55a
MB		 1167
1168 limit = 1000;
1169 do {
1170 u32 val;
1171
3dc6475c 1172 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
0ae99b5f 1173 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
9b1fc55a
MB		 1174 break;
1175 udelay(1);
1176 } while (limit--);
1177}
1178
1179/*
1180 * stop callback
1181 */
1182static int bcm_enet_stop(struct net_device *dev)
1183{
1184 struct bcm_enet_priv *priv;
1185 struct device *kdev;
1186 int i;
1187
1188 priv = netdev_priv(dev);
1189 kdev = &priv->pdev->dev;
1190
1191 netif_stop_queue(dev);
1192 napi_disable(&priv->napi);
1193 if (priv->has_phy)
1194 phy_stop(priv->phydev);
1195 del_timer_sync(&priv->rx_timeout);
1196
1197 /* mask all interrupts */
1198 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 1199 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1200 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 1201
1202 /* make sure no mib update is scheduled */
23f333a2 1203 cancel_work_sync(&priv->mib_update_task);
9b1fc55a
MB		 1204
1205 /* disable dma & mac */
1206 bcm_enet_disable_dma(priv, priv->tx_chan);
1207 bcm_enet_disable_dma(priv, priv->rx_chan);
1208 bcm_enet_disable_mac(priv);
1209
1210 /* force reclaim of all tx buffers */
1211 bcm_enet_tx_reclaim(dev, 1);
1212
1213 /* free the rx skb ring */
1214 for (i = 0; i < priv->rx_ring_size; i++) {
1215 struct bcm_enet_desc *desc;
1216
1217 if (!priv->rx_skb[i])
1218 continue;
1219
1220 desc = &priv->rx_desc_cpu[i];
1221 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1222 DMA_FROM_DEVICE);
1223 kfree_skb(priv->rx_skb[i]);
1224 }
1225
1226 /* free remaining allocated memory */
1227 kfree(priv->rx_skb);
1228 kfree(priv->tx_skb);
1229 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1230 priv->rx_desc_cpu, priv->rx_desc_dma);
1231 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1232 priv->tx_desc_cpu, priv->tx_desc_dma);
1233 free_irq(priv->irq_tx, dev);
1234 free_irq(priv->irq_rx, dev);
1235 free_irq(dev->irq, dev);
1236
1237 /* release phy */
1238 if (priv->has_phy) {
1239 phy_disconnect(priv->phydev);
1240 priv->phydev = NULL;
1241 }
1242
1243 return 0;
1244}
1245
9b1fc55a
MB		 1246/*
1247 * ethtool callbacks
1248 */
1249struct bcm_enet_stats {
1250 char stat_string[ETH_GSTRING_LEN];
1251 int sizeof_stat;
1252 int stat_offset;
1253 int mib_reg;
1254};
1255
1256#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1257 offsetof(struct bcm_enet_priv, m)
c32d83c0
ED		 1258#define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1259 offsetof(struct net_device_stats, m)
9b1fc55a
MB		 1260
1261static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
c32d83c0
ED		 1262 { "rx_packets", DEV_STAT(rx_packets), -1 },
1263 { "tx_packets", DEV_STAT(tx_packets), -1 },
1264 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1265 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1266 { "rx_errors", DEV_STAT(rx_errors), -1 },
1267 { "tx_errors", DEV_STAT(tx_errors), -1 },
1268 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1269 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
9b1fc55a
MB		 1270
1271 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1272 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1273 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1274 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1275 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1276 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1277 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1278 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1279 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1280 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1281 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1282 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1283 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1284 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1285 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1286 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1287 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1288 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1289 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1290 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1291 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1292
1293 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1294 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1295 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1296 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1297 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1298 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1299 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1300 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1301 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1302 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1303 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1304 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1305 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1306 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1307 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1308 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1309 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1310 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1311 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1312 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1313 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1314 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1315
1316};
1317
6afc0d7a 1318#define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
9b1fc55a
MB		 1319
1320static const u32 unused_mib_regs[] = {
1321 ETH_MIB_TX_ALL_OCTETS,
1322 ETH_MIB_TX_ALL_PKTS,
1323 ETH_MIB_RX_ALL_OCTETS,
1324 ETH_MIB_RX_ALL_PKTS,
1325};
1326
1327
1328static void bcm_enet_get_drvinfo(struct net_device *netdev,
1329 struct ethtool_drvinfo *drvinfo)
1330{
7826d43f
JP		 1331 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1332 strlcpy(drvinfo->version, bcm_enet_driver_version,
1333 sizeof(drvinfo->version));
1334 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1335 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
9b1fc55a
MB		 1336 drvinfo->n_stats = BCM_ENET_STATS_LEN;
1337}
1338
a3f92eea
FF		 1339static int bcm_enet_get_sset_count(struct net_device *netdev,
1340 int string_set)
9b1fc55a 1341{
a3f92eea
FF		 1342 switch (string_set) {
1343 case ETH_SS_STATS:
1344 return BCM_ENET_STATS_LEN;
1345 default:
1346 return -EINVAL;
1347 }
9b1fc55a
MB		 1348}
1349
1350static void bcm_enet_get_strings(struct net_device *netdev,
1351 u32 stringset, u8 *data)
1352{
1353 int i;
1354
1355 switch (stringset) {
1356 case ETH_SS_STATS:
1357 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1358 memcpy(data + i * ETH_GSTRING_LEN,
1359 bcm_enet_gstrings_stats[i].stat_string,
1360 ETH_GSTRING_LEN);
1361 }
1362 break;
1363 }
1364}
1365
1366static void update_mib_counters(struct bcm_enet_priv *priv)
1367{
1368 int i;
1369
1370 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1371 const struct bcm_enet_stats *s;
1372 u32 val;
1373 char *p;
1374
1375 s = &bcm_enet_gstrings_stats[i];
1376 if (s->mib_reg == -1)
1377 continue;
1378
1379 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1380 p = (char *)priv + s->stat_offset;
1381
1382 if (s->sizeof_stat == sizeof(u64))
1383 *(u64 *)p += val;
1384 else
1385 *(u32 *)p += val;
1386 }
1387
1388 /* also empty unused mib counters to make sure mib counter
1389 * overflow interrupt is cleared */
1390 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1391 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1392}
1393
1394static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1395{
1396 struct bcm_enet_priv *priv;
1397
1398 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1399 mutex_lock(&priv->mib_update_lock);
1400 update_mib_counters(priv);
1401 mutex_unlock(&priv->mib_update_lock);
1402
1403 /* reenable mib interrupt */
1404 if (netif_running(priv->net_dev))
1405 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1406}
1407
1408static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1409 struct ethtool_stats *stats,
1410 u64 *data)
1411{
1412 struct bcm_enet_priv *priv;
1413 int i;
1414
1415 priv = netdev_priv(netdev);
1416
1417 mutex_lock(&priv->mib_update_lock);
1418 update_mib_counters(priv);
1419
1420 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1421 const struct bcm_enet_stats *s;
1422 char *p;
1423
1424 s = &bcm_enet_gstrings_stats[i];
c32d83c0
ED		 1425 if (s->mib_reg == -1)
1426 p = (char *)&netdev->stats;
1427 else
1428 p = (char *)priv;
1429 p += s->stat_offset;
9b1fc55a
MB		 1430 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1431 *(u64 *)p : *(u32 *)p;
1432 }
1433 mutex_unlock(&priv->mib_update_lock);
1434}
1435
7260aac9
MB		 1436static int bcm_enet_nway_reset(struct net_device *dev)
1437{
1438 struct bcm_enet_priv *priv;
1439
1440 priv = netdev_priv(dev);
1441 if (priv->has_phy) {
1442 if (!priv->phydev)
1443 return -ENODEV;
1444 return genphy_restart_aneg(priv->phydev);
1445 }
1446
1447 return -EOPNOTSUPP;
1448}
1449
9b1fc55a
MB		 1450static int bcm_enet_get_settings(struct net_device *dev,
1451 struct ethtool_cmd *cmd)
1452{
1453 struct bcm_enet_priv *priv;
1454
1455 priv = netdev_priv(dev);
1456
1457 cmd->maxrxpkt = 0;
1458 cmd->maxtxpkt = 0;
1459
1460 if (priv->has_phy) {
1461 if (!priv->phydev)
1462 return -ENODEV;
1463 return phy_ethtool_gset(priv->phydev, cmd);
1464 } else {
1465 cmd->autoneg = 0;
70739497
DD		 1466 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1467 ? SPEED_100 : SPEED_10));
9b1fc55a
MB		 1468 cmd->duplex = (priv->force_duplex_full) ?
1469 DUPLEX_FULL : DUPLEX_HALF;
1470 cmd->supported = ADVERTISED_10baseT_Half |
1471 ADVERTISED_10baseT_Full |
1472 ADVERTISED_100baseT_Half |
1473 ADVERTISED_100baseT_Full;
1474 cmd->advertising = 0;
1475 cmd->port = PORT_MII;
1476 cmd->transceiver = XCVR_EXTERNAL;
1477 }
1478 return 0;
1479}
1480
1481static int bcm_enet_set_settings(struct net_device *dev,
1482 struct ethtool_cmd *cmd)
1483{
1484 struct bcm_enet_priv *priv;
1485
1486 priv = netdev_priv(dev);
1487 if (priv->has_phy) {
1488 if (!priv->phydev)
1489 return -ENODEV;
1490 return phy_ethtool_sset(priv->phydev, cmd);
1491 } else {
1492
1493 if (cmd->autoneg ||
1494 (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1495 cmd->port != PORT_MII)
1496 return -EINVAL;
1497
1498 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1499 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1500
1501 if (netif_running(dev))
1502 bcm_enet_adjust_link(dev);
1503 return 0;
1504 }
1505}
1506
1507static void bcm_enet_get_ringparam(struct net_device *dev,
1508 struct ethtool_ringparam *ering)
1509{
1510 struct bcm_enet_priv *priv;
1511
1512 priv = netdev_priv(dev);
1513
1514 /* rx/tx ring is actually only limited by memory */
1515 ering->rx_max_pending = 8192;
1516 ering->tx_max_pending = 8192;
9b1fc55a
MB		 1517 ering->rx_pending = priv->rx_ring_size;
1518 ering->tx_pending = priv->tx_ring_size;
1519}
1520
1521static int bcm_enet_set_ringparam(struct net_device *dev,
1522 struct ethtool_ringparam *ering)
1523{
1524 struct bcm_enet_priv *priv;
1525 int was_running;
1526
1527 priv = netdev_priv(dev);
1528
1529 was_running = 0;
1530 if (netif_running(dev)) {
1531 bcm_enet_stop(dev);
1532 was_running = 1;
1533 }
1534
1535 priv->rx_ring_size = ering->rx_pending;
1536 priv->tx_ring_size = ering->tx_pending;
1537
1538 if (was_running) {
1539 int err;
1540
1541 err = bcm_enet_open(dev);
1542 if (err)
1543 dev_close(dev);
1544 else
1545 bcm_enet_set_multicast_list(dev);
1546 }
1547 return 0;
1548}
1549
1550static void bcm_enet_get_pauseparam(struct net_device *dev,
1551 struct ethtool_pauseparam *ecmd)
1552{
1553 struct bcm_enet_priv *priv;
1554
1555 priv = netdev_priv(dev);
1556 ecmd->autoneg = priv->pause_auto;
1557 ecmd->rx_pause = priv->pause_rx;
1558 ecmd->tx_pause = priv->pause_tx;
1559}
1560
1561static int bcm_enet_set_pauseparam(struct net_device *dev,
1562 struct ethtool_pauseparam *ecmd)
1563{
1564 struct bcm_enet_priv *priv;
1565
1566 priv = netdev_priv(dev);
1567
1568 if (priv->has_phy) {
1569 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1570 /* asymetric pause mode not supported,
1571 * actually possible but integrated PHY has RO
1572 * asym_pause bit */
1573 return -EINVAL;
1574 }
1575 } else {
1576 /* no pause autoneg on direct mii connection */
1577 if (ecmd->autoneg)
1578 return -EINVAL;
1579 }
1580
1581 priv->pause_auto = ecmd->autoneg;
1582 priv->pause_rx = ecmd->rx_pause;
1583 priv->pause_tx = ecmd->tx_pause;
1584
1585 return 0;
1586}
1587
1aff0cbe 1588static const struct ethtool_ops bcm_enet_ethtool_ops = {
9b1fc55a 1589 .get_strings = bcm_enet_get_strings,
a3f92eea 1590 .get_sset_count = bcm_enet_get_sset_count,
9b1fc55a 1591 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
7260aac9 1592 .nway_reset = bcm_enet_nway_reset,
9b1fc55a
MB		 1593 .get_settings = bcm_enet_get_settings,
1594 .set_settings = bcm_enet_set_settings,
1595 .get_drvinfo = bcm_enet_get_drvinfo,
1596 .get_link = ethtool_op_get_link,
1597 .get_ringparam = bcm_enet_get_ringparam,
1598 .set_ringparam = bcm_enet_set_ringparam,
1599 .get_pauseparam = bcm_enet_get_pauseparam,
1600 .set_pauseparam = bcm_enet_set_pauseparam,
1601};
1602
1603static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1604{
1605 struct bcm_enet_priv *priv;
1606
1607 priv = netdev_priv(dev);
1608 if (priv->has_phy) {
1609 if (!priv->phydev)
1610 return -ENODEV;
28b04113 1611 return phy_mii_ioctl(priv->phydev, rq, cmd);
9b1fc55a
MB		 1612 } else {
1613 struct mii_if_info mii;
1614
1615 mii.dev = dev;
1616 mii.mdio_read = bcm_enet_mdio_read_mii;
1617 mii.mdio_write = bcm_enet_mdio_write_mii;
1618 mii.phy_id = 0;
1619 mii.phy_id_mask = 0x3f;
1620 mii.reg_num_mask = 0x1f;
1621 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1622 }
1623}
1624
1625/*
1626 * calculate actual hardware mtu
1627 */
1628static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1629{
1630 int actual_mtu;
1631
1632 actual_mtu = mtu;
1633
1634 /* add ethernet header + vlan tag size */
1635 actual_mtu += VLAN_ETH_HLEN;
1636
1637 if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1638 return -EINVAL;
1639
1640 /*
1641 * setup maximum size before we get overflow mark in
1642 * descriptor, note that this will not prevent reception of
1643 * big frames, they will be split into multiple buffers
1644 * anyway
1645 */
1646 priv->hw_mtu = actual_mtu;
1647
1648 /*
1649 * align rx buffer size to dma burst len, account FCS since
1650 * it's appended
1651 */
1652 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
6f00a022 1653 priv->dma_maxburst * 4);
9b1fc55a
MB		 1654 return 0;
1655}
1656
1657/*
1658 * adjust mtu, can't be called while device is running
1659 */
1660static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1661{
1662 int ret;
1663
1664 if (netif_running(dev))
1665 return -EBUSY;
1666
1667 ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1668 if (ret)
1669 return ret;
1670 dev->mtu = new_mtu;
1671 return 0;
1672}
1673
1674/*
1675 * preinit hardware to allow mii operation while device is down
1676 */
1677static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1678{
1679 u32 val;
1680 int limit;
1681
1682 /* make sure mac is disabled */
1683 bcm_enet_disable_mac(priv);
1684
1685 /* soft reset mac */
1686 val = ENET_CTL_SRESET_MASK;
1687 enet_writel(priv, val, ENET_CTL_REG);
1688 wmb();
1689
1690 limit = 1000;
1691 do {
1692 val = enet_readl(priv, ENET_CTL_REG);
1693 if (!(val & ENET_CTL_SRESET_MASK))
1694 break;
1695 udelay(1);
1696 } while (limit--);
1697
1698 /* select correct mii interface */
1699 val = enet_readl(priv, ENET_CTL_REG);
1700 if (priv->use_external_mii)
1701 val |= ENET_CTL_EPHYSEL_MASK;
1702 else
1703 val &= ~ENET_CTL_EPHYSEL_MASK;
1704 enet_writel(priv, val, ENET_CTL_REG);
1705
1706 /* turn on mdc clock */
1707 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1708 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1709
1710 /* set mib counters to self-clear when read */
1711 val = enet_readl(priv, ENET_MIBCTL_REG);
1712 val |= ENET_MIBCTL_RDCLEAR_MASK;
1713 enet_writel(priv, val, ENET_MIBCTL_REG);
1714}
1715
1716static const struct net_device_ops bcm_enet_ops = {
1717 .ndo_open = bcm_enet_open,
1718 .ndo_stop = bcm_enet_stop,
1719 .ndo_start_xmit = bcm_enet_start_xmit,
9b1fc55a 1720 .ndo_set_mac_address = bcm_enet_set_mac_address,
afc4b13d 1721 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
9b1fc55a
MB		 1722 .ndo_do_ioctl = bcm_enet_ioctl,
1723 .ndo_change_mtu = bcm_enet_change_mtu,
9b1fc55a
MB		 1724};
1725
1726/*
1727 * allocate netdevice, request register memory and register device.
1728 */
047fc566 1729static int bcm_enet_probe(struct platform_device *pdev)
9b1fc55a
MB		 1730{
1731 struct bcm_enet_priv *priv;
1732 struct net_device *dev;
1733 struct bcm63xx_enet_platform_data *pd;
1734 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1735 struct mii_bus *bus;
1736 const char *clk_name;
9b1fc55a
MB		 1737 int i, ret;
1738
1739 /* stop if shared driver failed, assume driver->probe will be
1740 * called in the same order we register devices (correct ?) */
0ae99b5f 1741 if (!bcm_enet_shared_base[0])
9b1fc55a
MB		 1742 return -ENODEV;
1743
9b1fc55a
MB		 1744 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1745 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1746 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
f607e059 1747 if (!res_irq || !res_irq_rx || !res_irq_tx)
9b1fc55a
MB		 1748 return -ENODEV;
1749
1750 ret = 0;
1751 dev = alloc_etherdev(sizeof(*priv));
1752 if (!dev)
1753 return -ENOMEM;
1754 priv = netdev_priv(dev);
9b1fc55a 1755
6f00a022
MB		 1756 priv->enet_is_sw = false;
1757 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1758
9b1fc55a
MB		 1759 ret = compute_hw_mtu(priv, dev->mtu);
1760 if (ret)
1761 goto out;
1762
f607e059
JL		 1763 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1764 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1765 if (IS_ERR(priv->base)) {
1766 ret = PTR_ERR(priv->base);
1c03da05 1767 goto out;
9b1fc55a 1768 }
1c03da05 1769
9b1fc55a
MB		 1770 dev->irq = priv->irq = res_irq->start;
1771 priv->irq_rx = res_irq_rx->start;
1772 priv->irq_tx = res_irq_tx->start;
1773 priv->mac_id = pdev->id;
1774
1775 /* get rx & tx dma channel id for this mac */
1776 if (priv->mac_id == 0) {
1777 priv->rx_chan = 0;
1778 priv->tx_chan = 1;
1779 clk_name = "enet0";
1780 } else {
1781 priv->rx_chan = 2;
1782 priv->tx_chan = 3;
1783 clk_name = "enet1";
1784 }
1785
1786 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1787 if (IS_ERR(priv->mac_clk)) {
1788 ret = PTR_ERR(priv->mac_clk);
1c03da05 1789 goto out;
9b1fc55a 1790 }
624e2d21 1791 clk_prepare_enable(priv->mac_clk);
9b1fc55a
MB		 1792
1793 /* initialize default and fetch platform data */
1794 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1795 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1796
cf0e7794 1797 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1798 if (pd) {
1799 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1800 priv->has_phy = pd->has_phy;
1801 priv->phy_id = pd->phy_id;
1802 priv->has_phy_interrupt = pd->has_phy_interrupt;
1803 priv->phy_interrupt = pd->phy_interrupt;
1804 priv->use_external_mii = !pd->use_internal_phy;
1805 priv->pause_auto = pd->pause_auto;
1806 priv->pause_rx = pd->pause_rx;
1807 priv->pause_tx = pd->pause_tx;
1808 priv->force_duplex_full = pd->force_duplex_full;
1809 priv->force_speed_100 = pd->force_speed_100;
3dc6475c
FF		 1810 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1811 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1812 priv->dma_chan_width = pd->dma_chan_width;
1813 priv->dma_has_sram = pd->dma_has_sram;
1814 priv->dma_desc_shift = pd->dma_desc_shift;
9b1fc55a
MB		 1815 }
1816
1817 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1818 /* using internal PHY, enable clock */
1819 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1820 if (IS_ERR(priv->phy_clk)) {
1821 ret = PTR_ERR(priv->phy_clk);
1822 priv->phy_clk = NULL;
1823 goto out_put_clk_mac;
1824 }
624e2d21 1825 clk_prepare_enable(priv->phy_clk);
9b1fc55a
MB		 1826 }
1827
1828 /* do minimal hardware init to be able to probe mii bus */
1829 bcm_enet_hw_preinit(priv);
1830
1831 /* MII bus registration */
1832 if (priv->has_phy) {
1833
1834 priv->mii_bus = mdiobus_alloc();
1835 if (!priv->mii_bus) {
1836 ret = -ENOMEM;
1837 goto out_uninit_hw;
1838 }
1839
1840 bus = priv->mii_bus;
1841 bus->name = "bcm63xx_enet MII bus";
1842 bus->parent = &pdev->dev;
1843 bus->priv = priv;
1844 bus->read = bcm_enet_mdio_read_phylib;
1845 bus->write = bcm_enet_mdio_write_phylib;
3e617506 1846 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
9b1fc55a
MB		 1847
1848 /* only probe bus where we think the PHY is, because
1849 * the mdio read operation return 0 instead of 0xffff
1850 * if a slave is not present on hw */
1851 bus->phy_mask = ~(1 << priv->phy_id);
1852
2a80b5e1
JG		 1853 bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR,
1854 GFP_KERNEL);
9b1fc55a
MB		 1855 if (!bus->irq) {
1856 ret = -ENOMEM;
1857 goto out_free_mdio;
1858 }
1859
1860 if (priv->has_phy_interrupt)
1861 bus->irq[priv->phy_id] = priv->phy_interrupt;
1862 else
1863 bus->irq[priv->phy_id] = PHY_POLL;
1864
1865 ret = mdiobus_register(bus);
1866 if (ret) {
1867 dev_err(&pdev->dev, "unable to register mdio bus\n");
1868 goto out_free_mdio;
1869 }
1870 } else {
1871
1872 /* run platform code to initialize PHY device */
1873 if (pd->mii_config &&
1874 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1875 bcm_enet_mdio_write_mii)) {
1876 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1877 goto out_uninit_hw;
1878 }
1879 }
1880
1881 spin_lock_init(&priv->rx_lock);
1882
1883 /* init rx timeout (used for oom) */
1884 init_timer(&priv->rx_timeout);
1885 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1886 priv->rx_timeout.data = (unsigned long)dev;
1887
1888 /* init the mib update lock&work */
1889 mutex_init(&priv->mib_update_lock);
1890 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1891
1892 /* zero mib counters */
1893 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1894 enet_writel(priv, 0, ENET_MIB_REG(i));
1895
1896 /* register netdevice */
1897 dev->netdev_ops = &bcm_enet_ops;
1898 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1899
7ad24ea4 1900 dev->ethtool_ops = &bcm_enet_ethtool_ops;
9b1fc55a
MB		 1901 SET_NETDEV_DEV(dev, &pdev->dev);
1902
1903 ret = register_netdev(dev);
1904 if (ret)
1905 goto out_unregister_mdio;
1906
1907 netif_carrier_off(dev);
1908 platform_set_drvdata(pdev, dev);
1909 priv->pdev = pdev;
1910 priv->net_dev = dev;
1911
1912 return 0;
1913
1914out_unregister_mdio:
2a80b5e1 1915 if (priv->mii_bus)
9b1fc55a 1916 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1917
1918out_free_mdio:
1919 if (priv->mii_bus)
1920 mdiobus_free(priv->mii_bus);
1921
1922out_uninit_hw:
1923 /* turn off mdc clock */
1924 enet_writel(priv, 0, ENET_MIISC_REG);
1925 if (priv->phy_clk) {
624e2d21 1926 clk_disable_unprepare(priv->phy_clk);
9b1fc55a
MB		 1927 clk_put(priv->phy_clk);
1928 }
1929
1930out_put_clk_mac:
624e2d21 1931 clk_disable_unprepare(priv->mac_clk);
9b1fc55a 1932 clk_put(priv->mac_clk);
9b1fc55a
MB		 1933out:
1934 free_netdev(dev);
1935 return ret;
1936}
1937
1938
1939/*
1940 * exit func, stops hardware and unregisters netdevice
1941 */
047fc566 1942static int bcm_enet_remove(struct platform_device *pdev)
9b1fc55a
MB		 1943{
1944 struct bcm_enet_priv *priv;
1945 struct net_device *dev;
9b1fc55a
MB		 1946
1947 /* stop netdevice */
1948 dev = platform_get_drvdata(pdev);
1949 priv = netdev_priv(dev);
1950 unregister_netdev(dev);
1951
1952 /* turn off mdc clock */
1953 enet_writel(priv, 0, ENET_MIISC_REG);
1954
1955 if (priv->has_phy) {
1956 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1957 mdiobus_free(priv->mii_bus);
1958 } else {
1959 struct bcm63xx_enet_platform_data *pd;
1960
cf0e7794 1961 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1962 if (pd && pd->mii_config)
1963 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1964 bcm_enet_mdio_write_mii);
1965 }
1966
9b1fc55a
MB		 1967 /* disable hw block clocks */
1968 if (priv->phy_clk) {
624e2d21 1969 clk_disable_unprepare(priv->phy_clk);
9b1fc55a
MB		 1970 clk_put(priv->phy_clk);
1971 }
624e2d21 1972 clk_disable_unprepare(priv->mac_clk);
9b1fc55a
MB		 1973 clk_put(priv->mac_clk);
1974
9b1fc55a
MB		 1975 free_netdev(dev);
1976 return 0;
1977}
1978
1979struct platform_driver bcm63xx_enet_driver = {
1980 .probe = bcm_enet_probe,
047fc566 1981 .remove = bcm_enet_remove,
9b1fc55a
MB		 1982 .driver = {
1983 .name = "bcm63xx_enet",
1984 .owner = THIS_MODULE,
1985 },
1986};
1987
1988/*
6f00a022 1989 * switch mii access callbacks
9b1fc55a 1990 */
6f00a022
MB		 1991static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1992 int ext, int phy_id, int location)
9b1fc55a 1993{
6f00a022
MB		 1994 u32 reg;
1995 int ret;
9b1fc55a 1996
6f00a022
MB		 1997 spin_lock_bh(&priv->enetsw_mdio_lock);
1998 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
9b1fc55a 1999
6f00a022
MB		 2000 reg = ENETSW_MDIOC_RD_MASK |
2001 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2002 (location << ENETSW_MDIOC_REG_SHIFT);
0ae99b5f 2003
6f00a022
MB		 2004 if (ext)
2005 reg |= ENETSW_MDIOC_EXT_MASK;
1c03da05 2006
6f00a022
MB		 2007 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2008 udelay(50);
2009 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
2010 spin_unlock_bh(&priv->enetsw_mdio_lock);
2011 return ret;
9b1fc55a
MB		 2012}
2013
6f00a022
MB		 2014static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2015 int ext, int phy_id, int location,
2016 uint16_t data)
9b1fc55a 2017{
6f00a022
MB		 2018 u32 reg;
2019
2020 spin_lock_bh(&priv->enetsw_mdio_lock);
2021 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2022
2023 reg = ENETSW_MDIOC_WR_MASK |
2024 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2025 (location << ENETSW_MDIOC_REG_SHIFT);
2026
2027 if (ext)
2028 reg |= ENETSW_MDIOC_EXT_MASK;
2029
2030 reg |= data;
2031
2032 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2033 udelay(50);
2034 spin_unlock_bh(&priv->enetsw_mdio_lock);
2035}
2036
2037static inline int bcm_enet_port_is_rgmii(int portid)
2038{
2039 return portid >= ENETSW_RGMII_PORT0;
9b1fc55a
MB		 2040}
2041
2042/*
6f00a022 2043 * enet sw PHY polling
9b1fc55a 2044 */
6f00a022
MB		 2045static void swphy_poll_timer(unsigned long data)
2046{
2047 struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2048 unsigned int i;
2049
2050 for (i = 0; i < priv->num_ports; i++) {
2051 struct bcm63xx_enetsw_port *port;
2052 int val, j, up, advertise, lpa, lpa2, speed, duplex, media;
2053 int external_phy = bcm_enet_port_is_rgmii(i);
2054 u8 override;
2055
2056 port = &priv->used_ports[i];
2057 if (!port->used)
2058 continue;
2059
2060 if (port->bypass_link)
2061 continue;
2062
2063 /* dummy read to clear */
2064 for (j = 0; j < 2; j++)
2065 val = bcmenet_sw_mdio_read(priv, external_phy,
2066 port->phy_id, MII_BMSR);
2067
2068 if (val == 0xffff)
2069 continue;
2070
2071 up = (val & BMSR_LSTATUS) ? 1 : 0;
2072 if (!(up ^ priv->sw_port_link[i]))
2073 continue;
2074
2075 priv->sw_port_link[i] = up;
2076
2077 /* link changed */
2078 if (!up) {
2079 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2080 port->name);
2081 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2082 ENETSW_PORTOV_REG(i));
2083 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2084 ENETSW_PTCTRL_TXDIS_MASK,
2085 ENETSW_PTCTRL_REG(i));
2086 continue;
2087 }
2088
2089 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2090 port->phy_id, MII_ADVERTISE);
2091
2092 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2093 MII_LPA);
2094
2095 lpa2 = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2096 MII_STAT1000);
2097
2098 /* figure out media and duplex from advertise and LPA values */
2099 media = mii_nway_result(lpa & advertise);
2100 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2101 if (lpa2 & LPA_1000FULL)
2102 duplex = 1;
2103
2104 if (lpa2 & (LPA_1000FULL | LPA_1000HALF))
2105 speed = 1000;
2106 else {
2107 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2108 speed = 100;
2109 else
2110 speed = 10;
2111 }
2112
2113 dev_info(&priv->pdev->dev,
2114 "link UP on %s, %dMbps, %s-duplex\n",
2115 port->name, speed, duplex ? "full" : "half");
2116
2117 override = ENETSW_PORTOV_ENABLE_MASK |
2118 ENETSW_PORTOV_LINKUP_MASK;
2119
2120 if (speed == 1000)
2121 override |= ENETSW_IMPOV_1000_MASK;
2122 else if (speed == 100)
2123 override |= ENETSW_IMPOV_100_MASK;
2124 if (duplex)
2125 override |= ENETSW_IMPOV_FDX_MASK;
2126
2127 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2128 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2129 }
2130
2131 priv->swphy_poll.expires = jiffies + HZ;
2132 add_timer(&priv->swphy_poll);
2133}
9b1fc55a
MB		 2134
2135/*
6f00a022 2136 * open callback, allocate dma rings & buffers and start rx operation
9b1fc55a 2137 */
6f00a022 2138static int bcm_enetsw_open(struct net_device *dev)
9b1fc55a 2139{
6f00a022
MB		 2140 struct bcm_enet_priv *priv;
2141 struct device *kdev;
2142 int i, ret;
2143 unsigned int size;
2144 void *p;
2145 u32 val;
9b1fc55a 2146
6f00a022
MB		 2147 priv = netdev_priv(dev);
2148 kdev = &priv->pdev->dev;
9b1fc55a 2149
6f00a022 2150 /* mask all interrupts and request them */
3dc6475c
FF		 2151 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2152 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2153
2154 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
df9f1b9f 2155 0, dev->name, dev);
9b1fc55a 2156 if (ret)
6f00a022
MB		 2157 goto out_freeirq;
2158
2159 if (priv->irq_tx != -1) {
2160 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 2161 0, dev->name, dev);
6f00a022
MB		 2162 if (ret)
2163 goto out_freeirq_rx;
2164 }
2165
2166 /* allocate rx dma ring */
2167 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2168 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2169 if (!p) {
2170 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2171 ret = -ENOMEM;
2172 goto out_freeirq_tx;
2173 }
2174
2175 memset(p, 0, size);
2176 priv->rx_desc_alloc_size = size;
2177 priv->rx_desc_cpu = p;
2178
2179 /* allocate tx dma ring */
2180 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2181 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2182 if (!p) {
2183 dev_err(kdev, "cannot allocate tx ring\n");
2184 ret = -ENOMEM;
2185 goto out_free_rx_ring;
2186 }
2187
2188 memset(p, 0, size);
2189 priv->tx_desc_alloc_size = size;
2190 priv->tx_desc_cpu = p;
2191
2192 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2193 GFP_KERNEL);
2194 if (!priv->tx_skb) {
2195 dev_err(kdev, "cannot allocate rx skb queue\n");
2196 ret = -ENOMEM;
2197 goto out_free_tx_ring;
2198 }
2199
2200 priv->tx_desc_count = priv->tx_ring_size;
2201 priv->tx_dirty_desc = 0;
2202 priv->tx_curr_desc = 0;
2203 spin_lock_init(&priv->tx_lock);
2204
2205 /* init & fill rx ring with skbs */
2206 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2207 GFP_KERNEL);
2208 if (!priv->rx_skb) {
2209 dev_err(kdev, "cannot allocate rx skb queue\n");
2210 ret = -ENOMEM;
2211 goto out_free_tx_skb;
2212 }
2213
2214 priv->rx_desc_count = 0;
2215 priv->rx_dirty_desc = 0;
2216 priv->rx_curr_desc = 0;
2217
2218 /* disable all ports */
2219 for (i = 0; i < priv->num_ports; i++) {
2220 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2221 ENETSW_PORTOV_REG(i));
2222 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2223 ENETSW_PTCTRL_TXDIS_MASK,
2224 ENETSW_PTCTRL_REG(i));
2225
2226 priv->sw_port_link[i] = 0;
2227 }
2228
2229 /* reset mib */
2230 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2231 val |= ENETSW_GMCR_RST_MIB_MASK;
2232 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2233 mdelay(1);
2234 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2235 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2236 mdelay(1);
2237
2238 /* force CPU port state */
2239 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2240 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2241 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2242
2243 /* enable switch forward engine */
2244 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2245 val |= ENETSW_SWMODE_FWD_EN_MASK;
2246 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2247
2248 /* enable jumbo on all ports */
2249 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2250 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2251
2252 /* initialize flow control buffer allocation */
2253 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2254 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2255
2256 if (bcm_enet_refill_rx(dev)) {
2257 dev_err(kdev, "cannot allocate rx skb queue\n");
2258 ret = -ENOMEM;
2259 goto out;
2260 }
2261
2262 /* write rx & tx ring addresses */
2263 enet_dmas_writel(priv, priv->rx_desc_dma,
3dc6475c 2264 ENETDMAS_RSTART_REG, priv->rx_chan);
6f00a022 2265 enet_dmas_writel(priv, priv->tx_desc_dma,
3dc6475c 2266 ENETDMAS_RSTART_REG, priv->tx_chan);
6f00a022
MB		 2267
2268 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 2269 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2270 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2271 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2272 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2273 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2274 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
6f00a022
MB		 2275
2276 /* set dma maximum burst len */
2277 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2278 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 2279 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2280 ENETDMAC_MAXBURST, priv->tx_chan);
6f00a022
MB		 2281
2282 /* set flow control low/high threshold to 1/3 / 2/3 */
2283 val = priv->rx_ring_size / 3;
2284 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2285 val = (priv->rx_ring_size * 2) / 3;
2286 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2287
2288 /* all set, enable mac and interrupts, start dma engine and
2289 * kick rx dma channel
2290 */
2291 wmb();
2292 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2293 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
3dc6475c 2294 ENETDMAC_CHANCFG, priv->rx_chan);
6f00a022
MB		 2295
2296 /* watch "packet transferred" interrupt in rx and tx */
2297 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2298 ENETDMAC_IR, priv->rx_chan);
6f00a022 2299 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2300 ENETDMAC_IR, priv->tx_chan);
6f00a022
MB		 2301
2302 /* make sure we enable napi before rx interrupt */
2303 napi_enable(&priv->napi);
2304
2305 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2306 ENETDMAC_IRMASK, priv->rx_chan);
6f00a022 2307 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2308 ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2309
2310 netif_carrier_on(dev);
2311 netif_start_queue(dev);
2312
2313 /* apply override config for bypass_link ports here. */
2314 for (i = 0; i < priv->num_ports; i++) {
2315 struct bcm63xx_enetsw_port *port;
2316 u8 override;
2317 port = &priv->used_ports[i];
2318 if (!port->used)
2319 continue;
2320
2321 if (!port->bypass_link)
2322 continue;
2323
2324 override = ENETSW_PORTOV_ENABLE_MASK |
2325 ENETSW_PORTOV_LINKUP_MASK;
2326
2327 switch (port->force_speed) {
2328 case 1000:
2329 override |= ENETSW_IMPOV_1000_MASK;
2330 break;
2331 case 100:
2332 override |= ENETSW_IMPOV_100_MASK;
2333 break;
2334 case 10:
2335 break;
2336 default:
2337 pr_warn("invalid forced speed on port %s: assume 10\n",
2338 port->name);
2339 break;
2340 }
2341
2342 if (port->force_duplex_full)
2343 override |= ENETSW_IMPOV_FDX_MASK;
2344
2345
2346 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2347 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2348 }
2349
2350 /* start phy polling timer */
2351 init_timer(&priv->swphy_poll);
2352 priv->swphy_poll.function = swphy_poll_timer;
2353 priv->swphy_poll.data = (unsigned long)priv;
2354 priv->swphy_poll.expires = jiffies;
2355 add_timer(&priv->swphy_poll);
2356 return 0;
2357
2358out:
2359 for (i = 0; i < priv->rx_ring_size; i++) {
2360 struct bcm_enet_desc *desc;
2361
2362 if (!priv->rx_skb[i])
2363 continue;
2364
2365 desc = &priv->rx_desc_cpu[i];
2366 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2367 DMA_FROM_DEVICE);
2368 kfree_skb(priv->rx_skb[i]);
2369 }
2370 kfree(priv->rx_skb);
2371
2372out_free_tx_skb:
2373 kfree(priv->tx_skb);
2374
2375out_free_tx_ring:
2376 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2377 priv->tx_desc_cpu, priv->tx_desc_dma);
2378
2379out_free_rx_ring:
2380 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2381 priv->rx_desc_cpu, priv->rx_desc_dma);
2382
2383out_freeirq_tx:
2384 if (priv->irq_tx != -1)
2385 free_irq(priv->irq_tx, dev);
2386
2387out_freeirq_rx:
2388 free_irq(priv->irq_rx, dev);
2389
2390out_freeirq:
2391 return ret;
2392}
2393
2394/* stop callback */
2395static int bcm_enetsw_stop(struct net_device *dev)
2396{
2397 struct bcm_enet_priv *priv;
2398 struct device *kdev;
2399 int i;
2400
2401 priv = netdev_priv(dev);
2402 kdev = &priv->pdev->dev;
2403
2404 del_timer_sync(&priv->swphy_poll);
2405 netif_stop_queue(dev);
2406 napi_disable(&priv->napi);
2407 del_timer_sync(&priv->rx_timeout);
2408
2409 /* mask all interrupts */
3dc6475c
FF		 2410 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2411 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2412
2413 /* disable dma & mac */
2414 bcm_enet_disable_dma(priv, priv->tx_chan);
2415 bcm_enet_disable_dma(priv, priv->rx_chan);
2416
2417 /* force reclaim of all tx buffers */
2418 bcm_enet_tx_reclaim(dev, 1);
2419
2420 /* free the rx skb ring */
2421 for (i = 0; i < priv->rx_ring_size; i++) {
2422 struct bcm_enet_desc *desc;
2423
2424 if (!priv->rx_skb[i])
2425 continue;
2426
2427 desc = &priv->rx_desc_cpu[i];
2428 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2429 DMA_FROM_DEVICE);
2430 kfree_skb(priv->rx_skb[i]);
2431 }
2432
2433 /* free remaining allocated memory */
2434 kfree(priv->rx_skb);
2435 kfree(priv->tx_skb);
2436 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2437 priv->rx_desc_cpu, priv->rx_desc_dma);
2438 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2439 priv->tx_desc_cpu, priv->tx_desc_dma);
2440 if (priv->irq_tx != -1)
2441 free_irq(priv->irq_tx, dev);
2442 free_irq(priv->irq_rx, dev);
2443
2444 return 0;
2445}
2446
2447/* try to sort out phy external status by walking the used_port field
2448 * in the bcm_enet_priv structure. in case the phy address is not
2449 * assigned to any physical port on the switch, assume it is external
2450 * (and yell at the user).
2451 */
2452static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2453{
2454 int i;
2455
2456 for (i = 0; i < priv->num_ports; ++i) {
2457 if (!priv->used_ports[i].used)
2458 continue;
2459 if (priv->used_ports[i].phy_id == phy_id)
2460 return bcm_enet_port_is_rgmii(i);
2461 }
2462
2463 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2464 phy_id);
2465 return 1;
2466}
2467
2468/* can't use bcmenet_sw_mdio_read directly as we need to sort out
2469 * external/internal status of the given phy_id first.
2470 */
2471static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2472 int location)
2473{
2474 struct bcm_enet_priv *priv;
2475
2476 priv = netdev_priv(dev);
2477 return bcmenet_sw_mdio_read(priv,
2478 bcm_enetsw_phy_is_external(priv, phy_id),
2479 phy_id, location);
2480}
2481
2482/* can't use bcmenet_sw_mdio_write directly as we need to sort out
2483 * external/internal status of the given phy_id first.
2484 */
2485static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2486 int location,
2487 int val)
2488{
2489 struct bcm_enet_priv *priv;
2490
2491 priv = netdev_priv(dev);
2492 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2493 phy_id, location, val);
2494}
2495
2496static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2497{
2498 struct mii_if_info mii;
2499
2500 mii.dev = dev;
2501 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2502 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2503 mii.phy_id = 0;
2504 mii.phy_id_mask = 0x3f;
2505 mii.reg_num_mask = 0x1f;
2506 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2507
2508}
2509
2510static const struct net_device_ops bcm_enetsw_ops = {
2511 .ndo_open = bcm_enetsw_open,
2512 .ndo_stop = bcm_enetsw_stop,
2513 .ndo_start_xmit = bcm_enet_start_xmit,
2514 .ndo_change_mtu = bcm_enet_change_mtu,
2515 .ndo_do_ioctl = bcm_enetsw_ioctl,
2516};
2517
2518
2519static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2520 { "rx_packets", DEV_STAT(rx_packets), -1 },
2521 { "tx_packets", DEV_STAT(tx_packets), -1 },
2522 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2523 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2524 { "rx_errors", DEV_STAT(rx_errors), -1 },
2525 { "tx_errors", DEV_STAT(tx_errors), -1 },
2526 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2527 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2528
2529 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2530 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2531 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2532 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2533 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2534 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2535 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2536 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2537 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2538 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2539 ETHSW_MIB_RX_1024_1522 },
2540 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2541 ETHSW_MIB_RX_1523_2047 },
2542 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2543 ETHSW_MIB_RX_2048_4095 },
2544 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2545 ETHSW_MIB_RX_4096_8191 },
2546 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2547 ETHSW_MIB_RX_8192_9728 },
2548 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2549 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2550 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2551 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2552 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2553
2554 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2555 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2556 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2557 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2558 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2559 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2560
2561};
2562
2563#define BCM_ENETSW_STATS_LEN \
2564 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2565
2566static void bcm_enetsw_get_strings(struct net_device *netdev,
2567 u32 stringset, u8 *data)
2568{
2569 int i;
2570
2571 switch (stringset) {
2572 case ETH_SS_STATS:
2573 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2574 memcpy(data + i * ETH_GSTRING_LEN,
2575 bcm_enetsw_gstrings_stats[i].stat_string,
2576 ETH_GSTRING_LEN);
2577 }
2578 break;
2579 }
2580}
2581
2582static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2583 int string_set)
2584{
2585 switch (string_set) {
2586 case ETH_SS_STATS:
2587 return BCM_ENETSW_STATS_LEN;
2588 default:
2589 return -EINVAL;
2590 }
2591}
2592
2593static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2594 struct ethtool_drvinfo *drvinfo)
2595{
2596 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2597 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2598 strncpy(drvinfo->fw_version, "N/A", 32);
2599 strncpy(drvinfo->bus_info, "bcm63xx", 32);
2600 drvinfo->n_stats = BCM_ENETSW_STATS_LEN;
2601}
2602
2603static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2604 struct ethtool_stats *stats,
2605 u64 *data)
2606{
2607 struct bcm_enet_priv *priv;
2608 int i;
2609
2610 priv = netdev_priv(netdev);
2611
2612 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2613 const struct bcm_enet_stats *s;
2614 u32 lo, hi;
2615 char *p;
2616 int reg;
2617
2618 s = &bcm_enetsw_gstrings_stats[i];
2619
2620 reg = s->mib_reg;
2621 if (reg == -1)
2622 continue;
2623
2624 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2625 p = (char *)priv + s->stat_offset;
2626
2627 if (s->sizeof_stat == sizeof(u64)) {
2628 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2629 *(u64 *)p = ((u64)hi << 32 | lo);
2630 } else {
2631 *(u32 *)p = lo;
2632 }
2633 }
2634
2635 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2636 const struct bcm_enet_stats *s;
2637 char *p;
2638
2639 s = &bcm_enetsw_gstrings_stats[i];
2640
2641 if (s->mib_reg == -1)
2642 p = (char *)&netdev->stats + s->stat_offset;
2643 else
2644 p = (char *)priv + s->stat_offset;
2645
2646 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2647 *(u64 *)p : *(u32 *)p;
2648 }
2649}
2650
2651static void bcm_enetsw_get_ringparam(struct net_device *dev,
2652 struct ethtool_ringparam *ering)
2653{
2654 struct bcm_enet_priv *priv;
2655
2656 priv = netdev_priv(dev);
2657
2658 /* rx/tx ring is actually only limited by memory */
2659 ering->rx_max_pending = 8192;
2660 ering->tx_max_pending = 8192;
2661 ering->rx_mini_max_pending = 0;
2662 ering->rx_jumbo_max_pending = 0;
2663 ering->rx_pending = priv->rx_ring_size;
2664 ering->tx_pending = priv->tx_ring_size;
2665}
2666
2667static int bcm_enetsw_set_ringparam(struct net_device *dev,
2668 struct ethtool_ringparam *ering)
2669{
2670 struct bcm_enet_priv *priv;
2671 int was_running;
2672
2673 priv = netdev_priv(dev);
2674
2675 was_running = 0;
2676 if (netif_running(dev)) {
2677 bcm_enetsw_stop(dev);
2678 was_running = 1;
2679 }
2680
2681 priv->rx_ring_size = ering->rx_pending;
2682 priv->tx_ring_size = ering->tx_pending;
2683
2684 if (was_running) {
2685 int err;
2686
2687 err = bcm_enetsw_open(dev);
2688 if (err)
2689 dev_close(dev);
2690 }
2691 return 0;
2692}
2693
2694static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2695 .get_strings = bcm_enetsw_get_strings,
2696 .get_sset_count = bcm_enetsw_get_sset_count,
2697 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2698 .get_drvinfo = bcm_enetsw_get_drvinfo,
2699 .get_ringparam = bcm_enetsw_get_ringparam,
2700 .set_ringparam = bcm_enetsw_set_ringparam,
2701};
2702
2703/* allocate netdevice, request register memory and register device. */
2704static int bcm_enetsw_probe(struct platform_device *pdev)
2705{
2706 struct bcm_enet_priv *priv;
2707 struct net_device *dev;
2708 struct bcm63xx_enetsw_platform_data *pd;
2709 struct resource *res_mem;
2710 int ret, irq_rx, irq_tx;
2711
2712 /* stop if shared driver failed, assume driver->probe will be
2713 * called in the same order we register devices (correct ?)
2714 */
2715 if (!bcm_enet_shared_base[0])
2716 return -ENODEV;
2717
2718 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2719 irq_rx = platform_get_irq(pdev, 0);
2720 irq_tx = platform_get_irq(pdev, 1);
2721 if (!res_mem || irq_rx < 0)
2722 return -ENODEV;
2723
2724 ret = 0;
2725 dev = alloc_etherdev(sizeof(*priv));
2726 if (!dev)
2727 return -ENOMEM;
2728 priv = netdev_priv(dev);
2729 memset(priv, 0, sizeof(*priv));
2730
2731 /* initialize default and fetch platform data */
2732 priv->enet_is_sw = true;
2733 priv->irq_rx = irq_rx;
2734 priv->irq_tx = irq_tx;
2735 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2736 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2737 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2738
cf0e7794 2739 pd = dev_get_platdata(&pdev->dev);
6f00a022
MB		 2740 if (pd) {
2741 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2742 memcpy(priv->used_ports, pd->used_ports,
2743 sizeof(pd->used_ports));
2744 priv->num_ports = pd->num_ports;
3dc6475c
FF		 2745 priv->dma_has_sram = pd->dma_has_sram;
2746 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2747 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2748 priv->dma_chan_width = pd->dma_chan_width;
6f00a022
MB		 2749 }
2750
2751 ret = compute_hw_mtu(priv, dev->mtu);
2752 if (ret)
2753 goto out;
2754
2755 if (!request_mem_region(res_mem->start, resource_size(res_mem),
2756 "bcm63xx_enetsw")) {
2757 ret = -EBUSY;
2758 goto out;
2759 }
2760
2761 priv->base = ioremap(res_mem->start, resource_size(res_mem));
2762 if (priv->base == NULL) {
2763 ret = -ENOMEM;
2764 goto out_release_mem;
2765 }
2766
2767 priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2768 if (IS_ERR(priv->mac_clk)) {
2769 ret = PTR_ERR(priv->mac_clk);
2770 goto out_unmap;
2771 }
2772 clk_enable(priv->mac_clk);
2773
2774 priv->rx_chan = 0;
2775 priv->tx_chan = 1;
2776 spin_lock_init(&priv->rx_lock);
2777
2778 /* init rx timeout (used for oom) */
2779 init_timer(&priv->rx_timeout);
2780 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2781 priv->rx_timeout.data = (unsigned long)dev;
2782
2783 /* register netdevice */
2784 dev->netdev_ops = &bcm_enetsw_ops;
2785 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
7ad24ea4 2786 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
6f00a022
MB		 2787 SET_NETDEV_DEV(dev, &pdev->dev);
2788
2789 spin_lock_init(&priv->enetsw_mdio_lock);
2790
2791 ret = register_netdev(dev);
2792 if (ret)
2793 goto out_put_clk;
2794
2795 netif_carrier_off(dev);
2796 platform_set_drvdata(pdev, dev);
2797 priv->pdev = pdev;
2798 priv->net_dev = dev;
2799
2800 return 0;
2801
2802out_put_clk:
2803 clk_put(priv->mac_clk);
2804
2805out_unmap:
2806 iounmap(priv->base);
2807
2808out_release_mem:
2809 release_mem_region(res_mem->start, resource_size(res_mem));
2810out:
2811 free_netdev(dev);
2812 return ret;
2813}
2814
2815
2816/* exit func, stops hardware and unregisters netdevice */
2817static int bcm_enetsw_remove(struct platform_device *pdev)
2818{
2819 struct bcm_enet_priv *priv;
2820 struct net_device *dev;
2821 struct resource *res;
2822
2823 /* stop netdevice */
2824 dev = platform_get_drvdata(pdev);
2825 priv = netdev_priv(dev);
2826 unregister_netdev(dev);
2827
2828 /* release device resources */
2829 iounmap(priv->base);
2830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2831 release_mem_region(res->start, resource_size(res));
2832
6f00a022
MB		 2833 free_netdev(dev);
2834 return 0;
2835}
2836
2837struct platform_driver bcm63xx_enetsw_driver = {
2838 .probe = bcm_enetsw_probe,
2839 .remove = bcm_enetsw_remove,
2840 .driver = {
2841 .name = "bcm63xx_enetsw",
2842 .owner = THIS_MODULE,
2843 },
2844};
2845
2846/* reserve & remap memory space shared between all macs */
2847static int bcm_enet_shared_probe(struct platform_device *pdev)
2848{
2849 struct resource *res;
2850 void __iomem *p[3];
2851 unsigned int i;
2852
2853 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2854
2855 for (i = 0; i < 3; i++) {
2856 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2857 p[i] = devm_ioremap_resource(&pdev->dev, res);
646093a2
WY		 2858 if (IS_ERR(p[i]))
2859 return PTR_ERR(p[i]);
6f00a022
MB		 2860 }
2861
2862 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2863
2864 return 0;
2865}
2866
2867static int bcm_enet_shared_remove(struct platform_device *pdev)
2868{
2869 return 0;
2870}
2871
2872/* this "shared" driver is needed because both macs share a single
2873 * address space
2874 */
2875struct platform_driver bcm63xx_enet_shared_driver = {
2876 .probe = bcm_enet_shared_probe,
2877 .remove = bcm_enet_shared_remove,
2878 .driver = {
2879 .name = "bcm63xx_enet_shared",
2880 .owner = THIS_MODULE,
2881 },
2882};
2883
2884/* entry point */
2885static int __init bcm_enet_init(void)
2886{
2887 int ret;
2888
2889 ret = platform_driver_register(&bcm63xx_enet_shared_driver);
2890 if (ret)
2891 return ret;
2892
2893 ret = platform_driver_register(&bcm63xx_enet_driver);
2894 if (ret)
2895 platform_driver_unregister(&bcm63xx_enet_shared_driver);
2896
2897 ret = platform_driver_register(&bcm63xx_enetsw_driver);
2898 if (ret) {
2899 platform_driver_unregister(&bcm63xx_enet_driver);
2900 platform_driver_unregister(&bcm63xx_enet_shared_driver);
2901 }
9b1fc55a
MB		 2902
2903 return ret;
2904}
2905
2906static void __exit bcm_enet_exit(void)
2907{
2908 platform_driver_unregister(&bcm63xx_enet_driver);
6f00a022 2909 platform_driver_unregister(&bcm63xx_enetsw_driver);
9b1fc55a
MB		 2910 platform_driver_unregister(&bcm63xx_enet_shared_driver);
2911}
2912
2913
2914module_init(bcm_enet_init);
2915module_exit(bcm_enet_exit);
2916
2917MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2918MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2919MODULE_LICENSE("GPL");
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