]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/ethernet/broadcom/bcm63xx_enet.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: nb8800: Utilize phy_ethtool_nway_reset
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.c
CommitLineData
9b1fc55a
MB		 1/*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#include <linux/init.h>
539d3ee6 21#include <linux/interrupt.h>
9b1fc55a
MB		 22#include <linux/module.h>
23#include <linux/clk.h>
24#include <linux/etherdevice.h>
5a0e3ad6 25#include <linux/slab.h>
9b1fc55a
MB		 26#include <linux/delay.h>
27#include <linux/ethtool.h>
28#include <linux/crc32.h>
29#include <linux/err.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/if_vlan.h>
33
34#include <bcm63xx_dev_enet.h>
35#include "bcm63xx_enet.h"
36
37static char bcm_enet_driver_name[] = "bcm63xx_enet";
38static char bcm_enet_driver_version[] = "1.0";
39
40static int copybreak __read_mostly = 128;
41module_param(copybreak, int, 0);
42MODULE_PARM_DESC(copybreak, "Receive copy threshold");
43
0ae99b5f
MB		 44/* io registers memory shared between all devices */
45static void __iomem *bcm_enet_shared_base[3];
9b1fc55a
MB		 46
47/*
48 * io helpers to access mac registers
49 */
50static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
51{
52 return bcm_readl(priv->base + off);
53}
54
55static inline void enet_writel(struct bcm_enet_priv *priv,
56 u32 val, u32 off)
57{
58 bcm_writel(val, priv->base + off);
59}
60
61/*
6f00a022 62 * io helpers to access switch registers
9b1fc55a 63 */
6f00a022
MB		 64static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
65{
66 return bcm_readl(priv->base + off);
67}
68
69static inline void enetsw_writel(struct bcm_enet_priv *priv,
70 u32 val, u32 off)
71{
72 bcm_writel(val, priv->base + off);
73}
74
75static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
76{
77 return bcm_readw(priv->base + off);
78}
79
80static inline void enetsw_writew(struct bcm_enet_priv *priv,
81 u16 val, u32 off)
82{
83 bcm_writew(val, priv->base + off);
84}
85
86static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
87{
88 return bcm_readb(priv->base + off);
89}
90
91static inline void enetsw_writeb(struct bcm_enet_priv *priv,
92 u8 val, u32 off)
93{
94 bcm_writeb(val, priv->base + off);
95}
96
97
98/* io helpers to access shared registers */
9b1fc55a
MB		 99static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
100{
0ae99b5f 101 return bcm_readl(bcm_enet_shared_base[0] + off);
9b1fc55a
MB		 102}
103
104static inline void enet_dma_writel(struct bcm_enet_priv *priv,
105 u32 val, u32 off)
106{
0ae99b5f
MB		 107 bcm_writel(val, bcm_enet_shared_base[0] + off);
108}
109
3dc6475c 110static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 111{
3dc6475c
FF		 112 return bcm_readl(bcm_enet_shared_base[1] +
113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 114}
115
116static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
3dc6475c 117 u32 val, u32 off, int chan)
0ae99b5f 118{
3dc6475c
FF		 119 bcm_writel(val, bcm_enet_shared_base[1] +
120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
0ae99b5f
MB		 121}
122
3dc6475c 123static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
0ae99b5f 124{
3dc6475c 125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
0ae99b5f
MB		 126}
127
128static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
3dc6475c 129 u32 val, u32 off, int chan)
0ae99b5f 130{
3dc6475c 131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
9b1fc55a
MB		 132}
133
134/*
135 * write given data into mii register and wait for transfer to end
136 * with timeout (average measured transfer time is 25us)
137 */
138static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
139{
140 int limit;
141
142 /* make sure mii interrupt status is cleared */
143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
144
145 enet_writel(priv, data, ENET_MIIDATA_REG);
146 wmb();
147
148 /* busy wait on mii interrupt bit, with timeout */
149 limit = 1000;
150 do {
151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
152 break;
153 udelay(1);
ec1652af 154 } while (limit-- > 0);
9b1fc55a
MB		 155
156 return (limit < 0) ? 1 : 0;
157}
158
159/*
160 * MII internal read callback
161 */
162static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
163 int regnum)
164{
165 u32 tmp, val;
166
167 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
170 tmp |= ENET_MIIDATA_OP_READ_MASK;
171
172 if (do_mdio_op(priv, tmp))
173 return -1;
174
175 val = enet_readl(priv, ENET_MIIDATA_REG);
176 val &= 0xffff;
177 return val;
178}
179
180/*
181 * MII internal write callback
182 */
183static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
184 int regnum, u16 value)
185{
186 u32 tmp;
187
188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
192 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
193
194 (void)do_mdio_op(priv, tmp);
195 return 0;
196}
197
198/*
199 * MII read callback from phylib
200 */
201static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
202 int regnum)
203{
204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
205}
206
207/*
208 * MII write callback from phylib
209 */
210static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
211 int regnum, u16 value)
212{
213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
214}
215
216/*
217 * MII read callback from mii core
218 */
219static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
220 int regnum)
221{
222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
223}
224
225/*
226 * MII write callback from mii core
227 */
228static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
229 int regnum, int value)
230{
231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
232}
233
234/*
235 * refill rx queue
236 */
237static int bcm_enet_refill_rx(struct net_device *dev)
238{
239 struct bcm_enet_priv *priv;
240
241 priv = netdev_priv(dev);
242
243 while (priv->rx_desc_count < priv->rx_ring_size) {
244 struct bcm_enet_desc *desc;
245 struct sk_buff *skb;
246 dma_addr_t p;
247 int desc_idx;
248 u32 len_stat;
249
250 desc_idx = priv->rx_dirty_desc;
251 desc = &priv->rx_desc_cpu[desc_idx];
252
253 if (!priv->rx_skb[desc_idx]) {
254 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
255 if (!skb)
256 break;
257 priv->rx_skb[desc_idx] = skb;
9b1fc55a
MB		 258 p = dma_map_single(&priv->pdev->dev, skb->data,
259 priv->rx_skb_size,
260 DMA_FROM_DEVICE);
261 desc->address = p;
262 }
263
264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
265 len_stat |= DMADESC_OWNER_MASK;
266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
3dc6475c 267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 268 priv->rx_dirty_desc = 0;
269 } else {
270 priv->rx_dirty_desc++;
271 }
272 wmb();
273 desc->len_stat = len_stat;
274
275 priv->rx_desc_count++;
276
277 /* tell dma engine we allocated one buffer */
3dc6475c
FF		 278 if (priv->dma_has_sram)
279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
280 else
281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 282 }
283
284 /* If rx ring is still empty, set a timer to try allocating
285 * again at a later time. */
286 if (priv->rx_desc_count == 0 && netif_running(dev)) {
287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
288 priv->rx_timeout.expires = jiffies + HZ;
289 add_timer(&priv->rx_timeout);
290 }
291
292 return 0;
293}
294
295/*
296 * timer callback to defer refill rx queue in case we're OOM
297 */
298static void bcm_enet_refill_rx_timer(unsigned long data)
299{
300 struct net_device *dev;
301 struct bcm_enet_priv *priv;
302
303 dev = (struct net_device *)data;
304 priv = netdev_priv(dev);
305
306 spin_lock(&priv->rx_lock);
307 bcm_enet_refill_rx((struct net_device *)data);
308 spin_unlock(&priv->rx_lock);
309}
310
311/*
312 * extract packet from rx queue
313 */
314static int bcm_enet_receive_queue(struct net_device *dev, int budget)
315{
316 struct bcm_enet_priv *priv;
317 struct device *kdev;
318 int processed;
319
320 priv = netdev_priv(dev);
321 kdev = &priv->pdev->dev;
322 processed = 0;
323
324 /* don't scan ring further than number of refilled
325 * descriptor */
326 if (budget > priv->rx_desc_count)
327 budget = priv->rx_desc_count;
328
329 do {
330 struct bcm_enet_desc *desc;
331 struct sk_buff *skb;
332 int desc_idx;
333 u32 len_stat;
334 unsigned int len;
335
336 desc_idx = priv->rx_curr_desc;
337 desc = &priv->rx_desc_cpu[desc_idx];
338
339 /* make sure we actually read the descriptor status at
340 * each loop */
341 rmb();
342
343 len_stat = desc->len_stat;
344
345 /* break if dma ownership belongs to hw */
346 if (len_stat & DMADESC_OWNER_MASK)
347 break;
348
349 processed++;
350 priv->rx_curr_desc++;
351 if (priv->rx_curr_desc == priv->rx_ring_size)
352 priv->rx_curr_desc = 0;
353 priv->rx_desc_count--;
354
355 /* if the packet does not have start of packet _and_
356 * end of packet flag set, then just recycle it */
3dc6475c
FF		 357 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
358 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
c32d83c0 359 dev->stats.rx_dropped++;
9b1fc55a
MB		 360 continue;
361 }
362
363 /* recycle packet if it's marked as bad */
6f00a022
MB		 364 if (!priv->enet_is_sw &&
365 unlikely(len_stat & DMADESC_ERR_MASK)) {
c32d83c0 366 dev->stats.rx_errors++;
9b1fc55a
MB		 367
368 if (len_stat & DMADESC_OVSIZE_MASK)
c32d83c0 369 dev->stats.rx_length_errors++;
9b1fc55a 370 if (len_stat & DMADESC_CRC_MASK)
c32d83c0 371 dev->stats.rx_crc_errors++;
9b1fc55a 372 if (len_stat & DMADESC_UNDER_MASK)
c32d83c0 373 dev->stats.rx_frame_errors++;
9b1fc55a 374 if (len_stat & DMADESC_OV_MASK)
c32d83c0 375 dev->stats.rx_fifo_errors++;
9b1fc55a
MB		 376 continue;
377 }
378
379 /* valid packet */
380 skb = priv->rx_skb[desc_idx];
381 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
382 /* don't include FCS */
383 len -= 4;
384
385 if (len < copybreak) {
386 struct sk_buff *nskb;
387
45abfb10 388 nskb = napi_alloc_skb(&priv->napi, len);
9b1fc55a
MB		 389 if (!nskb) {
390 /* forget packet, just rearm desc */
c32d83c0 391 dev->stats.rx_dropped++;
9b1fc55a
MB		 392 continue;
393 }
394
9b1fc55a
MB		 395 dma_sync_single_for_cpu(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 memcpy(nskb->data, skb->data, len);
398 dma_sync_single_for_device(kdev, desc->address,
399 len, DMA_FROM_DEVICE);
400 skb = nskb;
401 } else {
402 dma_unmap_single(&priv->pdev->dev, desc->address,
403 priv->rx_skb_size, DMA_FROM_DEVICE);
404 priv->rx_skb[desc_idx] = NULL;
405 }
406
407 skb_put(skb, len);
9b1fc55a 408 skb->protocol = eth_type_trans(skb, dev);
c32d83c0
ED		 409 dev->stats.rx_packets++;
410 dev->stats.rx_bytes += len;
9b1fc55a
MB		 411 netif_receive_skb(skb);
412
413 } while (--budget > 0);
414
415 if (processed || !priv->rx_desc_count) {
416 bcm_enet_refill_rx(dev);
417
418 /* kick rx dma */
3dc6475c
FF		 419 enet_dmac_writel(priv, priv->dma_chan_en_mask,
420 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 421 }
422
423 return processed;
424}
425
426
427/*
428 * try to or force reclaim of transmitted buffers
429 */
430static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
431{
432 struct bcm_enet_priv *priv;
433 int released;
434
435 priv = netdev_priv(dev);
436 released = 0;
437
438 while (priv->tx_desc_count < priv->tx_ring_size) {
439 struct bcm_enet_desc *desc;
440 struct sk_buff *skb;
441
442 /* We run in a bh and fight against start_xmit, which
443 * is called with bh disabled */
444 spin_lock(&priv->tx_lock);
445
446 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
447
448 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
449 spin_unlock(&priv->tx_lock);
450 break;
451 }
452
453 /* ensure other field of the descriptor were not read
454 * before we checked ownership */
455 rmb();
456
457 skb = priv->tx_skb[priv->tx_dirty_desc];
458 priv->tx_skb[priv->tx_dirty_desc] = NULL;
459 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
460 DMA_TO_DEVICE);
461
462 priv->tx_dirty_desc++;
463 if (priv->tx_dirty_desc == priv->tx_ring_size)
464 priv->tx_dirty_desc = 0;
465 priv->tx_desc_count++;
466
467 spin_unlock(&priv->tx_lock);
468
469 if (desc->len_stat & DMADESC_UNDER_MASK)
c32d83c0 470 dev->stats.tx_errors++;
9b1fc55a
MB		 471
472 dev_kfree_skb(skb);
473 released++;
474 }
475
476 if (netif_queue_stopped(dev) && released)
477 netif_wake_queue(dev);
478
479 return released;
480}
481
482/*
483 * poll func, called by network core
484 */
485static int bcm_enet_poll(struct napi_struct *napi, int budget)
486{
487 struct bcm_enet_priv *priv;
488 struct net_device *dev;
cd33ccf5 489 int rx_work_done;
9b1fc55a
MB		 490
491 priv = container_of(napi, struct bcm_enet_priv, napi);
492 dev = priv->net_dev;
493
494 /* ack interrupts */
3dc6475c
FF		 495 enet_dmac_writel(priv, priv->dma_chan_int_mask,
496 ENETDMAC_IR, priv->rx_chan);
497 enet_dmac_writel(priv, priv->dma_chan_int_mask,
498 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 499
500 /* reclaim sent skb */
cd33ccf5 501 bcm_enet_tx_reclaim(dev, 0);
9b1fc55a
MB		 502
503 spin_lock(&priv->rx_lock);
504 rx_work_done = bcm_enet_receive_queue(dev, budget);
505 spin_unlock(&priv->rx_lock);
506
cd33ccf5
NS		 507 if (rx_work_done >= budget) {
508 /* rx queue is not yet empty/clean */
9b1fc55a
MB		 509 return rx_work_done;
510 }
511
512 /* no more packet in rx/tx queue, remove device from poll
513 * queue */
514 napi_complete(napi);
515
516 /* restore rx/tx interrupt */
3dc6475c
FF		 517 enet_dmac_writel(priv, priv->dma_chan_int_mask,
518 ENETDMAC_IRMASK, priv->rx_chan);
519 enet_dmac_writel(priv, priv->dma_chan_int_mask,
520 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 521
522 return rx_work_done;
523}
524
525/*
526 * mac interrupt handler
527 */
528static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
529{
530 struct net_device *dev;
531 struct bcm_enet_priv *priv;
532 u32 stat;
533
534 dev = dev_id;
535 priv = netdev_priv(dev);
536
537 stat = enet_readl(priv, ENET_IR_REG);
538 if (!(stat & ENET_IR_MIB))
539 return IRQ_NONE;
540
541 /* clear & mask interrupt */
542 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
543 enet_writel(priv, 0, ENET_IRMASK_REG);
544
545 /* read mib registers in workqueue */
546 schedule_work(&priv->mib_update_task);
547
548 return IRQ_HANDLED;
549}
550
551/*
552 * rx/tx dma interrupt handler
553 */
554static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
555{
556 struct net_device *dev;
557 struct bcm_enet_priv *priv;
558
559 dev = dev_id;
560 priv = netdev_priv(dev);
561
562 /* mask rx/tx interrupts */
3dc6475c
FF		 563 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
564 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 565
566 napi_schedule(&priv->napi);
567
568 return IRQ_HANDLED;
569}
570
571/*
572 * tx request callback
573 */
574static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
575{
576 struct bcm_enet_priv *priv;
577 struct bcm_enet_desc *desc;
578 u32 len_stat;
579 int ret;
580
581 priv = netdev_priv(dev);
582
583 /* lock against tx reclaim */
584 spin_lock(&priv->tx_lock);
585
586 /* make sure the tx hw queue is not full, should not happen
587 * since we stop queue before it's the case */
588 if (unlikely(!priv->tx_desc_count)) {
589 netif_stop_queue(dev);
590 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
591 "available?\n");
592 ret = NETDEV_TX_BUSY;
593 goto out_unlock;
594 }
595
6f00a022
MB		 596 /* pad small packets sent on a switch device */
597 if (priv->enet_is_sw && skb->len < 64) {
598 int needed = 64 - skb->len;
599 char *data;
600
601 if (unlikely(skb_tailroom(skb) < needed)) {
602 struct sk_buff *nskb;
603
604 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
605 if (!nskb) {
606 ret = NETDEV_TX_BUSY;
607 goto out_unlock;
608 }
609 dev_kfree_skb(skb);
610 skb = nskb;
611 }
612 data = skb_put(skb, needed);
613 memset(data, 0, needed);
614 }
615
9b1fc55a
MB		 616 /* point to the next available desc */
617 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
618 priv->tx_skb[priv->tx_curr_desc] = skb;
619
620 /* fill descriptor */
621 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
622 DMA_TO_DEVICE);
623
624 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
3dc6475c 625 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
9b1fc55a
MB		 626 DMADESC_APPEND_CRC |
627 DMADESC_OWNER_MASK;
628
629 priv->tx_curr_desc++;
630 if (priv->tx_curr_desc == priv->tx_ring_size) {
631 priv->tx_curr_desc = 0;
3dc6475c 632 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
9b1fc55a
MB		 633 }
634 priv->tx_desc_count--;
635
636 /* dma might be already polling, make sure we update desc
637 * fields in correct order */
638 wmb();
639 desc->len_stat = len_stat;
640 wmb();
641
642 /* kick tx dma */
3dc6475c
FF		 643 enet_dmac_writel(priv, priv->dma_chan_en_mask,
644 ENETDMAC_CHANCFG, priv->tx_chan);
9b1fc55a
MB		 645
646 /* stop queue if no more desc available */
647 if (!priv->tx_desc_count)
648 netif_stop_queue(dev);
649
c32d83c0
ED		 650 dev->stats.tx_bytes += skb->len;
651 dev->stats.tx_packets++;
9b1fc55a
MB		 652 ret = NETDEV_TX_OK;
653
654out_unlock:
655 spin_unlock(&priv->tx_lock);
656 return ret;
657}
658
659/*
660 * Change the interface's mac address.
661 */
662static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
663{
664 struct bcm_enet_priv *priv;
665 struct sockaddr *addr = p;
666 u32 val;
667
668 priv = netdev_priv(dev);
669 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
670
671 /* use perfect match register 0 to store my mac address */
672 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
673 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
674 enet_writel(priv, val, ENET_PML_REG(0));
675
676 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
677 val |= ENET_PMH_DATAVALID_MASK;
678 enet_writel(priv, val, ENET_PMH_REG(0));
679
680 return 0;
681}
682
683/*
25985edc 684 * Change rx mode (promiscuous/allmulti) and update multicast list
9b1fc55a
MB		 685 */
686static void bcm_enet_set_multicast_list(struct net_device *dev)
687{
688 struct bcm_enet_priv *priv;
22bedad3 689 struct netdev_hw_addr *ha;
9b1fc55a
MB		 690 u32 val;
691 int i;
692
693 priv = netdev_priv(dev);
694
695 val = enet_readl(priv, ENET_RXCFG_REG);
696
697 if (dev->flags & IFF_PROMISC)
698 val |= ENET_RXCFG_PROMISC_MASK;
699 else
700 val &= ~ENET_RXCFG_PROMISC_MASK;
701
702 /* only 3 perfect match registers left, first one is used for
703 * own mac address */
4cd24eaf 704 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
9b1fc55a
MB		 705 val |= ENET_RXCFG_ALLMCAST_MASK;
706 else
707 val &= ~ENET_RXCFG_ALLMCAST_MASK;
708
709 /* no need to set perfect match registers if we catch all
710 * multicast */
711 if (val & ENET_RXCFG_ALLMCAST_MASK) {
712 enet_writel(priv, val, ENET_RXCFG_REG);
713 return;
714 }
715
0ddf477b 716 i = 0;
22bedad3 717 netdev_for_each_mc_addr(ha, dev) {
9b1fc55a
MB		 718 u8 *dmi_addr;
719 u32 tmp;
720
0ddf477b
JP		 721 if (i == 3)
722 break;
9b1fc55a 723 /* update perfect match registers */
22bedad3 724 dmi_addr = ha->addr;
9b1fc55a
MB		 725 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
726 (dmi_addr[4] << 8) | dmi_addr[5];
727 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
728
729 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
730 tmp |= ENET_PMH_DATAVALID_MASK;
0ddf477b 731 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
9b1fc55a
MB		 732 }
733
734 for (; i < 3; i++) {
735 enet_writel(priv, 0, ENET_PML_REG(i + 1));
736 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
737 }
738
739 enet_writel(priv, val, ENET_RXCFG_REG);
740}
741
742/*
743 * set mac duplex parameters
744 */
745static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
746{
747 u32 val;
748
749 val = enet_readl(priv, ENET_TXCTL_REG);
750 if (fullduplex)
751 val |= ENET_TXCTL_FD_MASK;
752 else
753 val &= ~ENET_TXCTL_FD_MASK;
754 enet_writel(priv, val, ENET_TXCTL_REG);
755}
756
757/*
758 * set mac flow control parameters
759 */
760static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
761{
762 u32 val;
763
764 /* rx flow control (pause frame handling) */
765 val = enet_readl(priv, ENET_RXCFG_REG);
766 if (rx_en)
767 val |= ENET_RXCFG_ENFLOW_MASK;
768 else
769 val &= ~ENET_RXCFG_ENFLOW_MASK;
770 enet_writel(priv, val, ENET_RXCFG_REG);
771
3dc6475c
FF		 772 if (!priv->dma_has_sram)
773 return;
774
9b1fc55a
MB		 775 /* tx flow control (pause frame generation) */
776 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
777 if (tx_en)
778 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
779 else
780 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
781 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
782}
783
784/*
785 * link changed callback (from phylib)
786 */
787static void bcm_enet_adjust_phy_link(struct net_device *dev)
788{
789 struct bcm_enet_priv *priv;
790 struct phy_device *phydev;
791 int status_changed;
792
793 priv = netdev_priv(dev);
625eb866 794 phydev = dev->phydev;
9b1fc55a
MB		 795 status_changed = 0;
796
797 if (priv->old_link != phydev->link) {
798 status_changed = 1;
799 priv->old_link = phydev->link;
800 }
801
802 /* reflect duplex change in mac configuration */
803 if (phydev->link && phydev->duplex != priv->old_duplex) {
804 bcm_enet_set_duplex(priv,
805 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
806 status_changed = 1;
807 priv->old_duplex = phydev->duplex;
808 }
809
810 /* enable flow control if remote advertise it (trust phylib to
811 * check that duplex is full */
812 if (phydev->link && phydev->pause != priv->old_pause) {
813 int rx_pause_en, tx_pause_en;
814
815 if (phydev->pause) {
816 /* pause was advertised by lpa and us */
817 rx_pause_en = 1;
818 tx_pause_en = 1;
819 } else if (!priv->pause_auto) {
820 /* pause setting overrided by user */
821 rx_pause_en = priv->pause_rx;
822 tx_pause_en = priv->pause_tx;
823 } else {
824 rx_pause_en = 0;
825 tx_pause_en = 0;
826 }
827
828 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
829 status_changed = 1;
830 priv->old_pause = phydev->pause;
831 }
832
833 if (status_changed) {
834 pr_info("%s: link %s", dev->name, phydev->link ?
835 "UP" : "DOWN");
836 if (phydev->link)
837 pr_cont(" - %d/%s - flow control %s", phydev->speed,
838 DUPLEX_FULL == phydev->duplex ? "full" : "half",
839 phydev->pause == 1 ? "rx&tx" : "off");
840
841 pr_cont("\n");
842 }
843}
844
845/*
846 * link changed callback (if phylib is not used)
847 */
848static void bcm_enet_adjust_link(struct net_device *dev)
849{
850 struct bcm_enet_priv *priv;
851
852 priv = netdev_priv(dev);
853 bcm_enet_set_duplex(priv, priv->force_duplex_full);
854 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
855 netif_carrier_on(dev);
856
857 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
858 dev->name,
859 priv->force_speed_100 ? 100 : 10,
860 priv->force_duplex_full ? "full" : "half",
861 priv->pause_rx ? "rx" : "off",
862 priv->pause_tx ? "tx" : "off");
863}
864
865/*
866 * open callback, allocate dma rings & buffers and start rx operation
867 */
868static int bcm_enet_open(struct net_device *dev)
869{
870 struct bcm_enet_priv *priv;
871 struct sockaddr addr;
872 struct device *kdev;
873 struct phy_device *phydev;
874 int i, ret;
875 unsigned int size;
876 char phy_id[MII_BUS_ID_SIZE + 3];
877 void *p;
878 u32 val;
879
880 priv = netdev_priv(dev);
881 kdev = &priv->pdev->dev;
882
883 if (priv->has_phy) {
884 /* connect to PHY */
885 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
c56e9e2a 886 priv->mii_bus->id, priv->phy_id);
9b1fc55a 887
f9a8f83b 888 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
9b1fc55a
MB		 889 PHY_INTERFACE_MODE_MII);
890
891 if (IS_ERR(phydev)) {
892 dev_err(kdev, "could not attach to PHY\n");
893 return PTR_ERR(phydev);
894 }
895
896 /* mask with MAC supported features */
897 phydev->supported &= (SUPPORTED_10baseT_Half |
898 SUPPORTED_10baseT_Full |
899 SUPPORTED_100baseT_Half |
900 SUPPORTED_100baseT_Full |
901 SUPPORTED_Autoneg |
902 SUPPORTED_Pause |
903 SUPPORTED_MII);
904 phydev->advertising = phydev->supported;
905
906 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
907 phydev->advertising |= SUPPORTED_Pause;
908 else
909 phydev->advertising &= ~SUPPORTED_Pause;
910
2220943a 911 phy_attached_info(phydev);
9b1fc55a
MB		 912
913 priv->old_link = 0;
914 priv->old_duplex = -1;
915 priv->old_pause = -1;
9b1fc55a
MB		 916 }
917
918 /* mask all interrupts and request them */
919 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 920 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
921 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 922
923 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
924 if (ret)
925 goto out_phy_disconnect;
926
df9f1b9f 927 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
ab392d2d 928 dev->name, dev);
9b1fc55a
MB		 929 if (ret)
930 goto out_freeirq;
931
932 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 933 0, dev->name, dev);
9b1fc55a
MB		 934 if (ret)
935 goto out_freeirq_rx;
936
937 /* initialize perfect match registers */
938 for (i = 0; i < 4; i++) {
939 enet_writel(priv, 0, ENET_PML_REG(i));
940 enet_writel(priv, 0, ENET_PMH_REG(i));
941 }
942
943 /* write device mac address */
944 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
945 bcm_enet_set_mac_address(dev, &addr);
946
947 /* allocate rx dma ring */
948 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 949 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
9b1fc55a 950 if (!p) {
9b1fc55a
MB		 951 ret = -ENOMEM;
952 goto out_freeirq_tx;
953 }
954
9b1fc55a
MB		 955 priv->rx_desc_alloc_size = size;
956 priv->rx_desc_cpu = p;
957
958 /* allocate tx dma ring */
959 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
ede23fa8 960 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
9b1fc55a 961 if (!p) {
9b1fc55a
MB		 962 ret = -ENOMEM;
963 goto out_free_rx_ring;
964 }
965
9b1fc55a
MB		 966 priv->tx_desc_alloc_size = size;
967 priv->tx_desc_cpu = p;
968
b2adaca9 969 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 970 GFP_KERNEL);
971 if (!priv->tx_skb) {
9b1fc55a
MB		 972 ret = -ENOMEM;
973 goto out_free_tx_ring;
974 }
975
976 priv->tx_desc_count = priv->tx_ring_size;
977 priv->tx_dirty_desc = 0;
978 priv->tx_curr_desc = 0;
979 spin_lock_init(&priv->tx_lock);
980
981 /* init & fill rx ring with skbs */
b2adaca9 982 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
9b1fc55a
MB		 983 GFP_KERNEL);
984 if (!priv->rx_skb) {
9b1fc55a
MB		 985 ret = -ENOMEM;
986 goto out_free_tx_skb;
987 }
988
989 priv->rx_desc_count = 0;
990 priv->rx_dirty_desc = 0;
991 priv->rx_curr_desc = 0;
992
993 /* initialize flow control buffer allocation */
3dc6475c
FF		 994 if (priv->dma_has_sram)
995 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
996 ENETDMA_BUFALLOC_REG(priv->rx_chan));
997 else
998 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
999 ENETDMAC_BUFALLOC, priv->rx_chan);
9b1fc55a
MB		 1000
1001 if (bcm_enet_refill_rx(dev)) {
1002 dev_err(kdev, "cannot allocate rx skb queue\n");
1003 ret = -ENOMEM;
1004 goto out;
1005 }
1006
1007 /* write rx & tx ring addresses */
3dc6475c
FF		 1008 if (priv->dma_has_sram) {
1009 enet_dmas_writel(priv, priv->rx_desc_dma,
1010 ENETDMAS_RSTART_REG, priv->rx_chan);
1011 enet_dmas_writel(priv, priv->tx_desc_dma,
1012 ENETDMAS_RSTART_REG, priv->tx_chan);
1013 } else {
1014 enet_dmac_writel(priv, priv->rx_desc_dma,
1015 ENETDMAC_RSTART, priv->rx_chan);
1016 enet_dmac_writel(priv, priv->tx_desc_dma,
1017 ENETDMAC_RSTART, priv->tx_chan);
1018 }
9b1fc55a
MB		 1019
1020 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 1021 if (priv->dma_has_sram) {
1022 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1023 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1027 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1028 } else {
1029 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1030 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1031 }
9b1fc55a
MB		 1032
1033 /* set max rx/tx length */
1034 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1035 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1036
1037 /* set dma maximum burst len */
6f00a022 1038 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1039 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 1040 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 1041 ENETDMAC_MAXBURST, priv->tx_chan);
9b1fc55a
MB		 1042
1043 /* set correct transmit fifo watermark */
1044 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1045
1046 /* set flow control low/high threshold to 1/3 / 2/3 */
3dc6475c
FF		 1047 if (priv->dma_has_sram) {
1048 val = priv->rx_ring_size / 3;
1049 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1050 val = (priv->rx_ring_size * 2) / 3;
1051 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1052 } else {
1053 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1054 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1055 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1056 }
9b1fc55a
MB		 1057
1058 /* all set, enable mac and interrupts, start dma engine and
1059 * kick rx dma channel */
1060 wmb();
5e10d4a7
FF		 1061 val = enet_readl(priv, ENET_CTL_REG);
1062 val |= ENET_CTL_ENABLE_MASK;
1063 enet_writel(priv, val, ENET_CTL_REG);
9b1fc55a 1064 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
3dc6475c
FF		 1065 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066 ENETDMAC_CHANCFG, priv->rx_chan);
9b1fc55a
MB		 1067
1068 /* watch "mib counters about to overflow" interrupt */
1069 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072 /* watch "packet transferred" interrupt in rx and tx */
3dc6475c
FF		 1073 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074 ENETDMAC_IR, priv->rx_chan);
1075 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076 ENETDMAC_IR, priv->tx_chan);
9b1fc55a
MB		 1077
1078 /* make sure we enable napi before rx interrupt */
1079 napi_enable(&priv->napi);
1080
3dc6475c
FF		 1081 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082 ENETDMAC_IRMASK, priv->rx_chan);
1083 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084 ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 1085
1086 if (priv->has_phy)
625eb866 1087 phy_start(phydev);
9b1fc55a
MB		 1088 else
1089 bcm_enet_adjust_link(dev);
1090
1091 netif_start_queue(dev);
1092 return 0;
1093
1094out:
1095 for (i = 0; i < priv->rx_ring_size; i++) {
1096 struct bcm_enet_desc *desc;
1097
1098 if (!priv->rx_skb[i])
1099 continue;
1100
1101 desc = &priv->rx_desc_cpu[i];
1102 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103 DMA_FROM_DEVICE);
1104 kfree_skb(priv->rx_skb[i]);
1105 }
1106 kfree(priv->rx_skb);
1107
1108out_free_tx_skb:
1109 kfree(priv->tx_skb);
1110
1111out_free_tx_ring:
1112 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113 priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115out_free_rx_ring:
1116 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117 priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119out_freeirq_tx:
1120 free_irq(priv->irq_tx, dev);
1121
1122out_freeirq_rx:
1123 free_irq(priv->irq_rx, dev);
1124
1125out_freeirq:
1126 free_irq(dev->irq, dev);
1127
1128out_phy_disconnect:
4b75ca5a
AB		 1129 if (priv->has_phy)
1130 phy_disconnect(phydev);
9b1fc55a
MB		 1131
1132 return ret;
1133}
1134
1135/*
1136 * disable mac
1137 */
1138static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1139{
1140 int limit;
1141 u32 val;
1142
1143 val = enet_readl(priv, ENET_CTL_REG);
1144 val |= ENET_CTL_DISABLE_MASK;
1145 enet_writel(priv, val, ENET_CTL_REG);
1146
1147 limit = 1000;
1148 do {
1149 u32 val;
1150
1151 val = enet_readl(priv, ENET_CTL_REG);
1152 if (!(val & ENET_CTL_DISABLE_MASK))
1153 break;
1154 udelay(1);
1155 } while (limit--);
1156}
1157
1158/*
1159 * disable dma in given channel
1160 */
1161static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1162{
1163 int limit;
1164
3dc6475c 1165 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
9b1fc55a
MB		 1166
1167 limit = 1000;
1168 do {
1169 u32 val;
1170
3dc6475c 1171 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
0ae99b5f 1172 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
9b1fc55a
MB		 1173 break;
1174 udelay(1);
1175 } while (limit--);
1176}
1177
1178/*
1179 * stop callback
1180 */
1181static int bcm_enet_stop(struct net_device *dev)
1182{
1183 struct bcm_enet_priv *priv;
1184 struct device *kdev;
1185 int i;
1186
1187 priv = netdev_priv(dev);
1188 kdev = &priv->pdev->dev;
1189
1190 netif_stop_queue(dev);
1191 napi_disable(&priv->napi);
1192 if (priv->has_phy)
625eb866 1193 phy_stop(dev->phydev);
9b1fc55a
MB		 1194 del_timer_sync(&priv->rx_timeout);
1195
1196 /* mask all interrupts */
1197 enet_writel(priv, 0, ENET_IRMASK_REG);
3dc6475c
FF		 1198 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1199 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
9b1fc55a
MB		 1200
1201 /* make sure no mib update is scheduled */
23f333a2 1202 cancel_work_sync(&priv->mib_update_task);
9b1fc55a
MB		 1203
1204 /* disable dma & mac */
1205 bcm_enet_disable_dma(priv, priv->tx_chan);
1206 bcm_enet_disable_dma(priv, priv->rx_chan);
1207 bcm_enet_disable_mac(priv);
1208
1209 /* force reclaim of all tx buffers */
1210 bcm_enet_tx_reclaim(dev, 1);
1211
1212 /* free the rx skb ring */
1213 for (i = 0; i < priv->rx_ring_size; i++) {
1214 struct bcm_enet_desc *desc;
1215
1216 if (!priv->rx_skb[i])
1217 continue;
1218
1219 desc = &priv->rx_desc_cpu[i];
1220 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1221 DMA_FROM_DEVICE);
1222 kfree_skb(priv->rx_skb[i]);
1223 }
1224
1225 /* free remaining allocated memory */
1226 kfree(priv->rx_skb);
1227 kfree(priv->tx_skb);
1228 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1229 priv->rx_desc_cpu, priv->rx_desc_dma);
1230 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1231 priv->tx_desc_cpu, priv->tx_desc_dma);
1232 free_irq(priv->irq_tx, dev);
1233 free_irq(priv->irq_rx, dev);
1234 free_irq(dev->irq, dev);
1235
1236 /* release phy */
625eb866
PR		 1237 if (priv->has_phy)
1238 phy_disconnect(dev->phydev);
9b1fc55a
MB		 1239
1240 return 0;
1241}
1242
9b1fc55a
MB		 1243/*
1244 * ethtool callbacks
1245 */
1246struct bcm_enet_stats {
1247 char stat_string[ETH_GSTRING_LEN];
1248 int sizeof_stat;
1249 int stat_offset;
1250 int mib_reg;
1251};
1252
1253#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1254 offsetof(struct bcm_enet_priv, m)
c32d83c0
ED		 1255#define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1256 offsetof(struct net_device_stats, m)
9b1fc55a
MB		 1257
1258static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
c32d83c0
ED		 1259 { "rx_packets", DEV_STAT(rx_packets), -1 },
1260 { "tx_packets", DEV_STAT(tx_packets), -1 },
1261 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1262 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1263 { "rx_errors", DEV_STAT(rx_errors), -1 },
1264 { "tx_errors", DEV_STAT(tx_errors), -1 },
1265 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1266 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
9b1fc55a
MB		 1267
1268 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1269 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1270 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1271 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1272 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1273 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1274 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1275 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1276 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1277 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1278 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1279 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1280 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1281 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1282 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1283 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1284 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1285 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1286 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1287 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1288 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1289
1290 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1291 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1292 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1293 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1294 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1295 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1296 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1297 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1298 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1299 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1300 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1301 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1302 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1303 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1304 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1305 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1306 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1307 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1308 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1309 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1310 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1311 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1312
1313};
1314
6afc0d7a 1315#define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
9b1fc55a
MB		 1316
1317static const u32 unused_mib_regs[] = {
1318 ETH_MIB_TX_ALL_OCTETS,
1319 ETH_MIB_TX_ALL_PKTS,
1320 ETH_MIB_RX_ALL_OCTETS,
1321 ETH_MIB_RX_ALL_PKTS,
1322};
1323
1324
1325static void bcm_enet_get_drvinfo(struct net_device *netdev,
1326 struct ethtool_drvinfo *drvinfo)
1327{
7826d43f
JP		 1328 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1329 strlcpy(drvinfo->version, bcm_enet_driver_version,
1330 sizeof(drvinfo->version));
1331 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1332 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
9b1fc55a
MB		 1333}
1334
a3f92eea
FF		 1335static int bcm_enet_get_sset_count(struct net_device *netdev,
1336 int string_set)
9b1fc55a 1337{
a3f92eea
FF		 1338 switch (string_set) {
1339 case ETH_SS_STATS:
1340 return BCM_ENET_STATS_LEN;
1341 default:
1342 return -EINVAL;
1343 }
9b1fc55a
MB		 1344}
1345
1346static void bcm_enet_get_strings(struct net_device *netdev,
1347 u32 stringset, u8 *data)
1348{
1349 int i;
1350
1351 switch (stringset) {
1352 case ETH_SS_STATS:
1353 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1354 memcpy(data + i * ETH_GSTRING_LEN,
1355 bcm_enet_gstrings_stats[i].stat_string,
1356 ETH_GSTRING_LEN);
1357 }
1358 break;
1359 }
1360}
1361
1362static void update_mib_counters(struct bcm_enet_priv *priv)
1363{
1364 int i;
1365
1366 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1367 const struct bcm_enet_stats *s;
1368 u32 val;
1369 char *p;
1370
1371 s = &bcm_enet_gstrings_stats[i];
1372 if (s->mib_reg == -1)
1373 continue;
1374
1375 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1376 p = (char *)priv + s->stat_offset;
1377
1378 if (s->sizeof_stat == sizeof(u64))
1379 *(u64 *)p += val;
1380 else
1381 *(u32 *)p += val;
1382 }
1383
1384 /* also empty unused mib counters to make sure mib counter
1385 * overflow interrupt is cleared */
1386 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1387 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1388}
1389
1390static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1391{
1392 struct bcm_enet_priv *priv;
1393
1394 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1395 mutex_lock(&priv->mib_update_lock);
1396 update_mib_counters(priv);
1397 mutex_unlock(&priv->mib_update_lock);
1398
1399 /* reenable mib interrupt */
1400 if (netif_running(priv->net_dev))
1401 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1402}
1403
1404static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1405 struct ethtool_stats *stats,
1406 u64 *data)
1407{
1408 struct bcm_enet_priv *priv;
1409 int i;
1410
1411 priv = netdev_priv(netdev);
1412
1413 mutex_lock(&priv->mib_update_lock);
1414 update_mib_counters(priv);
1415
1416 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1417 const struct bcm_enet_stats *s;
1418 char *p;
1419
1420 s = &bcm_enet_gstrings_stats[i];
c32d83c0
ED		 1421 if (s->mib_reg == -1)
1422 p = (char *)&netdev->stats;
1423 else
1424 p = (char *)priv;
1425 p += s->stat_offset;
9b1fc55a
MB		 1426 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1427 *(u64 *)p : *(u32 *)p;
1428 }
1429 mutex_unlock(&priv->mib_update_lock);
1430}
1431
7260aac9
MB		 1432static int bcm_enet_nway_reset(struct net_device *dev)
1433{
1434 struct bcm_enet_priv *priv;
1435
1436 priv = netdev_priv(dev);
1437 if (priv->has_phy) {
625eb866 1438 if (!dev->phydev)
7260aac9 1439 return -ENODEV;
625eb866 1440 return genphy_restart_aneg(dev->phydev);
7260aac9
MB		 1441 }
1442
1443 return -EOPNOTSUPP;
1444}
1445
639cfa9e
PR		 1446static int bcm_enet_get_link_ksettings(struct net_device *dev,
1447 struct ethtool_link_ksettings *cmd)
9b1fc55a
MB		 1448{
1449 struct bcm_enet_priv *priv;
639cfa9e 1450 u32 supported, advertising;
9b1fc55a
MB		 1451
1452 priv = netdev_priv(dev);
1453
9b1fc55a 1454 if (priv->has_phy) {
625eb866 1455 if (!dev->phydev)
9b1fc55a 1456 return -ENODEV;
639cfa9e 1457 return phy_ethtool_ksettings_get(dev->phydev, cmd);
9b1fc55a 1458 } else {
639cfa9e
PR		 1459 cmd->base.autoneg = 0;
1460 cmd->base.speed = (priv->force_speed_100) ?
1461 SPEED_100 : SPEED_10;
1462 cmd->base.duplex = (priv->force_duplex_full) ?
9b1fc55a 1463 DUPLEX_FULL : DUPLEX_HALF;
639cfa9e 1464 supported = ADVERTISED_10baseT_Half |
9b1fc55a
MB		 1465 ADVERTISED_10baseT_Full |
1466 ADVERTISED_100baseT_Half |
1467 ADVERTISED_100baseT_Full;
639cfa9e
PR		 1468 advertising = 0;
1469 ethtool_convert_legacy_u32_to_link_mode(
1470 cmd->link_modes.supported, supported);
1471 ethtool_convert_legacy_u32_to_link_mode(
1472 cmd->link_modes.advertising, advertising);
1473 cmd->base.port = PORT_MII;
9b1fc55a
MB		 1474 }
1475 return 0;
1476}
1477
639cfa9e
PR		 1478static int bcm_enet_set_link_ksettings(struct net_device *dev,
1479 const struct ethtool_link_ksettings *cmd)
9b1fc55a
MB		 1480{
1481 struct bcm_enet_priv *priv;
1482
1483 priv = netdev_priv(dev);
1484 if (priv->has_phy) {
625eb866 1485 if (!dev->phydev)
9b1fc55a 1486 return -ENODEV;
639cfa9e 1487 return phy_ethtool_ksettings_set(dev->phydev, cmd);
9b1fc55a
MB		 1488 } else {
1489
639cfa9e
PR		 1490 if (cmd->base.autoneg ||
1491 (cmd->base.speed != SPEED_100 &&
1492 cmd->base.speed != SPEED_10) ||
1493 cmd->base.port != PORT_MII)
9b1fc55a
MB		 1494 return -EINVAL;
1495
639cfa9e
PR		 1496 priv->force_speed_100 =
1497 (cmd->base.speed == SPEED_100) ? 1 : 0;
1498 priv->force_duplex_full =
1499 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
9b1fc55a
MB		 1500
1501 if (netif_running(dev))
1502 bcm_enet_adjust_link(dev);
1503 return 0;
1504 }
1505}
1506
1507static void bcm_enet_get_ringparam(struct net_device *dev,
1508 struct ethtool_ringparam *ering)
1509{
1510 struct bcm_enet_priv *priv;
1511
1512 priv = netdev_priv(dev);
1513
1514 /* rx/tx ring is actually only limited by memory */
1515 ering->rx_max_pending = 8192;
1516 ering->tx_max_pending = 8192;
9b1fc55a
MB		 1517 ering->rx_pending = priv->rx_ring_size;
1518 ering->tx_pending = priv->tx_ring_size;
1519}
1520
1521static int bcm_enet_set_ringparam(struct net_device *dev,
1522 struct ethtool_ringparam *ering)
1523{
1524 struct bcm_enet_priv *priv;
1525 int was_running;
1526
1527 priv = netdev_priv(dev);
1528
1529 was_running = 0;
1530 if (netif_running(dev)) {
1531 bcm_enet_stop(dev);
1532 was_running = 1;
1533 }
1534
1535 priv->rx_ring_size = ering->rx_pending;
1536 priv->tx_ring_size = ering->tx_pending;
1537
1538 if (was_running) {
1539 int err;
1540
1541 err = bcm_enet_open(dev);
1542 if (err)
1543 dev_close(dev);
1544 else
1545 bcm_enet_set_multicast_list(dev);
1546 }
1547 return 0;
1548}
1549
1550static void bcm_enet_get_pauseparam(struct net_device *dev,
1551 struct ethtool_pauseparam *ecmd)
1552{
1553 struct bcm_enet_priv *priv;
1554
1555 priv = netdev_priv(dev);
1556 ecmd->autoneg = priv->pause_auto;
1557 ecmd->rx_pause = priv->pause_rx;
1558 ecmd->tx_pause = priv->pause_tx;
1559}
1560
1561static int bcm_enet_set_pauseparam(struct net_device *dev,
1562 struct ethtool_pauseparam *ecmd)
1563{
1564 struct bcm_enet_priv *priv;
1565
1566 priv = netdev_priv(dev);
1567
1568 if (priv->has_phy) {
1569 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1570 /* asymetric pause mode not supported,
1571 * actually possible but integrated PHY has RO
1572 * asym_pause bit */
1573 return -EINVAL;
1574 }
1575 } else {
1576 /* no pause autoneg on direct mii connection */
1577 if (ecmd->autoneg)
1578 return -EINVAL;
1579 }
1580
1581 priv->pause_auto = ecmd->autoneg;
1582 priv->pause_rx = ecmd->rx_pause;
1583 priv->pause_tx = ecmd->tx_pause;
1584
1585 return 0;
1586}
1587
1aff0cbe 1588static const struct ethtool_ops bcm_enet_ethtool_ops = {
9b1fc55a 1589 .get_strings = bcm_enet_get_strings,
a3f92eea 1590 .get_sset_count = bcm_enet_get_sset_count,
9b1fc55a 1591 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
7260aac9 1592 .nway_reset = bcm_enet_nway_reset,
9b1fc55a
MB		 1593 .get_drvinfo = bcm_enet_get_drvinfo,
1594 .get_link = ethtool_op_get_link,
1595 .get_ringparam = bcm_enet_get_ringparam,
1596 .set_ringparam = bcm_enet_set_ringparam,
1597 .get_pauseparam = bcm_enet_get_pauseparam,
1598 .set_pauseparam = bcm_enet_set_pauseparam,
639cfa9e
PR		 1599 .get_link_ksettings = bcm_enet_get_link_ksettings,
1600 .set_link_ksettings = bcm_enet_set_link_ksettings,
9b1fc55a
MB		 1601};
1602
1603static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1604{
1605 struct bcm_enet_priv *priv;
1606
1607 priv = netdev_priv(dev);
1608 if (priv->has_phy) {
625eb866 1609 if (!dev->phydev)
9b1fc55a 1610 return -ENODEV;
625eb866 1611 return phy_mii_ioctl(dev->phydev, rq, cmd);
9b1fc55a
MB		 1612 } else {
1613 struct mii_if_info mii;
1614
1615 mii.dev = dev;
1616 mii.mdio_read = bcm_enet_mdio_read_mii;
1617 mii.mdio_write = bcm_enet_mdio_write_mii;
1618 mii.phy_id = 0;
1619 mii.phy_id_mask = 0x3f;
1620 mii.reg_num_mask = 0x1f;
1621 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1622 }
1623}
1624
1625/*
e1c6dcca 1626 * adjust mtu, can't be called while device is running
9b1fc55a 1627 */
e1c6dcca 1628static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
9b1fc55a 1629{
e1c6dcca
JW		 1630 struct bcm_enet_priv *priv = netdev_priv(dev);
1631 int actual_mtu = new_mtu;
9b1fc55a 1632
e1c6dcca
JW		 1633 if (netif_running(dev))
1634 return -EBUSY;
9b1fc55a
MB		 1635
1636 /* add ethernet header + vlan tag size */
1637 actual_mtu += VLAN_ETH_HLEN;
1638
9b1fc55a
MB		 1639 /*
1640 * setup maximum size before we get overflow mark in
1641 * descriptor, note that this will not prevent reception of
1642 * big frames, they will be split into multiple buffers
1643 * anyway
1644 */
1645 priv->hw_mtu = actual_mtu;
1646
1647 /*
1648 * align rx buffer size to dma burst len, account FCS since
1649 * it's appended
1650 */
1651 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
6f00a022 1652 priv->dma_maxburst * 4);
9b1fc55a 1653
9b1fc55a
MB		 1654 dev->mtu = new_mtu;
1655 return 0;
1656}
1657
1658/*
1659 * preinit hardware to allow mii operation while device is down
1660 */
1661static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1662{
1663 u32 val;
1664 int limit;
1665
1666 /* make sure mac is disabled */
1667 bcm_enet_disable_mac(priv);
1668
1669 /* soft reset mac */
1670 val = ENET_CTL_SRESET_MASK;
1671 enet_writel(priv, val, ENET_CTL_REG);
1672 wmb();
1673
1674 limit = 1000;
1675 do {
1676 val = enet_readl(priv, ENET_CTL_REG);
1677 if (!(val & ENET_CTL_SRESET_MASK))
1678 break;
1679 udelay(1);
1680 } while (limit--);
1681
1682 /* select correct mii interface */
1683 val = enet_readl(priv, ENET_CTL_REG);
1684 if (priv->use_external_mii)
1685 val |= ENET_CTL_EPHYSEL_MASK;
1686 else
1687 val &= ~ENET_CTL_EPHYSEL_MASK;
1688 enet_writel(priv, val, ENET_CTL_REG);
1689
1690 /* turn on mdc clock */
1691 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1692 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1693
1694 /* set mib counters to self-clear when read */
1695 val = enet_readl(priv, ENET_MIBCTL_REG);
1696 val |= ENET_MIBCTL_RDCLEAR_MASK;
1697 enet_writel(priv, val, ENET_MIBCTL_REG);
1698}
1699
1700static const struct net_device_ops bcm_enet_ops = {
1701 .ndo_open = bcm_enet_open,
1702 .ndo_stop = bcm_enet_stop,
1703 .ndo_start_xmit = bcm_enet_start_xmit,
9b1fc55a 1704 .ndo_set_mac_address = bcm_enet_set_mac_address,
afc4b13d 1705 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
9b1fc55a
MB		 1706 .ndo_do_ioctl = bcm_enet_ioctl,
1707 .ndo_change_mtu = bcm_enet_change_mtu,
9b1fc55a
MB		 1708};
1709
1710/*
1711 * allocate netdevice, request register memory and register device.
1712 */
047fc566 1713static int bcm_enet_probe(struct platform_device *pdev)
9b1fc55a
MB		 1714{
1715 struct bcm_enet_priv *priv;
1716 struct net_device *dev;
1717 struct bcm63xx_enet_platform_data *pd;
1718 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1719 struct mii_bus *bus;
1720 const char *clk_name;
9b1fc55a
MB		 1721 int i, ret;
1722
1723 /* stop if shared driver failed, assume driver->probe will be
1724 * called in the same order we register devices (correct ?) */
0ae99b5f 1725 if (!bcm_enet_shared_base[0])
9b1fc55a
MB		 1726 return -ENODEV;
1727
9b1fc55a
MB		 1728 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1729 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1730 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
f607e059 1731 if (!res_irq || !res_irq_rx || !res_irq_tx)
9b1fc55a
MB		 1732 return -ENODEV;
1733
1734 ret = 0;
1735 dev = alloc_etherdev(sizeof(*priv));
1736 if (!dev)
1737 return -ENOMEM;
1738 priv = netdev_priv(dev);
9b1fc55a 1739
6f00a022
MB		 1740 priv->enet_is_sw = false;
1741 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1742
e1c6dcca 1743 ret = bcm_enet_change_mtu(dev, dev->mtu);
9b1fc55a
MB		 1744 if (ret)
1745 goto out;
1746
f607e059
JL		 1747 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1748 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1749 if (IS_ERR(priv->base)) {
1750 ret = PTR_ERR(priv->base);
1c03da05 1751 goto out;
9b1fc55a 1752 }
1c03da05 1753
9b1fc55a
MB		 1754 dev->irq = priv->irq = res_irq->start;
1755 priv->irq_rx = res_irq_rx->start;
1756 priv->irq_tx = res_irq_tx->start;
1757 priv->mac_id = pdev->id;
1758
1759 /* get rx & tx dma channel id for this mac */
1760 if (priv->mac_id == 0) {
1761 priv->rx_chan = 0;
1762 priv->tx_chan = 1;
1763 clk_name = "enet0";
1764 } else {
1765 priv->rx_chan = 2;
1766 priv->tx_chan = 3;
1767 clk_name = "enet1";
1768 }
1769
1770 priv->mac_clk = clk_get(&pdev->dev, clk_name);
1771 if (IS_ERR(priv->mac_clk)) {
1772 ret = PTR_ERR(priv->mac_clk);
1c03da05 1773 goto out;
9b1fc55a 1774 }
624e2d21 1775 clk_prepare_enable(priv->mac_clk);
9b1fc55a
MB		 1776
1777 /* initialize default and fetch platform data */
1778 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1779 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1780
cf0e7794 1781 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1782 if (pd) {
1783 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1784 priv->has_phy = pd->has_phy;
1785 priv->phy_id = pd->phy_id;
1786 priv->has_phy_interrupt = pd->has_phy_interrupt;
1787 priv->phy_interrupt = pd->phy_interrupt;
1788 priv->use_external_mii = !pd->use_internal_phy;
1789 priv->pause_auto = pd->pause_auto;
1790 priv->pause_rx = pd->pause_rx;
1791 priv->pause_tx = pd->pause_tx;
1792 priv->force_duplex_full = pd->force_duplex_full;
1793 priv->force_speed_100 = pd->force_speed_100;
3dc6475c
FF		 1794 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1795 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1796 priv->dma_chan_width = pd->dma_chan_width;
1797 priv->dma_has_sram = pd->dma_has_sram;
1798 priv->dma_desc_shift = pd->dma_desc_shift;
9b1fc55a
MB		 1799 }
1800
1801 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1802 /* using internal PHY, enable clock */
1803 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1804 if (IS_ERR(priv->phy_clk)) {
1805 ret = PTR_ERR(priv->phy_clk);
1806 priv->phy_clk = NULL;
1807 goto out_put_clk_mac;
1808 }
624e2d21 1809 clk_prepare_enable(priv->phy_clk);
9b1fc55a
MB		 1810 }
1811
1812 /* do minimal hardware init to be able to probe mii bus */
1813 bcm_enet_hw_preinit(priv);
1814
1815 /* MII bus registration */
1816 if (priv->has_phy) {
1817
1818 priv->mii_bus = mdiobus_alloc();
1819 if (!priv->mii_bus) {
1820 ret = -ENOMEM;
1821 goto out_uninit_hw;
1822 }
1823
1824 bus = priv->mii_bus;
1825 bus->name = "bcm63xx_enet MII bus";
1826 bus->parent = &pdev->dev;
1827 bus->priv = priv;
1828 bus->read = bcm_enet_mdio_read_phylib;
1829 bus->write = bcm_enet_mdio_write_phylib;
3e617506 1830 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
9b1fc55a
MB		 1831
1832 /* only probe bus where we think the PHY is, because
1833 * the mdio read operation return 0 instead of 0xffff
1834 * if a slave is not present on hw */
1835 bus->phy_mask = ~(1 << priv->phy_id);
1836
9b1fc55a
MB		 1837 if (priv->has_phy_interrupt)
1838 bus->irq[priv->phy_id] = priv->phy_interrupt;
9b1fc55a
MB		 1839
1840 ret = mdiobus_register(bus);
1841 if (ret) {
1842 dev_err(&pdev->dev, "unable to register mdio bus\n");
1843 goto out_free_mdio;
1844 }
1845 } else {
1846
1847 /* run platform code to initialize PHY device */
323b15b9 1848 if (pd && pd->mii_config &&
9b1fc55a
MB		 1849 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1850 bcm_enet_mdio_write_mii)) {
1851 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1852 goto out_uninit_hw;
1853 }
1854 }
1855
1856 spin_lock_init(&priv->rx_lock);
1857
1858 /* init rx timeout (used for oom) */
1859 init_timer(&priv->rx_timeout);
1860 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1861 priv->rx_timeout.data = (unsigned long)dev;
1862
1863 /* init the mib update lock&work */
1864 mutex_init(&priv->mib_update_lock);
1865 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1866
1867 /* zero mib counters */
1868 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1869 enet_writel(priv, 0, ENET_MIB_REG(i));
1870
1871 /* register netdevice */
1872 dev->netdev_ops = &bcm_enet_ops;
1873 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1874
7ad24ea4 1875 dev->ethtool_ops = &bcm_enet_ethtool_ops;
e1c6dcca
JW		 1876 /* MTU range: 46 - 2028 */
1877 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1878 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
9b1fc55a
MB		 1879 SET_NETDEV_DEV(dev, &pdev->dev);
1880
1881 ret = register_netdev(dev);
1882 if (ret)
1883 goto out_unregister_mdio;
1884
1885 netif_carrier_off(dev);
1886 platform_set_drvdata(pdev, dev);
1887 priv->pdev = pdev;
1888 priv->net_dev = dev;
1889
1890 return 0;
1891
1892out_unregister_mdio:
2a80b5e1 1893 if (priv->mii_bus)
9b1fc55a 1894 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1895
1896out_free_mdio:
1897 if (priv->mii_bus)
1898 mdiobus_free(priv->mii_bus);
1899
1900out_uninit_hw:
1901 /* turn off mdc clock */
1902 enet_writel(priv, 0, ENET_MIISC_REG);
1903 if (priv->phy_clk) {
624e2d21 1904 clk_disable_unprepare(priv->phy_clk);
9b1fc55a
MB		 1905 clk_put(priv->phy_clk);
1906 }
1907
1908out_put_clk_mac:
624e2d21 1909 clk_disable_unprepare(priv->mac_clk);
9b1fc55a 1910 clk_put(priv->mac_clk);
9b1fc55a
MB		 1911out:
1912 free_netdev(dev);
1913 return ret;
1914}
1915
1916
1917/*
1918 * exit func, stops hardware and unregisters netdevice
1919 */
047fc566 1920static int bcm_enet_remove(struct platform_device *pdev)
9b1fc55a
MB		 1921{
1922 struct bcm_enet_priv *priv;
1923 struct net_device *dev;
9b1fc55a
MB		 1924
1925 /* stop netdevice */
1926 dev = platform_get_drvdata(pdev);
1927 priv = netdev_priv(dev);
1928 unregister_netdev(dev);
1929
1930 /* turn off mdc clock */
1931 enet_writel(priv, 0, ENET_MIISC_REG);
1932
1933 if (priv->has_phy) {
1934 mdiobus_unregister(priv->mii_bus);
9b1fc55a
MB		 1935 mdiobus_free(priv->mii_bus);
1936 } else {
1937 struct bcm63xx_enet_platform_data *pd;
1938
cf0e7794 1939 pd = dev_get_platdata(&pdev->dev);
9b1fc55a
MB		 1940 if (pd && pd->mii_config)
1941 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1942 bcm_enet_mdio_write_mii);
1943 }
1944
9b1fc55a
MB		 1945 /* disable hw block clocks */
1946 if (priv->phy_clk) {
624e2d21 1947 clk_disable_unprepare(priv->phy_clk);
9b1fc55a
MB		 1948 clk_put(priv->phy_clk);
1949 }
624e2d21 1950 clk_disable_unprepare(priv->mac_clk);
9b1fc55a
MB		 1951 clk_put(priv->mac_clk);
1952
9b1fc55a
MB		 1953 free_netdev(dev);
1954 return 0;
1955}
1956
1957struct platform_driver bcm63xx_enet_driver = {
1958 .probe = bcm_enet_probe,
047fc566 1959 .remove = bcm_enet_remove,
9b1fc55a
MB		 1960 .driver = {
1961 .name = "bcm63xx_enet",
1962 .owner = THIS_MODULE,
1963 },
1964};
1965
1966/*
6f00a022 1967 * switch mii access callbacks
9b1fc55a 1968 */
6f00a022
MB		 1969static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1970 int ext, int phy_id, int location)
9b1fc55a 1971{
6f00a022
MB		 1972 u32 reg;
1973 int ret;
9b1fc55a 1974
6f00a022
MB		 1975 spin_lock_bh(&priv->enetsw_mdio_lock);
1976 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
9b1fc55a 1977
6f00a022
MB		 1978 reg = ENETSW_MDIOC_RD_MASK |
1979 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1980 (location << ENETSW_MDIOC_REG_SHIFT);
0ae99b5f 1981
6f00a022
MB		 1982 if (ext)
1983 reg |= ENETSW_MDIOC_EXT_MASK;
1c03da05 1984
6f00a022
MB		 1985 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1986 udelay(50);
1987 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1988 spin_unlock_bh(&priv->enetsw_mdio_lock);
1989 return ret;
9b1fc55a
MB		 1990}
1991
6f00a022
MB		 1992static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1993 int ext, int phy_id, int location,
1994 uint16_t data)
9b1fc55a 1995{
6f00a022
MB		 1996 u32 reg;
1997
1998 spin_lock_bh(&priv->enetsw_mdio_lock);
1999 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2000
2001 reg = ENETSW_MDIOC_WR_MASK |
2002 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2003 (location << ENETSW_MDIOC_REG_SHIFT);
2004
2005 if (ext)
2006 reg |= ENETSW_MDIOC_EXT_MASK;
2007
2008 reg |= data;
2009
2010 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2011 udelay(50);
2012 spin_unlock_bh(&priv->enetsw_mdio_lock);
2013}
2014
2015static inline int bcm_enet_port_is_rgmii(int portid)
2016{
2017 return portid >= ENETSW_RGMII_PORT0;
9b1fc55a
MB		 2018}
2019
2020/*
6f00a022 2021 * enet sw PHY polling
9b1fc55a 2022 */
6f00a022
MB		 2023static void swphy_poll_timer(unsigned long data)
2024{
2025 struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2026 unsigned int i;
2027
2028 for (i = 0; i < priv->num_ports; i++) {
2029 struct bcm63xx_enetsw_port *port;
aebd9947 2030 int val, j, up, advertise, lpa, speed, duplex, media;
6f00a022
MB		 2031 int external_phy = bcm_enet_port_is_rgmii(i);
2032 u8 override;
2033
2034 port = &priv->used_ports[i];
2035 if (!port->used)
2036 continue;
2037
2038 if (port->bypass_link)
2039 continue;
2040
2041 /* dummy read to clear */
2042 for (j = 0; j < 2; j++)
2043 val = bcmenet_sw_mdio_read(priv, external_phy,
2044 port->phy_id, MII_BMSR);
2045
2046 if (val == 0xffff)
2047 continue;
2048
2049 up = (val & BMSR_LSTATUS) ? 1 : 0;
2050 if (!(up ^ priv->sw_port_link[i]))
2051 continue;
2052
2053 priv->sw_port_link[i] = up;
2054
2055 /* link changed */
2056 if (!up) {
2057 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2058 port->name);
2059 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2060 ENETSW_PORTOV_REG(i));
2061 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2062 ENETSW_PTCTRL_TXDIS_MASK,
2063 ENETSW_PTCTRL_REG(i));
2064 continue;
2065 }
2066
2067 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2068 port->phy_id, MII_ADVERTISE);
2069
2070 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2071 MII_LPA);
2072
6f00a022
MB		 2073 /* figure out media and duplex from advertise and LPA values */
2074 media = mii_nway_result(lpa & advertise);
2075 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
aebd9947
SA		 2076
2077 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2078 speed = 100;
2079 else
2080 speed = 10;
2081
2082 if (val & BMSR_ESTATEN) {
2083 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2084 port->phy_id, MII_CTRL1000);
2085
2086 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2087 port->phy_id, MII_STAT1000);
2088
2089 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2090 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2091 speed = 1000;
2092 duplex = (lpa & LPA_1000FULL);
2093 }
6f00a022
MB		 2094 }
2095
2096 dev_info(&priv->pdev->dev,
2097 "link UP on %s, %dMbps, %s-duplex\n",
2098 port->name, speed, duplex ? "full" : "half");
2099
2100 override = ENETSW_PORTOV_ENABLE_MASK |
2101 ENETSW_PORTOV_LINKUP_MASK;
2102
2103 if (speed == 1000)
2104 override |= ENETSW_IMPOV_1000_MASK;
2105 else if (speed == 100)
2106 override |= ENETSW_IMPOV_100_MASK;
2107 if (duplex)
2108 override |= ENETSW_IMPOV_FDX_MASK;
2109
2110 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2111 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2112 }
2113
2114 priv->swphy_poll.expires = jiffies + HZ;
2115 add_timer(&priv->swphy_poll);
2116}
9b1fc55a
MB		 2117
2118/*
6f00a022 2119 * open callback, allocate dma rings & buffers and start rx operation
9b1fc55a 2120 */
6f00a022 2121static int bcm_enetsw_open(struct net_device *dev)
9b1fc55a 2122{
6f00a022
MB		 2123 struct bcm_enet_priv *priv;
2124 struct device *kdev;
2125 int i, ret;
2126 unsigned int size;
2127 void *p;
2128 u32 val;
9b1fc55a 2129
6f00a022
MB		 2130 priv = netdev_priv(dev);
2131 kdev = &priv->pdev->dev;
9b1fc55a 2132
6f00a022 2133 /* mask all interrupts and request them */
3dc6475c
FF		 2134 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2135 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2136
2137 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
df9f1b9f 2138 0, dev->name, dev);
9b1fc55a 2139 if (ret)
6f00a022
MB		 2140 goto out_freeirq;
2141
2142 if (priv->irq_tx != -1) {
2143 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
df9f1b9f 2144 0, dev->name, dev);
6f00a022
MB		 2145 if (ret)
2146 goto out_freeirq_rx;
2147 }
2148
2149 /* allocate rx dma ring */
2150 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2151 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2152 if (!p) {
2153 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2154 ret = -ENOMEM;
2155 goto out_freeirq_tx;
2156 }
2157
2158 memset(p, 0, size);
2159 priv->rx_desc_alloc_size = size;
2160 priv->rx_desc_cpu = p;
2161
2162 /* allocate tx dma ring */
2163 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2164 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2165 if (!p) {
2166 dev_err(kdev, "cannot allocate tx ring\n");
2167 ret = -ENOMEM;
2168 goto out_free_rx_ring;
2169 }
2170
2171 memset(p, 0, size);
2172 priv->tx_desc_alloc_size = size;
2173 priv->tx_desc_cpu = p;
2174
2175 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2176 GFP_KERNEL);
2177 if (!priv->tx_skb) {
2178 dev_err(kdev, "cannot allocate rx skb queue\n");
2179 ret = -ENOMEM;
2180 goto out_free_tx_ring;
2181 }
2182
2183 priv->tx_desc_count = priv->tx_ring_size;
2184 priv->tx_dirty_desc = 0;
2185 priv->tx_curr_desc = 0;
2186 spin_lock_init(&priv->tx_lock);
2187
2188 /* init & fill rx ring with skbs */
2189 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2190 GFP_KERNEL);
2191 if (!priv->rx_skb) {
2192 dev_err(kdev, "cannot allocate rx skb queue\n");
2193 ret = -ENOMEM;
2194 goto out_free_tx_skb;
2195 }
2196
2197 priv->rx_desc_count = 0;
2198 priv->rx_dirty_desc = 0;
2199 priv->rx_curr_desc = 0;
2200
2201 /* disable all ports */
2202 for (i = 0; i < priv->num_ports; i++) {
2203 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2204 ENETSW_PORTOV_REG(i));
2205 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2206 ENETSW_PTCTRL_TXDIS_MASK,
2207 ENETSW_PTCTRL_REG(i));
2208
2209 priv->sw_port_link[i] = 0;
2210 }
2211
2212 /* reset mib */
2213 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2214 val |= ENETSW_GMCR_RST_MIB_MASK;
2215 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2216 mdelay(1);
2217 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2218 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2219 mdelay(1);
2220
2221 /* force CPU port state */
2222 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2223 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2224 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2225
2226 /* enable switch forward engine */
2227 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2228 val |= ENETSW_SWMODE_FWD_EN_MASK;
2229 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2230
2231 /* enable jumbo on all ports */
2232 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2233 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2234
2235 /* initialize flow control buffer allocation */
2236 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2237 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2238
2239 if (bcm_enet_refill_rx(dev)) {
2240 dev_err(kdev, "cannot allocate rx skb queue\n");
2241 ret = -ENOMEM;
2242 goto out;
2243 }
2244
2245 /* write rx & tx ring addresses */
2246 enet_dmas_writel(priv, priv->rx_desc_dma,
3dc6475c 2247 ENETDMAS_RSTART_REG, priv->rx_chan);
6f00a022 2248 enet_dmas_writel(priv, priv->tx_desc_dma,
3dc6475c 2249 ENETDMAS_RSTART_REG, priv->tx_chan);
6f00a022
MB		 2250
2251 /* clear remaining state ram for rx & tx channel */
3dc6475c
FF		 2252 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2253 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2254 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2255 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2256 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2257 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
6f00a022
MB		 2258
2259 /* set dma maximum burst len */
2260 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2261 ENETDMAC_MAXBURST, priv->rx_chan);
6f00a022 2262 enet_dmac_writel(priv, priv->dma_maxburst,
3dc6475c 2263 ENETDMAC_MAXBURST, priv->tx_chan);
6f00a022
MB		 2264
2265 /* set flow control low/high threshold to 1/3 / 2/3 */
2266 val = priv->rx_ring_size / 3;
2267 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2268 val = (priv->rx_ring_size * 2) / 3;
2269 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2270
2271 /* all set, enable mac and interrupts, start dma engine and
2272 * kick rx dma channel
2273 */
2274 wmb();
2275 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2276 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
3dc6475c 2277 ENETDMAC_CHANCFG, priv->rx_chan);
6f00a022
MB		 2278
2279 /* watch "packet transferred" interrupt in rx and tx */
2280 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2281 ENETDMAC_IR, priv->rx_chan);
6f00a022 2282 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2283 ENETDMAC_IR, priv->tx_chan);
6f00a022
MB		 2284
2285 /* make sure we enable napi before rx interrupt */
2286 napi_enable(&priv->napi);
2287
2288 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2289 ENETDMAC_IRMASK, priv->rx_chan);
6f00a022 2290 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
3dc6475c 2291 ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2292
2293 netif_carrier_on(dev);
2294 netif_start_queue(dev);
2295
2296 /* apply override config for bypass_link ports here. */
2297 for (i = 0; i < priv->num_ports; i++) {
2298 struct bcm63xx_enetsw_port *port;
2299 u8 override;
2300 port = &priv->used_ports[i];
2301 if (!port->used)
2302 continue;
2303
2304 if (!port->bypass_link)
2305 continue;
2306
2307 override = ENETSW_PORTOV_ENABLE_MASK |
2308 ENETSW_PORTOV_LINKUP_MASK;
2309
2310 switch (port->force_speed) {
2311 case 1000:
2312 override |= ENETSW_IMPOV_1000_MASK;
2313 break;
2314 case 100:
2315 override |= ENETSW_IMPOV_100_MASK;
2316 break;
2317 case 10:
2318 break;
2319 default:
2320 pr_warn("invalid forced speed on port %s: assume 10\n",
2321 port->name);
2322 break;
2323 }
2324
2325 if (port->force_duplex_full)
2326 override |= ENETSW_IMPOV_FDX_MASK;
2327
2328
2329 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2330 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2331 }
2332
2333 /* start phy polling timer */
2334 init_timer(&priv->swphy_poll);
2335 priv->swphy_poll.function = swphy_poll_timer;
2336 priv->swphy_poll.data = (unsigned long)priv;
2337 priv->swphy_poll.expires = jiffies;
2338 add_timer(&priv->swphy_poll);
2339 return 0;
2340
2341out:
2342 for (i = 0; i < priv->rx_ring_size; i++) {
2343 struct bcm_enet_desc *desc;
2344
2345 if (!priv->rx_skb[i])
2346 continue;
2347
2348 desc = &priv->rx_desc_cpu[i];
2349 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2350 DMA_FROM_DEVICE);
2351 kfree_skb(priv->rx_skb[i]);
2352 }
2353 kfree(priv->rx_skb);
2354
2355out_free_tx_skb:
2356 kfree(priv->tx_skb);
2357
2358out_free_tx_ring:
2359 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2360 priv->tx_desc_cpu, priv->tx_desc_dma);
2361
2362out_free_rx_ring:
2363 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2364 priv->rx_desc_cpu, priv->rx_desc_dma);
2365
2366out_freeirq_tx:
2367 if (priv->irq_tx != -1)
2368 free_irq(priv->irq_tx, dev);
2369
2370out_freeirq_rx:
2371 free_irq(priv->irq_rx, dev);
2372
2373out_freeirq:
2374 return ret;
2375}
2376
2377/* stop callback */
2378static int bcm_enetsw_stop(struct net_device *dev)
2379{
2380 struct bcm_enet_priv *priv;
2381 struct device *kdev;
2382 int i;
2383
2384 priv = netdev_priv(dev);
2385 kdev = &priv->pdev->dev;
2386
2387 del_timer_sync(&priv->swphy_poll);
2388 netif_stop_queue(dev);
2389 napi_disable(&priv->napi);
2390 del_timer_sync(&priv->rx_timeout);
2391
2392 /* mask all interrupts */
3dc6475c
FF		 2393 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2394 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
6f00a022
MB		 2395
2396 /* disable dma & mac */
2397 bcm_enet_disable_dma(priv, priv->tx_chan);
2398 bcm_enet_disable_dma(priv, priv->rx_chan);
2399
2400 /* force reclaim of all tx buffers */
2401 bcm_enet_tx_reclaim(dev, 1);
2402
2403 /* free the rx skb ring */
2404 for (i = 0; i < priv->rx_ring_size; i++) {
2405 struct bcm_enet_desc *desc;
2406
2407 if (!priv->rx_skb[i])
2408 continue;
2409
2410 desc = &priv->rx_desc_cpu[i];
2411 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2412 DMA_FROM_DEVICE);
2413 kfree_skb(priv->rx_skb[i]);
2414 }
2415
2416 /* free remaining allocated memory */
2417 kfree(priv->rx_skb);
2418 kfree(priv->tx_skb);
2419 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2420 priv->rx_desc_cpu, priv->rx_desc_dma);
2421 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2422 priv->tx_desc_cpu, priv->tx_desc_dma);
2423 if (priv->irq_tx != -1)
2424 free_irq(priv->irq_tx, dev);
2425 free_irq(priv->irq_rx, dev);
2426
2427 return 0;
2428}
2429
2430/* try to sort out phy external status by walking the used_port field
2431 * in the bcm_enet_priv structure. in case the phy address is not
2432 * assigned to any physical port on the switch, assume it is external
2433 * (and yell at the user).
2434 */
2435static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2436{
2437 int i;
2438
2439 for (i = 0; i < priv->num_ports; ++i) {
2440 if (!priv->used_ports[i].used)
2441 continue;
2442 if (priv->used_ports[i].phy_id == phy_id)
2443 return bcm_enet_port_is_rgmii(i);
2444 }
2445
2446 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2447 phy_id);
2448 return 1;
2449}
2450
2451/* can't use bcmenet_sw_mdio_read directly as we need to sort out
2452 * external/internal status of the given phy_id first.
2453 */
2454static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2455 int location)
2456{
2457 struct bcm_enet_priv *priv;
2458
2459 priv = netdev_priv(dev);
2460 return bcmenet_sw_mdio_read(priv,
2461 bcm_enetsw_phy_is_external(priv, phy_id),
2462 phy_id, location);
2463}
2464
2465/* can't use bcmenet_sw_mdio_write directly as we need to sort out
2466 * external/internal status of the given phy_id first.
2467 */
2468static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2469 int location,
2470 int val)
2471{
2472 struct bcm_enet_priv *priv;
2473
2474 priv = netdev_priv(dev);
2475 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2476 phy_id, location, val);
2477}
2478
2479static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2480{
2481 struct mii_if_info mii;
2482
2483 mii.dev = dev;
2484 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2485 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2486 mii.phy_id = 0;
2487 mii.phy_id_mask = 0x3f;
2488 mii.reg_num_mask = 0x1f;
2489 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2490
2491}
2492
2493static const struct net_device_ops bcm_enetsw_ops = {
2494 .ndo_open = bcm_enetsw_open,
2495 .ndo_stop = bcm_enetsw_stop,
2496 .ndo_start_xmit = bcm_enet_start_xmit,
2497 .ndo_change_mtu = bcm_enet_change_mtu,
2498 .ndo_do_ioctl = bcm_enetsw_ioctl,
2499};
2500
2501
2502static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2503 { "rx_packets", DEV_STAT(rx_packets), -1 },
2504 { "tx_packets", DEV_STAT(tx_packets), -1 },
2505 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2506 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2507 { "rx_errors", DEV_STAT(rx_errors), -1 },
2508 { "tx_errors", DEV_STAT(tx_errors), -1 },
2509 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2510 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2511
2512 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2513 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2514 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2515 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2516 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2517 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2518 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2519 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2520 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2521 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2522 ETHSW_MIB_RX_1024_1522 },
2523 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2524 ETHSW_MIB_RX_1523_2047 },
2525 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2526 ETHSW_MIB_RX_2048_4095 },
2527 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2528 ETHSW_MIB_RX_4096_8191 },
2529 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2530 ETHSW_MIB_RX_8192_9728 },
2531 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2532 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2533 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2534 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2535 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2536
2537 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2538 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2539 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2540 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2541 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2542 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2543
2544};
2545
2546#define BCM_ENETSW_STATS_LEN \
2547 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2548
2549static void bcm_enetsw_get_strings(struct net_device *netdev,
2550 u32 stringset, u8 *data)
2551{
2552 int i;
2553
2554 switch (stringset) {
2555 case ETH_SS_STATS:
2556 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2557 memcpy(data + i * ETH_GSTRING_LEN,
2558 bcm_enetsw_gstrings_stats[i].stat_string,
2559 ETH_GSTRING_LEN);
2560 }
2561 break;
2562 }
2563}
2564
2565static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2566 int string_set)
2567{
2568 switch (string_set) {
2569 case ETH_SS_STATS:
2570 return BCM_ENETSW_STATS_LEN;
2571 default:
2572 return -EINVAL;
2573 }
2574}
2575
2576static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2577 struct ethtool_drvinfo *drvinfo)
2578{
2579 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2580 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2581 strncpy(drvinfo->fw_version, "N/A", 32);
2582 strncpy(drvinfo->bus_info, "bcm63xx", 32);
6f00a022
MB		 2583}
2584
2585static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2586 struct ethtool_stats *stats,
2587 u64 *data)
2588{
2589 struct bcm_enet_priv *priv;
2590 int i;
2591
2592 priv = netdev_priv(netdev);
2593
2594 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2595 const struct bcm_enet_stats *s;
2596 u32 lo, hi;
2597 char *p;
2598 int reg;
2599
2600 s = &bcm_enetsw_gstrings_stats[i];
2601
2602 reg = s->mib_reg;
2603 if (reg == -1)
2604 continue;
2605
2606 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2607 p = (char *)priv + s->stat_offset;
2608
2609 if (s->sizeof_stat == sizeof(u64)) {
2610 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2611 *(u64 *)p = ((u64)hi << 32 | lo);
2612 } else {
2613 *(u32 *)p = lo;
2614 }
2615 }
2616
2617 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2618 const struct bcm_enet_stats *s;
2619 char *p;
2620
2621 s = &bcm_enetsw_gstrings_stats[i];
2622
2623 if (s->mib_reg == -1)
2624 p = (char *)&netdev->stats + s->stat_offset;
2625 else
2626 p = (char *)priv + s->stat_offset;
2627
2628 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2629 *(u64 *)p : *(u32 *)p;
2630 }
2631}
2632
2633static void bcm_enetsw_get_ringparam(struct net_device *dev,
2634 struct ethtool_ringparam *ering)
2635{
2636 struct bcm_enet_priv *priv;
2637
2638 priv = netdev_priv(dev);
2639
2640 /* rx/tx ring is actually only limited by memory */
2641 ering->rx_max_pending = 8192;
2642 ering->tx_max_pending = 8192;
2643 ering->rx_mini_max_pending = 0;
2644 ering->rx_jumbo_max_pending = 0;
2645 ering->rx_pending = priv->rx_ring_size;
2646 ering->tx_pending = priv->tx_ring_size;
2647}
2648
2649static int bcm_enetsw_set_ringparam(struct net_device *dev,
2650 struct ethtool_ringparam *ering)
2651{
2652 struct bcm_enet_priv *priv;
2653 int was_running;
2654
2655 priv = netdev_priv(dev);
2656
2657 was_running = 0;
2658 if (netif_running(dev)) {
2659 bcm_enetsw_stop(dev);
2660 was_running = 1;
2661 }
2662
2663 priv->rx_ring_size = ering->rx_pending;
2664 priv->tx_ring_size = ering->tx_pending;
2665
2666 if (was_running) {
2667 int err;
2668
2669 err = bcm_enetsw_open(dev);
2670 if (err)
2671 dev_close(dev);
2672 }
2673 return 0;
2674}
2675
2676static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2677 .get_strings = bcm_enetsw_get_strings,
2678 .get_sset_count = bcm_enetsw_get_sset_count,
2679 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2680 .get_drvinfo = bcm_enetsw_get_drvinfo,
2681 .get_ringparam = bcm_enetsw_get_ringparam,
2682 .set_ringparam = bcm_enetsw_set_ringparam,
2683};
2684
2685/* allocate netdevice, request register memory and register device. */
2686static int bcm_enetsw_probe(struct platform_device *pdev)
2687{
2688 struct bcm_enet_priv *priv;
2689 struct net_device *dev;
2690 struct bcm63xx_enetsw_platform_data *pd;
2691 struct resource *res_mem;
2692 int ret, irq_rx, irq_tx;
2693
2694 /* stop if shared driver failed, assume driver->probe will be
2695 * called in the same order we register devices (correct ?)
2696 */
2697 if (!bcm_enet_shared_base[0])
2698 return -ENODEV;
2699
2700 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2701 irq_rx = platform_get_irq(pdev, 0);
2702 irq_tx = platform_get_irq(pdev, 1);
2703 if (!res_mem || irq_rx < 0)
2704 return -ENODEV;
2705
2706 ret = 0;
2707 dev = alloc_etherdev(sizeof(*priv));
2708 if (!dev)
2709 return -ENOMEM;
2710 priv = netdev_priv(dev);
2711 memset(priv, 0, sizeof(*priv));
2712
2713 /* initialize default and fetch platform data */
2714 priv->enet_is_sw = true;
2715 priv->irq_rx = irq_rx;
2716 priv->irq_tx = irq_tx;
2717 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2718 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2719 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2720
cf0e7794 2721 pd = dev_get_platdata(&pdev->dev);
6f00a022
MB		 2722 if (pd) {
2723 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2724 memcpy(priv->used_ports, pd->used_ports,
2725 sizeof(pd->used_ports));
2726 priv->num_ports = pd->num_ports;
3dc6475c
FF		 2727 priv->dma_has_sram = pd->dma_has_sram;
2728 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2729 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2730 priv->dma_chan_width = pd->dma_chan_width;
6f00a022
MB		 2731 }
2732
e1c6dcca 2733 ret = bcm_enet_change_mtu(dev, dev->mtu);
6f00a022
MB		 2734 if (ret)
2735 goto out;
2736
2737 if (!request_mem_region(res_mem->start, resource_size(res_mem),
2738 "bcm63xx_enetsw")) {
2739 ret = -EBUSY;
2740 goto out;
2741 }
2742
2743 priv->base = ioremap(res_mem->start, resource_size(res_mem));
2744 if (priv->base == NULL) {
2745 ret = -ENOMEM;
2746 goto out_release_mem;
2747 }
2748
2749 priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2750 if (IS_ERR(priv->mac_clk)) {
2751 ret = PTR_ERR(priv->mac_clk);
2752 goto out_unmap;
2753 }
2754 clk_enable(priv->mac_clk);
2755
2756 priv->rx_chan = 0;
2757 priv->tx_chan = 1;
2758 spin_lock_init(&priv->rx_lock);
2759
2760 /* init rx timeout (used for oom) */
2761 init_timer(&priv->rx_timeout);
2762 priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2763 priv->rx_timeout.data = (unsigned long)dev;
2764
2765 /* register netdevice */
2766 dev->netdev_ops = &bcm_enetsw_ops;
2767 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
7ad24ea4 2768 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
6f00a022
MB		 2769 SET_NETDEV_DEV(dev, &pdev->dev);
2770
2771 spin_lock_init(&priv->enetsw_mdio_lock);
2772
2773 ret = register_netdev(dev);
2774 if (ret)
2775 goto out_put_clk;
2776
2777 netif_carrier_off(dev);
2778 platform_set_drvdata(pdev, dev);
2779 priv->pdev = pdev;
2780 priv->net_dev = dev;
2781
2782 return 0;
2783
2784out_put_clk:
2785 clk_put(priv->mac_clk);
2786
2787out_unmap:
2788 iounmap(priv->base);
2789
2790out_release_mem:
2791 release_mem_region(res_mem->start, resource_size(res_mem));
2792out:
2793 free_netdev(dev);
2794 return ret;
2795}
2796
2797
2798/* exit func, stops hardware and unregisters netdevice */
2799static int bcm_enetsw_remove(struct platform_device *pdev)
2800{
2801 struct bcm_enet_priv *priv;
2802 struct net_device *dev;
2803 struct resource *res;
2804
2805 /* stop netdevice */
2806 dev = platform_get_drvdata(pdev);
2807 priv = netdev_priv(dev);
2808 unregister_netdev(dev);
2809
2810 /* release device resources */
2811 iounmap(priv->base);
2812 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2813 release_mem_region(res->start, resource_size(res));
2814
6f00a022
MB		 2815 free_netdev(dev);
2816 return 0;
2817}
2818
2819struct platform_driver bcm63xx_enetsw_driver = {
2820 .probe = bcm_enetsw_probe,
2821 .remove = bcm_enetsw_remove,
2822 .driver = {
2823 .name = "bcm63xx_enetsw",
2824 .owner = THIS_MODULE,
2825 },
2826};
2827
2828/* reserve & remap memory space shared between all macs */
2829static int bcm_enet_shared_probe(struct platform_device *pdev)
2830{
2831 struct resource *res;
2832 void __iomem *p[3];
2833 unsigned int i;
2834
2835 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2836
2837 for (i = 0; i < 3; i++) {
2838 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2839 p[i] = devm_ioremap_resource(&pdev->dev, res);
646093a2
WY		 2840 if (IS_ERR(p[i]))
2841 return PTR_ERR(p[i]);
6f00a022
MB		 2842 }
2843
2844 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2845
2846 return 0;
2847}
2848
2849static int bcm_enet_shared_remove(struct platform_device *pdev)
2850{
2851 return 0;
2852}
2853
2854/* this "shared" driver is needed because both macs share a single
2855 * address space
2856 */
2857struct platform_driver bcm63xx_enet_shared_driver = {
2858 .probe = bcm_enet_shared_probe,
2859 .remove = bcm_enet_shared_remove,
2860 .driver = {
2861 .name = "bcm63xx_enet_shared",
2862 .owner = THIS_MODULE,
2863 },
2864};
2865
0d1c744c
TR		 2866static struct platform_driver * const drivers[] = {
2867 &bcm63xx_enet_shared_driver,
2868 &bcm63xx_enet_driver,
2869 &bcm63xx_enetsw_driver,
2870};
2871
6f00a022
MB		 2872/* entry point */
2873static int __init bcm_enet_init(void)
2874{
0d1c744c 2875 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
9b1fc55a
MB		 2876}
2877
2878static void __exit bcm_enet_exit(void)
2879{
0d1c744c 2880 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
9b1fc55a
MB		 2881}
2882
2883
2884module_init(bcm_enet_init);
2885module_exit(bcm_enet_exit);
2886
2887MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2888MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2889MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror