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80105bef FF |
1 | /* |
2 | * Broadcom BCM7xxx System Port Ethernet MAC driver | |
3 | * | |
4 | * Copyright (C) 2014 Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/etherdevice.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_net.h> | |
22 | #include <linux/of_mdio.h> | |
23 | #include <linux/phy.h> | |
24 | #include <linux/phy_fixed.h> | |
25 | #include <net/ip.h> | |
26 | #include <net/ipv6.h> | |
27 | ||
28 | #include "bcmsysport.h" | |
29 | ||
30 | /* I/O accessors register helpers */ | |
31 | #define BCM_SYSPORT_IO_MACRO(name, offset) \ | |
32 | static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ | |
33 | { \ | |
34 | u32 reg = __raw_readl(priv->base + offset + off); \ | |
35 | return reg; \ | |
36 | } \ | |
37 | static inline void name##_writel(struct bcm_sysport_priv *priv, \ | |
38 | u32 val, u32 off) \ | |
39 | { \ | |
40 | __raw_writel(val, priv->base + offset + off); \ | |
41 | } \ | |
42 | ||
43 | BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); | |
44 | BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); | |
45 | BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); | |
46 | BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); | |
47 | BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET); | |
48 | BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); | |
49 | BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); | |
50 | BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); | |
51 | BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); | |
52 | BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); | |
53 | ||
54 | /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied | |
55 | * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. | |
56 | */ | |
57 | #define BCM_SYSPORT_INTR_L2(which) \ | |
58 | static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ | |
59 | u32 mask) \ | |
60 | { \ | |
61 | intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ | |
62 | priv->irq##which##_mask &= ~(mask); \ | |
63 | } \ | |
64 | static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ | |
65 | u32 mask) \ | |
66 | { \ | |
67 | intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ | |
68 | priv->irq##which##_mask |= (mask); \ | |
69 | } \ | |
70 | ||
71 | BCM_SYSPORT_INTR_L2(0) | |
72 | BCM_SYSPORT_INTR_L2(1) | |
73 | ||
74 | /* Register accesses to GISB/RBUS registers are expensive (few hundred | |
75 | * nanoseconds), so keep the check for 64-bits explicit here to save | |
76 | * one register write per-packet on 32-bits platforms. | |
77 | */ | |
78 | static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, | |
79 | void __iomem *d, | |
80 | dma_addr_t addr) | |
81 | { | |
82 | #ifdef CONFIG_PHYS_ADDR_T_64BIT | |
83 | __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK, | |
23acb2fc | 84 | d + DESC_ADDR_HI_STATUS_LEN); |
80105bef FF |
85 | #endif |
86 | __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO); | |
87 | } | |
88 | ||
89 | static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv, | |
23acb2fc FF |
90 | struct dma_desc *desc, |
91 | unsigned int port) | |
80105bef FF |
92 | { |
93 | /* Ports are latched, so write upper address first */ | |
94 | tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port)); | |
95 | tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port)); | |
96 | } | |
97 | ||
98 | /* Ethtool operations */ | |
99 | static int bcm_sysport_set_settings(struct net_device *dev, | |
100 | struct ethtool_cmd *cmd) | |
101 | { | |
102 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
103 | ||
104 | if (!netif_running(dev)) | |
105 | return -EINVAL; | |
106 | ||
107 | return phy_ethtool_sset(priv->phydev, cmd); | |
108 | } | |
109 | ||
110 | static int bcm_sysport_get_settings(struct net_device *dev, | |
23acb2fc | 111 | struct ethtool_cmd *cmd) |
80105bef FF |
112 | { |
113 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
114 | ||
115 | if (!netif_running(dev)) | |
116 | return -EINVAL; | |
117 | ||
118 | return phy_ethtool_gset(priv->phydev, cmd); | |
119 | } | |
120 | ||
121 | static int bcm_sysport_set_rx_csum(struct net_device *dev, | |
23acb2fc | 122 | netdev_features_t wanted) |
80105bef FF |
123 | { |
124 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
125 | u32 reg; | |
126 | ||
9d34c1cb | 127 | priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); |
80105bef | 128 | reg = rxchk_readl(priv, RXCHK_CONTROL); |
9d34c1cb | 129 | if (priv->rx_chk_en) |
80105bef FF |
130 | reg |= RXCHK_EN; |
131 | else | |
132 | reg &= ~RXCHK_EN; | |
133 | ||
134 | /* If UniMAC forwards CRC, we need to skip over it to get | |
135 | * a valid CHK bit to be set in the per-packet status word | |
136 | */ | |
9d34c1cb | 137 | if (priv->rx_chk_en && priv->crc_fwd) |
80105bef FF |
138 | reg |= RXCHK_SKIP_FCS; |
139 | else | |
140 | reg &= ~RXCHK_SKIP_FCS; | |
141 | ||
142 | rxchk_writel(priv, reg, RXCHK_CONTROL); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static int bcm_sysport_set_tx_csum(struct net_device *dev, | |
23acb2fc | 148 | netdev_features_t wanted) |
80105bef FF |
149 | { |
150 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
151 | u32 reg; | |
152 | ||
153 | /* Hardware transmit checksum requires us to enable the Transmit status | |
154 | * block prepended to the packet contents | |
155 | */ | |
156 | priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); | |
157 | reg = tdma_readl(priv, TDMA_CONTROL); | |
158 | if (priv->tsb_en) | |
159 | reg |= TSB_EN; | |
160 | else | |
161 | reg &= ~TSB_EN; | |
162 | tdma_writel(priv, reg, TDMA_CONTROL); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static int bcm_sysport_set_features(struct net_device *dev, | |
23acb2fc | 168 | netdev_features_t features) |
80105bef FF |
169 | { |
170 | netdev_features_t changed = features ^ dev->features; | |
171 | netdev_features_t wanted = dev->wanted_features; | |
172 | int ret = 0; | |
173 | ||
174 | if (changed & NETIF_F_RXCSUM) | |
175 | ret = bcm_sysport_set_rx_csum(dev, wanted); | |
176 | if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) | |
177 | ret = bcm_sysport_set_tx_csum(dev, wanted); | |
178 | ||
179 | return ret; | |
180 | } | |
181 | ||
182 | /* Hardware counters must be kept in sync because the order/offset | |
183 | * is important here (order in structure declaration = order in hardware) | |
184 | */ | |
185 | static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { | |
186 | /* general stats */ | |
187 | STAT_NETDEV(rx_packets), | |
188 | STAT_NETDEV(tx_packets), | |
189 | STAT_NETDEV(rx_bytes), | |
190 | STAT_NETDEV(tx_bytes), | |
191 | STAT_NETDEV(rx_errors), | |
192 | STAT_NETDEV(tx_errors), | |
193 | STAT_NETDEV(rx_dropped), | |
194 | STAT_NETDEV(tx_dropped), | |
195 | STAT_NETDEV(multicast), | |
196 | /* UniMAC RSV counters */ | |
197 | STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), | |
198 | STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), | |
199 | STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), | |
200 | STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), | |
201 | STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), | |
202 | STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), | |
203 | STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), | |
204 | STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), | |
205 | STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), | |
206 | STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), | |
207 | STAT_MIB_RX("rx_pkts", mib.rx.pkt), | |
208 | STAT_MIB_RX("rx_bytes", mib.rx.bytes), | |
209 | STAT_MIB_RX("rx_multicast", mib.rx.mca), | |
210 | STAT_MIB_RX("rx_broadcast", mib.rx.bca), | |
211 | STAT_MIB_RX("rx_fcs", mib.rx.fcs), | |
212 | STAT_MIB_RX("rx_control", mib.rx.cf), | |
213 | STAT_MIB_RX("rx_pause", mib.rx.pf), | |
214 | STAT_MIB_RX("rx_unknown", mib.rx.uo), | |
215 | STAT_MIB_RX("rx_align", mib.rx.aln), | |
216 | STAT_MIB_RX("rx_outrange", mib.rx.flr), | |
217 | STAT_MIB_RX("rx_code", mib.rx.cde), | |
218 | STAT_MIB_RX("rx_carrier", mib.rx.fcr), | |
219 | STAT_MIB_RX("rx_oversize", mib.rx.ovr), | |
220 | STAT_MIB_RX("rx_jabber", mib.rx.jbr), | |
221 | STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), | |
222 | STAT_MIB_RX("rx_good_pkts", mib.rx.pok), | |
223 | STAT_MIB_RX("rx_unicast", mib.rx.uc), | |
224 | STAT_MIB_RX("rx_ppp", mib.rx.ppp), | |
225 | STAT_MIB_RX("rx_crc", mib.rx.rcrc), | |
226 | /* UniMAC TSV counters */ | |
227 | STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), | |
228 | STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), | |
229 | STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), | |
230 | STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), | |
231 | STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), | |
232 | STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), | |
233 | STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), | |
234 | STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), | |
235 | STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), | |
236 | STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), | |
237 | STAT_MIB_TX("tx_pkts", mib.tx.pkts), | |
238 | STAT_MIB_TX("tx_multicast", mib.tx.mca), | |
239 | STAT_MIB_TX("tx_broadcast", mib.tx.bca), | |
240 | STAT_MIB_TX("tx_pause", mib.tx.pf), | |
241 | STAT_MIB_TX("tx_control", mib.tx.cf), | |
242 | STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), | |
243 | STAT_MIB_TX("tx_oversize", mib.tx.ovr), | |
244 | STAT_MIB_TX("tx_defer", mib.tx.drf), | |
245 | STAT_MIB_TX("tx_excess_defer", mib.tx.edf), | |
246 | STAT_MIB_TX("tx_single_col", mib.tx.scl), | |
247 | STAT_MIB_TX("tx_multi_col", mib.tx.mcl), | |
248 | STAT_MIB_TX("tx_late_col", mib.tx.lcl), | |
249 | STAT_MIB_TX("tx_excess_col", mib.tx.ecl), | |
250 | STAT_MIB_TX("tx_frags", mib.tx.frg), | |
251 | STAT_MIB_TX("tx_total_col", mib.tx.ncl), | |
252 | STAT_MIB_TX("tx_jabber", mib.tx.jbr), | |
253 | STAT_MIB_TX("tx_bytes", mib.tx.bytes), | |
254 | STAT_MIB_TX("tx_good_pkts", mib.tx.pok), | |
255 | STAT_MIB_TX("tx_unicast", mib.tx.uc), | |
256 | /* UniMAC RUNT counters */ | |
257 | STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), | |
258 | STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), | |
259 | STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), | |
260 | STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), | |
261 | /* RXCHK misc statistics */ | |
262 | STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), | |
263 | STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, | |
23acb2fc | 264 | RXCHK_OTHER_DISC_CNTR), |
80105bef FF |
265 | /* RBUF misc statistics */ |
266 | STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), | |
267 | STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), | |
268 | }; | |
269 | ||
270 | #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) | |
271 | ||
272 | static void bcm_sysport_get_drvinfo(struct net_device *dev, | |
23acb2fc | 273 | struct ethtool_drvinfo *info) |
80105bef FF |
274 | { |
275 | strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); | |
276 | strlcpy(info->version, "0.1", sizeof(info->version)); | |
277 | strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); | |
278 | info->n_stats = BCM_SYSPORT_STATS_LEN; | |
279 | } | |
280 | ||
281 | static u32 bcm_sysport_get_msglvl(struct net_device *dev) | |
282 | { | |
283 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
284 | ||
285 | return priv->msg_enable; | |
286 | } | |
287 | ||
288 | static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) | |
289 | { | |
290 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
291 | ||
292 | priv->msg_enable = enable; | |
293 | } | |
294 | ||
295 | static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) | |
296 | { | |
297 | switch (string_set) { | |
298 | case ETH_SS_STATS: | |
299 | return BCM_SYSPORT_STATS_LEN; | |
300 | default: | |
301 | return -EOPNOTSUPP; | |
302 | } | |
303 | } | |
304 | ||
305 | static void bcm_sysport_get_strings(struct net_device *dev, | |
23acb2fc | 306 | u32 stringset, u8 *data) |
80105bef FF |
307 | { |
308 | int i; | |
309 | ||
310 | switch (stringset) { | |
311 | case ETH_SS_STATS: | |
312 | for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { | |
313 | memcpy(data + i * ETH_GSTRING_LEN, | |
23acb2fc FF |
314 | bcm_sysport_gstrings_stats[i].stat_string, |
315 | ETH_GSTRING_LEN); | |
80105bef FF |
316 | } |
317 | break; | |
318 | default: | |
319 | break; | |
320 | } | |
321 | } | |
322 | ||
323 | static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) | |
324 | { | |
325 | int i, j = 0; | |
326 | ||
327 | for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { | |
328 | const struct bcm_sysport_stats *s; | |
329 | u8 offset = 0; | |
330 | u32 val = 0; | |
331 | char *p; | |
332 | ||
333 | s = &bcm_sysport_gstrings_stats[i]; | |
334 | switch (s->type) { | |
335 | case BCM_SYSPORT_STAT_NETDEV: | |
336 | continue; | |
337 | case BCM_SYSPORT_STAT_MIB_RX: | |
338 | case BCM_SYSPORT_STAT_MIB_TX: | |
339 | case BCM_SYSPORT_STAT_RUNT: | |
340 | if (s->type != BCM_SYSPORT_STAT_MIB_RX) | |
341 | offset = UMAC_MIB_STAT_OFFSET; | |
342 | val = umac_readl(priv, UMAC_MIB_START + j + offset); | |
343 | break; | |
344 | case BCM_SYSPORT_STAT_RXCHK: | |
345 | val = rxchk_readl(priv, s->reg_offset); | |
346 | if (val == ~0) | |
347 | rxchk_writel(priv, 0, s->reg_offset); | |
348 | break; | |
349 | case BCM_SYSPORT_STAT_RBUF: | |
350 | val = rbuf_readl(priv, s->reg_offset); | |
351 | if (val == ~0) | |
352 | rbuf_writel(priv, 0, s->reg_offset); | |
353 | break; | |
354 | } | |
355 | ||
356 | j += s->stat_sizeof; | |
357 | p = (char *)priv + s->stat_offset; | |
358 | *(u32 *)p = val; | |
359 | } | |
360 | ||
361 | netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); | |
362 | } | |
363 | ||
364 | static void bcm_sysport_get_stats(struct net_device *dev, | |
23acb2fc | 365 | struct ethtool_stats *stats, u64 *data) |
80105bef FF |
366 | { |
367 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
368 | int i; | |
369 | ||
370 | if (netif_running(dev)) | |
371 | bcm_sysport_update_mib_counters(priv); | |
372 | ||
373 | for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { | |
374 | const struct bcm_sysport_stats *s; | |
375 | char *p; | |
376 | ||
377 | s = &bcm_sysport_gstrings_stats[i]; | |
378 | if (s->type == BCM_SYSPORT_STAT_NETDEV) | |
379 | p = (char *)&dev->stats; | |
380 | else | |
381 | p = (char *)priv; | |
382 | p += s->stat_offset; | |
383 | data[i] = *(u32 *)p; | |
384 | } | |
385 | } | |
386 | ||
83e82f4c FF |
387 | static void bcm_sysport_get_wol(struct net_device *dev, |
388 | struct ethtool_wolinfo *wol) | |
389 | { | |
390 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
391 | u32 reg; | |
392 | ||
393 | wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; | |
394 | wol->wolopts = priv->wolopts; | |
395 | ||
396 | if (!(priv->wolopts & WAKE_MAGICSECURE)) | |
397 | return; | |
398 | ||
399 | /* Return the programmed SecureOn password */ | |
400 | reg = umac_readl(priv, UMAC_PSW_MS); | |
401 | put_unaligned_be16(reg, &wol->sopass[0]); | |
402 | reg = umac_readl(priv, UMAC_PSW_LS); | |
403 | put_unaligned_be32(reg, &wol->sopass[2]); | |
404 | } | |
405 | ||
406 | static int bcm_sysport_set_wol(struct net_device *dev, | |
23acb2fc | 407 | struct ethtool_wolinfo *wol) |
83e82f4c FF |
408 | { |
409 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
410 | struct device *kdev = &priv->pdev->dev; | |
411 | u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; | |
412 | ||
413 | if (!device_can_wakeup(kdev)) | |
414 | return -ENOTSUPP; | |
415 | ||
416 | if (wol->wolopts & ~supported) | |
417 | return -EINVAL; | |
418 | ||
419 | /* Program the SecureOn password */ | |
420 | if (wol->wolopts & WAKE_MAGICSECURE) { | |
421 | umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), | |
23acb2fc | 422 | UMAC_PSW_MS); |
83e82f4c | 423 | umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), |
23acb2fc | 424 | UMAC_PSW_LS); |
83e82f4c FF |
425 | } |
426 | ||
427 | /* Flag the device and relevant IRQ as wakeup capable */ | |
428 | if (wol->wolopts) { | |
429 | device_set_wakeup_enable(kdev, 1); | |
430 | enable_irq_wake(priv->wol_irq); | |
431 | priv->wol_irq_disabled = 0; | |
432 | } else { | |
433 | device_set_wakeup_enable(kdev, 0); | |
434 | /* Avoid unbalanced disable_irq_wake calls */ | |
435 | if (!priv->wol_irq_disabled) | |
436 | disable_irq_wake(priv->wol_irq); | |
437 | priv->wol_irq_disabled = 1; | |
438 | } | |
439 | ||
440 | priv->wolopts = wol->wolopts; | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
80105bef FF |
445 | static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) |
446 | { | |
447 | dev_kfree_skb_any(cb->skb); | |
448 | cb->skb = NULL; | |
449 | dma_unmap_addr_set(cb, dma_addr, 0); | |
450 | } | |
451 | ||
452 | static int bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, | |
453 | struct bcm_sysport_cb *cb) | |
454 | { | |
455 | struct device *kdev = &priv->pdev->dev; | |
456 | struct net_device *ndev = priv->netdev; | |
457 | dma_addr_t mapping; | |
458 | int ret; | |
459 | ||
460 | cb->skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); | |
461 | if (!cb->skb) { | |
462 | netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); | |
463 | return -ENOMEM; | |
464 | } | |
465 | ||
466 | mapping = dma_map_single(kdev, cb->skb->data, | |
23acb2fc | 467 | RX_BUF_LENGTH, DMA_FROM_DEVICE); |
80105bef FF |
468 | ret = dma_mapping_error(kdev, mapping); |
469 | if (ret) { | |
470 | bcm_sysport_free_cb(cb); | |
471 | netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); | |
472 | return ret; | |
473 | } | |
474 | ||
475 | dma_unmap_addr_set(cb, dma_addr, mapping); | |
476 | dma_desc_set_addr(priv, priv->rx_bd_assign_ptr, mapping); | |
477 | ||
478 | priv->rx_bd_assign_index++; | |
479 | priv->rx_bd_assign_index &= (priv->num_rx_bds - 1); | |
480 | priv->rx_bd_assign_ptr = priv->rx_bds + | |
481 | (priv->rx_bd_assign_index * DESC_SIZE); | |
482 | ||
483 | netif_dbg(priv, rx_status, ndev, "RX refill\n"); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) | |
489 | { | |
490 | struct bcm_sysport_cb *cb; | |
491 | int ret = 0; | |
492 | unsigned int i; | |
493 | ||
494 | for (i = 0; i < priv->num_rx_bds; i++) { | |
495 | cb = &priv->rx_cbs[priv->rx_bd_assign_index]; | |
496 | if (cb->skb) | |
497 | continue; | |
498 | ||
499 | ret = bcm_sysport_rx_refill(priv, cb); | |
500 | if (ret) | |
501 | break; | |
502 | } | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
507 | /* Poll the hardware for up to budget packets to process */ | |
508 | static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, | |
509 | unsigned int budget) | |
510 | { | |
511 | struct device *kdev = &priv->pdev->dev; | |
512 | struct net_device *ndev = priv->netdev; | |
513 | unsigned int processed = 0, to_process; | |
514 | struct bcm_sysport_cb *cb; | |
515 | struct sk_buff *skb; | |
516 | unsigned int p_index; | |
517 | u16 len, status; | |
3afc557d | 518 | struct bcm_rsb *rsb; |
80105bef FF |
519 | |
520 | /* Determine how much we should process since last call */ | |
521 | p_index = rdma_readl(priv, RDMA_PROD_INDEX); | |
522 | p_index &= RDMA_PROD_INDEX_MASK; | |
523 | ||
524 | if (p_index < priv->rx_c_index) | |
525 | to_process = (RDMA_CONS_INDEX_MASK + 1) - | |
526 | priv->rx_c_index + p_index; | |
527 | else | |
528 | to_process = p_index - priv->rx_c_index; | |
529 | ||
530 | netif_dbg(priv, rx_status, ndev, | |
23acb2fc FF |
531 | "p_index=%d rx_c_index=%d to_process=%d\n", |
532 | p_index, priv->rx_c_index, to_process); | |
80105bef | 533 | |
23acb2fc | 534 | while ((processed < to_process) && (processed < budget)) { |
80105bef FF |
535 | cb = &priv->rx_cbs[priv->rx_read_ptr]; |
536 | skb = cb->skb; | |
537 | dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), | |
23acb2fc | 538 | RX_BUF_LENGTH, DMA_FROM_DEVICE); |
80105bef FF |
539 | |
540 | /* Extract the Receive Status Block prepended */ | |
3afc557d | 541 | rsb = (struct bcm_rsb *)skb->data; |
80105bef FF |
542 | len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; |
543 | status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & | |
23acb2fc | 544 | DESC_STATUS_MASK; |
80105bef FF |
545 | |
546 | processed++; | |
547 | priv->rx_read_ptr++; | |
548 | if (priv->rx_read_ptr == priv->num_rx_bds) | |
549 | priv->rx_read_ptr = 0; | |
550 | ||
551 | netif_dbg(priv, rx_status, ndev, | |
23acb2fc FF |
552 | "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", |
553 | p_index, priv->rx_c_index, priv->rx_read_ptr, | |
554 | len, status); | |
80105bef FF |
555 | |
556 | if (unlikely(!skb)) { | |
557 | netif_err(priv, rx_err, ndev, "out of memory!\n"); | |
558 | ndev->stats.rx_dropped++; | |
559 | ndev->stats.rx_errors++; | |
560 | goto refill; | |
561 | } | |
562 | ||
563 | if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { | |
564 | netif_err(priv, rx_status, ndev, "fragmented packet!\n"); | |
565 | ndev->stats.rx_dropped++; | |
566 | ndev->stats.rx_errors++; | |
567 | bcm_sysport_free_cb(cb); | |
568 | goto refill; | |
569 | } | |
570 | ||
571 | if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { | |
572 | netif_err(priv, rx_err, ndev, "error packet\n"); | |
ad51c610 | 573 | if (status & RX_STATUS_OVFLOW) |
80105bef FF |
574 | ndev->stats.rx_over_errors++; |
575 | ndev->stats.rx_dropped++; | |
576 | ndev->stats.rx_errors++; | |
577 | bcm_sysport_free_cb(cb); | |
578 | goto refill; | |
579 | } | |
580 | ||
581 | skb_put(skb, len); | |
582 | ||
583 | /* Hardware validated our checksum */ | |
584 | if (likely(status & DESC_L4_CSUM)) | |
585 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
586 | ||
e0ea05d0 FF |
587 | /* Hardware pre-pends packets with 2bytes before Ethernet |
588 | * header plus we have the Receive Status Block, strip off all | |
589 | * of this from the SKB. | |
80105bef FF |
590 | */ |
591 | skb_pull(skb, sizeof(*rsb) + 2); | |
592 | len -= (sizeof(*rsb) + 2); | |
593 | ||
594 | /* UniMAC may forward CRC */ | |
595 | if (priv->crc_fwd) { | |
596 | skb_trim(skb, len - ETH_FCS_LEN); | |
597 | len -= ETH_FCS_LEN; | |
598 | } | |
599 | ||
600 | skb->protocol = eth_type_trans(skb, ndev); | |
601 | ndev->stats.rx_packets++; | |
602 | ndev->stats.rx_bytes += len; | |
603 | ||
604 | napi_gro_receive(&priv->napi, skb); | |
605 | refill: | |
606 | bcm_sysport_rx_refill(priv, cb); | |
607 | } | |
608 | ||
609 | return processed; | |
610 | } | |
611 | ||
612 | static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv, | |
23acb2fc FF |
613 | struct bcm_sysport_cb *cb, |
614 | unsigned int *bytes_compl, | |
615 | unsigned int *pkts_compl) | |
80105bef FF |
616 | { |
617 | struct device *kdev = &priv->pdev->dev; | |
618 | struct net_device *ndev = priv->netdev; | |
619 | ||
620 | if (cb->skb) { | |
621 | ndev->stats.tx_bytes += cb->skb->len; | |
622 | *bytes_compl += cb->skb->len; | |
623 | dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), | |
23acb2fc FF |
624 | dma_unmap_len(cb, dma_len), |
625 | DMA_TO_DEVICE); | |
80105bef FF |
626 | ndev->stats.tx_packets++; |
627 | (*pkts_compl)++; | |
628 | bcm_sysport_free_cb(cb); | |
629 | /* SKB fragment */ | |
630 | } else if (dma_unmap_addr(cb, dma_addr)) { | |
631 | ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len); | |
632 | dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), | |
23acb2fc | 633 | dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); |
80105bef FF |
634 | dma_unmap_addr_set(cb, dma_addr, 0); |
635 | } | |
636 | } | |
637 | ||
638 | /* Reclaim queued SKBs for transmission completion, lockless version */ | |
639 | static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, | |
640 | struct bcm_sysport_tx_ring *ring) | |
641 | { | |
642 | struct net_device *ndev = priv->netdev; | |
643 | unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs; | |
644 | unsigned int pkts_compl = 0, bytes_compl = 0; | |
645 | struct bcm_sysport_cb *cb; | |
646 | struct netdev_queue *txq; | |
647 | u32 hw_ind; | |
648 | ||
649 | txq = netdev_get_tx_queue(ndev, ring->index); | |
650 | ||
651 | /* Compute how many descriptors have been processed since last call */ | |
652 | hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); | |
653 | c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; | |
654 | ring->p_index = (hw_ind & RING_PROD_INDEX_MASK); | |
655 | ||
656 | last_c_index = ring->c_index; | |
657 | num_tx_cbs = ring->size; | |
658 | ||
659 | c_index &= (num_tx_cbs - 1); | |
660 | ||
661 | if (c_index >= last_c_index) | |
662 | last_tx_cn = c_index - last_c_index; | |
663 | else | |
664 | last_tx_cn = num_tx_cbs - last_c_index + c_index; | |
665 | ||
666 | netif_dbg(priv, tx_done, ndev, | |
23acb2fc FF |
667 | "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n", |
668 | ring->index, c_index, last_tx_cn, last_c_index); | |
80105bef FF |
669 | |
670 | while (last_tx_cn-- > 0) { | |
671 | cb = ring->cbs + last_c_index; | |
672 | bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl); | |
673 | ||
674 | ring->desc_count++; | |
675 | last_c_index++; | |
676 | last_c_index &= (num_tx_cbs - 1); | |
677 | } | |
678 | ||
679 | ring->c_index = c_index; | |
680 | ||
681 | if (netif_tx_queue_stopped(txq) && pkts_compl) | |
682 | netif_tx_wake_queue(txq); | |
683 | ||
684 | netif_dbg(priv, tx_done, ndev, | |
23acb2fc FF |
685 | "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", |
686 | ring->index, ring->c_index, pkts_compl, bytes_compl); | |
80105bef FF |
687 | |
688 | return pkts_compl; | |
689 | } | |
690 | ||
691 | /* Locked version of the per-ring TX reclaim routine */ | |
692 | static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, | |
693 | struct bcm_sysport_tx_ring *ring) | |
694 | { | |
695 | unsigned int released; | |
d8498088 | 696 | unsigned long flags; |
80105bef | 697 | |
d8498088 | 698 | spin_lock_irqsave(&ring->lock, flags); |
80105bef | 699 | released = __bcm_sysport_tx_reclaim(priv, ring); |
d8498088 | 700 | spin_unlock_irqrestore(&ring->lock, flags); |
80105bef FF |
701 | |
702 | return released; | |
703 | } | |
704 | ||
705 | static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) | |
706 | { | |
707 | struct bcm_sysport_tx_ring *ring = | |
708 | container_of(napi, struct bcm_sysport_tx_ring, napi); | |
709 | unsigned int work_done = 0; | |
710 | ||
711 | work_done = bcm_sysport_tx_reclaim(ring->priv, ring); | |
712 | ||
713 | if (work_done < budget) { | |
714 | napi_complete(napi); | |
715 | /* re-enable TX interrupt */ | |
716 | intrl2_1_mask_clear(ring->priv, BIT(ring->index)); | |
717 | } | |
718 | ||
719 | return work_done; | |
720 | } | |
721 | ||
722 | static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) | |
723 | { | |
724 | unsigned int q; | |
725 | ||
726 | for (q = 0; q < priv->netdev->num_tx_queues; q++) | |
727 | bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); | |
728 | } | |
729 | ||
730 | static int bcm_sysport_poll(struct napi_struct *napi, int budget) | |
731 | { | |
732 | struct bcm_sysport_priv *priv = | |
733 | container_of(napi, struct bcm_sysport_priv, napi); | |
734 | unsigned int work_done = 0; | |
735 | ||
736 | work_done = bcm_sysport_desc_rx(priv, budget); | |
737 | ||
738 | priv->rx_c_index += work_done; | |
739 | priv->rx_c_index &= RDMA_CONS_INDEX_MASK; | |
740 | rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); | |
741 | ||
742 | if (work_done < budget) { | |
743 | napi_complete(napi); | |
744 | /* re-enable RX interrupts */ | |
745 | intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); | |
746 | } | |
747 | ||
748 | return work_done; | |
749 | } | |
750 | ||
83e82f4c FF |
751 | static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) |
752 | { | |
753 | u32 reg; | |
754 | ||
755 | /* Stop monitoring MPD interrupt */ | |
756 | intrl2_0_mask_set(priv, INTRL2_0_MPD); | |
757 | ||
758 | /* Clear the MagicPacket detection logic */ | |
759 | reg = umac_readl(priv, UMAC_MPD_CTRL); | |
760 | reg &= ~MPD_EN; | |
761 | umac_writel(priv, reg, UMAC_MPD_CTRL); | |
762 | ||
763 | netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); | |
764 | } | |
80105bef FF |
765 | |
766 | /* RX and misc interrupt routine */ | |
767 | static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) | |
768 | { | |
769 | struct net_device *dev = dev_id; | |
770 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
771 | ||
772 | priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & | |
773 | ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); | |
774 | intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); | |
775 | ||
776 | if (unlikely(priv->irq0_stat == 0)) { | |
777 | netdev_warn(priv->netdev, "spurious RX interrupt\n"); | |
778 | return IRQ_NONE; | |
779 | } | |
780 | ||
781 | if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { | |
782 | if (likely(napi_schedule_prep(&priv->napi))) { | |
783 | /* disable RX interrupts */ | |
784 | intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); | |
785 | __napi_schedule(&priv->napi); | |
786 | } | |
787 | } | |
788 | ||
789 | /* TX ring is full, perform a full reclaim since we do not know | |
790 | * which one would trigger this interrupt | |
791 | */ | |
792 | if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) | |
793 | bcm_sysport_tx_reclaim_all(priv); | |
794 | ||
83e82f4c FF |
795 | if (priv->irq0_stat & INTRL2_0_MPD) { |
796 | netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n"); | |
797 | bcm_sysport_resume_from_wol(priv); | |
798 | } | |
799 | ||
80105bef FF |
800 | return IRQ_HANDLED; |
801 | } | |
802 | ||
803 | /* TX interrupt service routine */ | |
804 | static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) | |
805 | { | |
806 | struct net_device *dev = dev_id; | |
807 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
808 | struct bcm_sysport_tx_ring *txr; | |
809 | unsigned int ring; | |
810 | ||
811 | priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & | |
812 | ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); | |
813 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); | |
814 | ||
815 | if (unlikely(priv->irq1_stat == 0)) { | |
816 | netdev_warn(priv->netdev, "spurious TX interrupt\n"); | |
817 | return IRQ_NONE; | |
818 | } | |
819 | ||
820 | for (ring = 0; ring < dev->num_tx_queues; ring++) { | |
821 | if (!(priv->irq1_stat & BIT(ring))) | |
822 | continue; | |
823 | ||
824 | txr = &priv->tx_rings[ring]; | |
825 | ||
826 | if (likely(napi_schedule_prep(&txr->napi))) { | |
827 | intrl2_1_mask_set(priv, BIT(ring)); | |
828 | __napi_schedule(&txr->napi); | |
829 | } | |
830 | } | |
831 | ||
832 | return IRQ_HANDLED; | |
833 | } | |
834 | ||
83e82f4c FF |
835 | static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) |
836 | { | |
837 | struct bcm_sysport_priv *priv = dev_id; | |
838 | ||
839 | pm_wakeup_event(&priv->pdev->dev, 0); | |
840 | ||
841 | return IRQ_HANDLED; | |
842 | } | |
843 | ||
80105bef FF |
844 | static int bcm_sysport_insert_tsb(struct sk_buff *skb, struct net_device *dev) |
845 | { | |
846 | struct sk_buff *nskb; | |
3afc557d | 847 | struct bcm_tsb *tsb; |
80105bef FF |
848 | u32 csum_info; |
849 | u8 ip_proto; | |
850 | u16 csum_start; | |
851 | u16 ip_ver; | |
852 | ||
853 | /* Re-allocate SKB if needed */ | |
854 | if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { | |
855 | nskb = skb_realloc_headroom(skb, sizeof(*tsb)); | |
856 | dev_kfree_skb(skb); | |
857 | if (!nskb) { | |
858 | dev->stats.tx_errors++; | |
859 | dev->stats.tx_dropped++; | |
860 | return -ENOMEM; | |
861 | } | |
862 | skb = nskb; | |
863 | } | |
864 | ||
3afc557d | 865 | tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb)); |
80105bef FF |
866 | /* Zero-out TSB by default */ |
867 | memset(tsb, 0, sizeof(*tsb)); | |
868 | ||
869 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
870 | ip_ver = htons(skb->protocol); | |
871 | switch (ip_ver) { | |
872 | case ETH_P_IP: | |
873 | ip_proto = ip_hdr(skb)->protocol; | |
874 | break; | |
875 | case ETH_P_IPV6: | |
876 | ip_proto = ipv6_hdr(skb)->nexthdr; | |
877 | break; | |
878 | default: | |
879 | return 0; | |
880 | } | |
881 | ||
882 | /* Get the checksum offset and the L4 (transport) offset */ | |
883 | csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); | |
884 | csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; | |
885 | csum_info |= (csum_start << L4_PTR_SHIFT); | |
886 | ||
887 | if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { | |
888 | csum_info |= L4_LENGTH_VALID; | |
889 | if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) | |
890 | csum_info |= L4_UDP; | |
23acb2fc | 891 | } else { |
80105bef | 892 | csum_info = 0; |
23acb2fc | 893 | } |
80105bef FF |
894 | |
895 | tsb->l4_ptr_dest_map = csum_info; | |
896 | } | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, | |
902 | struct net_device *dev) | |
903 | { | |
904 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
905 | struct device *kdev = &priv->pdev->dev; | |
906 | struct bcm_sysport_tx_ring *ring; | |
907 | struct bcm_sysport_cb *cb; | |
908 | struct netdev_queue *txq; | |
909 | struct dma_desc *desc; | |
dab531b4 | 910 | unsigned int skb_len; |
d8498088 | 911 | unsigned long flags; |
80105bef FF |
912 | dma_addr_t mapping; |
913 | u32 len_status; | |
914 | u16 queue; | |
915 | int ret; | |
916 | ||
917 | queue = skb_get_queue_mapping(skb); | |
918 | txq = netdev_get_tx_queue(dev, queue); | |
919 | ring = &priv->tx_rings[queue]; | |
920 | ||
d8498088 FF |
921 | /* lock against tx reclaim in BH context and TX ring full interrupt */ |
922 | spin_lock_irqsave(&ring->lock, flags); | |
80105bef FF |
923 | if (unlikely(ring->desc_count == 0)) { |
924 | netif_tx_stop_queue(txq); | |
925 | netdev_err(dev, "queue %d awake and ring full!\n", queue); | |
926 | ret = NETDEV_TX_BUSY; | |
927 | goto out; | |
928 | } | |
929 | ||
930 | /* Insert TSB and checksum infos */ | |
931 | if (priv->tsb_en) { | |
932 | ret = bcm_sysport_insert_tsb(skb, dev); | |
933 | if (ret) { | |
934 | ret = NETDEV_TX_OK; | |
935 | goto out; | |
936 | } | |
937 | } | |
938 | ||
dab531b4 FF |
939 | /* The Ethernet switch we are interfaced with needs packets to be at |
940 | * least 64 bytes (including FCS) otherwise they will be discarded when | |
941 | * they enter the switch port logic. When Broadcom tags are enabled, we | |
942 | * need to make sure that packets are at least 68 bytes | |
943 | * (including FCS and tag) because the length verification is done after | |
944 | * the Broadcom tag is stripped off the ingress packet. | |
945 | */ | |
946 | if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { | |
947 | ret = NETDEV_TX_OK; | |
948 | goto out; | |
949 | } | |
950 | ||
951 | skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ? | |
952 | ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len; | |
953 | ||
954 | mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); | |
80105bef FF |
955 | if (dma_mapping_error(kdev, mapping)) { |
956 | netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", | |
23acb2fc | 957 | skb->data, skb_len); |
80105bef FF |
958 | ret = NETDEV_TX_OK; |
959 | goto out; | |
960 | } | |
961 | ||
962 | /* Remember the SKB for future freeing */ | |
963 | cb = &ring->cbs[ring->curr_desc]; | |
964 | cb->skb = skb; | |
965 | dma_unmap_addr_set(cb, dma_addr, mapping); | |
dab531b4 | 966 | dma_unmap_len_set(cb, dma_len, skb_len); |
80105bef FF |
967 | |
968 | /* Fetch a descriptor entry from our pool */ | |
969 | desc = ring->desc_cpu; | |
970 | ||
971 | desc->addr_lo = lower_32_bits(mapping); | |
972 | len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; | |
dab531b4 | 973 | len_status |= (skb_len << DESC_LEN_SHIFT); |
80105bef | 974 | len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << |
23acb2fc | 975 | DESC_STATUS_SHIFT; |
80105bef FF |
976 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
977 | len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); | |
978 | ||
979 | ring->curr_desc++; | |
980 | if (ring->curr_desc == ring->size) | |
981 | ring->curr_desc = 0; | |
982 | ring->desc_count--; | |
983 | ||
984 | /* Ensure write completion of the descriptor status/length | |
985 | * in DRAM before the System Port WRITE_PORT register latches | |
986 | * the value | |
987 | */ | |
988 | wmb(); | |
989 | desc->addr_status_len = len_status; | |
990 | wmb(); | |
991 | ||
992 | /* Write this descriptor address to the RING write port */ | |
993 | tdma_port_write_desc_addr(priv, desc, ring->index); | |
994 | ||
995 | /* Check ring space and update SW control flow */ | |
996 | if (ring->desc_count == 0) | |
997 | netif_tx_stop_queue(txq); | |
998 | ||
999 | netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", | |
23acb2fc | 1000 | ring->index, ring->desc_count, ring->curr_desc); |
80105bef FF |
1001 | |
1002 | ret = NETDEV_TX_OK; | |
1003 | out: | |
d8498088 | 1004 | spin_unlock_irqrestore(&ring->lock, flags); |
80105bef FF |
1005 | return ret; |
1006 | } | |
1007 | ||
1008 | static void bcm_sysport_tx_timeout(struct net_device *dev) | |
1009 | { | |
1010 | netdev_warn(dev, "transmit timeout!\n"); | |
1011 | ||
1012 | dev->trans_start = jiffies; | |
1013 | dev->stats.tx_errors++; | |
1014 | ||
1015 | netif_tx_wake_all_queues(dev); | |
1016 | } | |
1017 | ||
1018 | /* phylib adjust link callback */ | |
1019 | static void bcm_sysport_adj_link(struct net_device *dev) | |
1020 | { | |
1021 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1022 | struct phy_device *phydev = priv->phydev; | |
1023 | unsigned int changed = 0; | |
1024 | u32 cmd_bits = 0, reg; | |
1025 | ||
1026 | if (priv->old_link != phydev->link) { | |
1027 | changed = 1; | |
1028 | priv->old_link = phydev->link; | |
1029 | } | |
1030 | ||
1031 | if (priv->old_duplex != phydev->duplex) { | |
1032 | changed = 1; | |
1033 | priv->old_duplex = phydev->duplex; | |
1034 | } | |
1035 | ||
1036 | switch (phydev->speed) { | |
1037 | case SPEED_2500: | |
1038 | cmd_bits = CMD_SPEED_2500; | |
1039 | break; | |
1040 | case SPEED_1000: | |
1041 | cmd_bits = CMD_SPEED_1000; | |
1042 | break; | |
1043 | case SPEED_100: | |
1044 | cmd_bits = CMD_SPEED_100; | |
1045 | break; | |
1046 | case SPEED_10: | |
1047 | cmd_bits = CMD_SPEED_10; | |
1048 | break; | |
1049 | default: | |
1050 | break; | |
1051 | } | |
1052 | cmd_bits <<= CMD_SPEED_SHIFT; | |
1053 | ||
1054 | if (phydev->duplex == DUPLEX_HALF) | |
1055 | cmd_bits |= CMD_HD_EN; | |
1056 | ||
1057 | if (priv->old_pause != phydev->pause) { | |
1058 | changed = 1; | |
1059 | priv->old_pause = phydev->pause; | |
1060 | } | |
1061 | ||
1062 | if (!phydev->pause) | |
1063 | cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; | |
1064 | ||
d5e32cc7 FF |
1065 | if (changed) { |
1066 | reg = umac_readl(priv, UMAC_CMD); | |
1067 | reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | | |
80105bef FF |
1068 | CMD_HD_EN | CMD_RX_PAUSE_IGNORE | |
1069 | CMD_TX_PAUSE_IGNORE); | |
d5e32cc7 FF |
1070 | reg |= cmd_bits; |
1071 | umac_writel(priv, reg, UMAC_CMD); | |
80105bef | 1072 | |
80105bef | 1073 | phy_print_status(priv->phydev); |
d5e32cc7 | 1074 | } |
80105bef FF |
1075 | } |
1076 | ||
1077 | static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, | |
1078 | unsigned int index) | |
1079 | { | |
1080 | struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; | |
1081 | struct device *kdev = &priv->pdev->dev; | |
1082 | size_t size; | |
1083 | void *p; | |
1084 | u32 reg; | |
1085 | ||
1086 | /* Simple descriptors partitioning for now */ | |
1087 | size = 256; | |
1088 | ||
1089 | /* We just need one DMA descriptor which is DMA-able, since writing to | |
1090 | * the port will allocate a new descriptor in its internal linked-list | |
1091 | */ | |
1092 | p = dma_zalloc_coherent(kdev, 1, &ring->desc_dma, GFP_KERNEL); | |
1093 | if (!p) { | |
1094 | netif_err(priv, hw, priv->netdev, "DMA alloc failed\n"); | |
1095 | return -ENOMEM; | |
1096 | } | |
1097 | ||
1098 | ring->cbs = kzalloc(sizeof(struct bcm_sysport_cb) * size, GFP_KERNEL); | |
1099 | if (!ring->cbs) { | |
1100 | netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); | |
1101 | return -ENOMEM; | |
1102 | } | |
1103 | ||
1104 | /* Initialize SW view of the ring */ | |
1105 | spin_lock_init(&ring->lock); | |
1106 | ring->priv = priv; | |
1107 | netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); | |
1108 | ring->index = index; | |
1109 | ring->size = size; | |
1110 | ring->alloc_size = ring->size; | |
1111 | ring->desc_cpu = p; | |
1112 | ring->desc_count = ring->size; | |
1113 | ring->curr_desc = 0; | |
1114 | ||
1115 | /* Initialize HW ring */ | |
1116 | tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); | |
1117 | tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); | |
1118 | tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); | |
1119 | tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); | |
1120 | tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); | |
1121 | tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); | |
1122 | ||
1123 | /* Program the number of descriptors as MAX_THRESHOLD and half of | |
1124 | * its size for the hysteresis trigger | |
1125 | */ | |
1126 | tdma_writel(priv, ring->size | | |
1127 | 1 << RING_HYST_THRESH_SHIFT, | |
1128 | TDMA_DESC_RING_MAX_HYST(index)); | |
1129 | ||
1130 | /* Enable the ring queue in the arbiter */ | |
1131 | reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); | |
1132 | reg |= (1 << index); | |
1133 | tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); | |
1134 | ||
1135 | napi_enable(&ring->napi); | |
1136 | ||
1137 | netif_dbg(priv, hw, priv->netdev, | |
23acb2fc FF |
1138 | "TDMA cfg, size=%d, desc_cpu=%p\n", |
1139 | ring->size, ring->desc_cpu); | |
80105bef FF |
1140 | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, | |
23acb2fc | 1145 | unsigned int index) |
80105bef FF |
1146 | { |
1147 | struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; | |
1148 | struct device *kdev = &priv->pdev->dev; | |
1149 | u32 reg; | |
1150 | ||
1151 | /* Caller should stop the TDMA engine */ | |
1152 | reg = tdma_readl(priv, TDMA_STATUS); | |
1153 | if (!(reg & TDMA_DISABLED)) | |
1154 | netdev_warn(priv->netdev, "TDMA not stopped!\n"); | |
1155 | ||
1156 | napi_disable(&ring->napi); | |
1157 | netif_napi_del(&ring->napi); | |
1158 | ||
1159 | bcm_sysport_tx_reclaim(priv, ring); | |
1160 | ||
1161 | kfree(ring->cbs); | |
1162 | ring->cbs = NULL; | |
1163 | ||
1164 | if (ring->desc_dma) { | |
1165 | dma_free_coherent(kdev, 1, ring->desc_cpu, ring->desc_dma); | |
1166 | ring->desc_dma = 0; | |
1167 | } | |
1168 | ring->size = 0; | |
1169 | ring->alloc_size = 0; | |
1170 | ||
1171 | netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); | |
1172 | } | |
1173 | ||
1174 | /* RDMA helper */ | |
1175 | static inline int rdma_enable_set(struct bcm_sysport_priv *priv, | |
23acb2fc | 1176 | unsigned int enable) |
80105bef FF |
1177 | { |
1178 | unsigned int timeout = 1000; | |
1179 | u32 reg; | |
1180 | ||
1181 | reg = rdma_readl(priv, RDMA_CONTROL); | |
1182 | if (enable) | |
1183 | reg |= RDMA_EN; | |
1184 | else | |
1185 | reg &= ~RDMA_EN; | |
1186 | rdma_writel(priv, reg, RDMA_CONTROL); | |
1187 | ||
1188 | /* Poll for RMDA disabling completion */ | |
1189 | do { | |
1190 | reg = rdma_readl(priv, RDMA_STATUS); | |
1191 | if (!!(reg & RDMA_DISABLED) == !enable) | |
1192 | return 0; | |
1193 | usleep_range(1000, 2000); | |
1194 | } while (timeout-- > 0); | |
1195 | ||
1196 | netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); | |
1197 | ||
1198 | return -ETIMEDOUT; | |
1199 | } | |
1200 | ||
1201 | /* TDMA helper */ | |
1202 | static inline int tdma_enable_set(struct bcm_sysport_priv *priv, | |
23acb2fc | 1203 | unsigned int enable) |
80105bef FF |
1204 | { |
1205 | unsigned int timeout = 1000; | |
1206 | u32 reg; | |
1207 | ||
1208 | reg = tdma_readl(priv, TDMA_CONTROL); | |
1209 | if (enable) | |
1210 | reg |= TDMA_EN; | |
1211 | else | |
1212 | reg &= ~TDMA_EN; | |
1213 | tdma_writel(priv, reg, TDMA_CONTROL); | |
1214 | ||
1215 | /* Poll for TMDA disabling completion */ | |
1216 | do { | |
1217 | reg = tdma_readl(priv, TDMA_STATUS); | |
1218 | if (!!(reg & TDMA_DISABLED) == !enable) | |
1219 | return 0; | |
1220 | ||
1221 | usleep_range(1000, 2000); | |
1222 | } while (timeout-- > 0); | |
1223 | ||
1224 | netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); | |
1225 | ||
1226 | return -ETIMEDOUT; | |
1227 | } | |
1228 | ||
1229 | static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) | |
1230 | { | |
1231 | u32 reg; | |
1232 | int ret; | |
1233 | ||
1234 | /* Initialize SW view of the RX ring */ | |
1235 | priv->num_rx_bds = NUM_RX_DESC; | |
1236 | priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; | |
1237 | priv->rx_bd_assign_ptr = priv->rx_bds; | |
1238 | priv->rx_bd_assign_index = 0; | |
1239 | priv->rx_c_index = 0; | |
1240 | priv->rx_read_ptr = 0; | |
1241 | priv->rx_cbs = kzalloc(priv->num_rx_bds * | |
1242 | sizeof(struct bcm_sysport_cb), GFP_KERNEL); | |
1243 | if (!priv->rx_cbs) { | |
1244 | netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); | |
1245 | return -ENOMEM; | |
1246 | } | |
1247 | ||
1248 | ret = bcm_sysport_alloc_rx_bufs(priv); | |
1249 | if (ret) { | |
1250 | netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); | |
1251 | return ret; | |
1252 | } | |
1253 | ||
1254 | /* Initialize HW, ensure RDMA is disabled */ | |
1255 | reg = rdma_readl(priv, RDMA_STATUS); | |
1256 | if (!(reg & RDMA_DISABLED)) | |
1257 | rdma_enable_set(priv, 0); | |
1258 | ||
1259 | rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); | |
1260 | rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); | |
1261 | rdma_writel(priv, 0, RDMA_PROD_INDEX); | |
1262 | rdma_writel(priv, 0, RDMA_CONS_INDEX); | |
1263 | rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | | |
1264 | RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); | |
1265 | /* Operate the queue in ring mode */ | |
1266 | rdma_writel(priv, 0, RDMA_START_ADDR_HI); | |
1267 | rdma_writel(priv, 0, RDMA_START_ADDR_LO); | |
1268 | rdma_writel(priv, 0, RDMA_END_ADDR_HI); | |
1269 | rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO); | |
1270 | ||
1271 | rdma_writel(priv, 1, RDMA_MBDONE_INTR); | |
1272 | ||
1273 | netif_dbg(priv, hw, priv->netdev, | |
23acb2fc FF |
1274 | "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", |
1275 | priv->num_rx_bds, priv->rx_bds); | |
80105bef FF |
1276 | |
1277 | return 0; | |
1278 | } | |
1279 | ||
1280 | static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) | |
1281 | { | |
1282 | struct bcm_sysport_cb *cb; | |
1283 | unsigned int i; | |
1284 | u32 reg; | |
1285 | ||
1286 | /* Caller should ensure RDMA is disabled */ | |
1287 | reg = rdma_readl(priv, RDMA_STATUS); | |
1288 | if (!(reg & RDMA_DISABLED)) | |
1289 | netdev_warn(priv->netdev, "RDMA not stopped!\n"); | |
1290 | ||
1291 | for (i = 0; i < priv->num_rx_bds; i++) { | |
1292 | cb = &priv->rx_cbs[i]; | |
1293 | if (dma_unmap_addr(cb, dma_addr)) | |
1294 | dma_unmap_single(&priv->pdev->dev, | |
23acb2fc FF |
1295 | dma_unmap_addr(cb, dma_addr), |
1296 | RX_BUF_LENGTH, DMA_FROM_DEVICE); | |
80105bef FF |
1297 | bcm_sysport_free_cb(cb); |
1298 | } | |
1299 | ||
1300 | kfree(priv->rx_cbs); | |
1301 | priv->rx_cbs = NULL; | |
1302 | ||
1303 | netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); | |
1304 | } | |
1305 | ||
1306 | static void bcm_sysport_set_rx_mode(struct net_device *dev) | |
1307 | { | |
1308 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1309 | u32 reg; | |
1310 | ||
1311 | reg = umac_readl(priv, UMAC_CMD); | |
1312 | if (dev->flags & IFF_PROMISC) | |
1313 | reg |= CMD_PROMISC; | |
1314 | else | |
1315 | reg &= ~CMD_PROMISC; | |
1316 | umac_writel(priv, reg, UMAC_CMD); | |
1317 | ||
1318 | /* No support for ALLMULTI */ | |
1319 | if (dev->flags & IFF_ALLMULTI) | |
1320 | return; | |
1321 | } | |
1322 | ||
1323 | static inline void umac_enable_set(struct bcm_sysport_priv *priv, | |
23acb2fc | 1324 | u32 mask, unsigned int enable) |
80105bef FF |
1325 | { |
1326 | u32 reg; | |
1327 | ||
1328 | reg = umac_readl(priv, UMAC_CMD); | |
1329 | if (enable) | |
18e21b01 | 1330 | reg |= mask; |
80105bef | 1331 | else |
18e21b01 | 1332 | reg &= ~mask; |
80105bef | 1333 | umac_writel(priv, reg, UMAC_CMD); |
00b91c69 FF |
1334 | |
1335 | /* UniMAC stops on a packet boundary, wait for a full-sized packet | |
1336 | * to be processed (1 msec). | |
1337 | */ | |
1338 | if (enable == 0) | |
1339 | usleep_range(1000, 2000); | |
80105bef FF |
1340 | } |
1341 | ||
1342 | static inline int umac_reset(struct bcm_sysport_priv *priv) | |
1343 | { | |
1344 | unsigned int timeout = 0; | |
1345 | u32 reg; | |
1346 | int ret = 0; | |
1347 | ||
1348 | umac_writel(priv, 0, UMAC_CMD); | |
1349 | while (timeout++ < 1000) { | |
1350 | reg = umac_readl(priv, UMAC_CMD); | |
1351 | if (!(reg & CMD_SW_RESET)) | |
1352 | break; | |
1353 | ||
1354 | udelay(1); | |
1355 | } | |
1356 | ||
1357 | if (timeout == 1000) { | |
1358 | dev_err(&priv->pdev->dev, | |
1359 | "timeout waiting for MAC to come out of reset\n"); | |
1360 | ret = -ETIMEDOUT; | |
1361 | } | |
1362 | ||
1363 | return ret; | |
1364 | } | |
1365 | ||
1366 | static void umac_set_hw_addr(struct bcm_sysport_priv *priv, | |
23acb2fc | 1367 | unsigned char *addr) |
80105bef FF |
1368 | { |
1369 | umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | | |
1370 | (addr[2] << 8) | addr[3], UMAC_MAC0); | |
1371 | umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); | |
1372 | } | |
1373 | ||
1374 | static void topctrl_flush(struct bcm_sysport_priv *priv) | |
1375 | { | |
1376 | topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); | |
1377 | topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); | |
1378 | mdelay(1); | |
1379 | topctrl_writel(priv, 0, RX_FLUSH_CNTL); | |
1380 | topctrl_writel(priv, 0, TX_FLUSH_CNTL); | |
1381 | } | |
1382 | ||
b02e6d9b FF |
1383 | static void bcm_sysport_netif_start(struct net_device *dev) |
1384 | { | |
1385 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1386 | ||
1387 | /* Enable NAPI */ | |
1388 | napi_enable(&priv->napi); | |
1389 | ||
1390 | phy_start(priv->phydev); | |
1391 | ||
1392 | /* Enable TX interrupts for the 32 TXQs */ | |
1393 | intrl2_1_mask_clear(priv, 0xffffffff); | |
1394 | ||
1395 | /* Last call before we start the real business */ | |
1396 | netif_tx_start_all_queues(dev); | |
1397 | } | |
1398 | ||
40755a0f FF |
1399 | static void rbuf_init(struct bcm_sysport_priv *priv) |
1400 | { | |
1401 | u32 reg; | |
1402 | ||
1403 | reg = rbuf_readl(priv, RBUF_CONTROL); | |
1404 | reg |= RBUF_4B_ALGN | RBUF_RSB_EN; | |
1405 | rbuf_writel(priv, reg, RBUF_CONTROL); | |
1406 | } | |
1407 | ||
80105bef FF |
1408 | static int bcm_sysport_open(struct net_device *dev) |
1409 | { | |
1410 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1411 | unsigned int i; | |
80105bef FF |
1412 | int ret; |
1413 | ||
1414 | /* Reset UniMAC */ | |
1415 | ret = umac_reset(priv); | |
1416 | if (ret) { | |
1417 | netdev_err(dev, "UniMAC reset failed\n"); | |
1418 | return ret; | |
1419 | } | |
1420 | ||
1421 | /* Flush TX and RX FIFOs at TOPCTRL level */ | |
1422 | topctrl_flush(priv); | |
1423 | ||
1424 | /* Disable the UniMAC RX/TX */ | |
18e21b01 | 1425 | umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); |
80105bef FF |
1426 | |
1427 | /* Enable RBUF 2bytes alignment and Receive Status Block */ | |
40755a0f | 1428 | rbuf_init(priv); |
80105bef FF |
1429 | |
1430 | /* Set maximum frame length */ | |
1431 | umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); | |
1432 | ||
1433 | /* Set MAC address */ | |
1434 | umac_set_hw_addr(priv, dev->dev_addr); | |
1435 | ||
1436 | /* Read CRC forward */ | |
1437 | priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); | |
1438 | ||
186534a3 FF |
1439 | priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, |
1440 | 0, priv->phy_interface); | |
80105bef FF |
1441 | if (!priv->phydev) { |
1442 | netdev_err(dev, "could not attach to PHY\n"); | |
1443 | return -ENODEV; | |
1444 | } | |
1445 | ||
1446 | /* Reset house keeping link status */ | |
1447 | priv->old_duplex = -1; | |
1448 | priv->old_link = -1; | |
1449 | priv->old_pause = -1; | |
1450 | ||
1451 | /* mask all interrupts and request them */ | |
1452 | intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); | |
1453 | intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); | |
1454 | intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); | |
1455 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET); | |
1456 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); | |
1457 | intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); | |
1458 | ||
1459 | ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); | |
1460 | if (ret) { | |
1461 | netdev_err(dev, "failed to request RX interrupt\n"); | |
1462 | goto out_phy_disconnect; | |
1463 | } | |
1464 | ||
1465 | ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev); | |
1466 | if (ret) { | |
1467 | netdev_err(dev, "failed to request TX interrupt\n"); | |
1468 | goto out_free_irq0; | |
1469 | } | |
1470 | ||
1471 | /* Initialize both hardware and software ring */ | |
1472 | for (i = 0; i < dev->num_tx_queues; i++) { | |
1473 | ret = bcm_sysport_init_tx_ring(priv, i); | |
1474 | if (ret) { | |
1475 | netdev_err(dev, "failed to initialize TX ring %d\n", | |
23acb2fc | 1476 | i); |
80105bef FF |
1477 | goto out_free_tx_ring; |
1478 | } | |
1479 | } | |
1480 | ||
1481 | /* Initialize linked-list */ | |
1482 | tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); | |
1483 | ||
1484 | /* Initialize RX ring */ | |
1485 | ret = bcm_sysport_init_rx_ring(priv); | |
1486 | if (ret) { | |
1487 | netdev_err(dev, "failed to initialize RX ring\n"); | |
1488 | goto out_free_rx_ring; | |
1489 | } | |
1490 | ||
1491 | /* Turn on RDMA */ | |
1492 | ret = rdma_enable_set(priv, 1); | |
1493 | if (ret) | |
1494 | goto out_free_rx_ring; | |
1495 | ||
1496 | /* Enable RX interrupt and TX ring full interrupt */ | |
1497 | intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); | |
1498 | ||
1499 | /* Turn on TDMA */ | |
1500 | ret = tdma_enable_set(priv, 1); | |
1501 | if (ret) | |
1502 | goto out_clear_rx_int; | |
1503 | ||
80105bef | 1504 | /* Turn on UniMAC TX/RX */ |
18e21b01 | 1505 | umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); |
80105bef | 1506 | |
b02e6d9b | 1507 | bcm_sysport_netif_start(dev); |
80105bef FF |
1508 | |
1509 | return 0; | |
1510 | ||
1511 | out_clear_rx_int: | |
1512 | intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); | |
1513 | out_free_rx_ring: | |
1514 | bcm_sysport_fini_rx_ring(priv); | |
1515 | out_free_tx_ring: | |
1516 | for (i = 0; i < dev->num_tx_queues; i++) | |
1517 | bcm_sysport_fini_tx_ring(priv, i); | |
1518 | free_irq(priv->irq1, dev); | |
1519 | out_free_irq0: | |
1520 | free_irq(priv->irq0, dev); | |
1521 | out_phy_disconnect: | |
1522 | phy_disconnect(priv->phydev); | |
1523 | return ret; | |
1524 | } | |
1525 | ||
b02e6d9b | 1526 | static void bcm_sysport_netif_stop(struct net_device *dev) |
80105bef FF |
1527 | { |
1528 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
80105bef FF |
1529 | |
1530 | /* stop all software from updating hardware */ | |
1531 | netif_tx_stop_all_queues(dev); | |
1532 | napi_disable(&priv->napi); | |
1533 | phy_stop(priv->phydev); | |
1534 | ||
1535 | /* mask all interrupts */ | |
1536 | intrl2_0_mask_set(priv, 0xffffffff); | |
1537 | intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); | |
1538 | intrl2_1_mask_set(priv, 0xffffffff); | |
1539 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); | |
b02e6d9b FF |
1540 | } |
1541 | ||
1542 | static int bcm_sysport_stop(struct net_device *dev) | |
1543 | { | |
1544 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1545 | unsigned int i; | |
1546 | int ret; | |
1547 | ||
1548 | bcm_sysport_netif_stop(dev); | |
80105bef FF |
1549 | |
1550 | /* Disable UniMAC RX */ | |
18e21b01 | 1551 | umac_enable_set(priv, CMD_RX_EN, 0); |
80105bef FF |
1552 | |
1553 | ret = tdma_enable_set(priv, 0); | |
1554 | if (ret) { | |
1555 | netdev_err(dev, "timeout disabling RDMA\n"); | |
1556 | return ret; | |
1557 | } | |
1558 | ||
1559 | /* Wait for a maximum packet size to be drained */ | |
1560 | usleep_range(2000, 3000); | |
1561 | ||
1562 | ret = rdma_enable_set(priv, 0); | |
1563 | if (ret) { | |
1564 | netdev_err(dev, "timeout disabling TDMA\n"); | |
1565 | return ret; | |
1566 | } | |
1567 | ||
1568 | /* Disable UniMAC TX */ | |
18e21b01 | 1569 | umac_enable_set(priv, CMD_TX_EN, 0); |
80105bef FF |
1570 | |
1571 | /* Free RX/TX rings SW structures */ | |
1572 | for (i = 0; i < dev->num_tx_queues; i++) | |
1573 | bcm_sysport_fini_tx_ring(priv, i); | |
1574 | bcm_sysport_fini_rx_ring(priv); | |
1575 | ||
1576 | free_irq(priv->irq0, dev); | |
1577 | free_irq(priv->irq1, dev); | |
1578 | ||
1579 | /* Disconnect from PHY */ | |
1580 | phy_disconnect(priv->phydev); | |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
1585 | static struct ethtool_ops bcm_sysport_ethtool_ops = { | |
1586 | .get_settings = bcm_sysport_get_settings, | |
1587 | .set_settings = bcm_sysport_set_settings, | |
1588 | .get_drvinfo = bcm_sysport_get_drvinfo, | |
1589 | .get_msglevel = bcm_sysport_get_msglvl, | |
1590 | .set_msglevel = bcm_sysport_set_msglvl, | |
1591 | .get_link = ethtool_op_get_link, | |
1592 | .get_strings = bcm_sysport_get_strings, | |
1593 | .get_ethtool_stats = bcm_sysport_get_stats, | |
1594 | .get_sset_count = bcm_sysport_get_sset_count, | |
83e82f4c FF |
1595 | .get_wol = bcm_sysport_get_wol, |
1596 | .set_wol = bcm_sysport_set_wol, | |
80105bef FF |
1597 | }; |
1598 | ||
1599 | static const struct net_device_ops bcm_sysport_netdev_ops = { | |
1600 | .ndo_start_xmit = bcm_sysport_xmit, | |
1601 | .ndo_tx_timeout = bcm_sysport_tx_timeout, | |
1602 | .ndo_open = bcm_sysport_open, | |
1603 | .ndo_stop = bcm_sysport_stop, | |
1604 | .ndo_set_features = bcm_sysport_set_features, | |
1605 | .ndo_set_rx_mode = bcm_sysport_set_rx_mode, | |
1606 | }; | |
1607 | ||
1608 | #define REV_FMT "v%2x.%02x" | |
1609 | ||
1610 | static int bcm_sysport_probe(struct platform_device *pdev) | |
1611 | { | |
1612 | struct bcm_sysport_priv *priv; | |
1613 | struct device_node *dn; | |
1614 | struct net_device *dev; | |
1615 | const void *macaddr; | |
1616 | struct resource *r; | |
1617 | u32 txq, rxq; | |
1618 | int ret; | |
1619 | ||
1620 | dn = pdev->dev.of_node; | |
1621 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1622 | ||
1623 | /* Read the Transmit/Receive Queue properties */ | |
1624 | if (of_property_read_u32(dn, "systemport,num-txq", &txq)) | |
1625 | txq = TDMA_NUM_RINGS; | |
1626 | if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) | |
1627 | rxq = 1; | |
1628 | ||
1629 | dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); | |
1630 | if (!dev) | |
1631 | return -ENOMEM; | |
1632 | ||
1633 | /* Initialize private members */ | |
1634 | priv = netdev_priv(dev); | |
1635 | ||
1636 | priv->irq0 = platform_get_irq(pdev, 0); | |
1637 | priv->irq1 = platform_get_irq(pdev, 1); | |
83e82f4c | 1638 | priv->wol_irq = platform_get_irq(pdev, 2); |
80105bef FF |
1639 | if (priv->irq0 <= 0 || priv->irq1 <= 0) { |
1640 | dev_err(&pdev->dev, "invalid interrupts\n"); | |
1641 | ret = -EINVAL; | |
1642 | goto err; | |
1643 | } | |
1644 | ||
126e6122 JH |
1645 | priv->base = devm_ioremap_resource(&pdev->dev, r); |
1646 | if (IS_ERR(priv->base)) { | |
1647 | ret = PTR_ERR(priv->base); | |
80105bef FF |
1648 | goto err; |
1649 | } | |
1650 | ||
1651 | priv->netdev = dev; | |
1652 | priv->pdev = pdev; | |
1653 | ||
1654 | priv->phy_interface = of_get_phy_mode(dn); | |
1655 | /* Default to GMII interface mode */ | |
1656 | if (priv->phy_interface < 0) | |
1657 | priv->phy_interface = PHY_INTERFACE_MODE_GMII; | |
1658 | ||
186534a3 FF |
1659 | /* In the case of a fixed PHY, the DT node associated |
1660 | * to the PHY is the Ethernet MAC DT node. | |
1661 | */ | |
1662 | if (of_phy_is_fixed_link(dn)) { | |
1663 | ret = of_phy_register_fixed_link(dn); | |
1664 | if (ret) { | |
1665 | dev_err(&pdev->dev, "failed to register fixed PHY\n"); | |
1666 | goto err; | |
1667 | } | |
1668 | ||
1669 | priv->phy_dn = dn; | |
1670 | } | |
1671 | ||
80105bef FF |
1672 | /* Initialize netdevice members */ |
1673 | macaddr = of_get_mac_address(dn); | |
1674 | if (!macaddr || !is_valid_ether_addr(macaddr)) { | |
1675 | dev_warn(&pdev->dev, "using random Ethernet MAC\n"); | |
1676 | random_ether_addr(dev->dev_addr); | |
1677 | } else { | |
1678 | ether_addr_copy(dev->dev_addr, macaddr); | |
1679 | } | |
1680 | ||
1681 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1682 | dev_set_drvdata(&pdev->dev, dev); | |
7ad24ea4 | 1683 | dev->ethtool_ops = &bcm_sysport_ethtool_ops; |
80105bef FF |
1684 | dev->netdev_ops = &bcm_sysport_netdev_ops; |
1685 | netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); | |
1686 | ||
1687 | /* HW supported features, none enabled by default */ | |
1688 | dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | | |
1689 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; | |
1690 | ||
83e82f4c FF |
1691 | /* Request the WOL interrupt and advertise suspend if available */ |
1692 | priv->wol_irq_disabled = 1; | |
1693 | ret = devm_request_irq(&pdev->dev, priv->wol_irq, | |
23acb2fc | 1694 | bcm_sysport_wol_isr, 0, dev->name, priv); |
83e82f4c FF |
1695 | if (!ret) |
1696 | device_set_wakeup_capable(&pdev->dev, 1); | |
1697 | ||
80105bef | 1698 | /* Set the needed headroom once and for all */ |
3afc557d PG |
1699 | BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); |
1700 | dev->needed_headroom += sizeof(struct bcm_tsb); | |
80105bef FF |
1701 | |
1702 | /* We are interfaced to a switch which handles the multicast | |
1703 | * filtering for us, so we do not support programming any | |
1704 | * multicast hash table in this Ethernet MAC. | |
1705 | */ | |
1706 | dev->flags &= ~IFF_MULTICAST; | |
1707 | ||
f532e744 FF |
1708 | /* libphy will adjust the link state accordingly */ |
1709 | netif_carrier_off(dev); | |
1710 | ||
80105bef FF |
1711 | ret = register_netdev(dev); |
1712 | if (ret) { | |
1713 | dev_err(&pdev->dev, "failed to register net_device\n"); | |
1714 | goto err; | |
1715 | } | |
1716 | ||
1717 | priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; | |
1718 | dev_info(&pdev->dev, | |
23acb2fc FF |
1719 | "Broadcom SYSTEMPORT" REV_FMT |
1720 | " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", | |
1721 | (priv->rev >> 8) & 0xff, priv->rev & 0xff, | |
1722 | priv->base, priv->irq0, priv->irq1, txq, rxq); | |
80105bef FF |
1723 | |
1724 | return 0; | |
1725 | err: | |
1726 | free_netdev(dev); | |
1727 | return ret; | |
1728 | } | |
1729 | ||
1730 | static int bcm_sysport_remove(struct platform_device *pdev) | |
1731 | { | |
1732 | struct net_device *dev = dev_get_drvdata(&pdev->dev); | |
1733 | ||
1734 | /* Not much to do, ndo_close has been called | |
1735 | * and we use managed allocations | |
1736 | */ | |
1737 | unregister_netdev(dev); | |
1738 | free_netdev(dev); | |
1739 | dev_set_drvdata(&pdev->dev, NULL); | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
40755a0f | 1744 | #ifdef CONFIG_PM_SLEEP |
83e82f4c FF |
1745 | static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) |
1746 | { | |
1747 | struct net_device *ndev = priv->netdev; | |
1748 | unsigned int timeout = 1000; | |
1749 | u32 reg; | |
1750 | ||
1751 | /* Password has already been programmed */ | |
1752 | reg = umac_readl(priv, UMAC_MPD_CTRL); | |
1753 | reg |= MPD_EN; | |
1754 | reg &= ~PSW_EN; | |
1755 | if (priv->wolopts & WAKE_MAGICSECURE) | |
1756 | reg |= PSW_EN; | |
1757 | umac_writel(priv, reg, UMAC_MPD_CTRL); | |
1758 | ||
1759 | /* Make sure RBUF entered WoL mode as result */ | |
1760 | do { | |
1761 | reg = rbuf_readl(priv, RBUF_STATUS); | |
1762 | if (reg & RBUF_WOL_MODE) | |
1763 | break; | |
1764 | ||
1765 | udelay(10); | |
1766 | } while (timeout-- > 0); | |
1767 | ||
1768 | /* Do not leave the UniMAC RBUF matching only MPD packets */ | |
1769 | if (!timeout) { | |
1770 | reg = umac_readl(priv, UMAC_MPD_CTRL); | |
1771 | reg &= ~MPD_EN; | |
1772 | umac_writel(priv, reg, UMAC_MPD_CTRL); | |
1773 | netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); | |
1774 | return -ETIMEDOUT; | |
1775 | } | |
1776 | ||
1777 | /* UniMAC receive needs to be turned on */ | |
1778 | umac_enable_set(priv, CMD_RX_EN, 1); | |
1779 | ||
1780 | /* Enable the interrupt wake-up source */ | |
1781 | intrl2_0_mask_clear(priv, INTRL2_0_MPD); | |
1782 | ||
1783 | netif_dbg(priv, wol, ndev, "entered WOL mode\n"); | |
1784 | ||
1785 | return 0; | |
1786 | } | |
1787 | ||
40755a0f FF |
1788 | static int bcm_sysport_suspend(struct device *d) |
1789 | { | |
1790 | struct net_device *dev = dev_get_drvdata(d); | |
1791 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1792 | unsigned int i; | |
83e82f4c | 1793 | int ret = 0; |
40755a0f FF |
1794 | u32 reg; |
1795 | ||
1796 | if (!netif_running(dev)) | |
1797 | return 0; | |
1798 | ||
1799 | bcm_sysport_netif_stop(dev); | |
1800 | ||
1801 | phy_suspend(priv->phydev); | |
1802 | ||
1803 | netif_device_detach(dev); | |
1804 | ||
1805 | /* Disable UniMAC RX */ | |
1806 | umac_enable_set(priv, CMD_RX_EN, 0); | |
1807 | ||
1808 | ret = rdma_enable_set(priv, 0); | |
1809 | if (ret) { | |
1810 | netdev_err(dev, "RDMA timeout!\n"); | |
1811 | return ret; | |
1812 | } | |
1813 | ||
1814 | /* Disable RXCHK if enabled */ | |
9d34c1cb | 1815 | if (priv->rx_chk_en) { |
40755a0f FF |
1816 | reg = rxchk_readl(priv, RXCHK_CONTROL); |
1817 | reg &= ~RXCHK_EN; | |
1818 | rxchk_writel(priv, reg, RXCHK_CONTROL); | |
1819 | } | |
1820 | ||
1821 | /* Flush RX pipe */ | |
83e82f4c FF |
1822 | if (!priv->wolopts) |
1823 | topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); | |
40755a0f FF |
1824 | |
1825 | ret = tdma_enable_set(priv, 0); | |
1826 | if (ret) { | |
1827 | netdev_err(dev, "TDMA timeout!\n"); | |
1828 | return ret; | |
1829 | } | |
1830 | ||
1831 | /* Wait for a packet boundary */ | |
1832 | usleep_range(2000, 3000); | |
1833 | ||
1834 | umac_enable_set(priv, CMD_TX_EN, 0); | |
1835 | ||
1836 | topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); | |
1837 | ||
1838 | /* Free RX/TX rings SW structures */ | |
1839 | for (i = 0; i < dev->num_tx_queues; i++) | |
1840 | bcm_sysport_fini_tx_ring(priv, i); | |
1841 | bcm_sysport_fini_rx_ring(priv); | |
1842 | ||
83e82f4c FF |
1843 | /* Get prepared for Wake-on-LAN */ |
1844 | if (device_may_wakeup(d) && priv->wolopts) | |
1845 | ret = bcm_sysport_suspend_to_wol(priv); | |
1846 | ||
1847 | return ret; | |
40755a0f FF |
1848 | } |
1849 | ||
1850 | static int bcm_sysport_resume(struct device *d) | |
1851 | { | |
1852 | struct net_device *dev = dev_get_drvdata(d); | |
1853 | struct bcm_sysport_priv *priv = netdev_priv(dev); | |
1854 | unsigned int i; | |
1855 | u32 reg; | |
1856 | int ret; | |
1857 | ||
1858 | if (!netif_running(dev)) | |
1859 | return 0; | |
1860 | ||
83e82f4c FF |
1861 | /* We may have been suspended and never received a WOL event that |
1862 | * would turn off MPD detection, take care of that now | |
1863 | */ | |
1864 | bcm_sysport_resume_from_wol(priv); | |
1865 | ||
40755a0f FF |
1866 | /* Initialize both hardware and software ring */ |
1867 | for (i = 0; i < dev->num_tx_queues; i++) { | |
1868 | ret = bcm_sysport_init_tx_ring(priv, i); | |
1869 | if (ret) { | |
1870 | netdev_err(dev, "failed to initialize TX ring %d\n", | |
23acb2fc | 1871 | i); |
40755a0f FF |
1872 | goto out_free_tx_rings; |
1873 | } | |
1874 | } | |
1875 | ||
1876 | /* Initialize linked-list */ | |
1877 | tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); | |
1878 | ||
1879 | /* Initialize RX ring */ | |
1880 | ret = bcm_sysport_init_rx_ring(priv); | |
1881 | if (ret) { | |
1882 | netdev_err(dev, "failed to initialize RX ring\n"); | |
1883 | goto out_free_rx_ring; | |
1884 | } | |
1885 | ||
1886 | netif_device_attach(dev); | |
1887 | ||
1888 | /* Enable RX interrupt and TX ring full interrupt */ | |
1889 | intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); | |
1890 | ||
1891 | /* RX pipe enable */ | |
1892 | topctrl_writel(priv, 0, RX_FLUSH_CNTL); | |
1893 | ||
1894 | ret = rdma_enable_set(priv, 1); | |
1895 | if (ret) { | |
1896 | netdev_err(dev, "failed to enable RDMA\n"); | |
1897 | goto out_free_rx_ring; | |
1898 | } | |
1899 | ||
1900 | /* Enable rxhck */ | |
9d34c1cb | 1901 | if (priv->rx_chk_en) { |
40755a0f FF |
1902 | reg = rxchk_readl(priv, RXCHK_CONTROL); |
1903 | reg |= RXCHK_EN; | |
1904 | rxchk_writel(priv, reg, RXCHK_CONTROL); | |
1905 | } | |
1906 | ||
1907 | rbuf_init(priv); | |
1908 | ||
1909 | /* Set maximum frame length */ | |
1910 | umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); | |
1911 | ||
1912 | /* Set MAC address */ | |
1913 | umac_set_hw_addr(priv, dev->dev_addr); | |
1914 | ||
1915 | umac_enable_set(priv, CMD_RX_EN, 1); | |
1916 | ||
1917 | /* TX pipe enable */ | |
1918 | topctrl_writel(priv, 0, TX_FLUSH_CNTL); | |
1919 | ||
1920 | umac_enable_set(priv, CMD_TX_EN, 1); | |
1921 | ||
1922 | ret = tdma_enable_set(priv, 1); | |
1923 | if (ret) { | |
1924 | netdev_err(dev, "TDMA timeout!\n"); | |
1925 | goto out_free_rx_ring; | |
1926 | } | |
1927 | ||
1928 | phy_resume(priv->phydev); | |
1929 | ||
1930 | bcm_sysport_netif_start(dev); | |
1931 | ||
1932 | return 0; | |
1933 | ||
1934 | out_free_rx_ring: | |
1935 | bcm_sysport_fini_rx_ring(priv); | |
1936 | out_free_tx_rings: | |
1937 | for (i = 0; i < dev->num_tx_queues; i++) | |
1938 | bcm_sysport_fini_tx_ring(priv, i); | |
1939 | return ret; | |
1940 | } | |
1941 | #endif | |
1942 | ||
1943 | static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, | |
1944 | bcm_sysport_suspend, bcm_sysport_resume); | |
1945 | ||
80105bef FF |
1946 | static const struct of_device_id bcm_sysport_of_match[] = { |
1947 | { .compatible = "brcm,systemport-v1.00" }, | |
1948 | { .compatible = "brcm,systemport" }, | |
1949 | { /* sentinel */ } | |
1950 | }; | |
1951 | ||
1952 | static struct platform_driver bcm_sysport_driver = { | |
1953 | .probe = bcm_sysport_probe, | |
1954 | .remove = bcm_sysport_remove, | |
1955 | .driver = { | |
1956 | .name = "brcm-systemport", | |
1957 | .owner = THIS_MODULE, | |
1958 | .of_match_table = bcm_sysport_of_match, | |
40755a0f | 1959 | .pm = &bcm_sysport_pm_ops, |
80105bef FF |
1960 | }, |
1961 | }; | |
1962 | module_platform_driver(bcm_sysport_driver); | |
1963 | ||
1964 | MODULE_AUTHOR("Broadcom Corporation"); | |
1965 | MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); | |
1966 | MODULE_ALIAS("platform:brcm-systemport"); | |
1967 | MODULE_LICENSE("GPL"); |