]>
Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
80105bef FF |
2 | /* |
3 | * Broadcom BCM7xxx System Port Ethernet MAC driver | |
4 | * | |
5 | * Copyright (C) 2014 Broadcom Corporation | |
80105bef FF |
6 | */ |
7 | ||
8 | #ifndef __BCM_SYSPORT_H | |
9 | #define __BCM_SYSPORT_H | |
10 | ||
bb9051a2 | 11 | #include <linux/bitmap.h> |
8dfb8d2c | 12 | #include <linux/ethtool.h> |
80105bef | 13 | #include <linux/if_vlan.h> |
4f75da36 | 14 | #include <linux/dim.h> |
80105bef FF |
15 | |
16 | /* Receive/transmit descriptor format */ | |
17 | #define DESC_ADDR_HI_STATUS_LEN 0x00 | |
18 | #define DESC_ADDR_HI_SHIFT 0 | |
19 | #define DESC_ADDR_HI_MASK 0xff | |
20 | #define DESC_STATUS_SHIFT 8 | |
21 | #define DESC_STATUS_MASK 0x3ff | |
22 | #define DESC_LEN_SHIFT 18 | |
23 | #define DESC_LEN_MASK 0x7fff | |
24 | #define DESC_ADDR_LO 0x04 | |
25 | ||
26 | /* HW supports 40-bit addressing hence the */ | |
27 | #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) | |
28 | ||
29 | /* Default RX buffer allocation size */ | |
30 | #define RX_BUF_LENGTH 2048 | |
31 | ||
dab531b4 | 32 | /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. |
80105bef FF |
33 | * 1536 is multiple of 256 bytes |
34 | */ | |
dab531b4 FF |
35 | #define ENET_BRCM_TAG_LEN 4 |
36 | #define ENET_PAD 10 | |
80105bef FF |
37 | #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ |
38 | ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) | |
39 | ||
40 | /* Transmit status block */ | |
3afc557d | 41 | struct bcm_tsb { |
80105bef FF |
42 | u32 pcp_dei_vid; |
43 | #define PCP_DEI_MASK 0xf | |
44 | #define VID_SHIFT 4 | |
45 | #define VID_MASK 0xfff | |
46 | u32 l4_ptr_dest_map; | |
47 | #define L4_CSUM_PTR_MASK 0x1ff | |
48 | #define L4_PTR_SHIFT 9 | |
49 | #define L4_PTR_MASK 0x1ff | |
50 | #define L4_UDP (1 << 18) | |
51 | #define L4_LENGTH_VALID (1 << 19) | |
52 | #define DEST_MAP_SHIFT 20 | |
53 | #define DEST_MAP_MASK 0x1ff | |
54 | }; | |
55 | ||
56 | /* Receive status block uses the same | |
57 | * definitions as the DMA descriptor | |
58 | */ | |
3afc557d | 59 | struct bcm_rsb { |
80105bef FF |
60 | u32 rx_status_len; |
61 | u32 brcm_egress_tag; | |
62 | }; | |
63 | ||
64 | /* Common Receive/Transmit status bits */ | |
65 | #define DESC_L4_CSUM (1 << 7) | |
66 | #define DESC_SOP (1 << 8) | |
67 | #define DESC_EOP (1 << 9) | |
68 | ||
69 | /* Receive Status bits */ | |
70 | #define RX_STATUS_UCAST 0 | |
71 | #define RX_STATUS_BCAST 0x04 | |
72 | #define RX_STATUS_MCAST 0x08 | |
73 | #define RX_STATUS_L2_MCAST 0x0c | |
74 | #define RX_STATUS_ERR (1 << 4) | |
75 | #define RX_STATUS_OVFLOW (1 << 5) | |
76 | #define RX_STATUS_PARSE_FAIL (1 << 6) | |
77 | ||
78 | /* Transmit Status bits */ | |
79 | #define TX_STATUS_VLAN_NO_ACT 0x00 | |
80 | #define TX_STATUS_VLAN_PCP_TSB 0x01 | |
81 | #define TX_STATUS_VLAN_QUEUE 0x02 | |
82 | #define TX_STATUS_VLAN_VID_TSB 0x03 | |
83 | #define TX_STATUS_OWR_CRC (1 << 2) | |
84 | #define TX_STATUS_APP_CRC (1 << 3) | |
85 | #define TX_STATUS_BRCM_TAG_NO_ACT 0 | |
86 | #define TX_STATUS_BRCM_TAG_ZERO 0x10 | |
87 | #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 | |
88 | #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 | |
89 | #define TX_STATUS_SKIP_BYTES (1 << 6) | |
90 | ||
91 | /* Specific register definitions */ | |
92 | #define SYS_PORT_TOPCTRL_OFFSET 0 | |
93 | #define REV_CNTL 0x00 | |
94 | #define REV_MASK 0xffff | |
95 | ||
96 | #define RX_FLUSH_CNTL 0x04 | |
97 | #define RX_FLUSH (1 << 0) | |
98 | ||
99 | #define TX_FLUSH_CNTL 0x08 | |
100 | #define TX_FLUSH (1 << 0) | |
101 | ||
102 | #define MISC_CNTL 0x0c | |
103 | #define SYS_CLK_SEL (1 << 0) | |
104 | #define TDMA_EOP_SEL (1 << 1) | |
105 | ||
106 | /* Level-2 Interrupt controller offsets and defines */ | |
107 | #define SYS_PORT_INTRL2_0_OFFSET 0x200 | |
108 | #define SYS_PORT_INTRL2_1_OFFSET 0x240 | |
109 | #define INTRL2_CPU_STATUS 0x00 | |
110 | #define INTRL2_CPU_SET 0x04 | |
111 | #define INTRL2_CPU_CLEAR 0x08 | |
112 | #define INTRL2_CPU_MASK_STATUS 0x0c | |
113 | #define INTRL2_CPU_MASK_SET 0x10 | |
114 | #define INTRL2_CPU_MASK_CLEAR 0x14 | |
115 | ||
116 | /* Level-2 instance 0 interrupt bits */ | |
117 | #define INTRL2_0_GISB_ERR (1 << 0) | |
118 | #define INTRL2_0_RBUF_OVFLOW (1 << 1) | |
119 | #define INTRL2_0_TBUF_UNDFLOW (1 << 2) | |
120 | #define INTRL2_0_MPD (1 << 3) | |
121 | #define INTRL2_0_BRCM_MATCH_TAG (1 << 4) | |
122 | #define INTRL2_0_RDMA_MBDONE (1 << 5) | |
123 | #define INTRL2_0_OVER_MAX_THRESH (1 << 6) | |
124 | #define INTRL2_0_BELOW_HYST_THRESH (1 << 7) | |
125 | #define INTRL2_0_FREE_LIST_EMPTY (1 << 8) | |
126 | #define INTRL2_0_TX_RING_FULL (1 << 9) | |
127 | #define INTRL2_0_DESC_ALLOC_ERR (1 << 10) | |
128 | #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) | |
129 | ||
44a4524c FF |
130 | /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ |
131 | #define INTRL2_0_TDMA_MBDONE_SHIFT 12 | |
132 | #define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT) | |
133 | ||
80105bef FF |
134 | /* RXCHK offset and defines */ |
135 | #define SYS_PORT_RXCHK_OFFSET 0x300 | |
136 | ||
137 | #define RXCHK_CONTROL 0x00 | |
138 | #define RXCHK_EN (1 << 0) | |
139 | #define RXCHK_SKIP_FCS (1 << 1) | |
140 | #define RXCHK_BAD_CSUM_DIS (1 << 2) | |
141 | #define RXCHK_BRCM_TAG_EN (1 << 3) | |
142 | #define RXCHK_BRCM_TAG_MATCH_SHIFT 4 | |
143 | #define RXCHK_BRCM_TAG_MATCH_MASK 0xff | |
144 | #define RXCHK_PARSE_TNL (1 << 12) | |
145 | #define RXCHK_VIOL_EN (1 << 13) | |
146 | #define RXCHK_VIOL_DIS (1 << 14) | |
147 | #define RXCHK_INCOM_PKT (1 << 15) | |
148 | #define RXCHK_V6_DUPEXT_EN (1 << 16) | |
149 | #define RXCHK_V6_DUPEXT_DIS (1 << 17) | |
150 | #define RXCHK_ETHERTYPE_DIS (1 << 18) | |
151 | #define RXCHK_L2_HDR_DIS (1 << 19) | |
152 | #define RXCHK_L3_HDR_DIS (1 << 20) | |
153 | #define RXCHK_MAC_RX_ERR_DIS (1 << 21) | |
154 | #define RXCHK_PARSE_AUTH (1 << 22) | |
155 | ||
156 | #define RXCHK_BRCM_TAG0 0x04 | |
bb9051a2 | 157 | #define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0) |
80105bef | 158 | #define RXCHK_BRCM_TAG0_MASK 0x24 |
bb9051a2 | 159 | #define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK) |
80105bef FF |
160 | #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 |
161 | #define RXCHK_ETHERTYPE 0x48 | |
162 | #define RXCHK_BAD_CSUM_CNTR 0x4C | |
163 | #define RXCHK_OTHER_DISC_CNTR 0x50 | |
164 | ||
bb9051a2 FF |
165 | #define RXCHK_BRCM_TAG_MAX 8 |
166 | #define RXCHK_BRCM_TAG_CID_SHIFT 16 | |
167 | #define RXCHK_BRCM_TAG_CID_MASK 0xff | |
168 | ||
80105bef FF |
169 | /* TXCHCK offsets and defines */ |
170 | #define SYS_PORT_TXCHK_OFFSET 0x380 | |
171 | #define TXCHK_PKT_RDY_THRESH 0x00 | |
172 | ||
173 | /* Receive buffer offset and defines */ | |
174 | #define SYS_PORT_RBUF_OFFSET 0x400 | |
175 | ||
176 | #define RBUF_CONTROL 0x00 | |
177 | #define RBUF_RSB_EN (1 << 0) | |
178 | #define RBUF_4B_ALGN (1 << 1) | |
179 | #define RBUF_BRCM_TAG_STRIP (1 << 2) | |
180 | #define RBUF_BAD_PKT_DISC (1 << 3) | |
181 | #define RBUF_RESUME_THRESH_SHIFT 4 | |
182 | #define RBUF_RESUME_THRESH_MASK 0xff | |
183 | #define RBUF_OK_TO_SEND_SHIFT 12 | |
184 | #define RBUF_OK_TO_SEND_MASK 0xff | |
185 | #define RBUF_CRC_REPLACE (1 << 20) | |
186 | #define RBUF_OK_TO_SEND_MODE (1 << 21) | |
44a4524c FF |
187 | /* SYSTEMPORT Lite uses two bits here */ |
188 | #define RBUF_RSB_SWAP0 (1 << 22) | |
189 | #define RBUF_RSB_SWAP1 (1 << 23) | |
80105bef | 190 | #define RBUF_ACPI_EN (1 << 23) |
bb9051a2 | 191 | #define RBUF_ACPI_EN_LITE (1 << 24) |
80105bef FF |
192 | |
193 | #define RBUF_PKT_RDY_THRESH 0x04 | |
194 | ||
195 | #define RBUF_STATUS 0x08 | |
196 | #define RBUF_WOL_MODE (1 << 0) | |
197 | #define RBUF_MPD (1 << 1) | |
198 | #define RBUF_ACPI (1 << 2) | |
199 | ||
200 | #define RBUF_OVFL_DISC_CNTR 0x0c | |
201 | #define RBUF_ERR_PKT_CNTR 0x10 | |
202 | ||
203 | /* Transmit buffer offset and defines */ | |
204 | #define SYS_PORT_TBUF_OFFSET 0x600 | |
205 | ||
206 | #define TBUF_CONTROL 0x00 | |
207 | #define TBUF_BP_EN (1 << 0) | |
208 | #define TBUF_MAX_PKT_THRESH_SHIFT 1 | |
209 | #define TBUF_MAX_PKT_THRESH_MASK 0x1f | |
210 | #define TBUF_FULL_THRESH_SHIFT 8 | |
211 | #define TBUF_FULL_THRESH_MASK 0x1f | |
212 | ||
213 | /* UniMAC offset and defines */ | |
214 | #define SYS_PORT_UMAC_OFFSET 0x800 | |
215 | ||
216 | #define UMAC_CMD 0x008 | |
217 | #define CMD_TX_EN (1 << 0) | |
218 | #define CMD_RX_EN (1 << 1) | |
219 | #define CMD_SPEED_SHIFT 2 | |
220 | #define CMD_SPEED_10 0 | |
221 | #define CMD_SPEED_100 1 | |
222 | #define CMD_SPEED_1000 2 | |
223 | #define CMD_SPEED_2500 3 | |
224 | #define CMD_SPEED_MASK 3 | |
225 | #define CMD_PROMISC (1 << 4) | |
226 | #define CMD_PAD_EN (1 << 5) | |
227 | #define CMD_CRC_FWD (1 << 6) | |
228 | #define CMD_PAUSE_FWD (1 << 7) | |
229 | #define CMD_RX_PAUSE_IGNORE (1 << 8) | |
230 | #define CMD_TX_ADDR_INS (1 << 9) | |
231 | #define CMD_HD_EN (1 << 10) | |
232 | #define CMD_SW_RESET (1 << 13) | |
233 | #define CMD_LCL_LOOP_EN (1 << 15) | |
234 | #define CMD_AUTO_CONFIG (1 << 22) | |
235 | #define CMD_CNTL_FRM_EN (1 << 23) | |
236 | #define CMD_NO_LEN_CHK (1 << 24) | |
237 | #define CMD_RMT_LOOP_EN (1 << 25) | |
238 | #define CMD_PRBL_EN (1 << 27) | |
239 | #define CMD_TX_PAUSE_IGNORE (1 << 28) | |
240 | #define CMD_TX_RX_EN (1 << 29) | |
241 | #define CMD_RUNT_FILTER_DIS (1 << 30) | |
242 | ||
243 | #define UMAC_MAC0 0x00c | |
244 | #define UMAC_MAC1 0x010 | |
245 | #define UMAC_MAX_FRAME_LEN 0x014 | |
246 | ||
247 | #define UMAC_TX_FLUSH 0x334 | |
248 | ||
249 | #define UMAC_MIB_START 0x400 | |
250 | ||
251 | /* There is a 0xC gap between the end of RX and beginning of TX stats and then | |
252 | * between the end of TX stats and the beginning of the RX RUNT | |
253 | */ | |
254 | #define UMAC_MIB_STAT_OFFSET 0xc | |
255 | ||
256 | #define UMAC_MIB_CTRL 0x580 | |
257 | #define MIB_RX_CNT_RST (1 << 0) | |
258 | #define MIB_RUNT_CNT_RST (1 << 1) | |
259 | #define MIB_TX_CNT_RST (1 << 2) | |
83e82f4c | 260 | |
44a4524c | 261 | /* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ |
83e82f4c FF |
262 | #define UMAC_MPD_CTRL 0x620 |
263 | #define MPD_EN (1 << 0) | |
264 | #define MSEQ_LEN_SHIFT 16 | |
265 | #define MSEQ_LEN_MASK 0xff | |
266 | #define PSW_EN (1 << 27) | |
267 | ||
268 | #define UMAC_PSW_MS 0x624 | |
269 | #define UMAC_PSW_LS 0x628 | |
80105bef FF |
270 | #define UMAC_MDF_CTRL 0x650 |
271 | #define UMAC_MDF_ADDR 0x654 | |
272 | ||
44a4524c FF |
273 | /* Only valid on SYSTEMPORT Lite */ |
274 | #define SYS_PORT_GIB_OFFSET 0x1000 | |
275 | ||
276 | #define GIB_CONTROL 0x00 | |
277 | #define GIB_TX_EN (1 << 0) | |
278 | #define GIB_RX_EN (1 << 1) | |
279 | #define GIB_TX_FLUSH (1 << 2) | |
280 | #define GIB_RX_FLUSH (1 << 3) | |
281 | #define GIB_GTX_CLK_SEL_SHIFT 4 | |
282 | #define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT) | |
283 | #define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT) | |
284 | #define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT) | |
9e3bff92 FF |
285 | #define GIB_FCS_STRIP_SHIFT 6 |
286 | #define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT) | |
44a4524c FF |
287 | #define GIB_LCL_LOOP_EN (1 << 7) |
288 | #define GIB_LCL_LOOP_TXEN (1 << 8) | |
289 | #define GIB_RMT_LOOP_EN (1 << 9) | |
290 | #define GIB_RMT_LOOP_RXEN (1 << 10) | |
291 | #define GIB_RX_PAUSE_EN (1 << 11) | |
292 | #define GIB_PREAMBLE_LEN_SHIFT 12 | |
293 | #define GIB_PREAMBLE_LEN_MASK 0xf | |
294 | #define GIB_IPG_LEN_SHIFT 16 | |
295 | #define GIB_IPG_LEN_MASK 0x3f | |
296 | #define GIB_PAD_EXTENSION_SHIFT 22 | |
297 | #define GIB_PAD_EXTENSION_MASK 0x3f | |
298 | ||
299 | #define GIB_MAC1 0x08 | |
300 | #define GIB_MAC0 0x0c | |
301 | ||
80105bef FF |
302 | /* Receive DMA offset and defines */ |
303 | #define SYS_PORT_RDMA_OFFSET 0x2000 | |
304 | ||
305 | #define RDMA_CONTROL 0x1000 | |
306 | #define RDMA_EN (1 << 0) | |
307 | #define RDMA_RING_CFG (1 << 1) | |
308 | #define RDMA_DISC_EN (1 << 2) | |
309 | #define RDMA_BUF_DATA_OFFSET_SHIFT 4 | |
310 | #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff | |
311 | ||
312 | #define RDMA_STATUS 0x1004 | |
313 | #define RDMA_DISABLED (1 << 0) | |
314 | #define RDMA_DESC_RAM_INIT_BUSY (1 << 1) | |
315 | #define RDMA_BP_STATUS (1 << 2) | |
316 | ||
317 | #define RDMA_SCB_BURST_SIZE 0x1008 | |
318 | ||
319 | #define RDMA_RING_BUF_SIZE 0x100c | |
320 | #define RDMA_RING_SIZE_SHIFT 16 | |
321 | ||
322 | #define RDMA_WRITE_PTR_HI 0x1010 | |
323 | #define RDMA_WRITE_PTR_LO 0x1014 | |
324 | #define RDMA_PROD_INDEX 0x1018 | |
325 | #define RDMA_PROD_INDEX_MASK 0xffff | |
326 | ||
327 | #define RDMA_CONS_INDEX 0x101c | |
328 | #define RDMA_CONS_INDEX_MASK 0xffff | |
329 | ||
330 | #define RDMA_START_ADDR_HI 0x1020 | |
331 | #define RDMA_START_ADDR_LO 0x1024 | |
332 | #define RDMA_END_ADDR_HI 0x1028 | |
333 | #define RDMA_END_ADDR_LO 0x102c | |
334 | ||
335 | #define RDMA_MBDONE_INTR 0x1030 | |
d0634868 | 336 | #define RDMA_INTR_THRESH_MASK 0x1ff |
80105bef FF |
337 | #define RDMA_TIMEOUT_SHIFT 16 |
338 | #define RDMA_TIMEOUT_MASK 0xffff | |
339 | ||
340 | #define RDMA_XON_XOFF_THRESH 0x1034 | |
341 | #define RDMA_XON_XOFF_THRESH_MASK 0xffff | |
342 | #define RDMA_XOFF_THRESH_SHIFT 16 | |
343 | ||
344 | #define RDMA_READ_PTR_HI 0x1038 | |
345 | #define RDMA_READ_PTR_LO 0x103c | |
346 | ||
347 | #define RDMA_OVERRIDE 0x1040 | |
348 | #define RDMA_LE_MODE (1 << 0) | |
349 | #define RDMA_REG_MODE (1 << 1) | |
350 | ||
351 | #define RDMA_TEST 0x1044 | |
352 | #define RDMA_TP_OUT_SEL (1 << 0) | |
353 | #define RDMA_MEM_SEL (1 << 1) | |
354 | ||
355 | #define RDMA_DEBUG 0x1048 | |
356 | ||
357 | /* Transmit DMA offset and defines */ | |
358 | #define TDMA_NUM_RINGS 32 /* rings = queues */ | |
359 | #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ | |
360 | ||
361 | #define SYS_PORT_TDMA_OFFSET 0x4000 | |
362 | #define TDMA_WRITE_PORT_OFFSET 0x0000 | |
363 | #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ | |
364 | (i) * TDMA_PORT_SIZE) | |
365 | #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ | |
366 | sizeof(u32) + (i) * TDMA_PORT_SIZE) | |
367 | ||
368 | #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ | |
369 | (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) | |
370 | #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ | |
371 | (i) * TDMA_PORT_SIZE) | |
372 | #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ | |
373 | sizeof(u32) + (i) * TDMA_PORT_SIZE) | |
374 | ||
375 | #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ | |
376 | (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) | |
377 | #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ | |
378 | (i) * sizeof(u32)) | |
379 | ||
380 | #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ | |
381 | (TDMA_NUM_RINGS * sizeof(u32))) | |
382 | ||
383 | /* Register offsets and defines relatives to a specific ring number */ | |
384 | #define RING_HEAD_TAIL_PTR 0x00 | |
385 | #define RING_HEAD_MASK 0x7ff | |
386 | #define RING_TAIL_SHIFT 11 | |
387 | #define RING_TAIL_MASK 0x7ff | |
388 | #define RING_FLUSH (1 << 24) | |
389 | #define RING_EN (1 << 25) | |
390 | ||
391 | #define RING_COUNT 0x04 | |
392 | #define RING_COUNT_MASK 0x7ff | |
393 | #define RING_BUFF_DONE_SHIFT 11 | |
394 | #define RING_BUFF_DONE_MASK 0x7ff | |
395 | ||
396 | #define RING_MAX_HYST 0x08 | |
397 | #define RING_MAX_THRESH_MASK 0x7ff | |
398 | #define RING_HYST_THRESH_SHIFT 11 | |
399 | #define RING_HYST_THRESH_MASK 0x7ff | |
400 | ||
401 | #define RING_INTR_CONTROL 0x0c | |
402 | #define RING_INTR_THRESH_MASK 0x7ff | |
403 | #define RING_EMPTY_INTR_EN (1 << 15) | |
404 | #define RING_TIMEOUT_SHIFT 16 | |
405 | #define RING_TIMEOUT_MASK 0xffff | |
406 | ||
407 | #define RING_PROD_CONS_INDEX 0x10 | |
408 | #define RING_PROD_INDEX_MASK 0xffff | |
409 | #define RING_CONS_INDEX_SHIFT 16 | |
410 | #define RING_CONS_INDEX_MASK 0xffff | |
411 | ||
412 | #define RING_MAPPING 0x14 | |
d1565763 | 413 | #define RING_QID_MASK 0x7 |
80105bef FF |
414 | #define RING_PORT_ID_SHIFT 3 |
415 | #define RING_PORT_ID_MASK 0x7 | |
416 | #define RING_IGNORE_STATUS (1 << 6) | |
417 | #define RING_FAILOVER_EN (1 << 7) | |
418 | #define RING_CREDIT_SHIFT 8 | |
419 | #define RING_CREDIT_MASK 0xffff | |
420 | ||
421 | #define RING_PCP_DEI_VID 0x18 | |
422 | #define RING_VID_MASK 0x7ff | |
423 | #define RING_DEI (1 << 12) | |
424 | #define RING_PCP_SHIFT 13 | |
425 | #define RING_PCP_MASK 0x7 | |
426 | #define RING_PKT_SIZE_ADJ_SHIFT 16 | |
427 | #define RING_PKT_SIZE_ADJ_MASK 0xf | |
428 | ||
429 | #define TDMA_DESC_RING_SIZE 28 | |
430 | ||
431 | /* Defininition for a given TX ring base address */ | |
432 | #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ | |
433 | ((i) * TDMA_DESC_RING_SIZE)) | |
434 | ||
435 | /* Ring indexed register addreses */ | |
436 | #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ | |
437 | RING_HEAD_TAIL_PTR) | |
438 | #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ | |
439 | RING_COUNT) | |
440 | #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ | |
441 | RING_MAX_HYST) | |
442 | #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ | |
443 | RING_INTR_CONTROL) | |
444 | #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ | |
445 | (TDMA_DESC_RING_BASE(i) + \ | |
446 | RING_PROD_CONS_INDEX) | |
447 | #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ | |
448 | RING_MAPPING) | |
449 | #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ | |
450 | RING_PCP_DEI_VID) | |
451 | ||
452 | #define TDMA_CONTROL 0x600 | |
44a4524c FF |
453 | #define TDMA_EN 0 |
454 | #define TSB_EN 1 | |
455 | /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we | |
456 | * keep the SYSTEMPORT layout here and adjust with tdma_control_bit() | |
457 | */ | |
487234cc FF |
458 | #define TSB_SWAP0 2 |
459 | #define TSB_SWAP1 3 | |
44a4524c | 460 | #define ACB_ALGO 3 |
80105bef FF |
461 | #define BUF_DATA_OFFSET_SHIFT 4 |
462 | #define BUF_DATA_OFFSET_MASK 0x3ff | |
44a4524c FF |
463 | #define VLAN_EN 14 |
464 | #define SW_BRCM_TAG 15 | |
465 | #define WNC_KPT_SIZE_UPDATE 16 | |
466 | #define SYNC_PKT_SIZE 17 | |
80105bef FF |
467 | #define ACH_TXDONE_DELAY_SHIFT 18 |
468 | #define ACH_TXDONE_DELAY_MASK 0xff | |
469 | ||
470 | #define TDMA_STATUS 0x604 | |
471 | #define TDMA_DISABLED (1 << 0) | |
472 | #define TDMA_LL_RAM_INIT_BUSY (1 << 1) | |
473 | ||
474 | #define TDMA_SCB_BURST_SIZE 0x608 | |
475 | #define TDMA_OVER_MAX_THRESH_STATUS 0x60c | |
476 | #define TDMA_OVER_HYST_THRESH_STATUS 0x610 | |
477 | #define TDMA_TPID 0x614 | |
478 | ||
479 | #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 | |
480 | #define TDMA_FREE_HEAD_MASK 0x7ff | |
481 | #define TDMA_FREE_TAIL_SHIFT 11 | |
482 | #define TDMA_FREE_TAIL_MASK 0x7ff | |
483 | ||
484 | #define TDMA_FREE_LIST_COUNT 0x61c | |
485 | #define TDMA_FREE_LIST_COUNT_MASK 0x7ff | |
486 | ||
487 | #define TDMA_TIER2_ARB_CTRL 0x620 | |
488 | #define TDMA_ARB_MODE_RR 0 | |
489 | #define TDMA_ARB_MODE_WEIGHT_RR 0x1 | |
490 | #define TDMA_ARB_MODE_STRICT 0x2 | |
491 | #define TDMA_ARB_MODE_DEFICIT_RR 0x3 | |
492 | #define TDMA_CREDIT_SHIFT 4 | |
493 | #define TDMA_CREDIT_MASK 0xffff | |
494 | ||
495 | #define TDMA_TIER1_ARB_0_CTRL 0x624 | |
496 | #define TDMA_ARB_EN (1 << 0) | |
497 | ||
498 | #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 | |
499 | #define TDMA_TIER1_ARB_1_CTRL 0x62c | |
500 | #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 | |
501 | #define TDMA_TIER1_ARB_2_CTRL 0x634 | |
502 | #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 | |
503 | #define TDMA_TIER1_ARB_3_CTRL 0x63c | |
504 | #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 | |
505 | ||
506 | #define TDMA_SCB_ENDIAN_OVERRIDE 0x644 | |
507 | #define TDMA_LE_MODE (1 << 0) | |
508 | #define TDMA_REG_MODE (1 << 1) | |
509 | ||
510 | #define TDMA_TEST 0x648 | |
511 | #define TDMA_TP_OUT_SEL (1 << 0) | |
512 | #define TDMA_MEM_TM (1 << 1) | |
513 | ||
514 | #define TDMA_DEBUG 0x64c | |
515 | ||
80105bef | 516 | /* Number of Receive hardware descriptor words */ |
44a4524c FF |
517 | #define SP_NUM_HW_RX_DESC_WORDS 1024 |
518 | #define SP_LT_NUM_HW_RX_DESC_WORDS 256 | |
80105bef | 519 | |
44a4524c FF |
520 | /* Internal linked-list RAM size */ |
521 | #define SP_NUM_TX_DESC 1536 | |
522 | #define SP_LT_NUM_TX_DESC 256 | |
80105bef | 523 | |
7e6e185c | 524 | #define WORDS_PER_DESC 2 |
80105bef FF |
525 | |
526 | /* Rx/Tx common counter group.*/ | |
527 | struct bcm_sysport_pkt_counters { | |
528 | u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ | |
529 | u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ | |
530 | u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ | |
531 | u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ | |
532 | u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ | |
533 | u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ | |
534 | u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ | |
535 | u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ | |
536 | u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ | |
537 | u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ | |
538 | }; | |
539 | ||
540 | /* RSV, Receive Status Vector */ | |
541 | struct bcm_sysport_rx_counters { | |
542 | struct bcm_sysport_pkt_counters pkt_cnt; | |
543 | u32 pkt; /* RO (0x428) Received pkt count*/ | |
544 | u32 bytes; /* RO Received byte count */ | |
545 | u32 mca; /* RO # of Received multicast pkt */ | |
546 | u32 bca; /* RO # of Receive broadcast pkt */ | |
547 | u32 fcs; /* RO # of Received FCS error */ | |
548 | u32 cf; /* RO # of Received control frame pkt*/ | |
549 | u32 pf; /* RO # of Received pause frame pkt */ | |
550 | u32 uo; /* RO # of unknown op code pkt */ | |
551 | u32 aln; /* RO # of alignment error count */ | |
552 | u32 flr; /* RO # of frame length out of range count */ | |
553 | u32 cde; /* RO # of code error pkt */ | |
554 | u32 fcr; /* RO # of carrier sense error pkt */ | |
555 | u32 ovr; /* RO # of oversize pkt*/ | |
556 | u32 jbr; /* RO # of jabber count */ | |
557 | u32 mtue; /* RO # of MTU error pkt*/ | |
558 | u32 pok; /* RO # of Received good pkt */ | |
559 | u32 uc; /* RO # of unicast pkt */ | |
560 | u32 ppp; /* RO # of PPP pkt */ | |
561 | u32 rcrc; /* RO (0x470),# of CRC match pkt */ | |
562 | }; | |
563 | ||
564 | /* TSV, Transmit Status Vector */ | |
565 | struct bcm_sysport_tx_counters { | |
566 | struct bcm_sysport_pkt_counters pkt_cnt; | |
567 | u32 pkts; /* RO (0x4a8) Transmited pkt */ | |
568 | u32 mca; /* RO # of xmited multicast pkt */ | |
569 | u32 bca; /* RO # of xmited broadcast pkt */ | |
570 | u32 pf; /* RO # of xmited pause frame count */ | |
571 | u32 cf; /* RO # of xmited control frame count */ | |
572 | u32 fcs; /* RO # of xmited FCS error count */ | |
573 | u32 ovr; /* RO # of xmited oversize pkt */ | |
574 | u32 drf; /* RO # of xmited deferral pkt */ | |
575 | u32 edf; /* RO # of xmited Excessive deferral pkt*/ | |
576 | u32 scl; /* RO # of xmited single collision pkt */ | |
577 | u32 mcl; /* RO # of xmited multiple collision pkt*/ | |
578 | u32 lcl; /* RO # of xmited late collision pkt */ | |
579 | u32 ecl; /* RO # of xmited excessive collision pkt*/ | |
580 | u32 frg; /* RO # of xmited fragments pkt*/ | |
581 | u32 ncl; /* RO # of xmited total collision count */ | |
582 | u32 jbr; /* RO # of xmited jabber count*/ | |
583 | u32 bytes; /* RO # of xmited byte count */ | |
584 | u32 pok; /* RO # of xmited good pkt */ | |
165996bd | 585 | u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ |
80105bef FF |
586 | }; |
587 | ||
588 | struct bcm_sysport_mib { | |
589 | struct bcm_sysport_rx_counters rx; | |
590 | struct bcm_sysport_tx_counters tx; | |
591 | u32 rx_runt_cnt; | |
592 | u32 rx_runt_fcs; | |
593 | u32 rx_runt_fcs_align; | |
594 | u32 rx_runt_bytes; | |
595 | u32 rxchk_bad_csum; | |
596 | u32 rxchk_other_pkt_disc; | |
597 | u32 rbuf_ovflow_cnt; | |
598 | u32 rbuf_err_cnt; | |
60b4ea17 FF |
599 | u32 alloc_rx_buff_failed; |
600 | u32 rx_dma_failed; | |
601 | u32 tx_dma_failed; | |
a5d78ce7 FF |
602 | u32 tx_realloc_tsb; |
603 | u32 tx_realloc_tsb_failed; | |
80105bef FF |
604 | }; |
605 | ||
606 | /* HW maintains a large list of counters */ | |
607 | enum bcm_sysport_stat_type { | |
608 | BCM_SYSPORT_STAT_NETDEV = -1, | |
10377ba7 | 609 | BCM_SYSPORT_STAT_NETDEV64, |
80105bef FF |
610 | BCM_SYSPORT_STAT_MIB_RX, |
611 | BCM_SYSPORT_STAT_MIB_TX, | |
612 | BCM_SYSPORT_STAT_RUNT, | |
613 | BCM_SYSPORT_STAT_RXCHK, | |
614 | BCM_SYSPORT_STAT_RBUF, | |
55ff4ea9 | 615 | BCM_SYSPORT_STAT_SOFT, |
80105bef FF |
616 | }; |
617 | ||
618 | /* Macros to help define ethtool statistics */ | |
619 | #define STAT_NETDEV(m) { \ | |
620 | .stat_string = __stringify(m), \ | |
621 | .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ | |
622 | .stat_offset = offsetof(struct net_device_stats, m), \ | |
623 | .type = BCM_SYSPORT_STAT_NETDEV, \ | |
624 | } | |
625 | ||
10377ba7 | 626 | #define STAT_NETDEV64(m) { \ |
627 | .stat_string = __stringify(m), \ | |
628 | .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \ | |
629 | .stat_offset = offsetof(struct bcm_sysport_stats64, m), \ | |
630 | .type = BCM_SYSPORT_STAT_NETDEV64, \ | |
631 | } | |
632 | ||
80105bef FF |
633 | #define STAT_MIB(str, m, _type) { \ |
634 | .stat_string = str, \ | |
635 | .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ | |
636 | .stat_offset = offsetof(struct bcm_sysport_priv, m), \ | |
637 | .type = _type, \ | |
638 | } | |
639 | ||
640 | #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) | |
641 | #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) | |
642 | #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) | |
55ff4ea9 | 643 | #define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) |
80105bef FF |
644 | |
645 | #define STAT_RXCHK(str, m, ofs) { \ | |
646 | .stat_string = str, \ | |
647 | .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ | |
648 | .stat_offset = offsetof(struct bcm_sysport_priv, m), \ | |
649 | .type = BCM_SYSPORT_STAT_RXCHK, \ | |
650 | .reg_offset = ofs, \ | |
651 | } | |
652 | ||
653 | #define STAT_RBUF(str, m, ofs) { \ | |
654 | .stat_string = str, \ | |
655 | .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ | |
656 | .stat_offset = offsetof(struct bcm_sysport_priv, m), \ | |
657 | .type = BCM_SYSPORT_STAT_RBUF, \ | |
658 | .reg_offset = ofs, \ | |
659 | } | |
660 | ||
30defeb2 FF |
661 | /* TX bytes and packets */ |
662 | #define NUM_SYSPORT_TXQ_STAT 2 | |
663 | ||
80105bef FF |
664 | struct bcm_sysport_stats { |
665 | char stat_string[ETH_GSTRING_LEN]; | |
666 | int stat_sizeof; | |
667 | int stat_offset; | |
668 | enum bcm_sysport_stat_type type; | |
669 | /* reg offset from UMAC base for misc counters */ | |
670 | u16 reg_offset; | |
671 | }; | |
672 | ||
10377ba7 | 673 | struct bcm_sysport_stats64 { |
674 | /* 64bit stats on 32bit/64bit Machine */ | |
675 | u64 rx_packets; | |
676 | u64 rx_bytes; | |
677 | u64 tx_packets; | |
678 | u64 tx_bytes; | |
679 | }; | |
680 | ||
80105bef FF |
681 | /* Software house keeping helper structure */ |
682 | struct bcm_sysport_cb { | |
683 | struct sk_buff *skb; /* SKB for RX packets */ | |
684 | void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ | |
685 | ||
686 | DEFINE_DMA_UNMAP_ADDR(dma_addr); | |
687 | DEFINE_DMA_UNMAP_LEN(dma_len); | |
688 | }; | |
689 | ||
44a4524c FF |
690 | enum bcm_sysport_type { |
691 | SYSTEMPORT = 0, | |
692 | SYSTEMPORT_LITE, | |
693 | }; | |
694 | ||
695 | struct bcm_sysport_hw_params { | |
696 | bool is_lite; | |
697 | unsigned int num_rx_desc_words; | |
698 | }; | |
699 | ||
b6e0e875 FF |
700 | struct bcm_sysport_net_dim { |
701 | u16 use_dim; | |
702 | u16 event_ctr; | |
703 | unsigned long packets; | |
704 | unsigned long bytes; | |
8960b389 | 705 | struct dim dim; |
b6e0e875 FF |
706 | }; |
707 | ||
80105bef FF |
708 | /* Software view of the TX ring */ |
709 | struct bcm_sysport_tx_ring { | |
710 | spinlock_t lock; /* Ring lock for tx reclaim/xmit */ | |
711 | struct napi_struct napi; /* NAPI per tx queue */ | |
80105bef FF |
712 | unsigned int index; /* Ring index */ |
713 | unsigned int size; /* Ring current size */ | |
714 | unsigned int alloc_size; /* Ring one-time allocated size */ | |
715 | unsigned int desc_count; /* Number of descriptors */ | |
716 | unsigned int curr_desc; /* Current descriptor */ | |
717 | unsigned int c_index; /* Last consumer index */ | |
484d802d | 718 | unsigned int clean_index; /* Current clean index */ |
80105bef | 719 | struct bcm_sysport_cb *cbs; /* Transmit control blocks */ |
80105bef | 720 | struct bcm_sysport_priv *priv; /* private context backpointer */ |
30defeb2 FF |
721 | unsigned long packets; /* packets statistics */ |
722 | unsigned long bytes; /* bytes statistics */ | |
d1565763 FF |
723 | unsigned int switch_queue; /* switch port queue number */ |
724 | unsigned int switch_port; /* switch port queue number */ | |
3ded76a8 | 725 | bool inspect; /* inspect switch port and queue */ |
80105bef FF |
726 | }; |
727 | ||
728 | /* Driver private structure */ | |
729 | struct bcm_sysport_priv { | |
730 | void __iomem *base; | |
731 | u32 irq0_stat; | |
732 | u32 irq0_mask; | |
733 | u32 irq1_stat; | |
734 | u32 irq1_mask; | |
44a4524c FF |
735 | bool is_lite; |
736 | unsigned int num_rx_desc_words; | |
80105bef FF |
737 | struct napi_struct napi ____cacheline_aligned; |
738 | struct net_device *netdev; | |
739 | struct platform_device *pdev; | |
740 | int irq0; | |
741 | int irq1; | |
83e82f4c | 742 | int wol_irq; |
80105bef FF |
743 | |
744 | /* Transmit rings */ | |
7b78be48 | 745 | struct bcm_sysport_tx_ring *tx_rings; |
80105bef FF |
746 | |
747 | /* Receive queue */ | |
748 | void __iomem *rx_bds; | |
80105bef FF |
749 | struct bcm_sysport_cb *rx_cbs; |
750 | unsigned int num_rx_bds; | |
751 | unsigned int rx_read_ptr; | |
752 | unsigned int rx_c_index; | |
753 | ||
b6e0e875 | 754 | struct bcm_sysport_net_dim dim; |
a8cdfbdf FF |
755 | u32 rx_max_coalesced_frames; |
756 | u32 rx_coalesce_usecs; | |
b6e0e875 | 757 | |
80105bef | 758 | /* PHY device */ |
186534a3 | 759 | struct device_node *phy_dn; |
80105bef FF |
760 | phy_interface_t phy_interface; |
761 | int old_pause; | |
762 | int old_link; | |
763 | int old_duplex; | |
764 | ||
765 | /* Misc fields */ | |
9d34c1cb | 766 | unsigned int rx_chk_en:1; |
80105bef FF |
767 | unsigned int tsb_en:1; |
768 | unsigned int crc_fwd:1; | |
769 | u16 rev; | |
83e82f4c | 770 | u32 wolopts; |
8dfb8d2c | 771 | u8 sopass[SOPASS_MAX]; |
83e82f4c | 772 | unsigned int wol_irq_disabled:1; |
80105bef FF |
773 | |
774 | /* MIB related fields */ | |
775 | struct bcm_sysport_mib mib; | |
776 | ||
777 | /* Ethtool */ | |
778 | u32 msg_enable; | |
bb9051a2 | 779 | DECLARE_BITMAP(filters, RXCHK_BRCM_TAG_MAX); |
80f8dea8 | 780 | u32 filters_loc[RXCHK_BRCM_TAG_MAX]; |
10377ba7 | 781 | |
782 | struct bcm_sysport_stats64 stats64; | |
783 | ||
784 | /* For atomic update generic 64bit value on 32bit Machine */ | |
785 | struct u64_stats_sync syncp; | |
d1565763 FF |
786 | |
787 | /* map information between switch port queues and local queues */ | |
788 | struct notifier_block dsa_notifier; | |
789 | unsigned int per_port_num_tx_queues; | |
d1565763 FF |
790 | struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8]; |
791 | ||
80105bef FF |
792 | }; |
793 | #endif /* __BCM_SYSPORT_H */ |