[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bgmac-bcma-mdio.c

/*
 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
 *
 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#define pr_fmt(fmt)		KBUILD_MODNAME ": " fmt

#include <linux/bcma/bcma.h>
#include <linux/brcmphy.h>
#include "bgmac.h"

static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,
				 u32 value, int timeout)
{
	u32 val;
	int i;

	for (i = 0; i < timeout / 10; i++) {
		val = bcma_read32(core, reg);
		if ((val & mask) == value)
			return true;
		udelay(10);
	}
	dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg);
	return false;
}

/**************************************************
 * PHY ops
 **************************************************/

static u16 bcma_mdio_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
{
	struct bcma_device *core;
	u16 phy_access_addr;
	u16 phy_ctl_addr;
	u32 tmp;

	BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
	BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
	BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
	BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
	BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
	BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
	BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
	BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
	BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
	BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
	BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);

	if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
		core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
		phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
		phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
	} else {
		core = bgmac->bcma.core;
		phy_access_addr = BGMAC_PHY_ACCESS;
		phy_ctl_addr = BGMAC_PHY_CNTL;
	}

	tmp = bcma_read32(core, phy_ctl_addr);
	tmp &= ~BGMAC_PC_EPA_MASK;
	tmp |= phyaddr;
	bcma_write32(core, phy_ctl_addr, tmp);

	tmp = BGMAC_PA_START;
	tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
	tmp |= reg << BGMAC_PA_REG_SHIFT;
	bcma_write32(core, phy_access_addr, tmp);

	if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
				  1000)) {
		dev_err(&core->dev, "Reading PHY %d register 0x%X failed\n",
			phyaddr, reg);
		return 0xffff;
	}

	return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
}

/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
static int bcma_mdio_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg,
			       u16 value)
{
	struct bcma_device *core;
	u16 phy_access_addr;
	u16 phy_ctl_addr;
	u32 tmp;

	if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
		core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
		phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
		phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
	} else {
		core = bgmac->bcma.core;
		phy_access_addr = BGMAC_PHY_ACCESS;
		phy_ctl_addr = BGMAC_PHY_CNTL;
	}

	tmp = bcma_read32(core, phy_ctl_addr);
	tmp &= ~BGMAC_PC_EPA_MASK;
	tmp |= phyaddr;
	bcma_write32(core, phy_ctl_addr, tmp);

	bcma_write32(bgmac->bcma.core, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
	if (bcma_read32(bgmac->bcma.core, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
		dev_warn(&core->dev, "Error setting MDIO int\n");

	tmp = BGMAC_PA_START;
	tmp |= BGMAC_PA_WRITE;
	tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
	tmp |= reg << BGMAC_PA_REG_SHIFT;
	tmp |= value;
	bcma_write32(core, phy_access_addr, tmp);

	if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
				  1000)) {
		dev_err(&core->dev, "Writing to PHY %d register 0x%X failed\n",
			phyaddr, reg);
		return -ETIMEDOUT;
	}

	return 0;
}

/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
static void bcma_mdio_phy_init(struct bgmac *bgmac)
{
	struct bcma_chipinfo *ci = &bgmac->bcma.core->bus->chipinfo;
	u8 i;

	/* For some legacy hardware we do chipset-based PHY initialization here
	 * without even detecting PHY ID. It's hacky and should be cleaned as
	 * soon as someone can test it.
	 */
	if (ci->id == BCMA_CHIP_ID_BCM5356) {
		for (i = 0; i < 5; i++) {
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x008b);
			bcma_mdio_phy_write(bgmac, i, 0x15, 0x0100);
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
			bcma_mdio_phy_write(bgmac, i, 0x12, 0x2aaa);
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
		}
		return;
	}
	if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
	    (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
	    (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
		struct bcma_drv_cc *cc = &bgmac->bcma.core->bus->drv_cc;

		bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
		bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
		for (i = 0; i < 5; i++) {
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
			bcma_mdio_phy_write(bgmac, i, 0x16, 0x5284);
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
			bcma_mdio_phy_write(bgmac, i, 0x17, 0x0010);
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
			bcma_mdio_phy_write(bgmac, i, 0x16, 0x5296);
			bcma_mdio_phy_write(bgmac, i, 0x17, 0x1073);
			bcma_mdio_phy_write(bgmac, i, 0x17, 0x9073);
			bcma_mdio_phy_write(bgmac, i, 0x16, 0x52b6);
			bcma_mdio_phy_write(bgmac, i, 0x17, 0x9273);
			bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
		}
		return;
	}

	/* For all other hw do initialization using PHY subsystem. */
	if (bgmac->net_dev && bgmac->net_dev->phydev)
		phy_init_hw(bgmac->net_dev->phydev);
}

/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
static int bcma_mdio_phy_reset(struct mii_bus *bus)
{
	struct bgmac *bgmac = bus->priv;
	u8 phyaddr = bgmac->phyaddr;

	if (phyaddr == BGMAC_PHY_NOREGS)
		return 0;

	bcma_mdio_phy_write(bgmac, phyaddr, MII_BMCR, BMCR_RESET);
	udelay(100);
	if (bcma_mdio_phy_read(bgmac, phyaddr, MII_BMCR) & BMCR_RESET)
		dev_err(bgmac->dev, "PHY reset failed\n");
	bcma_mdio_phy_init(bgmac);

	return 0;
}

/**************************************************
 * MII
 **************************************************/

static int bcma_mdio_mii_read(struct mii_bus *bus, int mii_id, int regnum)
{
	return bcma_mdio_phy_read(bus->priv, mii_id, regnum);
}

static int bcma_mdio_mii_write(struct mii_bus *bus, int mii_id, int regnum,
			       u16 value)
{
	return bcma_mdio_phy_write(bus->priv, mii_id, regnum, value);
}

struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac)
{
	struct bcma_device *core = bgmac->bcma.core;
	struct mii_bus *mii_bus;
	int err;

	mii_bus = mdiobus_alloc();
	if (!mii_bus) {
		err = -ENOMEM;
		goto err;
	}

	mii_bus->name = "bcma_mdio mii bus";
	sprintf(mii_bus->id, "%s-%d-%d", "bcma_mdio", core->bus->num,
		core->core_unit);
	mii_bus->priv = bgmac;
	mii_bus->read = bcma_mdio_mii_read;
	mii_bus->write = bcma_mdio_mii_write;
	mii_bus->reset = bcma_mdio_phy_reset;
	mii_bus->parent = &core->dev;
	mii_bus->phy_mask = ~(1 << bgmac->phyaddr);

	err = mdiobus_register(mii_bus);
	if (err) {
		dev_err(&core->dev, "Registration of mii bus failed\n");
		goto err_free_bus;
	}

	return mii_bus;

err_free_bus:
	mdiobus_free(mii_bus);
err:
	return ERR_PTR(err);
}
EXPORT_SYMBOL_GPL(bcma_mdio_mii_register);

void bcma_mdio_mii_unregister(struct mii_bus *mii_bus)
{
	if (!mii_bus)
		return;

	mdiobus_unregister(mii_bus);
	mdiobus_free(mii_bus);
}
EXPORT_SYMBOL_GPL(bcma_mdio_mii_unregister);

MODULE_AUTHOR("Rafał Miłecki");
MODULE_LICENSE("GPL");
Commit	Line	Data
55954f3b JM	1	/*
	2	* Driver for (BCM4706)? GBit MAC core on BCMA bus.
	3	*
	4	* Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
	5	*
	6	* Licensed under the GNU/GPL. See COPYING for details.
	7	*/
	8
	9	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	10
	11	#include <linux/bcma/bcma.h>
	12	#include <linux/brcmphy.h>
	13	#include "bgmac.h"
	14
55954f3b JM	15	static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,
	16	u32 value, int timeout)
	17	{
	18	u32 val;
	19	int i;
	20
	21	for (i = 0; i < timeout / 10; i++) {
	22	val = bcma_read32(core, reg);
	23	if ((val & mask) == value)
	24	return true;
	25	udelay(10);
	26	}
	27	dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg);
	28	return false;
	29	}
	30
	31	/**************************************************
	32	* PHY ops
	33	**************************************************/
	34
aa8863e5	35	static u16 bcma_mdio_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
55954f3b JM	36	{
	37	struct bcma_device *core;
	38	u16 phy_access_addr;
	39	u16 phy_ctl_addr;
	40	u32 tmp;
	41
	42	BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
	43	BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
	44	BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
	45	BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
	46	BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
	47	BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
	48	BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
	49	BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
	50	BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
	51	BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
	52	BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
	53
aa8863e5 RM	54	if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
aa8863e5 RM	55	core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
55954f3b JM	56	phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
	57	phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
	58	} else {
aa8863e5	59	core = bgmac->bcma.core;
55954f3b JM	60	phy_access_addr = BGMAC_PHY_ACCESS;
	61	phy_ctl_addr = BGMAC_PHY_CNTL;
	62	}
	63
	64	tmp = bcma_read32(core, phy_ctl_addr);
	65	tmp &= ~BGMAC_PC_EPA_MASK;
	66	tmp \|= phyaddr;
	67	bcma_write32(core, phy_ctl_addr, tmp);
	68
	69	tmp = BGMAC_PA_START;
	70	tmp \|= phyaddr << BGMAC_PA_ADDR_SHIFT;
	71	tmp \|= reg << BGMAC_PA_REG_SHIFT;
	72	bcma_write32(core, phy_access_addr, tmp);
	73
	74	if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
	75	1000)) {
	76	dev_err(&core->dev, "Reading PHY %d register 0x%X failed\n",
	77	phyaddr, reg);
	78	return 0xffff;
	79	}
	80
	81	return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
	82	}
	83
	84	/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
aa8863e5	85	static int bcma_mdio_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg,
55954f3b JM	86	u16 value)
	87	{
	88	struct bcma_device *core;
	89	u16 phy_access_addr;
	90	u16 phy_ctl_addr;
	91	u32 tmp;
	92
aa8863e5 RM	93	if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
aa8863e5 RM	94	core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
55954f3b JM	95	phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
	96	phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
	97	} else {
aa8863e5	98	core = bgmac->bcma.core;
55954f3b JM	99	phy_access_addr = BGMAC_PHY_ACCESS;
	100	phy_ctl_addr = BGMAC_PHY_CNTL;
	101	}
	102
	103	tmp = bcma_read32(core, phy_ctl_addr);
	104	tmp &= ~BGMAC_PC_EPA_MASK;
	105	tmp \|= phyaddr;
	106	bcma_write32(core, phy_ctl_addr, tmp);
	107
aa8863e5 RM	108	bcma_write32(bgmac->bcma.core, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
aa8863e5 RM	109	if (bcma_read32(bgmac->bcma.core, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
55954f3b JM	110	dev_warn(&core->dev, "Error setting MDIO int\n");
	111
	112	tmp = BGMAC_PA_START;
	113	tmp \|= BGMAC_PA_WRITE;
	114	tmp \|= phyaddr << BGMAC_PA_ADDR_SHIFT;
	115	tmp \|= reg << BGMAC_PA_REG_SHIFT;
	116	tmp \|= value;
	117	bcma_write32(core, phy_access_addr, tmp);
	118
	119	if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
	120	1000)) {
	121	dev_err(&core->dev, "Writing to PHY %d register 0x%X failed\n",
	122	phyaddr, reg);
	123	return -ETIMEDOUT;
	124	}
	125
	126	return 0;
	127	}
	128
	129	/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
aa8863e5	130	static void bcma_mdio_phy_init(struct bgmac *bgmac)
55954f3b	131	{
aa8863e5	132	struct bcma_chipinfo *ci = &bgmac->bcma.core->bus->chipinfo;
55954f3b JM	133	u8 i;
55954f3b JM	134
8e6f31ba RM	135	/* For some legacy hardware we do chipset-based PHY initialization here
	136	* without even detecting PHY ID. It's hacky and should be cleaned as
	137	* soon as someone can test it.
	138	*/
55954f3b JM	139	if (ci->id == BCMA_CHIP_ID_BCM5356) {
55954f3b JM	140	for (i = 0; i < 5; i++) {
aa8863e5 RM	141	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x008b);
	142	bcma_mdio_phy_write(bgmac, i, 0x15, 0x0100);
	143	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
	144	bcma_mdio_phy_write(bgmac, i, 0x12, 0x2aaa);
	145	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
55954f3b	146	}
8e6f31ba	147	return;
55954f3b JM	148	}
	149	if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) \|\|
	150	(ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) \|\|
	151	(ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
aa8863e5	152	struct bcma_drv_cc *cc = &bgmac->bcma.core->bus->drv_cc;
55954f3b JM	153
	154	bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
	155	bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
	156	for (i = 0; i < 5; i++) {
aa8863e5 RM	157	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
	158	bcma_mdio_phy_write(bgmac, i, 0x16, 0x5284);
	159	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
	160	bcma_mdio_phy_write(bgmac, i, 0x17, 0x0010);
	161	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
	162	bcma_mdio_phy_write(bgmac, i, 0x16, 0x5296);
	163	bcma_mdio_phy_write(bgmac, i, 0x17, 0x1073);
	164	bcma_mdio_phy_write(bgmac, i, 0x17, 0x9073);
	165	bcma_mdio_phy_write(bgmac, i, 0x16, 0x52b6);
	166	bcma_mdio_phy_write(bgmac, i, 0x17, 0x9273);
	167	bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
55954f3b	168	}
8e6f31ba	169	return;
55954f3b	170	}
8e6f31ba RM	171
	172	/* For all other hw do initialization using PHY subsystem. */
	173	if (bgmac->net_dev && bgmac->net_dev->phydev)
	174	phy_init_hw(bgmac->net_dev->phydev);
55954f3b JM	175	}
	176
	177	/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
	178	static int bcma_mdio_phy_reset(struct mii_bus *bus)
	179	{
aa8863e5 RM	180	struct bgmac *bgmac = bus->priv;
aa8863e5 RM	181	u8 phyaddr = bgmac->phyaddr;
55954f3b	182
aa8863e5	183	if (phyaddr == BGMAC_PHY_NOREGS)
55954f3b JM	184	return 0;
55954f3b JM	185
aa8863e5	186	bcma_mdio_phy_write(bgmac, phyaddr, MII_BMCR, BMCR_RESET);
55954f3b	187	udelay(100);
aa8863e5 RM	188	if (bcma_mdio_phy_read(bgmac, phyaddr, MII_BMCR) & BMCR_RESET)
	189	dev_err(bgmac->dev, "PHY reset failed\n");
	190	bcma_mdio_phy_init(bgmac);
55954f3b JM	191
	192	return 0;
	193	}
	194
	195	/**************************************************
	196	* MII
	197	**************************************************/
	198
	199	static int bcma_mdio_mii_read(struct mii_bus *bus, int mii_id, int regnum)
	200	{
	201	return bcma_mdio_phy_read(bus->priv, mii_id, regnum);
	202	}
	203
	204	static int bcma_mdio_mii_write(struct mii_bus *bus, int mii_id, int regnum,
	205	u16 value)
	206	{
	207	return bcma_mdio_phy_write(bus->priv, mii_id, regnum, value);
	208	}
	209
aa8863e5	210	struct mii_bus bcma_mdio_mii_register(struct bgmac bgmac)
55954f3b	211	{
aa8863e5	212	struct bcma_device *core = bgmac->bcma.core;
55954f3b JM	213	struct mii_bus *mii_bus;
	214	int err;
	215
55954f3b JM	216	mii_bus = mdiobus_alloc();
	217	if (!mii_bus) {
	218	err = -ENOMEM;
	219	goto err;
	220	}
	221
	222	mii_bus->name = "bcma_mdio mii bus";
	223	sprintf(mii_bus->id, "%s-%d-%d", "bcma_mdio", core->bus->num,
	224	core->core_unit);
aa8863e5	225	mii_bus->priv = bgmac;
55954f3b JM	226	mii_bus->read = bcma_mdio_mii_read;
	227	mii_bus->write = bcma_mdio_mii_write;
	228	mii_bus->reset = bcma_mdio_phy_reset;
	229	mii_bus->parent = &core->dev;
aa8863e5	230	mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
55954f3b JM	231
	232	err = mdiobus_register(mii_bus);
	233	if (err) {
	234	dev_err(&core->dev, "Registration of mii bus failed\n");
	235	goto err_free_bus;
	236	}
	237
	238	return mii_bus;
	239
	240	err_free_bus:
	241	mdiobus_free(mii_bus);
	242	err:
55954f3b JM	243	return ERR_PTR(err);
55954f3b JM	244	}
f6a95a24	245	EXPORT_SYMBOL_GPL(bcma_mdio_mii_register);
55954f3b JM	246
	247	void bcma_mdio_mii_unregister(struct mii_bus *mii_bus)
	248	{
55954f3b JM	249	if (!mii_bus)
	250	return;
	251
55954f3b JM	252	mdiobus_unregister(mii_bus);
55954f3b JM	253	mdiobus_free(mii_bus);
55954f3b	254	}
f6a95a24	255	EXPORT_SYMBOL_GPL(bcma_mdio_mii_unregister);
55954f3b JM	256
	257	MODULE_AUTHOR("Rafał Miłecki");
	258	MODULE_LICENSE("GPL");